[llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
Changes in directory llvm/lib/VMCore:
ConstantFold.cpp updated: 1.148 -> 1.149
---
Log message:
fold constantexprs more aggressively, fixing PR1265: http://llvm.org/PR1265
---
Diffs of the changes: (+17 -2)
ConstantFold.cpp | 19 +--
1 files changed, 17 insertions(+), 2 deletions(-)
Index: llvm/lib/VMCore/ConstantFold.cpp
diff -u llvm/lib/VMCore/ConstantFold.cpp:1.148
llvm/lib/VMCore/ConstantFold.cpp:1.149
--- llvm/lib/VMCore/ConstantFold.cpp:1.148 Fri Mar 23 00:33:23 2007
+++ llvm/lib/VMCore/ConstantFold.cppSun Mar 25 00:47:04 2007
@@ -519,10 +519,20 @@
return Constant::getNullValue(CI->getType()); // X % 1 == 0
break;
case Instruction::And:
-if (const ConstantInt *CI = dyn_cast(C2))
+if (const ConstantInt *CI = dyn_cast(C2)) {
+ if (CI->isZero()) return const_cast(C2); // X & 0 == 0
if (CI->isAllOnesValue())
return const_cast(C1); // X & -1 ==
X
-if (C2->isNullValue()) return const_cast(C2); // X & 0 == 0
+
+ // (zext i32 to i64) & 4294967295 -> (zext i32 to i64)
+ if (CE1->getOpcode() == Instruction::ZExt) {
+APInt PossiblySetBits
+ = cast(CE1->getOperand(0)->getType())->getMask();
+PossiblySetBits.zext(C1->getType()->getPrimitiveSizeInBits());
+if ((PossiblySetBits & CI->getValue()) == PossiblySetBits)
+ return const_cast(C1);
+ }
+}
if (CE1->isCast() && isa(CE1->getOperand(0))) {
GlobalValue *CPR = cast(CE1->getOperand(0));
@@ -543,6 +553,11 @@
case Instruction::Xor:
if (C2->isNullValue()) return const_cast(C1); // X ^ 0 == X
break;
+ case Instruction::AShr:
+if (CE1->getOpcode() == Instruction::ZExt) // Top bits known zero.
+ return ConstantExpr::getLShr(const_cast(C1),
+ const_cast(C2));
+break;
}
}
} else if (isa(C2)) {
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.687 -> 1.688
---
Log message:
Refactor several ConstantExpr::getXXX calls with ConstantInt arguments
using the facilities of APInt. While this duplicates a tiny fraction of
the constant folding code, it also makes the code easier to read and
avoids large ConstantExpr overhead for simple, known computations.
---
Diffs of the changes: (+40 -27)
InstructionCombining.cpp | 67 ---
1 files changed, 40 insertions(+), 27 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.687
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.688
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.687 Sun Mar 25
00:01:29 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sun Mar 25 00:33:51 2007
@@ -540,8 +540,9 @@
if (I->getOpcode() == Instruction::Shl)
if ((CST = dyn_cast(I->getOperand(1 {
// The multiplier is really 1 << CST.
- Constant *One = ConstantInt::get(V->getType(), 1);
- CST = cast(ConstantExpr::getShl(One, CST));
+ APInt Multiplier(V->getType()->getPrimitiveSizeInBits(), 0);
+ Multiplier.set(CST->getZExtValue()); // set bit is == 1 << CST
+ CST = ConstantInt::get(Multiplier);
return I->getOperand(0);
}
}
@@ -558,14 +559,31 @@
return false;
}
-// AddOne, SubOne - Add or subtract a constant one from an integer constant...
+/// AddOne - Add one to a ConstantInt
static ConstantInt *AddOne(ConstantInt *C) {
- return cast(ConstantExpr::getAdd(C,
- ConstantInt::get(C->getType(), 1)));
+ APInt One(C->getType()->getPrimitiveSizeInBits(),1);
+ return ConstantInt::get(C->getValue() + One);
}
+/// SubOne - Subtract one from a ConstantInt
static ConstantInt *SubOne(ConstantInt *C) {
- return cast(ConstantExpr::getSub(C,
- ConstantInt::get(C->getType(), 1)));
+ APInt One(C->getType()->getPrimitiveSizeInBits(),1);
+ return ConstantInt::get(C->getValue() - One);
+}
+/// Add - Add two ConstantInts together
+static ConstantInt *Add(ConstantInt *C1, ConstantInt *C2) {
+ return ConstantInt::get(C1->getValue() + C2->getValue());
+}
+/// And - Bitwise AND two ConstantInts together
+static ConstantInt *And(ConstantInt *C1, ConstantInt *C2) {
+ return ConstantInt::get(C1->getValue() & C2->getValue());
+}
+/// Subtract - Subtract one ConstantInt from another
+static ConstantInt *Subtract(ConstantInt *C1, ConstantInt *C2) {
+ return ConstantInt::get(C1->getValue() - C2->getValue());
+}
+/// Multiply - Multiply two ConstantInts together
+static ConstantInt *Multiply(ConstantInt *C1, ConstantInt *C2) {
+ return ConstantInt::get(C1->getValue() * C2->getValue());
}
/// ComputeMaskedBits - Determine which of the bits specified in Mask are
@@ -1966,7 +1984,7 @@
// X*C1 + X*C2 --> X * (C1+C2)
ConstantInt *C1;
if (X == dyn_castFoldableMul(RHS, C1))
- return BinaryOperator::createMul(X, ConstantExpr::getAdd(C1, C2));
+ return BinaryOperator::createMul(X, Add(C1, C2));
}
// X + X*C --> X * (C+1)
@@ -1986,14 +2004,12 @@
if (ConstantInt *CRHS = dyn_cast(RHS)) {
Value *X = 0;
-if (match(LHS, m_Not(m_Value(X { // ~X + C --> (C-1) - X
- Constant *C= ConstantExpr::getSub(CRHS, ConstantInt::get(I.getType(),
1));
- return BinaryOperator::createSub(C, X);
-}
+if (match(LHS, m_Not(m_Value(X// ~X + C --> (C-1) - X
+ return BinaryOperator::createSub(SubOne(CRHS), X);
// (X & FF00) + xx00 -> (X+xx00) & FF00
if (LHS->hasOneUse() && match(LHS, m_And(m_Value(X), m_ConstantInt(C2 {
- Constant *Anded = ConstantExpr::getAnd(CRHS, C2);
+ Constant *Anded = And(CRHS, C2);
if (Anded == CRHS) {
// See if all bits from the first bit set in the Add RHS up are
included
// in the mask. First, get the rightmost bit.
@@ -2075,8 +2091,8 @@
// C - ~X == X + (1+C)
Value *X = 0;
if (match(Op1, m_Not(m_Value(X
- return BinaryOperator::createAdd(X,
-ConstantExpr::getAdd(C, ConstantInt::get(I.getType(), 1)));
+ return BinaryOperator::createAdd(X, AddOne(C));
+
// -(X >>u 31) -> (X >>s 31)
// -(X >>s 31) -> (X >>u 31)
if (C->isNullValue()) {
@@ -2125,7 +2141,7 @@
else if (ConstantInt *CI1 = dyn_cast(I.getOperand(0))) {
if (ConstantInt *CI2 = dyn_cast(Op1I->getOperand(1)))
// C1-(X+C2) --> (C1-C2)-X
- return BinaryOperator::createSub(ConstantExpr::getSub(CI1, CI2),
+ return BinaryOperator::createSub(Subtract(CI1, CI2),
Op1I->getOperand(0));
}
}
@@ -2167,8 +2183,7 @@
// X - X*C --> X * (1-C)
ConstantInt *C2 = 0;
if (dyn_castFold
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
> @@ -2443,10 +2443,9 @@
>// Check to see if this is an unsigned division with an exact
> power of 2,
>// if so, convert to a right shift.
>if (ConstantInt *C = dyn_cast(Op1)) {
> -APInt Val(C->getValue());
> -if (Val != 0 && Val.isPowerOf2())// Don't break X / 0
> +if (!C->isZero() && C->getValue().isPowerOf2()) // Don't
> break X / 0
Zero isn't a power of two, you should be able to drop the isZero check.
Thanks. BTW, nice work on instcombine!
-Chris
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Mar 24, 2007, at 9:55 PM, Nick Lewycky wrote:
> Chris Lattner wrote:
>> On Mar 23, 2007, at 11:46 AM, Reid Spencer wrote:
>>
>>> // shl uint X, 32 = 0 and shr ubyte Y, 9 = 0, ... just don't
>>> eliminate shr
>>> // of a signed value.
>>> //
>>> - unsigned TypeBits = Op0->getType()->getPrimitiveSizeInBits();
>>> - if (Op1->getZExtValue() >= TypeBits) {
>>> + if (Op1->getZExtValue() >= TypeBits) { // shift amount always
>>> <= 32 bits
>>
>>
>> This isn't safe. Code like:
>>
>> shl i1024 %A, 123456789123456789123456789123456789
>>
>> is undefined but legal. The compiler should not crash on it.
>
> What exactly is undefined? Just the result of that single instruction,
> or the behaviour of any program that attempts to execute it?
The behavior of any program that attempts to execute it.
> Would it be
> acceptable to replace such an instruction with "unreachable"?
Yes, in theory, but I'm not sure that's a good idea.
> If so, then it gives me a new source of information for predsimplify.
> After the instruction executes, I can assume that the RHS of a
> shift is
> within range.
I don't think this is appropriate. The failure mode is just too
great. You can treat the shift as though it returns an undef though.
-Chris
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Sun, 2007-03-25 at 00:55 -0400, Nick Lewycky wrote:
> Chris Lattner wrote:
> > On Mar 23, 2007, at 11:46 AM, Reid Spencer wrote:
> >
> >> // shl uint X, 32 = 0 and shr ubyte Y, 9 = 0, ... just don't
> >>eliminate shr
> >> // of a signed value.
> >> //
> >>- unsigned TypeBits = Op0->getType()->getPrimitiveSizeInBits();
> >>- if (Op1->getZExtValue() >= TypeBits) {
> >>+ if (Op1->getZExtValue() >= TypeBits) { // shift amount always
> >><= 32 bits
> >
> >
> > This isn't safe. Code like:
> >
> > shl i1024 %A, 123456789123456789123456789123456789
> >
> > is undefined but legal. The compiler should not crash on it.
>
> What exactly is undefined?
The result of the shift operation is undefined (any shift >= size of
integer type is undefined).
> Just the result of that single instruction,
> or the behaviour of any program that attempts to execute it?
The behavior of the program may go awry but just the instruction result
is undefined.
> Would it be
> acceptable to replace such an instruction with "unreachable"?
No.
>
> If so, then it gives me a new source of information for predsimplify.
> After the instruction executes, I can assume that the RHS of a shift is
> within range.
huh? The RHS of the shift is some number. You can't say anything about
it.
It is the result of the shift that becomes undefined when the value
exceeds the bit width of the quantity being shifted. What you could
assume is that the result of such shifts matches anything. But I'm not
sure you'd want to base an optimization on that.
Reid.
>
> Nick Lewycky
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.112 -> 1.113 --- Log message: add a note --- Diffs of the changes: (+1 -0) README.txt |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.112 llvm/lib/Target/PowerPC/README.txt:1.113 --- llvm/lib/Target/PowerPC/README.txt:1.112Sat Mar 24 23:46:28 2007 +++ llvm/lib/Target/PowerPC/README.txt Sun Mar 25 00:10:46 2007 @@ -3,6 +3,7 @@ TODO: * gpr0 allocation * implement do-loop -> bdnz transform +* __builtin_return_address not supported on PPC ===-=== ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.686 -> 1.687
---
Log message:
1. Avoid unnecessary APInt construction if possible.
2. Use isStrictlyPositive() instead of isPositive() in two places where
they need APInt value > 0 not only >=0.
---
Diffs of the changes: (+5 -7)
InstructionCombining.cpp | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.686
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.687
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.686 Sat Mar 24
23:26:16 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sun Mar 25 00:01:29 2007
@@ -2443,10 +2443,9 @@
// Check to see if this is an unsigned division with an exact power of 2,
// if so, convert to a right shift.
if (ConstantInt *C = dyn_cast(Op1)) {
-APInt Val(C->getValue());
-if (Val != 0 && Val.isPowerOf2())// Don't break X / 0
+if (!C->isZero() && C->getValue().isPowerOf2()) // Don't break X / 0
return BinaryOperator::createLShr(Op0,
- ConstantInt::get(Op0->getType(), Val.logBase2()));
+ ConstantInt::get(Op0->getType(), C->getValue().logBase2()));
}
// X udiv (C1 << N), where C1 is "1< X >> (N+C2)
@@ -2673,8 +2672,7 @@
// Turn A % (C << N), where C is 2^k, into A & ((C << N)-1)
if (RHSI->getOpcode() == Instruction::Shl &&
isa(RHSI->getOperand(0))) {
- APInt C1(cast(RHSI->getOperand(0))->getValue());
- if (C1.isPowerOf2()) {
+ if (cast(RHSI->getOperand(0))->getValue().isPowerOf2()) {
Constant *N1 = ConstantInt::getAllOnesValue(I.getType());
Value *Add = InsertNewInstBefore(BinaryOperator::createAdd(RHSI, N1,
"tmp"), I);
@@ -2711,7 +2709,7 @@
if (Value *RHSNeg = dyn_castNegVal(Op1))
if (!isa(RHSNeg) ||
-cast(RHSNeg)->getValue().isPositive()) {
+cast(RHSNeg)->getValue().isStrictlyPositive()) {
// X % -Y -> X % Y
AddUsesToWorkList(I);
I.setOperand(1, RHSNeg);
@@ -7466,7 +7464,7 @@
(ParamTy->isInteger() && ActTy->isInteger() &&
ParamTy->getPrimitiveSizeInBits() >= ActTy->getPrimitiveSizeInBits()) ||
(c && ParamTy->getPrimitiveSizeInBits() >=
ActTy->getPrimitiveSizeInBits()
- && c->getValue().isPositive());
+ && c->getValue().isStrictlyPositive());
if (Callee->isDeclaration() && !isConvertible) return false;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.392 -> 1.393
---
Log message:
Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
---
Diffs of the changes: (+16 -4)
SelectionDAGISel.cpp | 20
1 files changed, 16 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.393
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392Sat Mar 24
21:14:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Mar 25 00:00:54 2007
@@ -2387,14 +2387,23 @@
if (RegVT == ValueVT)
return Val;
+ if (MVT::isVector(RegVT)) {
+assert(ValueVT == MVT::Vector && "Unknown vector conversion!");
+return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
+ DAG.getConstant(MVT::getVectorNumElements(RegVT),
+ MVT::i32),
+ DAG.getValueType(MVT::getVectorBaseType(RegVT)));
+ }
+
if (MVT::isInteger(RegVT)) {
if (ValueVT < RegVT)
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
else
return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
- } else {
-return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
}
+
+ assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT));
+ return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
}
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
@@ -2407,7 +2416,10 @@
// If there is a single register and the types differ, this must be
// a promotion.
if (RegVT != ValueVT) {
- if (MVT::isInteger(RegVT)) {
+ if (MVT::isVector(RegVT)) {
+assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector
cast?");
+Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
+ } else if (MVT::isInteger(RegVT)) {
if (RegVT < ValueVT)
Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
else
@@ -3424,7 +3436,7 @@
// If this value was promoted, truncate it down.
if (ResVal.getValueType() != VT) {
if (VT == MVT::Vector) {
- // Insert a VBITCONVERT to convert from the packed result type to the
+ // Insert a VBIT_CONVERT to convert from the packed result type to
the
// MVT::Vector type.
unsigned NumElems = cast(RetTy)->getNumElements();
const Type *EltTy = cast(RetTy)->getElementType();
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[llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
Changes in directory llvm/test/CodeGen/X86:
2007-03-24-InlineAsmVectorOp.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+11 -0)
2007-03-24-InlineAsmVectorOp.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
diff -c /dev/null llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll:1.1
*** /dev/null Sun Mar 25 00:00:33 2007
--- llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll Sun Mar 25
00:00:23 2007
***
*** 0
--- 1,11
+ ; RUN: llvm-as < %s | llc -march=x86 | grep 'cmpltsd %xmm0, %xmm0'
+ target datalayout = "e-p:32:32"
+ target triple = "i686-apple-darwin9"
+
+ implementation ; Functions:
+
+ define void @acoshf() {
+ %tmp19 = tail call <2 x double> asm sideeffect "pcmpeqd $0, $0 \0A\09
cmpltsd $0, $0", "=x,0,~{dirflag},~{fpsr},~{flags}"( <2 x double>
zeroinitializer ) ; <<2 x double>> [#uses=0]
+ ret void
+ }
+
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Chris Lattner wrote:
> On Mar 23, 2007, at 11:46 AM, Reid Spencer wrote:
>
>> // shl uint X, 32 = 0 and shr ubyte Y, 9 = 0, ... just don't
>>eliminate shr
>> // of a signed value.
>> //
>>- unsigned TypeBits = Op0->getType()->getPrimitiveSizeInBits();
>>- if (Op1->getZExtValue() >= TypeBits) {
>>+ if (Op1->getZExtValue() >= TypeBits) { // shift amount always
>><= 32 bits
>
>
> This isn't safe. Code like:
>
> shl i1024 %A, 123456789123456789123456789123456789
>
> is undefined but legal. The compiler should not crash on it.
What exactly is undefined? Just the result of that single instruction,
or the behaviour of any program that attempts to execute it? Would it be
acceptable to replace such an instruction with "unreachable"?
If so, then it gives me a new source of information for predsimplify.
After the instruction executes, I can assume that the RHS of a shift is
within range.
Nick Lewycky
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.111 -> 1.112 --- Log message: add a note --- Diffs of the changes: (+13 -0) README.txt | 13 + 1 files changed, 13 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.111 llvm/lib/Target/PowerPC/README.txt:1.112 --- llvm/lib/Target/PowerPC/README.txt:1.111Fri Feb 9 11:38:01 2007 +++ llvm/lib/Target/PowerPC/README.txt Sat Mar 24 23:46:28 2007 @@ -625,3 +625,16 @@ blr ===-=== + +test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to: + +__ZNK4llvm5APInt17countLeadingZerosEv: +ld r2, 0(r3) +cntlzd r2, r2 +or r2, r2, r2 <<-- silly. +addi r3, r2, -64 +blr + +The dead or is a 'truncate' from 64- to 32-bits. + +===-=== ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.41 -> 1.42 --- Log message: Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll --- Diffs of the changes: (+4 -1) PPCInstr64Bit.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.41 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.42 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.41 Tue Feb 27 07:01:19 2007 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdSat Mar 24 23:44:03 2007 @@ -273,7 +273,10 @@ def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH), "sradi $rA, $rS, $SH", IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; - +def CNTLZD : XForm_11<31, 58, (ops G8RC:$rA, G8RC:$rS), + "cntlzd $rA, $rS", IntGeneral, + [(set G8RC:$rA, (ctlz G8RC:$rS))]>; + def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), "divd $rT, $rA, $rB", IntDivD, [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
Changes in directory llvm/test/CodeGen/PowerPC:
2007-03-24-cntlzd.ll added (r1.1)
---
Log message:
test that the ppc backend can do 64-bit cntlz
---
Diffs of the changes: (+13 -0)
2007-03-24-cntlzd.ll | 13 +
1 files changed, 13 insertions(+)
Index: llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
diff -c /dev/null llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll:1.1
*** /dev/null Sat Mar 24 23:44:01 2007
--- llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll Sat Mar 24 23:43:51 2007
***
*** 0
--- 1,13
+ ; RUN: llvm-as < %s | llc -march=ppc64 -mcpu=g5 | grep cntlzd
+
+ define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) {
+ %tmp19 = load i64* %t
+ %tmp23 = tail call i64 @llvm.ctlz.i64( i64 %tmp19 ) ;
[#uses=1]
+ %tmp2324 = trunc i64 %tmp23 to i32 ; [#uses=1]
+ %tmp89 = add i32 %tmp2324, -64 ; [#uses=1]
+ %tmp90 = add i32 %tmp89, 0 ; [#uses=1]
+ ret i32 %tmp90
+ }
+
+ declare i64 @llvm.ctlz.i64(i64)
+
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: TargetLowering.cpp updated: 1.101 -> 1.102 --- Log message: implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll --- Diffs of the changes: (+2 -0) TargetLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.101 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.102 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.101 Sat Mar 24 21:18:14 2007 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppSat Mar 24 23:35:41 2007 @@ -1841,6 +1841,7 @@ case 'i':// Simple Integer or Relocatable Constant case 'n':// Simple Integer case 's':// Relocatable Constant +case 'X':// Allow ANY value. case 'I':// Target registers. case 'J': case 'K': @@ -1870,6 +1871,7 @@ case 'i':// Simple Integer or Relocatable Constant case 'n':// Simple Integer case 's':// Relocatable Constant + case 'X':// Allows any operand. // These are okay if the operand is either a global variable address or a // simple immediate value. If we have one of these, map to the TargetXXX // version so that the value itself doesn't get selected. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
Changes in directory llvm/test/CodeGen/X86:
2007-03-24-InlineAsmXConstraint.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+9 -0)
2007-03-24-InlineAsmXConstraint.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
diff -c /dev/null llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll:1.1
*** /dev/null Sat Mar 24 23:35:33 2007
--- llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.llSat Mar 24
23:35:23 2007
***
*** 0
--- 1,9
+ ; RUN: llvm-as < %s | llc -march=x86 | grep 'psrlw $8, %xmm0'
+ target datalayout = "e-p:32:32"
+ target triple = "i686-apple-darwin9"
+
+ define void @test() {
+ tail call void asm sideeffect "psrlw $0, %xmm0",
"X,~{dirflag},~{fpsr},~{flags}"( i32 8 )
+ ret void
+ }
+
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.685 -> 1.686
---
Log message:
Make more uses of getHighBitsSet and get rid of some pointless & of an
APInt with its type mask.
---
Diffs of the changes: (+12 -12)
InstructionCombining.cpp | 24
1 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.685
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.686
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.685 Sat Mar 24
21:03:12 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Mar 24 23:26:16 2007
@@ -685,9 +685,9 @@
case Instruction::ZExt: {
// Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast(I->getOperand(0)->getType());
-APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
-
uint32_t SrcBitWidth = SrcTy->getBitWidth();
+APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
+
ComputeMaskedBits(I->getOperand(0), APInt(Mask).trunc(SrcBitWidth),
KnownZero.trunc(SrcBitWidth), KnownOne.trunc(SrcBitWidth), Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
@@ -700,9 +700,9 @@
case Instruction::SExt: {
// Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast(I->getOperand(0)->getType());
-APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
-
uint32_t SrcBitWidth = SrcTy->getBitWidth();
+APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
+
ComputeMaskedBits(I->getOperand(0), APInt(Mask).trunc(SrcBitWidth),
KnownZero.trunc(SrcBitWidth), KnownOne.trunc(SrcBitWidth), Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
@@ -743,7 +743,7 @@
if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
// Compute the new bits that are at the top now.
uint64_t ShiftAmt = SA->getZExtValue();
- APInt HighBits(APInt::getAllOnesValue(BitWidth).shl(BitWidth-ShiftAmt));
+ APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
// Unsigned shift right.
APInt Mask2(Mask.shl(ShiftAmt));
@@ -760,7 +760,7 @@
if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
// Compute the new bits that are at the top now.
uint64_t ShiftAmt = SA->getZExtValue();
- APInt HighBits(APInt::getAllOnesValue(BitWidth).shl(BitWidth-ShiftAmt));
+ APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
// Signed shift right.
APInt Mask2(Mask.shl(ShiftAmt));
@@ -830,8 +830,7 @@
KnownOne.getBitWidth() == BitWidth &&
Min.getBitWidth() == BitWidth && Max.getBitWidth() == BitWidth &&
"Ty, KnownZero, KnownOne and Min, Max must have equal bitwidth.");
- APInt TypeBits(APInt::getAllOnesValue(BitWidth));
- APInt UnknownBits = ~(KnownZero|KnownOne) & TypeBits;
+ APInt UnknownBits = ~(KnownZero|KnownOne);
APInt SignBit(APInt::getSignBit(BitWidth));
@@ -860,8 +859,7 @@
KnownOne.getBitWidth() == BitWidth &&
Min.getBitWidth() == BitWidth && Max.getBitWidth() &&
"Ty, KnownZero, KnownOne and Min, Max must have equal bitwidth.");
- APInt TypeBits(APInt::getAllOnesValue(BitWidth));
- APInt UnknownBits = ~(KnownZero|KnownOne) & TypeBits;
+ APInt UnknownBits = ~(KnownZero|KnownOne);
// The minimum value is when the unknown bits are all zeros.
Min = KnownOne;
@@ -1118,7 +1116,8 @@
case Instruction::ZExt: {
// Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast(I->getOperand(0)->getType());
-APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
+uint32_t SrcBitWidth = SrcTy->getBitWidth();
+APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
DemandedMask &= SrcTy->getMask().zext(BitWidth);
uint32_t zextBf = SrcTy->getBitWidth();
@@ -1137,7 +1136,8 @@
case Instruction::SExt: {
// Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast(I->getOperand(0)->getType());
-APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
+uint32_t SrcBitWidth = SrcTy->getBitWidth();
+APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
// Get the sign bit for the source type
APInt InSignBit(APInt::getSignBit(SrcTy->getPrimitiveSizeInBits()));
___
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[llvm-commits] [125328] Improve CanonicalizeConstraint to support canonicalization of multiple-alternative inline asm constraints , e.g., turn:
Revision: 125328
Author: clattner
Date: 2007-03-24 21:02:59 -0700 (Sat, 24 Mar 2007)
Log Message:
---
Improve CanonicalizeConstraint to support canonicalization of
multiple-alternative inline asm constraints, e.g., turn:
__asm__ volatile("inw %w1, %w0" : "=a" (datum) : "Nd" (port));
into:
"={ax},N{dx},...
instead of:
"={ax},Nd,...
This allows us to correctly compile inline asm like the example above.
Modified Paths:
--
apple-local/branches/llvm/gcc/llvm-convert.cpp
Modified: apple-local/branches/llvm/gcc/llvm-convert.cpp
===
--- apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-03-25 03:39:48 UTC
(rev 125327)
+++ apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-03-25 04:02:59 UTC
(rev 125328)
@@ -3415,11 +3415,9 @@
/// CanonicalizeConstraint - If we can canonicalize the constraint into
/// something simpler, do so now. This turns register classes with a single
/// register into the register itself, expands builtin constraints to multiple
-/// alternatives, etc. If the constraint cannot be simplified, this returns an
-/// empty string.
+/// alternatives, etc.
static std::string CanonicalizeConstraint(const char *Constraint) {
std::string Result;
- unsigned RegClass;
// Skip over modifier characters.
bool DoneModifiers = false;
@@ -3436,51 +3434,67 @@
++Constraint;
break;
case '#': // No constraint letters left.
- return "";
+ return Result;
}
}
+ while (*Constraint) {
+char ConstraintChar = *Constraint++;
+
+// 'g' is just short-hand for 'imr'.
+if (ConstraintChar == 'g') {
+ Result += "imr";
+ continue;
+}
- if (*Constraint == 'r') // r is a special case for some reason.
-RegClass = GENERAL_REGS;
- else if (*Constraint == 'g')
-return "imr";
- else
-RegClass = REG_CLASS_FROM_CONSTRAINT(*Constraint, Constraint);
+// See if this is a regclass constraint.
+unsigned RegClass;
+if (ConstraintChar == 'r')
+ // REG_CLASS_FROM_CONSTRAINT doesn't support 'r' for some reason.
+ RegClass = GENERAL_REGS;
+else
+ RegClass = REG_CLASS_FROM_CONSTRAINT(Constraint[-1], Constraint-1);
- if (RegClass == NO_REGS) return Result; // not a reg class.
+if (RegClass == NO_REGS) { // not a reg class.
+ Result += ConstraintChar;
+ continue;
+}
- // Look to see if the specified regclass has exactly one member, and if so,
- // what it is. Cache this information in AnalyzedRegClasses once computed.
- static std::map AnalyzedRegClasses;
+// Look to see if the specified regclass has exactly one member, and if so,
+// what it is. Cache this information in AnalyzedRegClasses once computed.
+static std::map AnalyzedRegClasses;
- std::map::iterator I
=AnalyzedRegClasses.lower_bound(RegClass);
+std::map::iterator I =
+ AnalyzedRegClasses.lower_bound(RegClass);
- int RegMember;
- if (I != AnalyzedRegClasses.end() && I->first == RegClass) {
-// We've already computed this, reuse value.
-RegMember = I->second;
- } else {
-// Otherwise, scan the regclass, looking for exactly one member.
-RegMember = -1; // -1 => not one thing
-for (unsigned j = 0; j != FIRST_PSEUDO_REGISTER; ++j)
- if (TEST_HARD_REG_BIT(reg_class_contents[RegClass], j)) {
-if (RegMember == -1) {
- RegMember = j;
-} else {
- RegMember = -1;
- break;
+int RegMember;
+if (I != AnalyzedRegClasses.end() && I->first == RegClass) {
+ // We've already computed this, reuse value.
+ RegMember = I->second;
+} else {
+ // Otherwise, scan the regclass, looking for exactly one member.
+ RegMember = -1; // -1 => not a single-register class.
+ for (unsigned j = 0; j != FIRST_PSEUDO_REGISTER; ++j)
+if (TEST_HARD_REG_BIT(reg_class_contents[RegClass], j)) {
+ if (RegMember == -1) {
+RegMember = j;
+ } else {
+RegMember = -1;
+break;
+ }
}
- }
-// Remember this answer for the next query of this regclass.
-AnalyzedRegClasses.insert(I, std::make_pair(RegClass, RegMember));
- }
+ // Remember this answer for the next query of this regclass.
+ AnalyzedRegClasses.insert(I, std::make_pair(RegClass, RegMember));
+}
- // If we found a single register register class, return the register.
- if (RegMember != -1) {
-Result = '{';
-Result += reg_names[RegMember];
-Result += '}';
+// If we found a single register register class, return the register.
+if (RegMember != -1) {
+ Result += '{';
+ Result += reg_names[RegMember];
+ Result += '}';
+} else {
+ Result += ConstraintChar;
+}
}
return Result;
@@ -3556,14 +3570,7 @@
// If we can simplify the constraint into something else, do so now. This
[llvm-commits] [125327] use a correct substitute for the 'g' constraint, now that it is safe.
Revision: 125327 Author: clattner Date: 2007-03-24 20:39:48 -0700 (Sat, 24 Mar 2007) Log Message: --- use a correct substitute for the 'g' constraint, now that it is safe. Modified Paths: -- apple-local/branches/llvm/gcc/llvm-convert.cpp Modified: apple-local/branches/llvm/gcc/llvm-convert.cpp === --- apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-03-25 01:47:34 UTC (rev 125326) +++ apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-03-25 03:39:48 UTC (rev 125327) @@ -3444,11 +3444,7 @@ if (*Constraint == 'r') // r is a special case for some reason. RegClass = GENERAL_REGS; else if (*Constraint == 'g') -// FIXME: 'imr' is the appropriate constraint to use here, as it allows -// maximum generality. However, we accept just "r" for now because LLVM -// doesn't support multiple alternatives yet. -//return "imr"; -return "r"; +return "imr"; else RegClass = REG_CLASS_FROM_CONSTRAINT(*Constraint, Constraint); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
TargetLowering.cpp updated: 1.100 -> 1.101
---
Log message:
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
---
Diffs of the changes: (+4 -1)
TargetLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.100
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.101
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.100 Sat Mar 24
21:14:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppSat Mar 24 21:18:14 2007
@@ -1852,7 +1852,10 @@
return C_Other;
}
}
- // TODO: Handle registers.
+
+ if (Constraint.size() > 1 && Constraint[0] == '{' &&
+ Constraint[Constraint.size()-1] == '}')
+return C_Register;
return C_Unknown;
}
___
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[llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
Changes in directory llvm/test/CodeGen/X86:
2007-03-24-InlineAsmMultiRegConstraint.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+11 -0)
2007-03-24-InlineAsmMultiRegConstraint.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
diff -c /dev/null
llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll:1.1
*** /dev/null Sat Mar 24 21:18:08 2007
--- llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll Sat Mar
24 21:17:58 2007
***
*** 0
--- 1,11
+ ; RUN: llvm-as < %s | llc -march=x86
+
+ define i32 @test(i16 %tmp40414244) {
+ %tmp48 = call i32 asm sideeffect "inl ${1:w}, $0",
"={ax},N{dx},~{dirflag},~{fpsr},~{flags}"( i16 %tmp40414244 )
+ ret i32 %tmp48
+ }
+
+ define i32 @test2(i16 %tmp40414244) {
+ %tmp48 = call i32 asm sideeffect "inl ${1:w}, $0",
"={ax},N{dx},~{dirflag},~{fpsr},~{flags}"( i16 14 )
+ ret i32 %tmp48
+ }
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.262 -> 1.263
PPCISelLowering.h updated: 1.62 -> 1.63
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+15 -13)
PPCISelLowering.cpp | 26 ++
PPCISelLowering.h |2 +-
2 files changed, 15 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.262
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.263
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.262 Tue Mar 13 10:02:46 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -3105,20 +3105,22 @@
}
-/// getConstraintType - Given a constraint letter, return the type of
+/// getConstraintType - Given a constraint, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
-PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
- default: break;
- case 'b':
- case 'r':
- case 'f':
- case 'v':
- case 'y':
-return C_RegisterClass;
- }
- return TargetLowering::getConstraintType(ConstraintLetter);
+PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'b':
+case 'r':
+case 'f':
+case 'v':
+case 'y':
+ return C_RegisterClass;
+}
+ }
+ return TargetLowering::getConstraintType(Constraint);
}
std::pair
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.62
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.62 Mon Mar 12 18:29:01 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sat Mar 24 21:14:49 2007
@@ -229,7 +229,7 @@
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
___
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaISelLowering.h
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.84 -> 1.85
AlphaISelLowering.h updated: 1.24 -> 1.25
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+11 -9)
AlphaISelLowering.cpp | 18 ++
AlphaISelLowering.h |2 +-
2 files changed, 11 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.84
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.85
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.84Wed Mar 7 10:25:08 2007
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -571,14 +571,16 @@
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
AlphaTargetLowering::ConstraintType
-AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
- default: break;
- case 'f':
- case 'r':
-return C_RegisterClass;
- }
- return TargetLowering::getConstraintType(ConstraintLetter);
+AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'f':
+case 'r':
+ return C_RegisterClass;
+}
+ }
+ return TargetLowering::getConstraintType(Constraint);
}
std::vector AlphaTargetLowering::
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.24
llvm/lib/Target/Alpha/AlphaISelLowering.h:1.25
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.24 Wed Jan 24 15:09:16 2007
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Sat Mar 24 21:14:49 2007
@@ -81,7 +81,7 @@
bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG);
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string &Constraint) const;
std::vector
getRegClassForInlineAsmConstraint(const std::string &Constraint,
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.29 -> 1.30
ARMISelLowering.h updated: 1.7 -> 1.8
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+8 -6)
ARMISelLowering.cpp | 12 +++-
ARMISelLowering.h |2 +-
2 files changed, 8 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.29
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.30
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.29Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -1550,12 +1550,14 @@
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
ARMTargetLowering::ConstraintType
-ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
-case 'l':
- return C_RegisterClass;
-default: return TargetLowering::getConstraintType(ConstraintLetter);
+ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'l': return C_RegisterClass;
+}
}
+ return TargetLowering::getConstraintType(Constraint);
}
std::pair
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.7
llvm/lib/Target/ARM/ARMISelLowering.h:1.8
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.7 Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Sat Mar 24 21:14:49 2007
@@ -133,7 +133,7 @@
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const;
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.391 -> 1.392
TargetLowering.cpp updated: 1.99 -> 1.100
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+28 -24)
SelectionDAGISel.cpp |8
TargetLowering.cpp | 44
2 files changed, 28 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.391
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.391Thu Mar 22
11:38:57 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Mar 24 21:14:49 2007
@@ -2633,9 +2633,9 @@
std::string *Current = &C[0];
// If we have multiple constraints, try to pick the most general one ahead
// of time. This isn't a wonderful solution, but handles common cases.
- TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0][0]);
+ TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
for (unsigned j = 1, e = C.size(); j != e; ++j) {
-TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j][0]);
+TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
if (getConstraintGenerality(ThisFlavor) >
getConstraintGenerality(Flavor)) {
// This constraint letter is more general than the previous one,
@@ -2748,7 +2748,7 @@
case InlineAsm::isOutput: {
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (ConstraintCode.size() == 1) // not a physreg name.
-CTy = TLI.getConstraintType(ConstraintCode[0]);
+CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Memory) {
// Memory output.
@@ -2863,7 +2863,7 @@
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (ConstraintCode.size() == 1) // not a physreg name.
-CTy = TLI.getConstraintType(ConstraintCode[0]);
+CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Other) {
InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.99
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.100
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.99 Wed Mar 21
16:51:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppSat Mar 24 21:14:49 2007
@@ -1828,28 +1828,32 @@
//===--===//
TargetLowering::ConstraintType
-TargetLowering::getConstraintType(char ConstraintLetter) const {
+TargetLowering::getConstraintType(const std::string &Constraint) const {
// FIXME: lots more standard ones to handle.
- switch (ConstraintLetter) {
- default: return C_Unknown;
- case 'r': return C_RegisterClass;
- case 'm':// memory
- case 'o':// offsetable
- case 'V':// not offsetable
-return C_Memory;
- case 'i':// Simple Integer or Relocatable Constant
- case 'n':// Simple Integer
- case 's':// Relocatable Constant
- case 'I':// Target registers.
- case 'J':
- case 'K':
- case 'L':
- case 'M':
- case 'N':
- case 'O':
- case 'P':
-return C_Other;
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'r': return C_RegisterClass;
+case 'm':// memory
+case 'o':// offsetable
+case 'V':// not offsetable
+ return C_Memory;
+case 'i':// Simple Integer or Relocatable Constant
+case 'n':// Simple Integer
+case 's':// Relocatable Constant
+case 'I':// Target registers.
+case 'J':
+case 'K':
+case 'L':
+case 'M':
+case 'N':
+case 'O':
+case 'P':
+ return C_Other;
+}
}
+ // TODO: Handle registers.
+ return C_Unknown;
}
/// isOperandValidForConstraint - Return the specified operand (possibly
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.376 -> 1.377
X86ISelLowering.h updated: 1.93 -> 1.94
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+17 -13)
X86ISelLowering.cpp | 28
X86ISelLowering.h |2 +-
2 files changed, 17 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.376
llvm/lib/Target/X86/X86ISelLowering.cpp:1.377
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.376 Sat Mar 24 20:57:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -4521,19 +4521,23 @@
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
X86TargetLowering::ConstraintType
-X86TargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
- case 'A':
- case 'r':
- case 'R':
- case 'l':
- case 'q':
- case 'Q':
- case 'x':
- case 'Y':
-return C_RegisterClass;
- default: return TargetLowering::getConstraintType(ConstraintLetter);
+X86TargetLowering::getConstraintType(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+case 'A':
+case 'r':
+case 'R':
+case 'l':
+case 'q':
+case 'Q':
+case 'x':
+case 'Y':
+ return C_RegisterClass;
+default:
+ break;
+}
}
+ return TargetLowering::getConstraintType(Constraint);
}
/// isOperandValidForConstraint - Return the specified operand (possibly
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.93
llvm/lib/Target/X86/X86ISelLowering.h:1.94
--- llvm/lib/Target/X86/X86ISelLowering.h:1.93 Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Sat Mar 24 21:14:49 2007
@@ -316,7 +316,7 @@
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string &Constraint) const;
std::vector
getRegClassForInlineAsmConstraint(const std::string &Constraint,
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.115 -> 1.116 --- Log message: switch TargetLowering::getConstraintType to take the entire constraint, not just the first letter. No functionality change. --- Diffs of the changes: (+3 -3) TargetLowering.h |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.115 llvm/include/llvm/Target/TargetLowering.h:1.116 --- llvm/include/llvm/Target/TargetLowering.h:1.115 Wed Mar 21 16:51:52 2007 +++ llvm/include/llvm/Target/TargetLowering.h Sat Mar 24 21:14:49 2007 @@ -806,9 +806,9 @@ C_Unknown // Unsupported constraint. }; - /// getConstraintType - Given a constraint letter, return the type of - /// constraint it is for this target. - virtual ConstraintType getConstraintType(char ConstraintLetter) const; + /// getConstraintType - Given a constraint, return the type of constraint it + /// is for this target. + virtual ConstraintType getConstraintType(const std::string &Constraint) const; /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.684 -> 1.685
---
Log message:
More APIntification:
* Convert the last use of a uint64_t that should have been an APInt.
* Change ComputeMaskedBits to have a const reference argument for the Mask
so that recursions don't cause unneeded temporaries. This causes temps
to be needed in other places (where the mask has to change) but this
change optimizes for the recursion which is more frequent.
* Remove two instances of &ing a Mask with getAllOnesValue. Its not
needed any more because APInt is accurate in its bit computations.
* Start using the getLowBitsSet and getHighBits set methods on APInt
instead of shifting. This makes it more clear in the code what is
going on.
---
Diffs of the changes: (+24 -24)
InstructionCombining.cpp | 48 +++
1 files changed, 24 insertions(+), 24 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.684
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.685
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.684 Sat Mar 24
18:56:43 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Mar 24 21:03:12 2007
@@ -578,7 +578,7 @@
/// optimized based on the contradictory assumption that it is non-zero.
/// Because instcombine aggressively folds operations with undef args anyway,
/// this won't lose us code quality.
-static void ComputeMaskedBits(Value *V, APInt Mask, APInt& KnownZero,
+static void ComputeMaskedBits(Value *V, const APInt& Mask, APInt& KnownZero,
APInt& KnownOne, unsigned Depth = 0) {
assert(V && "No Value?");
assert(Depth <= 6 && "Limit Search Depth");
@@ -603,14 +603,13 @@
KnownZero.clear(); KnownOne.clear(); // Don't know anything.
APInt KnownZero2(KnownZero), KnownOne2(KnownOne);
- Mask &= APInt::getAllOnesValue(BitWidth);
switch (I->getOpcode()) {
- case Instruction::And:
+ case Instruction::And: {
// If either the LHS or the RHS are Zero, the result is zero.
ComputeMaskedBits(I->getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
-Mask &= ~KnownZero;
-ComputeMaskedBits(I->getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+APInt Mask2(Mask & ~KnownZero);
+ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@@ -619,10 +618,11 @@
// Output known-0 are known to be clear if zero in either the LHS | RHS.
KnownZero |= KnownZero2;
return;
- case Instruction::Or:
+ }
+ case Instruction::Or: {
ComputeMaskedBits(I->getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
-Mask &= ~KnownOne;
-ComputeMaskedBits(I->getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+APInt Mask2(Mask & ~KnownOne);
+ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@@ -631,6 +631,7 @@
// Output known-1 are known to be set if set in either the LHS | RHS.
KnownOne |= KnownOne2;
return;
+ }
case Instruction::Xor: {
ComputeMaskedBits(I->getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(I->getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
@@ -667,7 +668,7 @@
// All these have integer operands
uint32_t SrcBitWidth =
cast(I->getOperand(0)->getType())->getBitWidth();
-ComputeMaskedBits(I->getOperand(0), Mask.zext(SrcBitWidth),
+ComputeMaskedBits(I->getOperand(0), APInt(Mask).zext(SrcBitWidth),
KnownZero.zext(SrcBitWidth), KnownOne.zext(SrcBitWidth), Depth+1);
KnownZero.trunc(BitWidth);
KnownOne.trunc(BitWidth);
@@ -687,7 +688,7 @@
APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
uint32_t SrcBitWidth = SrcTy->getBitWidth();
-ComputeMaskedBits(I->getOperand(0), Mask.trunc(SrcBitWidth),
+ComputeMaskedBits(I->getOperand(0), APInt(Mask).trunc(SrcBitWidth),
KnownZero.trunc(SrcBitWidth), KnownOne.trunc(SrcBitWidth), Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
// The top bits are known to be zero.
@@ -702,7 +703,7 @@
APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
uint32_t SrcBitWidth = SrcTy->getBitWidth();
-ComputeMaskedBits(I->getOperand(0), Mask.trunc(SrcBitWidth),
+ComputeMaskedBits(I->getOperand(0), APInt(Mask).trunc(SrcBitWidth),
KnownZero.trunc(SrcBitWidth), KnownOne.trunc(SrcBitWidth), Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZ
[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.98 -> 1.99 --- Log message: Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. --- Diffs of the changes: (+4 -1) X86ATTAsmPrinter.cpp |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.98 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.99 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.98 Sat Mar 24 20:44:57 2007 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppSat Mar 24 21:01:03 2007 @@ -499,7 +499,10 @@ case 'h': // Print QImode high register case 'w': // Print HImode register case 'k': // Print SImode register - return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]); + if (MI->getOperand(OpNo).isReg()) +return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]); + printOperand(MI, OpNo); + return false; case 'P': // Don't print @PLT, but do print as memory. printOperand(MI, OpNo, "mem"); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.375 -> 1.376
---
Log message:
enforce the proper range for the i386 N constraint.
---
Diffs of the changes: (+9 -8)
X86ISelLowering.cpp | 17 +
1 files changed, 9 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.375
llvm/lib/Target/X86/X86ISelLowering.cpp:1.376
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.375 Thu Mar 22 13:42:45 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 24 20:57:35 2007
@@ -4544,16 +4544,17 @@
switch (Constraint) {
default: break;
case 'I':
-if (isa(Op)) {
- unsigned Value = cast(Op)->getValue();
- if (Value <= 31)
+if (ConstantSDNode *C = dyn_cast(Op)) {
+ if (C->getValue() <= 31)
return Op;
- else
-return SDOperand(0,0);
-} else {
-return SDOperand(0,0);
}
-break;
+return SDOperand(0,0);
+ case 'N':
+if (ConstantSDNode *C = dyn_cast(Op)) {
+ if (C->getValue() <= 255)
+return Op;
+}
+return SDOperand(0,0);
case 'i':
// Literal immediates are always ok.
if (isa(Op)) return Op;
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[llvm-commits] [125326] fix in 80 cols
Revision: 125326
Author: clattner
Date: 2007-03-24 18:47:34 -0700 (Sat, 24 Mar 2007)
Log Message:
---
fix in 80 cols
Modified Paths:
--
apple-local/branches/llvm/gcc/llvm-types.cpp
Modified: apple-local/branches/llvm/gcc/llvm-types.cpp
===
--- apple-local/branches/llvm/gcc/llvm-types.cpp2007-03-25 01:30:48 UTC
(rev 125325)
+++ apple-local/branches/llvm/gcc/llvm-types.cpp2007-03-25 01:47:34 UTC
(rev 125326)
@@ -66,7 +66,8 @@
// GET_TYPE_LLVM/SET_TYPE_LLVM - Associate an LLVM type with each TREE type.
// These are lazily computed by ConvertType.
-#define SET_TYPE_SYMTAB_LLVM(NODE, index) (TYPE_CHECK (NODE)->type.symtab.llvm
= index)
+#define SET_TYPE_SYMTAB_LLVM(NODE, index) \
+ (TYPE_CHECK (NODE)->type.symtab.llvm = index)
// Note down LLVM type for GCC tree node.
static const Type * llvm_set_type(tree Tr, const Type *Ty) {
@@ -139,7 +140,8 @@
LTypes.push_back(Ty);
}
- // Now, llvm.pch.types value is not required so remove it from the symbol
table.
+ // Now, llvm.pch.types value is not required so remove it from the symbol
+ // table.
GV->eraseFromParent();
}
@@ -169,8 +171,9 @@
// Give names to nameless types.
if (Ty && TypeNameMap[Ty].empty()) {
- std::string NewName =
TheModule->getTypeSymbolTable().getUniqueName("llvm.fe.ty");
- TheModule->addTypeName (NewName, Ty);
+ std::string NewName =
+TheModule->getTypeSymbolTable().getUniqueName("llvm.fe.ty");
+ TheModule->addTypeName(NewName, Ty);
TypeNameMap[*I] = NewName;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.97 -> 1.98 --- Log message: Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll --- Diffs of the changes: (+4 -0) X86ATTAsmPrinter.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.97 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.98 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.97 Thu Feb 22 19:58:50 2007 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppSat Mar 24 20:44:57 2007 @@ -500,6 +500,10 @@ case 'w': // Print HImode register case 'k': // Print SImode register return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]); + +case 'P': // Don't print @PLT, but do print as memory. + printOperand(MI, OpNo, "mem"); + return false; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
Changes in directory llvm/test/CodeGen/X86:
2007-03-24-InlineAsmPModifier.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+10 -0)
2007-03-24-InlineAsmPModifier.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
diff -c /dev/null llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll:1.1
*** /dev/null Sat Mar 24 20:44:50 2007
--- llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll Sat Mar 24
20:44:40 2007
***
*** 0
--- 1,10
+ ; RUN: llvm-as < %s | llc -march=x86 | grep 'mov %gs:72, %eax'
+ target datalayout = "e-p:32:32"
+ target triple = "i686-apple-darwin9"
+
+ define void @test() {
+ %tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0",
"=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 );
<%struct._pthread*> [#uses=1]
+ ret void
+ }
+
+
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[llvm-commits] [125325] work around a latent bug, until it can be fixed properly.
Revision: 125325 Author: clattner Date: 2007-03-24 18:30:48 -0700 (Sat, 24 Mar 2007) Log Message: --- work around a latent bug, until it can be fixed properly. Modified Paths: -- apple-local/branches/llvm/gcc/llvm-types.cpp Modified: apple-local/branches/llvm/gcc/llvm-types.cpp === --- apple-local/branches/llvm/gcc/llvm-types.cpp2007-03-24 09:41:55 UTC (rev 125324) +++ apple-local/branches/llvm/gcc/llvm-types.cpp2007-03-25 01:30:48 UTC (rev 125325) @@ -963,7 +963,8 @@ if (CurFieldNo < ElementOffsetInBytes.size()) return CurFieldNo; // Otherwise, we couldn't find the field! - assert(0 && "Could not find field!"); + // FIXME: this works around a latent bug! + //assert(0 && "Could not find field!"); return ~0U; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT: APInt.h updated: 1.56 -> 1.57 --- Log message: Fix a typo in a comment. --- Diffs of the changes: (+1 -1) APInt.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/ADT/APInt.h diff -u llvm/include/llvm/ADT/APInt.h:1.56 llvm/include/llvm/ADT/APInt.h:1.57 --- llvm/include/llvm/ADT/APInt.h:1.56 Sat Mar 24 19:01:47 2007 +++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 20:13:46 2007 @@ -726,7 +726,7 @@ /// @brief Sign extend to a new width. APInt &sext(uint32_t width); - /// This operation zero extends the APInt to a new width. Thie high order bits + /// This operation zero extends the APInt to a new width. The high order bits /// are filled with 0 bits. It is an error to specify a width that is less /// than or equal to the current width. /// @brief Zero extend to a new width. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] SwitchLowering refactoring patch for review
On Mar 20, 2007, at 9:29 AM, Anton Korobeynikov wrote:
This is the first patch targeting switch lowering refactoring as
indicated in PR926.
oooh!
Currently it implements "worklist" strategy, where we're deciding
either
emit JT or split the case range or each step (not only in the early
beginning). Also, I've included some heuristic to calculate pivot:
maximise sum of densities of RHS & LHS. This lead to unbalanced tree,
but really increase chances of JT emission in the future.
E.g. we split switch (0-5, 120-126, 1024) into 2 JT's and 1 specific
comparison + some "glue" code to discriminate cases.
Tested with:
1. llvm-gcc bootstrap
2. Building mozilla & qt with bootstrapped compiler.
+ struct JumpTableHeader
+ {
+JumpTableHeader(uint64_t F, uint64_t L, Value* SV,
MachineBasicBlock* H,
+bool E = false):
Nitpick: the { should go on the same line as the struct.
+void SelectionDAGLowering::visitJumpTableHeader
(SelectionDAGISel::JumpTable &JT,
+
SelectionDAGISel::JumpTableHeader &JTH) {
Please add a comment block before this method, describing what it does.
+ unsigned LSize = 1;
+ unsigned RSize = Size-1;
+ for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
+ J!=E; ++I, ++J, ++LSize, --RSize) {
+uint64_t LEnd = cast(I->first)->getSExtValue();
+uint64_t RBegin = cast(J->first)->getSExtValue();
+double LDensity = (double)LSize / (double)((LEnd - First) +
1ULL);
+double RDensity = (double)RSize / (double)((Last - RBegin) +
1ULL);
+if (Density < (LDensity + RDensity)) {
+ Pivot = J;
+ Density = LDensity + RDensity;
+}
+ }
Please add some comments explaining how this works.
I have to say, you did an *excellent* job. Nice work,
-Chris___
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.55 -> 1.56
---
Log message:
Actually, for getHighBitsSet and getLowBitsSet, don't make a 0 bit size
illegal. Instead do the 0 valued construction for the user. This is because
the caller may not know (or care to check) that the number of bits set is
zero.
---
Diffs of the changes: (+6 -2)
APInt.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.55 llvm/include/llvm/ADT/APInt.h:1.56
--- llvm/include/llvm/ADT/APInt.h:1.55 Sat Mar 24 18:47:58 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 19:01:47 2007
@@ -355,7 +355,9 @@
/// @brief Get a value with high bits set
static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet) {
assert(hiBitsSet <= numBits && "Too many bits to set!");
-assert(hiBitsSet > 0 && "You must set SOME bits");
+// Handle a degenerate case, to avoid shifting by word size
+if (hiBitsSet == 0)
+ return APInt(numBits, 0);
uint32_t shiftAmt = numBits - hiBitsSet;
// For small values, return quickly
if (numBits <= APINT_BITS_PER_WORD)
@@ -369,7 +371,9 @@
/// @brief Get a value with low bits set
static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet) {
assert(loBitsSet <= numBits && "Too many bits to set!");
-assert(loBitsSet > 0 && "You must set SOME bits");
+// Handle a degenerate case, to avoid shifting by word size
+if (loBitsSet == 0)
+ return APInt(numBits, 0);
uint32_t shiftAmt = numBits - loBitsSet;
// For small values, return quickly
if (numBits <= APINT_BITS_PER_WORD)
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.683 -> 1.684
---
Log message:
fix a regression on vector or instructions.
---
Diffs of the changes: (+9 -9)
InstructionCombining.cpp | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.683
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.684
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.683 Sat Mar 24
10:34:37 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Mar 24 18:56:43 2007
@@ -3636,9 +3636,8 @@
bool Changed = SimplifyCommutative(I);
Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
- if (isa(Op1))
-return ReplaceInstUsesWith(I, // X | undef -> -1
- ConstantInt::getAllOnesValue(I.getType()));
+ if (isa(Op1)) // X | undef -> -1
+return ReplaceInstUsesWith(I, ConstantInt::getAllOnesValue(I.getType()));
// or X, X = X
if (Op0 == Op1)
@@ -3646,12 +3645,13 @@
// See if we can simplify any instructions used by the instruction whose
sole
// purpose is to compute bits we don't care about.
- uint32_t BitWidth = cast(I.getType())->getBitWidth();
- APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
- if (!isa(I.getType()) &&
- SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth),
- KnownZero, KnownOne))
-return &I;
+ if (!isa(I.getType())) {
+uint32_t BitWidth = cast(I.getType())->getBitWidth();
+APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
+if (SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth),
+ KnownZero, KnownOne))
+ return &I;
+ }
// or X, -1 == -1
if (ConstantInt *RHS = dyn_cast(Op1)) {
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/README.txt
On Mar 20, 2007, at 3:22 PM, Evan Cheng wrote: > Potential spiller improvement. > > Index: llvm/lib/CodeGen/README.txt > diff -c /dev/null llvm/lib/CodeGen/README.txt:1.1 > *** /dev/null Tue Mar 20 17:22:48 2007 > --- llvm/lib/CodeGen/README.txt Tue Mar 20 17:22:38 2007 > *** > *** 0 > --- 1,27 > + Common register allocation / spilling problem: > + > + mul lr, r4, lr > + str lr, [sp, #+52] > + ldr lr, [r1, #+32] > + sxth r3, r3 > + ldr r4, [sp, #+52] > + mla r4, r3, lr, r4 > + > + can be: > + > + mul lr, r4, lr > + mov r4, lr > + str lr, [sp, #+52] > + ldr lr, [r1, #+32] > + sxth r3, r3 > + mla r4, r3, lr, r4 > + > + and then "merge" mul and mov: > + > + mul r4, r4, lr > + str lr, [sp, #+52] This should be 'str r4, ...' no? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [125160] Better support for variable size struct fields.
On Mar 21, 2007, at 1:52 PM, Lauro Ramos Venancio wrote:
> Something in this patch broke the llvm-gcc compilation on arm-linux:
Is this already fixed?
If not, Duncan, can you please investigate? Lauro, can you try to
reduce a .i file?
Thanks,
-Chris
> /home/laurov/llvm/llvm-gcc/build/gcc/xgcc
> -B/home/laurov/llvm/llvm-gcc/build/gcc/
> -B/usr/local/arm-linux-gnueabi/bin/
> -B/usr/local/arm-linux-gnueabi/lib/ -isystem
> /usr/local/arm-linux-gnueabi/include -isystem
> /usr/local/arm-linux-gnueabi/sys-include -O2 -DIN_GCC-W -Wall
> -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes
> -Wold-style-definition -isystem ./include -fPIC -g
> -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I.
> -I/home/laurov/llvm/llvm-gcc/gcc -I/home/laurov/llvm/llvm-gcc/gcc/.
> -I/home/laurov/llvm/llvm-gcc/gcc/../include
> -I/home/laurov/llvm/llvm-gcc/gcc/../libcpp/include
> -I/home/laurov/llvm/llvm/include
> -I/home/laurov/llvm/llvm/build//include -fexceptions -c
> /home/laurov/llvm/llvm-gcc/gcc/config/arm/unwind-arm.c -o
> libgcc/./unwind-arm.o
> cc1: /home/laurov/llvm/llvm-gcc/gcc/llvm-types.cpp:968: unsigned int
> StructTypeConversionInfo::getLLVMFieldFor(uint64_t, unsigned int&,
> bool): Assertion `0 && "Could not find field!"' failed.
> /home/laurov/llvm/llvm-gcc/gcc/config/arm/unwind-arm.c: In function
> '_Unwind_Complete':
> /home/laurov/llvm/llvm-gcc/gcc/config/arm/unwind-arm.c:582: internal
> compiler error: Aborted
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See http://llvm.org/bugs> for instructions.
> make[2]: *** [libgcc/./unwind-arm.o] Error 1
>
>
>
> This bug can be reproduced using llvm-gcc for i386:
>
> [EMAIL PROTECTED]:/tmp$ llvm-gcc unwind-arm.c
> cc1: ../../gcc/llvm-types.cpp:968: unsigned int
> StructTypeConversionInfo::getLLVMFieldFor(uint64_t, unsigned int&,
> bool): Assertion `0 && "Could not find field!"' failed.
> unwind-arm.c: In function 'get_eit_entry':
> unwind-arm.c:382: internal compiler error: Aborted
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See http://llvm.org/bugs> for instructions.
>
> Lauro
>
>
> 2007/3/19, [EMAIL PROTECTED] <[EMAIL PROTECTED]>:
>> Revision: 125160
>> Author: dpatel
>> Date: 2007-03-19 13:55:02 -0700 (Mon, 19 Mar 2007)
>>
>> Log Message:
>> ---
>> Better support for variable size struct fields.
>> Patch by Duncan Sands.
>>
>> Modified Paths:
>> --
>> apple-local/branches/llvm/gcc/llvm-convert.cpp
>> apple-local/branches/llvm/gcc/llvm-types.cpp
>>
>> Modified: apple-local/branches/llvm/gcc/llvm-convert.cpp
>> ===
>> --- apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-03-19
>> 19:06:59 UTC (rev 125159)
>> +++ apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-03-19
>> 20:55:02 UTC (rev 125160)
>> @@ -4660,12 +4660,6 @@
>> assert(DECL_LLVM_SET_P(FieldDecl) && "Struct not laid out for
>> LLVM?");
>> ConstantInt *CI = cast(DECL_LLVM(FieldDecl));
>> uint32_t MemberIndex = CI->getZExtValue();
>> -if (MemberIndex == ~0U) {
>> - assert(isStructWithVarSizeArrayAtEnd(StructTy) &&
>> - "Isn't var sized array access!");
>> - CI = ConstantInt::get(Type::Int32Ty, StructTy-
>> >getNumContainedTypes()-1);
>> - MemberIndex = CI->getZExtValue();
>> -}
>> assert(MemberIndex < StructTy->getNumContainedTypes() &&
>> "Field Idx out of range!");
>> FieldPtr = new GetElementPtrInst(StructAddrLV.Ptr,
>> @@ -5476,35 +5470,32 @@
>>// If not, things are much simpler.
>>assert(DECL_LLVM_SET_P(Field) && "Struct not laid out for
>> LLVM?");
>>unsigned FieldNo = cast(DECL_LLVM(Field))-
>> >getZExtValue();
>> -
>> + assert(FieldNo < ResultElts.size() && "Invalid struct field
>> number!");
>> +
>> + // Example: struct X { int A; char C[]; } x = { 4, "foo" };
>> + assert(TYPE_SIZE(TREE_TYPE(Field)) ||
>> + (FieldNo == ResultElts.size()-1 &&
>> + isStructWithVarSizeArrayAtEnd(STy))
>> + && "field with no size is not array at end of
>> struct!");
>> +
>>// If this is an initialization of a global that ends with
>> a variable
>>// sized array at its end, and the initializer has a non-
>> zero number of
>> - // elements, we must handle this case now. In this case,
>> FieldNo is ~0U
>> - // and Val contains the actual type for the array.
>> - if (FieldNo == ~0U) {
>> -// Handle: struct X { int A; char C[]; } x = { 4, "foo" };
>> -assert(isStructWithVarSizeArrayAtEnd(STy) &&
>> - "Struct doesn't end with variable sized array!");
>> -FieldNo = STy->getNumElements()-1;
>> -ResultElts[FieldNo] = Val;
>> - } else {
>> -assert(FieldNo < ResultElts.size() && "Invalid struct
>> field number!");
>> -
>> -// Otherwise, we know that the initi
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.54 -> 1.55
---
Log message:
Make it illegal to set 0 bits in getHighBitsSet and getLowBitsSet. For that
they should have used the uint64_t constructor. This avoids causing
undefined results via shifts by the word size when the bit width is an
exact multiple of the word size.
---
Diffs of the changes: (+2 -0)
APInt.h |2 ++
1 files changed, 2 insertions(+)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.54 llvm/include/llvm/ADT/APInt.h:1.55
--- llvm/include/llvm/ADT/APInt.h:1.54 Sat Mar 24 18:42:47 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 18:47:58 2007
@@ -355,6 +355,7 @@
/// @brief Get a value with high bits set
static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet) {
assert(hiBitsSet <= numBits && "Too many bits to set!");
+assert(hiBitsSet > 0 && "You must set SOME bits");
uint32_t shiftAmt = numBits - hiBitsSet;
// For small values, return quickly
if (numBits <= APINT_BITS_PER_WORD)
@@ -368,6 +369,7 @@
/// @brief Get a value with low bits set
static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet) {
assert(loBitsSet <= numBits && "Too many bits to set!");
+assert(loBitsSet > 0 && "You must set SOME bits");
uint32_t shiftAmt = numBits - loBitsSet;
// For small values, return quickly
if (numBits <= APINT_BITS_PER_WORD)
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.53 -> 1.54
---
Log message:
In the getBitsSet function, don't optimize for a common case that is
already covered by getLowBitsSet (i.e. when loBits==0). Consequently, remove
the default value for loBits and reorder the arguments to the more natural
loBits, hiBits order. This makes it more clear that this function is for bit
groups in the middle of the bit width and not towards one end or the other.
---
Diffs of the changes: (+2 -4)
APInt.h |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.53 llvm/include/llvm/ADT/APInt.h:1.54
--- llvm/include/llvm/ADT/APInt.h:1.53 Sat Mar 24 18:35:54 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 18:42:47 2007
@@ -336,18 +336,16 @@
/// less than loBit then the set bits "wrap". For example, with
/// parameters (32, 3, 28), you would get 0xF00F.
/// @param numBits the intended bit width of the result
- /// @param hiBit the index of the highest bit set.
/// @param loBit the index of the lowest bit set.
+ /// @param hiBit the index of the highest bit set.
/// @returns An APInt value with the requested bits set.
/// @brief Get a value with a block of bits set.
- static APInt getBitsSet(uint32_t numBits, uint32_t hiBit, uint32_t loBit =
0){
+ static APInt getBitsSet(uint32_t numBits, uint32_t loBit, uint32_t hiBit) {
assert(hiBit < numBits && "hiBit out of range");
assert(loBit < numBits && "loBit out of range");
if (hiBit < loBit)
return getLowBitsSet(numBits, hiBit+1) |
getHighBitsSet(numBits, numBits-loBit+1);
-else if (loBit == 0)
- return getLowBitsSet(numBits, hiBit+1);
return getLowBitsSet(numBits, hiBit-loBit+1).shl(loBit);
}
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Re: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
On Mar 24, 2007, at 4:37 PM, Reid Spencer wrote:
> On Sat, 2007-03-24 at 16:31 -0700, Chris Lattner wrote:
>>>/// @param loBit the index of the lowest bit set.
>>>/// @returns An APInt value with the requested bits set.
>>>/// @brief Get a value with a block of bits set.
>>> - static APInt getBitsSet(uint32_t numBits, uint32_t hiBit,
>>> uint32_t loBit = 0);
>>> + static APInt getBitsSet(uint32_t numBits, uint32_t hiBit,
>>> uint32_t loBit = 0){
>>> +assert(hiBit < numBits && "hiBit out of range");
>>> +assert(loBit < numBits && "loBit out of range");
>>> +if (hiBit < loBit)
>>
>> Hrm? Why would you allow hiBit < loBit? This seems like something
>> that should be asserted against.
>
> Read the definition of the function in the documentation. It allows
> you
> to construct things like:
> 0xFFFF with getBitsSet(32, 8, 24);
Ah, ok, makes sense!
>>> + return getLowBitsSet(numBits, hiBit+1) |
>>> + getHighBitsSet(numBits, numBits-loBit+1);
>>> +else if (loBit == 0)
>>> + return getLowBitsSet(numBits, hiBit+1);
>>
>> Do you need this special case for correctness?
>
> No, I was trying to saves a rather expensive shl for a common case.
> However, I decided that before I wrote getLowBitsSet (which is the
> equivalent). I'll remove that case and the default parameter.
Thanks,
-Chris
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Re: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
On Mar 24, 2007, at 4:36 PM, Reid Spencer wrote:
>/// @brief Get a value with high bits set
>static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet) {
> assert(hiBitsSet <= numBits && "Too many bits to set!");
> -uint32_t mvBits = numBits - hiBitsSet;
> +uint32_t shiftAmt = numBits - hiBitsSet;
> // For small values, return quickly
> if (numBits <= APINT_BITS_PER_WORD)
> + return APInt(numBits, ~0ULL << shiftAmt);
Now we get undefined behavior if hibitsset = 0, no?
-Chris
> +return (~APInt(numBits, 0)).shl(shiftAmt);
>}
>
>/// Constructs an APInt value that has the bottom loBitsSet bits
> set.
> @@ -371,10 +370,11 @@
>/// @brief Get a value with low bits set
>static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet) {
> assert(loBitsSet <= numBits && "Too many bits to set!");
> +uint32_t shiftAmt = numBits - loBitsSet;
> // For small values, return quickly
> if (numBits <= APINT_BITS_PER_WORD)
> - return APInt(numBits, (1ULL << loBitsSet) - 1ULL);
> -return APInt(numBits, 1).shl(loBitsSet) - APInt(numBits, 1);
> + return APInt(numBits, ~0ULL >> shiftAmt);
> +return (~APInt(numBits, 0)).lshr(shiftAmt);
>}
>
>/// The hash value is computed as the sum of the words and the
> bit width.
>
>
>
> ___
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Re: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h
On Mar 22, 2007, at 1:18 PM, Reid Spencer wrote: > On Thu, 2007-03-22 at 12:35 -0700, Jeff Cohen wrote: >> How is it any worse than checking for GCC? > > I don't like that either :) FWIW, I don't see anything wrong with Jeff's change. MathExtras may be suboptimal w.r.t to libsystem, but so is compiler.h and others. I think it's fine for headers/inline functions to violate the libsystem design. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
On Sat, 2007-03-24 at 16:31 -0700, Chris Lattner wrote:
> >/// @param loBit the index of the lowest bit set.
> >/// @returns An APInt value with the requested bits set.
> >/// @brief Get a value with a block of bits set.
> > - static APInt getBitsSet(uint32_t numBits, uint32_t hiBit,
> > uint32_t loBit = 0);
> > + static APInt getBitsSet(uint32_t numBits, uint32_t hiBit,
> > uint32_t loBit = 0){
> > +assert(hiBit < numBits && "hiBit out of range");
> > +assert(loBit < numBits && "loBit out of range");
> > +if (hiBit < loBit)
>
> Hrm? Why would you allow hiBit < loBit? This seems like something
> that should be asserted against.
Read the definition of the function in the documentation. It allows you
to construct things like:
0xFFFF with getBitsSet(32, 8, 24);
>
> > + return getLowBitsSet(numBits, hiBit+1) |
> > + getHighBitsSet(numBits, numBits-loBit+1);
> > +else if (loBit == 0)
> > + return getLowBitsSet(numBits, hiBit+1);
>
> Do you need this special case for correctness?
No, I was trying to saves a rather expensive shl for a common case.
However, I decided that before I wrote getLowBitsSet (which is the
equivalent). I'll remove that case and the default parameter.
>
> -Chris
>
> > +return getLowBitsSet(numBits, hiBit-loBit+1).shl(loBit);
> > + }
> >
> >/// Constructs an APInt value that has the top hiBitsSet bits set.
> >/// @param numBits the bitwidth of the result
> >
> >
> >
> > ___
> > llvm-commits mailing list
> > llvm-commits@cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.52 -> 1.53
---
Log message:
Don't invoke undefined behavior in shifts in the functions getHighBitsSet
and getLowBitsSet.
---
Diffs of the changes: (+6 -6)
APInt.h | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.52 llvm/include/llvm/ADT/APInt.h:1.53
--- llvm/include/llvm/ADT/APInt.h:1.52 Sat Mar 24 18:27:48 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 18:35:54 2007
@@ -357,12 +357,11 @@
/// @brief Get a value with high bits set
static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet) {
assert(hiBitsSet <= numBits && "Too many bits to set!");
-uint32_t mvBits = numBits - hiBitsSet;
+uint32_t shiftAmt = numBits - hiBitsSet;
// For small values, return quickly
if (numBits <= APINT_BITS_PER_WORD)
- return APInt(numBits, ((1ULL << hiBitsSet) - 1) << mvBits);
-APInt Result(numBits, 1);
-return (APInt(numBits, 1).shl(hiBitsSet) - APInt(numBits, 1)).shl(mvBits);
+ return APInt(numBits, ~0ULL << shiftAmt);
+return (~APInt(numBits, 0)).shl(shiftAmt);
}
/// Constructs an APInt value that has the bottom loBitsSet bits set.
@@ -371,10 +370,11 @@
/// @brief Get a value with low bits set
static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet) {
assert(loBitsSet <= numBits && "Too many bits to set!");
+uint32_t shiftAmt = numBits - loBitsSet;
// For small values, return quickly
if (numBits <= APINT_BITS_PER_WORD)
- return APInt(numBits, (1ULL << loBitsSet) - 1ULL);
-return APInt(numBits, 1).shl(loBitsSet) - APInt(numBits, 1);
+ return APInt(numBits, ~0ULL >> shiftAmt);
+return (~APInt(numBits, 0)).lshr(shiftAmt);
}
/// The hash value is computed as the sum of the words and the bit width.
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/README-MMX.txt README-SSE.txt X86ISelLowering.cpp X86InstrMMX.td
On Mar 22, 2007, at 11:43 AM, Bill Wendling wrote:
> +We should compile this:
> +
> +#include
> +
> +void foo(__m128i *A, __m128i *B) {
> + *A = _mm_sll_epi16 (*A, *B);
> +}
> +
> +to:
> +
> +_foo:
> + subl$12, %esp
> + movl16(%esp), %edx
> + movl20(%esp), %eax
> + movdqa (%edx), %xmm1
> + movdqa (%eax), %xmm0
> + psllw %xmm0, %xmm1
> + movdqa %xmm1, (%edx)
> + addl$12, %esp
> + ret
> +
> +not:
> +
> +_foo:
> + movl 8(%esp), %eax
> + movdqa (%eax), %xmm0
> + #IMPLICIT_DEF %eax
> + pinsrw $2, %eax, %xmm0
> + xorl %ecx, %ecx
> + pinsrw $3, %ecx, %xmm0
> + pinsrw $4, %eax, %xmm0
> + pinsrw $5, %ecx, %xmm0
> + pinsrw $6, %eax, %xmm0
> + pinsrw $7, %ecx, %xmm0
> + movl 4(%esp), %eax
> + movdqa (%eax), %xmm1
> + psllw %xmm0, %xmm1
> + movdqa %xmm1, (%eax)
> + ret
This looks like a *serious* SSE performance bug, not a missing
feature. Bill, can you look into this? Evan, can you help him if
needed?
Thanks,
-Chris
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Re: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
>/// @param loBit the index of the lowest bit set.
>/// @returns An APInt value with the requested bits set.
>/// @brief Get a value with a block of bits set.
> - static APInt getBitsSet(uint32_t numBits, uint32_t hiBit,
> uint32_t loBit = 0);
> + static APInt getBitsSet(uint32_t numBits, uint32_t hiBit,
> uint32_t loBit = 0){
> +assert(hiBit < numBits && "hiBit out of range");
> +assert(loBit < numBits && "loBit out of range");
> +if (hiBit < loBit)
Hrm? Why would you allow hiBit < loBit? This seems like something
that should be asserted against.
> + return getLowBitsSet(numBits, hiBit+1) |
> + getHighBitsSet(numBits, numBits-loBit+1);
> +else if (loBit == 0)
> + return getLowBitsSet(numBits, hiBit+1);
Do you need this special case for correctness?
-Chris
> +return getLowBitsSet(numBits, hiBit-loBit+1).shl(loBit);
> + }
>
>/// Constructs an APInt value that has the top hiBitsSet bits set.
>/// @param numBits the bitwidth of the result
>
>
>
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.51 -> 1.52
---
Log message:
Implement the getBitsSet function.
---
Diffs of the changes: (+10 -1)
APInt.h | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.51 llvm/include/llvm/ADT/APInt.h:1.52
--- llvm/include/llvm/ADT/APInt.h:1.51 Sat Mar 24 18:05:35 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 18:27:48 2007
@@ -340,7 +340,16 @@
/// @param loBit the index of the lowest bit set.
/// @returns An APInt value with the requested bits set.
/// @brief Get a value with a block of bits set.
- static APInt getBitsSet(uint32_t numBits, uint32_t hiBit, uint32_t loBit =
0);
+ static APInt getBitsSet(uint32_t numBits, uint32_t hiBit, uint32_t loBit =
0){
+assert(hiBit < numBits && "hiBit out of range");
+assert(loBit < numBits && "loBit out of range");
+if (hiBit < loBit)
+ return getLowBitsSet(numBits, hiBit+1) |
+ getHighBitsSet(numBits, numBits-loBit+1);
+else if (loBit == 0)
+ return getLowBitsSet(numBits, hiBit+1);
+return getLowBitsSet(numBits, hiBit-loBit+1).shl(loBit);
+ }
/// Constructs an APInt value that has the top hiBitsSet bits set.
/// @param numBits the bitwidth of the result
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
> @@ -2961,11 +2961,10 @@
>if (CI->isAllOnesValue()) // X * -1 == 0 - X
> return BinaryOperator::createNeg(Op0, I.getName());
>
> - int64_t Val = (int64_t)cast(CI)->getZExtValue();
> - if (isPowerOf2_64(Val)) { // Replace X*(2^C) with X
> << C
> -uint64_t C = Log2_64(Val);
> + APInt Val(cast(CI)->getValue());
In this case, Val is just a shorter way to refer to the APInt in CI,
you don't ever modify Val itself. In this case, just use a const
reference, to avoid copying the APInt. Likewise in many places.
Copying an APInt is far more expensive than copying a uint64_t.
> @@ -3427,7 +3424,7 @@
>
>if (Value *RHSNeg = dyn_castNegVal(Op1))
> if (!isa(RHSNeg) ||
> -cast(RHSNeg)->getSExtValue() > 0) {
> +cast(RHSNeg)->getValue().isPositive()) {
This is a bug, you want isStrictlyPositive(), please fix ASAP.
-Chris
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Re: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
> Implement the getHighBitsSet and getLowBitsSet functions.
>/// @param numBits the bitwidth of the result
>/// @param hiBitsSet the number of high-order bits set in the
> result.
>/// @brief Get a value with high bits set
> - static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet);
> + static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet) {
> +assert(hiBitsSet <= numBits && "Too many bits to set!");
> +uint32_t mvBits = numBits - hiBitsSet;
> +// For small values, return quickly
> +if (numBits <= APINT_BITS_PER_WORD)
> + return APInt(numBits, ((1ULL << hiBitsSet) - 1) << mvBits);
If hiBitsSet == numBIts == 64, this invokes undefined behavior.
> +APInt Result(numBits, 1);
> +return (APInt(numBits, 1).shl(hiBitsSet) - APInt(numBits,
> 1)).shl(mvBits);
likewise.
> + }
>
>/// Constructs an APInt value that has the bottom loBitsSet bits
> set.
>/// @param numBits the bitwidth of the result
>/// @param loBitsSet the number of low-order bits set in the
> result.
>/// @brief Get a value with low bits set
> - static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet);
> + static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet) {
> +assert(loBitsSet <= numBits && "Too many bits to set!");
> +// For small values, return quickly
> +if (numBits <= APINT_BITS_PER_WORD)
> + return APInt(numBits, (1ULL << loBitsSet) - 1ULL);
> +return APInt(numBits, 1).shl(loBitsSet) - APInt(numBits, 1);
likewise.
-Chris
> + }
>
>/// The hash value is computed as the sum of the words and the
> bit width.
>/// @returns A hash value computed from the sum of the APInt words.
>
>
>
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Re: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/APInt/
On Mar 24, 2007, at 4:05 PM, Reid Spencer wrote: > On Sat, 2007-03-24 at 15:56 -0700, Chris Lattner wrote: This is a temporary convenience while you're working on apint'ifying instcombine. This will not be useful once you're done. >>> >>> Okay, that's fine. Could you please copy all the ,v files from the >>> InstCombine/APInt files up one level, being sure not to overwrite >>> any >>> existing ones of the same name. If you want to rename them all >>> with a >>> -apint suffix, that would be fine. I'll do the rest after the ,v >>> files >>> are copied. > > You moved them again. Are you purposely trying to make the SVN > migration > harder? ;> How does that make svn migration harder in this case? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Mar 23, 2007, at 11:46 AM, Reid Spencer wrote:
>// shl uint X, 32 = 0 and shr ubyte Y, 9 = 0, ... just don't
> eliminate shr
>// of a signed value.
>//
> - unsigned TypeBits = Op0->getType()->getPrimitiveSizeInBits();
> - if (Op1->getZExtValue() >= TypeBits) {
> + if (Op1->getZExtValue() >= TypeBits) { // shift amount always
> <= 32 bits
This isn't safe. Code like:
shl i1024 %A, 123456789123456789123456789123456789
is undefined but legal. The compiler should not crash on it.
> @@ -6462,8 +6460,8 @@
> // operation.
> //
> if (isValid && !isLeftShift && I.getOpcode() ==
> Instruction::AShr) {
> - uint64_t Val = Op0C->getZExtValue();
> - isValid = ((Val & (1 << (TypeBits-1))) != 0) == highBitSet;
> + APInt Val(Op0C->getValue());
> + isValid = ((Val & APInt::getSignBit(TypeBits)) != 0) ==
> highBitSet;
> }
This should use operator[] to get the sign bit, or use isPositive/
isNegative.
>
> if (isValid) {
> @@ -6488,6 +6486,7 @@
>
>if (ShiftOp && isa(ShiftOp->getOperand(1))) {
> ConstantInt *ShiftAmt1C = cast(ShiftOp->getOperand
> (1));
> +// shift amount always <= 32 bits
Likewise, not safe.
> unsigned ShiftAmt1 = (unsigned)ShiftAmt1C->getZExtValue();
> unsigned ShiftAmt2 = (unsigned)Op1->getZExtValue();
> assert(ShiftAmt2 != 0 && "Should have been simplified earlier");
> @@ -6515,8 +6514,8 @@
> BinaryOperator::createAShr(X, ConstantInt::get(Ty, AmtSum));
>InsertNewInstBefore(Shift, I);
>
> - uint64_t Mask = Ty->getBitMask() >> ShiftAmt2;
> - return BinaryOperator::createAnd(Shift, ConstantInt::get(Ty,
> Mask));
> + APInt Mask(APInt::getAllOnesValue(TypeBits).lshr(ShiftAmt2));
> + return BinaryOperator::createAnd(Shift, ConstantInt::get
> (Mask));
> }
One of many places that need to use the new methods.
> @@ -6538,9 +6537,12 @@
>// generators.
>const Type *SExtType = 0;
>switch (Ty->getBitWidth() - ShiftAmt1) {
> - case 8 : SExtType = Type::Int8Ty; break;
> - case 16: SExtType = Type::Int16Ty; break;
> - case 32: SExtType = Type::Int32Ty; break;
> + case 1 : SExtType = Type::Int1Ty; break;
> + case 8 : SExtType = Type::Int8Ty; break;
> + case 16 : SExtType = Type::Int16Ty; break;
> + case 32 : SExtType = Type::Int32Ty; break;
> + case 64 : SExtType = Type::Int64Ty; break;
> + case 128: SExtType = IntegerType::get(128); break;
>default: break;
It would be more efficient (code size) to do:
switch (Ty->getBitWidth() - ShiftAmt1) {
case 1:
case 8:
case 16:
case 32:
case 64:
case 128:
SExtType = IntegerType::get(Ty->getBitWidth() - ShiftAmt1);
break;
default: break;
> @@ -8191,7 +8193,7 @@
>(ParamTy->isInteger() && ActTy->isInteger() &&
> ParamTy->getPrimitiveSizeInBits() >= ActTy-
> >getPrimitiveSizeInBits()) ||
>(c && ParamTy->getPrimitiveSizeInBits() >= ActTy-
> >getPrimitiveSizeInBits()
> - && c->getSExtValue() > 0);
> + && c->getValue().isPositive());
Doesn't isPositive return true for zero also? If so, this is a bug.
-Chris
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[llvm-commits] CVS: llvm/test/Transforms/InstCombine/APInt/.cvsignore dg.exp
Changes in directory llvm/test/Transforms/InstCombine/APInt: .cvsignore (r1.1) removed dg.exp (r1.1) removed --- Log message: Remove the last vestiges of this directory. --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/APInt/
On Sat, 2007-03-24 at 15:56 -0700, Chris Lattner wrote: > >> This is a temporary convenience while you're working on apint'ifying > >> instcombine. This will not be useful once you're done. > > > > Okay, that's fine. Could you please copy all the ,v files from the > > InstCombine/APInt files up one level, being sure not to overwrite any > > existing ones of the same name. If you want to rename them all with a > > -apint suffix, that would be fine. I'll do the rest after the ,v > > files > > are copied. You moved them again. Are you purposely trying to make the SVN migration harder? ;> > > Done, thx. > > -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.50 -> 1.51
---
Log message:
Implement the getHighBitsSet and getLowBitsSet functions.
---
Diffs of the changes: (+16 -2)
APInt.h | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.50 llvm/include/llvm/ADT/APInt.h:1.51
--- llvm/include/llvm/ADT/APInt.h:1.50 Sat Mar 24 17:50:43 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 18:05:35 2007
@@ -346,13 +346,27 @@
/// @param numBits the bitwidth of the result
/// @param hiBitsSet the number of high-order bits set in the result.
/// @brief Get a value with high bits set
- static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet);
+ static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet) {
+assert(hiBitsSet <= numBits && "Too many bits to set!");
+uint32_t mvBits = numBits - hiBitsSet;
+// For small values, return quickly
+if (numBits <= APINT_BITS_PER_WORD)
+ return APInt(numBits, ((1ULL << hiBitsSet) - 1) << mvBits);
+APInt Result(numBits, 1);
+return (APInt(numBits, 1).shl(hiBitsSet) - APInt(numBits, 1)).shl(mvBits);
+ }
/// Constructs an APInt value that has the bottom loBitsSet bits set.
/// @param numBits the bitwidth of the result
/// @param loBitsSet the number of low-order bits set in the result.
/// @brief Get a value with low bits set
- static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet);
+ static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet) {
+assert(loBitsSet <= numBits && "Too many bits to set!");
+// For small values, return quickly
+if (numBits <= APINT_BITS_PER_WORD)
+ return APInt(numBits, (1ULL << loBitsSet) - 1ULL);
+return APInt(numBits, 1).shl(loBitsSet) - APInt(numBits, 1);
+ }
/// The hash value is computed as the sum of the words and the bit width.
/// @returns A hash value computed from the sum of the APInt words.
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Re: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/APInt/
>> This is a temporary convenience while you're working on apint'ifying >> instcombine. This will not be useful once you're done. > > Okay, that's fine. Could you please copy all the ,v files from the > InstCombine/APInt files up one level, being sure not to overwrite any > existing ones of the same name. If you want to rename them all with a > -apint suffix, that would be fine. I'll do the rest after the ,v > files > are copied. Done, thx. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
> @@ -4373,9 +4374,10 @@ > >// See if we can simplify any instructions used by the > instruction whose sole >// purpose is to compute bits we don't care about. > - uint64_t KnownZero, KnownOne; > + uint32_t BitWidth = cast(I.getType())->getBitWidth(); This is an important regression for vectors. And/Or/Xor do apply to VectorType and Integer types. Please fix ASAP, by moving this into the !isa clause. > + APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); >if (!isa(I.getType()) && > - SimplifyDemandedBits(&I, cast(I.getType())- > >getBitMask(), > + SimplifyDemandedBits(&I, APInt::getAllOnesValue(BitWidth), > KnownZero, KnownOne)) > return &I; > -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT: APInt.h updated: 1.49 -> 1.50 --- Log message: Get the signs in the right place! --- Diffs of the changes: (+1 -1) APInt.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/ADT/APInt.h diff -u llvm/include/llvm/ADT/APInt.h:1.49 llvm/include/llvm/ADT/APInt.h:1.50 --- llvm/include/llvm/ADT/APInt.h:1.49 Sat Mar 24 17:37:23 2007 +++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 17:50:43 2007 @@ -568,7 +568,7 @@ if (RHS.isNegative()) return -((-(*this)).urem(-RHS)); else -return -(-(*this)).urem(RHS); +return -((-(*this)).urem(RHS)); else if (RHS.isNegative()) return this->urem(-RHS); return this->urem(RHS); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Mar 22, 2007, at 1:57 PM, Reid Spencer wrote:
> @@ -7008,10 +7008,8 @@
>case Instruction::ZExt: {
> // We need to emit an AND to clear the high bits.
> assert(SrcBitSize < DestBitSize && "Not a zext?");
> -Constant *C =
> - ConstantInt::get(Type::Int64Ty, (1ULL << SrcBitSize)-1);
> -if (DestBitSize < 64)
> - C = ConstantExpr::getTrunc(C, DestTy);
> +Constant *C = ConstantInt::get(APInt::getAllOnesValue
> (SrcBitSize));
> +C = ConstantExpr::getZExt(C, DestTy);
This should be done with APInt's, not with ConstantExpr.
> return BinaryOperator::createAnd(Res, C);
>}
>case Instruction::SExt:
> @@ -7190,7 +7190,8 @@
> unsigned ShAmt = ShAmtV->getZExtValue();
>
> // Get a mask for the bits shifting in.
> -uint64_t Mask = (~0ULL >> (64-ShAmt)) << DestBitWidth;
> +APInt Mask(APInt::getAllOnesValue(SrcBitWidth).lshr(
> + SrcBitWidth-ShAmt).shl(DestBitWidth));
Please use the new methods.
> Value* SrcIOp0 = SrcI->getOperand(0);
> if (SrcI->hasOneUse() && MaskedValueIsZero(SrcIOp0, Mask)) {
>if (ShAmt >= DestBitWidth)// All zeros.
> @@ -7249,8 +7250,8 @@
>// If we're actually extending zero bits and the trunc is a
> no-op
>if (MidSize < DstSize && SrcSize == DstSize) {
> // Replace both of the casts with an And of the type mask.
> -uint64_t AndValue = cast(CSrc->getType())-
> >getBitMask();
> -Constant *AndConst = ConstantInt::get(A->getType(),
> AndValue);
> +APInt AndValue(APInt::getAllOnesValue(MidSize).zext
> (SrcSize));
> +Constant *AndConst = ConstantInt::get(AndValue);
Likewise
-Chris
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[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.215 -> 1.216 --- Log message: Fix a link. --- Diffs of the changes: (+2 -2) LangRef.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.215 llvm/docs/LangRef.html:1.216 --- llvm/docs/LangRef.html:1.215Sat Mar 24 17:23:39 2007 +++ llvm/docs/LangRef.html Sat Mar 24 17:40:44 2007 @@ -2011,7 +2011,7 @@ a value. For more information about the difference, see http://mathforum.org/dr.math/problems/anne.4.28.99.html";>The Math Forum. For a table of how this is implemented in various languages, -please see http://mathforum.org/dr.math/problems/anne.4.28.99.html";> +please see http://en.wikipedia.org/wiki/Modulo_operation";> Wikipedia: modulo operation. Example:= srem i32 4, %var ; yields {i32}:result = 4 % %var @@ -4612,7 +4612,7 @@ mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2007/03/24 22:23:39 $ + Last modified: $Date: 2007/03/24 22:40:44 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT: APInt.h updated: 1.48 -> 1.49 --- Log message: Undo the last change and make this really implement remainder and not modulus. The previous change was a result of incorrect documentation in the LangRef.html. --- Diffs of the changes: (+6 -4) APInt.h | 10 ++ 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/include/llvm/ADT/APInt.h diff -u llvm/include/llvm/ADT/APInt.h:1.48 llvm/include/llvm/ADT/APInt.h:1.49 --- llvm/include/llvm/ADT/APInt.h:1.48 Sat Mar 24 16:56:22 2007 +++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 17:37:23 2007 @@ -552,9 +552,11 @@ return this->udiv(RHS); } - /// Perform an Unsigned remainder operation on this APInt with RHS being the + /// Perform an unsigned remainder operation on this APInt with RHS being the /// divisor. Both this and RHS are treated as unsigned quantities for purposes - /// of this operation. + /// of this operation. Note that this is a true remainder operation and not + /// a modulo operation because the sign follows the sign of the dividend + /// which is *this. /// @returns a new APInt value containing the remainder result /// @brief Unsigned remainder operation. APInt urem(const APInt& RHS) const; @@ -566,9 +568,9 @@ if (RHS.isNegative()) return -((-(*this)).urem(-RHS)); else -return (-(*this)).urem(RHS); +return -(-(*this)).urem(RHS); else if (RHS.isNegative()) - return -(this->urem(-RHS)); + return this->urem(-RHS); return this->urem(RHS); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Integer/a15.ll.out a17.ll.out a31.ll.out a33.ll.out a63.ll.out a7.ll.out a9.ll.out
Changes in directory llvm/test/Integer: a15.ll.out updated: 1.6 -> 1.7 a17.ll.out updated: 1.6 -> 1.7 a31.ll.out updated: 1.6 -> 1.7 a33.ll.out updated: 1.6 -> 1.7 a63.ll.out updated: 1.6 -> 1.7 a7.ll.out updated: 1.7 -> 1.8 a9.ll.out updated: 1.6 -> 1.7 --- Log message: Flip the srem tests around. Previous commit was to correct an apparent bug in the srem implementation. Turns out it was a documentation bug instead. --- Diffs of the changes: (+11 -11) a15.ll.out |4 ++-- a17.ll.out |4 ++-- a31.ll.out |4 ++-- a33.ll.out |4 ++-- a63.ll.out |2 +- a7.ll.out |2 +- a9.ll.out |2 +- 7 files changed, 11 insertions(+), 11 deletions(-) Index: llvm/test/Integer/a15.ll.out diff -u llvm/test/Integer/a15.ll.out:1.6 llvm/test/Integer/a15.ll.out:1.7 --- llvm/test/Integer/a15.ll.out:1.6Sat Mar 24 16:55:26 2007 +++ llvm/test/Integer/a15.ll.outSat Mar 24 17:34:10 2007 @@ -13,10 +13,10 @@ @q = constant i15 16381; [#uses=0] @r = constant i15 0; [#uses=0] @s = constant i15 2; [#uses=0] [EMAIL PROTECTED] = constant i15 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i15 1 ; [#uses=0] @u = constant i15 0; [#uses=0] @o = constant i15 0; [#uses=0] @p = constant i15 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i15 1 ; [#uses=0] [EMAIL PROTECTED] = constant i15 -1 ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a17.ll.out diff -u llvm/test/Integer/a17.ll.out:1.6 llvm/test/Integer/a17.ll.out:1.7 --- llvm/test/Integer/a17.ll.out:1.6Sat Mar 24 16:55:26 2007 +++ llvm/test/Integer/a17.ll.outSat Mar 24 17:34:10 2007 @@ -12,10 +12,10 @@ @n = constant i17 -2 ; [#uses=0] @q = constant i17 0; [#uses=0] @r = constant i17 2; [#uses=0] [EMAIL PROTECTED] = constant i17 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i17 1 ; [#uses=0] @t = constant i17 0; [#uses=0] @o = constant i17 0; [#uses=0] @p = constant i17 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i17 1 ; [#uses=0] [EMAIL PROTECTED] = constant i17 -1 ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a31.ll.out diff -u llvm/test/Integer/a31.ll.out:1.6 llvm/test/Integer/a31.ll.out:1.7 --- llvm/test/Integer/a31.ll.out:1.6Sat Mar 24 16:55:26 2007 +++ llvm/test/Integer/a31.ll.outSat Mar 24 17:34:10 2007 @@ -12,10 +12,10 @@ @n = constant i31 -2 ; [#uses=0] @q = constant i31 0; [#uses=0] @r = constant i31 2; [#uses=0] [EMAIL PROTECTED] = constant i31 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i31 1 ; [#uses=0] @t = constant i31 0; [#uses=0] @o = constant i31 0; [#uses=0] @p = constant i31 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i31 3 ; [#uses=0] [EMAIL PROTECTED] = constant i31 -3 ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a33.ll.out diff -u llvm/test/Integer/a33.ll.out:1.6 llvm/test/Integer/a33.ll.out:1.7 --- llvm/test/Integer/a33.ll.out:1.6Sat Mar 24 16:55:26 2007 +++ llvm/test/Integer/a33.ll.outSat Mar 24 17:34:10 2007 @@ -12,10 +12,10 @@ @n = constant i33 -2 ; [#uses=0] @q = constant i33 0; [#uses=0] @r = constant i33 2; [#uses=0] [EMAIL PROTECTED] = constant i33 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i33 1 ; [#uses=0] @t = constant i33 0; [#uses=0] @o = constant i33 0; [#uses=0] @p = constant i33 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i33 1 ; [#uses=0] [EMAIL PROTECTED] = constant i33 -1 ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a63.ll.out diff -u llvm/test/Integer/a63.ll.out:1.6 llvm/test/Integer/a63.ll.out:1.7 --- llvm/test/Integer/a63.ll.out:1.6Sat Mar 24 16:55:26 2007 +++ llvm/test/Integer/a63.ll.outSat Mar 24 17:34:10 2007 @@ -13,7 +13,7 @@ @q = constant i63 0; [#uses=0] @u = constant i63 -1 ; [#uses=0] @r = constant i63 2; [#uses=0] [EMAIL PROTECTED] = constant i63 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i63 1 ; [#uses=0] @t = constant i63 0; [#uses=0] @o = constant i63 0; [#uses=0] @p = constant i63 -1 ; [#uses=0] Index: llvm/test/Integer/a7.ll.out diff -u llvm/test/Integer/a7.ll.out:1.7 llvm/test/Integer/a7.ll.out:1.8 --- llvm/test/Integer/a7.ll.out:1.7 Sat Mar 24 16:55:26 2007 +++ llvm/test/Integer/a7.ll.out Sat Mar 24 17:34:10 2007 @@ -18,7 +18,7 @@ @u = constant i7 -64 ; [#uses=0] @v = constant i7 0 ; [#uses=0] @w = constant i7 2 ; [#uses=0] [EMAIL PROTECTED] = constant i7 -1
Re: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/APInt/
On Sat, 2007-03-24 at 15:26 -0700, Chris Lattner wrote: > >> Hrm? Why a subdirectory? > > > > Three reasons: > > 1. Many of the tests are similar but just modified for APInt. So > > instead > > of having > >sext-apint.ll and zext-apint.ll and or-apint.ll, etc., I just > > factored the name > >out into a directory. Also reduces clutter in the > > test/Transforms/InstCombine > >directory. > > the is no logical difference between apint tests and non-apint tests > for instcombine. If you want to include apint in the filename, > that's fine, but I don't think a directory is useful. > > > 2. To allow "make check TESTSUITE=test/Transforms/InstCombine/ > > APInt" to > > just check > >the APInt versions of these tests. > > This is a temporary convenience while you're working on apint'ifying > instcombine. This will not be useful once you're done. Okay, that's fine. Could you please copy all the ,v files from the InstCombine/APInt files up one level, being sure not to overwrite any existing ones of the same name. If you want to rename them all with a -apint suffix, that would be fine. I'll do the rest after the ,v files are copied. Thanks, Reid. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/APInt/
>> Hrm? Why a subdirectory? > > Three reasons: > 1. Many of the tests are similar but just modified for APInt. So > instead > of having >sext-apint.ll and zext-apint.ll and or-apint.ll, etc., I just > factored the name >out into a directory. Also reduces clutter in the > test/Transforms/InstCombine >directory. the is no logical difference between apint tests and non-apint tests for instcombine. If you want to include apint in the filename, that's fine, but I don't think a directory is useful. > 2. To allow "make check TESTSUITE=test/Transforms/InstCombine/ > APInt" to > just check >the APInt versions of these tests. This is a temporary convenience while you're working on apint'ifying instcombine. This will not be useful once you're done. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.214 -> 1.215 --- Log message: Correct the description of srem. remainder follows the dividend not the divisor! --- Diffs of the changes: (+7 -5) LangRef.html | 12 +++- 1 files changed, 7 insertions(+), 5 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.214 llvm/docs/LangRef.html:1.215 --- llvm/docs/LangRef.html:1.214Wed Mar 21 21:18:56 2007 +++ llvm/docs/LangRef.html Sat Mar 24 17:23:39 2007 @@ -2006,11 +2006,13 @@ types. Semantics: This instruction returns the remainder of a division (where the result -has the same sign as the divisor), not the modulus (where the -result has the same sign as the dividend) of a value. For more -information about the difference, see var1), not the modulo +operator (where the result has the same sign as the divisor, var2) of +a value. For more information about the difference, see http://mathforum.org/dr.math/problems/anne.4.28.99.html";>The -Math Forum. +Math Forum. For a table of how this is implemented in various languages, +please see http://mathforum.org/dr.math/problems/anne.4.28.99.html";> +Wikipedia: modulo operation. Example:= srem i32 4, %var ; yields {i32}:result = 4 % %var @@ -4610,7 +4612,7 @@ mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2007/03/22 02:18:56 $ + Last modified: $Date: 2007/03/24 22:23:39 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/test/Integer/a1.ll a1.ll.out a15.ll a15.ll.out a17.ll a17.ll.out a31.ll a31.ll.out a33.ll a33.ll.out a63.ll.out a7.ll.out a9.ll.out
Hi Duncan, On Sat, 2007-03-24 at 23:10 +0100, Duncan Sands wrote: > > Fix incorrect test cases for srem. The definition of srem is a remainder so > > that the sign of the result follows the sign of the divisor. > > In "A rem B", I hope you mean A when you talk of the divisor! > Because > A rem B has the sign of A (unless B exactly divides A, in which case the > sign is zero). There is what is also called "mod" which differs in that > A mod B has the sign of B. In gcc, mod is called FLOOR_MOD_EXPR and > rem is called TRUNC_MOD_EXPR. When I implemented FLOOR_MOD_EXPR in > turns of rem, I checked that LLVM's rem operator behaves as I describe > above. Thanks for pointing this out. I have just implemented it entirely backwards, because the silly LangRef.html says divisor instead of dividend. I believe we wanted remainder and not modulo here. According to: http://en.wikipedia.org/wiki/Modulo_operation, that means the sign goes with the dividend, not the divisor. Thanks for noticing. I'll fix immediately. Reid. > > Ciao, > > Duncan. > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits signature.asc Description: This is a digitally signed message part ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
>>> Make some codes more efficient.
>>>
>>> @@ -5813,7 +5816,6 @@
>>>case 16 : SExtType = Type::Int16Ty; break;
>>>case 32 : SExtType = Type::Int32Ty; break;
>>>case 64 : SExtType = Type::Int64Ty; break;
>>> - case 128: SExtType = IntegerType::get(128); break;
>>>default: break;
>>>}
>>>if (SExtType) {
>>
>> why did you remove this?
>
> I asked Sheng to remove it because the back ends cannot deal with 128
> bit integers.
There is partial support already in place, and at some point, it
should be extended. See, for example:
CodeGen/Generic/i128-arith.ll
which works on all targets with the native codegen.
>>> @@ -5833,7 +5835,7 @@
>>>BinaryOperator::createShl(X, ConstantInt::get(Ty,
>>> ShiftDiff));
>>> InsertNewInstBefore(Shift, I);
>>>
>>> -APInt Mask(APInt::getAllOnesValue(TypeBits).shl
>>> (ShiftAmt2));
>>> +APInt Mask(Ty->getMask().shl(ShiftAmt2));
>>
>> You touched many instances of this. Please make a new
>> APInt::getHighBits method.
>
> The method getHiBits already exists and is used to extrat the N hi
> bits
> from an existing APInt, not construct a new value. I have just
> committed
> a re-organization of the APInt interface (mostly for documentation
> purposes) but while I was at it I added three new functions that
> should
> address this need:
Nice.
-Chris
>
> /// Constructs an APInt value that has a contiguous range of bits
> set.
> The
> /// bits from loBit to hiBit will be set. All other bits will be
> zero.
> For
> /// example, with parameters(32, 15, 0) you would get 0x. If
> hiBit is
> /// less than loBit then the set bits "wrap". For example, with
> /// parameters (32, 3, 28), you would get 0xF00F.
> /// @param numBits the intended bit width of the result
> /// @param hiBit the index of the highest bit set.
> /// @param loBit the index of the lowest bit set.
> /// @returns An APInt value with the requested bits set.
> /// @brief Get a value with a block of bits set.
> static APInt getBitsSet(uint32_t numBits, uint32_t hiBit, uint32_t
> loBit = 0);
>
> /// Constructs an APInt value that has the top hiBitsSet bits set.
> /// @param numBits the bitwidth of the result
> /// @param hiBitsSet the number of high-order bits set in the
> result.
> /// @brief Get a value with high bits set
> static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet);
>
> /// Constructs an APInt value that has the bottom loBitsSet bits
> set.
> /// @param numBits the bitwidth of the result
> /// @param loBitsSet the number of low-order bits set in the result.
> /// @brief Get a value with low bits set
> static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet);
>
> Reid.
>
>>
>> -Chris
>> ___
>> llvm-commits mailing list
>> llvm-commits@cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
___
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Re: [llvm-commits] CVS: llvm/test/Integer/a1.ll a1.ll.out a15.ll a15.ll.out a17.ll a17.ll.out a31.ll a31.ll.out a33.ll a33.ll.out a63.ll.out a7.ll.out a9.ll.out
> Fix incorrect test cases for srem. The definition of srem is a remainder so > that the sign of the result follows the sign of the divisor. In "A rem B", I hope you mean A when you talk of the divisor! Because A rem B has the sign of A (unless B exactly divides A, in which case the sign is zero). There is what is also called "mod" which differs in that A mod B has the sign of B. In gcc, mod is called FLOOR_MOD_EXPR and rem is called TRUNC_MOD_EXPR. When I implemented FLOOR_MOD_EXPR in turns of rem, I checked that LLVM's rem operator behaves as I describe above. Ciao, Duncan. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.47 -> 1.48
---
Log message:
Correct the implementation of srem to be remainder, not modulus. The sign of
the result must follow the sign of the divisor.
---
Diffs of the changes: (+2 -2)
APInt.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.47 llvm/include/llvm/ADT/APInt.h:1.48
--- llvm/include/llvm/ADT/APInt.h:1.47 Sat Mar 24 13:09:18 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 16:56:22 2007
@@ -564,9 +564,9 @@
inline APInt srem(const APInt& RHS) const {
if (isNegative())
if (RHS.isNegative())
-return (-(*this)).urem(-RHS);
+return -((-(*this)).urem(-RHS));
else
-return -((-(*this)).urem(RHS));
+return (-(*this)).urem(RHS);
else if (RHS.isNegative())
return -(this->urem(-RHS));
return this->urem(RHS);
___
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[llvm-commits] CVS: llvm/test/Integer/a1.ll a1.ll.out a15.ll a15.ll.out a17.ll a17.ll.out a31.ll a31.ll.out a33.ll a33.ll.out a63.ll.out a7.ll.out a9.ll.out
Changes in directory llvm/test/Integer: a1.ll updated: 1.6 -> 1.7 a1.ll.out updated: 1.5 -> 1.6 a15.ll updated: 1.5 -> 1.6 a15.ll.out updated: 1.5 -> 1.6 a17.ll updated: 1.5 -> 1.6 a17.ll.out updated: 1.5 -> 1.6 a31.ll updated: 1.5 -> 1.6 a31.ll.out updated: 1.5 -> 1.6 a33.ll updated: 1.5 -> 1.6 a33.ll.out updated: 1.5 -> 1.6 a63.ll.out updated: 1.5 -> 1.6 a7.ll.out updated: 1.6 -> 1.7 a9.ll.out updated: 1.5 -> 1.6 --- Log message: Fix incorrect test cases for srem. The definition of srem is a remainder so that the sign of the result follows the sign of the divisor. --- Diffs of the changes: (+19 -9) a1.ll |1 + a1.ll.out |1 + a15.ll |1 + a15.ll.out |3 ++- a17.ll |1 + a17.ll.out |3 ++- a31.ll |3 ++- a31.ll.out |3 ++- a33.ll |3 ++- a33.ll.out |3 ++- a63.ll.out |2 +- a7.ll.out |2 +- a9.ll.out |2 +- 13 files changed, 19 insertions(+), 9 deletions(-) Index: llvm/test/Integer/a1.ll diff -u llvm/test/Integer/a1.ll:1.6 llvm/test/Integer/a1.ll:1.7 --- llvm/test/Integer/a1.ll:1.6 Tue Feb 27 13:26:40 2007 +++ llvm/test/Integer/a1.ll Sat Mar 24 16:55:26 2007 @@ -22,3 +22,4 @@ @r = constant i1 udiv(i1 1, i1 -1) @s = constant i1 srem(i1 -1, i1 1) ; overflow @t = constant i1 urem(i1 -1, i1 1) [EMAIL PROTECTED] = constant i1 srem(i1 1, i1 -1) ; overflow Index: llvm/test/Integer/a1.ll.out diff -u llvm/test/Integer/a1.ll.out:1.5 llvm/test/Integer/a1.ll.out:1.6 --- llvm/test/Integer/a1.ll.out:1.5 Tue Feb 27 13:26:40 2007 +++ llvm/test/Integer/a1.ll.out Sat Mar 24 16:55:26 2007 @@ -16,5 +16,6 @@ @r = constant i1 true ; [#uses=0] @s = constant i1 srem (i1 true, i1 true) ; [#uses=0] @t = constant i1 false ; [#uses=0] [EMAIL PROTECTED] = constant i1 srem (i1 true, i1 true) ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a15.ll diff -u llvm/test/Integer/a15.ll:1.5 llvm/test/Integer/a15.ll:1.6 --- llvm/test/Integer/a15.ll:1.5Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a15.llSat Mar 24 16:55:26 2007 @@ -23,4 +23,5 @@ @u = constant i15 urem(i15 32767,i15 -1) @o = constant i15 trunc( i16 32768 to i15 ) @p = constant i15 trunc( i16 32767 to i15 ) [EMAIL PROTECTED] = constant i15 srem(i15 -1,i15 768) Index: llvm/test/Integer/a15.ll.out diff -u llvm/test/Integer/a15.ll.out:1.5 llvm/test/Integer/a15.ll.out:1.6 --- llvm/test/Integer/a15.ll.out:1.5Tue Feb 27 13:22:36 2007 +++ llvm/test/Integer/a15.ll.outSat Mar 24 16:55:26 2007 @@ -13,9 +13,10 @@ @q = constant i15 16381; [#uses=0] @r = constant i15 0; [#uses=0] @s = constant i15 2; [#uses=0] [EMAIL PROTECTED] = constant i15 1 ; [#uses=0] [EMAIL PROTECTED] = constant i15 -1 ; [#uses=0] @u = constant i15 0; [#uses=0] @o = constant i15 0; [#uses=0] @p = constant i15 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i15 1 ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a17.ll diff -u llvm/test/Integer/a17.ll:1.5 llvm/test/Integer/a17.ll:1.6 --- llvm/test/Integer/a17.ll:1.5Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a17.llSat Mar 24 16:55:26 2007 @@ -22,3 +22,4 @@ @t = constant i17 urem(i17 131071,i17 -1) @o = constant i17 trunc( i18 131072 to i17 ) @p = constant i17 trunc( i18 131071 to i17 ) [EMAIL PROTECTED] = constant i17 srem(i17 -1,i17 15) Index: llvm/test/Integer/a17.ll.out diff -u llvm/test/Integer/a17.ll.out:1.5 llvm/test/Integer/a17.ll.out:1.6 --- llvm/test/Integer/a17.ll.out:1.5Tue Feb 27 13:22:36 2007 +++ llvm/test/Integer/a17.ll.outSat Mar 24 16:55:26 2007 @@ -12,9 +12,10 @@ @n = constant i17 -2 ; [#uses=0] @q = constant i17 0; [#uses=0] @r = constant i17 2; [#uses=0] [EMAIL PROTECTED] = constant i17 1 ; [#uses=0] [EMAIL PROTECTED] = constant i17 -1 ; [#uses=0] @t = constant i17 0; [#uses=0] @o = constant i17 0; [#uses=0] @p = constant i17 -1 ; [#uses=0] [EMAIL PROTECTED] = constant i17 1 ; [#uses=0] implementation ; Functions: Index: llvm/test/Integer/a31.ll diff -u llvm/test/Integer/a31.ll:1.5 llvm/test/Integer/a31.ll:1.6 --- llvm/test/Integer/a31.ll:1.5Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a31.llSat Mar 24 16:55:26 2007 @@ -18,7 +18,8 @@ @n = constant i31 mul(i31 2147483647, i31 2) @q = constant i31 sdiv(i31 -1,i31 1073741823) @r = constant i31 udiv(i31 -1,i31 1073741823) [EMAIL PROTECTED] = constant i31 srem(i31 3,i31 2147483646) [EMAIL PROTECTED] = constant i31 srem(i31 1,i31 2147483646) @t = constant i31 urem(i31 2147483647,i31 -1) @o = constant i31 trunc( i32 2147483648 to i31 ) @p = constant i31 trunc( i32 2147483647 to i31 ) [EMAIL PROTECTED] = constant i31 srem(i31 -3,i31 1
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Sat, 2007-03-24 at 10:06 -0700, Chris Lattner wrote:
> On Mar 24, 2007, at 8:34 AM, Zhou Sheng wrote:
>
> >
> >
> > Changes in directory llvm/lib/Transforms/Scalar:
> >
> > InstructionCombining.cpp updated: 1.682 -> 1.683
> > ---
> > Log message:
> >
> > Make some codes more efficient.
> >
> > @@ -5813,7 +5816,6 @@
> >case 16 : SExtType = Type::Int16Ty; break;
> >case 32 : SExtType = Type::Int32Ty; break;
> >case 64 : SExtType = Type::Int64Ty; break;
> > - case 128: SExtType = IntegerType::get(128); break;
> >default: break;
> >}
> >if (SExtType) {
>
> why did you remove this?
I asked Sheng to remove it because the back ends cannot deal with 128
bit integers.
>
> > @@ -5833,7 +5835,7 @@
> >BinaryOperator::createShl(X, ConstantInt::get(Ty,
> > ShiftDiff));
> > InsertNewInstBefore(Shift, I);
> >
> > -APInt Mask(APInt::getAllOnesValue(TypeBits).shl(ShiftAmt2));
> > +APInt Mask(Ty->getMask().shl(ShiftAmt2));
>
> You touched many instances of this. Please make a new
> APInt::getHighBits method.
The method getHiBits already exists and is used to extrat the N hi bits
from an existing APInt, not construct a new value. I have just committed
a re-organization of the APInt interface (mostly for documentation
purposes) but while I was at it I added three new functions that should
address this need:
/// Constructs an APInt value that has a contiguous range of bits set.
The
/// bits from loBit to hiBit will be set. All other bits will be zero.
For
/// example, with parameters(32, 15, 0) you would get 0x. If
hiBit is
/// less than loBit then the set bits "wrap". For example, with
/// parameters (32, 3, 28), you would get 0xF00F.
/// @param numBits the intended bit width of the result
/// @param hiBit the index of the highest bit set.
/// @param loBit the index of the lowest bit set.
/// @returns An APInt value with the requested bits set.
/// @brief Get a value with a block of bits set.
static APInt getBitsSet(uint32_t numBits, uint32_t hiBit, uint32_t
loBit = 0);
/// Constructs an APInt value that has the top hiBitsSet bits set.
/// @param numBits the bitwidth of the result
/// @param hiBitsSet the number of high-order bits set in the result.
/// @brief Get a value with high bits set
static APInt getHighBitsSet(uint32_t numBits, uint32_t hiBitsSet);
/// Constructs an APInt value that has the bottom loBitsSet bits set.
/// @param numBits the bitwidth of the result
/// @param loBitsSet the number of low-order bits set in the result.
/// @brief Get a value with low bits set
static APInt getLowBitsSet(uint32_t numBits, uint32_t loBitsSet);
Reid.
>
> -Chris
> ___
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.46 -> 1.47
---
Log message:
Clean up this interface:
1. Group similar methods into doxygen groups
2. Reorganize the groups into a consist flow.
3. Significantly improve the quality of the documentation on several methods
4. Rewrite srem and sdiv to eliminate a copy and improve readability.
5. Eliminate unneeded forward references.
---
Diffs of the changes: (+457 -312)
APInt.h | 769 ++--
1 files changed, 457 insertions(+), 312 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.46 llvm/include/llvm/ADT/APInt.h:1.47
--- llvm/include/llvm/ADT/APInt.h:1.46 Wed Mar 21 17:22:19 2007
+++ llvm/include/llvm/ADT/APInt.h Sat Mar 24 13:09:18 2007
@@ -8,7 +8,7 @@
//===--===//
//
// This file implements a class to represent arbitrary precision integral
-// constant values.
+// constant values and operations on them.
//
//===--===//
@@ -21,13 +21,6 @@
namespace llvm {
-/// Forward declaration.
-class APInt;
-namespace APIntOps {
- APInt udiv(const APInt& LHS, const APInt& RHS);
- APInt urem(const APInt& LHS, const APInt& RHS);
-}
-
//===--===//
// APInt Class
//===--===//
@@ -63,20 +56,21 @@
uint32_t BitWidth; ///< The number of bits in this APInt.
/// This union is used to store the integer value. When the
- /// integer bit-width <= 64, it uses VAL;
- /// otherwise it uses the pVal.
+ /// integer bit-width <= 64, it uses VAL, otherwise it uses pVal.
union {
uint64_t VAL;///< Used to store the <= 64 bits integer value.
uint64_t *pVal; ///< Used to store the >64 bits integer value.
};
- /// This enum is just used to hold a constant we needed for APInt.
+ /// This enum is used to hold the constants we needed for APInt.
enum {
-APINT_BITS_PER_WORD = sizeof(uint64_t) * 8,
-APINT_WORD_SIZE = sizeof(uint64_t)
+APINT_BITS_PER_WORD = sizeof(uint64_t) * 8, ///< Bits in a word
+APINT_WORD_SIZE = sizeof(uint64_t) ///< Byte size of a word
};
- // Fast internal constructor
+ /// This constructor is used only internally for speed of construction of
+ /// temporaries. It is unsafe for general use so it is not public.
+ /// @brief Fast internal constructor
APInt(uint64_t* val, uint32_t bits) : BitWidth(bits), pVal(val) { }
/// @returns true if the number of bits <= 64, false otherwise.
@@ -86,26 +80,32 @@
}
/// @returns the word position for the specified bit position.
+ /// @brief Determine which word a bit is in.
static inline uint32_t whichWord(uint32_t bitPosition) {
return bitPosition / APINT_BITS_PER_WORD;
}
/// @returns the bit position in a word for the specified bit position
- /// in APInt.
+ /// in the APInt.
+ /// @brief Determine which bit in a word a bit is in.
static inline uint32_t whichBit(uint32_t bitPosition) {
return bitPosition % APINT_BITS_PER_WORD;
}
- /// @returns a uint64_t type integer with just bit position at
- /// "whichBit(bitPosition)" setting, others zero.
+ /// This method generates and returns a uint64_t (word) mask for a single
+ /// bit at a specific bit position. This is used to mask the bit in the
+ /// corresponding word.
+ /// @returns a uint64_t with only bit at "whichBit(bitPosition)" set
+ /// @brief Get a single bit mask.
static inline uint64_t maskBit(uint32_t bitPosition) {
return 1ULL << whichBit(bitPosition);
}
- /// This method is used internally to clear the to "N" bits that are not used
- /// by the APInt. This is needed after the most significant word is assigned
- /// a value to ensure that those bits are zero'd out.
- /// @brief Clear high order bits
+ /// This method is used internally to clear the to "N" bits in the high order
+ /// word that are not used by the APInt. This is needed after the most
+ /// significant word is assigned a value to ensure that those bits are
+ /// zero'd out.
+ /// @brief Clear unused high order bits
inline APInt& clearUnusedBits() {
// Compute how many bits are used in the final word
uint32_t wordBits = BitWidth % APINT_BITS_PER_WORD;
@@ -131,8 +131,8 @@
}
/// This is used by the constructors that take string arguments.
- /// @brief Converts a char array into an APInt
- void fromString(uint32_t numBits, const char *StrStart, uint32_t slen,
+ /// @brief Convert a char array into an APInt
+ void fromString(uint32_t numBits, const char *strStart, uint32_t slen,
uint8_t radix);
/// This is used by the toString method to divide by the radix. It sim
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.484 -> 1.485
---
Log message:
don't rely on ADL
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.484
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.485
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.484 Wed Mar 7 10:25:08 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 24 12:37:03 2007
@@ -484,7 +484,7 @@
unsigned NumElements =
cast(N->getOperand(NumOps-2))->getValue();
MVT::ValueType EVT = cast(N->getOperand(NumOps-1))->getVT();
- MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
+ MVT::ValueType PackedVT = MVT::getVectorType(EVT, NumElements);
if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
// In the common case, this is a legal vector type, convert it to the
// packed operation and type now.
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h ValueTypes.td
Changes in directory llvm/include/llvm/CodeGen:
ValueTypes.h updated: 1.29 -> 1.30
ValueTypes.td updated: 1.2 -> 1.3
---
Log message:
add a valuetype for v1i64, which is needed by mmx.
---
Diffs of the changes: (+34 -27)
ValueTypes.h | 45 +
ValueTypes.td | 16 +---
2 files changed, 34 insertions(+), 27 deletions(-)
Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.29
llvm/include/llvm/CodeGen/ValueTypes.h:1.30
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.29 Tue Jul 18 19:40:45 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h Sat Mar 24 12:36:26 2007
@@ -52,18 +52,19 @@
v8i8 = 14, // 8 x i8
v4i16 = 15, // 4 x i16
v2i32 = 16, // 2 x i32
-v16i8 = 17, // 16 x i8
-v8i16 = 18, // 8 x i16
-v4i32 = 19, // 4 x i32
-v2i64 = 20, // 2 x i64
-
-v2f32 = 21, // 2 x f32
-v4f32 = 22, // 4 x f32
-v2f64 = 23, // 2 x f64
+v1i64 = 17, // 1 x i64
+v16i8 = 18, // 16 x i8
+v8i16 = 19, // 8 x i16
+v4i32 = 20, // 4 x i32
+v2i64 = 21, // 2 x i64
+
+v2f32 = 22, // 2 x f32
+v4f32 = 23, // 4 x f32
+v2f64 = 24, // 2 x f64
FIRST_VECTOR_VALUETYPE = v8i8,
LAST_VECTOR_VALUETYPE = v2f64,
-LAST_VALUETYPE = 24, // This always remains at the end of the list.
+LAST_VALUETYPE = 25, // This always remains at the end of the list.
// iPTR - An int value the size of the pointer of the current
// target. This should only be used internal to tblgen!
@@ -103,6 +104,7 @@
case MVT::v8i8:
case MVT::v4i16:
case MVT::v2i32:
+case MVT::v1i64:
case MVT::v2f32: return 64;
case MVT::f80 : return 80;
case MVT::f128:
@@ -133,6 +135,7 @@
case v8i16: return i16;
case v2i32:
case v4i32: return i32;
+case v1i64:
case v2i64: return i64;
case v2f32:
case v4f32: return f32;
@@ -144,17 +147,18 @@
/// of elements it contains.
static inline unsigned getVectorNumElements(ValueType VT) {
switch (VT) {
- default: assert(0 && "Invalid vector type!");
- case v16i8: return 16;
- case v8i8 :
- case v8i16: return 8;
- case v4i16:
- case v4i32:
- case v4f32: return 4;
- case v2i32:
- case v2i64:
- case v2f32:
- case v2f64: return 2;
+default: assert(0 && "Invalid vector type!");
+case v16i8: return 16;
+case v8i8 :
+case v8i16: return 8;
+case v4i16:
+case v4i32:
+case v4f32: return 4;
+case v2i32:
+case v2i64:
+case v2f32:
+case v2f64: return 2;
+case v1i64: return 1;
}
}
@@ -163,6 +167,7 @@
static inline ValueType getIntVectorWithNumElements(unsigned NumElts) {
switch (NumElts) {
default: assert(0 && "Invalid vector type!");
+case 1: return v1i64;
case 2: return v2i32;
case 4: return v4i16;
case 8: return v8i8;
Index: llvm/include/llvm/CodeGen/ValueTypes.td
diff -u llvm/include/llvm/CodeGen/ValueTypes.td:1.2
llvm/include/llvm/CodeGen/ValueTypes.td:1.3
--- llvm/include/llvm/CodeGen/ValueTypes.td:1.2 Mon Mar 27 16:48:00 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.td Sat Mar 24 12:36:26 2007
@@ -36,13 +36,15 @@
def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value
def v4i16 : ValueType<64 , 15>; // 4 x i16 vector value
def v2i32 : ValueType<64 , 16>; // 2 x i32 vector value
-def v16i8 : ValueType<128, 17>; // 16 x i8 vector value
-def v8i16 : ValueType<128, 18>; // 8 x i16 vector value
-def v4i32 : ValueType<128, 19>; // 4 x i32 vector value
-def v2i64 : ValueType<128, 20>; // 2 x i64 vector value
-def v2f32 : ValueType<64, 21>; // 2 x f32 vector value
-def v4f32 : ValueType<128, 22>; // 4 x f32 vector value
-def v2f64 : ValueType<128, 23>; // 2 x f64 vector value
+def v1i64 : ValueType<64 , 17>; // 1 x i64 vector value
+
+def v16i8 : ValueType<128, 18>; // 16 x i8 vector value
+def v8i16 : ValueType<128, 19>; // 8 x i16 vector value
+def v4i32 : ValueType<128, 20>; // 4 x i32 vector value
+def v2i64 : ValueType<128, 21>; // 2 x i64 vector value
+def v2f32 : ValueType<64, 22>; // 2 x f32 vector value
+def v4f32 : ValueType<128, 23>; // 4 x f32 vector value
+def v2f64 : ValueType<128, 24>; // 2 x f64 vector value
// Pseudo valuetype mapped to the current pointer size.
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[llvm-commits] CVS: llvm/lib/VMCore/ValueTypes.cpp
Changes in directory llvm/lib/VMCore: ValueTypes.cpp updated: 1.14 -> 1.15 --- Log message: add a valuetype for v1i64, which is needed by mmx. --- Diffs of the changes: (+3 -0) ValueTypes.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/VMCore/ValueTypes.cpp diff -u llvm/lib/VMCore/ValueTypes.cpp:1.14 llvm/lib/VMCore/ValueTypes.cpp:1.15 --- llvm/lib/VMCore/ValueTypes.cpp:1.14 Wed Feb 14 20:26:10 2007 +++ llvm/lib/VMCore/ValueTypes.cpp Sat Mar 24 12:36:26 2007 @@ -38,6 +38,7 @@ case MVT::v8i8: return "v8i8"; case MVT::v4i16: return "v4i16"; case MVT::v2i32: return "v2i32"; + case MVT::v1i64: return "v1i64"; case MVT::v16i8: return "v16i8"; case MVT::v8i16: return "v8i16"; case MVT::v4i32: return "v4i32"; @@ -68,6 +69,7 @@ if (NumElements == 4) return MVT::v4i32; break; case MVT::i64: +if (NumElements == 1) return MVT::v1i64; if (NumElements == 2) return MVT::v2i64; break; case MVT::f32: @@ -99,6 +101,7 @@ case MVT::v8i8: return VectorType::get(Type::Int8Ty, 8); case MVT::v4i16: return VectorType::get(Type::Int16Ty, 4); case MVT::v2i32: return VectorType::get(Type::Int32Ty, 2); + case MVT::v1i64: return VectorType::get(Type::Int64Ty, 1); case MVT::v16i8: return VectorType::get(Type::Int8Ty, 16); case MVT::v8i16: return VectorType::get(Type::Int16Ty, 8); case MVT::v4i32: return VectorType::get(Type::Int32Ty, 4); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Mar 24, 2007, at 8:34 AM, Zhou Sheng wrote:
>
>
> Changes in directory llvm/lib/Transforms/Scalar:
>
> InstructionCombining.cpp updated: 1.682 -> 1.683
> ---
> Log message:
>
> Make some codes more efficient.
>
> @@ -5813,7 +5816,6 @@
>case 16 : SExtType = Type::Int16Ty; break;
>case 32 : SExtType = Type::Int32Ty; break;
>case 64 : SExtType = Type::Int64Ty; break;
> - case 128: SExtType = IntegerType::get(128); break;
>default: break;
>}
>if (SExtType) {
why did you remove this?
> @@ -5833,7 +5835,7 @@
>BinaryOperator::createShl(X, ConstantInt::get(Ty,
> ShiftDiff));
> InsertNewInstBefore(Shift, I);
>
> -APInt Mask(APInt::getAllOnesValue(TypeBits).shl(ShiftAmt2));
> +APInt Mask(Ty->getMask().shl(ShiftAmt2));
You touched many instances of this. Please make a new
APInt::getHighBits method.
-Chris
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.682 -> 1.683
---
Log message:
Make some codes more efficient.
---
Diffs of the changes: (+17 -15)
InstructionCombining.cpp | 32 +---
1 files changed, 17 insertions(+), 15 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.682
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.683
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.682 Fri Mar 23
19:42:08 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Mar 24 10:34:37 2007
@@ -3117,7 +3117,9 @@
case Instruction::And:
if (ConstantExpr::getAnd(N, Mask) == Mask) {
// If the AndRHS is a power of two minus one (0+1+), this is simple.
- if ((Mask->getValue() & Mask->getValue()+1) == 0)
+ if ((Mask->getValue().countLeadingZeros() +
+ Mask->getValue().countPopulation()) ==
+ Mask->getValue().getBitWidth())
break;
// Otherwise, if Mask is 0+1+0+, and if B is known to have the low 0+
@@ -3127,7 +3129,7 @@
if (isRunOfOnes(Mask, MB, ME)) { // begin/end bit of run, inclusive
uint32_t BitWidth = cast(RHS->getType())->getBitWidth();
APInt Mask(APInt::getAllOnesValue(BitWidth));
-Mask = APIntOps::lshr(Mask, BitWidth-MB+1);
+Mask = Mask.lshr(BitWidth-MB+1);
if (MaskedValueIsZero(RHS, Mask))
break;
}
@@ -3136,8 +3138,9 @@
case Instruction::Or:
case Instruction::Xor:
// If the AndRHS is a power of two minus one (0+1+), and N&Mask == 0
-if ((Mask->getValue() & Mask->getValue()+1) == 0 &&
-ConstantExpr::getAnd(N, Mask)->isNullValue())
+if ((Mask->getValue().countLeadingZeros() +
+ Mask->getValue().countPopulation()) == Mask->getValue().getBitWidth()
+&& ConstantExpr::getAnd(N, Mask)->isNullValue())
break;
return 0;
}
@@ -5731,8 +5734,8 @@
// operation.
//
if (isValid && !isLeftShift && I.getOpcode() == Instruction::AShr) {
- APInt Val(Op0C->getValue());
- isValid = ((Val & APInt::getSignBit(TypeBits)) != 0) == highBitSet;
+ isValid = ((Op0C->getValue() & APInt::getSignBit(TypeBits)) != 0) ==
+highBitSet;
}
if (isValid) {
@@ -5757,7 +5760,7 @@
if (ShiftOp && isa(ShiftOp->getOperand(1))) {
ConstantInt *ShiftAmt1C = cast(ShiftOp->getOperand(1));
-// shift amount always <= 32 bits
+// These shift amounts are always <= 32 bits.
unsigned ShiftAmt1 = (unsigned)ShiftAmt1C->getZExtValue();
unsigned ShiftAmt2 = (unsigned)Op1->getZExtValue();
assert(ShiftAmt2 != 0 && "Should have been simplified earlier");
@@ -5785,7 +5788,7 @@
BinaryOperator::createAShr(X, ConstantInt::get(Ty, AmtSum));
InsertNewInstBefore(Shift, I);
- APInt Mask(APInt::getAllOnesValue(TypeBits).lshr(ShiftAmt2));
+ APInt Mask(Ty->getMask().lshr(ShiftAmt2));
return BinaryOperator::createAnd(Shift, ConstantInt::get(Mask));
}
@@ -5794,12 +5797,12 @@
if (ShiftAmt1 == ShiftAmt2) {
// If we have ((X >>? C) << C), turn this into X & (-1 << C).
if (I.getOpcode() == Instruction::Shl) {
-APInt Mask(APInt::getAllOnesValue(TypeBits).shl(ShiftAmt1));
+APInt Mask(Ty->getMask().shl(ShiftAmt1));
return BinaryOperator::createAnd(X, ConstantInt::get(Mask));
}
// If we have ((X << C) >>u C), turn this into X & (-1 >>u C).
if (I.getOpcode() == Instruction::LShr) {
-APInt Mask(APInt::getAllOnesValue(TypeBits).lshr(ShiftAmt1));
+APInt Mask(Ty->getMask().lshr(ShiftAmt1));
return BinaryOperator::createAnd(X, ConstantInt::get(Mask));
}
// We can simplify ((X << C) >>s C) into a trunc + sext.
@@ -5813,7 +5816,6 @@
case 16 : SExtType = Type::Int16Ty; break;
case 32 : SExtType = Type::Int32Ty; break;
case 64 : SExtType = Type::Int64Ty; break;
- case 128: SExtType = IntegerType::get(128); break;
default: break;
}
if (SExtType) {
@@ -5833,7 +5835,7 @@
BinaryOperator::createShl(X, ConstantInt::get(Ty, ShiftDiff));
InsertNewInstBefore(Shift, I);
-APInt Mask(APInt::getAllOnesValue(TypeBits).shl(ShiftAmt2));
+APInt Mask(Ty->getMask().shl(ShiftAmt2));
return BinaryOperator::createAnd(Shift, ConstantInt::get(Mask));
}
@@ -5844,7 +5846,7 @@
BinaryOperator::createLShr(X, ConstantInt::get(Ty, ShiftDiff));
InsertNewInstBefore(Shift, I);
-APInt Mask(APInt::getAllOnesValue(TypeBits).lshr(ShiftAmt2));
+APInt Mask(Ty->getMask().lshr(ShiftAmt2));
return BinaryOperator::createAnd(Shift, ConstantInt::get(Mask));
}
@@ -5862,7 +5864,7 @@
Constant
