Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
On 2007-06-28, at 23:37, David A. Greene wrote: On Thursday 28 June 2007 21:51, Nick Lewycky wrote: David Greene wrote: +// Cray [dag]: Must recompute end() each iteration because it may Please don't mark the comments as being from Cray. Just write the comment as a standard explanation. Ok, will fix. Just wanted to take responsibility for screw-ups. :) svn blame will know your name. ;) — Gordon ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Hi Evan,
> +/// propagateEHRegister - The specified EH register is required in a
> successor
> +/// of the EH landing pad. Propagate it (by adding it to livein) to all the
> +/// blocks in the paths between the landing pad and the specified block.
thanks for this fix. For the moment we don't really need this much generality:
due to other problems (PR1508) we don't even try to handle the case where the
exception handling intrinsics are neither in the landing pad nor in an immediate
successor of the landing pad (we assert if this occurs). Thus the attached
minimal fix is good enough until PR1508 is resolved (shall I commit it?). Also,
I can't help feeling that the right way to solve the problem of reading the
exception
register in some block potentially far away from the landing pad is: (1) add
code to
the landing pad that writes the physical register to a virtual register; (2)
turn
the eh.exception intrinsic into a read from the virtual register. The problem
is
that we are in ssa form during codegen, so doing this means inserting phi nodes
etc
for the virtual register.
Ciao,
Duncan.
Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===
RCS file: /var/cvs/llvm/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp,v
retrieving revision 1.474
diff -u -3 -p -r1.474 SelectionDAGISel.cpp
--- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 29 Jun 2007 03:42:22 - 1.474
+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 29 Jun 2007 08:19:49 -
@@ -2336,25 +2336,6 @@ static void addCatchInfo(CallInst &I, Ma
MMI->addCatchTypeInfo(MBB, TyInfo);
}
-/// propagateEHRegister - The specified EH register is required in a successor
-/// of the EH landing pad. Propagate it (by adding it to livein) to all the
-/// blocks in the paths between the landing pad and the specified block.
-static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg,
-SmallPtrSet Visited) {
- if (MBB->isLandingPad() || !Visited.insert(MBB))
-return;
-
- MBB->addLiveIn(EHReg);
- for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
- E = MBB->pred_end(); PI != E; ++PI)
-propagateEHRegister(*PI, EHReg, Visited);
-}
-
-static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg) {
- SmallPtrSet Visited;
- propagateEHRegister(MBB, EHReg, Visited);
-}
-
/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
/// we want to emit this as a call to a named external function, return the name
/// otherwise lower it and return null.
@@ -2465,9 +2446,11 @@ SelectionDAGLowering::visitIntrinsicCall
case Intrinsic::eh_exception: {
if (ExceptionHandling) {
- if (!CurMBB->isLandingPad() && TLI.getExceptionAddressRegister())
- propagateEHRegister(CurMBB, TLI.getExceptionAddressRegister());
-
+ if (!CurMBB->isLandingPad()) {
+// FIXME: Mark exception register as live in. Hack for PR1508.
+unsigned Reg = TLI.getExceptionAddressRegister();
+if (Reg) CurMBB->addLiveIn(Reg);
+ }
// Insert the EXCEPTIONADDR instruction.
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDOperand Ops[1];
@@ -2492,8 +2475,9 @@ SelectionDAGLowering::visitIntrinsicCall
#ifndef NDEBUG
FuncInfo.CatchInfoLost.insert(&I);
#endif
-if (TLI.getExceptionSelectorRegister())
- propagateEHRegister(CurMBB, TLI.getExceptionSelectorRegister());
+// FIXME: Mark exception selector register as live in. Hack for PR1508.
+unsigned Reg = TLI.getExceptionSelectorRegister();
+if (Reg) CurMBB->addLiveIn(Reg);
}
// Insert the EHSELECTION instruction.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ScheduleDAGRRList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.473 -> 1.474
ScheduleDAGRRList.cpp updated: 1.32 -> 1.33
---
Log message:
Remove unnecessary attributions in comments.
---
Diffs of the changes: (+3 -3)
ScheduleDAGRRList.cpp |2 +-
SelectionDAGISel.cpp |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.473
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.474
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.473Thu Jun 28
21:49:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 28 22:42:22 2007
@@ -1700,8 +1700,8 @@
// Merge case into clusters
if (Cases.size()>=2)
-// Cray [dag]: Must recompute end() each iteration because it may
-// be invalidated by erase if we hold on to it
+// Must recompute end() each iteration because it may be
+// invalidated by erase if we hold on to it
for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
int64_t nextValue = cast(J->Low)->getSExtValue();
int64_t currentValue = cast(I->High)->getSExtValue();
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.32
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.33
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.32Thu Jun 28
21:48:09 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Jun 28 22:42:23 2007
@@ -618,7 +618,7 @@
bool LIsTarget = left->Node->isTargetOpcode();
bool RIsTarget = right->Node->isTargetOpcode();
- // Cray: There used to be a special tie breaker here that looked for
+ // There used to be a special tie breaker here that looked for
// two-address instructions and preferred the instruction with a
// def&use operand. The special case triggered diagnostics when
// _GLIBCXX_DEBUG was enabled because it broke the strict weak
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
David Greene wrote: > +// Cray [dag]: Must recompute end() each iteration because it may Please don't mark the comments as being from Cray. Just write the comment as a standard explanation. Nick ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.472 -> 1.473
---
Log message:
Fix reference to cached end iterator invalidated by an erase operation.
Uncovered by _GLIBCXX_DEBUG.
---
Diffs of the changes: (+3 -1)
SelectionDAGISel.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.472
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.473
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.472Thu Jun 28
18:29:44 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 28 21:49:11 2007
@@ -1700,7 +1700,9 @@
// Merge case into clusters
if (Cases.size()>=2)
-for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) {
+// Cray [dag]: Must recompute end() each iteration because it may
+// be invalidated by erase if we hold on to it
+for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
int64_t nextValue = cast(J->Low)->getSExtValue();
int64_t currentValue = cast(I->High)->getSExtValue();
MachineBasicBlock* nextBB = J->BB;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.471 -> 1.472
TargetLowering.cpp updated: 1.123 -> 1.124
---
Log message:
Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
---
Diffs of the changes: (+355 -453)
SelectionDAGISel.cpp | 642 ++-
TargetLowering.cpp | 166 +
2 files changed, 355 insertions(+), 453 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.471
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.472
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.471Wed Jun 27
13:45:32 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 28 18:29:44 2007
@@ -90,7 +90,7 @@
/// This is needed because values can be promoted into larger registers and
/// expanded into multiple smaller registers than the value.
struct VISIBILITY_HIDDEN RegsForValue {
-/// Regs - This list hold the register (for legal and promoted values)
+/// Regs - This list holds the register (for legal and promoted values)
/// or register set (for expanded values) that the value should be assigned
/// to.
std::vector Regs;
@@ -117,15 +117,16 @@
/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
/// this value and returns the result as a ValueVT value. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
+/// If the Flag pointer is NULL, no flag is used.
SDOperand getCopyFromRegs(SelectionDAG &DAG,
- SDOperand &Chain, SDOperand &Flag) const;
+ SDOperand &Chain, SDOperand *Flag) const;
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
/// specified value into the registers specified by this object. This
uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
+/// If the Flag pointer is NULL, no flag is used.
void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
- SDOperand &Chain, SDOperand &Flag,
- MVT::ValueType PtrVT) const;
+ SDOperand &Chain, SDOperand *Flag) const;
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
/// operand list. This adds the code marker and includes the number of
@@ -306,15 +307,8 @@
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
MVT::ValueType VT = TLI.getValueType(V->getType());
- unsigned NumRegisters;
- MVT::ValueType RegisterVT;
- if (MVT::isVector(VT)) {
-MVT::ValueType ElementVT;
-NumRegisters = TLI.getVectorTypeBreakdown(VT, ElementVT, RegisterVT);
- } else {
-RegisterVT = TLI.getTypeToTransformTo(VT);
-NumRegisters = TLI.getNumRegisters(VT);
- }
+ unsigned NumRegisters = TLI.getNumRegisters(VT);
+ MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
unsigned R = MakeReg(RegisterVT);
for (unsigned i = 1; i != NumRegisters; ++i)
@@ -695,79 +689,17 @@
unsigned InReg = FuncInfo.ValueMap[V];
assert(InReg && "Value not in map!");
- // If this type is not legal, make it so now.
- if (!MVT::isVector(VT)) {
-if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
- // Source must be expanded. This input value is actually coming from the
- // register pair InReg and InReg+1.
- MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
- unsigned NumVals = TLI.getNumRegisters(VT);
- N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
- if (NumVals == 1)
-N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
- else {
-assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
-N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
-DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1,
DestVT));
- }
-} else {
- MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
- N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
- if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
-N = MVT::isFloatingPoint(VT)
- ? DAG.getNode(ISD::FP_ROUND, VT, N)
- : DAG.getNode(ISD::TRUNCATE, VT, N);
-}
- } else {
-// Otherwise, if this is a vector, make it available as a vector
-// here.
-MVT::ValueType ElementVT, LegalElementVT;
-unsigned NE = TLI.getVectorTypeBreakdown(VT, ElementVT,
- LegalElementVT);
-
-// Build a BUILD_VECTOR or CONCAT_VECTORS with the input registers.
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.470 -> 1.471
---
Log message:
Partial fix for PR1502: http://llvm.org/PR1502 : If a EH register is needed in
a successor of landing pad, add it as livein to all the blocks in the paths
between the landing pad and the specified block.
---
Diffs of the changes: (+34 -11)
SelectionDAGISel.cpp | 45 ++---
1 files changed, 34 insertions(+), 11 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.470
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.471
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.470Wed Jun 27
09:34:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 27 13:45:32 2007
@@ -2402,6 +2402,25 @@
MMI->addCatchTypeInfo(MBB, TyInfo);
}
+/// propagateEHRegister - The specified EH register is required in a successor
+/// of the EH landing pad. Propagate it (by adding it to livein) to all the
+/// blocks in the paths between the landing pad and the specified block.
+static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg,
+SmallPtrSet Visited) {
+ if (MBB->isLandingPad() || !Visited.insert(MBB))
+return;
+
+ MBB->addLiveIn(EHReg);
+ for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
+ E = MBB->pred_end(); PI != E; ++PI)
+propagateEHRegister(*PI, EHReg, Visited);
+}
+
+static void propagateEHRegister(MachineBasicBlock *MBB, unsigned EHReg) {
+ SmallPtrSet Visited;
+ propagateEHRegister(MBB, EHReg, Visited);
+}
+
/// visitIntrinsicCall - Lower the call to the specified intrinsic function.
If
/// we want to emit this as a call to a named external function, return the
name
/// otherwise lower it and return null.
@@ -2511,12 +2530,9 @@
}
case Intrinsic::eh_exception: {
-MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-
-if (ExceptionHandling && MMI) {
- // Mark exception register as live in.
- unsigned Reg = TLI.getExceptionAddressRegister();
- if (Reg) CurMBB->addLiveIn(Reg);
+if (ExceptionHandling) {
+ if (!CurMBB->isLandingPad() && TLI.getExceptionAddressRegister())
+ propagateEHRegister(CurMBB, TLI.getExceptionAddressRegister());
// Insert the EXCEPTIONADDR instruction.
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
@@ -2538,14 +2554,13 @@
if (ExceptionHandling && MMI) {
if (CurMBB->isLandingPad())
addCatchInfo(I, MMI, CurMBB);
+ else {
#ifndef NDEBUG
- else
FuncInfo.CatchInfoLost.insert(&I);
#endif
-
- // Mark exception selector register as live in.
- unsigned Reg = TLI.getExceptionSelectorRegister();
- if (Reg) CurMBB->addLiveIn(Reg);
+if (TLI.getExceptionSelectorRegister())
+ propagateEHRegister(CurMBB, TLI.getExceptionSelectorRegister());
+ }
// Insert the EHSELECTION instruction.
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
@@ -4482,6 +4497,14 @@
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
DAG.getConstant(LabelID, MVT::i32)));
+// Mark exception register as live in.
+unsigned Reg = TLI.getExceptionAddressRegister();
+if (Reg) BB->addLiveIn(Reg);
+
+// Mark exception selector register as live in.
+Reg = TLI.getExceptionSelectorRegister();
+if (Reg) BB->addLiveIn(Reg);
+
// FIXME: Hack around an exception handling flaw (PR1508): the personality
// function and list of typeids logically belong to the invoke (or, if you
// like, the basic block containing the invoke), and need to be associated
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.469 -> 1.470
---
Log message:
Use getVectorTypeBreakdown in FunctionLoweringInfo::CreateRegForValue
to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529: http://llvm.org/PR1529 .
---
Diffs of the changes: (+11 -44)
SelectionDAGISel.cpp | 55 ++-
1 files changed, 11 insertions(+), 44 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.469
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.470
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.469Mon Jun 25
11:23:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 27 09:34:07 2007
@@ -306,53 +306,20 @@
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
MVT::ValueType VT = TLI.getValueType(V->getType());
- // The number of multiples of registers that we need, to, e.g., split up
- // a <2 x int64> -> 4 x i32 registers.
- unsigned NumVectorRegs = 1;
-
- // If this is a vector type, figure out what type it will decompose into
- // and how many of the elements it will use.
+ unsigned NumRegisters;
+ MVT::ValueType RegisterVT;
if (MVT::isVector(VT)) {
-const VectorType *PTy = cast(V->getType());
-unsigned NumElts = PTy->getNumElements();
-MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
-MVT::ValueType VecTy = MVT::getVectorType(EltTy, NumElts);
-
-// Divide the input until we get to a supported size. This will always
-// end with a scalar if the target doesn't support vectors.
-while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
- NumElts >>= 1;
- NumVectorRegs <<= 1;
- VecTy = MVT::getVectorType(EltTy, NumElts);
-}
-
-// Check that VecTy isn't a 1-element vector.
-if (NumElts == 1 && VecTy == MVT::Other)
- VT = EltTy;
-else
- VT = VecTy;
+MVT::ValueType ElementVT;
+NumRegisters = TLI.getVectorTypeBreakdown(VT, ElementVT, RegisterVT);
+ } else {
+RegisterVT = TLI.getTypeToTransformTo(VT);
+NumRegisters = TLI.getNumRegisters(VT);
}
- // The common case is that we will only create one register for this
- // value. If we have that case, create and return the virtual register.
- unsigned NV = TLI.getNumRegisters(VT);
- if (NV == 1) {
-// If we are promoting this value, pick the next largest supported type.
-MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
-unsigned Reg = MakeReg(PromotedType);
-// If this is a vector of supported or promoted types (e.g. 4 x i16),
-// create all of the registers.
-for (unsigned i = 1; i != NumVectorRegs; ++i)
- MakeReg(PromotedType);
-return Reg;
- }
-
- // If this value is represented with multiple target registers, make sure
- // to create enough consecutive registers of the right (smaller) type.
- VT = TLI.getTypeToExpandTo(VT);
- unsigned R = MakeReg(VT);
- for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
-MakeReg(VT);
+ unsigned R = MakeReg(RegisterVT);
+ for (unsigned i = 1; i != NumRegisters; ++i)
+MakeReg(RegisterVT);
+
return R;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.466 -> 1.467
TargetLowering.cpp updated: 1.119 -> 1.120
---
Log message:
Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
---
Diffs of the changes: (+19 -19)
SelectionDAGISel.cpp | 28 ++--
TargetLowering.cpp | 10 +-
2 files changed, 19 insertions(+), 19 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.467
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466Fri Jun 15
17:26:58 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 21 09:42:22 2007
@@ -290,19 +290,19 @@
if (PN->use_empty()) continue;
MVT::ValueType VT = TLI.getValueType(PN->getType());
- unsigned NumElements;
+ unsigned NumRegisters;
if (VT != MVT::Vector)
-NumElements = TLI.getNumElements(VT);
+NumRegisters = TLI.getNumRegisters(VT);
else {
MVT::ValueType VT1,VT2;
-NumElements =
+NumRegisters =
TLI.getVectorTypeBreakdown(cast(PN->getType()),
VT1, VT2);
}
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
- for (unsigned i = 0; i != NumElements; ++i)
+ for (unsigned i = 0; i != NumRegisters; ++i)
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
}
}
@@ -343,7 +343,7 @@
// The common case is that we will only create one register for this
// value. If we have that case, create and return the virtual register.
- unsigned NV = TLI.getNumElements(VT);
+ unsigned NV = TLI.getNumRegisters(VT);
if (NV == 1) {
// If we are promoting this value, pick the next largest supported type.
MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
@@ -750,7 +750,7 @@
// Source must be expanded. This input value is actually coming from the
// register pair InReg and InReg+1.
MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
- unsigned NumVals = TLI.getNumElements(VT);
+ unsigned NumVals = TLI.getNumRegisters(VT);
N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
if (NumVals == 1)
N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
@@ -3185,7 +3185,7 @@
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other)
-NumRegs = TLI.getNumElements(OpInfo.ConstraintVT);
+NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
MVT::ValueType RegVT;
MVT::ValueType ValueVT = OpInfo.ConstraintVT;
@@ -3831,7 +3831,7 @@
// integers. Figure out what the destination type is and how many
small
// integers it turns into.
MVT::ValueType NVT = getTypeToExpandTo(VT);
-unsigned NumVals = getNumElements(VT);
+unsigned NumVals = getNumRegisters(VT);
for (unsigned i = 0; i != NumVals; ++i) {
RetVals.push_back(NVT);
// if it isn't first piece, alignment must be 1
@@ -4088,7 +4088,7 @@
// integers. Figure out what the source elt type is and how many small
// integers it is.
MVT::ValueType NVT = getTypeToExpandTo(VT);
-unsigned NumVals = getNumElements(VT);
+unsigned NumVals = getNumRegisters(VT);
for (unsigned i = 0; i != NumVals; ++i)
RetTys.push_back(NVT);
} else {
@@ -4507,7 +4507,7 @@
return DAG.getCopyToReg(getRoot(), Reg, Op);
} else {
DestVT = TLI.getTypeToExpandTo(SrcVT);
-unsigned NumVals = TLI.getNumElements(SrcVT);
+unsigned NumVals = TLI.getNumRegisters(SrcVT);
if (NumVals == 1)
return DAG.getCopyToReg(getRoot(), Reg,
DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
@@ -4695,16 +4695,16 @@
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
MVT::ValueType VT = TLI.getValueType(PN->getType());
- unsigned NumElements;
+ unsigned NumRegisters;
if (VT != MVT::Vector)
-NumElements = TLI.getNumElements(VT);
+NumRegisters = TLI.getNumRegisters(VT);
else {
MVT::ValueType VT1,VT2;
-NumElements =
+NumRegisters =
TLI.getVectorTypeBreakdown(cast(PN->getType()),
VT1, VT2);
}
- for (unsigned i = 0, e = NumElements; i != e; ++i)
+ for (unsigned i = 0, e = NumRegisters; i != e; ++i)
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
}
}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.465 -> 1.466 --- Log message: Codegen support (stripped out) for the annotate attribute. --- Diffs of the changes: (+4 -0) SelectionDAGISel.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.465 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.465Fri Jun 15 14:11:01 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 15 17:26:58 2007 @@ -2774,6 +2774,10 @@ case Intrinsic::prefetch: // FIXME: Currently discarding prefetches. return 0; + + case Intrinsic::var_annotation: +// Discard annotate attributes +return 0; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.464 -> 1.465
---
Log message:
Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
for tied register constraints.
---
Diffs of the changes: (+9 -6)
SelectionDAGISel.cpp | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.464
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.465
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.464Fri Jun 15
14:04:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 15 14:11:01 2007
@@ -3222,7 +3222,8 @@
// Otherwise, if this was a reference to an LLVM register class, create vregs
// for this reference.
std::vector RegClassRegs;
- if (PhysReg.second) {
+ const TargetRegisterClass *RC = PhysReg.second;
+ if (RC) {
// If this is an early clobber or tied register, our regalloc doesn't know
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the regalloc do the right thing.
@@ -3272,11 +3273,13 @@
// Check to see if this register is allocatable (i.e. don't give out the
// stack pointer).
-const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
-if (!RC) {
- // Make sure we find consecutive registers.
- NumAllocated = 0;
- continue;
+if (RC == 0) {
+ RC = isAllocatableRegister(Reg, MF, TLI, MRI);
+ if (!RC) {// Couldn't allocate this register.
+// Reset NumAllocated to make sure we return consecutive registers.
+NumAllocated = 0;
+continue;
+ }
}
// Okay, this register is good, we can use it.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.463 -> 1.464
---
Log message:
Workaround for PR1508: http://llvm.org/PR1508 .
---
Diffs of the changes: (+96 -29)
SelectionDAGISel.cpp | 125 +++
1 files changed, 96 insertions(+), 29 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.463
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.464
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.463Thu Jun 14
17:58:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 15 14:04:19 2007
@@ -179,6 +179,11 @@
/// anywhere in the function.
std::map StaticAllocaMap;
+#ifndef NDEBUG
+SmallSet CatchInfoLost;
+SmallSet CatchInfoFound;
+#endif
+
unsigned MakeReg(MVT::ValueType VT) {
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -199,6 +204,15 @@
};
}
+/// isFilterOrSelector - Return true if this instruction is a call to the
+/// eh.filter or the eh.selector intrinsic.
+static bool isFilterOrSelector(Instruction *I) {
+ if (IntrinsicInst *II = dyn_cast(I))
+return II->getIntrinsicID() == Intrinsic::eh_selector
+ || II->getIntrinsicID() == Intrinsic::eh_filter;
+ return false;
+}
+
/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
/// PHI nodes or outside of the basic block that defines it, or used by a
/// switch instruction, which may expand to multiple basic blocks.
@@ -2463,6 +2477,33 @@
return NULL;
}
+/// addCatchInfo - Extract the personality and type infos from an eh.selector
+/// or eh.filter call, and add them to the specified machine basic block.
+static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
+ MachineBasicBlock *MBB) {
+ // Inform the MachineModuleInfo of the personality for this landing pad.
+ ConstantExpr *CE = cast(I.getOperand(2));
+ assert(CE->getOpcode() == Instruction::BitCast &&
+ isa(CE->getOperand(0)) &&
+ "Personality should be a function");
+ MMI->addPersonality(MBB, cast(CE->getOperand(0)));
+
+ // Gather all the type infos for this landing pad and pass them along to
+ // MachineModuleInfo.
+ std::vector TyInfo;
+ for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
+Constant *C = cast(I.getOperand(i));
+GlobalVariable *GV = ExtractGlobalVariable(C);
+assert (GV || isa(C) &&
+"TypeInfo must be a global variable or NULL");
+TyInfo.push_back(GV);
+ }
+ if (I.getCalledFunction()->getIntrinsicID() == Intrinsic::eh_filter)
+MMI->addFilterTypeInfo(MBB, TyInfo);
+ else
+MMI->addCatchTypeInfo(MBB, TyInfo);
+}
+
/// visitIntrinsicCall - Lower the call to the specified intrinsic function.
If
/// we want to emit this as a call to a named external function, return the
name
/// otherwise lower it and return null.
@@ -2595,29 +2636,14 @@
case Intrinsic::eh_selector:
case Intrinsic::eh_filter:{
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-
+
if (ExceptionHandling && MMI) {
- // Inform the MachineModuleInfo of the personality for this landing pad.
- ConstantExpr *CE = dyn_cast(I.getOperand(2));
- assert(CE && CE->getOpcode() == Instruction::BitCast &&
- isa(CE->getOperand(0)) &&
- "Personality should be a function");
- MMI->addPersonality(CurMBB, cast(CE->getOperand(0)));
-
- // Gather all the type infos for this landing pad and pass them along to
- // MachineModuleInfo.
- std::vector TyInfo;
- for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
-Constant *C = cast(I.getOperand(i));
-GlobalVariable *GV = ExtractGlobalVariable(C);
-assert (GV || isa(C) &&
-"TypeInfo must be a global variable or NULL");
-TyInfo.push_back(GV);
- }
- if (Intrinsic == Intrinsic::eh_filter)
-MMI->addFilterTypeInfo(CurMBB, TyInfo);
+ if (CurMBB->isLandingPad())
+addCatchInfo(I, MMI, CurMBB);
+#ifndef NDEBUG
else
-MMI->addCatchTypeInfo(CurMBB, TyInfo);
+FuncInfo.CatchInfoLost.insert(&I);
+#endif
// Mark exception selector register as live in.
unsigned Reg = TLI.getExceptionSelectorRegister();
@@ -4403,6 +4429,11 @@
E = MF.livein_end(); I != E; ++I)
BB->addLiveIn(I->first);
+#ifndef NDEBUG
+ assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
+ "Not all catch info was assigned to a landing pad!");
+#endif
+
return true;
}
@@ -4513,6 +4544,20 @@
EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
}
+static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
+ MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
+ assert(!FLI.MBBMap[SrcBB]->isLandingPad() &&
+ "Copying catch info out of a landi
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.459 -> 1.460
---
Log message:
When creating CopyFromReg nodes, always use legal types. And use the
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
---
Diffs of the changes: (+6 -6)
SelectionDAGISel.cpp | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.459
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.460
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.459Wed Jun 13
00:51:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 13 09:55:16 2007
@@ -772,7 +772,7 @@
// If the register was promoted, use TRUNCATE or FP_ROUND as appropriate.
for (unsigned i = 0; i != NE; ++i) {
SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
- PTyElementVT);
+ PTyLegalElementVT);
if (MVT::isFloatingPoint(PTyElementVT))
Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
else
@@ -782,17 +782,17 @@
} else {
// If the register was expanded, use BUILD_PAIR.
assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
- for (unsigned i = 0; i != NE/2; ++i) {
+ for (unsigned i = 0; i != NE; ++i) {
SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
- PTyElementVT);
+ PTyLegalElementVT);
SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
- PTyElementVT);
-Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
+ PTyLegalElementVT);
+Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, PTyElementVT, Op0, Op1));
}
}
Ops.push_back(DAG.getConstant(NE, MVT::i32));
-Ops.push_back(DAG.getValueType(PTyLegalElementVT));
+Ops.push_back(DAG.getValueType(PTyElementVT));
N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
// Finally, use a VBIT_CONVERT to make this available as the appropriate
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.461 -> 1.462
---
Log message:
Only correctly lower exception handing intrinsics if exception handling is
turned on. Likewise for scanning of invokes to mark landing pads.
---
Diffs of the changes: (+7 -8)
SelectionDAGISel.cpp | 15 +++
1 files changed, 7 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.461
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.462
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.461Wed Jun 13
10:12:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 13 11:53:21 2007
@@ -2574,7 +2574,7 @@
case Intrinsic::eh_exception: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-if (MMI) {
+if (ExceptionHandling && MMI) {
// Mark exception register as live in.
unsigned Reg = TLI.getExceptionAddressRegister();
if (Reg) CurMBB->addLiveIn(Reg);
@@ -2596,7 +2596,7 @@
case Intrinsic::eh_filter:{
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-if (MMI) {
+if (ExceptionHandling && MMI) {
// Inform the MachineModuleInfo of the personality for this landing pad.
ConstantExpr *CE = dyn_cast(I.getOperand(2));
assert(CE && CE->getOpcode() == Instruction::BitCast &&
@@ -4386,12 +4386,11 @@
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
- for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
-if (InvokeInst *Invoke = dyn_cast(I->getTerminator())) {
- // Mark landing pad.
- MachineBasicBlock *LandingPad = FuncInfo.MBBMap[Invoke->getSuccessor(1)];
- LandingPad->setIsLandingPad();
-}
+ if (ExceptionHandling)
+for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+ if (InvokeInst *Invoke = dyn_cast(I->getTerminator()))
+// Mark landing pad.
+FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
SelectBasicBlock(I, MF, FuncInfo);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.458 -> 1.459
---
Log message:
The fix that was applied for PR1224: http://llvm.org/PR1224 stops the compiler
crashing but breaks exception handling. The problem
described in PR1224: http://llvm.org/PR1224 is that invoke is a terminator that
can produce a value. The value may be needed in other
blocks. The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available. The fix that was applied was to do invoke
lowering earlier, before writing values to registers.
The problem this causes is that the code to copy values
to registers can be output after the invoke call. If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute. If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.
So revert the original fix and simply skip invoke values
in the general copying to registers code. Instead copy
the invoke value to a register in the invoke lowering code.
---
Diffs of the changes: (+25 -33)
SelectionDAGISel.cpp | 58 +--
1 files changed, 25 insertions(+), 33 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.458
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.459
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.458Thu Jun 7
16:07:15 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 13 00:51:31 2007
@@ -566,7 +566,6 @@
// These all get lowered before this pass.
void visitInvoke(InvokeInst &I);
- void visitInvoke(InvokeInst &I, bool AsTerminator);
void visitUnwind(UnwindInst &I);
void visitScalarBinary(User &I, unsigned OpCode);
@@ -1332,29 +1331,31 @@
}
void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
- assert(0 && "Should never be visited directly");
-}
-void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) {
// Retrieve successors.
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
+ MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
- if (!AsTerminator) {
-MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
-
-LowerCallTo(I, I.getCalledValue()->getType(),
-I.getCallingConv(),
-false,
-getValue(I.getOperand(0)),
-3, LandingPad);
-
-// Update successor info
-CurMBB->addSuccessor(Return);
-CurMBB->addSuccessor(LandingPad);
- } else {
-// Drop into normal successor.
-DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
-DAG.getBasicBlock(Return)));
+ LowerCallTo(I, I.getCalledValue()->getType(),
+ I.getCallingConv(),
+ false,
+ getValue(I.getOperand(0)),
+ 3, LandingPad);
+
+ // If the value of the invoke is used outside of its defining block, make it
+ // available as a virtual register.
+ if (!I.use_empty()) {
+DenseMap::iterator VMI =
FuncInfo.ValueMap.find(&I);
+if (VMI != FuncInfo.ValueMap.end())
+ DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
}
+
+ // Drop into normal successor.
+ DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
+ DAG.getBasicBlock(Return)));
+
+ // Update successor info
+ CurMBB->addSuccessor(Return);
+ CurMBB->addSuccessor(LandingPad);
}
void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
@@ -4546,15 +4547,11 @@
for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
I != E; ++I)
SDL.visit(*I);
-
- // Lower call part of invoke.
- InvokeInst *Invoke = dyn_cast(LLVMBB->getTerminator());
- if (Invoke) SDL.visitInvoke(*Invoke, false);
-
+
// Ensure that all instructions which are used outside of their defining
- // blocks are available as virtual registers.
+ // blocks are available as virtual registers. Invoke is handled elsewhere.
for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
-if (!I->use_empty() && !isa(I)) {
+if (!I->use_empty() && !isa(I) && !isa(I)) {
DenseMap::iterator VMI
=FuncInfo.ValueMap.find(I);
if (VMI != FuncInfo.ValueMap.end())
UnorderedChains.push_back(
@@ -4662,12 +4659,7 @@
}
// Lower the terminator after the copies are emitted.
- if (Invoke) {
-// Just the branch part of invoke.
-SDL.visitInvoke(*Invoke, true);
- } else {
-SDL.visit(*LLVMBB->getTerminator());
- }
+ SDL.visit(*LLVMBB->getTerminator());
// Copy over any CaseBlock records that may now exist due to SwitchInst
// lowering, as well as any jump table information.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.457 -> 1.458
---
Log message:
Do not change the size of function arguments. PR 1489: http://llvm.org/PR1489 .
---
Diffs of the changes: (+9 -1)
SelectionDAGISel.cpp | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.457
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.458
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.457Wed Jun 6
05:05:18 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 7 16:07:15 2007
@@ -3993,7 +3993,15 @@
Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
} else {
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
-Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
+// A true promotion would change the size of the argument.
+// Instead, pretend this is an int. If FP objects are not
+// passed the same as ints, the original type should be Legal
+// and we should not get here.
+Op = DAG.getNode(ISD::BIT_CONVERT,
+ VT==MVT::f32 ? MVT::i32 :
+ (VT==MVT::f64 ? MVT::i64 :
+ MVT::Other),
+ Op);
}
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.456 -> 1.457
---
Log message:
Additional fix for PR1422: http://llvm.org/PR1422 : make sure the landing pad
label is placed in the
correct machine basic block - do not rely on the eh.exception intrinsic
being in the landing pad: the loop optimizers can move it out.
---
Diffs of the changes: (+26 -15)
SelectionDAGISel.cpp | 41 ++---
1 files changed, 26 insertions(+), 15 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.456
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.457
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.456Sat Jun 2
11:53:42 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 6 05:05:18 2007
@@ -1337,12 +1337,10 @@
void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) {
// Retrieve successors.
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
- MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
-
+
if (!AsTerminator) {
-// Mark landing pad so that it doesn't get deleted in branch folding.
-LandingPad->setIsLandingPad();
-
+MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
+
LowerCallTo(I, I.getCalledValue()->getType(),
I.getCallingConv(),
false,
@@ -2577,16 +2575,10 @@
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
if (MMI) {
- // Add a label to mark the beginning of the landing pad. Deletion of the
- // landing pad can thus be detected via the MachineModuleInfo.
- unsigned LabelID = MMI->addLandingPad(CurMBB);
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
- DAG.getConstant(LabelID, MVT::i32)));
-
// Mark exception register as live in.
unsigned Reg = TLI.getExceptionAddressRegister();
if (Reg) CurMBB->addLiveIn(Reg);
-
+
// Insert the EXCEPTIONADDR instruction.
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDOperand Ops[1];
@@ -2626,7 +2618,7 @@
MMI->addFilterTypeInfo(CurMBB, TyInfo);
else
MMI->addCatchTypeInfo(CurMBB, TyInfo);
-
+
// Mark exception selector register as live in.
unsigned Reg = TLI.getExceptionSelectorRegister();
if (Reg) CurMBB->addLiveIn(Reg);
@@ -2788,7 +2780,7 @@
Args.push_back(Entry);
}
- if (ExceptionHandling) {
+ if (ExceptionHandling && MMI) {
// Insert a label before the invoke call to mark the try range. This can
be
// used to detect deletion of the invoke via the MachineModuleInfo.
BeginLabel = MMI->NextLabelID();
@@ -2805,7 +2797,7 @@
setValue(&I, Result.first);
DAG.setRoot(Result.second);
- if (ExceptionHandling) {
+ if (ExceptionHandling && MMI) {
// Insert a label at the end of the invoke call to mark the try range.
This
// can be used to detect deletion of the invoke via the MachineModuleInfo.
EndLabel = MMI->NextLabelID();
@@ -4387,6 +4379,13 @@
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+if (InvokeInst *Invoke = dyn_cast(I->getTerminator())) {
+ // Mark landing pad.
+ MachineBasicBlock *LandingPad = FuncInfo.MBBMap[Invoke->getSuccessor(1)];
+ LandingPad->setIsLandingPad();
+}
+
+ for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
SelectBasicBlock(I, MF, FuncInfo);
// Add function live-ins to entry block live-in set.
@@ -4523,6 +4522,18 @@
BB = FuncInfo.MBBMap[LLVMBB];
SDL.setCurrentBasicBlock(BB);
+ if (ExceptionHandling && BB->isLandingPad()) {
+MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+
+if (MMI) {
+ // Add a label to mark the beginning of the landing pad. Deletion of the
+ // landing pad can thus be detected via the MachineModuleInfo.
+ unsigned LabelID = MMI->addLandingPad(BB);
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
+ DAG.getConstant(LabelID, MVT::i32)));
+}
+ }
+
// Lower all of the non-terminator instructions.
for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
I != E; ++I)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.455 -> 1.456 --- Log message: Integrate exception filter support and exception catch support. This simplifies the code in DwarfWriter, allows for multiple filters and makes it trivial to specify filters accompanied by cleanups or catch-all specifications (see next patch). What a deal! Patch blessed by Anton. --- Diffs of the changes: (+4 -3) SelectionDAGISel.cpp |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.455 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.456 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.455Fri Jun 1 03:18:30 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Jun 2 11:53:42 2007 @@ -2611,8 +2611,6 @@ isa(CE->getOperand(0)) && "Personality should be a function"); MMI->addPersonality(CurMBB, cast(CE->getOperand(0))); - if (Intrinsic == Intrinsic::eh_filter) -MMI->setIsFilterLandingPad(CurMBB); // Gather all the type infos for this landing pad and pass them along to // MachineModuleInfo. @@ -2624,7 +2622,10 @@ "TypeInfo must be a global variable or NULL"); TyInfo.push_back(GV); } - MMI->addCatchTypeInfo(CurMBB, TyInfo); + if (Intrinsic == Intrinsic::eh_filter) +MMI->addFilterTypeInfo(CurMBB, TyInfo); + else +MMI->addCatchTypeInfo(CurMBB, TyInfo); // Mark exception selector register as live in. unsigned Reg = TLI.getExceptionSelectorRegister(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.454 -> 1.455
---
Log message:
Since TypeInfos are passed as i8 pointers, a NULL TypeInfo should be passed
as a null i8 pointer not as a 0 i32.
---
Diffs of the changes: (+2 -4)
SelectionDAGISel.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.454
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.455
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.454Thu May 24
09:36:04 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 1 03:18:30 2007
@@ -2620,8 +2620,7 @@
for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
Constant *C = cast(I.getOperand(i));
GlobalVariable *GV = ExtractGlobalVariable(C);
-assert (GV || (isa(C) &&
- cast(C)->isNullValue()) &&
+assert (GV || isa(C) &&
"TypeInfo must be a global variable or NULL");
TyInfo.push_back(GV);
}
@@ -2653,8 +2652,7 @@
// Find the type id for the given typeinfo.
Constant *C = cast(I.getOperand(1));
GlobalVariable *GV = ExtractGlobalVariable(C);
- assert (GV || (isa(C) &&
- cast(C)->isNullValue()) &&
+ assert (GV || isa(C) &&
"TypeInfo must be a global variable or NULL");
unsigned TypeID = MMI->getTypeIDFor(GV);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.453 -> 1.454
---
Log message:
Minor comment cleanups.
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.453
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.454
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.453Wed May 23
06:08:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu May 24 09:36:04 2007
@@ -770,7 +770,7 @@
Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
PTyElementVT));
} else if (PTyElementVT < PTyLegalElementVT) {
- // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
+ // If the register was promoted, use TRUNCATE or FP_ROUND as appropriate.
for (unsigned i = 0; i != NE; ++i) {
SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
PTyElementVT);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.452 -> 1.453
---
Log message:
Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP
info too. This fixes PR1439: http://llvm.org/PR1439
---
Diffs of the changes: (+38 -33)
SelectionDAGISel.cpp | 71 +++
1 files changed, 38 insertions(+), 33 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.452
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.453
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.452Fri May 18
12:52:13 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 23 06:08:31 2007
@@ -529,8 +529,9 @@
void ExportFromCurrentBlock(Value *V);
void LowerCallTo(Instruction &I,
const Type *CalledValueTy, unsigned CallingConv,
- bool IsTailCall, SDOperand Callee, unsigned OpIdx);
-
+ bool IsTailCall, SDOperand Callee, unsigned OpIdx,
+ MachineBasicBlock *LandingPad = NULL);
+
// Terminator instructions.
void visitRet(ReturnInst &I);
void visitBr(BranchInst &I);
@@ -1341,31 +1342,13 @@
if (!AsTerminator) {
// Mark landing pad so that it doesn't get deleted in branch folding.
LandingPad->setIsLandingPad();
-
-// Insert a label before the invoke call to mark the try range.
-// This can be used to detect deletion of the invoke via the
-// MachineModuleInfo.
-MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-unsigned BeginLabel = MMI->NextLabelID();
-DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
-DAG.getConstant(BeginLabel, MVT::i32)));
-
+
LowerCallTo(I, I.getCalledValue()->getType(),
- I.getCallingConv(),
- false,
- getValue(I.getOperand(0)),
- 3);
-
-// Insert a label before the invoke call to mark the try range.
-// This can be used to detect deletion of the invoke via the
-// MachineModuleInfo.
-unsigned EndLabel = MMI->NextLabelID();
-DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
-DAG.getConstant(EndLabel, MVT::i32)));
-
-// Inform MachineModuleInfo of range.
-MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
-
+I.getCallingConv(),
+false,
+getValue(I.getOperand(0)),
+3, LandingPad);
+
// Update successor info
CurMBB->addSuccessor(Return);
CurMBB->addSuccessor(LandingPad);
@@ -2782,11 +2765,14 @@
const Type *CalledValueTy,
unsigned CallingConv,
bool IsTailCall,
- SDOperand Callee, unsigned OpIdx) {
+ SDOperand Callee, unsigned OpIdx,
+ MachineBasicBlock *LandingPad) {
const PointerType *PT = cast(CalledValueTy);
const FunctionType *FTy = cast(PT->getElementType());
const ParamAttrsList *Attrs = FTy->getParamAttrs();
-
+ MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+ unsigned BeginLabel = 0, EndLabel = 0;
+
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
Args.reserve(I.getNumOperands());
@@ -2803,6 +2789,14 @@
Args.push_back(Entry);
}
+ if (ExceptionHandling) {
+// Insert a label before the invoke call to mark the try range. This can
be
+// used to detect deletion of the invoke via the MachineModuleInfo.
+BeginLabel = MMI->NextLabelID();
+DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+DAG.getConstant(BeginLabel, MVT::i32)));
+ }
+
std::pair Result =
TLI.LowerCallTo(getRoot(), I.getType(),
Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
@@ -2811,6 +2805,17 @@
if (I.getType() != Type::VoidTy)
setValue(&I, Result.first);
DAG.setRoot(Result.second);
+
+ if (ExceptionHandling) {
+// Insert a label at the end of the invoke call to mark the try range.
This
+// can be used to detect deletion of the invoke via the MachineModuleInfo.
+EndLabel = MMI->NextLabelID();
+DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+DAG.getConstant(EndLabel, MVT::i32)));
+
+// Inform MachineModuleInfo of range.
+MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
+ }
}
@@ -2871,12 +2876,12 @@
Callee = getValue(I.getOperand(0));
else
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
-
+
LowerCallTo(I, I.getCalledValue()->getType(),
- I.getCa
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.450 -> 1.451
---
Log message:
Fix some subtle issues handling immediate values. This fixes
test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
---
Diffs of the changes: (+6 -3)
SelectionDAGISel.cpp |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.450
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.451
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.450Wed May 9
15:07:09 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon May 14 20:33:58 2007
@@ -3448,7 +3448,8 @@
// Add information to the INLINEASM node to know about this output.
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
-AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
+AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+TLI.getPointerTy()));
AsmNodeOperands.push_back(OpInfo.CallOperand);
break;
}
@@ -3540,7 +3541,8 @@
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
-AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
+AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+TLI.getPointerTy()));
AsmNodeOperands.push_back(InOperandVal);
break;
} else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
@@ -3550,7 +3552,8 @@
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
-AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
+AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+TLI.getPointerTy()));
AsmNodeOperands.push_back(InOperandVal);
break;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.449 -> 1.450
---
Log message:
Do not assert, when case range split metric is zero and JTs are not allowed:
just emit binary tree in this case. This
fixes PR1403: http://llvm.org/PR1403 .
---
Diffs of the changes: (+12 -5)
SelectionDAGISel.cpp | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.449
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.450
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.449Mon May 7
15:49:28 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 9 15:07:09 2007
@@ -1462,6 +1462,11 @@
return true;
}
+static inline bool areJTsAllowed(const TargetLowering &TLI) {
+ return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
+ TLI.isOperationLegal(ISD::BRIND, MVT::Other));
+}
+
/// handleJTSwitchCase - Emit jumptable for current switch case range
bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
@@ -1478,9 +1483,7 @@
I!=E; ++I)
TSize += I->size();
- if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) &&
- !TLI.isOperationLegal(ISD::BRIND, MVT::Other)) ||
- TSize <= 3)
+ if (!areJTsAllowed(TLI) || TSize <= 3)
return false;
double Density = (double)TSize / (double)((Last - First) + 1ULL);
@@ -1622,8 +1625,12 @@
LSize += J->size();
RSize -= J->size();
}
- // If our case is dense we *really* should handle it earlier!
- assert((FMetric > 0) && "Should handle dense range earlier!");
+ if (areJTsAllowed(TLI)) {
+// If our case is dense we *really* should handle it earlier!
+assert((FMetric > 0) && "Should handle dense range earlier!");
+ } else {
+Pivot = CR.Range.first + Size/2;
+ }
CaseRange LHSR(CR.Range.first, Pivot);
CaseRange RHSR(Pivot, CR.Range.second);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.448 -> 1.449 --- Log message: Parameter attributes on invoke calls were being lost due to the wrong attribute index being used. Fix proposed by Anton Korobeynikov, who asked me to implement and commit it for him. This is PR1398: http://llvm.org/PR1398 . --- Diffs of the changes: (+6 -4) SelectionDAGISel.cpp | 10 ++ 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.448 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.449 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.448Sun May 6 15:14:21 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon May 7 15:49:28 2007 @@ -2787,10 +2787,12 @@ Value *Arg = I.getOperand(i); SDOperand ArgNode = getValue(Arg); Entry.Node = ArgNode; Entry.Ty = Arg->getType(); -Entry.isSExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::SExt); -Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::ZExt); -Entry.isInReg = Attrs && Attrs->paramHasAttr(i, ParamAttr::InReg); -Entry.isSRet = Attrs && Attrs->paramHasAttr(i, ParamAttr::StructRet); + +unsigned attrInd = i - OpIdx + 1; +Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt); +Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt); +Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg); +Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet); Args.push_back(Entry); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.447 -> 1.448
---
Log message:
Detabify
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.447
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.448
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.447Fri May 4
12:12:26 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun May 6 15:14:21 2007
@@ -2628,7 +2628,7 @@
// MachineModuleInfo.
std::vector TyInfo;
for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
- Constant *C = cast(I.getOperand(i));
+Constant *C = cast(I.getOperand(i));
GlobalVariable *GV = ExtractGlobalVariable(C);
assert (GV || (isa(C) &&
cast(C)->isNullValue()) &&
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.446 -> 1.447
---
Log message:
A bitcast of a global variable may have been constant folded to a GEP -
handle this case too.
---
Diffs of the changes: (+30 -26)
SelectionDAGISel.cpp | 56 +++
1 files changed, 30 insertions(+), 26 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.446
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.447
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.446Wed May 2
20:11:53 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri May 4 12:12:26 2007
@@ -2457,6 +2457,24 @@
}
}
+/// ExtractGlobalVariable - If C is a global variable, or a bitcast of one
+/// (possibly constant folded), return it. Otherwise return NULL.
+static GlobalVariable *ExtractGlobalVariable (Constant *C) {
+ if (GlobalVariable *GV = dyn_cast(C))
+return GV;
+ else if (ConstantExpr *CE = dyn_cast(C)) {
+if (CE->getOpcode() == Instruction::BitCast)
+ return dyn_cast(CE->getOperand(0));
+else if (CE->getOpcode() == Instruction::GetElementPtr) {
+ for (unsigned i = 1, e = CE->getNumOperands(); i != e; ++i)
+if (!CE->getOperand(i)->isNullValue())
+ return NULL;
+ return dyn_cast(CE->getOperand(0));
+}
+ }
+ return NULL;
+}
+
/// visitIntrinsicCall - Lower the call to the specified intrinsic function.
If
/// we want to emit this as a call to a named external function, return the
name
/// otherwise lower it and return null.
@@ -2610,20 +2628,12 @@
// MachineModuleInfo.
std::vector TyInfo;
for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
-Constant *C = cast(I.getOperand(i));
-if (GlobalVariable *GV = dyn_cast(C)) {
- TyInfo.push_back(GV);
-} else if (ConstantExpr *CE = dyn_cast(C)) {
- assert(CE->getOpcode() == Instruction::BitCast &&
- isa(CE->getOperand(0))
- && "TypeInfo must be a global variable or NULL");
- TyInfo.push_back(cast(CE->getOperand(0)));
-} else {
- ConstantInt *CI = dyn_cast(C);
- assert(CI && CI->isNullValue() &&
- "TypeInfo must be a global variable or NULL");
- TyInfo.push_back(NULL);
-}
+ Constant *C = cast(I.getOperand(i));
+GlobalVariable *GV = ExtractGlobalVariable(C);
+assert (GV || (isa(C) &&
+ cast(C)->isNullValue()) &&
+"TypeInfo must be a global variable or NULL");
+TyInfo.push_back(GV);
}
MMI->addCatchTypeInfo(CurMBB, TyInfo);
@@ -2651,18 +2661,12 @@
if (MMI) {
// Find the type id for the given typeinfo.
- GlobalVariable *GV = NULL;
- ConstantExpr *CE = dyn_cast(I.getOperand(1));
- if (CE && CE->getOpcode() == Instruction::BitCast &&
- isa(CE->getOperand(0))) {
-GV = cast(CE->getOperand(0));
- } else {
-ConstantInt *CI = dyn_cast(I.getOperand(1));
-assert(CI && CI->getZExtValue() == 0 &&
- "TypeInfo must be a global variable typeinfo or NULL");
-GV = NULL;
- }
-
+ Constant *C = cast(I.getOperand(1));
+ GlobalVariable *GV = ExtractGlobalVariable(C);
+ assert (GV || (isa(C) &&
+ cast(C)->isNullValue()) &&
+ "TypeInfo must be a global variable or NULL");
+
unsigned TypeID = MMI->getTypeIDFor(GV);
setValue(&I, DAG.getConstant(TypeID, MVT::i32));
} else {
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.445 -> 1.446 --- Log message: Drop 'const' --- Diffs of the changes: (+1 -1) SelectionDAGISel.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.445 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.446 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.445Wed May 2 17:15:48 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 2 20:11:53 2007 @@ -5012,4 +5012,4 @@ Ops.push_back(InOps.back()); } -const char SelectionDAGISel::ID = 0; +char SelectionDAGISel::ID = 0; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.444 -> 1.445
---
Log message:
Properly set arguments bitwidth of EHSELECT node
---
Diffs of the changes: (+2 -2)
SelectionDAGISel.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.444
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.445
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.444Wed May 2
16:39:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 2 17:15:48 2007
@@ -2632,7 +2632,7 @@
if (Reg) CurMBB->addLiveIn(Reg);
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDOperand Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -2640,7 +2640,7 @@
setValue(&I, Op);
DAG.setRoot(Op.getValue(1));
} else {
- setValue(&I, DAG.getConstant(0, MVT::i32));
+ setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
}
return 0;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.443 -> 1.444 --- Log message: Use 'static const char' instead of 'static const int'. Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. --- Diffs of the changes: (+1 -1) SelectionDAGISel.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.443 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.444 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.443Tue May 1 16:15:46 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 2 16:39:19 2007 @@ -5012,4 +5012,4 @@ Ops.push_back(InOps.back()); } -const int SelectionDAGISel::ID = 0; +const char SelectionDAGISel::ID = 0; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.442 -> 1.443 --- Log message: Do not use typeinfo to identify pass in pass manager. --- Diffs of the changes: (+2 -0) SelectionDAGISel.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.442 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.443 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.442Mon Apr 30 16:11:17 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 1 16:15:46 2007 @@ -5011,3 +5011,5 @@ if (e != InOps.size()) Ops.push_back(InOps.back()); } + +const int SelectionDAGISel::ID = 0; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.441 -> 1.442
---
Log message:
Continue refactoring inline asm code. If there is an earlyclobber output
register, preallocate all input registers and the early clobbered output.
This fixes PR1357: http://llvm.org/PR1357 and
CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
---
Diffs of the changes: (+108 -79)
SelectionDAGISel.cpp | 187 +--
1 files changed, 108 insertions(+), 79 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.441
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.442
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.441Mon Apr 30
12:29:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 30 16:11:17 2007
@@ -518,10 +518,9 @@
N = NewN;
}
- RegsForValue GetRegistersForValue(AsmOperandInfo &OpInfo,
-bool OutReg, bool InReg,
-std::set &OutputRegs,
-std::set &InputRegs);
+ void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
+std::set &OutputRegs,
+std::set &InputRegs);
void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
@@ -3035,6 +3034,10 @@
/// ConstraintVT - The ValueType for the operand value.
MVT::ValueType ConstraintVT;
+ /// AssignedRegs - If this is a register or register class operand, this
+ /// contains the set of register corresponding to the operand.
+ RegsForValue AssignedRegs;
+
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
: InlineAsm::ConstraintInfo(info),
ConstraintType(TargetLowering::C_Unknown),
@@ -3042,6 +3045,17 @@
}
void ComputeConstraintToUse(const TargetLowering &TLI);
+
+ /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
+ /// busy in OutputRegs/InputRegs.
+ void MarkAllocatedRegs(bool isOutReg, bool isInReg,
+ std::set &OutputRegs,
+ std::set &InputRegs) const {
+ if (isOutReg)
+ OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
+ if (isInReg)
+ InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
+ }
};
} // end anon namespace.
@@ -3093,13 +3107,42 @@
}
-RegsForValue SelectionDAGLowering::
-GetRegistersForValue(AsmOperandInfo &OpInfo, bool isOutReg, bool isInReg,
+void SelectionDAGLowering::
+GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
std::set &OutputRegs,
std::set &InputRegs) {
- std::pair PhysReg =
-
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,OpInfo.ConstraintVT);
+ // Compute whether this value requires an input register, an output register,
+ // or both.
+ bool isOutReg = false;
+ bool isInReg = false;
+ switch (OpInfo.Type) {
+ case InlineAsm::isOutput:
+isOutReg = true;
+
+// If this is an early-clobber output, or if there is an input
+// constraint that matches this, we need to reserve the input register
+// so no other inputs allocate to it.
+isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
+break;
+ case InlineAsm::isInput:
+isInReg = true;
+isOutReg = false;
+break;
+ case InlineAsm::isClobber:
+isOutReg = true;
+isInReg = true;
+break;
+ }
+
+
+ MachineFunction &MF = DAG.getMachineFunction();
std::vector Regs;
+
+ // If this is a constraint for a single physreg, or a constraint for a
+ // register class, find it.
+ std::pair PhysReg =
+TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
+ OpInfo.ConstraintVT);
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other)
@@ -3107,7 +3150,6 @@
MVT::ValueType RegVT;
MVT::ValueType ValueVT = OpInfo.ConstraintVT;
- MachineFunction &MF = DAG.getMachineFunction();
// If this is a constraint for a specific physical register, like {r17},
// assign it now.
@@ -3137,7 +3179,9 @@
Regs.push_back(*I);
}
}
-return RegsForValue(Regs, RegVT, ValueVT);
+OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
+OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
+return;
}
// Otherwise, if this was a reference to an LLVM register class, create vregs
@@ -3147,7 +3191,11 @@
// If this is an early clobber or tied register, our regalloc doesn't know
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the regalloc do the right thing.
-if (!isOutReg || !isInReg) {
+if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.440 -> 1.441
---
Log message:
refactor GetRegistersForValue to take OpInfo as an argument instead of various
pieces of it. No functionality change.
---
Diffs of the changes: (+101 -98)
SelectionDAGISel.cpp | 199 +--
1 files changed, 101 insertions(+), 98 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.440
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.441
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.440Mon Apr 30
12:16:27 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 30 12:29:31 2007
@@ -82,6 +82,8 @@
createDefaultScheduler);
} // namespace
+namespace { struct AsmOperandInfo; }
+
namespace {
/// RegsForValue - This struct represents the physical registers that a
/// particular value is assigned and the type information about the value.
@@ -516,8 +518,7 @@
N = NewN;
}
- RegsForValue GetRegistersForValue(const std::string &ConstrCode,
-MVT::ValueType VT,
+ RegsForValue GetRegistersForValue(AsmOperandInfo &OpInfo,
bool OutReg, bool InReg,
std::set &OutputRegs,
std::set &InputRegs);
@@ -3013,23 +3014,105 @@
return FoundRC;
}
+
+namespace {
+/// AsmOperandInfo - This contains information for each constraint that we are
+/// lowering.
+struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
+ /// ConstraintCode - This contains the actual string for the code, like "m".
+ std::string ConstraintCode;
+
+ /// ConstraintType - Information about the constraint code, e.g. Register,
+ /// RegisterClass, Memory, Other, Unknown.
+ TargetLowering::ConstraintType ConstraintType;
+
+ /// CallOperand/CallOperandval - If this is the result output operand or a
+ /// clobber, this is null, otherwise it is the incoming operand to the
+ /// CallInst. This gets modified as the asm is processed.
+ SDOperand CallOperand;
+ Value *CallOperandVal;
+
+ /// ConstraintVT - The ValueType for the operand value.
+ MVT::ValueType ConstraintVT;
+
+ AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
+: InlineAsm::ConstraintInfo(info),
+ ConstraintType(TargetLowering::C_Unknown),
+ CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
+ }
+
+ void ComputeConstraintToUse(const TargetLowering &TLI);
+};
+} // end anon namespace.
+
+/// getConstraintGenerality - Return an integer indicating how general CT is.
+static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
+ switch (CT) {
+default: assert(0 && "Unknown constraint type!");
+case TargetLowering::C_Other:
+case TargetLowering::C_Unknown:
+ return 0;
+case TargetLowering::C_Register:
+ return 1;
+case TargetLowering::C_RegisterClass:
+ return 2;
+case TargetLowering::C_Memory:
+ return 3;
+ }
+}
+
+void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
+ assert(!Codes.empty() && "Must have at least one constraint");
+
+ std::string *Current = &Codes[0];
+ TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
+ if (Codes.size() == 1) { // Single-letter constraints ('r') are very
common.
+ConstraintCode = *Current;
+ConstraintType = CurType;
+return;
+ }
+
+ unsigned CurGenerality = getConstraintGenerality(CurType);
+
+ // If we have multiple constraints, try to pick the most general one ahead
+ // of time. This isn't a wonderful solution, but handles common cases.
+ for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
+TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
+unsigned ThisGenerality = getConstraintGenerality(ThisType);
+if (ThisGenerality > CurGenerality) {
+ // This constraint letter is more general than the previous one,
+ // use it.
+ CurType = ThisType;
+ Current = &Codes[j];
+ CurGenerality = ThisGenerality;
+}
+ }
+
+ ConstraintCode = *Current;
+ ConstraintType = CurType;
+}
+
+
RegsForValue SelectionDAGLowering::
-GetRegistersForValue(const std::string &ConstrCode,
- MVT::ValueType VT, bool isOutReg, bool isInReg,
+GetRegistersForValue(AsmOperandInfo &OpInfo, bool isOutReg, bool isInReg,
std::set &OutputRegs,
std::set &InputRegs) {
std::pair PhysReg =
-TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
+
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,OpInfo.ConstraintVT);
std::vector Regs;
- unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
+ unsigned NumRegs = 1;
+ if (OpInfo.ConstraintVT != MVT::Other)
+NumRegs = TLI.getNumElement
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.439 -> 1.440
---
Log message:
refactor some code, no functionality change
---
Diffs of the changes: (+52 -44)
SelectionDAGISel.cpp | 96 +++
1 files changed, 52 insertions(+), 44 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.439
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.440
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.439Sun Apr 29
13:58:03 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 30 12:16:27 2007
@@ -3134,44 +3134,6 @@
return RegsForValue();
}
-/// getConstraintGenerality - Return an integer indicating how general CT is.
-static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
- switch (CT) {
- default: assert(0 && "Unknown constraint type!");
- case TargetLowering::C_Other:
- case TargetLowering::C_Unknown:
-return 0;
- case TargetLowering::C_Register:
-return 1;
- case TargetLowering::C_RegisterClass:
-return 2;
- case TargetLowering::C_Memory:
-return 3;
- }
-}
-
-static std::string GetMostGeneralConstraint(std::vector &C,
-const TargetLowering &TLI) {
- assert(!C.empty() && "Must have at least one constraint");
- if (C.size() == 1) return C[0];
-
- std::string *Current = &C[0];
- // If we have multiple constraints, try to pick the most general one ahead
- // of time. This isn't a wonderful solution, but handles common cases.
- TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
- for (unsigned j = 1, e = C.size(); j != e; ++j) {
-TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
-if (getConstraintGenerality(ThisFlavor) >
-getConstraintGenerality(Flavor)) {
- // This constraint letter is more general than the previous one,
- // use it.
- Flavor = ThisFlavor;
- Current = &C[j];
-}
- }
- return *Current;
-}
-
namespace {
/// AsmOperandInfo - This contains information for each constraint that we are
/// lowering.
@@ -3197,9 +3159,59 @@
ConstraintType(TargetLowering::C_Unknown),
CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
}
+
+ void ComputeConstraintToUse(const TargetLowering &TLI);
};
} // end anon namespace.
+/// getConstraintGenerality - Return an integer indicating how general CT is.
+static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
+ switch (CT) {
+default: assert(0 && "Unknown constraint type!");
+case TargetLowering::C_Other:
+case TargetLowering::C_Unknown:
+ return 0;
+case TargetLowering::C_Register:
+ return 1;
+case TargetLowering::C_RegisterClass:
+ return 2;
+case TargetLowering::C_Memory:
+ return 3;
+ }
+}
+
+void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
+ assert(!Codes.empty() && "Must have at least one constraint");
+
+ std::string *Current = &Codes[0];
+ TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
+ if (Codes.size() == 1) { // Single-letter constraints ('r') are very
common.
+ConstraintCode = *Current;
+ConstraintType = CurType;
+return;
+ }
+
+ unsigned CurGenerality = getConstraintGenerality(CurType);
+
+ // If we have multiple constraints, try to pick the most general one ahead
+ // of time. This isn't a wonderful solution, but handles common cases.
+ for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
+TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
+unsigned ThisGenerality = getConstraintGenerality(ThisType);
+if (ThisGenerality > CurGenerality) {
+ // This constraint letter is more general than the previous one,
+ // use it.
+ CurType = ThisType;
+ Current = &Codes[j];
+ CurGenerality = ThisGenerality;
+}
+ }
+
+ ConstraintCode = *Current;
+ ConstraintType = CurType;
+}
+
+
/// visitInlineAsm - Handle a call to an InlineAsm object.
///
void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
@@ -3274,12 +3286,8 @@
OpInfo.ConstraintVT = OpVT;
-// Compute the constraint code to use.
-OpInfo.ConstraintCode = GetMostGeneralConstraint(OpInfo.Codes, TLI);
-
-// Compute the constraint type.
-// FIXME: merge this into GetMostGeneralConstraint.
-OpInfo.ConstraintType = TLI.getConstraintType(OpInfo.ConstraintCode);
+// Compute the constraint code and ConstraintType to use.
+OpInfo.ComputeConstraintToUse(TLI);
// If this is a memory input, and if the operand is not indirect, do what
we
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.438 -> 1.439
---
Log message:
generalize aggregate handling
---
Diffs of the changes: (+21 -5)
SelectionDAGISel.cpp | 26 +-
1 files changed, 21 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.438
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.439
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.438Sat Apr 28
16:12:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Apr 29 13:58:03 2007
@@ -3248,12 +3248,28 @@
if (OpInfo.CallOperandVal) {
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
const Type *OpTy = OpInfo.CallOperandVal->getType();
- if (!OpInfo.isIndirect) {
-// Must be an input.
-OpVT = TLI.getValueType(OpTy);
- } else {
-OpVT =
TLI.getValueType(cast(OpTy)->getElementType(),true);
+ // If this is an indirect operand, the operand is a pointer to the
+ // accessed type.
+ if (OpInfo.isIndirect)
+OpTy = cast(OpTy)->getElementType();
+
+ // If OpTy is not a first-class value, it may be a struct/union that we
+ // can tile with integers.
+ if (!OpTy->isFirstClassType() && OpTy->isSized()) {
+unsigned BitSize = TD->getTypeSizeInBits(OpTy);
+switch (BitSize) {
+default: break;
+case 1:
+case 8:
+case 16:
+case 32:
+case 64:
+ OpTy = IntegerType::get(BitSize);
+ break;
+}
}
+
+ OpVT = TLI.getValueType(OpTy, true);
}
OpInfo.ConstraintVT = OpVT;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.437 -> 1.438
---
Log message:
memory operands that have a direct operand should have their stores created
before the copies into physregs are done. This avoids having flag operands
skip the store, causing cycles in the dag at sched time. This fixes infinite
loops on these tests:
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308:
http://llvm.org/PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828:
http://llvm.org/PR828
---
Diffs of the changes: (+42 -35)
SelectionDAGISel.cpp | 77 +++
1 files changed, 42 insertions(+), 35 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.437
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.438
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.437Sat Apr 28
16:03:16 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 16:12:06 2007
@@ -3265,6 +3265,45 @@
// FIXME: merge this into GetMostGeneralConstraint.
OpInfo.ConstraintType = TLI.getConstraintType(OpInfo.ConstraintCode);
+
+// If this is a memory input, and if the operand is not indirect, do what
we
+// need to to provide an address for the memory input.
+if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
+!OpInfo.isIndirect) {
+ assert(OpInfo.Type == InlineAsm::isInput &&
+ "Can only indirectify direct input operands!");
+
+ // Memory operands really want the address of the value. If we don't
have
+ // an indirect input, put it in the constpool if we can, otherwise spill
+ // it to a stack slot.
+
+ // If the operand is a float, integer, or vector constant, spill to a
+ // constant pool entry to get its address.
+ Value *OpVal = OpInfo.CallOperandVal;
+ if (isa(OpVal) || isa(OpVal) ||
+ isa(OpVal)) {
+OpInfo.CallOperand = DAG.getConstantPool(cast(OpVal),
+ TLI.getPointerTy());
+ } else {
+// Otherwise, create a stack slot and emit a store to it before the
+// asm.
+const Type *Ty = OpVal->getType();
+uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
+unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
+MachineFunction &MF = DAG.getMachineFunction();
+int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
+SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
+Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
+OpInfo.CallOperand = StackSlot;
+ }
+
+ // There is no longer a Value* corresponding to this operand.
+ OpInfo.CallOperandVal = 0;
+ // It is now an indirect operand.
+ OpInfo.isIndirect = true;
+}
+
+
if (TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpVT).first
==0)
continue; // Not assigned a fixed reg.
@@ -3323,19 +3362,12 @@
if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
OpInfo.ConstraintType != TargetLowering::C_Register) {
// Memory output, or 'other' output (e.g. 'X' constraint).
-SDOperand InOperandVal = OpInfo.CallOperand;
-
-// Check that the operand (the address to store to) isn't a float.
-if (!MVT::isInteger(InOperandVal.getValueType()))
- assert(0 && "MATCH FAIL!");
-
-if (!OpInfo.isIndirect)
- assert(0 && "MATCH FAIL!");
+assert(OpInfo.isIndirect && "Memory output must be indirect operand");
// Add information to the INLINEASM node to know about this output.
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
-AsmNodeOperands.push_back(InOperandVal);
+AsmNodeOperands.push_back(OpInfo.CallOperand);
break;
}
@@ -3440,32 +3472,7 @@
AsmNodeOperands.push_back(InOperandVal);
break;
} else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
-// Memory input. Memory operands really want the address of the value,
-// so we want an indirect input. If we don't have an indirect input,
-// spill the value somewhere if we can, otherwise spill it to a stack
-// slot.
-if (!OpInfo.isIndirect) {
- // If the operand is a float, integer, or vector constant, spill to a
- // constant pool entry to get its address.
- Value *OpVal = OpInfo.CallOperandVal;
- if (isa(OpVal) || isa(OpVal) ||
- isa(OpVal)) {
-InOperandVal = DAG.getConstantPool(cast(OpVal),
-
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.436 -> 1.437
---
Log message:
eliminate more redundant constraint type analysis
---
Diffs of the changes: (+2 -6)
SelectionDAGISel.cpp |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.436
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.437
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.436Sat Apr 28
16:01:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 16:03:16 2007
@@ -3320,12 +3320,8 @@
switch (OpInfo.Type) {
case InlineAsm::isOutput: {
- TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
- if (OpInfo.ConstraintCode.size() == 1) // not a physreg name.
-CTy = TLI.getConstraintType(OpInfo.ConstraintCode);
-
- if (CTy != TargetLowering::C_RegisterClass &&
- CTy != TargetLowering::C_Register) {
+ if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
+ OpInfo.ConstraintType != TargetLowering::C_Register) {
// Memory output, or 'other' output (e.g. 'X' constraint).
SDOperand InOperandVal = OpInfo.CallOperand;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.435 -> 1.436
---
Log message:
merge constraint type analysis stuff together.
---
Diffs of the changes: (+21 -14)
SelectionDAGISel.cpp | 35 +--
1 files changed, 21 insertions(+), 14 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.435
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.436
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.435Sat Apr 28
15:49:53 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 16:01:43 2007
@@ -3178,6 +3178,10 @@
struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
/// ConstraintCode - This contains the actual string for the code, like "m".
std::string ConstraintCode;
+
+ /// ConstraintType - Information about the constraint code, e.g. Register,
+ /// RegisterClass, Memory, Other, Unknown.
+ TargetLowering::ConstraintType ConstraintType;
/// CallOperand/CallOperandval - If this is the result output operand or a
/// clobber, this is null, otherwise it is the incoming operand to the
@@ -3189,7 +3193,8 @@
MVT::ValueType ConstraintVT;
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
-: InlineAsm::ConstraintInfo(info),
+: InlineAsm::ConstraintInfo(info),
+ ConstraintType(TargetLowering::C_Unknown),
CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
}
};
@@ -3217,9 +3222,6 @@
ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
AsmOperandInfo &OpInfo = ConstraintOperands.back();
-// Compute the constraint code to use.
-OpInfo.ConstraintCode = GetMostGeneralConstraint(OpInfo.Codes, TLI);
-
MVT::ValueType OpVT = MVT::Other;
// Compute the value type for each operand.
@@ -3255,6 +3257,13 @@
}
OpInfo.ConstraintVT = OpVT;
+
+// Compute the constraint code to use.
+OpInfo.ConstraintCode = GetMostGeneralConstraint(OpInfo.Codes, TLI);
+
+// Compute the constraint type.
+// FIXME: merge this into GetMostGeneralConstraint.
+OpInfo.ConstraintType = TLI.getConstraintType(OpInfo.ConstraintCode);
if (TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpVT).first
==0)
continue; // Not assigned a fixed reg.
@@ -3315,7 +3324,8 @@
if (OpInfo.ConstraintCode.size() == 1) // not a physreg name.
CTy = TLI.getConstraintType(OpInfo.ConstraintCode);
- if (CTy != TargetLowering::C_RegisterClass) {
+ if (CTy != TargetLowering::C_RegisterClass &&
+ CTy != TargetLowering::C_Register) {
// Memory output, or 'other' output (e.g. 'X' constraint).
SDOperand InOperandVal = OpInfo.CallOperand;
@@ -,8 +3343,7 @@
break;
}
- // Otherwise, this is a register output.
- assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
+ // Otherwise, this is a register or register class output.
// If this is an early-clobber output, or if there is an input
// constraint that matches this, we need to reserve the input register
@@ -3416,11 +3425,7 @@
}
}
- TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
- if (OpInfo.ConstraintCode.size() == 1) // not a physreg name.
-CTy = TLI.getConstraintType(OpInfo.ConstraintCode);
-
- if (CTy == TargetLowering::C_Other) {
+ if (OpInfo.ConstraintType == TargetLowering::C_Other) {
assert(!OpInfo.isIndirect &&
"Don't know how to handle indirect other inputs yet!");
@@ -3438,7 +3443,7 @@
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
AsmNodeOperands.push_back(InOperandVal);
break;
- } else if (CTy == TargetLowering::C_Memory) {
+ } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
// Memory input. Memory operands really want the address of the value,
// so we want an indirect input. If we don't have an indirect input,
// spill the value somewhere if we can, otherwise spill it to a stack
@@ -3475,7 +3480,9 @@
break;
}
- assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
+ assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
+ OpInfo.ConstraintType == TargetLowering::C_Register) &&
+ "Unknown constraint type!");
assert(!OpInfo.isIndirect &&
"Don't know how to handle indirect register inputs yet!");
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.434 -> 1.435
---
Log message:
Significant refactoring of the inline asm stuff, to support future changes.
No functionality change.
---
Diffs of the changes: (+107 -82)
SelectionDAGISel.cpp | 189 ---
1 files changed, 107 insertions(+), 82 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.434
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.435
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.434Sat Apr 28
01:42:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 15:49:53 2007
@@ -3172,85 +3172,109 @@
return *Current;
}
+namespace {
+/// AsmOperandInfo - This contains information for each constraint that we are
+/// lowering.
+struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
+ /// ConstraintCode - This contains the actual string for the code, like "m".
+ std::string ConstraintCode;
+
+ /// CallOperand/CallOperandval - If this is the result output operand or a
+ /// clobber, this is null, otherwise it is the incoming operand to the
+ /// CallInst. This gets modified as the asm is processed.
+ SDOperand CallOperand;
+ Value *CallOperandVal;
+
+ /// ConstraintVT - The ValueType for the operand value.
+ MVT::ValueType ConstraintVT;
+
+ AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
+: InlineAsm::ConstraintInfo(info),
+ CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
+ }
+};
+} // end anon namespace.
/// visitInlineAsm - Handle a call to an InlineAsm object.
///
void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
InlineAsm *IA = cast(I.getOperand(0));
-
- SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
- MVT::Other);
- std::vector Constraints = IA->ParseConstraints();
- std::vector ConstraintVTs;
-
- /// AsmNodeOperands - A list of pairs. The first element is a register, the
- /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
- /// if it is a def of that register.
- std::vector AsmNodeOperands;
- AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
- AsmNodeOperands.push_back(AsmStr);
+ /// ConstraintOperands - Information about all of the constraints.
+ std::vector ConstraintOperands;
SDOperand Chain = getRoot();
SDOperand Flag;
- // We fully assign registers here at isel time. This is not optimal, but
- // should work. For register classes that correspond to LLVM classes, we
- // could let the LLVM RA do its thing, but we currently don't. Do a prepass
- // over the constraints, collecting fixed registers that we know we can't
use.
std::set OutputRegs, InputRegs;
- unsigned OpNum = 1;
- for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
-std::string ConstraintCode =
- GetMostGeneralConstraint(Constraints[i].Codes, TLI);
+
+ // Do a prepass over the constraints, canonicalizing them, and building up
the
+ // ConstraintOperands list.
+ std::vector
+ConstraintInfos = IA->ParseConstraints();
+ unsigned OpNo = 1;
+ for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
+ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
+AsmOperandInfo &OpInfo = ConstraintOperands.back();
+
+// Compute the constraint code to use.
+OpInfo.ConstraintCode = GetMostGeneralConstraint(OpInfo.Codes, TLI);
-MVT::ValueType OpVT;
+MVT::ValueType OpVT = MVT::Other;
-// Compute the value type for each operand and add it to ConstraintVTs.
-switch (Constraints[i].Type) {
+// Compute the value type for each operand.
+switch (OpInfo.Type) {
case InlineAsm::isOutput:
- if (!Constraints[i].isIndirect) {
-// The return value of the call is this value.
+ if (!OpInfo.isIndirect) {
+// The return value of the call is this value. As such, there is no
+// corresponding argument.
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
OpVT = TLI.getValueType(I.getType());
} else {
-const Type *OpTy = I.getOperand(OpNum)->getType();
-OpVT =
TLI.getValueType(cast(OpTy)->getElementType(),true);
-OpNum++; // Consumes a call operand.
+OpInfo.CallOperandVal = I.getOperand(OpNo++);
}
break;
case InlineAsm::isInput:
- if (!Constraints[i].isIndirect) {
-OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
- } else {
-const Type *OpTy = I.getOperand(OpNum)->getType();
-OpVT =
TLI.getValueType(cast(OpTy)->getElementType(),true);
- }
- OpNum++; // Consumes a call operand.
+ OpInfo.CallOperandVal = I.getOperand(OpNo++);
break;
case InlineAsm::isClobber:
- OpVT = MVT::Other;
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.432 -> 1.433
---
Log message:
Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
---
Diffs of the changes: (+10 -4)
SelectionDAGISel.cpp | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.432
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.433
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.432Fri Apr 27
23:05:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 28 01:08:13 2007
@@ -3210,16 +3210,22 @@
switch (Constraints[i].Type) {
case InlineAsm::isOutput:
if (!Constraints[i].isIndirect) {
+// The return value of the call is this value.
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
OpVT = TLI.getValueType(I.getType());
} else {
const Type *OpTy = I.getOperand(OpNum)->getType();
-OpVT = TLI.getValueType(cast(OpTy)->getElementType());
+OpVT =
TLI.getValueType(cast(OpTy)->getElementType(),true);
OpNum++; // Consumes a call operand.
}
break;
case InlineAsm::isInput:
- OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
+ if (!Constraints[i].isIndirect) {
+OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
+ } else {
+const Type *OpTy = I.getOperand(OpNum)->getType();
+OpVT =
TLI.getValueType(cast(OpTy)->getElementType(),true);
+ }
OpNum++; // Consumes a call operand.
break;
case InlineAsm::isClobber:
@@ -3275,8 +3281,8 @@
if (ConstraintCode.size() == 1) // not a physreg name.
CTy = TLI.getConstraintType(ConstraintCode);
- if (CTy == TargetLowering::C_Memory) {
-// Memory output.
+ if (CTy != TargetLowering::C_RegisterClass) {
+// Memory output, or 'other' output (e.g. 'X' constraint).
SDOperand InOperandVal = getValue(I.getOperand(OpNum));
// Check that the operand (the address to store to) isn't a float.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.431 -> 1.432
---
Log message:
Fix this to match change to InlineAsm class.
---
Diffs of the changes: (+3 -3)
SelectionDAGISel.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.431
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.432
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.431Thu Apr 26
20:20:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Apr 27 23:05:59 2007
@@ -3209,7 +3209,7 @@
// Compute the value type for each operand and add it to ConstraintVTs.
switch (Constraints[i].Type) {
case InlineAsm::isOutput:
- if (!Constraints[i].isIndirectOutput) {
+ if (!Constraints[i].isIndirect) {
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
OpVT = TLI.getValueType(I.getType());
} else {
@@ -3283,7 +3283,7 @@
if (!MVT::isInteger(InOperandVal.getValueType()))
assert(0 && "MATCH FAIL!");
-if (!Constraints[i].isIndirectOutput)
+if (!Constraints[i].isIndirect)
assert(0 && "MATCH FAIL!");
OpNum++; // Consumes a call operand.
@@ -3324,7 +3324,7 @@
exit(1);
}
- if (!Constraints[i].isIndirectOutput) {
+ if (!Constraints[i].isIndirect) {
assert(RetValRegs.Regs.empty() &&
"Cannot have multiple output constraints yet!");
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.430 -> 1.431
---
Log message:
improve EH global handling, patch by Duncan Sands.
---
Diffs of the changes: (+10 -6)
SelectionDAGISel.cpp | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.430
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.431
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.430Thu Apr 26
16:09:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Apr 26 20:20:11 2007
@@ -2610,14 +2610,18 @@
// MachineModuleInfo.
std::vector TyInfo;
for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
-ConstantExpr *CE = dyn_cast(I.getOperand(i));
-if (CE && CE->getOpcode() == Instruction::BitCast &&
-isa(CE->getOperand(0))) {
+Constant *C = cast(I.getOperand(i));
+if (GlobalVariable *GV = dyn_cast(C)) {
+ TyInfo.push_back(GV);
+} else if (ConstantExpr *CE = dyn_cast(C)) {
+ assert(CE->getOpcode() == Instruction::BitCast &&
+ isa(CE->getOperand(0))
+ && "TypeInfo must be a global variable or NULL");
TyInfo.push_back(cast(CE->getOperand(0)));
} else {
- ConstantInt *CI = dyn_cast(I.getOperand(i));
- assert(CI && CI->getZExtValue() == 0 &&
-"TypeInfo must be a global variable typeinfo or NULL");
+ ConstantInt *CI = dyn_cast(C);
+ assert(CI && CI->isNullValue() &&
+ "TypeInfo must be a global variable or NULL");
TyInfo.push_back(NULL);
}
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.429 -> 1.430
---
Log message:
enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
successfully! woohoo...
---
Diffs of the changes: (+0 -1)
SelectionDAGISel.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.429
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.430
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.429Thu Apr 26
15:44:04 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Apr 26 16:09:43 2007
@@ -1682,7 +1682,6 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock*
Default){
- return false;
unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
Case& FrontCase = *CR.Range.first;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.428 -> 1.429 --- Log message: Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32 --- Diffs of the changes: (+1 -1) SelectionDAGISel.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.428 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.429 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.428Wed Apr 25 13:33:21 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Apr 26 15:44:04 2007 @@ -1722,7 +1722,7 @@ << "Low bound: " << cast(minValue)->getSExtValue() << "\n" << "High bound: " << cast(maxValue)->getSExtValue() << "\n"; - if (range>IntPtrBits || + if (range>=IntPtrBits || (!(Dests.size() == 1 && numCmps >= 3) && !(Dests.size() == 2 && numCmps >= 5) && !(Dests.size() >= 3 && numCmps >= 6))) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.427 -> 1.428
---
Log message:
This was lefted out. Fixed sumarray-dbl.
---
Diffs of the changes: (+1 -0)
SelectionDAGISel.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.427
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.428
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.427Tue Apr 24
23:08:28 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 25 13:33:21 2007
@@ -315,6 +315,7 @@
while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
NumElts >>= 1;
NumVectorRegs <<= 1;
+ VecTy = getVectorType(EltTy, NumElts);
}
// Check that VecTy isn't a 1-element vector.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.426 -> 1.427 --- Log message: allow support for 64-bit stack objects --- Diffs of the changes: (+1 -1) SelectionDAGISel.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.426 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.427 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.426Tue Apr 24 16:13:23 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Apr 24 23:08:28 2007 @@ -249,7 +249,7 @@ TySize *= CUI->getZExtValue(); // Get total allocated size. if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. StaticAllocaMap[AI] = - MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); + MF.getFrameInfo()->CreateStackObject(TySize, Align); } for (; BB != EB; ++BB) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.425 -> 1.426
---
Log message:
Assertion when using a 1-element vector for an add operation. Get the
real vector type in this case.
---
Diffs of the changes: (+7 -4)
SelectionDAGISel.cpp | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.426
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425Mon Apr 23
20:24:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Apr 24 16:13:23 2007
@@ -308,19 +308,22 @@
const VectorType *PTy = cast(V->getType());
unsigned NumElts = PTy->getNumElements();
MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
+MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
-while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
+while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
-if (NumElts == 1)
+
+// Check that VecTy isn't a 1-element vector.
+if (NumElts == 1 && VecTy == MVT::Other)
VT = EltTy;
else
- VT = getVectorType(EltTy, NumElts);
+ VT = VecTy;
}
-
+
// The common case is that we will only create one register for this
// value. If we have that case, create and return the virtual register.
unsigned NV = TLI.getNumElements(VT);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.424 -> 1.425
---
Log message:
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
tests always being true in the process.
---
Diffs of the changes: (+2 -2)
SelectionDAGISel.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.424
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.424Sun Apr 22
18:15:29 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 23 20:24:20 2007
@@ -1177,7 +1177,7 @@
/// visitJumpTable - Emit JumpTable node in the current MBB
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
// Emit the code for the jump table
- assert(JT.Reg != -1UL && "Should lower JT Header first!");
+ assert(JT.Reg != -1U && "Should lower JT Header first!");
MVT::ValueType PTy = TLI.getPointerTy();
SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
@@ -1544,7 +1544,7 @@
// Set the jump table information so that we can codegen it as a second
// MachineBasicBlock
- SelectionDAGISel::JumpTable JT(-1UL, JTI, JumpTableBB, Default);
+ SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
(CR.CaseBB == CurMBB));
if (CR.CaseBB == CurMBB)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp SelectionDAG.cpp DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.423 -> 1.424
SelectionDAG.cpp updated: 1.401 -> 1.402
DAGCombiner.cpp updated: 1.295 -> 1.296
---
Log message:
PR400: http://llvm.org/PR400 phase 2. Propagate attributed load/store
information through DAGs.
---
Diffs of the changes: (+112 -36)
DAGCombiner.cpp | 70 +--
SelectionDAG.cpp | 66 +++-
SelectionDAGISel.cpp | 12 +---
3 files changed, 112 insertions(+), 36 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.423
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.424
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.423Sat Apr 21
13:36:27 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Apr 22 18:15:29 2007
@@ -498,7 +498,7 @@
SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
const Value *SV, SDOperand Root,
-bool isVolatile);
+bool isVolatile, unsigned Alignment);
SDOperand getIntPtrConstant(uint64_t Val) {
return DAG.getConstant(Val, TLI.getPointerTy());
@@ -2313,19 +2313,21 @@
}
setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
- Root, I.isVolatile()));
+ Root, I.isVolatile(), I.getAlignment()));
}
SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
const Value *SV, SDOperand Root,
-bool isVolatile) {
+bool isVolatile,
+unsigned Alignment) {
SDOperand L;
if (const VectorType *PTy = dyn_cast(Ty)) {
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
DAG.getSrcValue(SV));
} else {
-L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, isVolatile);
+L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
+isVolatile, Alignment);
}
if (isVolatile)
@@ -2342,7 +2344,7 @@
SDOperand Src = getValue(SrcV);
SDOperand Ptr = getValue(I.getOperand(1));
DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
- I.isVolatile()));
+ I.isVolatile(), I.getAlignment()));
}
/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.401
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.402
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.401Sat Apr 21
15:56:26 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Apr 22 18:15:30 2007
@@ -15,11 +15,13 @@
#include "llvm/Constants.h"
#include "llvm/GlobalVariable.h"
#include "llvm/Intrinsics.h"
+#include "llvm/DerivedTypes.h"
#include "llvm/Assembly/Writer.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
@@ -1538,9 +1540,7 @@
SDOperand SelectionDAG::getLoad(MVT::ValueType VT,
SDOperand Chain, SDOperand Ptr,
const Value *SV, int SVOffset,
-bool isVolatile) {
- // FIXME: Alignment == 1 for now.
- unsigned Alignment = 1;
+bool isVolatile, unsigned Alignment) {
SDVTList VTs = getVTList(VT, MVT::Other);
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
SDOperand Ops[] = { Chain, Ptr, Undef };
@@ -1556,6 +1556,18 @@
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
+ if (Alignment == 0) { // Ensure that codegen never sees alignment 0
+const Type *Ty = 0;
+if (VT != MVT::Vector && VT != MVT::iPTR) {
+ Ty = MVT::getTypeForValueType(VT);
+} else if (SV) {
+ const PointerType *PT = dyn_cast(SV->getType());
+ assert(PT && "Value for load must be a pointer");
+ Ty = PT->getElementType();
+}
+assert(Ty && "Could not get type information for load");
+Alignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+ }
SDNode *N = new LoadSDNode(Ops, VTs, ISD::UNINDEXED,
ISD::NON_EXTLOAD, VT, SV, SVOffset, Alignment,
isVolatile);
@@ -1568,7 +1580,7 @@
SDOperand Chain, SDOperand Ptr,
co
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.420 -> 1.421
---
Log message:
disable switch lowering using shift/and. It still breaks ppc bootstrap for
some reason. :( Will investigate.
---
Diffs of the changes: (+1 -0)
SelectionDAGISel.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.420
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.421
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.420Sat Apr 14
08:25:55 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 14 14:39:41 2007
@@ -1678,6 +1678,7 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock*
Default){
+ return false;
unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
Case& FrontCase = *CR.Range.first;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.419 -> 1.420
---
Log message:
Fix PR1325: http://llvm.org/PR1325 : Case range optimization was performed in
the case it
shouldn't. Also fix some "latent" bug on 64-bit platforms
---
Diffs of the changes: (+2 -4)
SelectionDAGISel.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.419
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.420
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.419Fri Apr 13
21:26:56 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 14 08:25:55 2007
@@ -1678,8 +1678,6 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock*
Default){
- return false; // DISABLED FOR NOW: PR1325.
-
unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
Case& FrontCase = *CR.Range.first;
@@ -1732,7 +1730,7 @@
// word without having to subtract minValue. In this case,
// we can optimize away the subtraction.
if (cast(minValue)->getSExtValue() >= 0 &&
- cast(maxValue)->getSExtValue() <= IntPtrBits) {
+ cast(maxValue)->getSExtValue() < IntPtrBits) {
range = cast(maxValue)->getSExtValue();
} else {
lowBound = cast(minValue)->getSExtValue();
@@ -1757,7 +1755,7 @@
uint64_t hi = cast(I->High)->getSExtValue() - lowBound;
for (uint64_t j = lo; j <= hi; j++) {
- CasesBits[i].Mask |= 1 << j;
+ CasesBits[i].Mask |= 1ULL << j;
CasesBits[i].Bits++;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.418 -> 1.419
---
Log message:
disable shift/and lowering to work around PR1325: http://llvm.org/PR1325 for
now.
---
Diffs of the changes: (+3 -1)
SelectionDAGISel.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.418
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.419
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.418Fri Apr 13
01:53:51 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Apr 13 21:26:56 2007
@@ -1677,7 +1677,9 @@
bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
-MachineBasicBlock*
Default) {
+MachineBasicBlock*
Default){
+ return false; // DISABLED FOR NOW: PR1325.
+
unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
Case& FrontCase = *CR.Range.first;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.417 -> 1.418
---
Log message:
Fix PR1323: http://llvm.org/PR1323 : we haven't updated phi nodes in good
manner :)
---
Diffs of the changes: (+1 -0)
SelectionDAGISel.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.417
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.418
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.417Thu Apr 12
01:00:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Apr 13 01:53:51 2007
@@ -4634,6 +4634,7 @@
if (PHIBB == BitTestCases[i].Default) {
PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
+PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
}
// One of "cases" BB.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.416 -> 1.417
---
Log message:
the result of an inline asm copy can be an arbitrary VT that the register
class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes
CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
---
Diffs of the changes: (+21 -4)
SelectionDAGISel.cpp | 25 +
1 files changed, 21 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.416
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.417
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.416Wed Apr 11
21:48:46 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Apr 12 01:00:20 2007
@@ -3055,9 +3055,10 @@
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the regalloc do the right thing.
if (!isOutReg || !isInReg) {
- if (VT == MVT::Other)
-ValueVT = *PhysReg.second->vt_begin();
RegVT = *PhysReg.second->vt_begin();
+
+ if (VT == MVT::Other)
+ValueVT = RegVT;
// Create the appropriate number of virtual registers.
SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
@@ -3459,8 +3460,24 @@
// If this asm returns a register value, copy the result from that register
// and set it as the value of the call.
- if (!RetValRegs.Regs.empty())
-setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
+ if (!RetValRegs.Regs.empty()) {
+SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag);
+
+// If the result of the inline asm is a vector, it may have the wrong
+// width/num elts. Make sure to convert it to the right type with
+// vbit_convert.
+if (Val.getValueType() == MVT::Vector) {
+ const VectorType *VTy = cast(I.getType());
+ unsigned DesiredNumElts = VTy->getNumElements();
+ MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType());
+
+ Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
+DAG.getConstant(DesiredNumElts, MVT::i32),
+DAG.getValueType(DesiredEltVT));
+}
+
+setValue(&I, Val);
+ }
std::vector > StoresToEmit;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.415 -> 1.416
---
Log message:
For PR1284: http://llvm.org/PR1284 :
Implement the "part_set" intrinsic.
---
Diffs of the changes: (+6 -1)
SelectionDAGISel.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.415
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.416
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.415Tue Apr 10
21:44:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 11 21:48:46 2007
@@ -2691,7 +2691,12 @@
}
case Intrinsic::part_select: {
// Currently not implemented: just abort
-assert(0 && "bit_part_select intrinsic not implemented");
+assert(0 && "part_select intrinsic not implemented");
+abort();
+ }
+ case Intrinsic::part_set: {
+// Currently not implemented: just abort
+assert(0 && "part_set intrinsic not implemented");
abort();
}
case Intrinsic::bswap:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.414 -> 1.415
---
Log message:
For PR1146: http://llvm.org/PR1146 :
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
---
Diffs of the changes: (+13 -13)
SelectionDAGISel.cpp | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.414
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.415
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.414Mon Apr 9
22:20:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Apr 10 21:44:19 2007
@@ -828,9 +828,9 @@
const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
const ParamAttrsList *Attrs = FTy->getParamAttrs();
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
- if (Attrs && Attrs->paramHasAttr(0, SExtAttribute))
+ if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt))
ExtendKind = ISD::SIGN_EXTEND;
- if (Attrs && Attrs->paramHasAttr(0, ZExtAttribute))
+ if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt))
ExtendKind = ISD::ZERO_EXTEND;
RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
}
@@ -2768,16 +2768,16 @@
Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg);
Entry.Node = ArgNode; Entry.Ty = Arg->getType();
-Entry.isSExt = Attrs && Attrs->paramHasAttr(i, SExtAttribute);
-Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ZExtAttribute);
-Entry.isInReg = Attrs && Attrs->paramHasAttr(i, InRegAttribute);
-Entry.isSRet = Attrs && Attrs->paramHasAttr(i, StructRetAttribute);
+Entry.isSExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::SExt);
+Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::ZExt);
+Entry.isInReg = Attrs && Attrs->paramHasAttr(i, ParamAttr::InReg);
+Entry.isSRet = Attrs && Attrs->paramHasAttr(i, ParamAttr::StructRet);
Args.push_back(Entry);
}
std::pair Result =
TLI.LowerCallTo(getRoot(), I.getType(),
-Attrs && Attrs->paramHasAttr(0, SExtAttribute),
+Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
FTy->isVarArg(), CallingConv, IsTailCall,
Callee, Args, DAG);
if (I.getType() != Type::VoidTy)
@@ -3617,13 +3617,13 @@
// FIXME: Distinguish between a formal with no [sz]ext attribute from one
// that is zero extended!
-if (Attrs && Attrs->paramHasAttr(j, ZExtAttribute))
+if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt))
Flags &= ~(ISD::ParamFlags::SExt);
-if (Attrs && Attrs->paramHasAttr(j, SExtAttribute))
+if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt))
Flags |= ISD::ParamFlags::SExt;
-if (Attrs && Attrs->paramHasAttr(j, InRegAttribute))
+if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg))
Flags |= ISD::ParamFlags::InReg;
-if (Attrs && Attrs->paramHasAttr(j, StructRetAttribute))
+if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
Flags |= ISD::ParamFlags::StructReturn;
Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
@@ -3697,10 +3697,10 @@
case Promote: {
SDOperand Op(Result, i++);
if (MVT::isInteger(VT)) {
-if (Attrs && Attrs->paramHasAttr(Idx, SExtAttribute))
+if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt))
Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
DAG.getValueType(VT));
-else if (Attrs && Attrs->paramHasAttr(Idx, ZExtAttribute))
+else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt))
Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
DAG.getValueType(VT));
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.413 -> 1.414
---
Log message:
apparently some people commit without building the tree, or they forget to
commit a LOT of files.
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.413
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.414
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.413Mon Apr 9
18:42:32 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 9 22:20:39 2007
@@ -2689,7 +2689,7 @@
DAG.setRoot(Tmp.getValue(1));
return 0;
}
- case Intrinsic::bit_part_select: {
+ case Intrinsic::part_select: {
// Currently not implemented: just abort
assert(0 && "bit_part_select intrinsic not implemented");
abort();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.412 -> 1.413 --- Log message: No longer needed. --- Diffs of the changes: (+0 -1) SelectionDAGISel.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.412 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.413 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.412Mon Apr 9 16:57:03 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 9 18:42:32 2007 @@ -45,7 +45,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include -#include using namespace llvm; #ifndef NDEBUG ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.411 -> 1.412 --- Log message: Use integer log for metric calculation --- Diffs of the changes: (+2 -2) SelectionDAGISel.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.411 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.412 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.411Mon Apr 9 09:32:59 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 9 16:57:03 2007 @@ -1604,7 +1604,7 @@ assert((RBegin-LEnd>=1) && "Invalid case distance"); double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); -double Metric = log(double(RBegin-LEnd))*(LDensity+RDensity); +double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); // Should always split in some non-trivial place DOUT <<"=>Step\n" << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" @@ -1620,7 +1620,7 @@ RSize -= J->size(); } // If our case is dense we *really* should handle it earlier! - assert((FMetric != 0) && "Should handle dense range earlier!"); + assert((FMetric > 0) && "Should handle dense range earlier!"); CaseRange LHSR(CR.Range.first, Pivot); CaseRange RHSR(Pivot, CR.Range.second); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> Next stage into switch lowering refactoring
> 1. Fix some bugs in the jump table lowering threshold
> 2. Implement much better metric for optimal pivot selection
> 3. Tune thresholds for different lowering methods
> 4. Implement shift-and trick for lowering small ( length) cases with few destinations. Good testcase will follow.
Oooh, very cool.
> @@ -1484,20 +1593,33 @@
>
>uint64_t LSize = FrontCase.size();
>uint64_t RSize = TSize-LSize;
> + DOUT << "Selecting best pivot: \n"
> + << "First: " << First << ", Last: " << Last <<"\n"
> + << "LSize: " << LSize << ", RSize: " << RSize << "\n";
>for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
> J!=E; ++I, ++J) {
> int64_t LEnd = cast(I->High)->getSExtValue();
> int64_t RBegin = cast(J->Low)->getSExtValue();
> +assert((RBegin-LEnd>=1) && "Invalid case distance");
> double LDensity = (double)LSize / (double)((LEnd - First) +
> 1ULL);
> double RDensity = (double)RSize / (double)((Last - RBegin) +
> 1ULL);
> -if (Density < (LDensity + RDensity)) {
> +double Metric = log(RBegin-LEnd)*(LDensity+RDensity);
Is there any metric you can use here other than something based on
'log'? Can you do this determination with integer arithmetic?
> @@ -1549,6 +1671,130 @@
>return true;
> }
>
> +/// handleBitTestsSwitchCase - if current case range has few
> destination and
> +/// range span less, than machine word bitwidth, encode case range
> into series
> +/// of masks and emit bit tests with these masks.
> +bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
> +CaseRecVector&
> WorkList,
> +Value* SV,
> +
> MachineBasicBlock* Default) {
> + unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
...
> + if (range>IntPtrBits ||
Using intptr here is a good first step. However, some targets has
GPR's wider than intptr_t that are efficient (e.g. a ppc64 chip
running in ppc32 mode).
Overall, very very nice Anton,
-Chris
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.410 -> 1.411 --- Log message: Unbreak VC++ build. --- Diffs of the changes: (+3 -2) SelectionDAGISel.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.410 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.411 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.410Mon Apr 9 07:31:58 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 9 09:32:59 2007 @@ -45,6 +45,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include +#include using namespace llvm; #ifndef NDEBUG @@ -1603,7 +1604,7 @@ assert((RBegin-LEnd>=1) && "Invalid case distance"); double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); -double Metric = log(RBegin-LEnd)*(LDensity+RDensity); +double Metric = log(double(RBegin-LEnd))*(LDensity+RDensity); // Should always split in some non-trivial place DOUT <<"=>Step\n" << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" @@ -1783,7 +1784,7 @@ } SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV, - -1ULL, (CR.CaseBB == CurMBB), + -1U, (CR.CaseBB == CurMBB), CR.CaseBB, Default, BTC); if (CR.CaseBB == CurMBB) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.409 -> 1.410
---
Log message:
Next stage into switch lowering refactoring
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small ( CaseVector;
+ typedef std::vector CaseBitsVector;
typedef CaseVector::iteratorCaseItr;
typedef std::pair CaseRange;
@@ -404,9 +414,7 @@
/// The comparison function for sorting the switch case values in the vector.
/// WARNING: Case ranges should be disjoint!
struct CaseCmp {
-bool operator () (const Case& C1,
- const Case& C2) {
-
+bool operator () (const Case& C1, const Case& C2) {
assert(isa(C1.Low) && isa(C2.High));
const ConstantInt* CI1 = cast(C1.Low);
const ConstantInt* CI2 = cast(C2.High);
@@ -414,6 +422,12 @@
}
};
+ struct CaseBitsCmp {
+bool operator () (const CaseBits& C1, const CaseBits& C2) {
+ return C1.Bits > C2.Bits;
+}
+ };
+
unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
public:
@@ -430,6 +444,7 @@
/// JTCases - Vector of JumpTable structures used to communicate
/// SwitchInst code generation information.
std::vector JTCases;
+ std::vector BitTestCases;
/// FuncInfo - Information about the function as a whole.
///
@@ -531,7 +546,15 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default);
+ bool handleBitTestsSwitchCase(CaseRec& CR,
+CaseRecVector& WorkList,
+Value* SV,
+MachineBasicBlock* Default);
void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
+ void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
+ void visitBitTestCase(MachineBasicBlock* NextMBB,
+unsigned Reg,
+SelectionDAGISel::BitTestCase &B);
void visitJumpTable(SelectionDAGISel::JumpTable &JT);
void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
SelectionDAGISel::JumpTableHeader &JTH);
@@ -1210,9 +1233,98 @@
DAG.setRoot(BrCond);
else
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
-DAG.getBasicBlock(JT.MBB)));
+DAG.getBasicBlock(JT.MBB)));
+
+ return;
}
+/// visitBitTestHeader - This function emits necessary code to produce value
+/// suitable for "bit tests"
+void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock
&B) {
+ // Subtract the minimum value
+ SDOperand SwitchOp = getValue(B.SValue);
+ MVT::ValueType VT = SwitchOp.getValueType();
+ SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
+ DAG.getConstant(B.First, VT));
+
+ // Check range
+ SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
+DAG.getConstant(B.Range, VT),
+ISD::SETUGT);
+
+ SDOperand ShiftOp;
+ if (VT > TLI.getShiftAmountTy())
+ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
+ else
+ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
+
+ // Make desired shift
+ SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
+DAG.getConstant(1, TLI.getPointerTy()),
+ShiftOp);
+
+ unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
+ SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
+ B.Reg = SwitchReg;
+
+ SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
+ DAG.getBasicBlock(B.Default));
+
+ // Set NextBlock to be the MBB immediately after the current one, if any.
+ // This is used to avoid emitting unnecessary branches to the next block.
+ MachineBasicBlock *NextBlock = 0;
+ MachineFunction::iterator BBI = CurMBB;
+ if (++BBI != CurMBB->getParent()->end())
+NextBlock = BBI;
+
+ MachineBasicBlock* MBB = B.Cases[0].ThisBB;
+ if (MBB == NextBlock)
+DAG.setRoot(BrRange);
+ else
+DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
+DAG.getBasicBlock(MBB)));
+
+ CurMBB->addSuccessor(B.Default);
+ CurMBB->addSuccessor(MBB);
+
+ return;
+}
+
+/// visitBitTestCase - this function produces one "bit test"
+void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
+unsigned Reg,
+SelectionDAGISel::BitTestCase &B) {
+ // Emit bit tests and jumps
+ SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
+
+ SDOperand AndOp = DAG.getNode(
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.408 -> 1.409
---
Log message:
For PR1146: http://llvm.org/PR1146 :
Adapt handling of parameter attributes to use the new ParamAttrsList class.
---
Diffs of the changes: (+17 -13)
SelectionDAGISel.cpp | 30 +-
1 files changed, 17 insertions(+), 13 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.408
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.409
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.408Mon Apr 9
00:31:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 9 01:17:21 2007
@@ -25,6 +25,7 @@
#include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/IntrinsicInst.h"
+#include "llvm/ParameterAttributes.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -802,10 +803,11 @@
else
TmpVT = MVT::i32;
const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
+ const ParamAttrsList *Attrs = FTy->getParamAttrs();
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
- if (FTy->paramHasAttr(0, FunctionType::SExtAttribute))
+ if (Attrs && Attrs->paramHasAttr(0, SExtAttribute))
ExtendKind = ISD::SIGN_EXTEND;
- if (FTy->paramHasAttr(0, FunctionType::ZExtAttribute))
+ if (Attrs && Attrs->paramHasAttr(0, ZExtAttribute))
ExtendKind = ISD::ZERO_EXTEND;
RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
}
@@ -2508,6 +2510,7 @@
SDOperand Callee, unsigned OpIdx) {
const PointerType *PT = cast(CalledValueTy);
const FunctionType *FTy = cast(PT->getElementType());
+ const ParamAttrsList *Attrs = FTy->getParamAttrs();
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
@@ -2516,16 +2519,16 @@
Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg);
Entry.Node = ArgNode; Entry.Ty = Arg->getType();
-Entry.isSExt = FTy->paramHasAttr(i, FunctionType::SExtAttribute);
-Entry.isZExt = FTy->paramHasAttr(i, FunctionType::ZExtAttribute);
-Entry.isInReg = FTy->paramHasAttr(i, FunctionType::InRegAttribute);
-Entry.isSRet = FTy->paramHasAttr(i, FunctionType::StructRetAttribute);
+Entry.isSExt = Attrs && Attrs->paramHasAttr(i, SExtAttribute);
+Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ZExtAttribute);
+Entry.isInReg = Attrs && Attrs->paramHasAttr(i, InRegAttribute);
+Entry.isSRet = Attrs && Attrs->paramHasAttr(i, StructRetAttribute);
Args.push_back(Entry);
}
std::pair Result =
TLI.LowerCallTo(getRoot(), I.getType(),
-FTy->paramHasAttr(0,FunctionType::SExtAttribute),
+Attrs && Attrs->paramHasAttr(0, SExtAttribute),
FTy->isVarArg(), CallingConv, IsTailCall,
Callee, Args, DAG);
if (I.getType() != Type::VoidTy)
@@ -3346,6 +3349,7 @@
std::vector
TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
const FunctionType *FTy = F.getFunctionType();
+ const ParamAttrsList *Attrs = FTy->getParamAttrs();
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
std::vector Ops;
Ops.push_back(DAG.getRoot());
@@ -3364,13 +3368,13 @@
// FIXME: Distinguish between a formal with no [sz]ext attribute from one
// that is zero extended!
-if (FTy->paramHasAttr(j, FunctionType::ZExtAttribute))
+if (Attrs && Attrs->paramHasAttr(j, ZExtAttribute))
Flags &= ~(ISD::ParamFlags::SExt);
-if (FTy->paramHasAttr(j, FunctionType::SExtAttribute))
+if (Attrs && Attrs->paramHasAttr(j, SExtAttribute))
Flags |= ISD::ParamFlags::SExt;
-if (FTy->paramHasAttr(j, FunctionType::InRegAttribute))
+if (Attrs && Attrs->paramHasAttr(j, InRegAttribute))
Flags |= ISD::ParamFlags::InReg;
-if (FTy->paramHasAttr(j, FunctionType::StructRetAttribute))
+if (Attrs && Attrs->paramHasAttr(j, StructRetAttribute))
Flags |= ISD::ParamFlags::StructReturn;
Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
@@ -3444,10 +3448,10 @@
case Promote: {
SDOperand Op(Result, i++);
if (MVT::isInteger(VT)) {
-if (FTy->paramHasAttr(Idx, FunctionType::SExtAttribute))
+if (Attrs && Attrs->paramHasAttr(Idx, SExtAttribute))
Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
DAG.getValueType(VT));
-else if (FTy->paramHasAttr(Idx, FunctionType::ZExtAttribute))
+else if (Attrs && Attrs->paramHasAttr(Idx, ZExtAttribute))
Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
DAG.getValueType(VT));
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
__
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.407 -> 1.408
---
Log message:
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
---
Diffs of the changes: (+9 -2)
SelectionDAGISel.cpp | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.407
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.408
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.407Sun Apr 8
19:33:58 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 9 00:31:20 2007
@@ -2656,13 +2656,20 @@
if (MVT::isVector(RegVT)) {
assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector
cast?");
Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
- } else if (MVT::isInteger(RegVT)) {
+ } else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) {
if (RegVT < ValueVT)
Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
else
Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
- } else
+ } else if (MVT::isFloatingPoint(RegVT) &&
+ MVT::isFloatingPoint(Val.getValueType())) {
Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
+ } else if (MVT::getSizeInBits(RegVT) ==
+ MVT::getSizeInBits(Val.getValueType())) {
+Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val);
+ } else {
+assert(0 && "Unknown mismatch!");
+ }
}
Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
Flag = Chain.getValue(1);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.406 -> 1.407
---
Log message:
Fix PR1316: http://llvm.org/PR1316
---
Diffs of the changes: (+4 -4)
SelectionDAGISel.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.406
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.407
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.406Sun Apr 8
17:23:26 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Apr 8 19:33:58 2007
@@ -2439,8 +2439,6 @@
return 0;
}
case Intrinsic::bit_part_select: {
-// MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
-// setValue(&I, DAG.getTargetConstant(0, Ty));
// Currently not implemented: just abort
assert(0 && "bit_part_select intrinsic not implemented");
abort();
@@ -2687,7 +2685,8 @@
/// values added into it.
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
std::vector &Ops) const {
- Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), MVT::i32));
+ MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
+ Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(Regs[i], RegVT));
}
@@ -4524,8 +4523,9 @@
}
// Add this to the output node.
+ MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
- MVT::i32));
+ IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.405 -> 1.406
---
Log message:
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314:
http://llvm.org/PR1314
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.405
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.406
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.405Fri Apr 6
12:47:14 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Apr 8 17:23:26 2007
@@ -2687,7 +2687,7 @@
/// values added into it.
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
std::vector &Ops) const {
- Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
+ Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), MVT::i32));
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(Regs[i], RegVT));
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.404 -> 1.405
---
Log message:
minor comment fix
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.404
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.405
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.404Wed Apr 4
20:20:18 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Apr 6 12:47:14 2007
@@ -2840,7 +2840,7 @@
// Okay, this register is good, we can use it.
++NumAllocated;
-// If we allocated enough consecutive
+// If we allocated enough consecutive registers, succeed.
if (NumAllocated == NumRegs) {
unsigned RegStart = (i-NumAllocated)+1;
unsigned RegEnd = i+1;
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
On Apr 4, 2007, at 6:17 PM, Reid Spencer wrote: >> >> I'm fine with it aborting if you don't want to implement the lowering >> code. > > As you'd rather have an abort, I'll change it. > Thank you, -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.403 -> 1.404
---
Log message:
Change the bit_part_select (non)implementation from "return 0" to abort.
---
Diffs of the changes: (+5 -3)
SelectionDAGISel.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.403
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.404
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.403Wed Apr 4
18:48:25 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 4 20:20:18 2007
@@ -2439,9 +2439,11 @@
return 0;
}
case Intrinsic::bit_part_select: {
-MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
-setValue(&I, DAG.getTargetConstant(0, Ty));
-return 0;
+// MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
+// setValue(&I, DAG.getTargetConstant(0, Ty));
+// Currently not implemented: just abort
+assert(0 && "bit_part_select intrinsic not implemented");
+abort();
}
case Intrinsic::bswap:
setValue(&I, DAG.getNode(ISD::BSWAP,
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
On Wed, 2007-04-04 at 18:06 -0700, Chris Lattner wrote: > On Apr 4, 2007, at 5:54 PM, Reid Spencer wrote: > > > On Wed, 2007-04-04 at 17:37 -0700, Chris Lattner wrote: > >>> Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic. > >> > >> Urr? This is obviously incorrect. I'd much rather have the code > >> generator assert and die on an unsupported intrinsic than to > >> miscompile it silently. > > > > Okay, but you DID approve this in the plan. > > I did not approve silently miscompiling the code. You most certainly did. You agreed with the plan and it stated: I will *not* write lowering code for part_select in the SDISel because no known target can do anything with it and it expands to an entire function. If, at some point, it needs to be implemented on the "normal" targets, we can do so at that time. *To avoid having SDISel assert out, I will have this intrinsic simply generate a 0 for now.* This is mostly a time saving thing for right now. I will probably revisit after AutoESL's Phase 3 is over so we don't leave a rare but bad code gen bug in LLVM. > > I'm fine with it aborting if you don't want to implement the lowering > code. As you'd rather have an abort, I'll change it. > > -Chris > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits signature.asc Description: This is a digitally signed message part ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
On Apr 4, 2007, at 5:54 PM, Reid Spencer wrote: > On Wed, 2007-04-04 at 17:37 -0700, Chris Lattner wrote: >>> Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic. >> >> Urr? This is obviously incorrect. I'd much rather have the code >> generator assert and die on an unsupported intrinsic than to >> miscompile it silently. > > Okay, but you DID approve this in the plan. I did not approve silently miscompiling the code. I'm fine with it aborting if you don't want to implement the lowering code. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
On Wed, 2007-04-04 at 17:37 -0700, Chris Lattner wrote:
> > Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
>
> Urr? This is obviously incorrect. I'd much rather have the code
> generator assert and die on an unsupported intrinsic than to
> miscompile it silently.
Okay, but you DID approve this in the plan.
>
> -Chris
>
> >
> > ---
> > Diffs of the changes: (+5 -0)
> >
> > SelectionDAGISel.cpp |5 +
> > 1 files changed, 5 insertions(+)
> >
> >
> > Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> > diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402
> > llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.403
> > --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402Wed
> > Apr 4 16:14:49 2007
> > +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 4
> > 18:48:25 2007
> > @@ -2438,6 +2438,11 @@
> > DAG.setRoot(Tmp.getValue(1));
> > return 0;
> >}
> > + case Intrinsic::bit_part_select: {
> > +MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
> > +setValue(&I, DAG.getTargetConstant(0, Ty));
> > +return 0;
> > + }
> >case Intrinsic::bswap:
> > setValue(&I, DAG.getNode(ISD::BSWAP,
> > getValue(I.getOperand(1)).getValueType
> > (),
> >
> >
> >
> > ___
> > llvm-commits mailing list
> > llvm-commits@cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
Urr? This is obviously incorrect. I'd much rather have the code
generator assert and die on an unsupported intrinsic than to
miscompile it silently.
-Chris
>
> ---
> Diffs of the changes: (+5 -0)
>
> SelectionDAGISel.cpp |5 +
> 1 files changed, 5 insertions(+)
>
>
> Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402
> llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.403
> --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402 Wed
> Apr 4 16:14:49 2007
> +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cppWed Apr 4
> 18:48:25 2007
> @@ -2438,6 +2438,11 @@
> DAG.setRoot(Tmp.getValue(1));
> return 0;
>}
> + case Intrinsic::bit_part_select: {
> +MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
> +setValue(&I, DAG.getTargetConstant(0, Ty));
> +return 0;
> + }
>case Intrinsic::bswap:
> setValue(&I, DAG.getNode(ISD::BSWAP,
> getValue(I.getOperand(1)).getValueType
> (),
>
>
>
> ___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.402 -> 1.403
---
Log message:
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
---
Diffs of the changes: (+5 -0)
SelectionDAGISel.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.403
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402Wed Apr 4
16:14:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 4 18:48:25 2007
@@ -2438,6 +2438,11 @@
DAG.setRoot(Tmp.getValue(1));
return 0;
}
+ case Intrinsic::bit_part_select: {
+MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
+setValue(&I, DAG.getTargetConstant(0, Ty));
+return 0;
+ }
case Intrinsic::bswap:
setValue(&I, DAG.getNode(ISD::BSWAP,
getValue(I.getOperand(1)).getValueType(),
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.401 -> 1.402
---
Log message:
Properly emit range comparisons for switch cases, where neighbour cases
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
---
Diffs of the changes: (+181 -71)
SelectionDAGISel.cpp | 252 ---
1 files changed, 181 insertions(+), 71 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.401
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.401Sun Apr 1
02:34:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 4 16:14:49 2007
@@ -12,9 +12,11 @@
//===--===//
#define DEBUG_TYPE "isel"
+#include "llvm/ADT/BitVector.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/Constants.h"
#include "llvm/CallingConv.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
@@ -358,11 +360,26 @@
/// analysis.
std::vector PendingLoads;
- /// Case - A pair of values to record the Value for a switch case, and the
- /// case's target basic block.
- typedef std::pair Case;
- typedef std::vector::iterator CaseItr;
- typedef std::pair CaseRange;
+ /// Case - A struct to record the Value for a switch case, and the
+ /// case's target basic block.
+ struct Case {
+Constant* Low;
+Constant* High;
+MachineBasicBlock* BB;
+
+Case() : Low(0), High(0), BB(0) { }
+Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
+ Low(low), High(high), BB(bb) { }
+uint64_t size() const {
+ uint64_t rHigh = cast(High)->getSExtValue();
+ uint64_t rLow = cast(Low)->getSExtValue();
+ return (rHigh - rLow + 1ULL);
+}
+ };
+
+ typedef std::vector CaseVector;
+ typedef CaseVector::iteratorCaseItr;
+ typedef std::pair CaseRange;
/// CaseRec - A struct with ctor used in lowering switches to a binary tree
/// of conditional branches.
@@ -382,15 +399,21 @@
};
typedef std::vector CaseRecVector;
-
- /// The comparison function for sorting Case values.
+
+ /// The comparison function for sorting the switch case values in the vector.
+ /// WARNING: Case ranges should be disjoint!
struct CaseCmp {
-bool operator () (const Case& C1, const Case& C2) {
- assert(isa(C1.first) && isa(C2.first));
- return cast(C1.first)->getSExtValue() <
-cast(C2.first)->getSExtValue();
+bool operator () (const Case& C1,
+ const Case& C2) {
+
+ assert(isa(C1.Low) && isa(C2.High));
+ const ConstantInt* CI1 = cast(C1.Low);
+ const ConstantInt* CI2 = cast(C2.High);
+ return CI1->getValue().slt(CI2->getValue());
}
};
+
+ unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
public:
// TLI - This is information that describes the available target features we
@@ -912,14 +935,14 @@
}
SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
- BOp->getOperand(1), TBB, FBB, CurBB);
+ BOp->getOperand(1), NULL, TBB, FBB,
CurBB);
SwitchCases.push_back(CB);
return;
}
// Create a CaseBlock record representing this branch.
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
- TBB, FBB, CurBB);
+ NULL, TBB, FBB, CurBB);
SwitchCases.push_back(CB);
return;
}
@@ -1058,7 +1081,7 @@
// Create a CaseBlock record representing this branch.
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
- Succ0MBB, Succ1MBB, CurMBB);
+ NULL, Succ0MBB, Succ1MBB, CurMBB);
// Use visitSwitchCase to actually insert the fast branch sequence for this
// cond branch.
visitSwitchCase(CB);
@@ -1070,16 +1093,36 @@
SDOperand Cond;
SDOperand CondLHS = getValue(CB.CmpLHS);
- // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
- // handle common cases produced by branch lowering.
- if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
-Cond = CondLHS;
- else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
-SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
-Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
- } else
-Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ // Build the setcc now.
+ if (CB.CmpMHS == NULL) {
+// Fold "(X == true)" to X and "(X == false)" to !X to
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.400 -> 1.401
---
Log message:
For PR1297: http://llvm.org/PR1297 :
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
---
Diffs of the changes: (+31 -24)
SelectionDAGISel.cpp | 55 ---
1 files changed, 31 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.400
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.401
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.400Fri Mar 30
23:18:03 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Apr 1 02:34:11 2007
@@ -2328,37 +2328,44 @@
DAG.setRoot(Tmp.getValue(1));
return 0;
}
- case Intrinsic::bswap_i16:
- case Intrinsic::bswap_i32:
- case Intrinsic::bswap_i64:
+ case Intrinsic::bswap:
setValue(&I, DAG.getNode(ISD::BSWAP,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1;
return 0;
- case Intrinsic::cttz_i8:
- case Intrinsic::cttz_i16:
- case Intrinsic::cttz_i32:
- case Intrinsic::cttz_i64:
-setValue(&I, DAG.getNode(ISD::CTTZ,
- getValue(I.getOperand(1)).getValueType(),
- getValue(I.getOperand(1;
+ case Intrinsic::cttz: {
+SDOperand Arg = getValue(I.getOperand(1));
+MVT::ValueType Ty = Arg.getValueType();
+SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
+if (Ty < MVT::i32)
+ result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
+else if (Ty > MVT::i32)
+ result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
+setValue(&I, result);
return 0;
- case Intrinsic::ctlz_i8:
- case Intrinsic::ctlz_i16:
- case Intrinsic::ctlz_i32:
- case Intrinsic::ctlz_i64:
-setValue(&I, DAG.getNode(ISD::CTLZ,
- getValue(I.getOperand(1)).getValueType(),
- getValue(I.getOperand(1;
+ }
+ case Intrinsic::ctlz: {
+SDOperand Arg = getValue(I.getOperand(1));
+MVT::ValueType Ty = Arg.getValueType();
+SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
+if (Ty < MVT::i32)
+ result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
+else if (Ty > MVT::i32)
+ result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
+setValue(&I, result);
return 0;
- case Intrinsic::ctpop_i8:
- case Intrinsic::ctpop_i16:
- case Intrinsic::ctpop_i32:
- case Intrinsic::ctpop_i64:
-setValue(&I, DAG.getNode(ISD::CTPOP,
- getValue(I.getOperand(1)).getValueType(),
- getValue(I.getOperand(1;
+ }
+ case Intrinsic::ctpop: {
+SDOperand Arg = getValue(I.getOperand(1));
+MVT::ValueType Ty = Arg.getValueType();
+SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
+if (Ty < MVT::i32)
+ result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
+else if (Ty > MVT::i32)
+ result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
+setValue(&I, result);
return 0;
+ }
case Intrinsic::stacksave: {
SDOperand Op = getRoot();
SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.399 -> 1.400
---
Log message:
move a bunch of code out of the sdisel pass into its own opt pass
"codegenprepare".
---
Diffs of the changes: (+1 -483)
SelectionDAGISel.cpp | 484 ---
1 files changed, 1 insertion(+), 483 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.399
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.400
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.399Tue Mar 27
20:55:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Mar 30 23:18:03 2007
@@ -16,7 +16,6 @@
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CallingConv.h"
-#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
@@ -33,14 +32,12 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
-#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
@@ -3830,496 +3827,17 @@
}
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
- // FIXME: we only modify the CFG to split critical edges. This
- // updates dom and loop info.
AU.addRequired();
+ AU.setPreservesAll();
}
-/// OptimizeNoopCopyExpression - We have determined that the specified cast
-/// instruction is a noop copy (e.g. it's casting from one pointer type to
-/// another, int->uint, or int->sbyte on PPC.
-///
-/// Return true if any changes are made.
-static bool OptimizeNoopCopyExpression(CastInst *CI) {
- BasicBlock *DefBB = CI->getParent();
-
- /// InsertedCasts - Only insert a cast in each block once.
- std::map InsertedCasts;
-
- bool MadeChange = false;
- for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
- UI != E; ) {
-Use &TheUse = UI.getUse();
-Instruction *User = cast(*UI);
-
-// Figure out which BB this cast is used in. For PHI's this is the
-// appropriate predecessor block.
-BasicBlock *UserBB = User->getParent();
-if (PHINode *PN = dyn_cast(User)) {
- unsigned OpVal = UI.getOperandNo()/2;
- UserBB = PN->getIncomingBlock(OpVal);
-}
-
-// Preincrement use iterator so we don't invalidate it.
-++UI;
-
-// If this user is in the same block as the cast, don't change the cast.
-if (UserBB == DefBB) continue;
-
-// If we have already inserted a cast into this block, use it.
-CastInst *&InsertedCast = InsertedCasts[UserBB];
-
-if (!InsertedCast) {
- BasicBlock::iterator InsertPt = UserBB->begin();
- while (isa(InsertPt)) ++InsertPt;
-
- InsertedCast =
-CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
"",
- InsertPt);
- MadeChange = true;
-}
-
-// Replace a use of the cast with a use of the new casat.
-TheUse = InsertedCast;
- }
-
- // If we removed all uses, nuke the cast.
- if (CI->use_empty())
-CI->eraseFromParent();
-
- return MadeChange;
-}
-
-/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
-/// casting to the type of GEPI.
-static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
- Instruction *GEPI, Value *Ptr,
- Value *PtrOffset) {
- if (V) return V; // Already computed.
-
- // Figure out the insertion point
- BasicBlock::iterator InsertPt;
- if (BB == GEPI->getParent()) {
-// If GEP is already inserted into BB, insert right after the GEP.
-InsertPt = GEPI;
-++InsertPt;
- } else {
-// Otherwise, insert at the top of BB, after any PHI nodes
-InsertPt = BB->begin();
-while (isa(InsertPt)) ++InsertPt;
- }
-
- // If Ptr is itself a cast, but in some other BB, emit a copy of the cast
into
- // BB so that there is only one value live across basic blocks (the cast
- // operand).
- if (CastInst *CI = dyn_cast(Ptr))
-if (CI->getParent() != BB &&
isa(CI->getOperand(0)->getType()))
- Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
- "", InsertPt);
-
- // Add the offset, cast it to the right type.
- Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
- // Ptr is an integer type, GEPI is pointer type ==> IntToPtr
- return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.398 -> 1.399
---
Log message:
Scale 1 is always ok.
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.398
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.399
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.398Tue Mar 27
20:49:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 27 20:55:52 2007
@@ -4137,7 +4137,7 @@
int64_t Cst =
cast(BinOp->getOperand(1))->getSExtValue();
// e.g. load (gep i32 * %P, (X+42)) => load (%P + X*4 + 168).
if (TLI.isLegalAddressImmediate(Cst*Scale, UseTy) &&
- TLI.isLegalAddressScale(Scale, UseTy)) {
+ (Scale == 1 || TLI.isLegalAddressScale(Scale, UseTy))) {
DestBBs.insert(GEPIBB);
MadeChange = true;
break;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.397 -> 1.398
---
Log message:
GEP index sinking fixes:
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).
---
Diffs of the changes: (+34 -39)
SelectionDAGISel.cpp | 73 +++
1 files changed, 34 insertions(+), 39 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.397
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.398
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.397Tue Mar 27
07:05:48 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 27 20:49:39 2007
@@ -13,7 +13,6 @@
#define DEBUG_TYPE "isel"
#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CallingConv.h"
@@ -3834,7 +3833,6 @@
// FIXME: we only modify the CFG to split critical edges. This
// updates dom and loop info.
AU.addRequired();
- AU.addRequired();
}
@@ -4091,25 +4089,14 @@
return true;
}
-/// isLoopInvariantInst - Returns true if all operands of the instruction are
-/// loop invariants in the specified loop.
-static bool isLoopInvariantInst(Instruction *I, Loop *L) {
- // The instruction is loop invariant if all of its operands are
loop-invariant
- for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
-if (!L->isLoopInvariant(I->getOperand(i)))
- return false;
- return true;
-}
-
/// SinkInvariantGEPIndex - If a GEP instruction has a variable index that has
/// been hoisted out of the loop by LICM pass, sink it back into the use BB
/// if it can be determined that the index computation can be folded into the
/// addressing mode of the load / store uses.
-static bool SinkInvariantGEPIndex(BinaryOperator *BinOp, LoopInfo *loopInfo,
- const TargetLowering &TLI) {
- // Only look at Add / Sub for now.
- if (BinOp->getOpcode() != Instruction::Add &&
- BinOp->getOpcode() != Instruction::Sub)
+static bool SinkInvariantGEPIndex(BinaryOperator *BinOp,
+ const TargetLowering &TLI) {
+ // Only look at Add.
+ if (BinOp->getOpcode() != Instruction::Add)
return false;
// DestBBs - These are the blocks where a copy of BinOp will be inserted.
@@ -4118,32 +4105,43 @@
bool MadeChange = false;
for (Value::use_iterator UI = BinOp->use_begin(), E = BinOp->use_end();
UI != E; ++UI) {
-Instruction *User = cast(*UI);
+Instruction *GEPI = cast(*UI);
// Only look for GEP use in another block.
-if (User->getParent() == DefBB) continue;
+if (GEPI->getParent() == DefBB) continue;
-if (isa(User)) {
- BasicBlock *UserBB = User->getParent();
- Loop *L = loopInfo->getLoopFor(UserBB);
+if (isa(GEPI)) {
+ // If the GEP has another variable index, abondon.
+ bool hasVariableIndex = false;
+ for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
+ OE = GEPI->op_end(); OI != OE; ++OI)
+if (*OI != BinOp && !isa(*OI)) {
+ hasVariableIndex = true;
+ break;
+}
+ if (hasVariableIndex)
+break;
- // Only sink if expression is a loop invariant in the use BB.
- if (L && isLoopInvariantInst(BinOp, L) && !User->use_empty()) {
+ BasicBlock *GEPIBB = GEPI->getParent();
+ for (Value::use_iterator UUI = GEPI->use_begin(), UE = GEPI->use_end();
+ UUI != UE; ++UUI) {
+Instruction *GEPIUser = cast(*UUI);
const Type *UseTy = NULL;
-// FIXME: We are assuming all the uses of the GEP will have the
-// same type.
-Instruction *GEPUser = cast(*User->use_begin());
-if (LoadInst *Load = dyn_cast(GEPUser))
+if (LoadInst *Load = dyn_cast(GEPIUser))
UseTy = Load->getType();
-else if (StoreInst *Store = dyn_cast(GEPUser))
+else if (StoreInst *Store = dyn_cast(GEPIUser))
UseTy = Store->getOperand(0)->getType();
// Check if it is possible to fold the expression to address mode.
-if (UseTy &&
-TLI.isLegalAddressExpression(BinOp->getOpcode(),
- BinOp->getOperand(0),
- BinOp->getOperand(1), UseTy)) {
- DestBBs.insert(UserBB);
- MadeChange = true;
+if (UseTy && isa(BinOp->getOperand(1))) {
+ uint64_t Scale = TLI.getTargetData()->getTypeSize(UseTy);
+ int64_t Cst =
cast(BinOp->getOperand(1))->getSExtValue();
+ // e.g. load (gep i32 * %P, (X+42)) => load (%P + X*4 + 168).
+ if (TLI.isLegalAddressImmediate(Cst*Scale, UseTy)
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.396 -> 1.397
---
Log message:
Remove dead code
---
Diffs of the changes: (+46 -82)
SelectionDAGISel.cpp | 128 ++-
1 files changed, 46 insertions(+), 82 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.396
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.397
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.396Tue Mar 27
06:29:11 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 27 07:05:48 2007
@@ -499,19 +499,15 @@
void visitUnreachable(UnreachableInst &I) { /* noop */ }
// Helpers for visitSwitch
- void handleSmallSwitchRange(CaseRec& CR,
+ bool handleSmallSwitchRange(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default);
- void handleJTSwitchCase(CaseRec& CR,
+ bool handleJTSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default);
- void handleBTSplitSwitchCase(CaseRec& CR,
- CaseRecVector& WorkList,
- Value* SV,
- MachineBasicBlock* Default);
- void handleBTSmallSwitchCase(CaseRec& CR,
+ bool handleBTSplitSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default);
@@ -1228,10 +1224,17 @@
/// handleSmaaSwitchCaseRange - Emit a series of specific tests (suitable for
/// small case ranges).
-void SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
+bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default) {
+ Case& BackCase = *(CR.Range.second-1);
+
+ // Size is the number of Cases represented by this range.
+ unsigned Size = CR.Range.second - CR.Range.first;
+ if (Size >=3)
+return false;
+
// Get the MachineFunction which holds the current MBB. This is used when
// inserting any additional MBBs necessary to represent the switch.
MachineFunction *CurMF = CurMBB->getParent();
@@ -1240,8 +1243,6 @@
MachineBasicBlock *NextBlock = 0;
MachineFunction::iterator BBI = CR.CaseBB;
- Case& BackCase = *(CR.Range.second-1);
-
if (++BBI != CurMBB->getParent()->end())
NextBlock = BBI;
@@ -1290,16 +1291,36 @@
CurBlock = FallThrough;
}
+
+ return true;
}
/// handleJTSwitchCase - Emit jumptable for current switch case range
-void SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
+bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default) {
+ Case& FrontCase = *CR.Range.first;
+ Case& BackCase = *(CR.Range.second-1);
+
+ // Size is the number of Cases represented by this range.
+ unsigned Size = CR.Range.second - CR.Range.first;
+
+ uint64_t First = cast(FrontCase.first)->getSExtValue();
+ uint64_t Last = cast(BackCase.first)->getSExtValue();
+
+ if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) &&
+ !TLI.isOperationLegal(ISD::BRIND, MVT::Other)) ||
+ Size <= 5)
+return false;
+
+ double Density = (double)Size / (double)((Last - First) + 1ULL);
+ if (Density < 0.3125)
+return false;
+
// Get the MachineFunction which holds the current MBB. This is used when
// inserting any additional MBBs necessary to represent the switch.
- MachineFunction *CurMF = CurMBB->getParent();
+ MachineFunction *CurMF = CurMBB->getParent();
// Figure out which block is immediately after the current one.
MachineBasicBlock *NextBlock = 0;
@@ -1308,13 +1329,8 @@
if (++BBI != CurMBB->getParent()->end())
NextBlock = BBI;
- Case& FrontCase = *CR.Range.first;
- Case& BackCase = *(CR.Range.second-1);
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
- uint64_t First = cast(FrontCase.first)->getSExtValue();
- uint64_t Last = cast(BackCase.first)->getSExtValue();
-
// Create a new basic block to hold the code for loading the address
// of the jump table, and jumping to it. Update successor information;
// we will either branch to the default case for the switch, or the jump
@@ -1364,37 +1380,13 @@
visitJumpTableHeader(JT, JTH);
JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
-}
-/// handleBTSmallSwitchCase - handle leaf in the
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.395 -> 1.396
---
Log message:
Split big monster into small helpers. No functionality change.
---
Diffs of the changes: (+285 -190)
SelectionDAGISel.cpp | 475 ++-
1 files changed, 285 insertions(+), 190 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.395
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.396
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.395Mon Mar 26
19:53:36 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 27 06:29:11 2007
@@ -384,6 +384,8 @@
/// processed at this point in the binary search tree.
CaseRange Range;
};
+
+ typedef std::vector CaseRecVector;
/// The comparison function for sorting Case values.
struct CaseCmp {
@@ -496,7 +498,23 @@
void visitSwitch(SwitchInst &I);
void visitUnreachable(UnreachableInst &I) { /* noop */ }
- // Helper for visitSwitch
+ // Helpers for visitSwitch
+ void handleSmallSwitchRange(CaseRec& CR,
+ CaseRecVector& WorkList,
+ Value* SV,
+ MachineBasicBlock* Default);
+ void handleJTSwitchCase(CaseRec& CR,
+ CaseRecVector& WorkList,
+ Value* SV,
+ MachineBasicBlock* Default);
+ void handleBTSplitSwitchCase(CaseRec& CR,
+ CaseRecVector& WorkList,
+ Value* SV,
+ MachineBasicBlock* Default);
+ void handleBTSmallSwitchCase(CaseRec& CR,
+ CaseRecVector& WorkList,
+ Value* SV,
+ MachineBasicBlock* Default);
void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
void visitJumpTable(SelectionDAGISel::JumpTable &JT);
void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
@@ -1208,6 +1226,265 @@
void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
}
+/// handleSmaaSwitchCaseRange - Emit a series of specific tests (suitable for
+/// small case ranges).
+void SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
+ CaseRecVector& WorkList,
+ Value* SV,
+ MachineBasicBlock* Default) {
+ // Get the MachineFunction which holds the current MBB. This is used when
+ // inserting any additional MBBs necessary to represent the switch.
+ MachineFunction *CurMF = CurMBB->getParent();
+
+ // Figure out which block is immediately after the current one.
+ MachineBasicBlock *NextBlock = 0;
+ MachineFunction::iterator BBI = CR.CaseBB;
+
+ Case& BackCase = *(CR.Range.second-1);
+
+ if (++BBI != CurMBB->getParent()->end())
+NextBlock = BBI;
+
+ // TODO: If any two of the cases has the same destination, and if one value
+ // is the same as the other, but has one bit unset that the other has set,
+ // use bit manipulation to do two compares at once. For example:
+ // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
+
+ // Rearrange the case blocks so that the last one falls through if possible.
+ if (NextBlock && Default != NextBlock && BackCase.second != NextBlock) {
+// The last case block won't fall through into 'NextBlock' if we emit the
+// branches in this order. See if rearranging a case value would help.
+for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
+ if (I->second == NextBlock) {
+std::swap(*I, BackCase);
+break;
+ }
+}
+ }
+
+ // Create a CaseBlock record representing a conditional branch to
+ // the Case's target mbb if the value being switched on SV is equal
+ // to C.
+ MachineBasicBlock *CurBlock = CR.CaseBB;
+ for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
+MachineBasicBlock *FallThrough;
+if (I != E-1) {
+ FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
+ CurMF->getBasicBlockList().insert(BBI, FallThrough);
+} else {
+ // If the last case doesn't match, go to the default block.
+ FallThrough = Default;
+}
+
+SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, I->first,
+ I->second, FallThrough, CurBlock);
+
+// If emitting the first comparison, just call visitSwitchCase to emit the
+// code into the current block. Otherwise, push the CaseBlock onto the
+// vector to be later processed by SDISel, and insert the node's MBB
+// before the next MBB.
+if (CurBlock == CurMBB)
+ visitSwitchCase(CB);
+else
+ SwitchCases.push_back(CB);
+
+CurBlock = FallThrough;
+ }
+}
+
+/// handleJTSwitchCase - Emit jumptable for current sw
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.394 -> 1.395 --- Log message: SDISel does not preserve all, it changes CFG and other info. --- Diffs of the changes: (+0 -1) SelectionDAGISel.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.394 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.395 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.394Sun Mar 25 10:07:15 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Mar 26 19:53:36 2007 @@ -3776,7 +3776,6 @@ // updates dom and loop info. AU.addRequired(); AU.addRequired(); - AU.setPreservesAll(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.393 -> 1.394
---
Log message:
First step of switch lowering refactoring: perform worklist-driven
strategy, emit JT's where possible.
---
Diffs of the changes: (+253 -180)
SelectionDAGISel.cpp | 433 +--
1 files changed, 253 insertions(+), 180 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.393
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.394
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.393Sun Mar 25
00:00:54 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Mar 25 10:07:15 2007
@@ -405,7 +405,9 @@
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.
std::vector SwitchCases;
- SelectionDAGISel::JumpTable JT;
+ /// JTCases - Vector of JumpTable structures used to communicate
+ /// SwitchInst code generation information.
+ std::vector JTCases;
/// FuncInfo - Information about the function as a whole.
///
@@ -414,7 +416,7 @@
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
FunctionLoweringInfo &funcinfo)
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
- JT(0,0,0,0), FuncInfo(funcinfo) {
+ FuncInfo(funcinfo) {
}
/// getRoot - Return the current virtual root of the Selection DAG.
@@ -497,6 +499,8 @@
// Helper for visitSwitch
void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
void visitJumpTable(SelectionDAGISel::JumpTable &JT);
+ void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
+SelectionDAGISel::JumpTableHeader &JTH);
// These all get lowered before this pass.
void visitInvoke(InvokeInst &I);
@@ -1065,7 +1069,7 @@
Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
} else
Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
-
+
// Set NextBlock to be the MBB immediately after the current one, if any.
// This is used to avoid emitting unnecessary branches to the next block.
MachineBasicBlock *NextBlock = 0;
@@ -1092,8 +1096,10 @@
CurMBB->addSuccessor(CB.FalseBB);
}
+/// visitJumpTable - Emit JumpTable node in the current MBB
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
// Emit the code for the jump table
+ assert(JT.Reg != -1UL && "Should lower JT Header first!");
MVT::ValueType PTy = TLI.getPointerTy();
SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
@@ -1102,6 +1108,57 @@
return;
}
+/// visitJumpTableHeader - This function emits necessary code to produce index
+/// in the JumpTable from switch case.
+void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable
&JT,
+ SelectionDAGISel::JumpTableHeader
&JTH) {
+ // Subtract the lowest switch case value from the value being switched on
+ // and conditional branch to default mbb if the result is greater than the
+ // difference between smallest and largest cases.
+ SDOperand SwitchOp = getValue(JTH.SValue);
+ MVT::ValueType VT = SwitchOp.getValueType();
+ SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
+ DAG.getConstant(JTH.First, VT));
+
+ // The SDNode we just created, which holds the value being switched on
+ // minus the the smallest case value, needs to be copied to a virtual
+ // register so it can be used as an index into the jump table in a
+ // subsequent basic block. This value may be smaller or larger than the
+ // target's pointer type, and therefore require extension or truncating.
+ if (VT > TLI.getPointerTy())
+SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
+ else
+SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
+
+ unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
+ SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
+ JT.Reg = JumpTableReg;
+
+ // Emit the range check for the jump table, and branch to the default
+ // block for the switch statement if the value being switched on exceeds
+ // the largest case in the switch.
+ SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
+ DAG.getConstant(JTH.Last-JTH.First,VT),
+ ISD::SETUGT);
+
+ // Set NextBlock to be the MBB immediately after the current one, if any.
+ // This is used to avoid emitting unnecessary branches to the next block.
+ MachineBasicBlock *NextBlock = 0;
+ MachineFunction::iterator BBI = CurMBB;
+ if (++BBI != CurMBB->getParent()->end())
+NextBlock = BBI;
+
+ SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
+ DAG.getB
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.392 -> 1.393
---
Log message:
Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
---
Diffs of the changes: (+16 -4)
SelectionDAGISel.cpp | 20
1 files changed, 16 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.393
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392Sat Mar 24
21:14:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Mar 25 00:00:54 2007
@@ -2387,14 +2387,23 @@
if (RegVT == ValueVT)
return Val;
+ if (MVT::isVector(RegVT)) {
+assert(ValueVT == MVT::Vector && "Unknown vector conversion!");
+return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
+ DAG.getConstant(MVT::getVectorNumElements(RegVT),
+ MVT::i32),
+ DAG.getValueType(MVT::getVectorBaseType(RegVT)));
+ }
+
if (MVT::isInteger(RegVT)) {
if (ValueVT < RegVT)
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
else
return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
- } else {
-return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
}
+
+ assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT));
+ return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
}
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
@@ -2407,7 +2416,10 @@
// If there is a single register and the types differ, this must be
// a promotion.
if (RegVT != ValueVT) {
- if (MVT::isInteger(RegVT)) {
+ if (MVT::isVector(RegVT)) {
+assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector
cast?");
+Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
+ } else if (MVT::isInteger(RegVT)) {
if (RegVT < ValueVT)
Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
else
@@ -3424,7 +3436,7 @@
// If this value was promoted, truncate it down.
if (ResVal.getValueType() != VT) {
if (VT == MVT::Vector) {
- // Insert a VBITCONVERT to convert from the packed result type to the
+ // Insert a VBIT_CONVERT to convert from the packed result type to
the
// MVT::Vector type.
unsigned NumElems = cast(RetTy)->getNumElements();
const Type *EltTy = cast(RetTy)->getElementType();
___
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llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.391 -> 1.392
TargetLowering.cpp updated: 1.99 -> 1.100
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+28 -24)
SelectionDAGISel.cpp |8
TargetLowering.cpp | 44
2 files changed, 28 insertions(+), 24 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.391
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.391Thu Mar 22
11:38:57 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Mar 24 21:14:49 2007
@@ -2633,9 +2633,9 @@
std::string *Current = &C[0];
// If we have multiple constraints, try to pick the most general one ahead
// of time. This isn't a wonderful solution, but handles common cases.
- TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0][0]);
+ TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
for (unsigned j = 1, e = C.size(); j != e; ++j) {
-TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j][0]);
+TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
if (getConstraintGenerality(ThisFlavor) >
getConstraintGenerality(Flavor)) {
// This constraint letter is more general than the previous one,
@@ -2748,7 +2748,7 @@
case InlineAsm::isOutput: {
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (ConstraintCode.size() == 1) // not a physreg name.
-CTy = TLI.getConstraintType(ConstraintCode[0]);
+CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Memory) {
// Memory output.
@@ -2863,7 +2863,7 @@
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (ConstraintCode.size() == 1) // not a physreg name.
-CTy = TLI.getConstraintType(ConstraintCode[0]);
+CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Other) {
InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.99
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.100
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.99 Wed Mar 21
16:51:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppSat Mar 24 21:14:49 2007
@@ -1828,28 +1828,32 @@
//===--===//
TargetLowering::ConstraintType
-TargetLowering::getConstraintType(char ConstraintLetter) const {
+TargetLowering::getConstraintType(const std::string &Constraint) const {
// FIXME: lots more standard ones to handle.
- switch (ConstraintLetter) {
- default: return C_Unknown;
- case 'r': return C_RegisterClass;
- case 'm':// memory
- case 'o':// offsetable
- case 'V':// not offsetable
-return C_Memory;
- case 'i':// Simple Integer or Relocatable Constant
- case 'n':// Simple Integer
- case 's':// Relocatable Constant
- case 'I':// Target registers.
- case 'J':
- case 'K':
- case 'L':
- case 'M':
- case 'N':
- case 'O':
- case 'P':
-return C_Other;
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'r': return C_RegisterClass;
+case 'm':// memory
+case 'o':// offsetable
+case 'V':// not offsetable
+ return C_Memory;
+case 'i':// Simple Integer or Relocatable Constant
+case 'n':// Simple Integer
+case 's':// Relocatable Constant
+case 'I':// Target registers.
+case 'J':
+case 'K':
+case 'L':
+case 'M':
+case 'N':
+case 'O':
+case 'P':
+ return C_Other;
+}
}
+ // TODO: Handle registers.
+ return C_Unknown;
}
/// isOperandValidForConstraint - Return the specified operand (possibly
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.390 -> 1.391 --- Log message: Change uses of Function::front to Function::getEntryBlock for readability. --- Diffs of the changes: (+1 -1) SelectionDAGISel.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.390 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.391 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.390Tue Mar 20 14:32:11 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 22 11:38:57 2007 @@ -4328,7 +4328,7 @@ std::vector UnorderedChains; // Lower any arguments needed in this block if this is the entry block. - if (LLVMBB == &LLVMBB->getParent()->front()) + if (LLVMBB == &LLVMBB->getParent()->getEntryBlock()) LowerArguments(LLVMBB, SDL, UnorderedChains); BB = FuncInfo.MBBMap[LLVMBB]; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.389 -> 1.390
---
Log message:
Minor bug.
---
Diffs of the changes: (+2 -1)
SelectionDAGISel.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.389
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.390
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.389Sat Mar 17
03:53:30 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 20 14:32:11 2007
@@ -4009,7 +4009,8 @@
// Check if it is possible to fold the expression to address mode.
if (UseTy &&
-TLI.isLegalAddressExpression(Instruction::Add,
BinOp->getOperand(0),
+TLI.isLegalAddressExpression(BinOp->getOpcode(),
+ BinOp->getOperand(0),
BinOp->getOperand(1), UseTy)) {
DestBBs.insert(UserBB);
MadeChange = true;
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.388 -> 1.389 --- Log message: Use SmallSet instead of std::set. --- Diffs of the changes: (+1 -1) SelectionDAGISel.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.388 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.389 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.388Sat Mar 17 03:22:49 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Mar 17 03:53:30 2007 @@ -3983,7 +3983,7 @@ return false; // DestBBs - These are the blocks where a copy of BinOp will be inserted. - std::set DestBBs; + SmallSet DestBBs; BasicBlock *DefBB = BinOp->getParent(); bool MadeChange = false; for (Value::use_iterator UI = BinOp->use_begin(), E = BinOp->use_end(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.387 -> 1.388
---
Log message:
If sdisel has decided to sink GEP index expression into any BB. Replace all uses
in that BB.
---
Diffs of the changes: (+37 -22)
SelectionDAGISel.cpp | 59 +++
1 files changed, 37 insertions(+), 22 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.387
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.388
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.387Fri Mar 16
13:32:30 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Mar 17 03:22:49 2007
@@ -3982,18 +3982,13 @@
BinOp->getOpcode() != Instruction::Sub)
return false;
- /// InsertedOps - Only insert a duplicate in each block once.
- std::map InsertedOps;
-
- bool MadeChange = false;
+ // DestBBs - These are the blocks where a copy of BinOp will be inserted.
+ std::set DestBBs;
BasicBlock *DefBB = BinOp->getParent();
+ bool MadeChange = false;
for (Value::use_iterator UI = BinOp->use_begin(), E = BinOp->use_end();
- UI != E; ) {
+ UI != E; ++UI) {
Instruction *User = cast(*UI);
-
-// Preincrement use iterator so we don't invalidate it.
-++UI;
-
// Only look for GEP use in another block.
if (User->getParent() == DefBB) continue;
@@ -4016,28 +4011,48 @@
if (UseTy &&
TLI.isLegalAddressExpression(Instruction::Add,
BinOp->getOperand(0),
BinOp->getOperand(1), UseTy)) {
- // Sink it into user block.
- BinaryOperator *&InsertedOp = InsertedOps[UserBB];
- if (!InsertedOp) {
-BasicBlock::iterator InsertPt = UserBB->begin();
-while (isa(InsertPt)) ++InsertPt;
-
-InsertedOp =
- BinaryOperator::create(BinOp->getOpcode(), BinOp->getOperand(0),
- BinOp->getOperand(1), "", InsertPt);
- }
-
- User->replaceUsesOfWith(BinOp, InsertedOp);
+ DestBBs.insert(UserBB);
MadeChange = true;
}
}
}
}
+ // Nothing to do.
+ if (!MadeChange)
+return false;
+
+ /// InsertedOps - Only insert a duplicate in each block once.
+ std::map InsertedOps;
+ for (Value::use_iterator UI = BinOp->use_begin(), E = BinOp->use_end();
+ UI != E; ) {
+Instruction *User = cast(*UI);
+BasicBlock *UserBB = User->getParent();
+
+// Preincrement use iterator so we don't invalidate it.
+++UI;
+
+// If any user in this BB wants it, replace all the uses in the BB.
+if (DestBBs.count(UserBB)) {
+ // Sink it into user block.
+ BinaryOperator *&InsertedOp = InsertedOps[UserBB];
+ if (!InsertedOp) {
+BasicBlock::iterator InsertPt = UserBB->begin();
+while (isa(InsertPt)) ++InsertPt;
+
+InsertedOp =
+ BinaryOperator::create(BinOp->getOpcode(), BinOp->getOperand(0),
+ BinOp->getOperand(1), "", InsertPt);
+ }
+
+ User->replaceUsesOfWith(BinOp, InsertedOp);
+}
+ }
+
if (BinOp->use_empty())
BinOp->eraseFromParent();
- return MadeChange;
+ return true;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.386 -> 1.387
---
Log message:
Turn on GEP index sinking by default.
---
Diffs of the changes: (+0 -7)
SelectionDAGISel.cpp |7 ---
1 files changed, 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.386
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.387
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.386Fri Mar 16
12:50:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Mar 16 13:32:30 2007
@@ -59,10 +59,6 @@
static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
#endif
-static cl::opt
-EnableGEPIndexSink("enable-gep-index-sinking", cl::Hidden,
- cl::desc("Sink invariant GEP index computation into use
blocks"));
-
//===-===//
///
/// RegisterScheduler class - Track the registration of instruction schedulers.
@@ -3981,9 +3977,6 @@
/// addressing mode of the load / store uses.
static bool SinkInvariantGEPIndex(BinaryOperator *BinOp, LoopInfo *loopInfo,
const TargetLowering &TLI) {
- if (!EnableGEPIndexSink)
-return false;
-
// Only look at Add / Sub for now.
if (BinOp->getOpcode() != Instruction::Add &&
BinOp->getOpcode() != Instruction::Sub)
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.385 -> 1.386
---
Log message:
Stupid bug.
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.385
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.386
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.385Fri Mar 16
03:46:27 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Mar 16 12:50:20 2007
@@ -4009,7 +4009,7 @@
Loop *L = loopInfo->getLoopFor(UserBB);
// Only sink if expression is a loop invariant in the use BB.
- if (isLoopInvariantInst(BinOp, L) && !User->use_empty()) {
+ if (L && isLoopInvariantInst(BinOp, L) && !User->use_empty()) {
const Type *UseTy = NULL;
// FIXME: We are assuming all the uses of the GEP will have the
// same type.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.384 -> 1.385
---
Log message:
Sink a binary expression into its use blocks if it is a loop invariant
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.
---
Diffs of the changes: (+92 -0)
SelectionDAGISel.cpp | 92 +++
1 files changed, 92 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.384
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.385
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.384Thu Mar 8
16:29:47 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Mar 16 03:46:27 2007
@@ -13,6 +13,7 @@
#define DEBUG_TYPE "isel"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CallingConv.h"
@@ -58,6 +59,9 @@
static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
#endif
+static cl::opt
+EnableGEPIndexSink("enable-gep-index-sinking", cl::Hidden,
+ cl::desc("Sink invariant GEP index computation into use
blocks"));
//===-===//
///
@@ -3703,6 +3707,8 @@
// FIXME: we only modify the CFG to split critical edges. This
// updates dom and loop info.
AU.addRequired();
+ AU.addRequired();
+ AU.setPreservesAll();
}
@@ -3959,6 +3965,88 @@
return true;
}
+/// isLoopInvariantInst - Returns true if all operands of the instruction are
+/// loop invariants in the specified loop.
+static bool isLoopInvariantInst(Instruction *I, Loop *L) {
+ // The instruction is loop invariant if all of its operands are
loop-invariant
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
+if (!L->isLoopInvariant(I->getOperand(i)))
+ return false;
+ return true;
+}
+
+/// SinkInvariantGEPIndex - If a GEP instruction has a variable index that has
+/// been hoisted out of the loop by LICM pass, sink it back into the use BB
+/// if it can be determined that the index computation can be folded into the
+/// addressing mode of the load / store uses.
+static bool SinkInvariantGEPIndex(BinaryOperator *BinOp, LoopInfo *loopInfo,
+ const TargetLowering &TLI) {
+ if (!EnableGEPIndexSink)
+return false;
+
+ // Only look at Add / Sub for now.
+ if (BinOp->getOpcode() != Instruction::Add &&
+ BinOp->getOpcode() != Instruction::Sub)
+return false;
+
+ /// InsertedOps - Only insert a duplicate in each block once.
+ std::map InsertedOps;
+
+ bool MadeChange = false;
+ BasicBlock *DefBB = BinOp->getParent();
+ for (Value::use_iterator UI = BinOp->use_begin(), E = BinOp->use_end();
+ UI != E; ) {
+Instruction *User = cast(*UI);
+
+// Preincrement use iterator so we don't invalidate it.
+++UI;
+
+// Only look for GEP use in another block.
+if (User->getParent() == DefBB) continue;
+
+if (isa(User)) {
+ BasicBlock *UserBB = User->getParent();
+ Loop *L = loopInfo->getLoopFor(UserBB);
+
+ // Only sink if expression is a loop invariant in the use BB.
+ if (isLoopInvariantInst(BinOp, L) && !User->use_empty()) {
+const Type *UseTy = NULL;
+// FIXME: We are assuming all the uses of the GEP will have the
+// same type.
+Instruction *GEPUser = cast(*User->use_begin());
+if (LoadInst *Load = dyn_cast(GEPUser))
+ UseTy = Load->getType();
+else if (StoreInst *Store = dyn_cast(GEPUser))
+ UseTy = Store->getOperand(0)->getType();
+
+// Check if it is possible to fold the expression to address mode.
+if (UseTy &&
+TLI.isLegalAddressExpression(Instruction::Add,
BinOp->getOperand(0),
+ BinOp->getOperand(1), UseTy)) {
+ // Sink it into user block.
+ BinaryOperator *&InsertedOp = InsertedOps[UserBB];
+ if (!InsertedOp) {
+BasicBlock::iterator InsertPt = UserBB->begin();
+while (isa(InsertPt)) ++InsertPt;
+
+InsertedOp =
+ BinaryOperator::create(BinOp->getOpcode(), BinOp->getOperand(0),
+ BinOp->getOperand(1), "", InsertPt);
+ }
+
+ User->replaceUsesOfWith(BinOp, InsertedOp);
+ MadeChange = true;
+}
+ }
+}
+ }
+
+ if (BinOp->use_empty())
+ BinOp->eraseFromParent();
+
+ return MadeChange;
+}
+
/// SplitEdgeNicely - Split the critical edge from TI to it's specified
/// successor if it will improve codegen. We only do this if the successor has
@@ -4021,6 +4109,8 @@
RegMap = MF.getSSARegMap();
DOUT << "\n\n\n=== " << Fn.getName() << "\n";
+ LoopInfo *loopInfo = &getAnalysis();
+
// F
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.383 -> 1.384
---
Log message:
implement support for floating point constants used as inline asm memory
operands.
---
Diffs of the changes: (+7 -2)
SelectionDAGISel.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.383
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.384
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.383Thu Mar 8
01:07:03 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 8 16:29:47 2007
@@ -2882,9 +2882,14 @@
} else if (CTy == TargetLowering::C_Memory) {
// Memory input.
-// Check that the operand isn't a float.
+// If the operand is a float, spill to a constant pool entry to get its
+// address.
+if (ConstantFP *Val = dyn_cast(I.getOperand(OpNum-1)))
+ InOperandVal = DAG.getConstantPool(Val, TLI.getPointerTy());
+
if (!MVT::isInteger(InOperandVal.getValueType())) {
- cerr << "Match failed, can't handle floats yet!\n";
+ cerr << "Match failed, cannot handle this yet!\n";
+ InOperandVal.Val->dump();
exit(1);
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.382 -> 1.383
---
Log message:
make this fail even in non-assert builds.
---
Diffs of the changes: (+4 -2)
SelectionDAGISel.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.382
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.383
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.382Wed Mar 7
10:25:08 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 8 01:07:03 2007
@@ -2883,8 +2883,10 @@
// Memory input.
// Check that the operand isn't a float.
-if (!MVT::isInteger(InOperandVal.getValueType()))
- assert(0 && "MATCH FAIL!");
+if (!MVT::isInteger(InOperandVal.getValueType())) {
+ cerr << "Match failed, can't handle floats yet!\n";
+ exit(1);
+}
// Extend/truncate to the right pointer type if needed.
MVT::ValueType PtrType = TLI.getPointerTy();
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> // FIXME: Distinguish between a formal with no [sz]ext
> attribute from one
> // that is zero extended!
> if (FTy->paramHasAttr(j, FunctionType::ZExtAttribute))
> - Flags |= 0;
> + Flags &= ~(SDISelParamFlags::Signed);
this should set the zext bit.
> case Promote:
>if (MVT::isInteger(VT)) {
> -unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND :
> ISD::ZERO_EXTEND;
> +unsigned ExtOp = Args[i].isSigned ? ISD::SIGN_EXTEND :
> ISD::ZERO_EXTEND;
> Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
>} else {
> assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
This should use ZERO_EXTEND if zext, SIGN_EXTEND if sext, and
ANY_EXTEND if neither,
-Chris
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.380 -> 1.381
---
Log message:
Enumerate SDISel formal parameter attributes. Make use of new
enumeration.
---
Diffs of the changes: (+24 -22)
SelectionDAGISel.cpp | 46 --
1 files changed, 24 insertions(+), 22 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.380
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.381
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.380Sun Mar 4
18:00:42 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 6 00:10:33 2007
@@ -3099,22 +3099,21 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++j) {
MVT::ValueType VT = getValueType(I->getType());
-bool isInReg = FTy->paramHasAttr(j, FunctionType::InRegAttribute);
-bool isSRet = FTy->paramHasAttr(j, FunctionType::StructRetAttribute);
+unsigned Flags = SDISelParamFlags::NoFlagSet;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(I->getType());
-// Flags[31:27] -> OriginalAlignment
-// Flags[2] -> isSRet
-// Flags[1] -> isInReg
-// Flags[0] -> isSigned
-unsigned Flags = (isInReg << 1) | (isSRet << 2) | (OriginalAlignment <<
27);
// FIXME: Distinguish between a formal with no [sz]ext attribute from one
// that is zero extended!
if (FTy->paramHasAttr(j, FunctionType::ZExtAttribute))
- Flags |= 0;
+ Flags &= ~(SDISelParamFlags::Signed);
if (FTy->paramHasAttr(j, FunctionType::SExtAttribute))
- Flags |= 1;
+ Flags |= SDISelParamFlags::Signed;
+if (FTy->paramHasAttr(j, FunctionType::InRegAttribute))
+ Flags |= SDISelParamFlags::InReg;
+if (FTy->paramHasAttr(j, FunctionType::StructRetAttribute))
+ Flags |= SDISelParamFlags::StructReturn;
+Flags |= (OriginalAlignment << SDISelParamFlags::OrigAlignmentOffs);
switch (getTypeAction(VT)) {
default: assert(0 && "Unknown type action!");
@@ -3136,7 +3135,9 @@
for (unsigned i = 0; i != NumVals; ++i) {
RetVals.push_back(NVT);
// if it isn't first piece, alignment must be 1
- if (i == 1) Flags = (Flags & 0x07ff) | (1 << 27);
+ if (i > 0)
+Flags = (Flags & (~SDISelParamFlags::OrigAlignment)) |
+ (1 << SDISelParamFlags::OrigAlignmentOffs);
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
}
} else {
@@ -3245,7 +3246,8 @@
if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
// if it isn't first piece, alignment must be 1
if (!isFirst)
- Flags = (Flags & 0x07ff) | (1 << 27);
+ Flags = (Flags & (~SDISelParamFlags::OrigAlignment)) |
+(1 << SDISelParamFlags::OrigAlignmentOffs);
Ops.push_back(Arg);
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
return;
@@ -3292,18 +3294,18 @@
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
MVT::ValueType VT = getValueType(Args[i].Ty);
SDOperand Op = Args[i].Node;
-bool isSigned = Args[i].isSigned;
-bool isInReg = Args[i].isInReg;
-bool isSRet = Args[i].isSRet;
+unsigned Flags = SDISelParamFlags::NoFlagSet;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(Args[i].Ty);
-// Flags[31:27] -> OriginalAlignment
-// Flags[2] -> isSRet
-// Flags[1] -> isInReg
-// Flags[0] -> isSigned
-unsigned Flags = (isSRet << 2) | (isInReg << 1) | unsigned(isSigned) |
- (OriginalAlignment << 27);
-
+
+if (Args[i].isSigned)
+ Flags |= SDISelParamFlags::Signed;
+if (Args[i].isInReg)
+ Flags |= SDISelParamFlags::InReg;
+if (Args[i].isSRet)
+ Flags |= SDISelParamFlags::StructReturn;
+Flags |= OriginalAlignment << SDISelParamFlags::OrigAlignmentOffs;
+
switch (getTypeAction(VT)) {
default: assert(0 && "Unknown type action!");
case Legal:
@@ -3312,7 +3314,7 @@
break;
case Promote:
if (MVT::isInteger(VT)) {
-unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+unsigned ExtOp = Args[i].isSigned ? ISD::SIGN_EXTEND :
ISD::ZERO_EXTEND;
Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
} else {
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.379 -> 1.380
---
Log message:
Unbreak VC++ build.
---
Diffs of the changes: (+1 -1)
SelectionDAGISel.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.379
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.380
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.379Thu Mar 1
14:24:30 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Mar 4 18:00:42 2007
@@ -3301,7 +3301,7 @@
// Flags[2] -> isSRet
// Flags[1] -> isInReg
// Flags[0] -> isSigned
-unsigned Flags = (isSRet << 2) | (isInReg << 1) | isSigned |
+unsigned Flags = (isSRet << 2) | (isInReg << 1) | unsigned(isSigned) |
(OriginalAlignment << 27);
switch (getTypeAction(VT)) {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.378 -> 1.379
---
Log message:
Lower eh filter intrinsic.
---
Diffs of the changes: (+4 -1)
SelectionDAGISel.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.378
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.379
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.378Wed Feb 28
12:37:04 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 1 14:24:30 2007
@@ -2110,7 +2110,8 @@
return 0;
}
- case Intrinsic::eh_selector: {
+ case Intrinsic::eh_selector:
+ case Intrinsic::eh_filter:{
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
if (MMI) {
@@ -2120,6 +2121,8 @@
isa(CE->getOperand(0)) &&
"Personality should be a function");
MMI->addPersonality(CurMBB, cast(CE->getOperand(0)));
+ if (Intrinsic == Intrinsic::eh_filter)
+MMI->setIsFilterLandingPad(CurMBB);
// Gather all the type infos for this landing pad and pass them along to
// MachineModuleInfo.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.377 -> 1.378
---
Log message:
MERGE_VALUES unnecessary.
---
Diffs of the changes: (+4 -12)
SelectionDAGISel.cpp | 16
1 files changed, 4 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.377
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.378
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.377Sun Feb 25
20:56:58 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Feb 28 12:37:04 2007
@@ -2105,16 +2105,12 @@
setValue(&I, Op);
DAG.setRoot(Op.getValue(1));
} else {
- SDOperand Op = DAG.getNode(ISD::MERGE_VALUES, TLI.getPointerTy(),
- DAG.getConstant(0, TLI.getPointerTy()),
- DAG.getRoot());
- setValue(&I, Op);
- DAG.setRoot(Op.getValue(1));
+ setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
}
return 0;
}
- case Intrinsic::eh_handlers: {
+ case Intrinsic::eh_selector: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
if (MMI) {
@@ -2147,7 +2143,7 @@
if (Reg) CurMBB->addLiveIn(Reg);
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
SDOperand Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -2155,11 +2151,7 @@
setValue(&I, Op);
DAG.setRoot(Op.getValue(1));
} else {
- SDOperand Op = DAG.getNode(ISD::MERGE_VALUES, TLI.getPointerTy(),
- DAG.getConstant(0, TLI.getPointerTy()),
- getValue(I.getOperand(1)));
- setValue(&I, Op);
- DAG.setRoot(Op.getValue(1));
+ setValue(&I, DAG.getConstant(0, MVT::i32));
}
return 0;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.376 -> 1.377
---
Log message:
track signedness of formal argument, though we have a fixme here.
---
Diffs of the changes: (+8 -0)
SelectionDAGISel.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.376
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.377
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.376Sun Feb 25
15:43:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Feb 25 20:56:58 2007
@@ -3111,8 +3111,16 @@
// Flags[31:27] -> OriginalAlignment
// Flags[2] -> isSRet
// Flags[1] -> isInReg
+// Flags[0] -> isSigned
unsigned Flags = (isInReg << 1) | (isSRet << 2) | (OriginalAlignment <<
27);
+// FIXME: Distinguish between a formal with no [sz]ext attribute from one
+// that is zero extended!
+if (FTy->paramHasAttr(j, FunctionType::ZExtAttribute))
+ Flags |= 0;
+if (FTy->paramHasAttr(j, FunctionType::SExtAttribute))
+ Flags |= 1;
+
switch (getTypeAction(VT)) {
default: assert(0 && "Unknown type action!");
case Legal:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.375 -> 1.376
---
Log message:
Fix for PR1224: http://llvm.org/PR1224 .
---
Diffs of the changes: (+50 -35)
SelectionDAGISel.cpp | 85 ++-
1 files changed, 50 insertions(+), 35 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.375
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.376
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.375Sun Feb 25
12:40:32 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Feb 25 15:43:59 2007
@@ -500,6 +500,7 @@
// These all get lowered before this pass.
void visitInvoke(InvokeInst &I);
+ void visitInvoke(InvokeInst &I, bool AsTerminator);
void visitUnwind(UnwindInst &I);
void visitScalarBinary(User &I, unsigned OpCode);
@@ -1102,44 +1103,49 @@
}
void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
+ assert(0 && "Should never be visited directly");
+}
+void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) {
// Retrieve successors.
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
- // Mark landing pad so that it doesn't get deleted in branch folding.
- LandingPad->setIsLandingPad();
-
- // Insert a label before the invoke call to mark the try range.
- // This can be used to detect deletion of the invoke via the
- // MachineModuleInfo.
- MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- unsigned BeginLabel = MMI->NextLabelID();
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(BeginLabel, MVT::i32)));
-
- LowerCallTo(I, I.getCalledValue()->getType(),
- I.getCallingConv(),
- false,
- getValue(I.getOperand(0)),
- 3);
-
- // Insert a label before the invoke call to mark the try range.
- // This can be used to detect deletion of the invoke via the
- // MachineModuleInfo.
- unsigned EndLabel = MMI->NextLabelID();
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(EndLabel, MVT::i32)));
-
- // Inform MachineModuleInfo of range.
- MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
-
- // Drop into normal successor.
- DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
- DAG.getBasicBlock(Return)));
-
- // Update successor info
- CurMBB->addSuccessor(Return);
- CurMBB->addSuccessor(LandingPad);
+ if (!AsTerminator) {
+// Mark landing pad so that it doesn't get deleted in branch folding.
+LandingPad->setIsLandingPad();
+
+// Insert a label before the invoke call to mark the try range.
+// This can be used to detect deletion of the invoke via the
+// MachineModuleInfo.
+MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+unsigned BeginLabel = MMI->NextLabelID();
+DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+DAG.getConstant(BeginLabel, MVT::i32)));
+
+LowerCallTo(I, I.getCalledValue()->getType(),
+ I.getCallingConv(),
+ false,
+ getValue(I.getOperand(0)),
+ 3);
+
+// Insert a label before the invoke call to mark the try range.
+// This can be used to detect deletion of the invoke via the
+// MachineModuleInfo.
+unsigned EndLabel = MMI->NextLabelID();
+DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+DAG.getConstant(EndLabel, MVT::i32)));
+
+// Inform MachineModuleInfo of range.
+MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
+
+// Update successor info
+CurMBB->addSuccessor(Return);
+CurMBB->addSuccessor(LandingPad);
+ } else {
+// Drop into normal successor.
+DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
+DAG.getBasicBlock(Return)));
+ }
}
void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
@@ -4216,6 +4222,10 @@
for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
I != E; ++I)
SDL.visit(*I);
+
+ // Lower call part of invoke.
+ InvokeInst *Invoke = dyn_cast(LLVMBB->getTerminator());
+ if (Invoke) SDL.visitInvoke(*Invoke, false);
// Ensure that all instructions which are used outside of their defining
// blocks are available as virtual registers.
@@ -4328,7 +4338,12 @@
}
// Lower the terminator after the copies are emitted.
- SDL.visit(*LLVMBB->getTerminator());
+ if (Invoke) {
+// Just the branch part of invoke.
+SDL.visitInvoke(*Invoke, true);
+ } else {
+SDL.visit(*LLVMBB->getTerminator());
+ }
