[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.272 - 1.273
---
Log message:
If a function is vararg, never pass inreg arguments in registers. Thanks to
Anton for half of this patch.
---
Diffs of the changes: (+2 -1)
PPCISelLowering.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.272
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.273
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.272 Thu Jun 14 17:58:02 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jun 18 19:13:10 2007
@@ -1830,7 +1830,8 @@
static SDOperand LowerRET(SDOperand Op, SelectionDAG DAG, TargetMachine TM) {
SmallVectorCCValAssign, 16 RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()-getCallingConv();
- CCState CCInfo(CC, TM, RVLocs);
+ bool isVarArg = DAG.getMachineFunction().getFunction()-isVarArg();
+ CCState CCInfo(CC, isVarArg, TM, RVLocs);
CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
// If this is the first return lowered for this function, add the regs to the
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.273 - 1.274
---
Log message:
describe an argument, hide it.
---
Diffs of the changes: (+3 -1)
PPCISelLowering.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.273
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.274
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.273 Mon Jun 18 19:13:10 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 19 00:46:06 2007
@@ -32,7 +32,9 @@
#include llvm/Support/CommandLine.h
using namespace llvm;
-static cl::optbool EnablePPCPreinc(enable-ppc-preinc);
+static cl::optbool EnablePPCPreinc(enable-ppc-preinc,
+cl::desc(enable preincrement load/store generation on PPC (experimental)),
+ cl::Hidden);
PPCTargetLowering::PPCTargetLowering(PPCTargetMachine TM)
: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.270 - 1.271
---
Log message:
Apply this patch:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.270
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.271
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.270 Mon May 14 20:31:05 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri May 18 18:21:46 2007
@@ -222,7 +222,7 @@
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
- VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+ VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.269 - 1.270
---
Log message:
fix some subtle inline asm selection issues
---
Diffs of the changes: (+17 -9)
PPCISelLowering.cpp | 26 +-
1 files changed, 17 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.269
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.270
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.269 Mon Apr 9 17:10:05 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon May 14 20:31:05 2007
@@ -3326,31 +3326,39 @@
case 'N':
case 'O':
case 'P': {
-if (!isaConstantSDNode(Op)) return SDOperand(0,0);// Must be an
immediate.
-unsigned Value = castConstantSDNode(Op)-getValue();
+ConstantSDNode *CST = dyn_castConstantSDNode(Op);
+if (!CST) return SDOperand(0, 0); // Must be an immediate to match.
+unsigned Value = CST-getValue();
switch (Letter) {
default: assert(0 Unknown constraint letter!);
case 'I': // I is a signed 16-bit constant.
- if ((short)Value == (int)Value) return Op;
+ if ((short)Value == (int)Value)
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'J': // J is a constant with only the high-order 16 bits nonzero.
case 'L': // L is a signed 16-bit constant shifted left 16 bits.
- if ((short)Value == 0) return Op;
+ if ((short)Value == 0)
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'K': // K is a constant with only the low-order 16 bits nonzero.
- if ((Value 16) == 0) return Op;
+ if ((Value 16) == 0)
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'M': // M is a constant that is greater than 31.
- if (Value 31) return Op;
+ if (Value 31)
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'N': // N is a positive constant that is an exact power of two.
- if ((int)Value 0 isPowerOf2_32(Value)) return Op;
+ if ((int)Value 0 isPowerOf2_32(Value))
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'O': // O is the constant zero.
- if (Value == 0) return Op;
+ if (Value == 0)
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
case 'P': // P is a constant whose negation is a signed 16-bit constant.
- if ((short)-Value == (int)-Value) return Op;
+ if ((short)-Value == (int)-Value)
+return DAG.getTargetConstant(Value, Op.getValueType());
break;
}
break;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.267 - 1.268
PPCISelLowering.h updated: 1.64 - 1.65
---
Log message:
Starting implementation of the ELF32 ABI specification of varargs handling.
LowerVASTART emits the right code if the subtarget is ELF32, the other
intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
---
Diffs of the changes: (+177 -9)
PPCISelLowering.cpp | 180 +---
PPCISelLowering.h |6 +
2 files changed, 177 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.267
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.268
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.267 Tue Apr 3 07:35:28 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 3 08:59:52 2007
@@ -169,8 +169,13 @@
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);
+ // VAARG is custom lowered with ELF 32 ABI
+ if (TM.getSubtargetPPCSubtarget().isELF32_ABI())
+setOperationAction(ISD::VAARG, MVT::Other, Custom);
+ else
+setOperationAction(ISD::VAARG, MVT::Other, Expand);
+
// Use the default implementation.
- setOperationAction(ISD::VAARG , MVT::Other, Expand);
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
@@ -1086,15 +1091,96 @@
return SDOperand();
}
+static SDOperand LowerVAARG(SDOperand Op, SelectionDAG DAG,
+ int VarArgsFrameIndex,
+ int VarArgsStackOffset,
+ unsigned VarArgsNumGPR,
+ unsigned VarArgsNumFPR,
+ const PPCSubtarget Subtarget) {
+
+ assert(0 VAARG in ELF32 ABI not implemented yet!);
+}
+
static SDOperand LowerVASTART(SDOperand Op, SelectionDAG DAG,
- unsigned VarArgsFrameIndex) {
- // vastart just stores the address of the VarArgsFrameIndex slot into the
- // memory location argument.
+ int VarArgsFrameIndex,
+ int VarArgsStackOffset,
+ unsigned VarArgsNumGPR,
+ unsigned VarArgsNumFPR,
+ const PPCSubtarget Subtarget) {
+
+ if (Subtarget.isMachoABI()) {
+// vastart just stores the address of the VarArgsFrameIndex slot into the
+// memory location argument.
+MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+SrcValueSDNode *SV = castSrcValueSDNode(Op.getOperand(2));
+return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV-getValue(),
+SV-getOffset());
+ }
+
+ // For ELF 32 ABI we follow the layout of the va_list struct.
+ // We suppose the given va_list is already allocated.
+ //
+ // typedef struct {
+ // char gpr; /* index into the array of 8 GPRs
+ // * stored in the register save area
+ // * gpr=0 corresponds to r3,
+ // * gpr=1 to r4, etc.
+ // */
+ // char fpr; /* index into the array of 8 FPRs
+ // * stored in the register save area
+ // * fpr=0 corresponds to f1,
+ // * fpr=1 to f2, etc.
+ // */
+ // char *overflow_arg_area;
+ ///* location on stack that holds
+ // * the next overflow argument
+ // */
+ // char *reg_save_area;
+ // /* where r3:r10 and f1:f8 (if saved)
+ //* are stored
+ //*/
+ // } va_list[1];
+
+
+ SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
+ SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
+
+
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+
+ SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
+
+ SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
+ PtrVT);
+ SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
+ PtrVT);
+ SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
+
SrcValueSDNode *SV = castSrcValueSDNode(Op.getOperand(2));
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV-getValue(),
+
+ // Store first byte : number of int regs
+ SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
+ Op.getOperand(1), SV-getValue(),
+
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.264 - 1.265
PPCISelLowering.h updated: 1.63 - 1.64
---
Log message:
implement the new addressing mode description hook.
---
Diffs of the changes: (+38 -1)
PPCISelLowering.cpp | 35 ++-
PPCISelLowering.h |4
2 files changed, 38 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.265
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264 Tue Mar 27 11:33:08 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Mar 30 18:15:24 2007
@@ -3199,6 +3199,39 @@
return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
}
+// isLegalAddressingMode - Return true if the addressing mode represented
+// by AM is legal for this target, for a load/store of the specified type.
+bool PPCTargetLowering::isLegalAddressingMode(const AddrMode AM,
+ const Type *Ty) const {
+ // FIXME: PPC does not allow r+i addressing modes for vectors!
+
+ // PPC allows a sign-extended 16-bit immediate field.
+ if (AM.BaseOffs = -(1LL 16) || AM.BaseOffs = (1LL 16)-1)
+return false;
+
+ // No global is ever allowed as a base.
+ if (AM.BaseGV)
+return false;
+
+ // PPC only support r+r,
+ switch (AM.Scale) {
+ case 0: // r+i or just i, depending on HasBaseReg.
+break;
+ case 1:
+if (AM.HasBaseReg AM.BaseOffs) // r+r+i is not allowed.
+ return false;
+// Otherwise we have r+r or r+i.
+break;
+ case 2:
+if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
+ return false;
+// Allow 2*r as r+r.
+break;
+ }
+
+ return true;
+}
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
@@ -3208,7 +3241,7 @@
}
bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
- return TargetLowering::isLegalAddressImmediate(GV);
+ return false;
}
SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG DAG)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.64
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Fri Mar 30 18:15:24 2007
@@ -236,6 +236,10 @@
SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
SelectionDAG DAG);
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+virtual bool isLegalAddressingMode(const AddrMode AM, const Type
*Ty)const;
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.263 - 1.264
---
Log message:
The C standards do say that char may either be a signed char or unsigned
char and it is up to the compilers implementation or the platform which is
followed.
http://www.arm.linux.org.uk/docs/faqs/signedchar.php
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.263
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.263 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Mar 27 11:33:08 2007
@@ -2219,7 +2219,7 @@
// Check to see if this is a wide variety of vsplti*, binop self cases.
unsigned SplatBitSize = SplatSize*8;
-static const char SplatCsts[] = {
+static const signed char SplatCsts[] = {
-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
};
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.262 - 1.263
PPCISelLowering.h updated: 1.62 - 1.63
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+15 -13)
PPCISelLowering.cpp | 26 ++
PPCISelLowering.h |2 +-
2 files changed, 15 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.262
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.263
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.262 Tue Mar 13 10:02:46 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -3105,20 +3105,22 @@
}
-/// getConstraintType - Given a constraint letter, return the type of
+/// getConstraintType - Given a constraint, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
-PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
- default: break;
- case 'b':
- case 'r':
- case 'f':
- case 'v':
- case 'y':
-return C_RegisterClass;
- }
- return TargetLowering::getConstraintType(ConstraintLetter);
+PPCTargetLowering::getConstraintType(const std::string Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'b':
+case 'r':
+case 'f':
+case 'v':
+case 'y':
+ return C_RegisterClass;
+}
+ }
+ return TargetLowering::getConstraintType(Constraint);
}
std::pairunsigned, const TargetRegisterClass*
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.62
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.62 Mon Mar 12 18:29:01 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sat Mar 24 21:14:49 2007
@@ -229,7 +229,7 @@
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string Constraint) const;
std::pairunsigned, const TargetRegisterClass*
getRegForInlineAsmConstraint(const std::string Constraint,
MVT::ValueType VT) const;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.261 - 1.262
---
Log message:
Stack and register alignment of call arguments in the ELF ABI
---
Diffs of the changes: (+52 -6)
PPCISelLowering.cpp | 58 ++--
1 files changed, 52 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.261
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.262
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.261 Mon Mar 12 18:29:01 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Mar 13 10:02:46 2007
@@ -1132,6 +1132,7 @@
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
bool isMachoABI = Subtarget.isMachoABI();
+ bool isELF_ABI = Subtarget.isELF_ABI();
unsigned PtrByteSize = isPPC64 ? 8 : 4;
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
@@ -1163,17 +1164,30 @@
// Add DAG nodes to load the arguments or copy them out of registers. On
// entry to a function on PPC, the arguments start after the linkage area,
// although the first ones are often in registers.
+ //
+ // In the ELF ABI, GPRs and stack are double word align: an argument
+ // represented with two words (long long or double) must be copied to an
+ // even GPR_idx value or to an even ArgOffset value.
+
for (unsigned ArgNo = 0, e = Op.Val-getNumValues()-1; ArgNo != e; ++ArgNo) {
SDOperand ArgVal;
bool needsLoad = false;
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
unsigned ArgSize = ObjSize;
+unsigned Flags = castConstantSDNode(Op.getOperand(ArgNo+3))-getValue();
+unsigned AlignFlag = 1 ISD::ParamFlags::OrigAlignmentOffs;
+// See if next argument requires stack alignment in ELF
+bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 e)
+ (castConstantSDNode(Op.getOperand(ArgNo+4))-getValue() AlignFlag)
+ (!(Flags AlignFlag)));
unsigned CurArgOffset = ArgOffset;
switch (ObjectVT) {
default: assert(0 Unhandled argument type!);
case MVT::i32:
+ // Double word align in ELF
+ if (Expand isELF_ABI !isPPC64) GPR_idx += (GPR_idx % 2);
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
@@ -1183,6 +1197,9 @@
needsLoad = true;
ArgSize = PtrByteSize;
}
+ // Stack align in ELF
+ if (needsLoad Expand isELF_ABI !isPPC64)
+ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
// All int arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
break;
@@ -1204,7 +1221,7 @@
case MVT::f64:
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
- if (GPR_idx != Num_GPR_Regs) {
+ if (GPR_idx != Num_GPR_Regs isMachoABI) {
++GPR_idx;
if (ObjSize == 8 GPR_idx != Num_GPR_Regs !isPPC64)
++GPR_idx;
@@ -1222,6 +1239,9 @@
needsLoad = true;
}
+ // Stack align in ELF
+ if (needsLoad Expand isELF_ABI !isPPC64)
+ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
// All FP arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
break;
@@ -1324,6 +1344,7 @@
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
bool isMachoABI = Subtarget.isMachoABI();
+ bool isELF_ABI = Subtarget.isELF_ABI();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
@@ -1399,15 +1420,29 @@
for (unsigned i = 0; i != NumOps; ++i) {
bool inMem = false;
SDOperand Arg = Op.getOperand(5+2*i);
-
+unsigned Flags = castConstantSDNode(Op.getOperand(5+2*i+1))-getValue();
+unsigned AlignFlag = 1 ISD::ParamFlags::OrigAlignmentOffs;
+// See if next argument requires stack alignment in ELF
+unsigned next = 5+2*(i+1)+1;
+bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 NumOps)
+ (castConstantSDNode(Op.getOperand(next))-getValue() AlignFlag)
+ (!(Flags AlignFlag)));
+
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
-SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
+SDOperand PtrOff;
+
+// Stack align in ELF
+if (isELF_ABI Expand !isPPC64)
+ PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
+ StackPtr.getValueType());
+else
+ PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
+
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
// On PPC64, promote integers to
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.260 - 1.261
PPCISelLowering.h updated: 1.61 - 1.62
---
Log message:
More flexible TargetLowering LSR hooks for testing whether an immediate is a
legal target address immediate or scale.
---
Diffs of the changes: (+10 -5)
PPCISelLowering.cpp |5 +++--
PPCISelLowering.h | 10 +++---
2 files changed, 10 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.260
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.261
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.260 Mon Mar 5 18:59:59 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 12 18:29:01 2007
@@ -3152,8 +3152,9 @@
}
/// isLegalAddressImmediate - Return true if the integer value can be used
-/// as the offset of the target addressing mode.
-bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
+/// as the offset of the target addressing mode for load / store of the
+/// given type.
+bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty)
const{
// PPC allows a sign-extended 16-bit immediate field.
return (V -(1 16) V (1 16)-1);
}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.61
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.62
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.61 Thu Mar 1 07:11:38 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Mon Mar 12 18:29:01 2007
@@ -237,9 +237,13 @@
SelectionDAG DAG);
/// isLegalAddressImmediate - Return true if the integer value can be used
-/// as the offset of the target addressing mode.
-virtual bool isLegalAddressImmediate(int64_t V) const;
-virtual bool isLegalAddressImmediate(llvm::GlobalValue*) const;
+/// as the offset of the target addressing mode for load / store of the
+/// given type.
+virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
+
+/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
+/// the offset of the target addressing mode.
+virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG DAG);
};
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.257 - 1.258 PPCISelLowering.h updated: 1.59 - 1.60 PPCInstr64Bit.td updated: 1.40 - 1.41 PPCInstrInfo.td updated: 1.275 - 1.276 --- Log message: Differentiate between the MachO and the ELF ABI the CALL instruction. --- Diffs of the changes: (+12 -12) PPCISelLowering.cpp |5 +++-- PPCISelLowering.h |2 +- PPCInstr64Bit.td|5 ++--- PPCInstrInfo.td | 12 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.257 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.258 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.257 Mon Feb 26 13:44:02 2007 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 27 07:01:19 2007 @@ -326,7 +326,8 @@ case PPCISD::SHL: return PPCISD::SHL; case PPCISD::EXTSW_32: return PPCISD::EXTSW_32; case PPCISD::STD_32:return PPCISD::STD_32; - case PPCISD::CALL: return PPCISD::CALL; + case PPCISD::CALL_ELF: return PPCISD::CALL_ELF; + case PPCISD::CALL_Macho:return PPCISD::CALL_Macho; case PPCISD::MTCTR: return PPCISD::MTCTR; case PPCISD::BCTRL_Macho: return PPCISD::BCTRL_Macho; case PPCISD::BCTRL_ELF: return PPCISD::BCTRL_ELF; @@ -1510,7 +1511,7 @@ NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use. SmallVectorSDOperand, 8 Ops; - unsigned CallOpc = PPCISD::CALL; + unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.59 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.60 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.59 Sat Feb 24 23:34:32 2007 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Feb 27 07:01:19 2007 @@ -82,7 +82,7 @@ STD_32, /// CALL - A direct function call. - CALL, + CALL_Macho, CALL_ELF, /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a /// MTCTR instruction. Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.40 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.41 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.40 Sun Feb 25 13:20:53 2007 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Feb 27 07:01:19 2007 @@ -102,7 +102,7 @@ def BLA8_ELF : IForm18, 1, 1, (ops aaddr:$func, variable_ops), - bla $func, BrB, [/*(PPCcall_ELF (i64 imm:$func))*/]; + bla $func, BrB, [(PPCcall_ELF (i64 imm:$func))]; } @@ -111,12 +111,11 @@ (BL8_Macho tglobaladdr:$dst); def : Pat(PPCcall_Macho (i64 texternalsym:$dst)), (BL8_Macho texternalsym:$dst); -/* + def : Pat(PPCcall_ELF (i64 tglobaladdr:$dst)), (BL8_ELF tglobaladdr:$dst); def : Pat(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst); -*/ //===--===// // 64-bit SPR manipulation instrs. Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.275 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.276 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.275 Mon Feb 26 13:44:02 2007 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Feb 27 07:01:19 2007 @@ -81,9 +81,9 @@ [SDNPHasChain, SDNPOutFlag]; def SDT_PPCCall : SDTypeProfile0, -1, [SDTCisInt0]; -def PPCcall_Macho : SDNodePPCISD::CALL, SDT_PPCCall, +def PPCcall_Macho : SDNodePPCISD::CALL_Macho, SDT_PPCCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]; -def PPCcall_ELF : SDNodePPCISD::CALL, SDT_PPCCall, +def PPCcall_ELF : SDNodePPCISD::CALL_ELF, SDT_PPCCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]; def PPCmtctr : SDNodePPCISD::MTCTR, SDT_PPCCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]; @@ -407,11 +407,11 @@ def BLA_ELF : IForm18, 1, 1, (ops aaddr:$func, variable_ops), bla $func, BrB, - [/*(PPCcall_ELF (i32 imm:$func))*/]; + [(PPCcall_ELF (i32 imm:$func))]; def BCTRL_ELF : XLForm_2_ext19, 528, 20, 0, 1, (ops variable_ops), bctrl, BrB, - [/*(PPCbctrl_ELF)*/]; + [(PPCbctrl_ELF)]; } // DCB* instructions. @@ -1101,10 +1101,10 @@ (BL_Macho tglobaladdr:$dst); def : Pat(PPCcall_Macho (i32 texternalsym:$dst)), (BL_Macho
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.256 - 1.257
PPCInstrInfo.td updated: 1.274 - 1.275
---
Log message:
always lower to RETFLAG, never leave it as just ret.
---
Diffs of the changes: (+7 -11)
PPCISelLowering.cpp | 15 +++
PPCInstrInfo.td |3 ---
2 files changed, 7 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.256
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.257
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.256 Sun Feb 25 14:01:40 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Feb 26 13:44:02 2007
@@ -1626,13 +1626,13 @@
}
static SDOperand LowerRET(SDOperand Op, SelectionDAG DAG) {
- SDOperand Copy;
+ SDOperand Chain = Op.getOperand(0);
switch(Op.getNumOperands()) {
default:
assert(0 Do not know how to return this many arguments!);
abort();
case 1:
-return SDOperand(); // ret void is legal
+return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
@@ -1647,8 +1647,7 @@
ArgReg = PPC::F1;
}
-Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
-SDOperand());
+Chain = DAG.getCopyToReg(Chain, ArgReg, Op.getOperand(1), SDOperand());
// If we haven't noted the R3/F1 are live out, do so now.
if (DAG.getMachineFunction().liveout_empty())
@@ -1656,9 +1655,9 @@
break;
}
case 5:
-Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
-SDOperand());
-Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
+Chain = DAG.getCopyToReg(Chain, PPC::R3, Op.getOperand(3), SDOperand());
+Chain = DAG.getCopyToReg(Chain, PPC::R4, Op.getOperand(1),
+ Chain.getValue(1));
// If we haven't noted the R3+R4 are live out, do so now.
if (DAG.getMachineFunction().liveout_empty()) {
DAG.getMachineFunction().addLiveOut(PPC::R3);
@@ -1666,7 +1665,7 @@
}
break;
}
- return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
+ return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Chain.getValue(1));
}
static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG DAG,
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.274
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.275
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.274 Sun Feb 25 13:20:53 2007
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Feb 26 13:44:02 2007
@@ -1080,9 +1080,6 @@
def : Pat(sub immSExt16:$imm, GPRC:$in),
(SUBFIC GPRC:$in, imm:$imm);
-// Return void support.
-def : Pat(ret), (BLR);
-
// SHL/SRL
def : Pat(shl GPRC:$in, (i32 imm:$imm)),
(RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm));
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.254 - 1.255
---
Log message:
always promote float varargs to double.
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.254
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.255
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.254 Sat Feb 24 23:34:32 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Feb 25 13:59:18 2007
@@ -1423,7 +1423,7 @@
break;
case MVT::f32:
case MVT::f64:
- if (isVarArg isPPC64) {
+ if (isVarArg || isPPC64) {
// Float varargs need to be promoted to double.
if (Arg.getValueType() == MVT::f32)
Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.255 - 1.256
---
Log message:
no really, this is the right patch
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.255
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.256
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.255 Sun Feb 25 13:59:18 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Feb 25 14:01:40 2007
@@ -1423,7 +1423,7 @@
break;
case MVT::f32:
case MVT::f64:
- if (isVarArg || isPPC64) {
+ if (isVarArg) {
// Float varargs need to be promoted to double.
if (Arg.getValueType() == MVT::f32)
Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.252 - 1.253
---
Log message:
Simplify lowering and selection of exception ops.
---
Diffs of the changes: (+15 -34)
PPCISelLowering.cpp | 49 +++--
1 files changed, 15 insertions(+), 34 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.252
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.253
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.252 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Feb 22 08:56:36 2007
@@ -140,14 +140,18 @@
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
-
-
+
// Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- // FIXME - use subtarget debug flags
- if (!TM.getSubtargetPPCSubtarget().isDarwin())
+ if (!TM.getSubtargetPPCSubtarget().isDarwin()) {
setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ } else {
+setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
+setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
+setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
+ }
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
@@ -283,10 +287,15 @@
setShiftAmountType(MVT::i32);
setSetCCResultContents(ZeroOrOneSetCCResult);
- if (TM.getSubtargetPPCSubtarget().isPPC64())
+ if (TM.getSubtargetPPCSubtarget().isPPC64()) {
setStackPointerRegisterToSaveRestore(PPC::X1);
- else
+setExceptionPointerRegister(PPC::X3);
+setExceptionSelectorRegister(PPC::X4);
+ } else {
setStackPointerRegisterToSaveRestore(PPC::R1);
+setExceptionPointerRegister(PPC::R3);
+setExceptionSelectorRegister(PPC::R4);
+ }
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::SINT_TO_FP);
@@ -2610,30 +2619,6 @@
}
}
-/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception
-/// register. The register was made live in the ISel.
-static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG DAG) {
- const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
- getTargetMachine().
- getRegisterInfo();
- MVT::ValueType VT = Op.Val-getValueType(0);
- unsigned Reg = MRI-getEHExceptionRegister();
- SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
- return Result.getValue(Op.ResNo);
-}
-
-/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception
-/// selection register. The register was made live in the ISel.
-static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG DAG) {
- const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
- getTargetMachine().
- getRegisterInfo();
- MVT::ValueType VT = Op.Val-getValueType(0);
- unsigned Reg = MRI-getEHHandlerRegister();
- SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
- return Result.getValue(Op.ResNo);
-}
-
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
@@ -2671,10 +2656,6 @@
// Frame Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
-
- // Exception address and exception selector.
- case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG);
- case ISD::EHSELECTION:return LowerEHSELECTION(Op, DAG);
}
return SDOperand();
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.251 - 1.252
PPCRegisterInfo.cpp updated: 1.108 - 1.109
PPCRegisterInfo.h updated: 1.27 - 1.28
---
Log message:
Support to provide exception and selector registers.
---
Diffs of the changes: (+40 -1)
PPCISelLowering.cpp | 28
PPCRegisterInfo.cpp |9 -
PPCRegisterInfo.h |4
3 files changed, 40 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.251
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.252
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.251 Sat Feb 17 00:57:26 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 21 16:54:50 2007
@@ -2610,6 +2610,30 @@
}
}
+/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception
+/// register. The register was made live in the ISel.
+static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG DAG) {
+ const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+ getTargetMachine().
+ getRegisterInfo();
+ MVT::ValueType VT = Op.Val-getValueType(0);
+ unsigned Reg = MRI-getEHExceptionRegister();
+ SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
+ return Result.getValue(Op.ResNo);
+}
+
+/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception
+/// selection register. The register was made live in the ISel.
+static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG DAG) {
+ const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+ getTargetMachine().
+ getRegisterInfo();
+ MVT::ValueType VT = Op.Val-getValueType(0);
+ unsigned Reg = MRI-getEHHandlerRegister();
+ SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
+ return Result.getValue(Op.ResNo);
+}
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
@@ -2647,6 +2671,10 @@
// Frame Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+
+ // Exception address and exception selector.
+ case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG);
+ case ISD::EHSELECTION:return LowerEHSELECTION(Op, DAG);
}
return SDOperand();
}
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.108
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.109
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.108 Mon Feb 19 15:49:54 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Feb 21 16:54:50 2007
@@ -1022,7 +1022,6 @@
unsigned PPCRegisterInfo::getRARegister() const {
return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
-
}
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction MF) const {
@@ -1040,5 +1039,13 @@
Moves.push_back(MachineMove(0, Dst, Src));
}
+unsigned PPCRegisterInfo::getEHExceptionRegister() const {
+ return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
+}
+
+unsigned PPCRegisterInfo::getEHHandlerRegister() const {
+ return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
+}
+
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.27
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.28
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.27 Mon Feb 19 15:49:54 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Wed Feb 21 16:54:50 2007
@@ -89,6 +89,10 @@
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction MF) const;
void getInitialFrameState(std::vectorMachineMove Moves) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm
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Re: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCRegisterInfo.cpp PPCRegisterInfo.h
Support to provide exception and selector registers.
Hey Jim,
This behavior:
+/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from
the exception
+/// register. The register was made live in the ISel.
+static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG
DAG) {
+ const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+ getTargetMachine().
+ getRegisterInfo();
+ MVT::ValueType VT = Op.Val-getValueType(0);
+ unsigned Reg = MRI-getEHExceptionRegister();
+ SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
+ return Result.getValue(Op.ResNo);
+}
Is almost certainly guaranteed to work for other targets as well (not
just PPC). Can you change this code so that Legalize has this code,
and invokes it when the target requests that EXCEPTIONADDR be
expanded?
Right now, all non-ppc targets abort when this happens, which isn't
very nice. Please just have them lower to returning something stupid
but that will compile correctly (like return a constant zero) if MRI-
getEHExceptionRegister() returns 0.
With these changes, you should be able to remove the code you added
to each target.
-Chris
+
+/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the
exception
+/// selection register. The register was made live in the ISel.
+static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG DAG) {
+ const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+ getTargetMachine().
+ getRegisterInfo();
+ MVT::ValueType VT = Op.Val-getValueType(0);
+ unsigned Reg = MRI-getEHHandlerRegister();
+ SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
+ return Result.getValue(Op.ResNo);
+}
+
/// LowerOperation - Provide custom lowering hooks for some
operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op,
SelectionDAG DAG) {
@@ -2647,6 +2671,10 @@
// Frame Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+
+ // Exception address and exception selector.
+ case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG);
+ case ISD::EHSELECTION:return LowerEHSELECTION(Op, DAG);
}
return SDOperand();
}
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.108 llvm/lib/
Target/PowerPC/PPCRegisterInfo.cpp:1.109
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.108 Mon Feb 19
15:49:54 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Feb 21 16:54:50
2007
@@ -1022,7 +1022,6 @@
unsigned PPCRegisterInfo::getRARegister() const {
return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
-
}
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction MF)
const {
@@ -1040,5 +1039,13 @@
Moves.push_back(MachineMove(0, Dst, Src));
}
+unsigned PPCRegisterInfo::getEHExceptionRegister() const {
+ return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
+}
+
+unsigned PPCRegisterInfo::getEHHandlerRegister() const {
+ return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
+}
+
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.27 llvm/lib/
Target/PowerPC/PPCRegisterInfo.h:1.28
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.27Mon Feb 19
15:49:54 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Wed Feb 21 16:54:50 2007
@@ -89,6 +89,10 @@
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction MF) const;
void getInitialFrameState(std::vectorMachineMove Moves) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.249 - 1.250
---
Log message:
Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
_test:
lis r2, 743
li r3, 0
stw r3, 32751(r2)
blr
instead of:
_test:
li r2, 0
stw r2, 32751(48693248)
blr
Implement support for ppc64 as well, allowing it to produce better code.
---
Diffs of the changes: (+9 -5)
PPCISelLowering.cpp | 14 +-
1 files changed, 9 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.249
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.250
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.249 Mon Jan 29 16:58:52 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Feb 17 00:44:03 2007
@@ -743,14 +743,18 @@
Base = DAG.getRegister(PPC::R0, CN-getValueType(0));
return true;
}
-
-// FIXME: Handle small sext constant offsets in PPC64 mode also!
-if (CN-getValueType(0) == MVT::i32) {
+
+// Handle 32-bit sext immediates with LIS + addr mode.
+if (CN-getValueType(0) == MVT::i32 ||
+(int64_t)CN-getValue() == (int)CN-getValue()) {
int Addr = (int)CN-getValue();
// Otherwise, break this down into an LIS + disp.
- Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
- Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
+ Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
+
+ Base = DAG.getTargetConstant((Addr - (signed short)Addr) 16,
MVT::i32);
+ unsigned Opc = CN-getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
+ Base = SDOperand(DAG.getTargetNode(Opc, CN-getValueType(0), Base), 0);
return true;
}
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.250 - 1.251
---
Log message:
Fix ixaddrs as well, allowing ppc64 to compile to:
_test2:
li r2, 0
lis r3, 1
std r2, 9024(r3)
blr
instead of:
_test2:
lis r2, 1
li r3, 0
ori r2, r2, 9024
std r3, 0(r2)
blr
This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2
---
Diffs of the changes: (+24 -19)
PPCISelLowering.cpp | 43 ---
1 files changed, 24 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.250
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.251
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.250 Sat Feb 17 00:44:03 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Feb 17 00:57:26 2007
@@ -841,25 +841,30 @@
}
}
} else if (ConstantSDNode *CN = dyn_castConstantSDNode(N)) {
-// Loading from a constant address.
-
-// If this address fits entirely in a 14-bit sext immediate field, codegen
-// this as d, 0
-short Imm;
-if (isIntS16Immediate(CN, Imm)) {
- Disp = DAG.getTargetConstant((unsigned short)Imm 2, getPointerTy());
- Base = DAG.getRegister(PPC::R0, CN-getValueType(0));
- return true;
-}
-
-// FIXME: Handle small sext constant offsets in PPC64 mode also!
-if (CN-getValueType(0) == MVT::i32) {
- int Addr = (int)CN-getValue();
-
- // Otherwise, break this down into an LIS + disp.
- Disp = DAG.getTargetConstant((short)Addr 2, MVT::i32);
- Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
- return true;
+// Loading from a constant address. Verify low two bits are clear.
+if ((CN-getValue() 3) == 0) {
+ // If this address fits entirely in a 14-bit sext immediate field,
codegen
+ // this as d, 0
+ short Imm;
+ if (isIntS16Immediate(CN, Imm)) {
+Disp = DAG.getTargetConstant((unsigned short)Imm 2, getPointerTy());
+Base = DAG.getRegister(PPC::R0, CN-getValueType(0));
+return true;
+ }
+
+ // Fold the low-part of 32-bit absolute addresses into addr mode.
+ if (CN-getValueType(0) == MVT::i32 ||
+ (int64_t)CN-getValue() == (int)CN-getValue()) {
+int Addr = (int)CN-getValue();
+
+// Otherwise, break this down into an LIS + disp.
+Disp = DAG.getTargetConstant((short)Addr 2, MVT::i32);
+
+Base = DAG.getTargetConstant((Addr-(signed short)Addr) 16,
MVT::i32);
+unsigned Opc = CN-getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
+Base = SDOperand(DAG.getTargetNode(Opc, CN-getValueType(0), Base), 0);
+return true;
+ }
}
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.248 - 1.249 --- Log message: Finish off bug 680: http://llvm.org/PR680 , allowing targets to custom lower frame and return address nodes. --- Diffs of the changes: (+4 -0) PPCISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.248 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.249 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.248 Sun Jan 28 07:31:35 2007 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jan 29 16:58:52 2007 @@ -2634,6 +2634,10 @@ case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); case ISD::MUL:return LowerMUL(Op, DAG); + + // Frame Return address. Currently unimplemented + case ISD::RETURNADDR: break; + case ISD::FRAMEADDR: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.247 - 1.248
---
Log message:
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning place this
parameter in registers, if possible. This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret = sret.
Before this, there will be some unexpected test fails.
---
Diffs of the changes: (+3 -3)
PPCISelLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.247
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.248
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.247 Fri Jan 26 08:34:51 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jan 28 07:31:35 2007
@@ -1360,9 +1360,9 @@
// On PPC64, promote integers to 64-bit values.
if (isPPC64 Arg.getValueType() == MVT::i32) {
- unsigned ExtOp = ISD::ZERO_EXTEND;
- if (castConstantSDNode(Op.getOperand(5+2*i+1))-getValue())
-ExtOp = ISD::SIGN_EXTEND;
+ unsigned Flags =
castConstantSDNode(Op.getOperand(5+2*i+1))-getValue();
+ unsigned ExtOp = (Flags 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+
Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.245 - 1.246
---
Log message:
setSetCCIsExpensive is gone.
---
Diffs of the changes: (+0 -2)
PPCISelLowering.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.245
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.246
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.245 Fri Dec 15 08:32:57 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jan 5 17:42:53 2007
@@ -36,8 +36,6 @@
PPCTargetLowering::PPCTargetLowering(PPCTargetMachine TM)
: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
- // Fold away setcc operations if possible.
- setSetCCIsExpensive();
setPow2DivIsCheap();
// Use _setjmp/_longjmp instead of setjmp/longjmp.
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.244 - 1.245
---
Log message:
Provide support for FP_TO_UINT.
---
Diffs of the changes: (+3 -1)
PPCISelLowering.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.244
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.245
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.244 Mon Dec 11 17:22:45 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 15 08:32:57 2006
@@ -181,9 +181,11 @@
if (TM.getSubtargetPPCSubtarget().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
-
+setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+
// FIXME: disable this lowered code. This generates 64-bit register
values,
// and we don't model the fact that the top part is clobbered by calls. We
// need to flag these together so that the value isn't live across a call.
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Re: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Should read Provide ppc64 support for FP_TO_UINT On 15-Dec-06, at 10:33 AM, Jim Laskey wrote: Provide support for FP_TO_UINT. smime.p7s Description: S/MIME cryptographic signature ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.242 - 1.243 --- Log message: Missing opcode. --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.242 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.243 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.242 Sun Dec 10 17:12:42 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Dec 11 12:45:56 2006 @@ -310,6 +310,7 @@ case PPCISD::VPERM: return PPCISD::VPERM; case PPCISD::Hi:return PPCISD::Hi; case PPCISD::Lo:return PPCISD::Lo; + case PPCISD::DYNALLOC: return PPCISD::DYNALLOC; case PPCISD::GlobalBaseReg: return PPCISD::GlobalBaseReg; case PPCISD::SRL: return PPCISD::SRL; case PPCISD::SRA: return PPCISD::SRA; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.240 - 1.241 --- Log message: Fix i64 uint_to_fp on ppc64 --- Diffs of the changes: (+2 -1) PPCISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.240 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.241 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.240 Mon Dec 4 16:04:42 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Dec 6 19:24:16 2006 @@ -181,7 +181,8 @@ // They also have instructions for converting between i64 and fp. setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); - +setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + // FIXME: disable this lowered code. This generates 64-bit register values, // and we don't model the fact that the top part is clobbered by calls. We // need to flag these together so that the value isn't live across a call. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.239 - 1.240
---
Log message:
Restoration of the stack pointer after a deallocation of a alloca was not
updating the SP link.
---
Diffs of the changes: (+28 -1)
PPCISelLowering.cpp | 29 -
1 files changed, 28 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.239
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.240
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.239 Fri Dec 1 10:30:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Dec 4 16:04:42 2006
@@ -170,7 +170,7 @@
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
@@ -1606,6 +1606,32 @@
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
+static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG DAG,
+ const PPCSubtarget Subtarget) {
+ // When we pop the dynamic allocation we need to restore the SP link.
+
+ // Get the corect type for pointers.
+ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+
+ // Construct the stack pointer operand.
+ bool IsPPC64 = Subtarget.isPPC64();
+ unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
+ SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
+
+ // Get the operands for the STACKRESTORE.
+ SDOperand Chain = Op.getOperand(0);
+ SDOperand SaveSP = Op.getOperand(1);
+
+ // Load the old link SP.
+ SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
+
+ // Restore the stack pointer.
+ Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
+
+ // Store the old link SP.
+ return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
+}
+
static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG DAG,
const PPCSubtarget Subtarget) {
MachineFunction MF = DAG.getMachineFunction();
@@ -2587,6 +2613,7 @@
return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
case ISD::CALL: return LowerCALL(Op, DAG);
case ISD::RET:return LowerRET(Op, DAG);
+ case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG,
PPCSubTarget);
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
PPCSubTarget);
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.238 - 1.239
---
Log message:
1. In ppc64 mode we need only use one GPR.
2. Float values need to be promoted to double when they are vararg.
---
Diffs of the changes: (+7 -1)
PPCISelLowering.cpp |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.238
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.239
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.238 Thu Nov 30 19:45:39 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 1 10:30:47 2006
@@ -1377,6 +1377,12 @@
break;
case MVT::f32:
case MVT::f64:
+ if (isVarArg isPPC64) {
+// Float varargs need to be promoted to double.
+if (Arg.getValueType() == MVT::f32)
+ Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
+ }
+
if (FPR_idx != NumFPRs) {
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
@@ -1390,7 +1396,7 @@
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
- if (GPR_idx != NumGPRs Arg.getValueType() == MVT::f64) {
+ if (GPR_idx != NumGPRs Arg.getValueType() == MVT::f64
!isPPC64){
SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.237 - 1.238
---
Log message:
Fix the CodeGen/PowerPC/vec_constants.ll regression.
---
Diffs of the changes: (+9 -6)
PPCISelLowering.cpp | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.237
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.238
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.237 Wed Nov 29 13:58:49 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 30 19:45:39 2006
@@ -1958,13 +1958,17 @@
static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
SelectionDAG DAG) {
assert(Val = -16 Val = 15 vsplti is out of range!);
-
- // Force vspltis[hw] -1 to vspltisb -1.
- if (Val == -1) SplatSize = 1;
-
+
static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
};
+
+ MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
+
+ // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
+ if (Val == -1)
+SplatSize = 1;
+
MVT::ValueType CanonicalVT = VTys[SplatSize-1];
// Build a canonical splat for this value.
@@ -1973,8 +1977,7 @@
Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
Ops[0], Ops.size());
- if (VT == MVT::Other) return Res;
- return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
+ return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
}
/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.235 - 1.236
---
Log message:
Offset for load of 32-bit arg in 64-bit world was incorrect.
---
Diffs of the changes: (+4 -1)
PPCISelLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.235
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.236
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.235 Tue Nov 28 12:27:02 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 29 07:37:09 2006
@@ -1123,6 +1123,7 @@
bool needsLoad = false;
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
+unsigned ArgSize = ObjSize;
unsigned CurArgOffset = ArgOffset;
switch (ObjectVT) {
@@ -1138,6 +1139,7 @@
++GPR_idx;
} else {
needsLoad = true;
+ArgSize = PtrByteSize;
}
break;
case MVT::i64: // PPC64
@@ -1203,7 +1205,8 @@
// If the argument is actually used, emit a load from the right stack
// slot.
if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
-int FI = MFI-CreateFixedObject(ObjSize, CurArgOffset);
+int FI = MFI-CreateFixedObject(ObjSize,
+CurArgOffset + (ArgSize - ObjSize));
SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
} else {
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.236 - 1.237
---
Log message:
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
---
Diffs of the changes: (+22 -14)
PPCISelLowering.cpp | 36 ++--
1 files changed, 22 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.236
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.237
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.236 Wed Nov 29 07:37:09 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 29 13:58:49 2006
@@ -1973,6 +1973,7 @@
Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
Ops[0], Ops.size());
+ if (VT == MVT::Other) return Res;
return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
}
@@ -2086,6 +2087,7 @@
-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
};
+
for (unsigned idx = 0; idx sizeof(SplatCsts)/sizeof(SplatCsts[0]);
++idx){
// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
// cases which are ambiguous (e.g. formation of 0x8000_). 'vsplti
-1'
@@ -2097,43 +2099,47 @@
// vsplti + shl self.
if (SextVal == (i (int)TypeShiftAmt)) {
-Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
+SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
Intrinsic::ppc_altivec_vslw
};
-return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
+Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
+return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
}
// vsplti + srl self.
if (SextVal == (int)((unsigned)i TypeShiftAmt)) {
-Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
+SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
Intrinsic::ppc_altivec_vsrw
};
-return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
+Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
+return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
}
// vsplti + sra self.
if (SextVal == (int)((unsigned)i TypeShiftAmt)) {
-Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
+SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
Intrinsic::ppc_altivec_vsraw
};
-return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
+Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
+return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
}
// vsplti + rol self.
if (SextVal == (int)(((unsigned)i TypeShiftAmt) |
((unsigned)i (SplatBitSize-TypeShiftAmt {
-Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
+SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
Intrinsic::ppc_altivec_vrlw
};
-return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
+Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
+return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
}
// t = vsplti c, result = vsldoi t, t, 1
@@ -2157,15 +2163,17 @@
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
if (SextVal = 0 SextVal = 31) {
- SDOperand LHS = BuildSplatI(SextVal-16, SplatSize,
Op.getValueType(),DAG);
- SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
- return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
+ SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
+ SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
+ LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
+ return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
}
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
if (SextVal = -31 SextVal = 0) {
- SDOperand LHS = BuildSplatI(SextVal+16, SplatSize,
Op.getValueType(),DAG);
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.233 - 1.234
---
Log message:
32-bit int space was not accounted for properly in lowerCall.
---
Diffs of the changes: (+8 -3)
PPCISelLowering.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.233
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.234
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.233 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Nov 28 08:53:52 2006
@@ -1086,6 +1086,7 @@
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
+ unsigned PtrByteSize = isPPC64 ? 8 : 4;
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64);
@@ -1128,7 +1129,7 @@
default: assert(0 Unhandled argument type!);
case MVT::i32:
// All int arguments reserve stack space.
- ArgOffset += isPPC64 ? 8 : 4;
+ ArgOffset += PtrByteSize;
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
@@ -1266,6 +1267,7 @@
return DAG.getConstant((int)C-getValue() 2, MVT::i32).Val;
}
+#include iostream
static SDOperand LowerCALL(SDOperand Op, SelectionDAG DAG) {
SDOperand Chain = Op.getOperand(0);
@@ -1287,8 +1289,11 @@
unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64);
// Add up all the space actually used.
- for (unsigned i = 0; i != NumOps; ++i)
-NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
+ for (unsigned i = 0; i != NumOps; ++i) {
+unsigned ArgSize
=MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
+ArgSize = std::max(ArgSize, PtrByteSize);
+NumBytes += ArgSize;
+ }
// The prolog code of the callee may store up to 8 GPR argument registers to
// the stack, allowing va_start to index over them in memory if its varargs.
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.234 - 1.235
---
Log message:
Remove debug code.
---
Diffs of the changes: (+0 -2)
PPCISelLowering.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.234
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.235
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.234 Tue Nov 28 08:53:52 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Nov 28 12:27:02 2006
@@ -1267,8 +1267,6 @@
return DAG.getConstant((int)C-getValue() 2, MVT::i32).Val;
}
-#include iostream
-
static SDOperand LowerCALL(SDOperand Op, SelectionDAG DAG) {
SDOperand Chain = Op.getOperand(0);
bool isVarArg = castConstantSDNode(Op.getOperand(2))-getValue() !=
0;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.231 - 1.232
---
Log message:
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
Also, valist should create a pointer RC reg class value, not a GPRC value.
---
Diffs of the changes: (+8 -3)
PPCISelLowering.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.231
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.232
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.231 Fri Nov 17 16:37:34 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 17 19:57:19 2006
@@ -1155,13 +1155,13 @@
case MVT::f32:
case MVT::f64:
// All FP arguments reserve stack space.
- ArgOffset += ObjSize;
+ ArgOffset += isPPC64 ? 8 : ObjSize;
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_idx != Num_GPR_Regs) {
++GPR_idx;
-if (ObjSize == 8 GPR_idx != Num_GPR_Regs)
+if (ObjSize == 8 GPR_idx != Num_GPR_Regs !isPPC64)
++GPR_idx;
}
if (FPR_idx != Num_FPR_Regs) {
@@ -1226,7 +1226,12 @@
// result of va_next.
SmallVectorSDOperand, 8 MemOps;
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
- unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
+ unsigned VReg;
+ if (isPPC64)
+VReg = RegMap-createVirtualRegister(PPC::G8RCRegClass);
+ else
+VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
+
MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.224 - 1.225
---
Log message:
minor tweaks, reject vector preinc.
---
Diffs of the changes: (+9 -4)
PPCISelLowering.cpp | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.224
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.225
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.224 Fri Nov 10 18:08:42 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Nov 13 19:38:31 2006
@@ -874,17 +874,22 @@
if (!EnablePPCPreinc) return false;
SDOperand Ptr;
+ MVT::ValueType VT;
if (LoadSDNode *LD = dyn_castLoadSDNode(N)) {
Ptr = LD-getBasePtr();
+VT = LD-getValueType(0);
} else if (StoreSDNode *ST = dyn_castStoreSDNode(N)) {
ST = ST;
-//Ptr = ST-getBasePtr();
-//VT = ST-getStoredVT();
-// TODO: handle stores.
-return false;
+Ptr = ST-getBasePtr();
+VT = ST-getStoredVT();
+return false; // TODO: Stores.
} else
return false;
+ // PowerPC doesn't have preinc load/store instructions for vectors.
+ if (MVT::isVector(VT))
+return false;
+
// TODO: Handle reg+reg.
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
return false;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.225 - 1.226
---
Log message:
lower X = seteq Y, Z to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a-code == b-code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
---
Diffs of the changes: (+5 -3)
PPCISelLowering.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.225
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.226
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.225 Mon Nov 13 19:38:31 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Nov 13 23:28:08 2006
@@ -1038,12 +1038,14 @@
}
// If we have an integer seteq/setne, turn it into a compare against zero
- // by subtracting the rhs from the lhs, which is faster than setting a
- // condition register, reading it back out, and masking the correct bit.
+ // by xor'ing the rhs with the lhs, which is faster than setting a
+ // condition register, reading it back out, and masking the correct bit. The
+ // normal approach here uses sub to do this instead of xor. Using xor
exposes
+ // the result to other bit-twiddling opportunities.
MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
if (MVT::isInteger(LHSVT) (CC == ISD::SETEQ || CC == ISD::SETNE)) {
MVT::ValueType VT = Op.getValueType();
-SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
+SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
Op.getOperand(1));
return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.223 - 1.224
---
Log message:
ppc64 doesn't have lwau, don't attempt to form it.
---
Diffs of the changes: (+9 -3)
PPCISelLowering.cpp | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.223
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.224
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.223 Fri Nov 10 17:58:44 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 10 18:08:42 2006
@@ -876,9 +876,6 @@
SDOperand Ptr;
if (LoadSDNode *LD = dyn_castLoadSDNode(N)) {
Ptr = LD-getBasePtr();
-
-// FIXME: PPC has no LWAU!
-
} else if (StoreSDNode *ST = dyn_castStoreSDNode(N)) {
ST = ST;
//Ptr = ST-getBasePtr();
@@ -891,6 +888,15 @@
// TODO: Handle reg+reg.
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
return false;
+
+ // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
+ // sext i32 to i64 when addr mode is r+i.
+ if (LoadSDNode *LD = dyn_castLoadSDNode(N)) {
+if (LD-getValueType(0) == MVT::i64 LD-getLoadedVT() == MVT::i32
+LD-getExtensionType() == ISD::SEXTLOAD
+isaConstantSDNode(Offset))
+ return false;
+ }
AM = ISD::PRE_INC;
return true;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.219 - 1.220
PPCISelLowering.h updated: 1.55 - 1.56
---
Log message:
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
---
Diffs of the changes: (+2 -2)
PPCISelLowering.cpp |2 +-
PPCISelLowering.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.219
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.220
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.219 Tue Nov 7 20:15:41 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 9 11:55:04 2006
@@ -853,7 +853,7 @@
/// can be legally represented as pre-indexed load / store address.
bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand Base,
SDOperand Offset,
- ISD::MemOpAddrMode AM,
+ ISD::MemIndexedMode AM,
SelectionDAG DAG) {
return false;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.55
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.56
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.55 Tue Nov 7 20:15:41 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Nov 9 11:55:04 2006
@@ -182,7 +182,7 @@
/// can be legally represented as pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand Base,
SDOperand Offset,
- ISD::MemOpAddrMode AM,
+ ISD::MemIndexedMode AM,
SelectionDAG DAG);
/// SelectAddressRegReg - Given the specified addressed, check to see if it
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.220 - 1.221 --- Log message: PPC supports i32 / i64 pre-inc load / store. --- Diffs of the changes: (+6 -0) PPCISelLowering.cpp |6 ++ 1 files changed, 6 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.220 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.221 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.220 Thu Nov 9 11:55:04 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 9 13:11:50 2006 @@ -50,6 +50,12 @@ // PowerPC does not have truncstore for i1. setStoreXAction(MVT::i1, Promote); + // PowerPC has i32 and i64 pre-inc load and store's. + setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); + setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); + setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); + setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); + setOperationAction(ISD::ConstantFP, MVT::f64, Expand); setOperationAction(ISD::ConstantFP, MVT::f32, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.216 - 1.217
PPCISelLowering.h updated: 1.53 - 1.54
---
Log message:
Implement the getRegForInlineAsmConstraint method for PPC. With recent
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm(foo %0, %1 : =r(X): r(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
---
Diffs of the changes: (+29 -56)
PPCISelLowering.cpp | 75 +++-
PPCISelLowering.h | 10 --
2 files changed, 29 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.216
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.217
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.216 Tue Oct 31 13:40:43 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 1 19:44:04 2006
@@ -28,8 +28,8 @@
#include llvm/Target/TargetOptions.h
using namespace llvm;
-PPCTargetLowering::PPCTargetLowering(TargetMachine TM)
- : TargetLowering(TM) {
+PPCTargetLowering::PPCTargetLowering(PPCTargetMachine TM)
+ : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
// Fold away setcc operations if possible.
setSetCCIsExpensive();
@@ -2600,63 +2600,34 @@
return TargetLowering::getConstraintType(ConstraintLetter);
}
-
-std::vectorunsigned PPCTargetLowering::
-getRegClassForInlineAsmConstraint(const std::string Constraint,
- MVT::ValueType VT) const {
+std::pairunsigned, const TargetRegisterClass*
+PPCTargetLowering::getRegForInlineAsmConstraint(const std::string Constraint,
+MVT::ValueType VT) const {
if (Constraint.size() == 1) {
-switch (Constraint[0]) { // GCC RS6000 Constraint Letters
-default: break; // Unknown constriant letter
-case 'b':
- return make_vectorunsigned(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
- PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
- PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31,
- 0);
-case 'r':
- return make_vectorunsigned(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
- PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
- PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31,
- 0);
-case 'f':
- return make_vectorunsigned(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
- PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
- PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31,
- 0);
+// GCC RS6000 Constraint Letters
+switch (Constraint[0]) {
+case 'b': // R1-R31
+case 'r': // R0-R31
+ if (VT == MVT::i64 PPCSubTarget.isPPC64())
+return std::make_pair(0U, PPC::G8RCRegisterClass);
+ return std::make_pair(0U, PPC::GPRCRegisterClass);
+case 'f':
+ if (VT == MVT::f32)
+return std::make_pair(0U, PPC::F4RCRegisterClass);
+ else if (VT == MVT::f64)
+return std::make_pair(0U, PPC::F8RCRegisterClass);
+ break;
case 'v':
- return make_vectorunsigned(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
- PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
- PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
- PPC::V12, PPC::V13, PPC::V14, PPC::V15,
- PPC::V16, PPC::V17,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.215 - 1.216
PPCISelLowering.h updated: 1.52 - 1.53
---
Log message:
Change the prototype for TargetLowering::isOperandValidForConstraint
---
Diffs of the changes: (+20 -12)
PPCISelLowering.cpp | 29 ++---
PPCISelLowering.h |3 ++-
2 files changed, 20 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.215
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.216
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.215 Mon Oct 30 02:02:39 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Oct 31 13:40:43 2006
@@ -2658,8 +2658,8 @@
}
// isOperandValidForConstraint
-bool PPCTargetLowering::
-isOperandValidForConstraint(SDOperand Op, char Letter) {
+SDOperand PPCTargetLowering::
+isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG DAG) {
switch (Letter) {
default: break;
case 'I':
@@ -2670,32 +2670,39 @@
case 'N':
case 'O':
case 'P': {
-if (!isaConstantSDNode(Op)) return false; // Must be an immediate.
+if (!isaConstantSDNode(Op)) return SDOperand(0,0);// Must be an
immediate.
unsigned Value = castConstantSDNode(Op)-getValue();
switch (Letter) {
default: assert(0 Unknown constraint letter!);
case 'I': // I is a signed 16-bit constant.
- return (short)Value == (int)Value;
+ if ((short)Value == (int)Value) return Op;
+ break;
case 'J': // J is a constant with only the high-order 16 bits nonzero.
case 'L': // L is a signed 16-bit constant shifted left 16 bits.
- return (short)Value == 0;
+ if ((short)Value == 0) return Op;
+ break;
case 'K': // K is a constant with only the low-order 16 bits nonzero.
- return (Value 16) == 0;
+ if ((Value 16) == 0) return Op;
+ break;
case 'M': // M is a constant that is greater than 31.
- return Value 31;
+ if (Value 31) return Op;
+ break;
case 'N': // N is a positive constant that is an exact power of two.
- return (int)Value 0 isPowerOf2_32(Value);
+ if ((int)Value 0 isPowerOf2_32(Value)) return Op;
+ break;
case 'O': // O is the constant zero.
- return Value == 0;
+ if (Value == 0) return Op;
+ break;
case 'P': // P is a constant whose negation is a signed 16-bit constant.
- return (short)-Value == (int)-Value;
+ if ((short)-Value == (int)-Value) return Op;
+ break;
}
break;
}
}
// Handle standard constraint letters.
- return TargetLowering::isOperandValidForConstraint(Op, Letter);
+ return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
}
/// isLegalAddressImmediate - Return true if the integer value can be used
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.52
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.53
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.52 Sun Aug 27 20:02:49 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Oct 31 13:40:43 2006
@@ -194,7 +194,8 @@
std::vectorunsigned
getRegClassForInlineAsmConstraint(const std::string Constraint,
MVT::ValueType VT) const;
-bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
+SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
+ SelectionDAG DAG);
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.214 - 1.215 --- Log message: All targets expand BR_JT for now. --- Diffs of the changes: (+2 -0) PPCISelLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.214 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.215 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.214 Tue Oct 17 20:20:43 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Oct 30 02:02:39 2006 @@ -107,6 +107,8 @@ // PowerPC does not have BRCOND which requires SetCC setOperationAction(ISD::BRCOND, MVT::Other, Expand); + + setOperationAction(ISD::BR_JT, MVT::Other, Expand); // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.212 - 1.213 --- Log message: Expand alloca for ppc64 --- Diffs of the changes: (+2 -1) PPCISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.212 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.213 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.212 Fri Oct 13 16:14:26 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Oct 17 20:18:48 2006 @@ -153,7 +153,8 @@ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); - + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand); + // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.211 - 1.212
PPCInstr64Bit.td updated: 1.21 - 1.22
PPCInstrInfo.td updated: 1.247 - 1.248
---
Log message:
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
---
Diffs of the changes: (+21 -23)
PPCISelLowering.cpp | 24 +++-
PPCInstr64Bit.td| 12 ++--
PPCInstrInfo.td |8
3 files changed, 21 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.211
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.212
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.211 Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Oct 13 16:14:26 2006
@@ -47,6 +47,9 @@
setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ // PowerPC does not have truncstore for i1.
+ setStoreXAction(MVT::i1, Promote);
+
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
@@ -117,9 +120,6 @@
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
- // PowerPC does not have truncstore for i1.
- setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
-
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
@@ -743,7 +743,9 @@
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1),
Op.getOperand(2));
+ SrcValueSDNode *SV = castSrcValueSDNode(Op.getOperand(2));
+ return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV-getValue(),
+ SV-getOffset());
}
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG DAG,
@@ -898,8 +900,7 @@
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
- DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
@@ -1033,8 +1034,7 @@
if (GPR_idx != NumGPRs) {
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
} else {
-MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
ArgOffset += PtrByteSize;
break;
@@ -1044,8 +1044,7 @@
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
if (isVarArg) {
- SDOperand Store = DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
// Float varargs are always shadowed in available integer registers
@@ -1071,8 +1070,7 @@
++GPR_idx;
}
} else {
-MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
- DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
if (isPPC64)
ArgOffset += 8;
@@ -2119,7 +2117,7 @@
// Store the input value into Value#0 of the stack slot.
SDOperand Store = DAG.getStore(DAG.getEntryNode(),
- Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
+ Op.getOperand(0), FIdx, NULL, 0);
// Load it out.
return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.21
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.22
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.21 Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Oct 13 16:14:26 2006
@@ -304,24 +304,24 @@
// Truncating stores.
def STB8 : DForm_338, (ops G8RC:$rS, memri:$src),
stb $rS, $src, LdStGeneral,
- [(truncstore G8RC:$rS, iaddr:$src, i8)];
+ [(truncstorei8 G8RC:$rS, iaddr:$src)];
def STH8 : DForm_344, (ops G8RC:$rS, memri:$src),
sth $rS, $src, LdStGeneral,
- [(truncstore G8RC:$rS, iaddr:$src, i16)];
+ [(truncstorei16 G8RC:$rS, iaddr:$src)];
def STW8 : DForm_336, (ops G8RC:$rS,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.210 - 1.211
PPCInstr64Bit.td updated: 1.20 - 1.21
PPCInstrInfo.td updated: 1.243 - 1.244
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+49 -50)
PPCISelLowering.cpp | 27 +--
PPCInstr64Bit.td| 40
PPCInstrInfo.td | 32
3 files changed, 49 insertions(+), 50 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.210
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.211
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.210 Thu Oct 5 18:00:19 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Oct 9 15:57:25 2006
@@ -311,7 +311,7 @@
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_castConstantFPSDNode(Op))
return CFP-isExactlyValue(-0.0) || CFP-isExactlyValue(0.0);
- else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) {
+ else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_castConstantPoolSDNode(Op.getOperand(1)))
if (ConstantFP *CFP = dyn_castConstantFP(CP-getConstVal()))
@@ -694,7 +694,7 @@
// If the global is weak or external, we have to go through the lazy
// resolution stub.
- return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
+ return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
}
static SDOperand LowerSETCC(SDOperand Op, SelectionDAG DAG) {
@@ -873,8 +873,7 @@
if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
int FI = MFI-CreateFixedObject(ObjSize, CurArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
-ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
- DAG.getSrcValue(NULL));
+ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
} else {
// Don't emit a dead load.
ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
@@ -1051,16 +1050,14 @@
// Float varargs are always shadowed in available integer registers
if (GPR_idx != NumGPRs) {
-SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
- DAG.getSrcValue(NULL));
+SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
if (GPR_idx != NumGPRs Arg.getValueType() == MVT::f64) {
SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
-SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
- DAG.getSrcValue(NULL));
+SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
@@ -1401,7 +1398,7 @@
DAG.getEntryNode(), Ext64, FIdx,
DAG.getSrcValue(NULL));
// Load the value as a double.
- SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
+ SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
// FCFID it and return it.
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
@@ -2124,7 +2121,7 @@
SDOperand Store = DAG.getStore(DAG.getEntryNode(),
Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
// Load it out.
- return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
+ return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
}
static SDOperand LowerMUL(SDOperand Op, SelectionDAG DAG) {
@@ -2383,18 +2380,20 @@
break;
case ISD::BSWAP:
// Turn BSWAP (LOAD) - lhbrx/lwbrx.
-if (N-getOperand(0).getOpcode() == ISD::LOAD
+if (ISD::isNON_EXTLoad(N-getOperand(0).Val)
N-getOperand(0).hasOneUse()
(N-getValueType(0) == MVT::i32 || N-getValueType(0) == MVT::i16)) {
SDOperand Load = N-getOperand(0);
+ LoadSDNode *LD = castLoadSDNode(Load);
// Create the byte-swapping load.
std::vectorMVT::ValueType VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Other);
+ SDOperand SV = DAG.getSrcValue(LD-getSrcValue(),
LD-getSrcValueOffset());
SDOperand Ops[] = {
-Load.getOperand(0), // Chain
-Load.getOperand(1), // Ptr
-Load.getOperand(2), // SrcValue
+LD-getChain(),// Chain
+LD-getBasePtr(), // Ptr
+SV,// SrcValue
DAG.getValueType(N-getValueType(0)) // VT
};
SDOperand BSLoad =
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.209 - 1.210
---
Log message:
Make use of getStore().
---
Diffs of the changes: (+11 -13)
PPCISelLowering.cpp | 24 +++-
1 files changed, 11 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.209
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.210
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.209 Tue Oct 3 19:55:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Oct 5 18:00:19 2006
@@ -743,8 +743,7 @@
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
- Op.getOperand(1), Op.getOperand(2));
+ return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1),
Op.getOperand(2));
}
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG DAG,
@@ -900,8 +899,8 @@
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
-Val, FIN, DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
+ DAG.getSrcValue(NULL));
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
@@ -1035,8 +1034,8 @@
if (GPR_idx != NumGPRs) {
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
} else {
-MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Arg, PtrOff, DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
+ DAG.getSrcValue(NULL)));
}
ArgOffset += PtrByteSize;
break;
@@ -1046,9 +1045,8 @@
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
if (isVarArg) {
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-Arg, PtrOff,
-DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(Chain, Arg, PtrOff,
+ DAG.getSrcValue(NULL));
MemOpChains.push_back(Store);
// Float varargs are always shadowed in available integer registers
@@ -1076,8 +1074,8 @@
++GPR_idx;
}
} else {
-MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Arg, PtrOff, DAG.getSrcValue(NULL)));
+MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
+ DAG.getSrcValue(NULL)));
}
if (isPPC64)
ArgOffset += 8;
@@ -2123,8 +2121,8 @@
SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
// Store the input value into Value#0 of the stack slot.
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
-Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
+ SDOperand Store = DAG.getStore(DAG.getEntryNode(),
+ Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
// Load it out.
return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.208 - 1.209
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+5 -5)
PPCISelLowering.cpp | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.208
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.209
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.208 Tue Sep 19 22:47:40 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Oct 3 19:55:33 2006
@@ -43,6 +43,10 @@
addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
+ // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
+ setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
+ setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
+
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
@@ -51,10 +55,6 @@
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
- // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
- setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
- setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-
// PowerPC has no SREM/UREM instructions
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
@@ -311,7 +311,7 @@
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_castConstantFPSDNode(Op))
return CFP-isExactlyValue(-0.0) || CFP-isExactlyValue(0.0);
- else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
+ else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_castConstantPoolSDNode(Op.getOperand(1)))
if (ConstantFP *CFP = dyn_castConstantFP(CP-getConstVal()))
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.207 - 1.208
---
Log message:
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X (C|32);
}
long long foo2(long long X, int C) {
return X (C~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
---
Diffs of the changes: (+32 -41)
PPCISelLowering.cpp | 73 ++--
1 files changed, 32 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.207
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.208
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.207 Tue Sep 19 00:22:59 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 19 22:47:40 2006
@@ -181,9 +181,9 @@
setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
} else {
// 32 bit PowerPC wants to expand i64 shifts itself.
-setOperationAction(ISD::SHL, MVT::i64, Custom);
-setOperationAction(ISD::SRL, MVT::i64, Custom);
-setOperationAction(ISD::SRA, MVT::i64, Custom);
+setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
+setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
}
if (TM.getSubtargetPPCSubtarget().hasAltivec()) {
@@ -1412,20 +1412,15 @@
return FP;
}
-static SDOperand LowerSHL(SDOperand Op, SelectionDAG DAG,
- MVT::ValueType PtrVT) {
- assert(Op.getValueType() == MVT::i64
+static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG DAG) {
+ assert(Op.getNumOperands() == 3 Op.getValueType() == MVT::i32
Op.getOperand(1).getValueType() == MVT::i32 Unexpected SHL!);
- // The generic code does a fine job expanding shift by a constant.
- if (isaConstantSDNode(Op.getOperand(1))) return SDOperand();
- // Otherwise, expand into a bunch of logical ops. Note that these ops
+ // Expand into a bunch of logical ops. Note that these ops
// depend on the PPC behavior for oversized shift amounts.
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
- DAG.getConstant(0, PtrVT));
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
- DAG.getConstant(1, PtrVT));
- SDOperand Amt = Op.getOperand(1);
+ SDOperand Lo = Op.getOperand(0);
+ SDOperand Hi = Op.getOperand(1);
+ SDOperand Amt = Op.getOperand(2);
SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
DAG.getConstant(32, MVT::i32), Amt);
@@ -1437,23 +1432,20 @@
SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
+ SDOperand OutOps[] = { OutLo, OutHi };
+ return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
+ OutOps, 2);
}
-static SDOperand LowerSRL(SDOperand Op, SelectionDAG DAG,
- MVT::ValueType PtrVT) {
- assert(Op.getValueType() == MVT::i64
- Op.getOperand(1).getValueType() == MVT::i32 Unexpected SHL!);
- // The generic code does a fine job expanding shift by a constant.
- if (isaConstantSDNode(Op.getOperand(1))) return SDOperand();
+static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG DAG) {
+ assert(Op.getNumOperands() == 3 Op.getValueType() == MVT::i32
+ Op.getOperand(1).getValueType() == MVT::i32 Unexpected SRL!);
// Otherwise, expand into a bunch of logical ops. Note that these ops
// depend on the PPC behavior for oversized shift amounts.
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
- DAG.getConstant(0, PtrVT));
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
- DAG.getConstant(1, PtrVT));
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.206 - 1.207
---
Log message:
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
like:
long long test(long long X, int Y) {
return 1ULL Y;
}
long long test2(long long X, int Y) {
return -1LL Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
---
Diffs of the changes: (+20 -0)
PPCISelLowering.cpp | 20
1 files changed, 20 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.206
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.207
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.206 Tue Sep 12 16:02:35 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 19 00:22:59 2006
@@ -2309,6 +2309,26 @@
SelectionDAG DAG = DCI.DAG;
switch (N-getOpcode()) {
default: break;
+ case PPCISD::SHL:
+if (ConstantSDNode *C = dyn_castConstantSDNode(N-getOperand(0))) {
+ if (C-getValue() == 0) // 0 V - 0.
+return N-getOperand(0);
+}
+break;
+ case PPCISD::SRL:
+if (ConstantSDNode *C = dyn_castConstantSDNode(N-getOperand(0))) {
+ if (C-getValue() == 0) // 0 u V - 0.
+return N-getOperand(0);
+}
+break;
+ case PPCISD::SRA:
+if (ConstantSDNode *C = dyn_castConstantSDNode(N-getOperand(0))) {
+ if (C-getValue() == 0 || // 0 s V - 0.
+ C-isAllOnesValue())// -1 s V - -1.
+return N-getOperand(0);
+}
+break;
+
case ISD::SINT_TO_FP:
if (TM.getSubtargetPPCSubtarget().has64BitSupport()) {
if (N-getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.204 - 1.205
PPCISelLowering.h updated: 1.51 - 1.52
---
Log message:
For PR387: http://llvm.org/PR387 :
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
---
Diffs of the changes: (+5 -0)
PPCISelLowering.cpp |4
PPCISelLowering.h |1 +
2 files changed, 5 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.204
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.205
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.204 Sat Aug 12 02:20:05 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Aug 27 20:02:49 2006
@@ -2691,3 +2691,7 @@
// PPC allows a sign-extended 16-bit immediate field.
return (V -(1 16) V (1 16)-1);
}
+
+bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
+ return TargetLowering::isLegalAddressImmediate(GV);
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.51
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.52
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.51 Mon Jul 10 15:56:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sun Aug 27 20:02:49 2006
@@ -199,6 +199,7 @@
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode.
virtual bool isLegalAddressImmediate(int64_t V) const;
+virtual bool isLegalAddressImmediate(llvm::GlobalValue*) const;
};
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.203 - 1.204 --- Log message: Fix a bug in a recent refactoring that broke a bunch of stuff. --- Diffs of the changes: (+1 -1) PPCISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.203 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.204 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.203 Fri Aug 11 12:38:39 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Aug 12 02:20:05 2006 @@ -1216,7 +1216,7 @@ NodeTys.push_back(MVT::Other); // If the function returns void, just return the chain. - if (NumResults == 1) + if (NumResults == 0) return Chain; // Otherwise, merge everything together with a MERGE_VALUES node. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.201 - 1.202
---
Log message:
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of
getNode that takes a vector.
---
Diffs of the changes: (+42 -37)
PPCISelLowering.cpp | 79 +++-
1 files changed, 42 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.201
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.202
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.201 Fri Aug 11 11:47:32 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Aug 11 12:18:05 2006
@@ -754,7 +754,7 @@
MachineFunction MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SSARegMap *RegMap = MF.getSSARegMap();
- std::vectorSDOperand ArgValues;
+ SmallVectorSDOperand, 8 ArgValues;
SDOperand Root = Op.getOperand(0);
unsigned ArgOffset = 24;
@@ -916,7 +916,7 @@
// Return the new list of results.
std::vectorMVT::ValueType RetVT(Op.Val-value_begin(),
Op.Val-value_end());
- return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
+ return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues[0],
ArgValues.size());
}
/// isCallCompatibleAddress - Return the immediate to use if the specified
@@ -,7 +,7 @@
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
- std::vectorSDOperand Ops;
+ SmallVectorSDOperand, 8 Ops;
unsigned CallOpc = PPCISD::CALL;
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
@@ -1127,12 +1127,8 @@
else {
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
// to do the call, we can't use PPCISD::CALL.
-Ops.push_back(Chain);
-Ops.push_back(Callee);
-
-if (InFlag.Val)
- Ops.push_back(InFlag);
-Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops);
+SDOperand MTCTROps[] = {Chain, Callee, InFlag};
+Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
InFlag = Chain.getValue(1);
// Copy the callee address into R12 on darwin.
@@ -1142,7 +1138,6 @@
NodeTys.clear();
NodeTys.push_back(MVT::Other);
NodeTys.push_back(MVT::Flag);
-Ops.clear();
Ops.push_back(Chain);
CallOpc = PPCISD::BCTRL;
Callee.Val = 0;
@@ -1162,10 +1157,11 @@
if (InFlag.Val)
Ops.push_back(InFlag);
- Chain = DAG.getNode(CallOpc, NodeTys, Ops);
+ Chain = DAG.getNode(CallOpc, NodeTys, Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- std::vectorSDOperand ResultVals;
+ SDOperand ResultVals[3];
+ unsigned NumResults = 0;
NodeTys.clear();
// If the call has results, copy the values out of the ret val registers.
@@ -1175,27 +1171,31 @@
case MVT::i32:
if (Op.Val-getValueType(1) == MVT::i32) {
Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
- ResultVals.push_back(Chain.getValue(0));
+ ResultVals[0] = Chain.getValue(0);
Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
Chain.getValue(2)).getValue(1);
- ResultVals.push_back(Chain.getValue(0));
+ ResultVals[1] = Chain.getValue(0);
+ NumResults = 2;
NodeTys.push_back(MVT::i32);
} else {
Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
- ResultVals.push_back(Chain.getValue(0));
+ ResultVals[0] = Chain.getValue(0);
+ NumResults = 1;
}
NodeTys.push_back(MVT::i32);
break;
case MVT::i64:
Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
+ResultVals[0] = Chain.getValue(0);
+NumResults = 1;
NodeTys.push_back(MVT::i64);
break;
case MVT::f32:
case MVT::f64:
Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val-getValueType(0),
InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
+ResultVals[0] = Chain.getValue(0);
+NumResults = 1;
NodeTys.push_back(Op.Val-getValueType(0));
break;
case MVT::v4f32:
@@ -1204,7 +1204,8 @@
case MVT::v16i8:
Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val-getValueType(0),
InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
+ResultVals[0] = Chain.getValue(0);
+NumResults = 1;
NodeTys.push_back(Op.Val-getValueType(0));
break;
}
@@ -1214,12 +1215,13 @@
NodeTys.push_back(MVT::Other);
// If the function returns void, just return the chain.
- if (ResultVals.empty())
+ if (NumResults == 1)
return Chain;
// Otherwise, merge everything together with a MERGE_VALUES node.
- ResultVals.push_back(Chain);
- SDOperand Res = DAG.getNode(ISD::MERGE_VALUES,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.202 - 1.203
---
Log message:
Eliminate use of getNode that takes a vector.
---
Diffs of the changes: (+22 -19)
PPCISelLowering.cpp | 41 ++---
1 files changed, 22 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.202
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.203
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.202 Fri Aug 11 12:18:05 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Aug 11 12:38:39 2006
@@ -895,7 +895,7 @@
// If this function is vararg, store any remaining integer argument regs
// to their spots on the stack so that they may be loaded by deferencing
the
// result of va_next.
-std::vectorSDOperand MemOps;
+SmallVectorSDOperand, 8 MemOps;
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
@@ -908,7 +908,7 @@
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
+ Root = DAG.getNode(ISD::TokenFactor,
MVT::Other,MemOps[0],MemOps.size());
}
ArgValues.push_back(Root);
@@ -1011,7 +1011,7 @@
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
std::vectorstd::pairunsigned, SDOperand RegsToPass;
- std::vectorSDOperand MemOpChains;
+ SmallVectorSDOperand, 8 MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
@@ -1096,7 +1096,8 @@
}
}
if (!MemOpChains.empty())
-Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
+Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
@@ -1609,8 +1610,10 @@
// Build a canonical splat for this value.
SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
- std::vectorSDOperand Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
- SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
+ SmallVectorSDOperand, 8 Ops;
+ Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
+ SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
+ Ops[0], Ops.size());
return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
}
@@ -1643,11 +1646,11 @@
LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
- std::vectorSDOperand Ops;
+ SDOperand Ops[16];
for (unsigned i = 0; i != 16; ++i)
-Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
+Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
-DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
+DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
Ops,16));
return DAG.getNode(ISD::BIT_CONVERT, VT, T);
}
@@ -1879,12 +1882,12 @@
case OP_VSLDOI12:
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
}
- std::vectorSDOperand Ops;
+ SDOperand Ops[16];
for (unsigned i = 0; i != 16; ++i)
-Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
+Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
+ DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
}
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
@@ -1992,7 +1995,7 @@
MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
- std::vectorSDOperand ResultMask;
+ SmallVectorSDOperand, 16 ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
unsigned SrcElt;
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
@@ -2005,7 +2008,8 @@
MVT::i8));
}
- SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
+ SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
+ResultMask[0], ResultMask.size());
return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
}
@@ -2180,14 +2184,13 @@
OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
// Merge the results together.
-std::vectorSDOperand Ops;
+SDOperand Ops[16];
for (unsigned i = 0; i != 8; ++i) {
- Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.193 - 1.194 --- Log message: Use i32 for shift amounts instead of i64. This gets bisort working. --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.193 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.194 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.193 Mon Jun 26 19:04:13 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 27 12:34:57 2006 @@ -250,6 +250,7 @@ } setSetCCResultType(MVT::i32); + setShiftAmountType(MVT::i32); setSetCCResultContents(ZeroOrOneSetCCResult); setStackPointerRegisterToSaveRestore(PPC::R1); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.195 - 1.196 --- Log message: PPC doesn't have bit converts to/from i64 --- Diffs of the changes: (+2 -0) PPCISelLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.195 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.196 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.195 Tue Jun 27 13:18:41 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 27 13:40:08 2006 @@ -110,6 +110,8 @@ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); + setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); + setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); // PowerPC does not have truncstore for i1. setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.196 - 1.197 --- Log message: Implement 64-bit select, bswap, etc. --- Diffs of the changes: (+4 -0) PPCISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.196 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.197 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.196 Tue Jun 27 13:40:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 27 15:14:52 2006 @@ -82,12 +82,16 @@ setOperationAction(ISD::BSWAP, MVT::i32 , Expand); setOperationAction(ISD::CTPOP, MVT::i32 , Expand); setOperationAction(ISD::CTTZ , MVT::i32 , Expand); + setOperationAction(ISD::BSWAP, MVT::i64 , Expand); + setOperationAction(ISD::CTPOP, MVT::i64 , Expand); + setOperationAction(ISD::CTTZ , MVT::i64 , Expand); // PowerPC does not have ROTR setOperationAction(ISD::ROTR, MVT::i32 , Expand); // PowerPC does not have Select setOperationAction(ISD::SELECT, MVT::i32, Expand); + setOperationAction(ISD::SELECT, MVT::i64, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::f64, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.191 - 1.192
---
Log message:
Improve PPC64 calling convention support
---
Diffs of the changes: (+84 -37)
PPCISelLowering.cpp | 121
1 files changed, 84 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.191
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.192
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.191 Tue Jun 20 19:34:03 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jun 26 17:48:35 2006
@@ -733,8 +733,8 @@
Op.getOperand(1), Op.getOperand(2));
}
-static SDOperand LowerFORMAL_ARGUMENTS_32(SDOperand Op, SelectionDAG DAG,
- int VarArgsFrameIndex) {
+static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG DAG,
+ int VarArgsFrameIndex) {
// TODO: add description of PPC stack frame format, or at least some docs.
//
MachineFunction MF = DAG.getMachineFunction();
@@ -748,10 +748,15 @@
const unsigned Num_FPR_Regs = 13;
const unsigned Num_VR_Regs = 12;
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
- static const unsigned GPR[] = {
+
+ static const unsigned GPR_32[] = { // 32-bit registers.
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
+ static const unsigned GPR_64[] = { // 64-bit registers.
+PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+PPC::X7, PPC::X8, PPC::X9, PPC::X10,
+ };
static const unsigned FPR[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
@@ -760,6 +765,10 @@
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
};
+
+ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ bool isPPC64 = PtrVT == MVT::i64;
+ const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
// Add DAG nodes to load the arguments or copy them out of registers. On
// entry to a function on PPC, the arguments start at offset 24, although the
@@ -771,12 +780,11 @@
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
unsigned CurArgOffset = ArgOffset;
-
switch (ObjectVT) {
default: assert(0 Unhandled argument type!);
case MVT::i32:
// All int arguments reserve stack space.
- ArgOffset += 4;
+ ArgOffset += isPPC64 ? 8 : 4;
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
@@ -787,6 +795,19 @@
needsLoad = true;
}
break;
+case MVT::i64: // PPC64
+ // All int arguments reserve stack space.
+ ArgOffset += 8;
+
+ if (GPR_idx != Num_GPR_Regs) {
+unsigned VReg = RegMap-createVirtualRegister(PPC::G8RCRegClass);
+MF.addLiveIn(GPR[GPR_idx], VReg);
+ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
+++GPR_idx;
+ } else {
+needsLoad = true;
+ }
+ break;
case MVT::f32:
case MVT::f64:
// All FP arguments reserve stack space.
@@ -838,7 +859,7 @@
// slot.
if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
int FI = MFI-CreateFixedObject(ObjSize, CurArgOffset);
-SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
DAG.getSrcValue(NULL));
} else {
@@ -854,8 +875,9 @@
// the start of the first vararg value... for expansion of llvm.va_start.
bool isVarArg = castConstantSDNode(Op.getOperand(2))-getValue() != 0;
if (isVarArg) {
-VarArgsFrameIndex = MFI-CreateFixedObject(4, ArgOffset);
-SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+VarArgsFrameIndex = MFI-CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
+ ArgOffset);
+SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
// If this function is vararg, store any remaining integer argument regs
// to their spots on the stack so that they may be loaded by deferencing
the
// result of va_next.
@@ -863,13 +885,13 @@
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
- SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
Val, FIN, DAG.getSrcValue(NULL));
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
- SDOperand PtrOff = DAG.getConstant(4,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.190 - 1.191
---
Log message:
Correct returns of 64-bit values, though they seemed to work before...
---
Diffs of the changes: (+19 -9)
PPCISelLowering.cpp | 28 +++-
1 files changed, 19 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.190
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.191
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.190 Fri Jun 16 16:01:35 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 20 19:34:03 2006
@@ -733,8 +733,8 @@
Op.getOperand(1), Op.getOperand(2));
}
-static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG DAG,
- int VarArgsFrameIndex) {
+static SDOperand LowerFORMAL_ARGUMENTS_32(SDOperand Op, SelectionDAG DAG,
+ int VarArgsFrameIndex) {
// TODO: add description of PPC stack frame format, or at least some docs.
//
MachineFunction MF = DAG.getMachineFunction();
@@ -883,6 +883,11 @@
return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
}
+static SDOperand LowerFORMAL_ARGUMENTS_64(SDOperand Op, SelectionDAG DAG,
+ int VarArgsFrameIndex) {
+ return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
+}
+
/// isCallCompatibleAddress - Return the immediate to use if the specified
/// 32-bit value is representable in the immediate field of a BxA instruction.
static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG DAG) {
@@ -1165,13 +1170,15 @@
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
-if (MVT::isVector(ArgVT))
- ArgReg = PPC::V2;
-else if (MVT::isInteger(ArgVT))
+if (ArgVT == MVT::i32) {
ArgReg = PPC::R3;
-else {
- assert(MVT::isFloatingPoint(ArgVT));
+} else if (ArgVT == MVT::i64) {
+ ArgReg = PPC::X3;
+} else if (MVT::isFloatingPoint(ArgVT)) {
ArgReg = PPC::F1;
+} else {
+ assert(MVT::isVector(ArgVT));
+ ArgReg = PPC::V2;
}
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
@@ -2128,8 +2135,11 @@
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::VASTART:return LowerVASTART(Op, DAG,
VarArgsFrameIndex);
- case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
-
VarArgsFrameIndex);
+ case ISD::FORMAL_ARGUMENTS:
+if (getPointerTy() == MVT::i32)
+ return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
+else
+ return LowerFORMAL_ARGUMENTS_64(Op, DAG, VarArgsFrameIndex);
case ISD::CALL: return LowerCALL(Op, DAG);
case ISD::RET:return LowerRET(Op, DAG);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.189 - 1.190
PPCInstr64Bit.td updated: 1.1 - 1.2
PPCInstrInfo.td updated: 1.223 - 1.224
---
Log message:
fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
---
Diffs of the changes: (+59 -62)
PPCISelLowering.cpp | 67 +++-
PPCInstr64Bit.td| 33 ++---
PPCInstrInfo.td | 21 +++-
3 files changed, 59 insertions(+), 62 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.189
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.190
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.189 Fri Jun 16 12:34:12 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 16 16:01:35 2006
@@ -128,7 +128,10 @@
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
-
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+
// RET must be custom lowered, to meet ABI requirements
setOperationAction(ISD::RET , MVT::Other, Custom);
@@ -583,94 +586,94 @@
//===--===//
static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG DAG) {
+ MVT::ValueType PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = castConstantPoolSDNode(Op);
Constant *C = CP-get();
- SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP-getAlignment());
- SDOperand Zero = DAG.getConstant(0, MVT::i32);
+ SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP-getAlignment());
+ SDOperand Zero = DAG.getConstant(0, PtrVT);
const TargetMachine TM = DAG.getTarget();
+ SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
+ SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
+
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
if (TM.getRelocationModel() == Reloc::Static ||
!TM.getSubtargetPPCSubtarget().isDarwin()) {
// Generate non-pic code that has direct accesses to the constant pool.
// The address of the global is just (hi(g)+lo(g)).
-SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
-SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
-return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
}
- SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
if (TM.getRelocationModel() == Reloc::PIC) {
// With PIC, the first instruction is actually GR+hi(G).
-Hi = DAG.getNode(ISD::ADD, MVT::i32,
- DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
+Hi = DAG.getNode(ISD::ADD, PtrVT,
+ DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
}
- SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
- Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+ Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
return Lo;
}
static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG DAG) {
+ MVT::ValueType PtrVT = Op.getValueType();
JumpTableSDNode *JT = castJumpTableSDNode(Op);
- SDOperand JTI = DAG.getTargetJumpTable(JT-getIndex(), MVT::i32);
- SDOperand Zero = DAG.getConstant(0, MVT::i32);
+ SDOperand JTI = DAG.getTargetJumpTable(JT-getIndex(), PtrVT);
+ SDOperand Zero = DAG.getConstant(0, PtrVT);
const TargetMachine TM = DAG.getTarget();
-
+
+ SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
+ SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
+
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
if (TM.getRelocationModel() == Reloc::Static ||
!TM.getSubtargetPPCSubtarget().isDarwin()) {
// Generate non-pic code that has direct accesses to the constant pool.
// The address of the global is just (hi(g)+lo(g)).
-SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
-SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
-return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
}
- SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
if (TM.getRelocationModel() == Reloc::PIC) {
// With PIC, the first instruction is actually GR+hi(G).
-Hi = DAG.getNode(ISD::ADD, MVT::i32,
+Hi = DAG.getNode(ISD::ADD, PtrVT,
DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
}
- SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
- Lo =
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.185 - 1.186 --- Log message: Always reserve space for 8 spilled GPRs. GCC apparently assumes that this space will be available, even if the callee isn't varargs. --- Diffs of the changes: (+7 -12) PPCISelLowering.cpp | 19 +++ 1 files changed, 7 insertions(+), 12 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.185 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.186 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.185 Fri May 26 18:10:12 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 30 16:21:04 2006 @@ -916,18 +916,13 @@ for (unsigned i = 0; i != NumOps; ++i) NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; - // If we are calling what looks like a varargs function on the caller side, - // there are two cases: - // 1) The callee uses va_start. - // 2) The callee doesn't use va_start. - // - // In the case of #1, the prolog code will store up to 8 GPR argument - // registers to the stack, allowing va_start to index over them in memory. - // Because we cannot tell the difference (on the caller side) between #1/#2, - // we have to conservatively assume we have #1. As such, make sure we have - // at least enough stack space for the caller to store the 8 GPRs. - if (isVarArg Op.getNumOperands() 5 NumBytes 56) -NumBytes = 56; + // The prolog code of the callee may store up to 8 GPR argument registers to + // the stack, allowing va_start to index over them in memory if its varargs. + // Because we cannot tell if this is needed on the caller side, we have to + // conservatively assume that it is needed. As such, make sure we have at + // least enough stack space for the caller to store the 8 GPRs. + if (NumBytes 24+8*4) +NumBytes = 24+8*4; // Adjust the stack pointer for the new arguments... // These operations are automatically eliminated by the prolog/epilog pass ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.184 - 1.185
---
Log message:
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
---
Diffs of the changes: (+3 -3)
PPCISelLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.184
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.185
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.184 Wed May 24 19:57:32 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri May 26 18:10:12 2006
@@ -1160,7 +1160,7 @@
abort();
case 1:
return SDOperand(); // ret void is legal
- case 2: {
+ case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
if (MVT::isVector(ArgVT))
@@ -1180,8 +1180,8 @@
DAG.getMachineFunction().addLiveOut(ArgReg);
break;
}
- case 3:
-Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
+ case 5:
+Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
// If we haven't noted the R3+R4 are live out, do so now.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrInfo.h PPCJITInfo.cpp PPCRelocations.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.182 - 1.183
PPCInstrInfo.h updated: 1.14 - 1.15
PPCJITInfo.cpp updated: 1.21 - 1.22
PPCRelocations.h updated: 1.6 - 1.7
---
Log message:
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786:
http://llvm.cs.uiuc.edu/PR786 .
---
Diffs of the changes: (+5 -5)
PPCISelLowering.cpp |2 +-
PPCInstrInfo.h |4 ++--
PPCJITInfo.cpp |2 +-
PPCRelocations.h|2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.182
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.183
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.182 Tue May 23 19:15:25 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed May 24 12:04:04 2006
@@ -1748,7 +1748,7 @@
OP_VSPLTISW3,
OP_VSLDOI4,
OP_VSLDOI8,
-OP_VSLDOI12,
+OP_VSLDOI12
};
if (OpNum == OP_COPY) {
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.h
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.h:1.14
llvm/lib/Target/PowerPC/PPCInstrInfo.h:1.15
--- llvm/lib/Target/PowerPC/PPCInstrInfo.h:1.14 Sun Mar 12 23:15:10 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.h Wed May 24 12:04:04 2006
@@ -44,7 +44,7 @@
/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
/// an instruction is issued to.
PPC970_Shift = 3,
- PPC970_Mask = 0x07 PPC970_Shift,
+ PPC970_Mask = 0x07 PPC970_Shift
};
enum PPC970_Unit {
/// These are the various PPC970 execution unit pipelines. Each instruction
@@ -56,7 +56,7 @@
PPC970_CRU= 4 PPC970_Shift, // Control Register Unit
PPC970_VALU = 5 PPC970_Shift, // Vector ALU
PPC970_VPERM = 6 PPC970_Shift, // Vector Permute Unit
- PPC970_BRU= 7 PPC970_Shift, // Branch Unit
+ PPC970_BRU= 7 PPC970_Shift// Branch Unit
};
}
Index: llvm/lib/Target/PowerPC/PPCJITInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.21
llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.22
--- llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.21 Tue May 2 14:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCJITInfo.cpp Wed May 24 12:04:04 2006
@@ -165,7 +165,7 @@
void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter MCE) {
// If this is just a call to an external function, emit a branch instead of a
// call. The code is the same except for one bit of the last instruction.
- if (Fn != PPC32CompilationCallback) {
+ if (Fn != (void*)PPC32CompilationCallback) {
MCE.startFunctionStub(4*4);
void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
MCE.emitWordBE(0);
Index: llvm/lib/Target/PowerPC/PPCRelocations.h
diff -u llvm/lib/Target/PowerPC/PPCRelocations.h:1.6
llvm/lib/Target/PowerPC/PPCRelocations.h:1.7
--- llvm/lib/Target/PowerPC/PPCRelocations.h:1.6Sun Oct 16 00:39:50 2005
+++ llvm/lib/Target/PowerPC/PPCRelocations.hWed May 24 12:04:04 2006
@@ -50,7 +50,7 @@
// relocated to point to a POINTER to the indicated global. The low-16
// bits of the instruction are rewritten with the low 16-bits of the
// address of the pointer.
- reloc_absolute_ptr_low,
+ reloc_absolute_ptr_low
};
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.183 - 1.184
---
Log message:
CALL node change (arg / sign pairs instead of just arguments).
---
Diffs of the changes: (+6 -5)
PPCISelLowering.cpp | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.183
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.184
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.183 Wed May 24 12:04:04 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed May 24 19:57:32 2006
@@ -901,7 +901,8 @@
bool isVarArg = castConstantSDNode(Op.getOperand(2))-getValue() !=
0;
bool isTailCall = castConstantSDNode(Op.getOperand(3))-getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
-
+ unsigned NumOps = (Op.getNumOperands() - 5) / 2;
+
// args_to_use will accumulate outgoing args for the PPCISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vectorSDOperand args_to_use;
@@ -912,8 +913,8 @@
unsigned NumBytes = 24;
// Add up all the space actually used.
- for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i)
-NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8;
+ for (unsigned i = 0; i != NumOps; ++i)
+NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
// If we are calling what looks like a varargs function on the caller side,
// there are two cases:
@@ -962,8 +963,8 @@
std::vectorstd::pairunsigned, SDOperand RegsToPass;
std::vectorSDOperand MemOpChains;
- for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) {
-SDOperand Arg = Op.getOperand(i);
+ for (unsigned i = 0; i != NumOps; ++i) {
+SDOperand Arg = Op.getOperand(5+2*i);
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.180 - 1.181
---
Log message:
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
change. This fixes PowerPC/fnegsel.ll.
---
Diffs of the changes: (+8 -0)
PPCISelLowering.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.180
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.181
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.180 Wed May 17 14:00:46 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 23 19:06:44 2006
@@ -1216,17 +1216,21 @@
switch (CC) {
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT:
+case ISD::SETOLT:
case ISD::SETLT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETUGE:
+case ISD::SETOGE:
case ISD::SETGE:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
case ISD::SETUGT:
+case ISD::SETOGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETULE:
+case ISD::SETOLE:
case ISD::SETLE:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
@@ -1238,24 +1242,28 @@
switch (CC) {
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT:
+ case ISD::SETOLT:
case ISD::SETLT:
Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
case ISD::SETUGE:
+ case ISD::SETOGE:
case ISD::SETGE:
Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
case ISD::SETUGT:
+ case ISD::SETOGT:
case ISD::SETGT:
Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
case ISD::SETULE:
+ case ISD::SETOLE:
case ISD::SETLE:
Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.181 - 1.182 --- Log message: Fix CodeGen/Generic/vector.ll:test_div with altivec. --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.181 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.182 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.181 Tue May 23 19:06:44 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 23 19:15:25 2006 @@ -208,6 +208,7 @@ setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.171 - 1.172
PPCISelLowering.h updated: 1.47 - 1.48
---
Log message:
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
---
Diffs of the changes: (+157 -172)
PPCISelLowering.cpp | 325 +---
PPCISelLowering.h |4
2 files changed, 157 insertions(+), 172 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.171
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.172
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.171 Mon May 15 23:20:24 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:18:50 2006
@@ -727,6 +727,161 @@
Op.getOperand(1), Op.getOperand(2));
}
+static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG DAG,
+ int VarArgsFrameIndex) {
+ // TODO: add description of PPC stack frame format, or at least some docs.
+ //
+ MachineFunction MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ SSARegMap *RegMap = MF.getSSARegMap();
+ std::vectorSDOperand ArgValues;
+ SDOperand Root = Op.getOperand(0);
+
+ unsigned ArgOffset = 24;
+ unsigned GPR_remaining = 8;
+ unsigned FPR_remaining = 13;
+ unsigned VR_remaining = 12;
+ unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
+ static const unsigned GPR[] = {
+PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+ };
+ static const unsigned FPR[] = {
+PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
+ };
+ static const unsigned VR[] = {
+PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
+PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+ };
+
+ // Add DAG nodes to load the arguments or copy them out of registers. On
+ // entry to a function on PPC, the arguments start at offset 24, although the
+ // first ones are often in registers.
+ for (unsigned ArgNo = 0, e = Op.Val-getNumValues()-1; ArgNo != e; ++ArgNo) {
+SDOperand ArgVal;
+bool needsLoad = false;
+bool ArgLive = !Op.Val-hasNUsesOfValue(0, ArgNo);
+MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
+unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
+
+switch (ObjectVT) {
+default: assert(0 Unhandled argument type!);
+case MVT::i32:
+ if (!ArgLive) break;
+ if (GPR_remaining 0) {
+unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
+MF.addLiveIn(GPR[GPR_idx], VReg);
+ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ } else {
+needsLoad = true;
+ }
+ break;
+case MVT::f32:
+case MVT::f64:
+ if (!ArgLive) {
+if (FPR_remaining 0) {
+ --FPR_remaining;
+ ++FPR_idx;
+}
+break;
+ }
+ if (FPR_remaining 0) {
+unsigned VReg;
+if (ObjectVT == MVT::f32)
+ VReg = RegMap-createVirtualRegister(PPC::F4RCRegClass);
+else
+ VReg = RegMap-createVirtualRegister(PPC::F8RCRegClass);
+MF.addLiveIn(FPR[FPR_idx], VReg);
+ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
+--FPR_remaining;
+++FPR_idx;
+ } else {
+needsLoad = true;
+ }
+ break;
+case MVT::v4f32:
+case MVT::v4i32:
+case MVT::v8i16:
+case MVT::v16i8:
+ if (!ArgLive) {
+if (VR_remaining 0) {
+ --VR_remaining;
+ ++VR_idx;
+}
+break;
+ }
+ if (VR_remaining 0) {
+unsigned VReg = RegMap-createVirtualRegister(PPC::VRRCRegClass);
+MF.addLiveIn(VR[VR_idx], VReg);
+ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
+--VR_remaining;
+++VR_idx;
+ } else {
+// This should be simple, but requires getting 16-byte aligned stack
+// values.
+assert(0 Loading VR argument not implemented yet!);
+needsLoad = true;
+ }
+ break;
+}
+
+// We need to load the argument to a virtual register if we determined
above
+// that we ran out of physical registers of the appropriate type
+if (needsLoad) {
+ int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+ ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
+ DAG.getSrcValue(NULL));
+}
+
+// Every 4 bytes of argument space consumes one of the GPRs available for
+// argument passing.
+if (GPR_remaining 0) {
+ unsigned delta = (GPR_remaining 1 ObjSize == 8) ? 2 : 1;
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.172 - 1.173
---
Log message:
Vector args passed in registers don't reserve stack space.
---
Diffs of the changes: (+26 -11)
PPCISelLowering.cpp | 37 ++---
1 files changed, 26 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.172
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.173
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.172 Tue May 16 13:18:50 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:51:52 2006
@@ -765,20 +765,43 @@
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
+unsigned CurArgOffset = ArgOffset;
+
switch (ObjectVT) {
default: assert(0 Unhandled argument type!);
case MVT::i32:
- if (!ArgLive) break;
+ // All int arguments reserve stack space.
+ ArgOffset += 4;
+
+ if (!ArgLive) {
+if (GPR_remaining 0) {
+ --GPR_remaining;
+ ++GPR_idx;
+}
+break;
+ }
if (GPR_remaining 0) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+--GPR_remaining;
+++GPR_idx;
} else {
needsLoad = true;
}
break;
case MVT::f32:
case MVT::f64:
+ // All FP arguments reserve stack space.
+ ArgOffset += ObjSize;
+
+ // Every 4 bytes of argument space consumes one of the GPRs available for
+ // argument passing.
+ if (GPR_remaining 0) {
+unsigned delta = (GPR_remaining 1 ObjSize == 8) ? 2 : 1;
+GPR_remaining -= delta;
+GPR_idx += delta;
+ }
if (!ArgLive) {
if (FPR_remaining 0) {
--FPR_remaining;
@@ -804,6 +827,7 @@
case MVT::v4i32:
case MVT::v8i16:
case MVT::v16i8:
+ // Note that vector arguments in registers don't reserve stack space.
if (!ArgLive) {
if (VR_remaining 0) {
--VR_remaining;
@@ -829,21 +853,12 @@
// We need to load the argument to a virtual register if we determined
above
// that we ran out of physical registers of the appropriate type
if (needsLoad) {
- int FI = MFI-CreateFixedObject(ObjSize, ArgOffset);
+ int FI = MFI-CreateFixedObject(ObjSize, CurArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
DAG.getSrcValue(NULL));
}
-// Every 4 bytes of argument space consumes one of the GPRs available for
-// argument passing.
-if (GPR_remaining 0) {
- unsigned delta = (GPR_remaining 1 ObjSize == 8) ? 2 : 1;
- GPR_remaining -= delta;
- GPR_idx += delta;
-}
-ArgOffset += ObjSize;
-
if (ArgVal.Val == 0)
ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
ArgValues.push_back(ArgVal);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.173 - 1.174
---
Log message:
Simplify the dead argument handling code.
---
Diffs of the changes: (+11 -28)
PPCISelLowering.cpp | 39 +++
1 files changed, 11 insertions(+), 28 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.173
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.174
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.173 Tue May 16 13:51:52 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:54:32 2006
@@ -761,7 +761,6 @@
for (unsigned ArgNo = 0, e = Op.Val-getNumValues()-1; ArgNo != e; ++ArgNo) {
SDOperand ArgVal;
bool needsLoad = false;
-bool ArgLive = !Op.Val-hasNUsesOfValue(0, ArgNo);
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
@@ -773,13 +772,6 @@
// All int arguments reserve stack space.
ArgOffset += 4;
- if (!ArgLive) {
-if (GPR_remaining 0) {
- --GPR_remaining;
- ++GPR_idx;
-}
-break;
- }
if (GPR_remaining 0) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
@@ -802,13 +794,6 @@
GPR_remaining -= delta;
GPR_idx += delta;
}
- if (!ArgLive) {
-if (FPR_remaining 0) {
- --FPR_remaining;
- ++FPR_idx;
-}
-break;
- }
if (FPR_remaining 0) {
unsigned VReg;
if (ObjectVT == MVT::f32)
@@ -828,13 +813,6 @@
case MVT::v8i16:
case MVT::v16i8:
// Note that vector arguments in registers don't reserve stack space.
- if (!ArgLive) {
-if (VR_remaining 0) {
- --VR_remaining;
- ++VR_idx;
-}
-break;
- }
if (VR_remaining 0) {
unsigned VReg = RegMap-createVirtualRegister(PPC::VRRCRegClass);
MF.addLiveIn(VR[VR_idx], VReg);
@@ -853,14 +831,19 @@
// We need to load the argument to a virtual register if we determined
above
// that we ran out of physical registers of the appropriate type
if (needsLoad) {
- int FI = MFI-CreateFixedObject(ObjSize, CurArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
- ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
- DAG.getSrcValue(NULL));
+ // If the argument is actually used, emit a load from the right stack
+ // slot.
+ if (!Op.Val-hasNUsesOfValue(0, ArgNo)) {
+int FI = MFI-CreateFixedObject(ObjSize, CurArgOffset);
+SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
+ DAG.getSrcValue(NULL));
+ } else {
+// Don't emit a dead load.
+ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
+ }
}
-if (ArgVal.Val == 0)
- ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
ArgValues.push_back(ArgVal);
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.174 - 1.175
---
Log message:
Simplify the argument counting logic by only incrementing the index.
---
Diffs of the changes: (+11 -14)
PPCISelLowering.cpp | 25 +++--
1 files changed, 11 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.174
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.175
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.174 Tue May 16 13:54:32 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:58:15 2006
@@ -738,9 +738,9 @@
SDOperand Root = Op.getOperand(0);
unsigned ArgOffset = 24;
- unsigned GPR_remaining = 8;
- unsigned FPR_remaining = 13;
- unsigned VR_remaining = 12;
+ const unsigned Num_GPR_Regs = 8;
+ const unsigned Num_FPR_Regs = 13;
+ const unsigned Num_VR_Regs = 12;
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
@@ -772,11 +772,10 @@
// All int arguments reserve stack space.
ArgOffset += 4;
- if (GPR_remaining 0) {
+ if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
---GPR_remaining;
++GPR_idx;
} else {
needsLoad = true;
@@ -789,12 +788,12 @@
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
- if (GPR_remaining 0) {
-unsigned delta = (GPR_remaining 1 ObjSize == 8) ? 2 : 1;
-GPR_remaining -= delta;
-GPR_idx += delta;
+ if (GPR_idx != Num_GPR_Regs) {
+++GPR_idx;
+if (ObjSize == 8 GPR_idx != Num_GPR_Regs)
+ ++GPR_idx;
}
- if (FPR_remaining 0) {
+ if (FPR_idx != Num_FPR_Regs) {
unsigned VReg;
if (ObjectVT == MVT::f32)
VReg = RegMap-createVirtualRegister(PPC::F4RCRegClass);
@@ -802,7 +801,6 @@
VReg = RegMap-createVirtualRegister(PPC::F8RCRegClass);
MF.addLiveIn(FPR[FPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
---FPR_remaining;
++FPR_idx;
} else {
needsLoad = true;
@@ -813,11 +811,10 @@
case MVT::v8i16:
case MVT::v16i8:
// Note that vector arguments in registers don't reserve stack space.
- if (VR_remaining 0) {
+ if (VR_idx != Num_VR_Regs) {
unsigned VReg = RegMap-createVirtualRegister(PPC::VRRCRegClass);
MF.addLiveIn(VR[VR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
---VR_remaining;
++VR_idx;
} else {
// This should be simple, but requires getting 16-byte aligned stack
@@ -857,7 +854,7 @@
// to their spots on the stack so that they may be loaded by deferencing
the
// result of va_next.
std::vectorSDOperand MemOps;
-for (; GPR_remaining 0; --GPR_remaining, ++GPR_idx) {
+for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
unsigned VReg = RegMap-createVirtualRegister(PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.175 - 1.176
PPCISelLowering.h updated: 1.48 - 1.49
---
Log message:
Instead of implementing LowerCallTo directly, let the default impl produce an
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
---
Diffs of the changes: (+147 -219)
PPCISelLowering.cpp | 358 +---
PPCISelLowering.h |8 -
2 files changed, 147 insertions(+), 219 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.175
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.176
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.175 Tue May 16 13:58:15 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 17:56:08 2006
@@ -877,6 +877,152 @@
return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
}
+static SDOperand LowerCALL(SDOperand Op, SelectionDAG DAG) {
+ SDOperand Chain = Op.getOperand(0);
+ unsigned CallingConv= castConstantSDNode(Op.getOperand(1))-getValue();
+ bool isVarArg = castConstantSDNode(Op.getOperand(2))-getValue() !=
0;
+ bool isTailCall = castConstantSDNode(Op.getOperand(3))-getValue() !=
0;
+ SDOperand Callee= Op.getOperand(4);
+
+ // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
+ // SelectExpr to use to put the arguments in the appropriate registers.
+ std::vectorSDOperand args_to_use;
+
+ // Count how many bytes are to be pushed on the stack, including the linkage
+ // area, and parameter passing area.
+ unsigned NumBytes = 24;
+
+ if (Op.getNumOperands() == 5) {
+Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, MVT::i32));
+ } else {
+for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i)
+ NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8;
+
+// Just to be safe, we'll always reserve the full 24 bytes of linkage area
+// plus 32 bytes of argument space in case any called code gets funky on
us.
+// (Required by ABI to support var arg)
+if (NumBytes 56) NumBytes = 56;
+
+// Adjust the stack pointer for the new arguments...
+// These operations are automatically eliminated by the prolog/epilog pass
+Chain = DAG.getCALLSEQ_START(Chain,
+ DAG.getConstant(NumBytes, MVT::i32));
+
+// Set up a copy of the stack pointer for use loading and storing any
+// arguments that may not fit in the registers available for argument
+// passing.
+SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
+
+// Figure out which arguments are going to go in registers, and which in
+// memory. Also, if this is a vararg function, floating point operations
+// must be stored to our stack, and loaded into integer regs as well, if
+// any integer regs are available for argument passing.
+unsigned ArgOffset = 24;
+unsigned GPR_remaining = 8;
+unsigned FPR_remaining = 13;
+
+std::vectorSDOperand MemOps;
+for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) {
+ SDOperand Arg = Op.getOperand(i);
+
+ // PtrOff will be used to store the current argument to the stack if a
+ // register cannot be found for it.
+ SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
+ switch (Arg.getValueType()) {
+ default: assert(0 Unexpected ValueType for argument!);
+ case MVT::i32:
+if (GPR_remaining 0) {
+ args_to_use.push_back(Arg);
+ --GPR_remaining;
+} else {
+ MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Arg, PtrOff, DAG.getSrcValue(NULL)));
+}
+ArgOffset += 4;
+break;
+ case MVT::f32:
+ case MVT::f64:
+if (FPR_remaining 0) {
+ args_to_use.push_back(Arg);
+ --FPR_remaining;
+ if (isVarArg) {
+SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ Arg, PtrOff,
+ DAG.getSrcValue(NULL));
+MemOps.push_back(Store);
+// Float varargs are always shadowed in available integer registers
+if (GPR_remaining 0) {
+ SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
+ DAG.getSrcValue(NULL));
+ MemOps.push_back(Load.getValue(1));
+ args_to_use.push_back(Load);
+ --GPR_remaining;
+}
+if (GPR_remaining 0 Arg.getValueType() == MVT::f64) {
+ SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
+
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.177 - 1.178
---
Log message:
3 changes, 2 of which are cleanup one of which changes codegen:
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC calling convention.
3. Only round up to 56-bytes of stack space for an outgoing call if the callee
is varargs. This saves a bit of stack space.
---
Diffs of the changes: (+112 -106)
PPCISelLowering.cpp | 218 ++--
1 files changed, 112 insertions(+), 106 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.177
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.178
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.177 Tue May 16 18:54:25 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 19:15:40 2006
@@ -889,120 +889,126 @@
std::vectorSDOperand args_to_use;
// Count how many bytes are to be pushed on the stack, including the linkage
- // area, and parameter passing area.
+ // area, and parameter passing area. We start with 24 bytes, which is
+ // prereserved space for [SP][CR][LR][3 x unused].
unsigned NumBytes = 24;
- if (Op.getNumOperands() == 5) {
-Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, MVT::i32));
- } else {
-for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i)
- NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8;
-
-// Just to be safe, we'll always reserve the full 24 bytes of linkage area
-// plus 32 bytes of argument space in case any called code gets funky on
us.
-// (Required by ABI to support var arg)
-if (NumBytes 56) NumBytes = 56;
-
-// Adjust the stack pointer for the new arguments...
-// These operations are automatically eliminated by the prolog/epilog pass
-Chain = DAG.getCALLSEQ_START(Chain,
- DAG.getConstant(NumBytes, MVT::i32));
-
-// Set up a copy of the stack pointer for use loading and storing any
-// arguments that may not fit in the registers available for argument
-// passing.
-SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
-
-// Figure out which arguments are going to go in registers, and which in
-// memory. Also, if this is a vararg function, floating point operations
-// must be stored to our stack, and loaded into integer regs as well, if
-// any integer regs are available for argument passing.
-unsigned ArgOffset = 24;
-unsigned GPR_remaining = 8;
-unsigned FPR_remaining = 13;
-unsigned VR_remaining = 12;
-
-std::vectorSDOperand MemOps;
-for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) {
- SDOperand Arg = Op.getOperand(i);
-
- // PtrOff will be used to store the current argument to the stack if a
- // register cannot be found for it.
- SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- switch (Arg.getValueType()) {
- default: assert(0 Unexpected ValueType for argument!);
- case MVT::i32:
-if (GPR_remaining 0) {
- args_to_use.push_back(Arg);
- --GPR_remaining;
-} else {
- MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Arg, PtrOff, DAG.getSrcValue(NULL)));
-}
-ArgOffset += 4;
-break;
- case MVT::f32:
- case MVT::f64:
-if (FPR_remaining 0) {
- args_to_use.push_back(Arg);
- --FPR_remaining;
- if (isVarArg) {
-SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Arg, PtrOff,
- DAG.getSrcValue(NULL));
-MemOps.push_back(Store);
-// Float varargs are always shadowed in available integer registers
-if (GPR_remaining 0) {
- SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
- DAG.getSrcValue(NULL));
- MemOps.push_back(Load.getValue(1));
- args_to_use.push_back(Load);
- --GPR_remaining;
-}
-if (GPR_remaining 0 Arg.getValueType() == MVT::f64) {
- SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
- SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
- DAG.getSrcValue(NULL));
- MemOps.push_back(Load.getValue(1));
- args_to_use.push_back(Load);
- --GPR_remaining;
-}
- } else {
-// If we have any FPRs remaining, we may also have GPRs remaining.
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.170 - 1.171
---
Log message:
Fit in 80 cols
---
Diffs of the changes: (+3 -3)
PPCISelLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.170
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.171
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.170 Fri May 12 16:09:57 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon May 15 23:20:24 2006
@@ -1307,7 +1307,7 @@
unsigned RHSID = (PFEntry 0) ((1 13)-1);
enum {
-OP_COPY = 0, // Copy, used for things like u,u,u,3 to say it is
0,1,2,3
+OP_COPY = 0, // Copy, used for things like u,u,u,3 to say it is
0,1,2,3
OP_VMRGHW,
OP_VMRGLW,
OP_VSPLTISW0,
@@ -1978,9 +1978,9 @@
// free GPRs, then we can pass both halves of the i64 in registers.
if (GPR_remaining 0) {
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
- Args[i].first, DAG.getConstant(1,
MVT::i32));
+ Args[i].first, DAG.getConstant(1,
MVT::i32));
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
- Args[i].first, DAG.getConstant(0,
MVT::i32));
+ Args[i].first, DAG.getConstant(0,
MVT::i32));
args_to_use.push_back(Hi);
--GPR_remaining;
if (GPR_remaining 0) {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.168 - 1.169 --- Log message: Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll --- Diffs of the changes: (+4 -0) PPCISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.168 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.169 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.168 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 28 16:56:10 2006 @@ -112,6 +112,10 @@ // PowerPC does not have truncstore for i1. setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); + // We cannot sextinreg(i1). Expand to shifts. + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + + // Support label based line numbers. setOperationAction(ISD::LOCATION, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.164 - 1.165
PPCISelLowering.h updated: 1.46 - 1.47
PPCInstrInfo.td updated: 1.215 - 1.216
README_ALTIVEC.txt updated: 1.29 - 1.30
---
Log message:
Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
---
Diffs of the changes: (+106 -24)
PPCISelLowering.cpp | 103
PPCISelLowering.h |9
PPCInstrInfo.td | 12 +-
README_ALTIVEC.txt |6 ---
4 files changed, 106 insertions(+), 24 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.164
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.165
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.164 Mon Apr 17 23:28:57 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 18 12:59:36 2006
@@ -246,6 +246,7 @@
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::SINT_TO_FP);
setTargetDAGCombine(ISD::STORE);
+ setTargetDAGCombine(ISD::BR_CC);
computeRegisterProperties();
}
@@ -1460,18 +1461,17 @@
return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
}
-/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
-/// lower, do it, otherwise return null.
-static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG DAG) {
- unsigned IntNo = castConstantSDNode(Op.getOperand(0))-getValue();
-
- // If this is a lowered altivec predicate compare, CompareOpc is set to the
- // opcode number of the comparison.
- int CompareOpc = -1;
- bool isDot = false;
- switch (IntNo) {
- default: return SDOperand();// Don't custom lower most intrinsics.
- // Comparison predicates.
+/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
+/// altivec comparison. If it is, return true and fill in Opc/isDot with
+/// information about the intrinsic.
+static bool getAltivecCompareInfo(SDOperand Intrin, int CompareOpc,
+ bool isDot) {
+ unsigned IntrinsicID =
castConstantSDNode(Intrin.getOperand(0))-getValue();
+ CompareOpc = -1;
+ isDot = false;
+ switch (IntrinsicID) {
+ default: return false;
+// Comparison predicates.
case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
@@ -1501,10 +1501,20 @@
case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
}
+ return true;
+}
+
+/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
+/// lower, do it, otherwise return null.
+static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG DAG) {
+ // If this is a lowered altivec predicate compare, CompareOpc is set to the
+ // opcode number of the comparison.
+ int CompareOpc;
+ bool isDot;
+ if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
+return SDOperand();// Don't custom lower most intrinsics.
- assert(CompareOpc0 We only lower altivec predicate compares so far!);
-
- // If this is a non-dot comparison, make the VCMP node.
+ // If this is a non-dot comparison, make the VCMP node and we are done.
if (!isDot) {
SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
Op.getOperand(1),
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.165 - 1.166 --- Log message: pretty print node name --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.165 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.166 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.165 Tue Apr 18 12:59:36 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 18 13:05:58 2006 @@ -275,6 +275,7 @@ case PPCISD::MFCR: return PPCISD::MFCR; case PPCISD::VCMP: return PPCISD::VCMP; case PPCISD::VCMPo: return PPCISD::VCMPo; + case PPCISD::COND_BRANCH: return PPCISD::COND_BRANCH; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.166 - 1.167
---
Log message:
Fix a crash on:
void foo2(vector float *A, vector float *B) {
vector float C = (vector float)vec_cmpeq(*A, *B);
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
*A = C;
}
---
Diffs of the changes: (+24 -2)
PPCISelLowering.cpp | 26 --
1 files changed, 24 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.166
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.167
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.166 Tue Apr 18 13:05:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 18 13:28:22 2006
@@ -2203,8 +2203,30 @@
break;
}
- // If there are non-zero uses of the flag value, use the VCMPo node!
- if (VCMPoNode !VCMPoNode-hasNUsesOfValue(0, 1))
+ // If there is no VCMPo node, or if the flag value has a single use,
don't
+ // transform this.
+ if (!VCMPoNode || VCMPoNode-hasNUsesOfValue(0, 1))
+break;
+
+ // Look at the (necessarily single) use of the flag value. If it has a
+ // chain, this transformation is more complex. Note that multiple things
+ // could use the value result, which we should ignore.
+ SDNode *FlagUser = 0;
+ for (SDNode::use_iterator UI = VCMPoNode-use_begin();
+ FlagUser == 0; ++UI) {
+assert(UI != VCMPoNode-use_end() Didn't find user!);
+SDNode *User = *UI;
+for (unsigned i = 0, e = User-getNumOperands(); i != e; ++i) {
+ if (User-getOperand(i) == SDOperand(VCMPoNode, 1)) {
+FlagUser = User;
+break;
+ }
+}
+ }
+
+ // If the user is a MFCR instruction, we know this is safe. Otherwise we
+ // give up for right now.
+ if (FlagUser-getOpcode() == PPCISD::MFCR)
return SDOperand(VCMPoNode, 0);
}
break;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.155 - 1.156
---
Log message:
Pull some code out into a helper function.
Effeciently codegen even splats in the range [-32,30].
This allows us to codegen 30,30,30,30 as:
vspltisw v0, 15
vadduwm v2, v0, v0
instead of as a cp load.
---
Diffs of the changes: (+26 -16)
PPCISelLowering.cpp | 42 ++
1 files changed, 26 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.155
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.156
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.155 Mon Apr 17 00:28:54 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 01:00:21 2006
@@ -1041,6 +1041,23 @@
return true;
}
+/// BuildSplatI - Build a canonical splati of Val with an element size of
+/// SplatSize. Cast the result to VT.
+static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
+ SelectionDAG DAG) {
+ assert(Val = -16 Val = 15 vsplti is out of range!);
+ static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
+MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
+ };
+ MVT::ValueType CanonicalVT = VTys[SplatSize-1];
+
+ // Build a canonical splat for this value.
+ SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
+ std::vectorSDOperand Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
+ SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
+ return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
+}
+
// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, and if it
// selects to a single instruction, return Op. Otherwise, if we can codegen
@@ -1079,23 +1096,16 @@
// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
int32_t SextVal= int32_t(SplatBits (32-8*SplatSize))
(32-8*SplatSize);
-if (SextVal = -16 SextVal = 15) {
- const MVT::ValueType VTys[] = { // canonical VT to use for each size.
-MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
- };
- MVT::ValueType CanonicalVT = VTys[SplatSize-1];
-
- // If this is a non-canonical splat for this value,
- if (Op.getValueType() != CanonicalVT || HasAnyUndefs) {
-SDOperand Elt = DAG.getConstant(SplatBits,
-MVT::getVectorBaseType(CanonicalVT));
-std::vectorSDOperand Ops(MVT::getVectorNumElements(CanonicalVT),
Elt);
-SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
-Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
- }
- return Op;
-}
+if (SextVal = -16 SextVal = 15)
+ return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
+// If this value is in the range [-32,30] and is even, use:
+//tmp = VSPLTI[bhw], result = add tmp, tmp
+if (SextVal = -32 SextVal = 30 (SextVal 1) == 0) {
+ Op = BuildSplatI(SextVal 1, SplatSize, Op.getValueType(), DAG);
+ return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
+}
+
// If this is 0x8000_ x 4, turn into vspltisw + vslw. If it is
// 0x7FFF_ x 4, turn it into not(0x8000_). These are important
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.156 - 1.157
---
Log message:
Learn how to make odd splatted constants in range [17,29]. This implements
PowerPC/vec_constants.ll:test_29.
---
Diffs of the changes: (+7 -0)
PPCISelLowering.cpp |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.156
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.157
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.156 Mon Apr 17 01:00:21 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 01:07:44 2006
@@ -1105,6 +1105,13 @@
Op = BuildSplatI(SextVal 1, SplatSize, Op.getValueType(), DAG);
return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
}
+// Otherwise, in range [17,29]: (vsplti 15) + (vsplti C).
+if (SextVal = 0 SextVal = 29) {
+ SDOperand LHS = BuildSplatI(15, SplatSize, Op.getValueType(), DAG);
+ SDOperand RHS = BuildSplatI(SextVal-15, SplatSize,
Op.getValueType(),DAG);
+ return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
+
+}
// If this is 0x8000_ x 4, turn into vspltisw + vslw. If it is
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.157 - 1.158
---
Log message:
Make some code more general, adding support for constant formation of several
new patterns.
---
Diffs of the changes: (+78 -22)
PPCISelLowering.cpp | 100
1 files changed, 78 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.157
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.158
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.157 Mon Apr 17 01:07:44 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 01:58:41 2006
@@ -1046,6 +1046,10 @@
static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
SelectionDAG DAG) {
assert(Val = -16 Val = 15 vsplti is out of range!);
+
+ // Force vspltis[hw] -1 to vspltisb -1.
+ if (Val == -1) SplatSize = 1;
+
static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
};
@@ -1058,6 +1062,14 @@
return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
}
+/// BuildIntrinsicBinOp - Return a binary operator intrinsic node with the
+/// specified intrinsic ID.
+static SDOperand BuildIntrinsicBinOp(unsigned IID, SDOperand LHS, SDOperand
RHS,
+ SelectionDAG DAG) {
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, LHS.getValueType(),
+ DAG.getConstant(IID, MVT::i32), LHS, RHS);
+}
+
// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, and if it
// selects to a single instruction, return Op. Otherwise, if we can codegen
@@ -1105,37 +1117,81 @@
Op = BuildSplatI(SextVal 1, SplatSize, Op.getValueType(), DAG);
return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
}
-// Otherwise, in range [17,29]: (vsplti 15) + (vsplti C).
-if (SextVal = 0 SextVal = 29) {
- SDOperand LHS = BuildSplatI(15, SplatSize, Op.getValueType(), DAG);
- SDOperand RHS = BuildSplatI(SextVal-15, SplatSize,
Op.getValueType(),DAG);
- return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
-
-}
-
// If this is 0x8000_ x 4, turn into vspltisw + vslw. If it is
-// 0x7FFF_ x 4, turn it into not(0x8000_). These are important
+// 0x7FFF_ x 4, turn it into not(0x8000_). This is important
// for fneg/fabs.
-if (SplatSize == 4
-SplatBits == 0x8000 || SplatBits == (0x7FFF~SplatUndef)) {
+if (SplatSize == 4 SplatBits == (0x7FFF~SplatUndef)) {
// Make -1 and vspltisw -1:
- SDOperand OnesI = DAG.getConstant(~0U, MVT::i32);
- SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
-OnesI, OnesI, OnesI, OnesI);
+ SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
// Make the VSLW intrinsic, computing 0x8000_.
- SDOperand Res
-= DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32,
- DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32),
- OnesV, OnesV);
-
- // If this is 0x7FFF_, xor by OnesV to invert it.
- if (SplatBits == 0x8000)
-Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
+ SDOperand Res = BuildIntrinsicBinOp(Intrinsic::ppc_altivec_vslw, OnesV,
+ OnesV, DAG);
+ // xor by OnesV to invert it.
+ Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
}
+
+// Check to see if this is a wide variety of vsplti*, binop self cases.
+unsigned SplatBitSize = SplatSize*8;
+static const char SplatCsts[] = {
+ -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
+ -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 14, -15
+};
+for (unsigned idx = 0; idx sizeof(SplatCsts)/sizeof(SplatCsts[0]);
++idx){
+ // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
+ // cases which are ambiguous (e.g. formation of 0x8000_). 'vsplti
-1'
+ int i = SplatCsts[idx];
+
+ // Figure out what shift amount will be used by altivec if shifted by i
in
+ // this splat size.
+ unsigned TypeShiftAmt = i (SplatBitSize-1);
+
+ // vsplti + shl self.
+ if (SextVal == (i (int)TypeShiftAmt)) {
+Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
+static const unsigned IIDs[] = { // Intrinsic to use for each size.
+ Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
+ Intrinsic::ppc_altivec_vslw
+};
+return BuildIntrinsicBinOp(IIDs[SplatSize-1], Op, Op, DAG);
+ }
+
+ // vsplti + srl self.
+ if (SextVal ==
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.158 - 1.159
---
Log message:
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
This implements vec_constants.ll:test_vsldoi and test_rol
---
Diffs of the changes: (+49 -15)
PPCISelLowering.cpp | 64 +++-
1 files changed, 49 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.158
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.159
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.158 Mon Apr 17 01:58:41 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 12:55:10 2006
@@ -1070,6 +1070,22 @@
DAG.getConstant(IID, MVT::i32), LHS, RHS);
}
+/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
+/// amount. The result has the specified value type.
+static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
+ MVT::ValueType VT, SelectionDAG DAG) {
+ // Force LHS/RHS to be the right type.
+ LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
+
+ std::vectorSDOperand Ops;
+ for (unsigned i = 0; i != 16; ++i)
+Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
+ SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
+DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
+ return DAG.getNode(ISD::BIT_CONVERT, VT, T);
+}
+
// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, and if it
// selects to a single instruction, return Op. Otherwise, if we can codegen
@@ -1179,11 +1195,34 @@
return BuildIntrinsicBinOp(IIDs[SplatSize-1], Op, Op, DAG);
}
- // TODO: ROL.
+ // vsplti + rol self.
+ if (SextVal == (int)(((unsigned)i TypeShiftAmt) |
+ ((unsigned)i (SplatBitSize-TypeShiftAmt {
+Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
+static const unsigned IIDs[] = { // Intrinsic to use for each size.
+ Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
+ Intrinsic::ppc_altivec_vrlw
+};
+return BuildIntrinsicBinOp(IIDs[SplatSize-1], Op, Op, DAG);
+ }
+
+ // t = vsplti c, result = vsldoi t, t, 1
+ if (SextVal == ((i 8) | (i (TypeShiftAmt-8 {
+SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
+return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
+ }
+ // t = vsplti c, result = vsldoi t, t, 2
+ if (SextVal == ((i 16) | (i (TypeShiftAmt-16 {
+SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
+return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
+ }
+ // t = vsplti c, result = vsldoi t, t, 3
+ if (SextVal == ((i 24) | (i (TypeShiftAmt-24 {
+SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
+return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
+ }
}
-
-
// Three instruction sequences.
// Otherwise, in range [17,29]: (vsplti 15) + (vsplti C).
@@ -1224,6 +1263,10 @@
return RHS;
}
+ SDOperand OpLHS, OpRHS;
+ OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
+ OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
+
unsigned ShufIdxs[16];
switch (OpNum) {
default: assert(0 Unknown i32 permute!);
@@ -1256,24 +1299,15 @@
ShufIdxs[i] = (i3)+12;
break;
case OP_VSLDOI4:
-for (unsigned i = 0; i != 16; ++i)
- ShufIdxs[i] = i+4;
-break;
+return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
case OP_VSLDOI8:
-for (unsigned i = 0; i != 16; ++i)
- ShufIdxs[i] = i+8;
-break;
+return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
case OP_VSLDOI12:
-for (unsigned i = 0; i != 16; ++i)
- ShufIdxs[i] = i+12;
-break;
+return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
}
std::vectorSDOperand Ops;
for (unsigned i = 0; i != 16; ++i)
Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
- SDOperand OpLHS, OpRHS;
- OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
- OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.159 - 1.160
---
Log message:
Make sure to check splats of every constant we can, handle splat(31) by
being a bit more clever, add support for odd splats from -31 to -17.
---
Diffs of the changes: (+14 -5)
PPCISelLowering.cpp | 19 ++-
1 files changed, 14 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.159
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.160
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.159 Mon Apr 17 12:55:10 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 13:09:22 2006
@@ -1127,6 +1127,9 @@
if (SextVal = -16 SextVal = 15)
return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
+
+// Two instruction sequences.
+
// If this value is in the range [-32,30] and is even, use:
//tmp = VSPLTI[bhw], result = add tmp, tmp
if (SextVal = -32 SextVal = 30 (SextVal 1) == 0) {
@@ -1154,7 +1157,7 @@
unsigned SplatBitSize = SplatSize*8;
static const char SplatCsts[] = {
-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
- -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 14, -15
+ -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
};
for (unsigned idx = 0; idx sizeof(SplatCsts)/sizeof(SplatCsts[0]);
++idx){
// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
@@ -1225,10 +1228,16 @@
// Three instruction sequences.
-// Otherwise, in range [17,29]: (vsplti 15) + (vsplti C).
-if (SextVal = 0 SextVal = 29) {
- SDOperand LHS = BuildSplatI(15, SplatSize, Op.getValueType(), DAG);
- SDOperand RHS = BuildSplatI(SextVal-15, SplatSize,
Op.getValueType(),DAG);
+// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
+if (SextVal = 0 SextVal = 31) {
+ SDOperand LHS = BuildSplatI(SextVal-16, SplatSize,
Op.getValueType(),DAG);
+ SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
+ return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
+}
+// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
+if (SextVal = -31 SextVal = 0) {
+ SDOperand LHS = BuildSplatI(SextVal+16, SplatSize,
Op.getValueType(),DAG);
+ SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
}
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.161 - 1.162
---
Log message:
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0:; 16 x ubyte
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
---
Diffs of the changes: (+51 -25)
PPCISelLowering.cpp | 76 ++--
1 files changed, 51 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.161
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.162
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.161 Mon Apr 17 22:24:30 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 22:43:48 2006
@@ -228,6 +228,7 @@
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
setOperationAction(ISD::MUL, MVT::v4i32, Custom);
+setOperationAction(ISD::MUL, MVT::v8i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
@@ -1573,31 +1574,56 @@
}
static SDOperand LowerMUL(SDOperand Op, SelectionDAG DAG) {
- assert(Op.getValueType() == MVT::v4i32 Unknown mul to lower!);
- SDOperand LHS = Op.getOperand(0);
- SDOperand RHS = Op.getOperand(1);
-
- SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
- SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
-
- SDOperand RHSSwap = // = vrlw RHS, 16
-BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
-
- // Shrinkify inputs to v8i16.
- LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
- RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
-
- // Low parts multiplied together, generating 32-bit results (we ignore the
top
- // parts).
- SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
- LHS, RHS, DAG, MVT::v4i32);
-
- SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
- LHS, RHSSwap, Zero, DAG, MVT::v4i32);
- // Shift the high parts up 16 bits.
- HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
- return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
+ if (Op.getValueType() == MVT::v4i32) {
+SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+
+SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
+SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift
amt.
+
+SDOperand RHSSwap = // = vrlw RHS, 16
+ BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
+
+// Shrinkify inputs to v8i16.
+LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
+RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
+RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
+
+// Low parts multiplied together, generating 32-bit results (we ignore the
+// top parts).
+SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
+LHS, RHS, DAG, MVT::v4i32);
+
+SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
+LHS, RHSSwap, Zero, DAG, MVT::v4i32);
+// Shift the high parts up 16 bits.
+HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
+return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
+ } else if (Op.getValueType() == MVT::v8i16) {
+SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+
+// Multiply the even 16-parts, producing 32-bit sums.
+SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleuh,
+ LHS, RHS, DAG, MVT::v4i32);
+EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, EvenParts);
+
+// Multiply the odd 16-parts, producing 32-bit sums.
+SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
+ LHS, RHS, DAG, MVT::v4i32);
+OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, OddParts);
+
+// Merge the results together.
+std::vectorSDOperand Ops;
+for (unsigned i = 0; i != 4; ++i) {
+ Ops.push_back(DAG.getConstant(2*i+1, MVT::i16));
+ Ops.push_back(DAG.getConstant(2*i+1+8, MVT::i16));
+}
+
+return
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.162 - 1.163
README_ALTIVEC.txt updated: 1.27 - 1.28
---
Log message:
Implement v16i8 multiply with this code:
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements CodeGen/PowerPC/vec_mul.ll. With this, v16i8 multiplies are
6.79x faster than before.
Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with
GCC.
Remove the 'integer multiplies' todo from the README file.
---
Diffs of the changes: (+25 -11)
PPCISelLowering.cpp | 27 +--
README_ALTIVEC.txt |9 -
2 files changed, 25 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.162
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.163
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.162 Mon Apr 17 22:43:48 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 22:57:35 2006
@@ -229,6 +229,7 @@
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
setOperationAction(ISD::MUL, MVT::v4i32, Custom);
setOperationAction(ISD::MUL, MVT::v8i16, Custom);
+setOperationAction(ISD::MUL, MVT::v16i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
@@ -1601,12 +1602,12 @@
} else if (Op.getValueType() == MVT::v8i16) {
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
-// Multiply the even 16-parts, producing 32-bit sums.
+// Multiply the even 16-bit parts, producing 32-bit sums.
SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleuh,
LHS, RHS, DAG, MVT::v4i32);
EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, EvenParts);
-// Multiply the odd 16-parts, producing 32-bit sums.
+// Multiply the odd 16-bit parts, producing 32-bit sums.
SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
LHS, RHS, DAG, MVT::v4i32);
OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, OddParts);
@@ -1620,6 +1621,28 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, EvenParts, OddParts,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v8i16, Ops));
+ } else if (Op.getValueType() == MVT::v16i8) {
+SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
+
+// Multiply the even 8-bit parts, producing 16-bit sums.
+SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
+ LHS, RHS, DAG, MVT::v8i16);
+EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
+
+// Multiply the odd 8-bit parts, producing 16-bit sums.
+SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
+ LHS, RHS, DAG, MVT::v8i16);
+OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
+
+// Merge the results together.
+std::vectorSDOperand Ops;
+for (unsigned i = 0; i != 8; ++i) {
+ Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
+ Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
+}
+
+return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
+ DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
} else {
assert(0 Unknown mul to lower!);
abort();
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.27
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.28
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.27 Mon Apr 17 16:52:03 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Mon Apr 17 22:57:35 2006
@@ -75,15 +75,6 @@
//===--===//
-Implement multiply for vector integer types, to avoid the horrible scalarized
-code produced by legalize.
-
-void test(vector int *X, vector int *Y) {
- *X = *X * *Y;
-}
-
-//===--===//
-
extract_vector_elt of an arbitrary constant vector can be done with the
following instructions:
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.163 - 1.164
---
Log message:
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
even/odd halves. Thanks to Nate telling me what's what.
---
Diffs of the changes: (+3 -18)
PPCISelLowering.cpp | 21 +++--
1 files changed, 3 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.163
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.164
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.163 Mon Apr 17 22:57:35 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 23:28:57 2006
@@ -1602,25 +1602,10 @@
} else if (Op.getValueType() == MVT::v8i16) {
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
-// Multiply the even 16-bit parts, producing 32-bit sums.
-SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleuh,
- LHS, RHS, DAG, MVT::v4i32);
-EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, EvenParts);
-
-// Multiply the odd 16-bit parts, producing 32-bit sums.
-SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
- LHS, RHS, DAG, MVT::v4i32);
-OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, OddParts);
+SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
-// Merge the results together.
-std::vectorSDOperand Ops;
-for (unsigned i = 0; i != 4; ++i) {
- Ops.push_back(DAG.getConstant(2*i+1, MVT::i16));
- Ops.push_back(DAG.getConstant(2*i+1+8, MVT::i16));
-}
-
-return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, EvenParts, OddParts,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v8i16, Ops));
+return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
+LHS, RHS, Zero, DAG);
} else if (Op.getValueType() == MVT::v16i8) {
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.154 - 1.155
README_ALTIVEC.txt updated: 1.24 - 1.25
---
Log message:
Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll
---
Diffs of the changes: (+135 -14)
PPCISelLowering.cpp | 137 +++-
README_ALTIVEC.txt | 10 ---
2 files changed, 135 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.154
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.155
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.154 Sat Apr 15 20:37:57 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 17 00:28:54 2006
@@ -13,6 +13,7 @@
#include PPCISelLowering.h
#include PPCTargetMachine.h
+#include PPCPerfectShuffle.h
#include llvm/ADT/VectorExtras.h
#include llvm/Analysis/ScalarEvolutionExpressions.h
#include llvm/CodeGen/MachineFrameInfo.h
@@ -1123,6 +1124,88 @@
return SDOperand();
}
+/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
+/// the specified operations to build the shuffle.
+static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
+SDOperand RHS, SelectionDAG DAG) {
+ unsigned OpNum = (PFEntry 26) 0x0F;
+ unsigned LHSID = (PFEntry 13) ((1 13)-1);
+ unsigned RHSID = (PFEntry 0) ((1 13)-1);
+
+ enum {
+OP_COPY = 0, // Copy, used for things like u,u,u,3 to say it is
0,1,2,3
+OP_VMRGHW,
+OP_VMRGLW,
+OP_VSPLTISW0,
+OP_VSPLTISW1,
+OP_VSPLTISW2,
+OP_VSPLTISW3,
+OP_VSLDOI4,
+OP_VSLDOI8,
+OP_VSLDOI12,
+ };
+
+ if (OpNum == OP_COPY) {
+if (LHSID == (1*9+2)*9+3) return LHS;
+assert(LHSID == ((4*9+5)*9+6)*9+7 Illegal OP_COPY!);
+return RHS;
+ }
+
+ unsigned ShufIdxs[16];
+ switch (OpNum) {
+ default: assert(0 Unknown i32 permute!);
+ case OP_VMRGHW:
+ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
+ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
+ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
+ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
+break;
+ case OP_VMRGLW:
+ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
+ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
+ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
+ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
+break;
+ case OP_VSPLTISW0:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = (i3)+0;
+break;
+ case OP_VSPLTISW1:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = (i3)+4;
+break;
+ case OP_VSPLTISW2:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = (i3)+8;
+break;
+ case OP_VSPLTISW3:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = (i3)+12;
+break;
+ case OP_VSLDOI4:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = i+4;
+break;
+ case OP_VSLDOI8:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = i+8;
+break;
+ case OP_VSLDOI12:
+for (unsigned i = 0; i != 16; ++i)
+ ShufIdxs[i] = i+12;
+break;
+ }
+ std::vectorSDOperand Ops;
+ for (unsigned i = 0; i != 16; ++i)
+Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
+ SDOperand OpLHS, OpRHS;
+ OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
+ OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
+
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
+ DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
+}
+
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
/// is a shuffle we can handle in a single instruction, return it. Otherwise,
/// return the code it can be lowered into. Worst case, it can always be
@@ -1166,8 +1249,58 @@
PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
return Op;
- // TODO: Handle more cases, and also handle cases that are cheaper to do as
- // multiple such instructions than as a constant pool load/vperm pair.
+ // Check to see if this is a shuffle of 4-byte values. If so, we can use our
+ // perfect shuffle table to emit an optimal matching sequence.
+ unsigned PFIndexes[4];
+ bool isFourElementShuffle = true;
+ for (unsigned i = 0; i != 4 isFourElementShuffle; ++i) { // Element number
+unsigned EltNo = 8; // Start out undef.
+for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
+ if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
+continue; // Undef,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.151 - 1.152
---
Log message:
Fix a crash when faced with a shuffle vector that has an undef in its mask.
---
Diffs of the changes: (+5 -1)
PPCISelLowering.cpp |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.151
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.152
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.151 Fri Apr 14 18:19:08 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 15 18:48:05 2006
@@ -1116,7 +1116,11 @@
std::vectorSDOperand ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
-unsigned SrcElt =castConstantSDNode(PermMask.getOperand(i))-getValue();
+unsigned SrcElt;
+if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
+ SrcElt = 0;
+else
+ SrcElt = castConstantSDNode(PermMask.getOperand(i))-getValue();
for (unsigned j = 0; j != BytesPerElement; ++j)
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrAltivec.td README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.153 - 1.154
PPCInstrAltivec.td updated: 1.50 - 1.51
README_ALTIVEC.txt updated: 1.23 - 1.24
---
Log message:
Implement a TODO: have the legalizer canonicalize a bunch of operations to
one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.
---
Diffs of the changes: (+32 -68)
PPCISelLowering.cpp | 33 -
PPCInstrAltivec.td | 47 ++-
README_ALTIVEC.txt | 20 ++--
3 files changed, 32 insertions(+), 68 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.153
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.154
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.153 Sat Apr 15 20:01:29 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 15 20:37:57 2006
@@ -87,10 +87,6 @@
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::f64, Expand);
- setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
- setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
- setOperationAction(ISD::SELECT, MVT::v8i16, Expand);
- setOperationAction(ISD::SELECT, MVT::v16i8, Expand);
// PowerPC wants to turn select_cc of FP into fsel when possible.
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
@@ -178,17 +174,29 @@
// will selectively turn on ones that can be effectively codegen'd.
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
- // add/sub/and/or/xor are legal for all supported vector VT's.
+ // add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
- setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
- setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal);
- setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
// We promote all shuffles to v16i8.
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
- AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
+ AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
+
+ // We promote all non-typed operations to v4i32.
+ setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
+ AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
+ setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
+ AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v4i32);
+ setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
+ AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
+ setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
+ AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
+ setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
+ AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
+ setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
+ AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
+ // No other operations are legal.
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
@@ -205,6 +213,13 @@
// with merges, splats, etc.
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
+setOperationAction(ISD::AND , MVT::v4i32, Legal);
+setOperationAction(ISD::OR, MVT::v4i32, Legal);
+setOperationAction(ISD::XOR , MVT::v4i32, Legal);
+setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
+setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
+setOperationAction(ISD::STORE , MVT::v4i32, Legal);
+
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.50
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.51
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.50 Sat Apr 15 18:45:24 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Apr 15 20:37:57 2006
@@ -158,7 +158,7 @@
// Instruction Definitions.
def IMPLICIT_DEF_VRRC : Pseudo(ops VRRC:$rD), ; $rD = IMPLICIT_DEF_VRRC,
- [(set VRRC:$rD, (v4f32 (undef)))];
+ [(set VRRC:$rD, (v4i32 (undef)))];
let noResults = 1 in {
def DSS : DSS_Form822, (ops u5imm:$A,
u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
@@ -541,25 +541,16 @@
(DSTST 1,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.149 - 1.150
---
Log message:
Move the rest of the PPCTargetLowering::LowerOperation cases out into
separate functions, for simplicity and code clarity.
---
Diffs of the changes: (+531 -470)
PPCISelLowering.cpp | 1001 +++-
1 files changed, 531 insertions(+), 470 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.149
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.150
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.149 Fri Apr 14 00:19:18 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 14 01:01:58 2006
@@ -258,6 +258,10 @@
}
}
+//===--===//
+// Node matching predicates, for use by the tblgen matching code.
+//===--===//
+
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_castConstantFPSDNode(Op))
@@ -544,6 +548,388 @@
return SDOperand();
}
+//===--===//
+// LowerOperation implementation
+//===--===//
+
+static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG DAG) {
+ ConstantPoolSDNode *CP = castConstantPoolSDNode(Op);
+ Constant *C = CP-get();
+ SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP-getAlignment());
+ SDOperand Zero = DAG.getConstant(0, MVT::i32);
+
+ const TargetMachine TM = DAG.getTarget();
+
+ // If this is a non-darwin platform, we don't support non-static relo models
+ // yet.
+ if (TM.getRelocationModel() == Reloc::Static ||
+ !TM.getSubtargetPPCSubtarget().isDarwin()) {
+// Generate non-pic code that has direct accesses to the constant pool.
+// The address of the global is just (hi(g)+lo(g)).
+SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+ }
+
+ SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+ if (TM.getRelocationModel() == Reloc::PIC) {
+// With PIC, the first instruction is actually GR+hi(G).
+Hi = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
+ }
+
+ SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+ Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+ return Lo;
+}
+
+static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG DAG) {
+ GlobalAddressSDNode *GSDN = castGlobalAddressSDNode(Op);
+ GlobalValue *GV = GSDN-getGlobal();
+ SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN-getOffset());
+ SDOperand Zero = DAG.getConstant(0, MVT::i32);
+
+ const TargetMachine TM = DAG.getTarget();
+
+ // If this is a non-darwin platform, we don't support non-static relo models
+ // yet.
+ if (TM.getRelocationModel() == Reloc::Static ||
+ !TM.getSubtargetPPCSubtarget().isDarwin()) {
+// Generate non-pic code that has direct accesses to globals.
+// The address of the global is just (hi(g)+lo(g)).
+SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
+SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
+return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+ }
+
+ SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
+ if (TM.getRelocationModel() == Reloc::PIC) {
+// With PIC, the first instruction is actually GR+hi(G).
+Hi = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
+ }
+
+ SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
+ Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+
+ if (!GV-hasWeakLinkage() !GV-hasLinkOnceLinkage()
+ (!GV-isExternal() || GV-hasNotBeenReadFromBytecode()))
+return Lo;
+
+ // If the global is weak or external, we have to go through the lazy
+ // resolution stub.
+ return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
+}
+
+static SDOperand LowerSETCC(SDOperand Op, SelectionDAG DAG) {
+ ISD::CondCode CC = castCondCodeSDNode(Op.getOperand(2))-get();
+
+ // If we're comparing for equality to zero, expose the fact that this is
+ // implented as a ctlz/srl pair on ppc, so that the dag combiner can
+ // fold the new nodes.
+ if (ConstantSDNode *C = dyn_castConstantSDNode(Op.getOperand(1))) {
+if (C-isNullValue() CC == ISD::SETEQ) {
+ MVT::ValueType VT = Op.getOperand(0).getValueType();
+ SDOperand Zext = Op.getOperand(0);
+ if (VT MVT::i32) {
+VT = MVT::i32;
+Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
+ }
+ unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.150 - 1.151
---
Log message:
Allow undef in a shuffle mask
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.150
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.151
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.150 Fri Apr 14 01:01:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 14 18:19:08 2006
@@ -416,6 +416,7 @@
assert(isaConstantSDNode(Elt) Invalid VECTOR_SHUFFLE mask!);
for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
+if (N-getOperand(i).getOpcode() == ISD::UNDEF) continue;
assert(isaConstantSDNode(N-getOperand(i))
Invalid VECTOR_SHUFFLE mask!);
for (unsigned j = 0; j != EltSize; ++j)
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.144 - 1.145
PPCInstrAltivec.td updated: 1.47 - 1.48
---
Log message:
Ensure that zero vectors are always v4i32, which forces them to CSE with
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
---
Diffs of the changes: (+13 -8)
PPCISelLowering.cpp | 14 +++---
PPCInstrAltivec.td |7 ++-
2 files changed, 13 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.144
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.145
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.144 Mon Apr 10 20:38:39 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 12 11:53:28 2006
@@ -923,11 +923,19 @@
case ISD::BUILD_VECTOR:
// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, return Op.
-
-// See if this is all zeros.
+
// FIXME: We should handle splat(-0.0), and other cases here.
-if (ISD::isBuildVectorAllZeros(Op.Val))
+
+// See if this is all zeros.
+if (ISD::isBuildVectorAllZeros(Op.Val)) {
+ // Canonicalize all zero vectors to be v4i32.
+ if (Op.getValueType() != MVT::v4i32) {
+SDOperand Z = DAG.getConstant(0, MVT::i32);
+Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
+Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
+ }
return Op;
+}
if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val ||// vspltisb
PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val ||// vspltish
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.47
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.48
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.47 Sat Apr 8 01:46:53 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 12 11:53:28 2006
@@ -521,7 +521,7 @@
def V_SET0 : VXForm_setzero1220, (ops VRRC:$vD),
vxor $vD, $vD, $vD, VecFP,
- [(set VRRC:$vD, (v4f32 immAllZerosV))];
+ [(set VRRC:$vD, (v4i32 immAllZerosV))];
}
//===--===//
@@ -544,9 +544,6 @@
def : Pat(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC));
def : Pat(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC));
def : Pat(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC));
-def : Pat(v16i8 immAllZerosV), (v16i8 (V_SET0));
-def : Pat(v8i16 immAllZerosV), (v8i16 (V_SET0));
-def : Pat(v4i32 immAllZerosV), (v4i32 (V_SET0));
// Loads.
def : Pat(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src));
@@ -637,7 +634,7 @@
(v8i16 (VANDC VRRC:$A, VRRC:$B));
def : Pat(fmul VRRC:$vA, VRRC:$vB),
- (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0));
+ (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)));
// Fused multiply add and multiply sub for packed float. These are represented
// separately from the real instructions above, for operations that must have
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.145 - 1.146
PPCISelLowering.h updated: 1.45 - 1.46
PPCInstrAltivec.td updated: 1.48 - 1.49
---
Log message:
Rename get_VSPLI_elt - get_VSPLTI_elt
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
---
Diffs of the changes: (+40 -32)
PPCISelLowering.cpp | 35 ---
PPCISelLowering.h |4 ++--
PPCInstrAltivec.td | 33 ++---
3 files changed, 40 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.145
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.146
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.145 Wed Apr 12 11:53:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 12 12:37:20 2006
@@ -429,11 +429,11 @@
return castConstantSDNode(N-getOperand(0))-getValue() / EltSize;
}
-/// get_VSPLI_elt - If this is a build_vector of constants which can be formed
+/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
/// by using a vspltis[bhw] instruction of the specified element size, return
/// the constant being splatted. The ByteSize field indicates the number of
/// bytes of each element [124] - [bhw].
-SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG DAG) {
+SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG DAG)
{
SDOperand OpVal(0, 0);
// If ByteSize of the splat is bigger than the element size of the
@@ -920,7 +920,7 @@
// Load it out.
return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
}
- case ISD::BUILD_VECTOR:
+ case ISD::BUILD_VECTOR: {
// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, return Op.
@@ -937,13 +937,34 @@
return Op;
}
-if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val ||// vspltisb
-PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val ||// vspltish
-PPC::get_VSPLI_elt(Op.Val, 4, DAG).Val) // vspltisw
+// Check to see if this is something we can use VSPLTI* to form.
+MVT::ValueType CanonicalVT = MVT::Other;
+SDNode *CST = 0;
+
+if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw
+ CanonicalVT = MVT::v4i32;
+else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish
+ CanonicalVT = MVT::v8i16;
+else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb
+ CanonicalVT = MVT::v16i8;
+
+// If this matches one of the vsplti* patterns, force it to the canonical
+// type for the pattern.
+if (CST) {
+ if (Op.getValueType() != CanonicalVT) {
+// Convert the splatted element to the right element type.
+SDOperand Elt = DAG.getNode(ISD::TRUNCATE,
+MVT::getVectorBaseType(CanonicalVT),
+SDOperand(CST, 0));
+std::vectorSDOperand Ops(MVT::getVectorNumElements(CanonicalVT),
Elt);
+SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
+Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ }
return Op;
+}
return SDOperand();
-
+ }
case ISD::VECTOR_SHUFFLE: {
SDOperand V1 = Op.getOperand(0);
SDOperand V2 = Op.getOperand(1);
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.45
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.46
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.45 Sat Apr 8 01:46:53 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Wed Apr 12 12:37:20 2006
@@ -131,11 +131,11 @@
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
-/// get_VSPLI_elt - If this is a build_vector of constants which can be
+/// get_VSPLTI_elt - If this is a build_vector of constants which can be
/// formed by using a vspltis[bhw] instruction of the specified element
/// size, return the constant being splatted. The ByteSize field indicates
/// the number of bytes of each element [124] - [bhw].
-SDOperand get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG DAG);
+SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG DAG);
}
class PPCTargetLowering : public TargetLowering {
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.48
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.49
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.48 Wed Apr 12 11:53:28 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 12
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.146 - 1.147
README_ALTIVEC.txt updated: 1.20 - 1.21
---
Log message:
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFF) and spltw(0x8000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 = (vi){0x8000,0x8000,0x8000,0x8000};
*P2 = (vi){0x7FFF,0x7FFF,0x7FFF,0x7FFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256: http://llvm.cs.uiuc.edu/PR256 ,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256: http://llvm.cs.uiuc.edu/PR256 ,r12
blr
---
Diffs of the changes: (+91 -7)
PPCISelLowering.cpp | 89 +---
README_ALTIVEC.txt |9 +++--
2 files changed, 91 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.146
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.147
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.146 Wed Apr 12 12:37:20 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 12 14:07:14 2006
@@ -544,6 +544,48 @@
return SDOperand();
}
+// If this is a vector of constants or undefs, get the bits. A bit in
+// UndefBits is set if the corresponding element of the vector is an
+// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
+// zero. Return true if this is not an array of constants, false if it is.
+//
+// Note that VectorBits/UndefBits are returned in 'little endian' form, so
+// elements 0,1 go in VectorBits[0] and 2,3 go in VectorBits[1] for a v4i32.
+static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
+ uint64_t UndefBits[2]) {
+ // Start with zero'd results.
+ VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
+
+ unsigned EltBitSize = MVT::getSizeInBits(BV-getOperand(0).getValueType());
+ for (unsigned i = 0, e = BV-getNumOperands(); i != e; ++i) {
+SDOperand OpVal = BV-getOperand(i);
+
+unsigned PartNo = i = e/2; // In the upper 128 bits?
+unsigned SlotNo = i (e/2-1); // Which subpiece of the uint64_t it is.
+
+uint64_t EltBits = 0;
+if (OpVal.getOpcode() == ISD::UNDEF) {
+ uint64_t EltUndefBits = ~0U (32-EltBitSize);
+ UndefBits[PartNo] |= EltUndefBits (SlotNo*EltBitSize);
+ continue;
+} else if (ConstantSDNode *CN = dyn_castConstantSDNode(OpVal)) {
+ EltBits = CN-getValue() (~0U (32-EltBitSize));
+} else if (ConstantFPSDNode *CN = dyn_castConstantFPSDNode(OpVal)) {
+ assert(CN-getValueType(0) == MVT::f32
+ Only one legal FP vector type!);
+ EltBits = FloatToBits(CN-getValue());
+} else {
+ // Nonconstant element.
+ return true;
+}
+
+VectorBits[PartNo] |= EltBits (SlotNo*EltBitSize);
+ }
+
+ //printf(%llx %llx %llx %llx\n,
+ // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
+ return false;
+}
/// LowerOperation - Provide custom lowering hooks for some operations.
///
@@ -922,12 +964,20 @@
}
case ISD::BUILD_VECTOR: {
// If this is a case we can't handle, return null and let the default
-//
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.138 - 1.139
PPCISelLowering.h updated: 1.44 - 1.45
PPCInstrAltivec.td updated: 1.46 - 1.47
---
Log message:
Change the interface to the predicate that determines if vsplti* can be used.
No functionality changes.
---
Diffs of the changes: (+28 -32)
PPCISelLowering.cpp | 33 +
PPCISelLowering.h |9 +
PPCInstrAltivec.td | 18 ++
3 files changed, 28 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.138
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.138 Thu Apr 6 18:12:19 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 01:46:53 2006
@@ -425,10 +425,11 @@
return castConstantSDNode(N-getOperand(0))-getValue() / EltSize;
}
-/// isVecSplatImm - Return true if this is a build_vector of constants which
-/// can be formed by using a vspltis[bhw] instruction. The ByteSize field
-/// indicates the number of bytes of each element [124] - [bhw].
-bool PPC::isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val) {
+/// get_VSPLI_elt - If this is a build_vector of constants which can be formed
+/// by using a vspltis[bhw] instruction of the specified element size, return
+/// the constant being splatted. The ByteSize field indicates the number of
+/// bytes of each element [124] - [bhw].
+SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG DAG) {
SDOperand OpVal(0, 0);
// Check to see if this buildvec has a single non-undef value in its
elements.
for (unsigned i = 0, e = N-getNumOperands(); i != e; ++i) {
@@ -436,10 +437,10 @@
if (OpVal.Val == 0)
OpVal = N-getOperand(i);
else if (OpVal != N-getOperand(i))
- return false;
+ return SDOperand();
}
- if (OpVal.Val == 0) return false; // All UNDEF: use implicit def.
+ if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
unsigned ValSizeInBytes = 0;
uint64_t Value = 0;
@@ -455,7 +456,7 @@
// If the splat value is larger than the element value, then we can never do
// this splat. The only case that we could fit the replicated bits into our
// immediate field for would be zero, and we prefer to use vxor for it.
- if (ValSizeInBytes ByteSize) return false;
+ if (ValSizeInBytes ByteSize) return SDOperand();
// If the element value is larger than the splat value, cut it in half and
// check to see if the two halves are equal. Continue doing this until we
@@ -466,7 +467,7 @@
// If the top half equals the bottom half, we're still ok.
if (((Value (ValSizeInBytes*8)) ((1 (8*ValSizeInBytes))-1)) !=
(Value ((1 (8*ValSizeInBytes))-1)))
- return false;
+ return SDOperand();
}
// Properly sign extend the value.
@@ -474,12 +475,12 @@
int MaskVal = ((int)Value ShAmt) ShAmt;
// If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
- if (MaskVal == 0) return false;
+ if (MaskVal == 0) return SDOperand();
- if (Val) *Val = MaskVal;
-
- // Finally, if this value fits in a 5 bit sext field, return true.
- return ((MaskVal (32-5)) (32-5)) == MaskVal;
+ // Finally, if this value fits in a 5 bit sext field, return it
+ if (((MaskVal (32-5)) (32-5)) == MaskVal)
+return DAG.getTargetConstant(MaskVal, MVT::i32);
+ return SDOperand();
}
@@ -849,9 +850,9 @@
if (ISD::isBuildVectorAllZeros(Op.Val))
return Op;
-if (PPC::isVecSplatImm(Op.Val, 1) ||// vspltisb
-PPC::isVecSplatImm(Op.Val, 2) ||// vspltish
-PPC::isVecSplatImm(Op.Val, 4)) // vspltisw
+if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val ||// vspltisb
+PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val ||// vspltish
+PPC::get_VSPLI_elt(Op.Val, 4, DAG).Val) // vspltisw
return Op;
return SDOperand();
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.44
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.45
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.44 Thu Apr 6 17:28:36 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sat Apr 8 01:46:53 2006
@@ -131,10 +131,11 @@
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
-/// isVecSplatImm - Return true if this is a build_vector of constants
which
-/// can be formed by using a vspltis[bhw] instruction. The ByteSize field
-/// indicates the number of bytes of each element [124] - [bhw].
-bool isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val = 0);
+/// get_VSPLI_elt - If this is a build_vector of constants which can be
+/// formed by using a vspltis[bhw] instruction of the specified element
+/// size, return
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.139 - 1.140
---
Log message:
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
constant pool load.
---
Diffs of the changes: (+57 -0)
PPCISelLowering.cpp | 57
1 files changed, 57 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139 Sat Apr 8 01:46:53 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 02:14:26 2006
@@ -431,6 +431,63 @@
/// bytes of each element [124] - [bhw].
SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG DAG) {
SDOperand OpVal(0, 0);
+
+ // If ByteSize of the splat is bigger than the element size of the
+ // build_vector, then we have a case where we are checking for a splat where
+ // multiple elements of the buildvector are folded together into a single
+ // logical element of the splat (e.g. vsplish 1 to splat {0,1}*8).
+ unsigned EltSize = 16/N-getNumOperands();
+ if (EltSize ByteSize) {
+unsigned Multiple = ByteSize/EltSize; // Number of BV entries per
spltval.
+SDOperand UniquedVals[4];
+assert(Multiple 1 Multiple = 4 How can this happen?);
+
+// See if all of the elements in the buildvector agree across.
+for (unsigned i = 0, e = N-getNumOperands(); i != e; ++i) {
+ if (N-getOperand(i).getOpcode() == ISD::UNDEF) continue;
+ // If the element isn't a constant, bail fully out.
+ if (!isaConstantSDNode(N-getOperand(i))) return SDOperand();
+
+
+ if (UniquedVals[i(Multiple-1)].Val == 0)
+UniquedVals[i(Multiple-1)] = N-getOperand(i);
+ else if (UniquedVals[i(Multiple-1)] != N-getOperand(i))
+return SDOperand(); // no match.
+}
+
+// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
+// either constant or undef values that are identical for each chunk. See
+// if these chunks can form into a larger vspltis*.
+
+// Check to see if all of the leading entries are either 0 or -1. If
+// neither, then this won't fit into the immediate field.
+bool LeadingZero = true;
+bool LeadingOnes = true;
+for (unsigned i = 0; i != Multiple-1; ++i) {
+ if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
+
+ LeadingZero = castConstantSDNode(UniquedVals[i])-isNullValue();
+ LeadingOnes = castConstantSDNode(UniquedVals[i])-isAllOnesValue();
+}
+// Finally, check the least significant entry.
+if (LeadingZero) {
+ if (UniquedVals[Multiple-1].Val == 0)
+return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
+ int Val = castConstantSDNode(UniquedVals[Multiple-1])-getValue();
+ if (Val 16)
+return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 - vspltisw(4)
+}
+if (LeadingOnes) {
+ if (UniquedVals[Multiple-1].Val == 0)
+return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
+ int Val
=castConstantSDNode(UniquedVals[Multiple-1])-getSignExtended();
+ if (Val = -16)// -1,-1,-1,-2 - vspltisw(-2)
+return DAG.getTargetConstant(Val, MVT::i32);
+}
+
+return SDOperand();
+ }
+
// Check to see if this buildvec has a single non-undef value in its
elements.
for (unsigned i = 0, e = N-getNumOperands(); i != e; ++i) {
if (N-getOperand(i).getOpcode() == ISD::UNDEF) continue;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.141 - 1.142 --- Log message: properly mark vector selects as expanded to select_cc --- Diffs of the changes: (+4 -0) PPCISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 Sat Apr 8 17:45:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 17:59:15 2006 @@ -87,6 +87,10 @@ setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::f64, Expand); + setOperationAction(ISD::SELECT, MVT::v4f32, Expand); + setOperationAction(ISD::SELECT, MVT::v4i32, Expand); + setOperationAction(ISD::SELECT, MVT::v8i16, Expand); + setOperationAction(ISD::SELECT, MVT::v16i8, Expand); // PowerPC wants to turn select_cc of FP into fsel when possible. setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.132 - 1.133
PPCISelLowering.h updated: 1.39 - 1.40
PPCInstrAltivec.td updated: 1.41 - 1.42
---
Log message:
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
vperm with a perm mask lvx'd from the constant pool.
---
Diffs of the changes: (+75 -2)
PPCISelLowering.cpp | 54
PPCISelLowering.h |8 +++
PPCInstrAltivec.td | 15 --
3 files changed, 75 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.132
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.133
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.132 Wed Apr 5 12:39:25 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 12:23:16 2006
@@ -267,6 +267,56 @@
return false;
}
+/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
+/// true if Op is undef or if it matches the specified value.
+static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
+ return Op.getOpcode() == ISD::UNDEF ||
+ castConstantSDNode(Op)-getValue() == Val;
+}
+
+/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
+/// VPKUHUM instruction.
+bool PPC::isVPKUHUMShuffleMask(SDNode *N) {
+ return isConstantOrUndef(N-getOperand( 0), 1)
+ isConstantOrUndef(N-getOperand( 1), 3)
+ isConstantOrUndef(N-getOperand( 2), 5)
+ isConstantOrUndef(N-getOperand( 3), 7)
+ isConstantOrUndef(N-getOperand( 4), 9)
+ isConstantOrUndef(N-getOperand( 5), 11)
+ isConstantOrUndef(N-getOperand( 6), 13)
+ isConstantOrUndef(N-getOperand( 7), 15)
+ isConstantOrUndef(N-getOperand( 8), 17)
+ isConstantOrUndef(N-getOperand( 9), 19)
+ isConstantOrUndef(N-getOperand(10), 21)
+ isConstantOrUndef(N-getOperand(11), 23)
+ isConstantOrUndef(N-getOperand(12), 25)
+ isConstantOrUndef(N-getOperand(13), 27)
+ isConstantOrUndef(N-getOperand(14), 29)
+ isConstantOrUndef(N-getOperand(15), 31);
+}
+
+/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
+/// VPKUWUM instruction.
+bool PPC::isVPKUWUMShuffleMask(SDNode *N) {
+ return isConstantOrUndef(N-getOperand( 0), 2)
+ isConstantOrUndef(N-getOperand( 1), 3)
+ isConstantOrUndef(N-getOperand( 2), 6)
+ isConstantOrUndef(N-getOperand( 3), 7)
+ isConstantOrUndef(N-getOperand( 4), 10)
+ isConstantOrUndef(N-getOperand( 5), 11)
+ isConstantOrUndef(N-getOperand( 6), 14)
+ isConstantOrUndef(N-getOperand( 7), 15)
+ isConstantOrUndef(N-getOperand( 8), 18)
+ isConstantOrUndef(N-getOperand( 9), 19)
+ isConstantOrUndef(N-getOperand(10), 22)
+ isConstantOrUndef(N-getOperand(11), 23)
+ isConstantOrUndef(N-getOperand(12), 26)
+ isConstantOrUndef(N-getOperand(13), 27)
+ isConstantOrUndef(N-getOperand(14), 30)
+ isConstantOrUndef(N-getOperand(15), 31);
+}
+
+
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a splat of a single element that is suitable for input to
@@ -759,6 +809,10 @@
PPC::isSplatShuffleMask(PermMask.Val, 4)))
return Op;
+if (PPC::isVPKUWUMShuffleMask(PermMask.Val) ||
+PPC::isVPKUHUMShuffleMask(PermMask.Val))
+ return Op;
+
// TODO: Handle more cases, and also handle cases that are cheaper to do as
// multiple such instructions than as a constant pool load/vperm pair.
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.39
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.40
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.39 Tue Apr 4 12:25:31 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 12:23:16 2006
@@ -102,6 +102,14 @@
/// Define some predicates that are used for node matching.
namespace PPC {
+/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
+/// VPKUHUM instruction.
+bool isVPKUHUMShuffleMask(SDNode *N);
+
+/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
+/// VPKUWUM instruction.
+bool isVPKUWUMShuffleMask(SDNode *N);
+
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE
operand
/// specifies a splat of a single element that is suitable for input to
/// VSPLTB/VSPLTH/VSPLTW.
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.41
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.42
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.41 Wed Apr 5 17:27:14 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 12:23:16 2006
@@ -15,6 +15,15 @@
// Altivec transformation functions and
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.133 - 1.134
PPCISelLowering.h updated: 1.40 - 1.41
PPCInstrAltivec.td updated: 1.42 - 1.43
README_ALTIVEC.txt updated: 1.15 - 1.16
---
Log message:
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
---
Diffs of the changes: (+97 -41)
PPCISelLowering.cpp | 95 +---
PPCISelLowering.h |8
PPCInstrAltivec.td | 30 ++--
README_ALTIVEC.txt |5 --
4 files changed, 97 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.133
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.133 Thu Apr 6 12:23:16 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 13:26:28 2006
@@ -277,46 +277,73 @@
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
/// VPKUHUM instruction.
bool PPC::isVPKUHUMShuffleMask(SDNode *N) {
- return isConstantOrUndef(N-getOperand( 0), 1)
- isConstantOrUndef(N-getOperand( 1), 3)
- isConstantOrUndef(N-getOperand( 2), 5)
- isConstantOrUndef(N-getOperand( 3), 7)
- isConstantOrUndef(N-getOperand( 4), 9)
- isConstantOrUndef(N-getOperand( 5), 11)
- isConstantOrUndef(N-getOperand( 6), 13)
- isConstantOrUndef(N-getOperand( 7), 15)
- isConstantOrUndef(N-getOperand( 8), 17)
- isConstantOrUndef(N-getOperand( 9), 19)
- isConstantOrUndef(N-getOperand(10), 21)
- isConstantOrUndef(N-getOperand(11), 23)
- isConstantOrUndef(N-getOperand(12), 25)
- isConstantOrUndef(N-getOperand(13), 27)
- isConstantOrUndef(N-getOperand(14), 29)
- isConstantOrUndef(N-getOperand(15), 31);
+ for (unsigned i = 0; i != 16; ++i)
+if (!isConstantOrUndef(N-getOperand(i), i*2+1))
+ return false;
+ return true;
}
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
/// VPKUWUM instruction.
bool PPC::isVPKUWUMShuffleMask(SDNode *N) {
- return isConstantOrUndef(N-getOperand( 0), 2)
- isConstantOrUndef(N-getOperand( 1), 3)
- isConstantOrUndef(N-getOperand( 2), 6)
- isConstantOrUndef(N-getOperand( 3), 7)
- isConstantOrUndef(N-getOperand( 4), 10)
- isConstantOrUndef(N-getOperand( 5), 11)
- isConstantOrUndef(N-getOperand( 6), 14)
- isConstantOrUndef(N-getOperand( 7), 15)
- isConstantOrUndef(N-getOperand( 8), 18)
- isConstantOrUndef(N-getOperand( 9), 19)
- isConstantOrUndef(N-getOperand(10), 22)
- isConstantOrUndef(N-getOperand(11), 23)
- isConstantOrUndef(N-getOperand(12), 26)
- isConstantOrUndef(N-getOperand(13), 27)
- isConstantOrUndef(N-getOperand(14), 30)
- isConstantOrUndef(N-getOperand(15), 31);
+ for (unsigned i = 0; i != 16; i += 2)
+if (!isConstantOrUndef(N-getOperand(i ), i*2+2) ||
+!isConstantOrUndef(N-getOperand(i+1), i*2+3))
+ return false;
+ return true;
}
+/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
+/// amount, otherwise return -1.
+int PPC::isVSLDOIShuffleMask(SDNode *N) {
+ assert(N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
+ // Find the first non-undef value in the shuffle mask.
+ unsigned i;
+ for (i = 0; i != 16 N-getOperand(i).getOpcode() == ISD::UNDEF; ++i)
+/*search*/;
+
+ if (i == 16) return -1; // all undef.
+
+ // Otherwise, check to see if the rest of the elements are consequtively
+ // numbered from this value.
+ unsigned ShiftAmt = castConstantSDNode(N-getOperand(i))-getValue();
+ if (ShiftAmt i) return -1;
+ ShiftAmt -= i;
+
+ // Check the rest of the elements to see if they are consequtive.
+ for (++i; i != 16; ++i)
+if (!isConstantOrUndef(N-getOperand(i), ShiftAmt+i))
+ return -1;
+
+ return ShiftAmt;
+}
+/// isVSLDOIRotateShuffleMask - If this is a vsldoi rotate shuffle mask,
+/// return the shift amount, otherwise return -1. Note that vlsdoi(x,x) will
+/// result in the shuffle being changed to shuffle(x,undef, ...) with
+/// transformed byte numbers.
+int PPC::isVSLDOIRotateShuffleMask(SDNode *N) {
+ assert(N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
+ // Find the first non-undef value in the shuffle mask.
+ unsigned i;
+ for (i = 0; i != 16 N-getOperand(i).getOpcode() == ISD::UNDEF; ++i)
+/*search*/;
+
+ if (i == 16) return -1; // all undef.
+
+ // Otherwise, check to see if the rest of the elements are consequtively
+ // numbered from this value.
+ unsigned ShiftAmt = castConstantSDNode(N-getOperand(i))-getValue();
+ if (ShiftAmt i) return -1;
+ ShiftAmt -= i;
+
+ // Check the rest of
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.134 - 1.135
PPCISelLowering.h updated: 1.41 - 1.42
PPCInstrAltivec.td updated: 1.43 - 1.44
README_ALTIVEC.txt updated: 1.17 - 1.18
---
Log message:
Pattern match vmrg* instructions, which are now lowered by the CFE into
shuffles.
---
Diffs of the changes: (+101 -12)
PPCISelLowering.cpp | 52 +---
PPCISelLowering.h |8
PPCInstrAltivec.td | 50 --
README_ALTIVEC.txt |3 ---
4 files changed, 101 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134 Thu Apr 6 13:26:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 16:11:54 2006
@@ -293,10 +293,50 @@
return true;
}
+/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
+/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
+bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) {
+ assert(N-getOpcode() == ISD::BUILD_VECTOR
+ N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
+ assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4)
+ Unsupported merge size!);
+
+ for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
+for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
+ if (!isConstantOrUndef(N-getOperand(i*UnitSize*2+j),
+ 8+j+i*UnitSize) ||
+ !isConstantOrUndef(N-getOperand(i*UnitSize*2+UnitSize+j),
+ 24+j+i*UnitSize))
+return false;
+}
+ return true;
+}
+
+/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
+/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
+bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize) {
+ assert(N-getOpcode() == ISD::BUILD_VECTOR
+ N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
+ assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4)
+ Unsupported merge size!);
+
+ for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
+for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
+ if (!isConstantOrUndef(N-getOperand(i*UnitSize*2+j),
+ 0+j+i*UnitSize) ||
+ !isConstantOrUndef(N-getOperand(i*UnitSize*2+UnitSize+j),
+ 16+j+i*UnitSize))
+return false;
+}
+ return true;
+}
+
+
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
/// amount, otherwise return -1.
int PPC::isVSLDOIShuffleMask(SDNode *N) {
- assert(N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
+ assert(N-getOpcode() == ISD::BUILD_VECTOR
+ N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
// Find the first non-undef value in the shuffle mask.
unsigned i;
for (i = 0; i != 16 N-getOperand(i).getOpcode() == ISD::UNDEF; ++i)
@@ -833,13 +873,19 @@
if (V2.getOpcode() == ISD::UNDEF
(PPC::isSplatShuffleMask(PermMask.Val, 1) ||
PPC::isSplatShuffleMask(PermMask.Val, 2) ||
- PPC::isSplatShuffleMask(PermMask.Val, 4)))
+ PPC::isSplatShuffleMask(PermMask.Val, 4) ||
+ PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1))
return Op;
if (PPC::isVPKUWUMShuffleMask(PermMask.Val) ||
PPC::isVPKUHUMShuffleMask(PermMask.Val) ||
PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 ||
-PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1)
+PPC::isVMRGLShuffleMask(PermMask.Val, 1) ||
+PPC::isVMRGLShuffleMask(PermMask.Val, 2) ||
+PPC::isVMRGLShuffleMask(PermMask.Val, 4) ||
+PPC::isVMRGHShuffleMask(PermMask.Val, 1) ||
+PPC::isVMRGHShuffleMask(PermMask.Val, 2) ||
+PPC::isVMRGHShuffleMask(PermMask.Val, 4))
return Op;
// TODO: Handle more cases, and also handle cases that are cheaper to do as
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.42
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41 Thu Apr 6 13:26:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 16:11:54 2006
@@ -109,6 +109,14 @@
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
/// VPKUWUM instruction.
bool isVPKUWUMShuffleMask(SDNode *N);
+
+/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
+/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
+bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize);
+
+/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.135 - 1.136
PPCISelLowering.h updated: 1.42 - 1.43
PPCInstrAltivec.td updated: 1.44 - 1.45
---
Log message:
Add support for matching vmrg(x,x) patterns
---
Diffs of the changes: (+81 -41)
PPCISelLowering.cpp | 72
PPCISelLowering.h |4 +-
PPCInstrAltivec.td | 46 -
3 files changed, 81 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.136
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135 Thu Apr 6 16:11:54 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 17:02:42 2006
@@ -293,9 +293,10 @@
return true;
}
-/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
-/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
-bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) {
+/// isVMerge - Common function, used to match vmrg* shuffles.
+///
+static bool isVMerge(SDNode *N, unsigned UnitSize,
+ unsigned LHSStart, unsigned RHSStart) {
assert(N-getOpcode() == ISD::BUILD_VECTOR
N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4)
@@ -304,31 +305,28 @@
for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
if (!isConstantOrUndef(N-getOperand(i*UnitSize*2+j),
- 8+j+i*UnitSize) ||
+ LHSStart+j+i*UnitSize) ||
!isConstantOrUndef(N-getOperand(i*UnitSize*2+UnitSize+j),
- 24+j+i*UnitSize))
+ RHSStart+j+i*UnitSize))
return false;
}
- return true;
+ return true;
+}
+
+/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
+/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
+bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
+ if (!isUnary)
+return isVMerge(N, UnitSize, 8, 24);
+ return isVMerge(N, UnitSize, 8, 8);
}
/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
-bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize) {
- assert(N-getOpcode() == ISD::BUILD_VECTOR
- N-getNumOperands() == 16 PPC only supports shuffles by bytes!);
- assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4)
- Unsupported merge size!);
-
- for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
-for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
- if (!isConstantOrUndef(N-getOperand(i*UnitSize*2+j),
- 0+j+i*UnitSize) ||
- !isConstantOrUndef(N-getOperand(i*UnitSize*2+UnitSize+j),
- 16+j+i*UnitSize))
-return false;
-}
- return true;
+bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
+ if (!isUnary)
+return isVMerge(N, UnitSize, 0, 16);
+ return isVMerge(N, UnitSize, 0, 0);
}
@@ -870,22 +868,30 @@
// Cases that are handled by instructions that take permute immediates
// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
// selected by the instruction selector.
-if (V2.getOpcode() == ISD::UNDEF
-(PPC::isSplatShuffleMask(PermMask.Val, 1) ||
- PPC::isSplatShuffleMask(PermMask.Val, 2) ||
- PPC::isSplatShuffleMask(PermMask.Val, 4) ||
- PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1))
- return Op;
+if (V2.getOpcode() == ISD::UNDEF) {
+ if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
+ PPC::isSplatShuffleMask(PermMask.Val, 2) ||
+ PPC::isSplatShuffleMask(PermMask.Val, 4) ||
+ PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1 ||
+ PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
+ PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
+ PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
+ PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
+ PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
+ PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
+return Op;
+ }
+}
if (PPC::isVPKUWUMShuffleMask(PermMask.Val) ||
PPC::isVPKUHUMShuffleMask(PermMask.Val) ||
PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 ||
-PPC::isVMRGLShuffleMask(PermMask.Val, 1) ||
-PPC::isVMRGLShuffleMask(PermMask.Val, 2) ||
-PPC::isVMRGLShuffleMask(PermMask.Val, 4) ||
-PPC::isVMRGHShuffleMask(PermMask.Val, 1) ||
-PPC::isVMRGHShuffleMask(PermMask.Val, 2) ||
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.137 - 1.138
---
Log message:
Make sure to return the result in the right type.
---
Diffs of the changes: (+6 -4)
PPCISelLowering.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.137
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.138
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.137 Thu Apr 6 17:28:36 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 18:12:19 2006
@@ -962,10 +962,12 @@
assert(CompareOpc0 We only lower altivec predicate compares so far!);
// If this is a non-dot comparison, make the VCMP node.
-if (!isDot)
- return DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
- Op.getOperand(1), Op.getOperand(2),
- DAG.getConstant(CompareOpc, MVT::i32));
+if (!isDot) {
+ SDOperand Tmp = DAG.getNode(PPCISD::VCMP,
Op.getOperand(2).getValueType(),
+ Op.getOperand(1), Op.getOperand(2),
+ DAG.getConstant(CompareOpc, MVT::i32));
+ return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
+}
// Create the PPCISD altivec 'dot' comparison node.
std::vectorSDOperand Ops;
___
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