Re: [Mesa-dev] [PATCH 11/18] glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().
After debugging I have more information about what is going on. There
are two problems, one is that the stream variable in ir_emit_vertex gets
trashed and the other one is that even if we manage to avoid that it
won't get its value assigned. I explain how these two come to happen
below and maybe someone can point me to what I am doing wrong:
first, this is how I am defining EmitStreamVertex():
ir_function_signature *
builtin_builder::_EmitStreamVertex(builtin_available_predicate avail,
const glsl_type *stream_type)
{
ir_variable *stream =
new(mem_ctx) ir_variable(stream_type, "stream", ir_var_const_in);
MAKE_SIG(glsl_type::void_type, avail, 1, stream);
ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
ir->stream = var_ref(stream);
body.emit(ir);
return sig;
}
The pattern is similar to other built-in functions. Notice how
ir_stream_vertex will take a reference to the input stream variable.
And this is how I am defining ir_emit_vertex:
class ir_emit_vertex : public ir_instruction {
public:
ir_emit_vertex() : ir_instruction(ir_type_emit_vertex), stream(NULL) {}
virtual void accept(ir_visitor *v) { v->visit(this); }
virtual ir_emit_vertex *clone(void *mem_ctx, struct hash_table *ht)
const
{
ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
if (this->stream)
ir->stream = this->stream->clone(mem_ctx, ht);
return ir;
}
virtual ir_visitor_status accept(ir_hierarchical_visitor *);
ir_dereference_variable *stream;
};
Again, I don't see anything special as it follows the same pattern as
other IR definitions in ir.h.
If I only do this, then, by the time I reach
vec4_gs_visitor::visit(ir_emit_vertex *ir), ir->stream has been trashed.
¿Is this expected? ¿Am I missing something in EmitStreamVertex(),
ir_emit_vertex or somewhere else that is causing this?
Valgrind says the variable gets killed with the destruction of the
ralloc context created in link_shaders. And indeed, removing the
ralloc_free lets the variable reach the visitor. I suppose this is not
expected (otherwise we would have this problem in any built-in function
that accepts input parameters). Just in case, I noticed this code in
link_shaders:
clone_ir_list(mem_ctx, linked->ir, main->ir);
It seems that it clones code using that ralloc context created in
link_shaders, so I changed it to be:
clone_ir_list(linked, linked->ir, main->ir);
And it fixes the problem, but I suppose this is only a workaround for
the real problem.
As for the second problem, if I bypass the variable trashing by removing
the call to ralloc_free in link_shaders() or by doing the change above,
then when we reach vec4_gs_visitor::visit(ir_emit_vertex *ir), if I do
((ir_rvalue*)ir->stream)->as_constant() it will still return NULL, so it
is useless. I want to read the value of the variable here, which I
should be able to do since this is a constant expression.
However, as far as I can see by looking into ir_call::generate_inline()
this seems to be expected: inputs to functions get a *new* variable for
them, where the actual parameter value is set via an ir_assignment:
parameters[i] = sig_param->clone(ctx, ht);
parameters[i]->data.mode = ir_var_auto;
(...)
assign =
new(ctx) ir_assignment(new(ctx)
ir_dereference_variable(parameters[i]),
param, NULL);
next_ir->insert_before(assign);
(...)
And then it clones the body of the function, like so:
foreach_list(n, &callee->body) {
ir_instruction *ir = (ir_instruction *) n;
ir_instruction *new_ir = ir->clone(ctx, ht);
new_instructions.push_tail(new_ir);
visit_tree(new_ir, replace_return_with_assignment,
this->return_deref);
}
In our case, there is only one instruction here: ir_emit_vertex, and
when cloning it we are also cloning its reference to the stream
variable, but this is *different* from the parameter variable where we
copied the actual parameter value, so there is no way we will be able to
access the value of the variable from this reference.
I can work around this problem in the visitor by doing this:
dst_reg *reg = variable_storage(ir->stream->var);
This seems to return the register associated with the real stream
parameter that was the target of the ir_assignment, and then work with
reg directly rather than creating a register in the visitor and moving
the stream_id value to it. If I do it like this, however, I can't do
some things that I was doing before, like not generating any code to set
control data bits when we are calling EmitStreamVertex(0), because I
can't access the value of the variable in the visitor to assess its
value.
So that's it, hopefully that's enough information for someone to tell
what is missing in the implementation or if there is some other problem
that is causing all this.
Iago
On Wed, 2014-06-11 at 21:25 +1200, Chris Forbes wrote:
> This is pretty weird.
>
> We should be able to generate a
Re: [Mesa-dev] [PATCH 11/18] glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().
I forgot to add an important piece of info. I also had to add this in
the opt_dead_code.cpp, do_dead_code():
if (strcmp(entry->var->name, "stream") == 0)
continue;
without that, the variable referenced by ir_emit_vertex() gets trashed
anyway, whether the ralloc context in link_shaders is detroyed or not.
Iago
On Fri, 2014-06-13 at 10:09 +0200, Iago Toral wrote:
> After debugging I have more information about what is going on. There
> are two problems, one is that the stream variable in ir_emit_vertex gets
> trashed and the other one is that even if we manage to avoid that it
> won't get its value assigned. I explain how these two come to happen
> below and maybe someone can point me to what I am doing wrong:
>
> first, this is how I am defining EmitStreamVertex():
>
> ir_function_signature *
> builtin_builder::_EmitStreamVertex(builtin_available_predicate avail,
>const glsl_type *stream_type)
> {
>ir_variable *stream =
> new(mem_ctx) ir_variable(stream_type, "stream", ir_var_const_in);
>MAKE_SIG(glsl_type::void_type, avail, 1, stream);
>ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
>ir->stream = var_ref(stream);
>body.emit(ir);
>return sig;
> }
>
> The pattern is similar to other built-in functions. Notice how
> ir_stream_vertex will take a reference to the input stream variable.
>
> And this is how I am defining ir_emit_vertex:
>
> class ir_emit_vertex : public ir_instruction {
> public:
> ir_emit_vertex() : ir_instruction(ir_type_emit_vertex), stream(NULL) {}
>
> virtual void accept(ir_visitor *v) { v->visit(this); }
>
> virtual ir_emit_vertex *clone(void *mem_ctx, struct hash_table *ht)
> const
> {
> ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
> if (this->stream)
>ir->stream = this->stream->clone(mem_ctx, ht);
> return ir;
> }
>
> virtual ir_visitor_status accept(ir_hierarchical_visitor *);
> ir_dereference_variable *stream;
> };
>
> Again, I don't see anything special as it follows the same pattern as
> other IR definitions in ir.h.
>
> If I only do this, then, by the time I reach
> vec4_gs_visitor::visit(ir_emit_vertex *ir), ir->stream has been trashed.
>
> ¿Is this expected? ¿Am I missing something in EmitStreamVertex(),
> ir_emit_vertex or somewhere else that is causing this?
>
> Valgrind says the variable gets killed with the destruction of the
> ralloc context created in link_shaders. And indeed, removing the
> ralloc_free lets the variable reach the visitor. I suppose this is not
> expected (otherwise we would have this problem in any built-in function
> that accepts input parameters). Just in case, I noticed this code in
> link_shaders:
>
> clone_ir_list(mem_ctx, linked->ir, main->ir);
>
> It seems that it clones code using that ralloc context created in
> link_shaders, so I changed it to be:
>
>clone_ir_list(linked, linked->ir, main->ir);
>
> And it fixes the problem, but I suppose this is only a workaround for
> the real problem.
>
> As for the second problem, if I bypass the variable trashing by removing
> the call to ralloc_free in link_shaders() or by doing the change above,
> then when we reach vec4_gs_visitor::visit(ir_emit_vertex *ir), if I do
> ((ir_rvalue*)ir->stream)->as_constant() it will still return NULL, so it
> is useless. I want to read the value of the variable here, which I
> should be able to do since this is a constant expression.
>
> However, as far as I can see by looking into ir_call::generate_inline()
> this seems to be expected: inputs to functions get a *new* variable for
> them, where the actual parameter value is set via an ir_assignment:
>
> parameters[i] = sig_param->clone(ctx, ht);
> parameters[i]->data.mode = ir_var_auto;
> (...)
> assign =
>new(ctx) ir_assignment(new(ctx)
> ir_dereference_variable(parameters[i]),
> param, NULL);
> next_ir->insert_before(assign);
> (...)
>
> And then it clones the body of the function, like so:
>
> foreach_list(n, &callee->body) {
>ir_instruction *ir = (ir_instruction *) n;
>ir_instruction *new_ir = ir->clone(ctx, ht);
>
>new_instructions.push_tail(new_ir);
>visit_tree(new_ir, replace_return_with_assignment,
> this->return_deref);
> }
>
> In our case, there is only one instruction here: ir_emit_vertex, and
> when cloning it we are also cloning its reference to the stream
> variable, but this is *different* from the parameter variable where we
> copied the actual parameter value, so there is no way we will be able to
> access the value of the variable from this reference.
>
> I can work around this problem in the visitor by doing this:
>
> dst_reg *reg = variable_storage(ir->stream->var);
>
> This seems to return the register associated with the real stream
> parameter that was the target of the ir_assignment, and then work with
> reg directly rather than creating a register
[Mesa-dev] [Bug 74010] mesa-10.0.2: z-buffer issue with opengl 3.3 context on intel
https://bugs.freedesktop.org/show_bug.cgi?id=74010 Tapani Pälli changed: What|Removed |Added CC||lem...@gmail.com --- Comment #8 from Tapani Pälli --- For some reason the core version framebuffer does not have a depth buffer at all. I could not compile the test app (because of api differences happened in glm library) so I could not test which causes this, but I can see that there are several differences in OpenGLArea and OpenGLArea3 class implementation, not only the context version. Could you please 'minimize' these differences to see if it has impact (for example make glx_attrs content exactly the same in both cases)? From there is is much easier to figure out what could be the problem. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
v2:
Add RADEON_INFO_ACTIVE_CU_COUNT as a define, as suggested by
Tom Stellard
---
src/gallium/drivers/radeon/r600_pipe_common.c | 7 +++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 7 +++
src/gallium/winsys/radeon/drm/radeon_winsys.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 70c4d1a..e7d33a0 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -519,6 +519,13 @@ static int r600_get_compute_param(struct pipe_screen
*screen,
}
return sizeof(uint32_t);
+ case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
+ if (ret) {
+ uint32_t *max_compute_units = ret;
+ *max_compute_units = rscreen->info.max_compute_units;
+ }
+ return sizeof(uint32_t);
+
default:
fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
return 0;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index e54e79e..576fea5 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -45,6 +45,10 @@
#include
#include
+#ifndef RADEON_INFO_ACTIVE_CU_COUNT
+#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
+#endif
+
static struct util_hash_table *fd_tab = NULL;
pipe_static_mutex(fd_tab_mutex);
@@ -382,6 +386,9 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
&ws->info.r600_max_pipes);
+radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
+ &ws->info.max_compute_units);
+
if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
ws->info.si_tile_mode_array)) {
ws->info.si_tile_mode_array_valid = TRUE;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 2d13550..6df1987 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -198,6 +198,7 @@ struct radeon_info {
uint32_tgart_size;
uint32_tvram_size;
uint32_tmax_sclk;
+uint32_tmax_compute_units;
uint32_tdrm_major; /* version */
uint32_tdrm_minor;
--
2.0.0
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[Mesa-dev] [PATCH] i965/gen8: Align hiz depth clear to 8x4
This fixes framebuffer_blit_functionality_scissor_blit.test in
gles3 cts.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 8c70c62..7f1c23d 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -30,6 +30,17 @@
#include "brw_defines.h"
/**
+ * The documentation for Broadwell's Hierarchical Depth Buffer Resolve and for
+ * Depth Buffer Clear mandates the rectangle to be 8x4 aligned.
+ */
+static void
+align_rectangle_primitive(uint32_t *width, uint32_t *height)
+{
+ *width = ALIGN(*width, 8);
+ *height = ALIGN(*height, 4);
+}
+
+/**
* Helper function to emit depth related command packets.
*/
static void
@@ -54,6 +65,8 @@ emit_depth_packets(struct brw_context *brw,
return;
}
+ align_rectangle_primitive(&width, &height);
+
intel_emit_depth_stall_flushes(brw);
/* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
@@ -248,6 +261,8 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
unsigned rect_width = minify(mt->logical_width0, level);
unsigned rect_height = minify(mt->logical_height0, level);
+ align_rectangle_primitive(&rect_width, &rect_height);
+
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0);
--
1.9.1
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[Mesa-dev] [Bug 74010] mesa-10.0.2: z-buffer issue with opengl 3.3 context on intel
https://bugs.freedesktop.org/show_bug.cgi?id=74010 --- Comment #9 from Tapani Pälli --- The problem is with the glxconfig that gets chosen. The application queries for compatible list of configs with glXChooseFBConfig and then blindly selects the first one. Although attributes for config query state GLX_DEPTH_SIZE 24, Mesa returns some configs that have depth size 0 and application selects one of those. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 11/18] glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().
On Fri, 2014-06-13 at 10:28 +0200, Iago Toral wrote:
> I forgot to add an important piece of info. I also had to add this in
> the opt_dead_code.cpp, do_dead_code():
>
> if (strcmp(entry->var->name, "stream") == 0)
> continue;
>
> without that, the variable referenced by ir_emit_vertex() gets trashed
> anyway, whether the ralloc context in link_shaders is detroyed or not.
The variable is killed because it is not used, as I was anticipating in
my patch, but I don't think the optimization passes are broken, I think
this is expected to happen:
This is the code generated for EmitStreamVertex(0) after function
inlining:
(declare () int stream)
(assign (x) (var_ref stream) (constant int (0)) )
(emit-vertex)
(...)
(function EmitStreamVertex
(signature void
(parameters
(declare (const_in ) int stream)
)
(
(emit-vertex)
))
)
And this is after the dead code elimination passes (dead_code and
dead_code_local), first the assignment is removed:
(declare () int stream)
(emit-vertex)
And finally, in a second pass, it removes the declaration too, leaving:
(emit-vertex)
Seems to make sense: it is killing a variable that is, at this stage,
not used for anything. So, as I was saying in the original patch, I
think we can't do EmitStreamVertex(n) like any other built-in function
because we won't be using its input parameter in the body of the
function for anything, the variable's value is to be used in the visitor
when it is time to generate the native code and that happens after the
optimization passes, so we need to grab its constant value before the
optimization passes (as my original patch did) or we have to find a way
to tell the optimization passes that it should not touch this variable
specifically (and then we would still have to figure out how to access
that temporary variable holding the stream value from the visitor).
Iago
> Iago
>
> On Fri, 2014-06-13 at 10:09 +0200, Iago Toral wrote:
> > After debugging I have more information about what is going on. There
> > are two problems, one is that the stream variable in ir_emit_vertex gets
> > trashed and the other one is that even if we manage to avoid that it
> > won't get its value assigned. I explain how these two come to happen
> > below and maybe someone can point me to what I am doing wrong:
> >
> > first, this is how I am defining EmitStreamVertex():
> >
> > ir_function_signature *
> > builtin_builder::_EmitStreamVertex(builtin_available_predicate avail,
> >const glsl_type *stream_type)
> > {
> >ir_variable *stream =
> > new(mem_ctx) ir_variable(stream_type, "stream", ir_var_const_in);
> >MAKE_SIG(glsl_type::void_type, avail, 1, stream);
> >ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
> >ir->stream = var_ref(stream);
> >body.emit(ir);
> >return sig;
> > }
> >
> > The pattern is similar to other built-in functions. Notice how
> > ir_stream_vertex will take a reference to the input stream variable.
> >
> > And this is how I am defining ir_emit_vertex:
> >
> > class ir_emit_vertex : public ir_instruction {
> > public:
> > ir_emit_vertex() : ir_instruction(ir_type_emit_vertex), stream(NULL) {}
> >
> > virtual void accept(ir_visitor *v) { v->visit(this); }
> >
> > virtual ir_emit_vertex *clone(void *mem_ctx, struct hash_table *ht)
> > const
> > {
> > ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
> > if (this->stream)
> >ir->stream = this->stream->clone(mem_ctx, ht);
> > return ir;
> > }
> >
> > virtual ir_visitor_status accept(ir_hierarchical_visitor *);
> > ir_dereference_variable *stream;
> > };
> >
> > Again, I don't see anything special as it follows the same pattern as
> > other IR definitions in ir.h.
> >
> > If I only do this, then, by the time I reach
> > vec4_gs_visitor::visit(ir_emit_vertex *ir), ir->stream has been trashed.
> >
> > ¿Is this expected? ¿Am I missing something in EmitStreamVertex(),
> > ir_emit_vertex or somewhere else that is causing this?
> >
> > Valgrind says the variable gets killed with the destruction of the
> > ralloc context created in link_shaders. And indeed, removing the
> > ralloc_free lets the variable reach the visitor. I suppose this is not
> > expected (otherwise we would have this problem in any built-in function
> > that accepts input parameters). Just in case, I noticed this code in
> > link_shaders:
> >
> > clone_ir_list(mem_ctx, linked->ir, main->ir);
> >
> > It seems that it clones code using that ralloc context created in
> > link_shaders, so I changed it to be:
> >
> >clone_ir_list(linked, linked->ir, main->ir);
> >
> > And it fixes the problem, but I suppose this is only a workaround for
> > the real problem.
> >
> > As for the second problem, if I bypass the variable trashing by removing
> > the call to ralloc_free in link_shaders() or by doing the change above,
> > then when we reach vec4_gs_visitor::visit(ir_emit_vertex *ir), if I do
> > (
[Mesa-dev] [Bug 74010] mesa-10.0.2: z-buffer issue with opengl 3.3 context on intel
https://bugs.freedesktop.org/show_bug.cgi?id=74010 --- Comment #10 from Brian Paul --- Just FYI: There are some GL apps out there that use depth buffering but don't bother to request a GLX visual with a depth buffer. Topogun is one example. There's a DRI config option called "always_have_depth_buffer" which causes all visual types to be created with a depth buffer. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Remove _mesa_is_type_integer and _mesa_is_enum_format_or_type_integer
On 06/12/2014 10:52 AM, Neil Roberts wrote: The comment for _mesa_is_type_integer is confusing because it says that it returns whether the type is an “integer (non-normalized)” format. I don't think it makes sense to say whether a type is normalized or not because it depends on what format it is used with. For example, GL_RGBA+GL_UNSIGNED_BYTE is normalized but GL_RGBA_INTEGER+GL_UNSIGNED_BYTE isn't. If the normalized comment is just a mistake then it still doesn't make much sense because it is missing the packed-pixel types such as GL_UNSIGNED_INT_5_6_5. If those were added then it effectively just returns type != GL_FLOAT. That function was only used in _mesa_is_enum_format_or_type_integer. This function effectively checks whether the format is non-normalized or the type is an integer. I can't think of any situation where that check would make sense. As far as I can tell neither of these functions have ever been used anywhere so we should just remove them to avoid confusion. These functions were added in 9ad8f431b2a47060bf05517246ab0fa8d249c800. --- src/mesa/main/glformats.c | 30 -- src/mesa/main/glformats.h | 6 -- 2 files changed, 36 deletions(-) Reviewed-by: Brian Paul Do you need someone to commit/push this? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] r600g/radeonsi: Remove default case from PIPE_COMPUTE_CAP_* switch
Reviewed-by: Marek Olšák Marek On Fri, Jun 13, 2014 at 5:23 AM, Michel Dänzer wrote: > From: Michel Dänzer > > This way, the compiler warns about unhandled caps. > > Signed-off-by: Michel Dänzer > --- > src/gallium/drivers/radeon/r600_pipe_common.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c > b/src/gallium/drivers/radeon/r600_pipe_common.c > index 4c6cf0e..9813026 100644 > --- a/src/gallium/drivers/radeon/r600_pipe_common.c > +++ b/src/gallium/drivers/radeon/r600_pipe_common.c > @@ -519,11 +519,10 @@ static int r600_get_compute_param(struct pipe_screen > *screen, > *max_clock_frequency = rscreen->info.max_sclk; > } > return sizeof(uint32_t); > - > - default: > - fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); > - return 0; > } > + > +fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); > +return 0; > } > > static uint64_t r600_get_timestamp(struct pipe_screen *screen) > -- > 2.0.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Remove _mesa_is_type_integer and _mesa_is_enum_format_or_type_integer
Brian Paul writes: > Reviewed-by: Brian Paul > > Do you need someone to commit/push this? Thanks for the review. I do have commit access for Mesa so I've just pushed it. As an aside, I don't have commit access for Piglit and I haven't been able to find someone who can grant me access. If you are able to then I would very much appreciate it. https://bugs.freedesktop.org/show_bug.cgi?id=79718 Regards, - Neil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radeon/compute: Always report at least 1 compute unit
Some apps will abort if they detect 0 compute units. This fixes
crashes in some OpenCV tests.
---
src/gallium/drivers/radeon/r600_pipe_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 4b9d31c..1911cde 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -523,7 +523,7 @@ static int r600_get_compute_param(struct pipe_screen
*screen,
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
if (ret) {
uint32_t *max_compute_units = ret;
- *max_compute_units = rscreen->info.max_compute_units;
+ *max_compute_units =
MAX2(rscreen->info.max_compute_units, 1);
}
return sizeof(uint32_t);
--
1.8.1.5
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Re: [Mesa-dev] [PATCH] i965/gen8: Align hiz depth clear to 8x4
On Fri, Jun 13, 2014 at 12:38:43PM +0300, Topi Pohjolainen wrote:
> This fixes framebuffer_blit_functionality_scissor_blit.test in
> gles3 cts.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 8c70c62..7f1c23d 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -30,6 +30,17 @@
> #include "brw_defines.h"
>
> /**
> + * The documentation for Broadwell's Hierarchical Depth Buffer Resolve and
> for
> + * Depth Buffer Clear mandates the rectangle to be 8x4 aligned.
> + */
My reading of the spec leads me to believe the situation is actually a
lot more complicated than this, but this is sufficient. It would seem
though that this covers all cases. (Also, you don't need it for a
resolve AFAICT, only a clear).
Reviewed-by: Ben Widawsky
> +static void
> +align_rectangle_primitive(uint32_t *width, uint32_t *height)
> +{
> + *width = ALIGN(*width, 8);
> + *height = ALIGN(*height, 4);
> +}
> +
> +/**
> * Helper function to emit depth related command packets.
> */
> static void
> @@ -54,6 +65,8 @@ emit_depth_packets(struct brw_context *brw,
>return;
> }
>
> + align_rectangle_primitive(&width, &height);
> +
> intel_emit_depth_stall_flushes(brw);
>
> /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
> @@ -248,6 +261,8 @@ gen8_hiz_exec(struct brw_context *brw, struct
> intel_mipmap_tree *mt,
> unsigned rect_width = minify(mt->logical_width0, level);
> unsigned rect_height = minify(mt->logical_height0, level);
>
> + align_rectangle_primitive(&rect_width, &rect_height);
> +
> BEGIN_BATCH(4);
> OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
> OUT_BATCH(0);
> --
> 1.9.1
>
> ___
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Re: [Mesa-dev] [PATCH 04/15] glsl: Add preprocessor error condition for #else directive
On Thu, Jun 12, 2014 at 11:42 PM, Tapani Pälli wrote:
> On 06/07/2014 02:57 AM, Anuj Phogat wrote:
>> Fixes gles3 Khronos CTS tests:
>> tokens_after_else_vertex
>> tokens_after_else_fragment
>>
>> Cc:
>> Signed-off-by: Anuj Phogat
>> ---
>> src/glsl/glcpp/glcpp-lex.l | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/src/glsl/glcpp/glcpp-lex.l b/src/glsl/glcpp/glcpp-lex.l
>> index 188e454..393db81 100644
>> --- a/src/glsl/glcpp/glcpp-lex.l
>> +++ b/src/glsl/glcpp/glcpp-lex.l
>> @@ -221,6 +221,10 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]?
>> return HASH_ELSE;
>> }
>>
>> +{HASH}else{HSPACE}*[^ \t\n]+ {
>
> I can't find exact specification for a 'new-line' from the spec, so IMO
> we should allow '\r' also here.
>
I've dropped this patch from the series after Carl's comment. Now, Carl
has posted a patch to fix the issue.
>> +glcpp_error(yylloc, yyextra, "illegal tokens after #else");
>> +}
>> +
>> {HASH}endif {
>> yyextra->space_tokens = 0;
>> return HASH_ENDIF;
>
> // Tapani
>
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[Mesa-dev] [PATCH] clover: Cache serialized binaries
We were serializing the binaries once when clGetProgramInfo was called
with CL_PROGRAM_BINARY_SIZES and then again when it was called with
CL_PROGRAM_BINARIES. This was slowing down some OpenCV tests which were
building binary kernel caches.
This improves the run-time of OpenCV's OCL_ImgProc/CvtColor8u.*
test from 7 minutes to 1 minute.
---
src/gallium/state_trackers/clover/api/program.cpp | 10 ++
src/gallium/state_trackers/clover/core/program.cpp | 12
src/gallium/state_trackers/clover/core/program.hpp | 2 ++
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index fedc91d..68ef698 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -190,20 +190,14 @@ clGetProgramInfo(cl_program d_prog, cl_program_info param,
case CL_PROGRAM_BINARY_SIZES:
buf.as_vector() = map([&](const device &dev) {
-compat::ostream::buffer_t bin;
-compat::ostream s(bin);
-prog.binary(dev).serialize(s);
-return bin.size();
+return prog.serialized_binary(dev).size();
},
prog.devices());
break;
case CL_PROGRAM_BINARIES:
buf.as_matrix() = map([&](const device &dev) {
-compat::ostream::buffer_t bin;
-compat::ostream s(bin);
-prog.binary(dev).serialize(s);
-return bin;
+return prog.serialized_binary(dev);
},
prog.devices());
break;
diff --git a/src/gallium/state_trackers/clover/core/program.cpp
b/src/gallium/state_trackers/clover/core/program.cpp
index 3aaa652..b0c902c 100644
--- a/src/gallium/state_trackers/clover/core/program.cpp
+++ b/src/gallium/state_trackers/clover/core/program.cpp
@@ -47,6 +47,7 @@ program::build(const ref_vector &devs, const char
*opts) {
for (auto &dev : devs) {
_binaries.erase(&dev);
+ _serialized_binaries.erase(&dev);
_logs.erase(&dev);
_opts.erase(&dev);
@@ -82,6 +83,17 @@ program::binary(const device &dev) const {
return _binaries.find(&dev)->second;
}
+compat::ostream::buffer_t
+program::serialized_binary(const device &dev) {
+ if (_serialized_binaries.count(&dev) == 0) {
+compat::ostream::buffer_t bin;
+compat::ostream s(bin);
+binary(dev).serialize(s);
+_serialized_binaries.insert({&dev, bin});
+ }
+ return _serialized_binaries.find(&dev)->second;
+}
+
cl_build_status
program::build_status(const device &dev) const {
if (_binaries.count(&dev))
diff --git a/src/gallium/state_trackers/clover/core/program.hpp
b/src/gallium/state_trackers/clover/core/program.hpp
index 1081454..6edbe2a 100644
--- a/src/gallium/state_trackers/clover/core/program.hpp
+++ b/src/gallium/state_trackers/clover/core/program.hpp
@@ -54,6 +54,7 @@ namespace clover {
device_range devices() const;
const module &binary(const device &dev) const;
+ compat::ostream::buffer_t serialized_binary(const device &dev);
cl_build_status build_status(const device &dev) const;
std::string build_opts(const device &dev) const;
std::string build_log(const device &dev) const;
@@ -65,6 +66,7 @@ namespace clover {
private:
std::vector> _devices;
std::map _binaries;
+ std::map _serialized_binaries;
std::map _logs;
std::map _opts;
std::string _source;
--
1.8.1.5
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[Mesa-dev] [PATCH] meta_blit: properly compute texture width for the CopyTexSubImage fallback
---
src/mesa/drivers/common/meta_blit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/common/meta_blit.c
b/src/mesa/drivers/common/meta_blit.c
index aa12e04..2b99b99 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -407,7 +407,7 @@ blitframebuffer_texture(struct gl_context *ctx,
}
} else {
GLenum tex_base_format;
- int srcW = abs(srcY1 - srcY0);
+ int srcW = abs(srcX1 - srcX0);
int srcH = abs(srcY1 - srcY0);
/* Fall back to doing a CopyTexSubImage to get the destination
* renderbuffer into a texture.
--
2.0.0
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Re: [Mesa-dev] [PATCH] meta_blit: properly compute texture width for the CopyTexSubImage fallback
On 06/13/2014 01:17 PM, Jason Ekstrand wrote:
---
src/mesa/drivers/common/meta_blit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/common/meta_blit.c
b/src/mesa/drivers/common/meta_blit.c
index aa12e04..2b99b99 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -407,7 +407,7 @@ blitframebuffer_texture(struct gl_context *ctx,
}
} else {
GLenum tex_base_format;
- int srcW = abs(srcY1 - srcY0);
+ int srcW = abs(srcX1 - srcX0);
int srcH = abs(srcY1 - srcY0);
/* Fall back to doing a CopyTexSubImage to get the destination
* renderbuffer into a texture.
Reviewed-by: Brian Paul
I suspect this would apply to at least the 10.2 stable branch also. So,
please tag with:
Cc: mesa-sta...@lists.freedesktop.org
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Re: [Mesa-dev] [PATCH] meta_blit: properly compute texture width for the CopyTexSubImage fallback
Nice find. Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeon/compute: Always report at least 1 compute unit
Hi,
Looks good to me.
-Bruno
On Fri, 2014-06-13 at 12:58 -0400, Tom Stellard wrote:
> Some apps will abort if they detect 0 compute units. This fixes
> crashes in some OpenCV tests.
> ---
> src/gallium/drivers/radeon/r600_pipe_common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 4b9d31c..1911cde 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -523,7 +523,7 @@ static int r600_get_compute_param(struct pipe_screen
> *screen,
> case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
> if (ret) {
> uint32_t *max_compute_units = ret;
> - *max_compute_units = rscreen->info.max_compute_units;
> + *max_compute_units =
> MAX2(rscreen->info.max_compute_units, 1);
> }
> return sizeof(uint32_t);
>
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Re: [Mesa-dev] [PATCH] meta_blit: properly compute texture width for the CopyTexSubImage fallback
On Fri, Jun 13, 2014 at 12:20 PM, Brian Paul wrote:
> On 06/13/2014 01:17 PM, Jason Ekstrand wrote:
>
>> ---
>> src/mesa/drivers/common/meta_blit.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/drivers/common/meta_blit.c
>> b/src/mesa/drivers/common/meta_blit.c
>> index aa12e04..2b99b99 100644
>> --- a/src/mesa/drivers/common/meta_blit.c
>> +++ b/src/mesa/drivers/common/meta_blit.c
>> @@ -407,7 +407,7 @@ blitframebuffer_texture(struct gl_context *ctx,
>> }
>> } else {
>> GLenum tex_base_format;
>> - int srcW = abs(srcY1 - srcY0);
>> + int srcW = abs(srcX1 - srcX0);
>> int srcH = abs(srcY1 - srcY0);
>> /* Fall back to doing a CopyTexSubImage to get the destination
>> * renderbuffer into a texture.
>>
>>
> Reviewed-by: Brian Paul
>
> I suspect this would apply to at least the 10.2 stable branch also. So,
> please tag with:
>
> Cc: mesa-sta...@lists.freedesktop.org
>
What do you mean? Do you want me to re-send with the CC? Forward?
Thanks,
--Jason Ekstrand
>
>
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Re: [Mesa-dev] [PATCH] meta_blit: properly compute texture width for the CopyTexSubImage fallback
On Fri, Jun 13, 2014 at 12:47 PM, Jason Ekstrand wrote:
> On Fri, Jun 13, 2014 at 12:20 PM, Brian Paul wrote:
>> On 06/13/2014 01:17 PM, Jason Ekstrand wrote:
>>>
>>> ---
>>> src/mesa/drivers/common/meta_blit.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/src/mesa/drivers/common/meta_blit.c
>>> b/src/mesa/drivers/common/meta_blit.c
>>> index aa12e04..2b99b99 100644
>>> --- a/src/mesa/drivers/common/meta_blit.c
>>> +++ b/src/mesa/drivers/common/meta_blit.c
>>> @@ -407,7 +407,7 @@ blitframebuffer_texture(struct gl_context *ctx,
>>> }
>>> } else {
>>> GLenum tex_base_format;
>>> - int srcW = abs(srcY1 - srcY0);
>>> + int srcW = abs(srcX1 - srcX0);
>>> int srcH = abs(srcY1 - srcY0);
>>> /* Fall back to doing a CopyTexSubImage to get the destination
>>> * renderbuffer into a texture.
>>>
>>
>> Reviewed-by: Brian Paul
>>
>> I suspect this would apply to at least the 10.2 stable branch also. So,
>> please tag with:
>>
>> Cc: mesa-sta...@lists.freedesktop.org
>
> What do you mean? Do you want me to re-send with the CC? Forward?
Add this to the commit message before pushing. No need to re-send, as
there are scripts that scan the log.
Cc: "10.2"
-Jordan
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Re: [Mesa-dev] [PATCH 11/18] glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().
Right, this happens because ir_emit_vertex doesn't take a proper
operand, so it can't keep it alive.
What I think you want to do is change the stream in ir_emit_vertex and
ir_end_primitive to be a pointer to ir_rvalue (and apply the various
tweaks required to consider it alive; have rvalue visitors descend
into it; etc) then emit:
(function EmitStreamVertex
(signature void
(parameters
(declare (const_in ) int stream)
)
(
(emit-vertex (var_ref stream))
))
)
which would inline in your case to
(declare () int stream)
(assign (x) (var_ref stream) (constant int (0)) )
(emit-vertex (var_ref stream))
and then after constant propagation,
(emit-vertex (constant int (0)) )
which you can then pick out in your later visitors just as easily as
you can with the integer you're currently storing.
On Fri, Jun 13, 2014 at 11:52 PM, Iago Toral wrote:
> On Fri, 2014-06-13 at 10:28 +0200, Iago Toral wrote:
>> I forgot to add an important piece of info. I also had to add this in
>> the opt_dead_code.cpp, do_dead_code():
>>
>> if (strcmp(entry->var->name, "stream") == 0)
>> continue;
>>
>> without that, the variable referenced by ir_emit_vertex() gets trashed
>> anyway, whether the ralloc context in link_shaders is detroyed or not.
>
> The variable is killed because it is not used, as I was anticipating in
> my patch, but I don't think the optimization passes are broken, I think
> this is expected to happen:
>
> This is the code generated for EmitStreamVertex(0) after function
> inlining:
>
> (declare () int stream)
> (assign (x) (var_ref stream) (constant int (0)) )
> (emit-vertex)
>
> (...)
>
> (function EmitStreamVertex
> (signature void
> (parameters
> (declare (const_in ) int stream)
> )
> (
> (emit-vertex)
> ))
> )
>
> And this is after the dead code elimination passes (dead_code and
> dead_code_local), first the assignment is removed:
>
> (declare () int stream)
> (emit-vertex)
>
> And finally, in a second pass, it removes the declaration too, leaving:
>
> (emit-vertex)
>
> Seems to make sense: it is killing a variable that is, at this stage,
> not used for anything. So, as I was saying in the original patch, I
> think we can't do EmitStreamVertex(n) like any other built-in function
> because we won't be using its input parameter in the body of the
> function for anything, the variable's value is to be used in the visitor
> when it is time to generate the native code and that happens after the
> optimization passes, so we need to grab its constant value before the
> optimization passes (as my original patch did) or we have to find a way
> to tell the optimization passes that it should not touch this variable
> specifically (and then we would still have to figure out how to access
> that temporary variable holding the stream value from the visitor).
>
> Iago
>
>> Iago
>>
>> On Fri, 2014-06-13 at 10:09 +0200, Iago Toral wrote:
>> > After debugging I have more information about what is going on. There
>> > are two problems, one is that the stream variable in ir_emit_vertex gets
>> > trashed and the other one is that even if we manage to avoid that it
>> > won't get its value assigned. I explain how these two come to happen
>> > below and maybe someone can point me to what I am doing wrong:
>> >
>> > first, this is how I am defining EmitStreamVertex():
>> >
>> > ir_function_signature *
>> > builtin_builder::_EmitStreamVertex(builtin_available_predicate avail,
>> >const glsl_type *stream_type)
>> > {
>> >ir_variable *stream =
>> > new(mem_ctx) ir_variable(stream_type, "stream", ir_var_const_in);
>> >MAKE_SIG(glsl_type::void_type, avail, 1, stream);
>> >ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
>> >ir->stream = var_ref(stream);
>> >body.emit(ir);
>> >return sig;
>> > }
>> >
>> > The pattern is similar to other built-in functions. Notice how
>> > ir_stream_vertex will take a reference to the input stream variable.
>> >
>> > And this is how I am defining ir_emit_vertex:
>> >
>> > class ir_emit_vertex : public ir_instruction {
>> > public:
>> > ir_emit_vertex() : ir_instruction(ir_type_emit_vertex), stream(NULL) {}
>> >
>> > virtual void accept(ir_visitor *v) { v->visit(this); }
>> >
>> > virtual ir_emit_vertex *clone(void *mem_ctx, struct hash_table *ht)
>> > const
>> > {
>> > ir_emit_vertex *ir = new(mem_ctx) ir_emit_vertex();
>> > if (this->stream)
>> >ir->stream = this->stream->clone(mem_ctx, ht);
>> > return ir;
>> > }
>> >
>> > virtual ir_visitor_status accept(ir_hierarchical_visitor *);
>> > ir_dereference_variable *stream;
>> > };
>> >
>> > Again, I don't see anything special as it follows the same pattern as
>> > other IR definitions in ir.h.
>> >
>> > If I only do this, then, by the time I reach
>> > vec4_gs_visitor::visit(ir_emit_vertex *ir), ir->stream has been trashed.
>> >
>> > ¿Is this expected? ¿Am I missing something in EmitStreamVert
[Mesa-dev] [PATCH 5/9] r600g/compute: avoid problems when promoting items mapped for reading
Acording to the OpenCL spec, it is possible to have a buffer mapped
for reading and at read from it using commands or buffers.
With this we can keep the mapping (that exists against the
temporary item) and read with a kernel (from the item we have
just added to the pool) without problems.
---
src/gallium/drivers/r600/compute_memory_pool.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index 1da4609..e1f9c88 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -369,10 +369,16 @@ int compute_memory_promote_item(struct
compute_memory_pool *pool,
0, &(struct pipe_box) {.width = item->size_in_dw * 4,
.height = 1, .depth = 1});
- pool->screen->b.b.resource_destroy(
- (struct pipe_screen *)pool->screen,
- (struct pipe_resource *)item->real_buffer);
- item->real_buffer = NULL;
+ /* We check if the item is mapped for reading.
+* In this case, we need to keep the temporary buffer 'alive'
+* because it is possible to keep a map active for reading
+* while a kernel (that reads from it) executes */
+ if (!(item->status & ITEM_MAPPED_FOR_READING)) {
+ pool->screen->b.b.resource_destroy(
+ (struct pipe_screen *)pool->screen,
+ (struct pipe_resource *)item->real_buffer);
+ item->real_buffer = NULL;
+ }
return 0;
}
--
2.0.0
___
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/9] r600g/compute: Add an intermediate resource for OpenCL buffers
This patch changes completely the way buffers are added to the
compute_memory_pool. Before this, whenever we were going to
map a buffer or write to or read from it, it would get placed
into the pool. Now, every unallocated buffer has its own
r600_resource until it is allocated in the pool.
NOTE: This patch also increase the GPU memory usage at the moment
of putting every buffer in it's place. More or less, the memory
usage is ~2x(sum of every buffer size)
v2: Cleanup
---
src/gallium/drivers/r600/compute_memory_pool.c | 21 -
src/gallium/drivers/r600/compute_memory_pool.h | 2 ++
src/gallium/drivers/r600/evergreen_compute.c | 18 +-
3 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index ec8c470..94ddcde 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -71,7 +71,6 @@ static void compute_memory_pool_init(struct
compute_memory_pool * pool,
if (pool->shadow == NULL)
return;
- pool->next_id = 1;
pool->size_in_dw = initial_size_in_dw;
pool->bo = (struct
r600_resource*)r600_compute_buffer_alloc_vram(pool->screen,
pool->size_in_dw * 4);
@@ -365,6 +364,18 @@ int compute_memory_finalize_pending(struct
compute_memory_pool* pool,
pool->item_list = item;
}
+ ((struct r600_context *)pipe)->b.b.resource_copy_region(pipe,
+ (struct pipe_resource *)pool->bo,
+ 0, item->start_in_dw * 4, 0 ,0,
+ (struct pipe_resource *)item->real_buffer,
+ 0, &(struct pipe_box) {.width =
item->size_in_dw * 4,
+ .height = 1, .depth = 1});
+
+ pool->screen->b.b.resource_destroy(
+ (struct pipe_screen *)pool->screen,
+ (struct pipe_resource *)item->real_buffer);
+ item->real_buffer = NULL;
+
allocated += item->size_in_dw;
}
@@ -393,6 +404,12 @@ void compute_memory_free(struct compute_memory_pool* pool,
int64_t id)
item->next->prev = item->prev;
}
+ if (item->real_buffer) {
+ pool->screen->b.b.resource_destroy(
+ (struct pipe_screen
*)pool->screen,
+ (struct pipe_resource
*)item->real_buffer);
+ }
+
free(item);
return;
@@ -426,6 +443,8 @@ struct compute_memory_item* compute_memory_alloc(
new_item->start_in_dw = -1; /* mark pending */
new_item->id = pool->next_id++;
new_item->pool = pool;
+ new_item->real_buffer = (struct
r600_resource*)r600_compute_buffer_alloc_vram(
+ pool->screen,
size_in_dw * 4);
if (pool->item_list) {
for (last_item = pool->item_list; last_item->next;
diff --git a/src/gallium/drivers/r600/compute_memory_pool.h
b/src/gallium/drivers/r600/compute_memory_pool.h
index c711c59..e94159c 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.h
+++ b/src/gallium/drivers/r600/compute_memory_pool.h
@@ -38,6 +38,8 @@ struct compute_memory_item
int64_t start_in_dw; ///Start pointer in dwords relative in the pool bo
int64_t size_in_dw; ///Size of the chunk in dwords
+ struct r600_resource *real_buffer;
+
struct compute_memory_pool* pool;
struct compute_memory_item* prev;
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index a2abf15..c152e54 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -958,6 +958,17 @@ void *r600_compute_global_transfer_map(
struct r600_resource_global* buffer =
(struct r600_resource_global*)resource;
+ struct pipe_resource *dst;
+ unsigned offset = box->x;
+
+ if (buffer->chunk->real_buffer) {
+ dst = (struct pipe_resource*)buffer->chunk->real_buffer;
+ }
+ else {
+ dst = (struct pipe_resource*)buffer->chunk->pool->bo;
+ offset += (buffer->chunk->start_in_dw * 4);
+ }
+
COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n"
"level = %u, usage = %u, box(x = %u, y = %u, z = %u "
"width = %u, height = %u, depth = %u)\n", level, usage,
@@ -967,8 +978,6 @@ void *r600_compute_global_transfer_map(
"%u (box.x)\n", buffer->chunk->id, box->x);
- compute_memory_finali
[Mesa-dev] [PATCH 3/9] r600g/compute: divide the item list in two
Now we will have a list with the items that are in the pool
(item_list) and the items that are outside it (unallocated_list)
---
src/gallium/drivers/r600/compute_memory_pool.c | 99 +-
src/gallium/drivers/r600/compute_memory_pool.h | 1 +
2 files changed, 49 insertions(+), 51 deletions(-)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index 94ddcde..5a5ef12 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -108,13 +108,11 @@ int64_t compute_memory_prealloc_chunk(
size_in_dw);
for (item = pool->item_list; item; item = item->next) {
- if (item->start_in_dw > -1) {
- if (last_end + size_in_dw <= item->start_in_dw) {
- return last_end;
- }
-
- last_end = item->start_in_dw + align(item->size_in_dw,
ITEM_ALIGNMENT);
+ if (last_end + size_in_dw <= item->start_in_dw) {
+ return last_end;
}
+
+ last_end = item->start_in_dw + align(item->size_in_dw,
ITEM_ALIGNMENT);
}
if (pool->size_in_dw - last_end < size_in_dw) {
@@ -226,7 +224,6 @@ void compute_memory_shadow(struct compute_memory_pool* pool,
int compute_memory_finalize_pending(struct compute_memory_pool* pool,
struct pipe_context * pipe)
{
- struct compute_memory_item *pending_list = NULL, *end_p = NULL;
struct compute_memory_item *item, *next;
int64_t allocated = 0;
@@ -244,45 +241,16 @@ int compute_memory_finalize_pending(struct
compute_memory_pool* pool,
item->size_in_dw, item->size_in_dw * 4);
}
- /* Search through the list of memory items in the pool */
+ /* Calculate the total allocated size */
for (item = pool->item_list; item; item = next) {
next = item->next;
+ allocated += align(item->size_in_dw, ITEM_ALIGNMENT);
+ }
- /* Check if the item is pending. */
- if (item->start_in_dw == -1) {
- /* It is pending, so add it to the pending_list... */
- if (end_p) {
- end_p->next = item;
- }
- else {
- pending_list = item;
- }
-
- /* ... and then remove it from the item list. */
- if (item->prev) {
- item->prev->next = next;
- }
- else {
- pool->item_list = next;
- }
-
- if (next) {
- next->prev = item->prev;
- }
-
- /* This sequence makes the item be at the end of the
list */
- item->prev = end_p;
- item->next = NULL;
- end_p = item;
-
- /* Update the amount of space we will need to allocate.
*/
- unallocated += item->size_in_dw+1024;
- }
- else {
- /* The item is not pending, so update the amount of
space
-* that has already been allocated. */
- allocated += item->size_in_dw;
- }
+ /* Calculate the total unallocated size */
+ for (item = pool->unallocated_list; item; item = next) {
+ next = item->next;
+ unallocated += align(item->size_in_dw, ITEM_ALIGNMENT);
}
/* If we require more space than the size of the pool, then grow the
@@ -302,15 +270,15 @@ int compute_memory_finalize_pending(struct
compute_memory_pool* pool,
* In this case, there are 300 units of free space in the pool, but
* they aren't contiguous, so it will be impossible to allocate Item D.
*/
- if (pool->size_in_dw < allocated+unallocated) {
- err = compute_memory_grow_pool(pool, pipe,
allocated+unallocated);
+ if (pool->size_in_dw < allocated + unallocated) {
+ err = compute_memory_grow_pool(pool, pipe, allocated +
unallocated);
if (err == -1)
return -1;
}
- /* Loop through all the pending items, allocate space for them and
-* add them back to the item_list. */
- for (item = pending_list; item; item = next) {
+ /* Loop through all the unallocated items, allocate space for them
+* and add them to the item_list. */
+ for (item = pool->unallocated_list; item; item = next) {
next = item->next;
/* Search for free space in the pool for this item. */
@@ -379,6 +347,8 @@ int compute_memo
[Mesa-dev] [PATCH 0/9] [RFC] Solve the mapping bug
Hi, This is my latest attempt to fix the mapping bug and, so far, it seems that it is resolved. This series changes completely how OpenCL buffers are handled by the r600g driver. Before this, we would add them directly to a pool, and this pool would grow whenever we needed more space. But this process implied destroying the pool and creating a new one. There could be cases where a buffer would be mapped and the pool would grow, leaving one side of the mapping pointed to where the item was. This is the 'mapping bug' Now, Items will have an intermediate resource, where all mappings can be done, and when a buffer is going to be used with a kernel it is promoted to the pool. In the case where a promoted item is going to be mapped, it is previously demoted, so even if the pool changes its location due to growing, the map remains valid. In the case of a buffer mapped for reading, and used by a kernel to read from it, we will duplicate this buffer, having the intermediate buffer, where the user has its map, and an item in the pool, which is the one that the kernel is going to use. As a summary: Patches 1-7: These are the main part of the series, and solve the mapping bug. Patch 8: Introduces some utils for managing the pool's lists Patch 9: This is just a proof of concept for avoiding transfers GPU <-> GPU when using all CL Read/Write functions. In fact, it CAN'T land as it is because PIPE_TRANSFER_MAP_DIRECTLY collides with CL_MAP_WRITE_INVALIDATE_REGION Please review and Thanks :) Bruno Jiménez (9): r600g/compute: Add an intermediate resource for OpenCL buffers r600g/compute: Add statuses to the compute_memory_items r600g/compute: divide the item list in two r600g/compute: only move to the pool the buffers marked for promoting r600g/compute: avoid problems when promoting items mapped for reading r600g/compute: implement compute_memory_demote_item r600g/compute: map only against intermediate buffers r600g/compute: add util functions to add and remove items from lists r600g/compute: avoid demoting items when reading/writing src/gallium/drivers/r600/compute_memory_pool.c | 313 + src/gallium/drivers/r600/compute_memory_pool.h | 18 +- src/gallium/drivers/r600/evergreen_compute.c | 38 ++- src/gallium/state_trackers/clover/api/transfer.cpp | 4 +- .../state_trackers/clover/core/resource.cpp| 2 + 5 files changed, 255 insertions(+), 120 deletions(-) -- 2.0.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 8/9] r600g/compute: add util functions to add and remove items from lists
---
src/gallium/drivers/r600/compute_memory_pool.c | 158 -
1 file changed, 78 insertions(+), 80 deletions(-)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index 624b50d..26b9f98 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -43,6 +43,73 @@
#include
#define ITEM_ALIGNMENT 1024
+
+static inline void list_add_item_front(struct compute_memory_item **list,
+struct compute_memory_item *item)
+{
+ if (*list != NULL) {
+ item->next = *list;
+ (*list)->prev = item;
+ }
+ else {
+ item->next = NULL;
+ }
+
+ *list = item;
+ item->prev = NULL;
+}
+
+static inline void list_add_item_tail(struct compute_memory_item **list,
+struct compute_memory_item *item)
+{
+ struct compute_memory_item *last_item = NULL;
+
+ if (*list != NULL) {
+ for (last_item = *list; last_item->next != NULL; last_item =
last_item->next);
+
+ last_item->next = item;
+ item->prev = last_item;
+ }
+ else {
+ *list = item;
+ item->prev = NULL;
+ }
+
+ item->next = NULL;
+}
+
+static inline void list_add_item_after(struct compute_memory_item **list,
+ struct compute_memory_item *item, struct compute_memory_item
*pos)
+{
+ if (pos == NULL) {
+ list_add_item_front(list, item);
+ }
+ else {
+ if (pos->next != NULL) {
+ pos->next->prev = item;
+ }
+
+ item->prev = pos;
+ item->next = pos->next;
+ pos->next = item;
+ }
+}
+
+static inline void list_remove_item(struct compute_memory_item **list,
+ struct compute_memory_item *item)
+{
+ if (item->prev == NULL) {
+ *list = item->next;
+ }
+ else {
+ item->prev->next = item->next;
+ }
+
+ if (item->next != NULL) {
+ item->next->prev = item->prev;
+ }
+}
+
/**
* Creates a new pool
*/
@@ -299,6 +366,7 @@ int compute_memory_promote_item(struct compute_memory_pool
*pool,
struct compute_memory_item *item, struct pipe_context *pipe,
int64_t allocated)
{
+ struct compute_memory_item *pos;
int64_t start_in_dw;
int err = 0;
@@ -327,40 +395,12 @@ int compute_memory_promote_item(struct
compute_memory_pool *pool,
item->size_in_dw, item->size_in_dw * 4);
/* Remove the item from the unallocated list */
- if (item->prev == NULL)
- pool->unallocated_list = item->next;
- else
- item->prev->next = item->next;
-
- if (item->next != NULL)
- item->next->prev = item->prev;
+ list_remove_item(&pool->unallocated_list, item);
+ /* Add it back to the item_list */
+ pos = compute_memory_postalloc_chunk(pool, start_in_dw);
+ list_add_item_after(&pool->item_list, item, pos);
item->start_in_dw = start_in_dw;
- item->next = NULL;
- item->prev = NULL;
-
- if (pool->item_list) {
- struct compute_memory_item *pos;
-
- pos = compute_memory_postalloc_chunk(pool, start_in_dw);
- if (pos) {
- item->prev = pos;
- item->next = pos->next;
- pos->next = item;
- if (item->next) {
- item->next->prev = item;
- }
- } else {
- /* Add item to the front of the list */
- item->next = pool->item_list;
- item->prev = pool->item_list->prev;
- pool->item_list->prev = item;
- pool->item_list = item;
- }
- }
- else {
- pool->item_list = item;
- }
((struct r600_context *)pipe)->b.b.resource_copy_region(pipe,
(struct pipe_resource *)pool->bo,
@@ -387,26 +427,11 @@ void compute_memory_demote_item(struct
compute_memory_pool *pool,
struct compute_memory_item *item, struct pipe_context *pipe)
{
/* First, we remove the item from the item_list */
- if (item->prev == NULL)
- pool->item_list = item->next;
- else
- item->prev->next = item->next;
-
- if (item->next != NULL)
- item->next->prev = item->prev;
-
+ list_remove_item(&pool->item_list, item);
/* Now we add it to the beginning of the unallocated list
* NOTE: we could also add it to the end, but this is easier */
- item->next = NULL;
- item->prev = NULL;
- if (pool->unallocated_list) {
- item->next = pool->unallocated_list;
-
[Mesa-dev] [PATCH 9/9] r600g/compute: avoid demoting items when reading/writing
All the *Enqueue* functions that read/write buffers (except
clEnqueueCopyBuffer) would map the associated resource, making
it to be demoted if it was in the pool.
But we possitively know that this transfer will end before
any kernel is launched, so there's no need to demote it.
NOTE: As a proof of concept I have used PIPE_TRANSFER_MAP_DIRECTLY,
but it collides with OpenCL 1.2 CL_MAP_WRITE_INVALIDATE_REGION,
so we will have to find another bitfield to use.
---
src/gallium/drivers/r600/evergreen_compute.c| 20 +++-
src/gallium/state_trackers/clover/api/transfer.cpp | 4 ++--
src/gallium/state_trackers/clover/core/resource.cpp | 2 ++
3 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index e5967b5..794cbe6 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -967,18 +967,28 @@ void *r600_compute_global_transfer_map(
struct r600_resource_global* buffer =
(struct r600_resource_global*)resource;
- struct pipe_resource *dst;
+ struct pipe_resource *dst =
+ (struct pipe_resource *) buffer->chunk->real_buffer;
unsigned offset = box->x;
+ /* If the item is already in the pool, and we are going
+* to read/write it, map it directly without demoting it */
if (buffer->chunk->start_in_dw != -1) {
- compute_memory_demote_item(pool, buffer->chunk, ctx_);
+ if (usage & PIPE_TRANSFER_MAP_DIRECTLY) {
+ dst = (struct pipe_resource *) buffer->chunk->pool->bo;
+ offset += (buffer->chunk->start_in_dw * 4);
+ }
+ else {
+ compute_memory_demote_item(pool, buffer->chunk, ctx_);
+ dst = (struct pipe_resource *)
buffer->chunk->real_buffer;
+ }
}
- dst = (struct pipe_resource*)buffer->chunk->real_buffer;
-
- if (usage & PIPE_TRANSFER_READ)
+ if ((usage & PIPE_TRANSFER_READ) && !(usage &
PIPE_TRANSFER_MAP_DIRECTLY))
buffer->chunk->status |= ITEM_MAPPED_FOR_READING;
+ usage &= ~PIPE_TRANSFER_MAP_DIRECTLY;
+
COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n"
"level = %u, usage = %u, box(x = %u, y = %u, z = %u "
"width = %u, height = %u, depth = %u)\n", level, usage,
diff --git a/src/gallium/state_trackers/clover/api/transfer.cpp
b/src/gallium/state_trackers/clover/api/transfer.cpp
index 404ceb0..032542e 100644
--- a/src/gallium/state_trackers/clover/api/transfer.cpp
+++ b/src/gallium/state_trackers/clover/api/transfer.cpp
@@ -174,8 +174,8 @@ namespace {
static mapping
get(command_queue &q, T obj, cl_map_flags flags,
size_t offset, size_t size) {
- return { q, obj->resource(q), flags, true,
- {{ offset }}, {{ size, 1, 1 }} };
+ return { q, obj->resource(q), flags | PIPE_TRANSFER_MAP_DIRECTLY,
+ true, {{ offset }}, {{ size, 1, 1 }} };
}
};
diff --git a/src/gallium/state_trackers/clover/core/resource.cpp
b/src/gallium/state_trackers/clover/core/resource.cpp
index 7b8a40a..bda9847 100644
--- a/src/gallium/state_trackers/clover/core/resource.cpp
+++ b/src/gallium/state_trackers/clover/core/resource.cpp
@@ -174,6 +174,8 @@ mapping::mapping(command_queue &q, resource &r,
pctx(q.pipe) {
unsigned usage = ((flags & CL_MAP_WRITE ? PIPE_TRANSFER_WRITE : 0 ) |
(flags & CL_MAP_READ ? PIPE_TRANSFER_READ : 0 ) |
+ (flags & PIPE_TRANSFER_MAP_DIRECTLY ?
+ PIPE_TRANSFER_MAP_DIRECTLY : 0 ) |
(!blocking ? PIPE_TRANSFER_UNSYNCHRONIZED : 0));
p = pctx->transfer_map(pctx, r.pipe, 0, usage,
--
2.0.0
___
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http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/9] r600g/compute: Add statuses to the compute_memory_items
These statuses will help track whether the items are mapped
or if they should be promoted to or demoted from the pool
---
src/gallium/drivers/r600/compute_memory_pool.h | 7 ++-
src/gallium/drivers/r600/evergreen_compute.c | 12
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.h
b/src/gallium/drivers/r600/compute_memory_pool.h
index e94159c..166093d 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.h
+++ b/src/gallium/drivers/r600/compute_memory_pool.h
@@ -27,13 +27,18 @@
#include
+#define ITEM_MAPPED_FOR_READING (1<<0)
+#define ITEM_MAPPED_FOR_WRITING (1<<1)
+#define ITEM_FOR_PROMOTING (1<<2)
+#define ITEM_FOR_DEMOTING (1<<3)
+
struct compute_memory_pool;
struct compute_memory_item
{
int64_t id; ///ID of the memory chunk
- int untouched; ///True if the memory contains only junk, no need to
save it for defrag
+ uint32_t status; ///Will track the status of the item
int64_t start_in_dw; ///Start pointer in dwords relative in the pool bo
int64_t size_in_dw; ///Size of the chunk in dwords
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index c152e54..9123a40 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -659,6 +659,15 @@ static void evergreen_set_global_binding(
return;
}
+ /* We mark these items for promotion to the pool if they
+* aren't already there */
+ for (int i = 0; i < n; i++) {
+ struct compute_memory_item *item = buffers[i]->chunk;
+
+ if (item->start_in_dw == -1)
+ buffers[i]->chunk->status |= ITEM_FOR_PROMOTING;
+ }
+
compute_memory_finalize_pending(pool, ctx_);
for (int i = 0; i < n; i++)
@@ -969,6 +978,9 @@ void *r600_compute_global_transfer_map(
offset += (buffer->chunk->start_in_dw * 4);
}
+ if (usage & PIPE_TRANSFER_READ)
+ buffer->chunk->status |= ITEM_MAPPED_FOR_READING;
+
COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n"
"level = %u, usage = %u, box(x = %u, y = %u, z = %u "
"width = %u, height = %u, depth = %u)\n", level, usage,
--
2.0.0
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[Mesa-dev] [PATCH 4/9] r600g/compute: only move to the pool the buffers marked for promoting
---
src/gallium/drivers/r600/compute_memory_pool.c | 140 +++--
src/gallium/drivers/r600/compute_memory_pool.h | 5 +
2 files changed, 87 insertions(+), 58 deletions(-)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index 5a5ef12..1da4609 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -229,8 +229,6 @@ int compute_memory_finalize_pending(struct
compute_memory_pool* pool,
int64_t allocated = 0;
int64_t unallocated = 0;
- int64_t start_in_dw = 0;
-
int err = 0;
COMPUTE_DBG(pool->screen, "* compute_memory_finalize_pending()\n");
@@ -247,10 +245,12 @@ int compute_memory_finalize_pending(struct
compute_memory_pool* pool,
allocated += align(item->size_in_dw, ITEM_ALIGNMENT);
}
- /* Calculate the total unallocated size */
+ /* Calculate the total unallocated size of the items that
+* will be promoted to the pool */
for (item = pool->unallocated_list; item; item = next) {
next = item->next;
- unallocated += align(item->size_in_dw, ITEM_ALIGNMENT);
+ if (item->status & ITEM_FOR_PROMOTING)
+ unallocated += align(item->size_in_dw, ITEM_ALIGNMENT);
}
/* If we require more space than the size of the pool, then grow the
@@ -276,83 +276,107 @@ int compute_memory_finalize_pending(struct
compute_memory_pool* pool,
return -1;
}
- /* Loop through all the unallocated items, allocate space for them
-* and add them to the item_list. */
+ /* Loop through all the unallocated items, check if they are marked
+* for promoting, allocate space for them and add them to the
item_list. */
for (item = pool->unallocated_list; item; item = next) {
next = item->next;
- /* Search for free space in the pool for this item. */
- while ((start_in_dw=compute_memory_prealloc_chunk(pool,
- item->size_in_dw)) == -1) {
- int64_t need = item->size_in_dw+2048 -
- (pool->size_in_dw - allocated);
-
- if (need < 0) {
- need = pool->size_in_dw / 10;
- }
+ if (item->status & ITEM_FOR_PROMOTING) {
+ err = compute_memory_promote_item(pool, item, pipe,
allocated);
+ item->status ^= ITEM_FOR_PROMOTING;
- need = align(need, ITEM_ALIGNMENT);
-
- err = compute_memory_grow_pool(pool,
- pipe,
- pool->size_in_dw + need);
+ allocated += align(item->size_in_dw, ITEM_ALIGNMENT);
if (err == -1)
return -1;
}
- COMPUTE_DBG(pool->screen, " + Found space for Item %p id = %u "
+ }
+
+ return 0;
+}
+
+int compute_memory_promote_item(struct compute_memory_pool *pool,
+ struct compute_memory_item *item, struct pipe_context *pipe,
+ int64_t allocated)
+{
+ int64_t start_in_dw;
+ int err = 0;
+
+ /* Search for free space in the pool for this item. */
+ while ((start_in_dw=compute_memory_prealloc_chunk(pool,
+ item->size_in_dw)) == -1) {
+ int64_t need = item->size_in_dw + 2048 -
+ (pool->size_in_dw - allocated);
+
+ if (need < 0) {
+ need = pool->size_in_dw / 10;
+ }
+
+ need = align(need, ITEM_ALIGNMENT);
+
+ err = compute_memory_grow_pool(pool,
+ pipe,
+ pool->size_in_dw + need);
+
+ if (err == -1)
+ return -1;
+ }
+ COMPUTE_DBG(pool->screen, " + Found space for Item %p id = %u "
"start_in_dw = %u (%u bytes) size_in_dw = %u (%u
bytes)\n",
item, item->id, start_in_dw, start_in_dw * 4,
item->size_in_dw, item->size_in_dw * 4);
- item->start_in_dw = start_in_dw;
- item->next = NULL;
- item->prev = NULL;
-
- if (pool->item_list) {
- struct compute_memory_item *pos;
-
- pos = compute_memory_postalloc_chunk(pool, start_in_dw);
- if (pos) {
- item->prev = pos;
- item->next = pos->next;
- pos->next = item;
- if (item->next) {
-
[Mesa-dev] [PATCH 7/9] r600g/compute: map only against intermediate buffers
With this we can assure that mapped buffers will never change
its position when relocating the pool.
This patch should finally solve the mapping bug.
---
src/gallium/drivers/r600/evergreen_compute.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 9123a40..e5967b5 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -970,14 +970,12 @@ void *r600_compute_global_transfer_map(
struct pipe_resource *dst;
unsigned offset = box->x;
- if (buffer->chunk->real_buffer) {
- dst = (struct pipe_resource*)buffer->chunk->real_buffer;
- }
- else {
- dst = (struct pipe_resource*)buffer->chunk->pool->bo;
- offset += (buffer->chunk->start_in_dw * 4);
+ if (buffer->chunk->start_in_dw != -1) {
+ compute_memory_demote_item(pool, buffer->chunk, ctx_);
}
+ dst = (struct pipe_resource*)buffer->chunk->real_buffer;
+
if (usage & PIPE_TRANSFER_READ)
buffer->chunk->status |= ITEM_MAPPED_FOR_READING;
--
2.0.0
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[Mesa-dev] [PATCH 6/9] r600g/compute: implement compute_memory_demote_item
This function will be used when we want to map an item
that it's already in the pool.
---
src/gallium/drivers/r600/compute_memory_pool.c | 45 ++
src/gallium/drivers/r600/compute_memory_pool.h | 3 ++
2 files changed, 48 insertions(+)
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index e1f9c88..624b50d 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -383,6 +383,51 @@ int compute_memory_promote_item(struct compute_memory_pool
*pool,
return 0;
}
+void compute_memory_demote_item(struct compute_memory_pool *pool,
+ struct compute_memory_item *item, struct pipe_context *pipe)
+{
+ /* First, we remove the item from the item_list */
+ if (item->prev == NULL)
+ pool->item_list = item->next;
+ else
+ item->prev->next = item->next;
+
+ if (item->next != NULL)
+ item->next->prev = item->prev;
+
+
+ /* Now we add it to the beginning of the unallocated list
+* NOTE: we could also add it to the end, but this is easier */
+ item->next = NULL;
+ item->prev = NULL;
+ if (pool->unallocated_list) {
+ item->next = pool->unallocated_list;
+ item->next->prev = item;
+ pool->unallocated_list = item;
+ }
+ else
+ pool->unallocated_list = item;
+
+ /* We check if the intermediate buffer exists, and if it
+* doesn't, we create it again */
+ if (item->real_buffer == NULL) {
+ item->real_buffer = (struct
r600_resource*)r600_compute_buffer_alloc_vram(
+ pool->screen, item->size_in_dw * 4);
+ }
+
+ /* We transfer the memory from the item in the pool to the
+* temporary buffer */
+ ((struct r600_context *)pipe)->b.b.resource_copy_region(pipe,
+ (struct pipe_resource *)item->real_buffer,
+ 0, 0, 0, 0,
+ (struct pipe_resource *)pool->bo,
+ 0, &(struct pipe_box) { .x = item->start_in_dw * 4,
+ .width = item->size_in_dw * 4, .height = 1, .depth = 1});
+
+ /* Remember to mark the buffer as 'pending' by setting start_in_dw to
-1 */
+ item->start_in_dw = -1;
+}
+
void compute_memory_free(struct compute_memory_pool* pool, int64_t id)
{
struct compute_memory_item *item, *next;
diff --git a/src/gallium/drivers/r600/compute_memory_pool.h
b/src/gallium/drivers/r600/compute_memory_pool.h
index 6a45fb2..1eb60da 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.h
+++ b/src/gallium/drivers/r600/compute_memory_pool.h
@@ -85,6 +85,9 @@ int compute_memory_promote_item(struct compute_memory_pool
*pool,
struct compute_memory_item *item, struct pipe_context *pipe,
int64_t allocated);
+void compute_memory_demote_item(struct compute_memory_pool *pool,
+ struct compute_memory_item *item, struct pipe_context *pipe);
+
void compute_memory_free(struct compute_memory_pool* pool, int64_t id);
struct compute_memory_item* compute_memory_alloc(struct compute_memory_pool*
pool, int64_t size_in_dw); ///Creates pending allocations
--
2.0.0
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Re: [Mesa-dev] [PATCH] i965/gen8: Align hiz depth clear to 8x4
On Friday, June 13, 2014 12:38:43 PM Topi Pohjolainen wrote:
> This fixes framebuffer_blit_functionality_scissor_blit.test in
> gles3 cts.
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 8c70c62..7f1c23d 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -30,6 +30,17 @@
> #include "brw_defines.h"
>
> /**
> + * The documentation for Broadwell's Hierarchical Depth Buffer Resolve and
for
> + * Depth Buffer Clear mandates the rectangle to be 8x4 aligned.
> + */
> +static void
> +align_rectangle_primitive(uint32_t *width, uint32_t *height)
> +{
> + *width = ALIGN(*width, 8);
> + *height = ALIGN(*height, 4);
> +}
> +
> +/**
> * Helper function to emit depth related command packets.
> */
> static void
> @@ -54,6 +65,8 @@ emit_depth_packets(struct brw_context *brw,
>return;
> }
>
> + align_rectangle_primitive(&width, &height);
> +
> intel_emit_depth_stall_flushes(brw);
>
> /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
> @@ -248,6 +261,8 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
> unsigned rect_width = minify(mt->logical_width0, level);
> unsigned rect_height = minify(mt->logical_height0, level);
>
> + align_rectangle_primitive(&rect_width, &rect_height);
> +
> BEGIN_BATCH(4);
> OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
> OUT_BATCH(0);
>
NAK - unfortunately, this regresses piles and piles of depthstencil-render-
miplevels Piglit tests. I'll look into why - I'm still convinced we need to
do this, we're just probably not doing it quite right.
--Ken
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[Mesa-dev] [PATCH 1/2] glsl/glcpp: Add short-circuiting for || and && in #if/#elif for OpenGL ES.
The GLSL ES Specification 3.00.4 says:
#if, #ifdef, #ifndef, #else, #elif, and #endif are defined to operate
as for C++ except for the following:
...
• Undefined identifiers not consumed by the defined operator do not
default to '0'. Use of such identifiers causes an error.
[Page 11 (page 127 of the PDF file)]
as well as:
The semantics of applying operators in the preprocessor match those
standard in the C++ preprocessor with the following exceptions:
• The 2nd operand in a logical and ('&&') operation is evaluated if
and only if the 1st operand evaluates to non-zero.
• The 2nd operand in a logical or ('||') operation is evaluated if
and only if the 1st operand evaluates to zero.
If an operand is not evaluated, the presence of undefined identifiers
in the operand will not cause an error.
(Note that neither of these deviations from C++ preprocessor behavior apply to
non-ES GLSL, at least as of specfication version 4.30.6).
The first portion of this, (generating an error for an undefined macro in an
(short-circuiting to squelch errors), was not implemented previously, but is
implemented in this commit.
A test is added for "make check" to ensure this behavior.
Note: The change as implemented does make the error message a bit less
precise, (it just states that an undefined macro was encountered, but not the
name of the macro).
---
src/glsl/glcpp/glcpp-parse.y | 106 +++--
src/glsl/glcpp/glcpp.h | 7 ++
.../glcpp/tests/125-es-short-circuit-undefined.c | 27 ++
.../125-es-short-circuit-undefined.c.expected | 30 ++
4 files changed, 140 insertions(+), 30 deletions(-)
create mode 100644 src/glsl/glcpp/tests/125-es-short-circuit-undefined.c
create mode 100644
src/glsl/glcpp/tests/125-es-short-circuit-undefined.c.expected
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 6906e62..4309d26 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -166,7 +166,8 @@ add_builtin_define(glcpp_parser_t *parser, const char
*name, int value);
%expect 0
%token COMMA_FINAL DEFINED ELIF_EXPANDED HASH HASH_DEFINE FUNC_IDENTIFIER
OBJ_IDENTIFIER HASH_ELIF HASH_ELSE HASH_ENDIF HASH_IF HASH_IFDEF HASH_IFNDEF
HASH_LINE HASH_UNDEF HASH_VERSION IDENTIFIER IF_EXPANDED INTEGER INTEGER_STRING
LINE_EXPANDED NEWLINE OTHER PLACEHOLDER SPACE
%token PASTE
-%type expression INTEGER operator SPACE integer_constant
+%type INTEGER operator SPACE integer_constant
+%type expression
%type IDENTIFIER FUNC_IDENTIFIER OBJ_IDENTIFIER INTEGER_STRING OTHER
%type identifier_list
%type preprocessing_token conditional_token
@@ -216,10 +217,14 @@ line:
expanded_line:
IF_EXPANDED expression NEWLINE {
- _glcpp_parser_skip_stack_push_if (parser, & @1, $2);
+ if (parser->is_gles && $2.has_undefined)
+ glcpp_error(& @1, parser, "undefined macro in
expression (illegal in GLES)");
+ _glcpp_parser_skip_stack_push_if (parser, & @1, $2.value);
}
| ELIF_EXPANDED expression NEWLINE {
- _glcpp_parser_skip_stack_change_if (parser, & @1, "elif", $2);
+ if (parser->is_gles && $2.has_undefined)
+ glcpp_error(& @1, parser, "undefined macro in
expression (illegal in GLES)");
+ _glcpp_parser_skip_stack_change_if (parser, & @1, "elif",
$2.value);
}
| LINE_EXPANDED integer_constant NEWLINE {
parser->has_new_line_number = 1;
@@ -412,87 +417,128 @@ integer_constant:
}
expression:
- integer_constant
+ integer_constant {
+ $$.value = $1;
+ $$.has_undefined = false;
+ }
| IDENTIFIER {
+ $$.value = 0;
if (parser->is_gles)
- glcpp_error(& @1, parser, "undefined macro %s in
expression (illegal in GLES)", $1);
- $$ = 0;
+ $$.has_undefined = true;
+ else
+ $$.has_undefined = false;
}
| expression OR expression {
- $$ = $1 || $3;
+ $$.value = $1.value || $3.value;
+
+ /* Short-circuit: Only flag undefined from right side
+* if left side evaluates to false.
+*/
+ if ($1.value)
+ $$.has_undefined = $1.has_undefined;
+ else
+ $$.has_undefined = $1.has_undefined || $3.has_undefined;
}
| expression AND expression {
- $$ = $1 && $3;
+ $$.value = $1.value && $3.value;
+
+ /* Short-circuit: Only flag undefined from right-side
+* if left side evaluates to true.
+*/
+ if ($1.value)
+
[Mesa-dev] [PATCH 2/2] glsl/glcpp: Once again report undefined macro name in error message.
While writing the previous commit message, I just felt bad documenting the
shortcoming of the change, (that undefined macro names would not be reported
in error messages).
Fix this by preserving the first-encounterd undefined macro name and reporting
that in any resulting error message.
---
src/glsl/glcpp/glcpp-parse.y | 118 +++--
src/glsl/glcpp/glcpp.h | 2 +-
.../125-es-short-circuit-undefined.c.expected | 4 +-
3 files changed, 86 insertions(+), 38 deletions(-)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 4309d26..8447584 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -217,13 +217,13 @@ line:
expanded_line:
IF_EXPANDED expression NEWLINE {
- if (parser->is_gles && $2.has_undefined)
- glcpp_error(& @1, parser, "undefined macro in
expression (illegal in GLES)");
+ if (parser->is_gles && $2.undefined_macro)
+ glcpp_error(& @1, parser, "undefined macro %s in
expression (illegal in GLES)", $2.undefined_macro);
_glcpp_parser_skip_stack_push_if (parser, & @1, $2.value);
}
| ELIF_EXPANDED expression NEWLINE {
- if (parser->is_gles && $2.has_undefined)
- glcpp_error(& @1, parser, "undefined macro in
expression (illegal in GLES)");
+ if (parser->is_gles && $2.undefined_macro)
+ glcpp_error(& @1, parser, "undefined macro %s in
expression (illegal in GLES)", $2.undefined_macro);
_glcpp_parser_skip_stack_change_if (parser, & @1, "elif",
$2.value);
}
| LINE_EXPANDED integer_constant NEWLINE {
@@ -419,14 +419,14 @@ integer_constant:
expression:
integer_constant {
$$.value = $1;
- $$.has_undefined = false;
+ $$.undefined_macro = NULL;
}
| IDENTIFIER {
$$.value = 0;
if (parser->is_gles)
- $$.has_undefined = true;
+ $$.undefined_macro = ralloc_strdup (parser, $1);
else
- $$.has_undefined = false;
+ $$.undefined_macro = NULL;
}
| expression OR expression {
$$.value = $1.value || $3.value;
@@ -434,10 +434,10 @@ expression:
/* Short-circuit: Only flag undefined from right side
* if left side evaluates to false.
*/
- if ($1.value)
- $$.has_undefined = $1.has_undefined;
- else
- $$.has_undefined = $1.has_undefined || $3.has_undefined;
+ if ($1.undefined_macro)
+ $$.undefined_macro = $1.undefined_macro;
+else if (! $1.value)
+ $$.undefined_macro = $3.undefined_macro;
}
| expression AND expression {
$$.value = $1.value && $3.value;
@@ -445,62 +445,101 @@ expression:
/* Short-circuit: Only flag undefined from right-side
* if left side evaluates to true.
*/
- if ($1.value)
- $$.has_undefined = $1.has_undefined || $3.has_undefined;
- else
- $$.has_undefined = $1.has_undefined;
+ if ($1.undefined_macro)
+ $$.undefined_macro = $1.undefined_macro;
+else if ($1.value)
+ $$.undefined_macro = $3.undefined_macro;
}
| expression '|' expression {
$$.value = $1.value | $3.value;
- $$.has_undefined = $1.has_undefined || $3.has_undefined;
+ if ($1.undefined_macro)
+ $$.undefined_macro = $1.undefined_macro;
+else
+ $$.undefined_macro = $3.undefined_macro;
}
| expression '^' expression {
$$.value = $1.value ^ $3.value;
- $$.has_undefined = $1.has_undefined || $3.has_undefined;
+ if ($1.undefined_macro)
+ $$.undefined_macro = $1.undefined_macro;
+else
+ $$.undefined_macro = $3.undefined_macro;
}
| expression '&' expression {
$$.value = $1.value & $3.value;
- $$.has_undefined = $1.has_undefined || $3.has_undefined;
+ if ($1.undefined_macro)
+ $$.undefined_macro = $1.undefined_macro;
+else
+ $$.undefined_macro = $3.undefined_macro;
}
| expression NOT_EQUAL expression {
$$.value = $1.value != $3.value;
- $$.has_undefined = $1.has_undefined || $3.has_undefined;
+ if ($1.undefined_macro)
+ $$.undefined_macro = $1.undefined_
[Mesa-dev] A couple more to make the preprocessor conform better
This continues my ongoing series to make the preprocessor conform more precisely to the specifications. I am sprinkling these patches out as I write and test them because they are each logically independent. If people would prefer that I batch them up and submit them as a single series, I can do that instead. I am adding "make check" tests for each of the issues I fix with each patch. I haven't been running piglit, but I will do a piglit run over the whole series before I push anything to ensure I haven't caused any regressions. With the two patches emailed here, there's only one logical change. I did write it in two pieces though, so I'm submitting it that way. If anyone would prefer these to be squashed, I could easily do that. -Carl ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/gen8: Align hiz depth clear to 8x4
On Friday, June 13, 2014 03:11:00 PM Kenneth Graunke wrote:
> On Friday, June 13, 2014 12:38:43 PM Topi Pohjolainen wrote:
> > This fixes framebuffer_blit_functionality_scissor_blit.test in
> > gles3 cts.
> >
> > Signed-off-by: Topi Pohjolainen
> > ---
> > src/mesa/drivers/dri/i965/gen8_depth_state.c | 15 +++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > index 8c70c62..7f1c23d 100644
> > --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > @@ -30,6 +30,17 @@
> > #include "brw_defines.h"
> >
> > /**
> > + * The documentation for Broadwell's Hierarchical Depth Buffer Resolve
and
> for
> > + * Depth Buffer Clear mandates the rectangle to be 8x4 aligned.
> > + */
> > +static void
> > +align_rectangle_primitive(uint32_t *width, uint32_t *height)
> > +{
> > + *width = ALIGN(*width, 8);
> > + *height = ALIGN(*height, 4);
> > +}
> > +
> > +/**
> > * Helper function to emit depth related command packets.
> > */
> > static void
> > @@ -54,6 +65,8 @@ emit_depth_packets(struct brw_context *brw,
> >return;
> > }
> >
> > + align_rectangle_primitive(&width, &height);
> > +
> > intel_emit_depth_stall_flushes(brw);
> >
> > /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
> > @@ -248,6 +261,8 @@ gen8_hiz_exec(struct brw_context *brw, struct
> intel_mipmap_tree *mt,
> > unsigned rect_width = minify(mt->logical_width0, level);
> > unsigned rect_height = minify(mt->logical_height0, level);
> >
> > + align_rectangle_primitive(&rect_width, &rect_height);
> > +
> > BEGIN_BATCH(4);
> > OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
> > OUT_BATCH(0);
> >
>
> NAK - unfortunately, this regresses piles and piles of depthstencil-render-
> miplevels Piglit tests. I'll look into why - I'm still convinced we need to
> do this, we're just probably not doing it quite right.
>
> --Ken
Oh, amusingly, the align_rectangle_primitive call in emit_depth_packets broke
the non-HiZ case. Not all miplevels are 8x4 aligned. For example, the
miplevels of a 146x146 texture are layed out like this:
intel_miptree_set_level_info level 0, depth 1, offset 0,0
intel_miptree_set_level_info level 1, depth 1, offset 0,148
intel_miptree_set_level_info level 2, depth 1, offset 76,148
intel_miptree_set_level_info level 3, depth 1, offset 76,184
intel_miptree_set_level_info level 4, depth 1, offset 76,204
intel_miptree_set_level_info level 5, depth 1, offset 76,216
intel_miptree_set_level_info level 6, depth 1, offset 76,220
intel_miptree_set_level_info level 7, depth 1, offset 76,224
HiZ will only be enabled for slice 0.
Miplevel 1 is below the base level, with width 146/2 = 73. With your patch,
we configured it for rendering as ALIGN(73, 8) = 80 wide. So, rendering to
miplevel 1 would clobber leftmost 4 pixels of data in miplevels >= 2.
I'll send out a fixed patch shortly - running tests now.
--Ken
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[Mesa-dev] [PATCH 2/2] glsl: Don't choke on an empty pragma
The lexer was insisting that there be at least one character after "#pragma"
and before the end of the line. This caused an error for a line consisting
only of "#pragma" which volates at least the following sentence from the GLSL
ES Specification 3.00.4:
The scope as well as the effect of the optimize and debug pragmas is
implementation-dependent except that their use must not generate an
error. [Page 12 (Page 28 of PDF)]
and likely the following sentence from that specification and also in
GLSLangSpec 4.30.6:
If an implementation does not recognize the tokens following #pragma,
then it will ignore that pragma.
Add a "make check" test to ensure no future regressions.
This change fixes at least part of the following Khronos GLES3 CTS test:
preprocessor.pragmas.pragma_vertex
---
src/glsl/glcpp/glcpp-lex.l | 2 +-
src/glsl/glcpp/tests/127-pragma-empty.c | 3 +++
src/glsl/glcpp/tests/127-pragma-empty.c.expected | 4
3 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 src/glsl/glcpp/tests/127-pragma-empty.c
create mode 100644 src/glsl/glcpp/tests/127-pragma-empty.c.expected
diff --git a/src/glsl/glcpp/glcpp-lex.l b/src/glsl/glcpp/glcpp-lex.l
index 2b818dc..88e2818 100644
--- a/src/glsl/glcpp/glcpp-lex.l
+++ b/src/glsl/glcpp/glcpp-lex.l
@@ -180,7 +180,7 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]?
/* glcpp doesn't handle #extension, #version, or #pragma directives.
* Simply pass them through to the main compiler's lexer/parser. */
-{HASH}(extension|pragma)[^\n]+ {
+{HASH}(extension|pragma)[^\n]* {
if (parser->commented_newlines)
BEGIN NEWLINE_CATCHUP;
yylval->str = ralloc_strdup (yyextra, yytext);
diff --git a/src/glsl/glcpp/tests/127-pragma-empty.c
b/src/glsl/glcpp/tests/127-pragma-empty.c
new file mode 100644
index 000..0f9b0b3
--- /dev/null
+++ b/src/glsl/glcpp/tests/127-pragma-empty.c
@@ -0,0 +1,3 @@
+/* It seems an odd (and particularly useless) thing to have an empty pragma,
+ * but we probably shouldn't trigger an error in this case. */
+#pragma
diff --git a/src/glsl/glcpp/tests/127-pragma-empty.c.expected
b/src/glsl/glcpp/tests/127-pragma-empty.c.expected
new file mode 100644
index 000..957daff
--- /dev/null
+++ b/src/glsl/glcpp/tests/127-pragma-empty.c.expected
@@ -0,0 +1,4 @@
+
+
+#pragma
+
--
2.0.0
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[Mesa-dev] Two last tiny fixes for preprocessor conformance
So these last two, (very self-explanatory), patches complete my series based on an initial pass over preprocessor-related failures I saw in the Khronos GLES3 CTS. There is at least one more failure caused by a test case that has a non-ASCII character (decimal 129) in the name given to a #extension directive. I've verified that glcpp itself passes that non-ASCII character through just fine, so I'm assuming that the subsequent compiler chokes on it, but I haven't chased that down just yet. -Carl ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] glsl/glcpp: Promote "extra token at end of directive" from warning to error
We've always warned about this case, but a recent confromance test expects
this to be an error that causes compilation to fail. Make it so.
Also add a "make check" test to ensure these errors are generated.
This fixes at least the following Khronos GLES3 conformance tests:
invalid_conditionals.tokens_after_ifdef_vertex
invalid_conditionals.tokens_after_ifdef_fragment
invalid_conditionals.tokens_after_ifndef_vertex
invalid_conditionals.tokens_after_ifndef_fragment
---
src/glsl/glcpp/glcpp-parse.y| 2 +-
src/glsl/glcpp/tests/126-garbage-after-directive.c | 5 +
src/glsl/glcpp/tests/126-garbage-after-directive.c.expected | 8
3 files changed, 14 insertions(+), 1 deletion(-)
create mode 100644 src/glsl/glcpp/tests/126-garbage-after-directive.c
create mode 100644 src/glsl/glcpp/tests/126-garbage-after-directive.c.expected
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 8447584..e5a816b 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -625,7 +625,7 @@ replacement_list:
junk:
/* empty */
| pp_tokens {
- glcpp_warning(&@1, parser, "extra tokens at end of directive");
+ glcpp_error(&@1, parser, "extra tokens at end of directive");
}
;
diff --git a/src/glsl/glcpp/tests/126-garbage-after-directive.c
b/src/glsl/glcpp/tests/126-garbage-after-directive.c
new file mode 100644
index 000..4c0d290
--- /dev/null
+++ b/src/glsl/glcpp/tests/126-garbage-after-directive.c
@@ -0,0 +1,5 @@
+#ifdef MACRO garbage
+#endif
+
+#ifndef MORE garbage
+#endif
diff --git a/src/glsl/glcpp/tests/126-garbage-after-directive.c.expected
b/src/glsl/glcpp/tests/126-garbage-after-directive.c.expected
new file mode 100644
index 000..95a9e61
--- /dev/null
+++ b/src/glsl/glcpp/tests/126-garbage-after-directive.c.expected
@@ -0,0 +1,8 @@
+0:1(15): preprocessor error: extra tokens at end of directive
+0:4(14): preprocessor error: extra tokens at end of directive
+
+
+
+
+
+
--
2.0.0
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Re: [Mesa-dev] A couple more to make the preprocessor conform better
On Friday, June 13, 2014 03:27:13 PM Carl Worth wrote: > This continues my ongoing series to make the preprocessor conform more > precisely to the specifications. > > I am sprinkling these patches out as I write and test them because they are > each logically independent. If people would prefer that I batch them up and > submit them as a single series, I can do that instead. > > I am adding "make check" tests for each of the issues I fix with each patch. I > haven't been running piglit, but I will do a piglit run over the whole series > before I push anything to ensure I haven't caused any regressions. > > With the two patches emailed here, there's only one logical change. I did > write it in two pieces though, so I'm submitting it that way. If anyone would > prefer these to be squashed, I could easily do that. > > -Carl Both of these two are: Reviewed-by: Kenneth Graunke This isn't as bad as I thought. Also, I love the test cases :) signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] glsl/glcpp: Promote "extra token at end of directive" from warning to error
On Friday, June 13, 2014 04:04:43 PM Carl Worth wrote: > We've always warned about this case, but a recent confromance test expects > this to be an error that causes compilation to fail. Make it so. > > Also add a "make check" test to ensure these errors are generated. > > This fixes at least the following Khronos GLES3 conformance tests: > > invalid_conditionals.tokens_after_ifdef_vertex > invalid_conditionals.tokens_after_ifdef_fragment > invalid_conditionals.tokens_after_ifndef_vertex > invalid_conditionals.tokens_after_ifndef_fragment > --- > src/glsl/glcpp/glcpp-parse.y| 2 +- > src/glsl/glcpp/tests/126-garbage-after-directive.c | 5 + > src/glsl/glcpp/tests/126-garbage-after-directive.c.expected | 8 > 3 files changed, 14 insertions(+), 1 deletion(-) > create mode 100644 src/glsl/glcpp/tests/126-garbage-after-directive.c > create mode 100644 src/glsl/glcpp/tests/126-garbage-after- directive.c.expected Right, I'd added a warning about this in commit 65875743542fd1388b18a1, apparently to make CorrectPreprocess11.frag from the original 3Dlabs tests pass (as it was accepted by both gcc and nvidia's compiler). We've since determined that CorrectPreprocess11.frag wasn't so correct after all, and deleted it from Piglit (commit a9df70269aa25da). So, I'm fine with promoting this. Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] glsl: Don't choke on an empty pragma
On Friday, June 13, 2014 04:04:44 PM Carl Worth wrote: > The lexer was insisting that there be at least one character after "#pragma" > and before the end of the line. This caused an error for a line consisting > only of "#pragma" which volates at least the following sentence from the GLSL > ES Specification 3.00.4: > > The scope as well as the effect of the optimize and debug pragmas is > implementation-dependent except that their use must not generate an > error. [Page 12 (Page 28 of PDF)] > > and likely the following sentence from that specification and also in > GLSLangSpec 4.30.6: > > If an implementation does not recognize the tokens following #pragma, > then it will ignore that pragma. > > Add a "make check" test to ensure no future regressions. > > This change fixes at least part of the following Khronos GLES3 CTS test: > > preprocessor.pragmas.pragma_vertex Because empty #pragmas are so useful! Ah well. Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.
Like on Haswell, we need to use 8x4 aligned rectangle primitives for
hierarchical depth buffer resolves and depth clears. See the comments
in brw_blorp.cpp's brw_hiz_op_params() constructor. (The Broadwell
documentation confirms that this is still necessary.)
This patch makes the Broadwell code follow the same behavior as Chad and
Jordan's Gen7 BLORP code. Based on a patch by Topi Pohjolainen.
This fixes es3conform's framebuffer_blit_functionality_scissor_blit
test, with no Piglit regressions.
Signed-off-by: Kenneth Graunke
Cc: "10.2"
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 8c70c62..f538d23 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -225,6 +225,13 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
assert(mt->first_level == 0);
assert(mt->logical_depth0 >= 1);
+ /* If we're operating on LOD 0, align to 8x4 to meet the alignment
+* requirements for most HiZ operations. Otherwise, use the actual size
+* to allow the hardware to calculate the miplevel offsets correctly.
+*/
+ uint32_t surface_width = ALIGN(mt->logical_width0, level == 0 ? 8 : 1);
+ uint32_t surface_height = ALIGN(mt->logical_height0, level == 0 ? 4 : 1);
+
/* The basic algorithm is:
* - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
* 3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
@@ -239,14 +246,19 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
true, /* depth writes */
NULL, false, 0, /* no stencil for now */
true, /* hiz */
- mt->logical_width0,
- mt->logical_height0,
+ surface_width,
+ surface_height,
mt->logical_depth0,
level,
layer); /* min_array_element */
- unsigned rect_width = minify(mt->logical_width0, level);
- unsigned rect_height = minify(mt->logical_height0, level);
+ /* Depth buffer clears and HiZ resolves must use an 8x4 aligned rectangle.
+* Note that intel_miptree_level_enable_hiz disables HiZ for miplevels > 0
+* which aren't 8x4 aligned, so expanding the size is safe - it'll just
+* draw into empty padding space.
+*/
+ unsigned rect_width = ALIGN(minify(mt->logical_width0, level), 8);
+ unsigned rect_height = ALIGN(minify(mt->logical_height0, level), 4);
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
--
1.9.1
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[Mesa-dev] [PATCH 1/2] i965: Make INTEL_DEBUG=mip print out whether HiZ is enabled.
We only enable HiZ for miplevels which are aligned on 8x4 blocks. When
debugging HiZ failures, it's useful to know whether a particular
miplevel is using HiZ or not.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a0e637a..4c71e41 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1370,10 +1370,12 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
* force the proper size alignments.
*/
if (level > 0 && ((width & 7) || (height & 3))) {
+ DBG("mt %p level %d: HiZ DISABLED\n", mt, level);
return false;
}
}
+ DBG("mt %p level %d: HiZ enabled\n", mt, level);
mt->level[level].has_hiz = true;
return true;
}
--
1.9.1
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[Mesa-dev] [PATCH 2/5] mesa/main: Add generic bits of ARB_clear_texture implementation
This adds the driver entry point for glClearTexSubImage and fills in the
_mesa_ClearTexImage and _mesa_ClearTexSubImage functions that call it.
---
src/mesa/main/dd.h | 14 +++
src/mesa/main/teximage.c | 241 ++-
src/mesa/main/teximage.h | 12 +++
3 files changed, 266 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 633ea2c..8976535 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -239,6 +239,20 @@ struct dd_function_table {
struct gl_texture_image *texImage );
/**
+* Called by glClearTex[Sub]Image
+*
+* Clears a rectangular region of the image to a given value. The
+* clearValue argument is either NULL or points to a single texel to use as
+* the clear value in the same internal format as the texture image. If it
+* is NULL then the texture should be cleared to zeroes.
+*/
+ void (*ClearTexSubImage)(struct gl_context *ctx,
+struct gl_texture_image *texImage,
+GLint xoffset, GLint yoffset, GLint zoffset,
+GLsizei width, GLsizei height, GLsizei depth,
+const GLvoid *clearValue);
+
+ /**
* Called by glCopyTex[Sub]Image[123]D().
*
* This function should copy a rectangular region in the rb to a single
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index a893c70..d5baac8 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -51,6 +51,7 @@
#include "textureview.h"
#include "mtypes.h"
#include "glformats.h"
+#include "texstore.h"
/**
@@ -3848,20 +3849,259 @@ _mesa_CopyTexSubImage3D( GLenum target, GLint level,
x, y, width, height);
}
+static bool
+clear_tex_image(struct gl_context *ctx,
+const char *function,
+struct gl_texture_image *texImage, GLint level,
+GLint xoffset, GLint yoffset, GLint zoffset,
+GLsizei width, GLsizei height, GLsizei depth,
+GLenum format, GLenum type,
+const void *data)
+{
+ struct gl_texture_object *texObj = texImage->TexObject;
+ static const GLubyte zeroData[MAX_PIXEL_BYTES];
+ GLubyte clearValue[MAX_PIXEL_BYTES];
+ GLubyte *clearValuePtr = clearValue;
+ GLenum internalFormat = texImage->InternalFormat;
+ GLenum err;
+
+ if (texObj->Target == GL_TEXTURE_BUFFER) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(buffer texture)", function);
+ return false;
+ }
+
+ if (_mesa_is_compressed_format(ctx, internalFormat)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(compressed texture)", function);
+ return false;
+ }
+
+ err = _mesa_error_check_format_and_type(ctx, format, type);
+ if (err != GL_NO_ERROR) {
+ _mesa_error(ctx, err,
+ "%s(incompatible format = %s, type = %s)",
+ function,
+ _mesa_lookup_enum_by_nr(format),
+ _mesa_lookup_enum_by_nr(type));
+ return false;
+ }
+
+ /* make sure internal format and format basically agree */
+ if (!texture_formats_agree(internalFormat, format)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(incompatible internalFormat = %s, format = %s)",
+ function,
+ _mesa_lookup_enum_by_nr(internalFormat),
+ _mesa_lookup_enum_by_nr(format));
+ return false;
+ }
+
+ if (ctx->Version >= 30 || ctx->Extensions.EXT_texture_integer) {
+ /* both source and dest must be integer-valued, or neither */
+ if (_mesa_is_format_integer_color(texImage->TexFormat) !=
+ _mesa_is_enum_format_integer(format)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(integer/non-integer format mismatch)",
+ function);
+ return false;
+ }
+ }
+
+ if (!_mesa_texstore(ctx,
+ 1, /* dims */
+ texImage->_BaseFormat,
+ texImage->TexFormat,
+ 0, /* dstRowStride */
+ &clearValuePtr,
+ 1, 1, 1, /* srcWidth/Height/Depth */
+ format, type,
+ data ? data : zeroData,
+ &ctx->DefaultPacking)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, "%s(invalid format)", function);
+ return false;
+ }
+
+ ctx->Driver.ClearTexSubImage(ctx,
+texImage,
+xoffset, yoffset, zoffset,
+width, height, depth,
+data ? clearValue : NULL);
+
+ return true;
+}
+
+static struct gl_texture_object *
+get_tex_obj_for_clear(struct gl_context *ctx,
+ const char *function,
+ GLuint texture
[Mesa-dev] [PATCH 1/5] teximage: Add utility func for format/internalFormat compatibility check
In texture_error_check() there was a snippet of code to check whether the
given format and internal format are basically compatible. This has been split
out into its own static helper function so that it can be used by an
implementation of glClearTexImage too.
---
src/mesa/main/teximage.c | 63 +++-
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 47e64d7..a893c70 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -2020,6 +2020,46 @@ _mesa_legal_texture_base_format_for_target(struct
gl_context *ctx,
return true;
}
+static bool
+texture_formats_agree(GLenum internalFormat,
+ GLenum format)
+{
+ GLboolean colorFormat;
+ GLboolean is_format_depth_or_depthstencil;
+ GLboolean is_internalFormat_depth_or_depthstencil;
+
+ /* Even though there are no color-index textures, we still have to support
+* uploading color-index data and remapping it to RGB via the
+* GL_PIXEL_MAP_I_TO_[RGBA] tables.
+*/
+ const GLboolean indexFormat = (format == GL_COLOR_INDEX);
+
+ is_internalFormat_depth_or_depthstencil =
+ _mesa_is_depth_format(internalFormat) ||
+ _mesa_is_depthstencil_format(internalFormat);
+
+ is_format_depth_or_depthstencil =
+ _mesa_is_depth_format(format) ||
+ _mesa_is_depthstencil_format(format);
+
+ colorFormat = _mesa_is_color_format(format);
+
+ if (_mesa_is_color_format(internalFormat) && !colorFormat && !indexFormat)
+ return false;
+
+ if (is_internalFormat_depth_or_depthstencil !=
+ is_format_depth_or_depthstencil)
+ return false;
+
+ if (_mesa_is_ycbcr_format(internalFormat) != _mesa_is_ycbcr_format(format))
+ return false;
+
+ if (_mesa_is_dudv_format(internalFormat) != _mesa_is_dudv_format(format))
+ return false;
+
+ return true;
+}
+
/**
* Test the glTexImage[123]D() parameters for errors.
*
@@ -2053,17 +2093,8 @@ texture_error_check( struct gl_context *ctx,
GLint width, GLint height,
GLint depth, GLint border )
{
- GLboolean colorFormat;
- GLboolean is_format_depth_or_depthstencil;
- GLboolean is_internalFormat_depth_or_depthstencil;
GLenum err;
- /* Even though there are no color-index textures, we still have to support
-* uploading color-index data and remapping it to RGB via the
-* GL_PIXEL_MAP_I_TO_[RGBA] tables.
-*/
- const GLboolean indexFormat = (format == GL_COLOR_INDEX);
-
/* Note: for proxy textures, some error conditions immediately generate
* a GL error in the usual way. But others do not generate a GL error.
* Instead, they cause the width, height, depth, format fields of the
@@ -2146,19 +2177,7 @@ texture_error_check( struct gl_context *ctx,
}
/* make sure internal format and format basically agree */
- is_internalFormat_depth_or_depthstencil =
- _mesa_is_depth_format(internalFormat) ||
- _mesa_is_depthstencil_format(internalFormat);
-
- is_format_depth_or_depthstencil =
- _mesa_is_depth_format(format) ||
- _mesa_is_depthstencil_format(format);
-
- colorFormat = _mesa_is_color_format(format);
- if ((_mesa_is_color_format(internalFormat) && !colorFormat && !indexFormat)
||
- (is_internalFormat_depth_or_depthstencil !=
is_format_depth_or_depthstencil) ||
- (_mesa_is_ycbcr_format(internalFormat) !=
_mesa_is_ycbcr_format(format)) ||
- (_mesa_is_dudv_format(internalFormat) != _mesa_is_dudv_format(format)))
{
+ if (!texture_formats_agree(internalFormat, format)) {
_mesa_error(ctx, GL_INVALID_OPERATION,
"glTexImage%dD(incompatible internalFormat = %s, format =
%s)",
dimensions, _mesa_lookup_enum_by_nr(internalFormat),
--
1.9.3
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[Mesa-dev] [PATCH v2 0/6] Implement ARB_clear_texture
Here is a second attempt at implementing the GL_ARB_clear_texture extension. I've split up the patch into serveral smaller patches. They are based on top of the first patch in Ilia's series which is available here: https://github.com/imirkin/mesa/commit/9c2467020a8a3895a1debbad06561f37 I think I've addressed all of the issues mentioned in the reviews. Instead of enabling the extension unconditionally I've added a helper function which is called by all DRI-based drivers. The intention is for this to be a place to enable all extensions which are implemented for free by calling _mesa_init_driver_functions. On the piglit mailing list I've posted some more tests including one which checks some error conditions and another which tests integer textures. The patch series is available on a branch in Github here: https://github.com/bpeel/mesa/tree/wip/clear-texture The piglit patches are available here: https://github.com/bpeel/piglit/tree/wip/clear-texture - Neil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/5] Add a place to enable extensions that are common to all DRI drivers
This adds a function called _mesa_init_driver_extensions that is called by all
DRI-based drivers. The intention is that any extensions that are implemented
directly by _mesa_init_driver_functions without any driver-specific
entrypoints will be enabled here.
---
src/mesa/drivers/common/driverfuncs.c | 8
src/mesa/drivers/common/driverfuncs.h | 2 ++
src/mesa/drivers/dri/i915/intel_extensions.c | 3 +++
src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++
src/mesa/drivers/dri/nouveau/nouveau_context.c | 1 +
src/mesa/drivers/dri/r200/r200_context.c | 2 ++
src/mesa/drivers/dri/radeon/radeon_context.c | 2 ++
src/mesa/drivers/dri/swrast/swrast.c | 1 +
8 files changed, 22 insertions(+)
diff --git a/src/mesa/drivers/common/driverfuncs.c
b/src/mesa/drivers/common/driverfuncs.c
index 6ece5d8..ee8b390 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -326,3 +326,11 @@ _mesa_init_driver_state(struct gl_context *ctx)
ctx->Driver.DrawBuffer(ctx, ctx->Color.DrawBuffer[0]);
}
+
+/**
+ * Enable extensions that are available for all DRI-based drivers.
+ */
+void
+_mesa_init_driver_extensions(struct gl_context *ctx)
+{
+}
diff --git a/src/mesa/drivers/common/driverfuncs.h
b/src/mesa/drivers/common/driverfuncs.h
index 6b9a900..520c059 100644
--- a/src/mesa/drivers/common/driverfuncs.h
+++ b/src/mesa/drivers/common/driverfuncs.h
@@ -33,5 +33,7 @@ _mesa_init_driver_functions(struct dd_function_table *driver);
extern void
_mesa_init_driver_state(struct gl_context *ctx);
+extern void
+_mesa_init_driver_extensions(struct gl_context *ctx);
#endif
diff --git a/src/mesa/drivers/dri/i915/intel_extensions.c
b/src/mesa/drivers/dri/i915/intel_extensions.c
index 76f608e..3a8744a 100644
--- a/src/mesa/drivers/dri/i915/intel_extensions.c
+++ b/src/mesa/drivers/dri/i915/intel_extensions.c
@@ -31,6 +31,7 @@
#include "intel_context.h"
#include "intel_extensions.h"
#include "intel_reg.h"
+#include "drivers/common/driverfuncs.h"
#include "utils.h"
/**
@@ -44,6 +45,8 @@ intelInitExtensions(struct gl_context *ctx)
assert(intel->gen == 2 || intel->gen == 3);
+ _mesa_init_driver_extensions(ctx);
+
ctx->Extensions.ARB_draw_elements_base_vertex = true;
ctx->Extensions.ARB_explicit_attrib_location = true;
ctx->Extensions.ARB_framebuffer_object = true;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 39d0ab5..fe47464 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -31,6 +31,7 @@
#include "intel_batchbuffer.h"
#include "intel_reg.h"
#include "utils.h"
+#include "drivers/common/driverfuncs.h"
/**
* Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
@@ -162,6 +163,8 @@ intelInitExtensions(struct gl_context *ctx)
assert(brw->gen >= 4);
+ _mesa_init_driver_extensions(ctx);
+
ctx->Extensions.ARB_buffer_storage = true;
ctx->Extensions.ARB_depth_buffer_float = true;
ctx->Extensions.ARB_depth_clamp = true;
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c
b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index f8c8dc3..ad7ee86 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -183,6 +183,7 @@ nouveau_context_init(struct gl_context *ctx, gl_api api,
}
/* Enable any supported extensions. */
+_mesa_init_driver_extensions(ctx);
ctx->Extensions.EXT_blend_color = true;
ctx->Extensions.EXT_blend_minmax = true;
ctx->Extensions.EXT_texture_filter_anisotropic = true;
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 71dfcf3..93ca23d 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -366,6 +366,8 @@ GLboolean r200CreateContext( gl_api api,
_math_matrix_ctr( &rmesa->tmpmat );
_math_matrix_set_identity( &rmesa->tmpmat );
+ _mesa_init_driver_extensions(ctx);
+
ctx->Extensions.ARB_occlusion_query = true;
ctx->Extensions.ARB_point_sprite = true;
ctx->Extensions.ARB_texture_border_clamp = true;
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
b/src/mesa/drivers/dri/radeon/radeon_context.c
index 1ceb4ab..fd8e95b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -328,6 +328,8 @@ r100CreateContext( gl_api api,
_math_matrix_set_identity( &rmesa->tmpmat[i] );
}
+ _mesa_init_driver_extensions(ctx);
+
ctx->Extensions.ARB_occlusion_query = true;
ctx->Extensions.ARB_texture_border_clamp = true;
ctx->Extensions.ARB_texture_cube_map = true;
diff --git a/src/mesa/drivers/dri/swrast/swrast.c
b/src/mesa/drivers/dri/swrast/swrast.c
index 8881381..71e2184 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/dri
[Mesa-dev] [PATCH 4/5] texstore: Add a generic implementation of GL_ARB_clear_texture
Adds an implmentation of the ClearTexSubImage driver entry point that just
maps the texture and writes the values in. This should work as a reliable
fallback on any driver.
---
src/mesa/drivers/common/driverfuncs.c | 2 +
src/mesa/main/texstore.c | 70 +++
src/mesa/main/texstore.h | 7
3 files changed, 79 insertions(+)
diff --git a/src/mesa/drivers/common/driverfuncs.c
b/src/mesa/drivers/common/driverfuncs.c
index ee8b390..34b6fef 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -95,6 +95,7 @@ _mesa_init_driver_functions(struct dd_function_table *driver)
driver->TexImage = _mesa_store_teximage;
driver->TexSubImage = _mesa_store_texsubimage;
driver->GetTexImage = _mesa_meta_GetTexImage;
+ driver->ClearTexSubImage = _mesa_store_cleartexsubimage;
driver->CopyTexSubImage = _mesa_meta_CopyTexSubImage;
driver->GenerateMipmap = _mesa_meta_GenerateMipmap;
driver->TestProxyTexImage = _mesa_test_proxy_teximage;
@@ -333,4 +334,5 @@ _mesa_init_driver_state(struct gl_context *ctx)
void
_mesa_init_driver_extensions(struct gl_context *ctx)
{
+ ctx->Extensions.ARB_clear_texture = GL_TRUE;
}
diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
index cb81f3f..9c90492 100644
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -4157,6 +4157,76 @@ _mesa_store_texsubimage(struct gl_context *ctx, GLuint
dims,
format, type, pixels, packing, "glTexSubImage");
}
+static void
+clear_image_to_zero(GLubyte *dstMap, GLint dstRowStride,
+GLsizei width, GLsizei height,
+GLsizei clearValueSize)
+{
+ while (height-- > 0) {
+ memset(dstMap, 0, clearValueSize * width);
+ dstMap += dstRowStride;
+ }
+}
+
+static void
+clear_image_to_value(GLubyte *dstMap, GLint dstRowStride,
+ GLsizei width, GLsizei height,
+ const GLvoid *clearValue,
+ GLsizei clearValueSize)
+{
+ GLsizei x;
+
+ while (height-- > 0) {
+ for (x = 0; x < width; x++) {
+ memcpy(dstMap, clearValue, clearValueSize);
+ dstMap += clearValueSize;
+ }
+ dstMap += dstRowStride - clearValueSize * width;
+ }
+}
+
+/*
+ * Fallback for Driver.ClearTexSubImage().
+ */
+void
+_mesa_store_cleartexsubimage(struct gl_context *ctx,
+ struct gl_texture_image *texImage,
+ GLint xoffset, GLint yoffset, GLint zoffset,
+ GLsizei width, GLsizei height, GLsizei depth,
+ const GLvoid *clearValue)
+{
+ GLubyte *dstMap;
+ GLint dstRowStride;
+ GLsizeiptr clearValueSize;
+ GLsizei z;
+
+ clearValueSize = _mesa_get_format_bytes(texImage->TexFormat);
+
+ for (z = 0; z < depth; z++) {
+ ctx->Driver.MapTextureImage(ctx, texImage,
+ z + zoffset, xoffset, yoffset,
+ width, height,
+ GL_MAP_WRITE_BIT,
+ &dstMap, &dstRowStride);
+ if (dstMap == NULL) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, "glClearTex*Image");
+ return;
+ }
+
+ if (clearValue) {
+ clear_image_to_value(dstMap, dstRowStride,
+ width, height,
+ clearValue,
+ clearValueSize);
+ } else {
+ clear_image_to_zero(dstMap, dstRowStride,
+ width, height,
+ clearValueSize);
+ }
+
+ ctx->Driver.UnmapTextureImage(ctx, texImage, z + zoffset);
+ }
+}
/**
* Fallback for Driver.CompressedTexImage()
diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h
index c4cfffd..dd1e1d0 100644
--- a/src/mesa/main/texstore.h
+++ b/src/mesa/main/texstore.h
@@ -118,6 +118,13 @@ _mesa_store_texsubimage(struct gl_context *ctx, GLuint
dims,
extern void
+_mesa_store_cleartexsubimage(struct gl_context *ctx,
+ struct gl_texture_image *texImage,
+ GLint xoffset, GLint yoffset, GLint zoffset,
+ GLsizei width, GLsizei height, GLsizei depth,
+ const GLvoid *clearValue);
+
+extern void
_mesa_store_compressed_teximage(struct gl_context *ctx, GLuint dims,
struct gl_texture_image *texImage,
GLsizei imageSize, const GLvoid *data);
--
1.9.3
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/5] meta: Add a meta implementation of GL_ARB_clear_texture
Adds an implementation of the ClearTexSubImage driver entry point that tries
to set up an FBO to render to the texture and then calls glClear with a
scissor to perform the actual clear. If an FBO can't be created for the
texture then it will fall back to using _mesa_store_ClearTexSubImage.
---
src/mesa/drivers/common/driverfuncs.c | 2 +-
src/mesa/drivers/common/meta.c| 162 ++
src/mesa/drivers/common/meta.h| 7 ++
3 files changed, 170 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/common/driverfuncs.c
b/src/mesa/drivers/common/driverfuncs.c
index 34b6fef..1ac2aee 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -95,7 +95,7 @@ _mesa_init_driver_functions(struct dd_function_table *driver)
driver->TexImage = _mesa_store_teximage;
driver->TexSubImage = _mesa_store_texsubimage;
driver->GetTexImage = _mesa_meta_GetTexImage;
- driver->ClearTexSubImage = _mesa_store_cleartexsubimage;
+ driver->ClearTexSubImage = _mesa_meta_ClearTexSubImage;
driver->CopyTexSubImage = _mesa_meta_CopyTexSubImage;
driver->GenerateMipmap = _mesa_meta_GenerateMipmap;
driver->TestProxyTexImage = _mesa_test_proxy_teximage;
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index cab0dd8..7308ce6 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -40,6 +40,7 @@
#include "main/blit.h"
#include "main/bufferobj.h"
#include "main/buffers.h"
+#include "main/clear.h"
#include "main/colortab.h"
#include "main/condrender.h"
#include "main/depth.h"
@@ -47,6 +48,7 @@
#include "main/fbobject.h"
#include "main/feedback.h"
#include "main/formats.h"
+#include "main/format_unpack.h"
#include "main/glformats.h"
#include "main/image.h"
#include "main/macros.h"
@@ -71,6 +73,7 @@
#include "main/teximage.h"
#include "main/texparam.h"
#include "main/texstate.h"
+#include "main/texstore.h"
#include "main/transformfeedback.h"
#include "main/uniforms.h"
#include "main/varray.h"
@@ -3360,3 +3363,162 @@ _mesa_meta_DrawTex(struct gl_context *ctx, GLfloat x,
GLfloat y, GLfloat z,
_mesa_meta_end(ctx);
}
+
+static void
+set_color_clear_value(struct gl_context *ctx,
+ mesa_format format,
+ const GLvoid *clearValue)
+{
+ if (clearValue == 0) {
+ memset(&ctx->Color.ClearColor, 0, sizeof ctx->Color.ClearColor);
+ }
+ else {
+ switch (_mesa_get_format_datatype(format)) {
+ case GL_UNSIGNED_INT:
+ case GL_INT:
+ _mesa_unpack_uint_rgba_row(format, 1, clearValue,
+(GLuint (*)[4]) ctx->Color.ClearColor.ui);
+ break;
+ default:
+ _mesa_unpack_rgba_row(format, 1, clearValue,
+ (GLfloat (*)[4]) ctx->Color.ClearColor.f);
+ break;
+ }
+ }
+}
+
+static bool
+cleartexsubimage_using_fbo_for_zoffset(struct gl_context *ctx,
+ struct gl_texture_image *texImage,
+ GLint xoffset, GLint yoffset,
+ GLint zoffset,
+ GLsizei width, GLsizei height,
+ const GLvoid *clearValue)
+{
+ GLuint fbo;
+ bool success = false;
+ GLbitfield mask;
+ GLenum status;
+ GLuint depthStencilValue[2];
+ GLfloat depthValue;
+
+ _mesa_GenFramebuffers(1, &fbo);
+ _mesa_BindFramebuffer(GL_DRAW_FRAMEBUFFER, fbo);
+
+ if (texImage->_BaseFormat == GL_DEPTH_STENCIL ||
+ texImage->_BaseFormat == GL_DEPTH_COMPONENT) {
+ _mesa_meta_bind_fbo_image(GL_DEPTH_ATTACHMENT, texImage, zoffset);
+ mask = GL_DEPTH_BUFFER_BIT;
+
+ if (clearValue)
+ _mesa_unpack_float_32_uint_24_8_depth_stencil_row(texImage->TexFormat,
+ 1, /* n */
+ clearValue,
+ depthStencilValue);
+ else
+ memset(depthStencilValue, 0, sizeof depthStencilValue);
+
+ memcpy(&depthValue, depthStencilValue, sizeof depthValue);
+ ctx->Depth.Clear = depthValue;
+
+ if (texImage->_BaseFormat == GL_DEPTH_STENCIL) {
+ _mesa_meta_bind_fbo_image(GL_STENCIL_ATTACHMENT, texImage, zoffset);
+ mask |= GL_STENCIL_BUFFER_BIT;
+ ctx->Stencil.Clear = depthStencilValue[1] & 0xff;
+ }
+ _mesa_DrawBuffer(GL_NONE);
+ } else {
+ _mesa_meta_bind_fbo_image(GL_COLOR_ATTACHMENT0, texImage, zoffset);
+ _mesa_DrawBuffer(GL_COLOR_ATTACHMENT0);
+ mask = GL_COLOR_BUFFER_BIT;
+
+ set_color_clear_value(ctx, texImage->TexFormat, clearValue);
+ }
+
+ status = _mesa_CheckFramebufferStatus(GL_DRAW_FRAMEBUFFER);
+ if (status != GL_FRAMEBUFFER_COMPLETE)
+ goto out;
+
+ _mesa_set_enable(ctx, GL_SCISSOR_TEST,
[Mesa-dev] [Bug 80011] New: [softpipe] tgsi/tgsi_exec.c:2023:exec_txf: Assertion `0' failed.
https://bugs.freedesktop.org/show_bug.cgi?id=80011 Priority: medium Bug ID: 80011 Keywords: have-backtrace Assignee: mesa-dev@lists.freedesktop.org Summary: [softpipe] tgsi/tgsi_exec.c:2023:exec_txf: Assertion `0' failed. Severity: normal Classification: Unclassified OS: Linux (All) Reporter: v...@freedesktop.org Hardware: x86-64 (AMD64) Status: NEW Version: git Component: Other Product: Mesa mesa: ffe609cc69f328de5b57d4d7ab1d270fcf28de5f (master) Run glsl-resource-not-bound 2DMS. $ ./bin/glsl-resource-not-bound 2DMS -auto tgsi/tgsi_exec.c:2023:exec_txf: Assertion `0' failed. Trace/breakpoint trap (core dumped) (gdb) bt #0 0x7fdea2120e87 in _debug_assert_fail (expr=0x7fdea2231149 "0", file=0x7fdea2231114 "tgsi/tgsi_exec.c", line=2023, function=0x7fdea2231ae6 <__func__.6804> "exec_txf") at util/u_debug.c:309 #1 0x7fdea2101567 in exec_txf (mach=0x7fdea01ef010, inst=0xaed210) at tgsi/tgsi_exec.c:2023 #2 0x7fdea210919e in exec_instruction (mach=0x7fdea01ef010, inst=0xaed210, pc=0x7fff059470e4) at tgsi/tgsi_exec.c:4240 #3 0x7fdea210a881 in tgsi_exec_machine_run (mach=0x7fdea01ef010) at tgsi/tgsi_exec.c:4670 #4 0x7fdea1d7c170 in exec_run (var=0xaec9c0, machine=0x7fdea01ef010, quad=0x6f3d00) at sp_fs_exec.c:129 #5 0x7fdea1d84f56 in shade_quad (qs=0x648e00, quad=0x6f3d00) at sp_quad_fs.c:83 #6 0x7fdea1d85110 in shade_quads (qs=0x648e00, quads=0x6f6180, nr=1) at sp_quad_fs.c:136 #7 0x7fdea1d8e42a in flush_spans (setup=0x6f3c80) at sp_setup.c:251 #8 0x7fdea1d8f83a in subtriangle (setup=0x6f3c80, eleft=0x6f3ca8, eright=0x6f3cd8, lines=80) at sp_setup.c:755 #9 0x7fdea1d8fbaf in sp_setup_tri (setup=0x6f3c80, v0=0xaeee00, v1=0xaeee10, v2=0xaeee20) at sp_setup.c:855 #10 0x7fdea1d7fd08 in sp_vbuf_draw_arrays (vbr=0x642e20, start=0, nr=4) at sp_prim_vbuf.c:493 #11 0x7fdea20d2531 in draw_pt_emit_linear (emit=0x661a40, vert_info=0x7fff059474d0, prim_info=0x7fff05947600) at draw/draw_pt_emit.c:258 #12 0x7fdea20d516d in emit (emit=0x661a40, vert_info=0x7fff059474d0, prim_info=0x7fff05947600) at draw/draw_pt_fetch_shade_pipeline.c:196 #13 0x7fdea20d5749 in fetch_pipeline_generic (middle=0x661900, fetch_info=0x0, in_prim_info=0x7fff05947600) at draw/draw_pt_fetch_shade_pipeline.c:352 #14 0x7fdea20d58af in fetch_pipeline_linear_run (middle=0x661900, start=0, count=4, prim_flags=0) at draw/draw_pt_fetch_shade_pipeline.c:416 #15 0x7fdea20de023 in vsplit_segment_simple_linear (vsplit=0x6401e0, flags=0, istart=0, icount=4) at draw/draw_pt_vsplit_tmp.h:240 #16 0x7fdea20de31a in vsplit_run_linear (frontend=0x6401e0, start=0, count=4) at draw/draw_split_tmp.h:60 #17 0x7fdea20d0c3d in draw_pt_arrays (draw=0x631bd0, prim=6, start=0, count=4) at draw/draw_pt.c:149 #18 0x7fdea20d1a68 in draw_vbo (draw=0x631bd0, info=0x7fff05947760) at draw/draw_pt.c:564 #19 0x7fdea1d7e555 in softpipe_draw_vbo (pipe=0x6439f0, info=0x7fff059478b0) at sp_draw_arrays.c:131 #20 0x7fdea20b8287 in cso_draw_vbo (cso=0x74b810, info=0x7fff059478b0) at cso_cache/cso_context.c:1428 #21 0x7fdea1f910b8 in st_draw_vbo (ctx=0x7fdea7a3b010, prims=0x7fff05947980, nr_prims=1, ib=0x0, index_bounds_valid=1 '\001', min_index=0, max_index=3, tfb_vertcount=0x0, indirect=0x0) at state_tracker/st_draw.c:276 #22 0x7fdea1f49a48 in vbo_draw_arrays (ctx=0x7fdea7a3b010, mode=6, start=0, count=4, numInstances=1, baseInstance=0) at vbo/vbo_exec_array.c:667 #23 0x7fdea1f4a493 in vbo_exec_DrawArrays (mode=6, start=0, count=4) at vbo/vbo_exec_array.c:819 #24 0x7fdea755d518 in stub_glDrawArrays (mode=6, first=0, count=4) at piglit/tests/util/generated_dispatch.c:6274 #25 0x00401592 in draw_rect_core (x=-1, y=-1, w=1, h=1) at piglit/tests/spec/gl-3.2/glsl-resource-not-bound.c:116 #26 0x004015bf in piglit_display () at piglit/tests/spec/gl-3.2/glsl-resource-not-bound.c:126 #27 0x7fdea754ec02 in display () at piglit/tests/util/piglit-framework-gl/piglit_glut_framework.c:60 #28 0x7fdea6ce6244 in fghRedrawWindow (window=0x62cba0) at freeglut_main.c:231 #29 fghcbDisplayWindow (window=0x62cba0, enumerator=0x7fff05947b40) at freeglut_main.c:248 #30 0x7fdea6ce9aa9 in fgEnumWindows (enumCallback=enumCallback@entry=0x7fdea6ce61d0 , enumerator=enumerator@entry=0x7fff05947b40) at freeglut_structure.c:396 #31 0x7fdea6ce67fd in fghDisplayAll () at freeglut_main.c:271 #32 glutMainLoopEvent () at freeglut_main.c:1523 #33 0x7fdea6ce6ffd in glutMainLoop () at freeglut_main.c:1571 #34 0x7fdea754ef3e in run_test (gl_fw=0x7fdea783f3c0 , argc=2, argv=0x7fff05947f18) at piglit/tests/util/piglit-framework-gl/piglit_glut_framework.c:167 #35 0x7fdea754cc39 in piglit_gl_test_run (argc=2, argv=0x7fff05947f18, config=0x7fff05947de0) at piglit/tests/util/piglit-framework-gl.c:151 #36 0x004010
[Mesa-dev] [Bug 79472] [llvmpipe] [softpipe] SIGSEGV src/gallium/auxiliary/draw/draw_cliptest_tmp.h:91
https://bugs.freedesktop.org/show_bug.cgi?id=79472 Vinson Lee changed: What|Removed |Added Summary|[llvmpipe] SIGSEGV |[llvmpipe] [softpipe] |src/gallium/auxiliary/draw/ |SIGSEGV |draw_cliptest_tmp.h:91 |src/gallium/auxiliary/draw/ ||draw_cliptest_tmp.h:91 --- Comment #1 from Vinson Lee --- softpipe also crashes in the same way with the same piglit test. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 80012] New: [softpipe] draw/draw_gs.c:113:tgsi_fetch_gs_outputs: Assertion `!util_is_inf_or_nan(output[slot][0])' failed.
https://bugs.freedesktop.org/show_bug.cgi?id=80012
Priority: medium
Bug ID: 80012
Keywords: have-backtrace
Assignee: mesa-dev@lists.freedesktop.org
Summary: [softpipe] draw/draw_gs.c:113:tgsi_fetch_gs_outputs:
Assertion `!util_is_inf_or_nan(output[slot][0])'
failed.
Severity: normal
Classification: Unclassified
OS: Linux (All)
Reporter: v...@freedesktop.org
Hardware: x86-64 (AMD64)
Status: NEW
Version: git
Component: Mesa core
Product: Mesa
mesa: ffe609cc69f328de5b57d4d7ab1d270fcf28de5f (master)
Run piglit texelFetch gs isampler1D test.
$ ./bin/texelFetch gs isampler1D -auto
65x1x1
draw/draw_gs.c:113:tgsi_fetch_gs_outputs: Assertion
`!util_is_inf_or_nan(output[slot][0])' failed.
(gdb) bt
#0 0x7f4e03a26e87 in _debug_assert_fail (expr=0x7f4e03b21440
"!util_is_inf_or_nan(output[slot][0])", file=0x7f4e03b2142c "draw/draw_gs.c",
line=113,
function=0x7f4e03b21620 <__func__.6832> "tgsi_fetch_gs_outputs") at
util/u_debug.c:309
#1 0x7f4e039c1596 in tgsi_fetch_gs_outputs (shader=0x208e7d0,
num_primitives=1, p_output=0x208f030) at draw/draw_gs.c:113
#2 0x7f4e039c1b34 in gs_flush (shader=0x208e7d0) at draw/draw_gs.c:410
#3 0x7f4e039c1bc9 in gs_point (shader=0x208e7d0, idx=1) at
draw/draw_gs.c:435
#4 0x7f4e039c1f4b in gs_run (gs=0x208e7d0, input_prims=0x7fffde9e0380,
input_verts=0x7fffde9e0250, output_prims=0x7fffde9e02b0,
output_verts=0x7fffde9e0270) at draw/draw_decompose_tmp.h:66
#5 0x7f4e039c3afb in draw_geometry_shader_run (shader=0x208e7d0,
constants=0x1bd3568, constants_size=0x1bd3668, input_verts=0x7fffde9e0250,
input_prim=0x7fffde9e0380, input_info=0x208f1b8,
output_verts=0x7fffde9e0270, output_prims=0x7fffde9e02b0) at
draw/draw_gs.c:629
#6 0x7f4e039db564 in fetch_pipeline_generic (middle=0x1c02900,
fetch_info=0x0, in_prim_info=0x7fffde9e0380) at
draw/draw_pt_fetch_shade_pipeline.c:290
#7 0x7f4e039db8af in fetch_pipeline_linear_run (middle=0x1c02900, start=0,
count=65, prim_flags=0) at draw/draw_pt_fetch_shade_pipeline.c:416
#8 0x7f4e039e4023 in vsplit_segment_simple_linear (vsplit=0x1be11e0,
flags=0, istart=0, icount=65) at draw/draw_pt_vsplit_tmp.h:240
#9 0x7f4e039e431a in vsplit_run_linear (frontend=0x1be11e0, start=0,
count=65) at draw/draw_split_tmp.h:60
#10 0x7f4e039d6c3d in draw_pt_arrays (draw=0x1bd2bd0, prim=0, start=0,
count=65) at draw/draw_pt.c:149
#11 0x7f4e039d7a68 in draw_vbo (draw=0x1bd2bd0, info=0x7fffde9e04e0) at
draw/draw_pt.c:564
#12 0x7f4e03684555 in softpipe_draw_vbo (pipe=0x1be49f0,
info=0x7fffde9e0630) at sp_draw_arrays.c:131
#13 0x7f4e039be287 in cso_draw_vbo (cso=0x1cec810, info=0x7fffde9e0630) at
cso_cache/cso_context.c:1428
#14 0x7f4e038970b8 in st_draw_vbo (ctx=0x7f4e09341010,
prims=0x7fffde9e0700, nr_prims=1, ib=0x0, index_bounds_valid=1 '\001',
min_index=0, max_index=64, tfb_vertcount=0x0, indirect=0x0)
at state_tracker/st_draw.c:276
#15 0x7f4e0384fa48 in vbo_draw_arrays (ctx=0x7f4e09341010, mode=0, start=0,
count=65, numInstances=1, baseInstance=0) at vbo/vbo_exec_array.c:667
#16 0x7f4e03850493 in vbo_exec_DrawArrays (mode=0, start=0, count=65) at
vbo/vbo_exec_array.c:819
#17 0x7f4e08e63518 in stub_glDrawArrays (mode=0, first=0, count=65) at
piglit/tests/util/generated_dispatch.c:6274
#18 0x00402d61 in test_once () at
piglit/tests/texturing/shaders/texelFetch.c:167
#19 0x00404bb0 in piglit_display () at
piglit/tests/texturing/shaders/texelFetch.c:931
#20 0x7f4e08e54c02 in display () at
piglit/tests/util/piglit-framework-gl/piglit_glut_framework.c:60
#21 0x7f4e082e6244 in fghRedrawWindow (window=0x1bcdba0) at
freeglut_main.c:231
#22 fghcbDisplayWindow (window=0x1bcdba0, enumerator=0x7fffde9e08e0) at
freeglut_main.c:248
#23 0x7f4e082e9aa9 in fgEnumWindows
(enumCallback=enumCallback@entry=0x7f4e082e61d0 ,
enumerator=enumerator@entry=0x7fffde9e08e0) at freeglut_structure.c:396
#24 0x7f4e082e67fd in fghDisplayAll () at freeglut_main.c:271
#25 glutMainLoopEvent () at freeglut_main.c:1523
#26 0x7f4e082e6ffd in glutMainLoop () at freeglut_main.c:1571
#27 0x7f4e08e54f3e in run_test (gl_fw=0x7f4e091453c0 , argc=3,
argv=0x7fffde9e0cb8) at
piglit/tests/util/piglit-framework-gl/piglit_glut_framework.c:167
#28 0x7f4e08e52c39 in piglit_gl_test_run (argc=3, argv=0x7fffde9e0cb8,
config=0x7fffde9e0b80) at piglit/tests/util/piglit-framework-gl.c:151
#29 0x00402b3d in main (argc=3, argv=0x7fffde9e0cb8) at
piglit/tests/texturing/shaders/texelFetch.c:102
(gdb) frame 1
#1 0x7f4e039c1596 in tgsi_fetch_gs_outputs (shader=0x208e7d0,
num_primitives=1, p_output=0x208f030) at draw/draw_gs.c:113
113debug_assert(!util_is_inf_or_nan(output[slot][0]));
(gdb) print slot
$1 = 1
(gdb) print output[slot]
$2 = {-nan(0x7f), 0, 0, 0}
--
You are receiving this
Re: [Mesa-dev] [PATCH 4/5] texstore: Add a generic implementation of GL_ARB_clear_texture
On Fri, Jun 13, 2014 at 8:59 PM, Neil Roberts wrote:
> Adds an implmentation of the ClearTexSubImage driver entry point that just
> maps the texture and writes the values in. This should work as a reliable
> fallback on any driver.
Will it? What about the MS case? I thought that for generic you had to
do a shader-based approach.
> ---
> src/mesa/drivers/common/driverfuncs.c | 2 +
> src/mesa/main/texstore.c | 70
> +++
> src/mesa/main/texstore.h | 7
> 3 files changed, 79 insertions(+)
>
> diff --git a/src/mesa/drivers/common/driverfuncs.c
> b/src/mesa/drivers/common/driverfuncs.c
> index ee8b390..34b6fef 100644
> --- a/src/mesa/drivers/common/driverfuncs.c
> +++ b/src/mesa/drivers/common/driverfuncs.c
> @@ -95,6 +95,7 @@ _mesa_init_driver_functions(struct dd_function_table
> *driver)
> driver->TexImage = _mesa_store_teximage;
> driver->TexSubImage = _mesa_store_texsubimage;
> driver->GetTexImage = _mesa_meta_GetTexImage;
> + driver->ClearTexSubImage = _mesa_store_cleartexsubimage;
> driver->CopyTexSubImage = _mesa_meta_CopyTexSubImage;
> driver->GenerateMipmap = _mesa_meta_GenerateMipmap;
> driver->TestProxyTexImage = _mesa_test_proxy_teximage;
> @@ -333,4 +334,5 @@ _mesa_init_driver_state(struct gl_context *ctx)
> void
> _mesa_init_driver_extensions(struct gl_context *ctx)
> {
> + ctx->Extensions.ARB_clear_texture = GL_TRUE;
> }
> diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
> index cb81f3f..9c90492 100644
> --- a/src/mesa/main/texstore.c
> +++ b/src/mesa/main/texstore.c
> @@ -4157,6 +4157,76 @@ _mesa_store_texsubimage(struct gl_context *ctx, GLuint
> dims,
> format, type, pixels, packing, "glTexSubImage");
> }
>
> +static void
> +clear_image_to_zero(GLubyte *dstMap, GLint dstRowStride,
> +GLsizei width, GLsizei height,
> +GLsizei clearValueSize)
> +{
> + while (height-- > 0) {
While I'm sure we all love the
while (height --> 0) { // as height goes to 0
construct... it's not immediately obvious (to me) that it's correct
when just glancing at it. After a few seconds of thought, it is
clearly right, but I think the more common thing is to use a for loop
where it's obvious there isn't some silly off-by-one error. I don't
think this is really used anywhere else in mesa. Here and below.
> + memset(dstMap, 0, clearValueSize * width);
> + dstMap += dstRowStride;
> + }
> +}
> +
> +static void
> +clear_image_to_value(GLubyte *dstMap, GLint dstRowStride,
> + GLsizei width, GLsizei height,
> + const GLvoid *clearValue,
> + GLsizei clearValueSize)
> +{
> + GLsizei x;
> +
> + while (height-- > 0) {
> + for (x = 0; x < width; x++) {
> + memcpy(dstMap, clearValue, clearValueSize);
> + dstMap += clearValueSize;
> + }
> + dstMap += dstRowStride - clearValueSize * width;
> + }
> +}
> +
> +/*
> + * Fallback for Driver.ClearTexSubImage().
> + */
> +void
> +_mesa_store_cleartexsubimage(struct gl_context *ctx,
> + struct gl_texture_image *texImage,
> + GLint xoffset, GLint yoffset, GLint zoffset,
> + GLsizei width, GLsizei height, GLsizei depth,
> + const GLvoid *clearValue)
> +{
> + GLubyte *dstMap;
> + GLint dstRowStride;
> + GLsizeiptr clearValueSize;
> + GLsizei z;
> +
> + clearValueSize = _mesa_get_format_bytes(texImage->TexFormat);
> +
> + for (z = 0; z < depth; z++) {
> + ctx->Driver.MapTextureImage(ctx, texImage,
> + z + zoffset, xoffset, yoffset,
> + width, height,
> + GL_MAP_WRITE_BIT,
> + &dstMap, &dstRowStride);
> + if (dstMap == NULL) {
> + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glClearTex*Image");
> + return;
> + }
> +
> + if (clearValue) {
> + clear_image_to_value(dstMap, dstRowStride,
> + width, height,
> + clearValue,
> + clearValueSize);
> + } else {
> + clear_image_to_zero(dstMap, dstRowStride,
> + width, height,
> + clearValueSize);
> + }
> +
> + ctx->Driver.UnmapTextureImage(ctx, texImage, z + zoffset);
> + }
> +}
>
> /**
> * Fallback for Driver.CompressedTexImage()
> diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h
> index c4cfffd..dd1e1d0 100644
> --- a/src/mesa/main/texstore.h
> +++ b/src/mesa/main/texstore.h
> @@ -118,6 +118,13 @@ _mesa_store_texsubimage(struct gl_context *ctx, GLuint
> dims,
>
>
> extern void
> +_mesa_store_cleartexsubimage(struct gl_context *ctx,
> + struct gl_texture_image *texIma
Re: [Mesa-dev] [PATCH 2/5] mesa/main: Add generic bits of ARB_clear_texture implementation
On Fri, Jun 13, 2014 at 8:59 PM, Neil Roberts wrote:
> This adds the driver entry point for glClearTexSubImage and fills in the
> _mesa_ClearTexImage and _mesa_ClearTexSubImage functions that call it.
> ---
> src/mesa/main/dd.h | 14 +++
> src/mesa/main/teximage.c | 241
> ++-
> src/mesa/main/teximage.h | 12 +++
> 3 files changed, 266 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
> index 633ea2c..8976535 100644
> --- a/src/mesa/main/dd.h
> +++ b/src/mesa/main/dd.h
> @@ -239,6 +239,20 @@ struct dd_function_table {
> struct gl_texture_image *texImage );
>
> /**
> +* Called by glClearTex[Sub]Image
> +*
> +* Clears a rectangular region of the image to a given value. The
> +* clearValue argument is either NULL or points to a single texel to use
> as
> +* the clear value in the same internal format as the texture image. If it
> +* is NULL then the texture should be cleared to zeroes.
> +*/
> + void (*ClearTexSubImage)(struct gl_context *ctx,
> +struct gl_texture_image *texImage,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +const GLvoid *clearValue);
> +
> + /**
> * Called by glCopyTex[Sub]Image[123]D().
> *
> * This function should copy a rectangular region in the rb to a single
> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> index a893c70..d5baac8 100644
> --- a/src/mesa/main/teximage.c
> +++ b/src/mesa/main/teximage.c
> @@ -51,6 +51,7 @@
> #include "textureview.h"
> #include "mtypes.h"
> #include "glformats.h"
> +#include "texstore.h"
>
>
> /**
> @@ -3848,20 +3849,259 @@ _mesa_CopyTexSubImage3D( GLenum target, GLint level,
> x, y, width, height);
> }
>
> +static bool
> +clear_tex_image(struct gl_context *ctx,
> +const char *function,
> +struct gl_texture_image *texImage, GLint level,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +GLenum format, GLenum type,
> +const void *data)
> +{
> + struct gl_texture_object *texObj = texImage->TexObject;
> + static const GLubyte zeroData[MAX_PIXEL_BYTES];
> + GLubyte clearValue[MAX_PIXEL_BYTES];
> + GLubyte *clearValuePtr = clearValue;
> + GLenum internalFormat = texImage->InternalFormat;
> + GLenum err;
> +
> + if (texObj->Target == GL_TEXTURE_BUFFER) {
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(buffer texture)", function);
> + return false;
> + }
> +
> + if (_mesa_is_compressed_format(ctx, internalFormat)) {
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(compressed texture)", function);
> + return false;
> + }
> +
> + err = _mesa_error_check_format_and_type(ctx, format, type);
> + if (err != GL_NO_ERROR) {
> + _mesa_error(ctx, err,
> + "%s(incompatible format = %s, type = %s)",
> + function,
> + _mesa_lookup_enum_by_nr(format),
> + _mesa_lookup_enum_by_nr(type));
> + return false;
> + }
> +
> + /* make sure internal format and format basically agree */
> + if (!texture_formats_agree(internalFormat, format)) {
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(incompatible internalFormat = %s, format = %s)",
> + function,
> + _mesa_lookup_enum_by_nr(internalFormat),
> + _mesa_lookup_enum_by_nr(format));
> + return false;
> + }
> +
> + if (ctx->Version >= 30 || ctx->Extensions.EXT_texture_integer) {
Just ctx->Extensions.EXT_texture_integer should be enough here, no?
> + /* both source and dest must be integer-valued, or neither */
> + if (_mesa_is_format_integer_color(texImage->TexFormat) !=
> + _mesa_is_enum_format_integer(format)) {
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(integer/non-integer format mismatch)",
> + function);
> + return false;
> + }
> + }
> +
> + if (!_mesa_texstore(ctx,
> + 1, /* dims */
> + texImage->_BaseFormat,
> + texImage->TexFormat,
> + 0, /* dstRowStride */
> + &clearValuePtr,
> + 1, 1, 1, /* srcWidth/Height/Depth */
> + format, type,
> + data ? data : zeroData,
> + &ctx->DefaultPacking)) {
> + _mesa_error(ctx, GL_INVALID_OPERATION, "%s(invalid format)", function);
> + return false;
> + }
> +
> + ctx->Driver.ClearTexSubImage(ctx,
> +texI
[Mesa-dev] [PATCH] radeonsi: fixup sizes of shader resource and sampler arrays
From: Marek Olšák
This was wrong for a very long time. I wonder if the array size has any
effect on anything.
---
src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index a7ca35b..4ed5906 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2266,9 +2266,9 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
/* We assume at most 16 textures per program at the moment.
* This need probably need to be changed to support bindless textures */
params[SI_PARAM_SAMPLER] = LLVMPointerType(
- LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS),
CONST_ADDR_SPACE);
+ LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_STATES),
CONST_ADDR_SPACE);
params[SI_PARAM_RESOURCE] = LLVMPointerType(
- LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES),
CONST_ADDR_SPACE);
+ LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_VIEWS),
CONST_ADDR_SPACE);
switch (si_shader_ctx->type) {
case TGSI_PROCESSOR_VERTEX:
--
1.9.1
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Re: [Mesa-dev] [PATCH v2 0/6] Implement ARB_clear_texture
On Fri, Jun 13, 2014 at 8:59 PM, Neil Roberts wrote: > Here is a second attempt at implementing the GL_ARB_clear_texture > extension. I've split up the patch into serveral smaller patches. They > are based on top of the first patch in Ilia's series which is > available here: > > https://github.com/imirkin/mesa/commit/9c2467020a8a3895a1debbad06561f37 The usual thing is to include it in your patch series. Assuming you're using git tooling and properly import it, you should be able to maintain me as the author, and when you email it out it'll start with "From: Ilia Mirkin <...>". > > I think I've addressed all of the issues mentioned in the reviews. > Instead of enabling the extension unconditionally I've added a helper > function which is called by all DRI-based drivers. The intention is > for this to be a place to enable all extensions which are implemented > for free by calling _mesa_init_driver_functions. > > On the piglit mailing list I've posted some more tests including one > which checks some error conditions and another which tests integer > textures. > > The patch series is available on a branch in Github here: > > https://github.com/bpeel/mesa/tree/wip/clear-texture > > The piglit patches are available here: > > https://github.com/bpeel/piglit/tree/wip/clear-texture > > - Neil > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] mesa/drivers: Fix clang constant-logical-operand warnings.
This patch fixes several clang constant-logical-operand warnings such as
the following.
../../../../../src/mesa/tnl_dd/t_dd_tritmp.h:130:32: warning: use of logical
'||' with constant operand [-Wconstant-logical-operand]
if (DO_TWOSIDE || DO_OFFSET || DO_UNFILLED || DO_TWOSTENCIL)
^ ~~~
../../../../../src/mesa/tnl_dd/t_dd_tritmp.h:130:32: note: use '|' for a
bitwise operation
if (DO_TWOSIDE || DO_OFFSET || DO_UNFILLED || DO_TWOSTENCIL)
^~
|
Signed-off-by: Vinson Lee
---
v2: Updated after comments from Matt Turner.
src/mesa/drivers/dri/i915/intel_tris.c | 8
src/mesa/drivers/dri/r200/r200_swtcl.c | 4 ++--
src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 10 +-
src/mesa/drivers/dri/radeon/radeon_swtcl.c | 4 ++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c
b/src/mesa/drivers/dri/i915/intel_tris.c
index 97dbcbd..94d85ce 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -602,10 +602,10 @@ static struct
} rast_tab[INTEL_MAX_TRIFUNC];
-#define DO_FALLBACK (IND & INTEL_FALLBACK_BIT)
-#define DO_OFFSET (IND & INTEL_OFFSET_BIT)
-#define DO_UNFILLED (IND & INTEL_UNFILLED_BIT)
-#define DO_TWOSIDE (IND & INTEL_TWOSIDE_BIT)
+#define DO_FALLBACK ((IND & INTEL_FALLBACK_BIT) != 0)
+#define DO_OFFSET ((IND & INTEL_OFFSET_BIT) != 0)
+#define DO_UNFILLED ((IND & INTEL_UNFILLED_BIT) != 0)
+#define DO_TWOSIDE ((IND & INTEL_TWOSIDE_BIT) != 0)
#define DO_FLAT 0
#define DO_TRI 1
#define DO_QUAD 1
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c
b/src/mesa/drivers/dri/r200/r200_swtcl.c
index 28604ea..07c64f8 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -411,8 +411,8 @@ static struct {
#define DO_FALLBACK 0
-#define DO_UNFILLED (IND & R200_UNFILLED_BIT)
-#define DO_TWOSIDE (IND & R200_TWOSIDE_BIT)
+#define DO_UNFILLED ((IND & R200_UNFILLED_BIT) != 0)
+#define DO_TWOSIDE ((IND & R200_TWOSIDE_BIT) != 0)
#define DO_FLAT 0
#define DO_OFFSET 0
#define DO_TRI 1
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
index cb8c7b3..9a77850 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
@@ -67,11 +67,11 @@ static struct {
_mesa_need_secondary_color(ctx))
#define DO_FOG ((IND & RADEON_CP_VC_FRMT_PKSPEC) && ctx->Fog.Enabled && \
(ctx->Fog.FogCoordinateSource == GL_FOG_COORD))
-#define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
-#define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
-#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2)
-#define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
-#define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
+#define DO_TEX0 ((IND & RADEON_CP_VC_FRMT_ST0) != 0)
+#define DO_TEX1 ((IND & RADEON_CP_VC_FRMT_ST1) != 0)
+#define DO_TEX2 ((IND & RADEON_CP_VC_FRMT_ST2) != 0)
+#define DO_PTEX ((IND & RADEON_CP_VC_FRMT_Q0) != 0)
+#define DO_NORM ((IND & RADEON_CP_VC_FRMT_N0) != 0)
#define DO_TEX3 0
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index fae151a..abed7da 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -536,8 +536,8 @@ static struct {
#define DO_FALLBACK 0
#define DO_OFFSET0
-#define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
-#define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
+#define DO_UNFILLED ((IND & RADEON_UNFILLED_BIT) != 0)
+#define DO_TWOSIDE ((IND & RADEON_TWOSIDE_BIT) != 0)
#define DO_FLAT 0
#define DO_TRI 1
#define DO_QUAD 1
--
1.9.3
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Re: [Mesa-dev] [PATCH 3/5] Add a place to enable extensions that are common to all DRI drivers
Neil,
I've been thinking about this same thing. My one comment is that it might
be good to call that function after the driver has installed its
extensions. That way you can make meta extensions dependant on driver
extensions. Not sure how useful that is though.
--Jason Ekstrand
On Jun 13, 2014 5:59 PM, "Neil Roberts" wrote:
> This adds a function called _mesa_init_driver_extensions that is called by
> all
> DRI-based drivers. The intention is that any extensions that are
> implemented
> directly by _mesa_init_driver_functions without any driver-specific
> entrypoints will be enabled here.
> ---
> src/mesa/drivers/common/driverfuncs.c | 8
> src/mesa/drivers/common/driverfuncs.h | 2 ++
> src/mesa/drivers/dri/i915/intel_extensions.c | 3 +++
> src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++
> src/mesa/drivers/dri/nouveau/nouveau_context.c | 1 +
> src/mesa/drivers/dri/r200/r200_context.c | 2 ++
> src/mesa/drivers/dri/radeon/radeon_context.c | 2 ++
> src/mesa/drivers/dri/swrast/swrast.c | 1 +
> 8 files changed, 22 insertions(+)
>
> diff --git a/src/mesa/drivers/common/driverfuncs.c
> b/src/mesa/drivers/common/driverfuncs.c
> index 6ece5d8..ee8b390 100644
> --- a/src/mesa/drivers/common/driverfuncs.c
> +++ b/src/mesa/drivers/common/driverfuncs.c
> @@ -326,3 +326,11 @@ _mesa_init_driver_state(struct gl_context *ctx)
>
> ctx->Driver.DrawBuffer(ctx, ctx->Color.DrawBuffer[0]);
> }
> +
> +/**
> + * Enable extensions that are available for all DRI-based drivers.
> + */
> +void
> +_mesa_init_driver_extensions(struct gl_context *ctx)
> +{
> +}
> diff --git a/src/mesa/drivers/common/driverfuncs.h
> b/src/mesa/drivers/common/driverfuncs.h
> index 6b9a900..520c059 100644
> --- a/src/mesa/drivers/common/driverfuncs.h
> +++ b/src/mesa/drivers/common/driverfuncs.h
> @@ -33,5 +33,7 @@ _mesa_init_driver_functions(struct dd_function_table
> *driver);
> extern void
> _mesa_init_driver_state(struct gl_context *ctx);
>
> +extern void
> +_mesa_init_driver_extensions(struct gl_context *ctx);
>
> #endif
> diff --git a/src/mesa/drivers/dri/i915/intel_extensions.c
> b/src/mesa/drivers/dri/i915/intel_extensions.c
> index 76f608e..3a8744a 100644
> --- a/src/mesa/drivers/dri/i915/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i915/intel_extensions.c
> @@ -31,6 +31,7 @@
> #include "intel_context.h"
> #include "intel_extensions.h"
> #include "intel_reg.h"
> +#include "drivers/common/driverfuncs.h"
> #include "utils.h"
>
> /**
> @@ -44,6 +45,8 @@ intelInitExtensions(struct gl_context *ctx)
>
> assert(intel->gen == 2 || intel->gen == 3);
>
> + _mesa_init_driver_extensions(ctx);
> +
> ctx->Extensions.ARB_draw_elements_base_vertex = true;
> ctx->Extensions.ARB_explicit_attrib_location = true;
> ctx->Extensions.ARB_framebuffer_object = true;
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index 39d0ab5..fe47464 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -31,6 +31,7 @@
> #include "intel_batchbuffer.h"
> #include "intel_reg.h"
> #include "utils.h"
> +#include "drivers/common/driverfuncs.h"
>
> /**
> * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
> @@ -162,6 +163,8 @@ intelInitExtensions(struct gl_context *ctx)
>
> assert(brw->gen >= 4);
>
> + _mesa_init_driver_extensions(ctx);
> +
> ctx->Extensions.ARB_buffer_storage = true;
> ctx->Extensions.ARB_depth_buffer_float = true;
> ctx->Extensions.ARB_depth_clamp = true;
> diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c
> b/src/mesa/drivers/dri/nouveau/nouveau_context.c
> index f8c8dc3..ad7ee86 100644
> --- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
> +++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
> @@ -183,6 +183,7 @@ nouveau_context_init(struct gl_context *ctx, gl_api
> api,
> }
>
> /* Enable any supported extensions. */
> +_mesa_init_driver_extensions(ctx);
> ctx->Extensions.EXT_blend_color = true;
> ctx->Extensions.EXT_blend_minmax = true;
> ctx->Extensions.EXT_texture_filter_anisotropic = true;
> diff --git a/src/mesa/drivers/dri/r200/r200_context.c
> b/src/mesa/drivers/dri/r200/r200_context.c
> index 71dfcf3..93ca23d 100644
> --- a/src/mesa/drivers/dri/r200/r200_context.c
> +++ b/src/mesa/drivers/dri/r200/r200_context.c
> @@ -366,6 +366,8 @@ GLboolean r200CreateContext( gl_api api,
> _math_matrix_ctr( &rmesa->tmpmat );
> _math_matrix_set_identity( &rmesa->tmpmat );
>
> + _mesa_init_driver_extensions(ctx);
> +
> ctx->Extensions.ARB_occlusion_query = true;
> ctx->Extensions.ARB_point_sprite = true;
> ctx->Extensions.ARB_texture_border_clamp = true;
> diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
> b/src/mesa/drivers/dri/radeon/radeon_context.c
> index 1ceb4ab..fd8e95b 100644
> --- a/src/mesa/drivers/dri/radeon/rade
[Mesa-dev] [PATCH] Revert "i965: Add 'wait' instruction support"
This reverts commit 20be3ff57670529a410b30a1008a71e768d08428.
No evidence of ever being used.
---
src/mesa/drivers/dri/i965/brw_eu.h | 2 --
src/mesa/drivers/dri/i965/brw_eu_emit.c | 16
src/mesa/drivers/dri/i965/brw_reg.h | 16
3 files changed, 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 7a6c339..0f8cd42 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -346,8 +346,6 @@ brw_inst *brw_JMPI(struct brw_compile *p, struct brw_reg
index,
void brw_NOP(struct brw_compile *p);
-void brw_WAIT(struct brw_compile *p);
-
/* Special case: there is never a destination, execution size will be
* taken from src0:
*/
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index df1a4c8..5ea269c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1773,22 +1773,6 @@ void brw_CMP(struct brw_compile *p,
}
}
-/* Issue 'wait' instruction for n1, host could program MMIO
- to wake up thread. */
-void brw_WAIT (struct brw_compile *p)
-{
- const struct brw_context *brw = p->brw;
- brw_inst *insn = next_insn(p, BRW_OPCODE_WAIT);
- struct brw_reg src = brw_notification_1_reg();
-
- brw_set_dest(p, insn, src);
- brw_set_src0(p, insn, src);
- brw_set_src1(p, insn, brw_null_reg());
- brw_inst_set_exec_size(brw, insn, 0); /* must */
- brw_inst_set_pred_control(brw, insn, 0);
- brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
-}
-
/***
* Helpers for the various SEND message types:
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 38c0ae5..fc2e0b0 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -633,22 +633,6 @@ brw_acc_reg(void)
}
static inline struct brw_reg
-brw_notification_1_reg(void)
-{
-
- return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_NOTIFICATION_COUNT,
- 1,
- BRW_REGISTER_TYPE_UD,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_,
- WRITEMASK_X);
-}
-
-
-static inline struct brw_reg
brw_flag_reg(int reg, int subreg)
{
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
--
1.8.3.2
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Re: [Mesa-dev] [PATCH v2] mesa/drivers: Fix clang constant-logical-operand warnings.
Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/19] i965: Convert brw_sf_emit.c to the new brw_inst API.
From: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_sf_emit.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c
b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index 8f26e41..04d21a8 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -732,6 +732,7 @@ void brw_emit_point_setup(struct brw_sf_compile *c, bool
allocate)
void brw_emit_anyprim_setup( struct brw_sf_compile *c )
{
struct brw_compile *p = &c->func;
+ struct brw_context *brw = p->brw;
struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0);
struct brw_reg payload_attr =
get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0);
struct brw_reg primmask;
@@ -753,7 +754,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_POLYGON) |
(1<<_3DPRIM_RECTLIST) |
(1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_Z;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_tri_setup(c, false);
brw_land_fwd_jump(p, jmp);
@@ -764,13 +765,13 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_LINESTRIP_CONT) |
(1<<_3DPRIM_LINESTRIP_BF) |
(1<<_3DPRIM_LINESTRIP_CONT_BF)));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_Z;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z);
jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store;
brw_emit_line_setup(c, false);
brw_land_fwd_jump(p, jmp);
brw_AND(p, v1_null_ud, payload_attr,
brw_imm_ud(1store;
brw_emit_point_sprite_setup(c, false);
brw_land_fwd_jump(p, jmp);
--
1.8.3.2
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[Mesa-dev] [PATCH 03/19] i965: Convert brw_eu.[ch] to use the new brw_inst API.
From: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_eu.c | 30 +++---
src/mesa/drivers/dri/i965/brw_eu.h | 3 ++-
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index d2ff3f5..08fbf0b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -90,23 +90,23 @@ brw_swap_cmod(uint32_t cmod)
void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc )
{
- p->current->header.predicate_control = pc;
+ brw_inst_set_pred_control(p->brw, p->current, pc);
}
void brw_set_default_predicate_inverse(struct brw_compile *p, bool
predicate_inverse)
{
- p->current->header.predicate_inverse = predicate_inverse;
+ brw_inst_set_pred_inv(p->brw, p->current, predicate_inverse);
}
void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg)
{
- p->current->bits2.da1.flag_reg_nr = reg;
- p->current->bits2.da1.flag_subreg_nr = subreg;
+ brw_inst_set_flag_reg_nr(p->brw, p->current, reg);
+ brw_inst_set_flag_subreg_nr(p->brw, p->current, subreg);
}
void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode )
{
- p->current->header.access_mode = access_mode;
+ brw_inst_set_access_mode(p->brw, p->current, access_mode);
}
void
@@ -126,36 +126,36 @@ brw_set_default_compression_control(struct brw_compile *p,
/* This is the "use the first set of bits of dmask/vmask/arf
* according to execsize" option.
*/
-p->current->header.compression_control = GEN6_COMPRESSION_1Q;
+ brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1Q);
break;
case BRW_COMPRESSION_2NDHALF:
/* For SIMD8, this is "use the second set of 8 bits." */
-p->current->header.compression_control = GEN6_COMPRESSION_2Q;
+ brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_2Q);
break;
case BRW_COMPRESSION_COMPRESSED:
/* For SIMD16 instruction compression, use the first set of 16 bits
* since we don't do SIMD32 dispatch.
*/
-p->current->header.compression_control = GEN6_COMPRESSION_1H;
+ brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
break;
default:
assert(!"not reached");
-p->current->header.compression_control = GEN6_COMPRESSION_1H;
+ brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
break;
}
} else {
- p->current->header.compression_control = compression_control;
+ brw_inst_set_qtr_control(brw, p->current, compression_control);
}
}
void brw_set_default_mask_control( struct brw_compile *p, unsigned value )
{
- p->current->header.mask_control = value;
+ brw_inst_set_mask_control(p->brw, p->current, value);
}
void brw_set_default_saturate( struct brw_compile *p, bool enable )
{
- p->current->header.saturate = enable;
+ brw_inst_set_saturate(p->brw, p->current, enable);
}
void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
@@ -163,7 +163,7 @@ void brw_set_default_acc_write_control(struct brw_compile
*p, unsigned value)
struct brw_context *brw = p->brw;
if (brw->gen >= 6)
- p->current->header.acc_wr_control = value;
+ brw_inst_set_acc_wr_control(p->brw, p->current, value);
}
void brw_push_insn_state( struct brw_compile *p )
@@ -240,10 +240,10 @@ brw_disassemble(struct brw_context *brw,
for (int offset = start; offset < end;) {
struct brw_instruction *insn = assembly + offset;
struct brw_instruction uncompacted;
- bool compacted = insn->header.cmpt_control;
+ bool compacted = brw_inst_cmpt_control(brw, insn);
fprintf(out, "0x%08x: ", offset);
- if (insn->header.cmpt_control) {
+ if (compacted) {
struct brw_compact_instruction *compacted = (void *)insn;
if (dump_hex) {
fprintf(out, "0x%08x 0x%08x ",
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 9f1a5fd..84f293e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -34,6 +34,7 @@
#define BRW_EU_H
#include
+#include "brw_inst.h"
#include "brw_structs.h"
#include "brw_defines.h"
#include "brw_reg.h"
@@ -434,7 +435,7 @@ next_offset(const struct brw_context *brw, void *store, int
offset)
struct brw_instruction *insn =
(struct brw_instruction *)((char *)store + offset);
- if (insn->header.cmpt_control)
+ if (brw_inst_cmpt_control(brw, insn))
return offset + 8;
else
return offset + 16;
--
1.8.3.2
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[Mesa-dev] [PATCH 01/19] i965: Pass brw into next_offset().
From: Kenneth Graunke
The new brw_inst API is going to require a brw pointer in order
to access fields (so it can do generation checks). Plumb it in now.
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_eu.h | 2 +-
src/mesa/drivers/dri/i965/brw_eu_compact.c | 6 +++---
src/mesa/drivers/dri/i965/brw_eu_emit.c| 13 -
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 83f1eba..9f1a5fd 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -429,7 +429,7 @@ void brw_debug_compact_uncompact(struct brw_context *brw,
struct brw_instruction *uncompacted);
static inline int
-next_offset(void *store, int offset)
+next_offset(const struct brw_context *brw, void *store, int offset)
{
struct brw_instruction *insn =
(struct brw_instruction *)((char *)store + offset);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 0560367..0ae3f2d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -808,7 +808,7 @@ brw_compact_instructions(struct brw_compile *p, int
start_offset,
break;
}
- offset = next_offset(store, offset);
+ offset = next_offset(brw, store, offset);
}
/* p->nr_insn is counting the number of uncompacted instructions still, so
@@ -831,12 +831,12 @@ brw_compact_instructions(struct brw_compile *p, int
start_offset,
while (start_offset + old_ip[offset / 8] * 8 != annotation[i].offset)
{
assert(start_offset + old_ip[offset / 8] * 8 <
annotation[i].offset);
-offset = next_offset(store, offset);
+offset = next_offset(brw, store, offset);
}
annotation[i].offset = start_offset + offset;
- offset = next_offset(store, offset);
+ offset = next_offset(brw, store, offset);
}
annotation[num_annotations].offset = p->next_insn_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 68b03b7..8f34b43 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2371,9 +2371,11 @@ brw_find_next_block_end(struct brw_compile *p, int
start_offset)
{
int offset;
void *store = p->store;
+ const struct brw_context *brw = p->brw;
- for (offset = next_offset(store, start_offset); offset <
p->next_insn_offset;
-offset = next_offset(store, offset)) {
+ for (offset = next_offset(brw, store, start_offset);
+offset < p->next_insn_offset;
+offset = next_offset(brw, store, offset)) {
struct brw_instruction *insn = store + offset;
switch (insn->header.opcode) {
@@ -2403,8 +2405,9 @@ brw_find_loop_end(struct brw_compile *p, int start_offset)
/* Always start after the instruction (such as a WHILE) we're trying to fix
* up.
*/
- for (offset = next_offset(store, start_offset); offset <
p->next_insn_offset;
-offset = next_offset(store, offset)) {
+ for (offset = next_offset(brw, store, start_offset);
+offset < p->next_insn_offset;
+offset = next_offset(brw, store, offset)) {
struct brw_instruction *insn = store + offset;
if (insn->header.opcode == BRW_OPCODE_WHILE) {
@@ -2433,7 +2436,7 @@ brw_set_uip_jip(struct brw_compile *p)
return;
for (offset = 0; offset < p->next_insn_offset;
-offset = next_offset(store, offset)) {
+offset = next_offset(brw, store, offset)) {
struct brw_instruction *insn = store + offset;
if (insn->header.cmpt_control) {
--
1.8.3.2
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[Mesa-dev] [PATCH 06/19] i965: Convert Gen4-5 clipping code to the new brw_inst API.
From: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_clip_line.c | 21 +++--
src/mesa/drivers/dri/i965/brw_clip_tri.c | 44 +++
src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 26 +---
src/mesa/drivers/dri/i965/brw_clip_util.c | 2 +-
4 files changed, 52 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c
b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 7e218f5..90cd07c 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -158,9 +158,9 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
if (brw->has_negative_rhw_bug) {
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
- brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
}
/* Set the initial vertex source mask: The first 6 planes are the bounds
@@ -177,12 +177,12 @@ static void clip_and_emit_line( struct brw_clip_compile
*c )
/* if (planemask & 1)
*/
brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
brw_AND(p, v1_null_ud, c->reg.vertex_src_mask, brw_imm_ud(1));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
/* user clip distance: just fetch the correct float from each
vertex */
@@ -228,7 +228,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t,
c->reg.t1 );
brw_MOV(p, c->reg.t1, c->reg.t);
- brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, brw_last_inst,
BRW_PREDICATE_NORMAL);
}
brw_ELSE(p);
{
@@ -250,7 +250,8 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t,
c->reg.t0 );
brw_MOV(p, c->reg.t0, c->reg.t);
- brw_last_inst->header.predicate_control =
BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, brw_last_inst,
+ BRW_PREDICATE_NORMAL);
}
if (brw->has_negative_rhw_bug) {
@@ -268,14 +269,14 @@ static void clip_and_emit_line( struct brw_clip_compile
*c )
/* while (planemask>>=1) != 0
*/
brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask,
brw_imm_ud(1));
- brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset,
brw_imm_w(sizeof(float)));
- brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
}
brw_WHILE(p);
- brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL);
brw_ADD(p, c->reg.t, c->reg.t0, c->reg.t1);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t,
brw_imm_f(1.0));
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index ceae282..62336fc 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -235,10 +235,11 @@ load_clip_distance(struct brw_clip_compile *c, struct
brw_indirect vtx,
struct brw_reg dst, GLuint hpos_offset, int cond)
{
struct brw_compile *p = &c->func;
+ const struct brw_context *brw = p->brw;
dst = vec4(dst);
brw_AND(p, vec1(brw_null_reg()), c->reg.vertex_src_mask, brw_imm_ud(1));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
{
struct brw_indirect temp_ptr = brw_indirect(7, 0);
@@ -261,6 +262,7 @@ load_clip_distance(struct brw_clip_compile *c, struct
brw
[Mesa-dev] [PATCH 09/19] i965: Convert test_eu_compact.c to the new brw_inst API.
From: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/test_eu_compact.c | 41 +
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/test_eu_compact.c
b/src/mesa/drivers/dri/i965/test_eu_compact.c
index 809b557..2dd76db 100644
--- a/src/mesa/drivers/dri/i965/test_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/test_eu_compact.c
@@ -67,23 +67,20 @@ test_compact_instruction(struct brw_compile *p, struct
brw_instruction src)
* become meaningless once fuzzing twiddles a related bit.
*/
static void
-clear_pad_bits(struct brw_instruction *inst)
+clear_pad_bits(const struct brw_context *brw, struct brw_instruction *inst)
{
- if (inst->header.opcode != BRW_OPCODE_SEND &&
- inst->header.opcode != BRW_OPCODE_SENDC &&
- inst->header.opcode != BRW_OPCODE_BREAK &&
- inst->header.opcode != BRW_OPCODE_CONTINUE &&
- inst->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE &&
- inst->bits1.da1.src1_reg_file != BRW_IMMEDIATE_VALUE) {
- if (inst->bits3.da1.src1_address_mode)
-inst->bits3.ia1.pad1 = 0;
- else
-inst->bits3.da1.pad0 = 0;
+ if (brw_inst_opcode(brw, inst) != BRW_OPCODE_SEND &&
+ brw_inst_opcode(brw, inst) != BRW_OPCODE_SENDC &&
+ brw_inst_opcode(brw, inst) != BRW_OPCODE_BREAK &&
+ brw_inst_opcode(brw, inst) != BRW_OPCODE_CONTINUE &&
+ brw_inst_src0_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE &&
+ brw_inst_src1_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE) {
+ brw_inst_set_bits(inst, 127, 111, 0);
}
}
static bool
-skip_bit(struct brw_instruction *src, int bit)
+skip_bit(const struct brw_context *brw, struct brw_instruction *src, int bit)
{
/* pad bit */
if (bit == 7)
@@ -102,12 +99,12 @@ skip_bit(struct brw_instruction *src, int bit)
return true;
/* sometimes these are pad bits. */
- if (src->header.opcode != BRW_OPCODE_SEND &&
- src->header.opcode != BRW_OPCODE_SENDC &&
- src->header.opcode != BRW_OPCODE_BREAK &&
- src->header.opcode != BRW_OPCODE_CONTINUE &&
- src->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE &&
- src->bits1.da1.src1_reg_file != BRW_IMMEDIATE_VALUE &&
+ if (brw_inst_opcode(brw, src) != BRW_OPCODE_SEND &&
+ brw_inst_opcode(brw, src) != BRW_OPCODE_SENDC &&
+ brw_inst_opcode(brw, src) != BRW_OPCODE_BREAK &&
+ brw_inst_opcode(brw, src) != BRW_OPCODE_CONTINUE &&
+ brw_inst_src0_reg_file(brw, src) != BRW_IMMEDIATE_VALUE &&
+ brw_inst_src1_reg_file(brw, src) != BRW_IMMEDIATE_VALUE &&
bit >= 121) {
return true;
}
@@ -120,20 +117,20 @@ test_fuzz_compact_instruction(struct brw_compile *p,
struct brw_instruction src)
{
for (int bit0 = 0; bit0 < 128; bit0++) {
- if (skip_bit(&src, bit0))
+ if (skip_bit(p->brw, &src, bit0))
continue;
for (int bit1 = 0; bit1 < 128; bit1++) {
struct brw_instruction instr = src;
uint32_t *bits = (uint32_t *)&instr;
-if (skip_bit(&src, bit1))
+if (skip_bit(p->brw, &src, bit1))
continue;
bits[bit0 / 32] ^= (1 << (bit0 & 31));
bits[bit1 / 32] ^= (1 << (bit1 & 31));
-clear_pad_bits(&instr);
+clear_pad_bits(p->brw, &instr);
if (!test_compact_instruction(p, instr)) {
printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1);
@@ -237,7 +234,7 @@ gen_f0_1_MOV_GRF_GRF(struct brw_compile *p)
brw_push_insn_state(p);
brw_set_default_predicate_control(p, true);
struct brw_instruction *mov = brw_MOV(p, g0, g2);
- mov->bits2.da1.flag_subreg_nr = 1;
+ brw_inst_set_flag_subreg_nr(p->brw, mov, 1);
brw_pop_insn_state(p);
}
--
1.8.3.2
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[Mesa-dev] [PATCH 02/19] i965: Introduce a new brw_inst API.
From: Kenneth Graunke
This is similar to gen8_instruction, and will replace it
For now nothing uses this, but we can incrementally convert.
The new API takes the existing brw_instruction pointers to ease
conversion; when done, we can simply drop the old structure and rename
struct brw_instruction -> brw_inst.
Reviewed-by: Matt Turner
---
src/mesa/drivers/dri/i965/brw_inst.h | 660 +++
1 file changed, 660 insertions(+)
create mode 100644 src/mesa/drivers/dri/i965/brw_inst.h
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
b/src/mesa/drivers/dri/i965/brw_inst.h
new file mode 100644
index 000..a0cef08
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/**
+ * @file brw_inst.h
+ *
+ * A representation of i965 EU assembly instructions, with helper methods to
+ * get and set various fields. This is the actual hardware format.
+ */
+
+#ifndef BRW_INST_H
+#define BRW_INST_H
+
+#include
+#include
+
+#include "brw_context.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct brw_instruction;
+
+typedef struct {
+ uint64_t data[2];
+} brw_inst;
+
+static inline uint64_t brw_inst_bits(struct brw_instruction *inst,
+ unsigned high, unsigned low);
+static inline void brw_inst_set_bits(struct brw_instruction *inst,
+ unsigned high, unsigned low,
+ uint64_t value);
+
+#define FC(name, high, low, assertions) \
+static inline void\
+brw_inst_set_##name(const struct brw_context *brw,\
+struct brw_instruction *inst, uint64_t v) \
+{ \
+ assert(assertions);\
+ brw_inst_set_bits(inst, high, low, v); \
+} \
+static inline uint64_t\
+brw_inst_##name(const struct brw_context *brw,\
+struct brw_instruction *inst) \
+{ \
+ assert(assertions);\
+ return brw_inst_bits(inst, high, low); \
+}
+
+/* A simple macro for fields which stay in the same place on all generations.
*/
+#define F(name, high, low) FC(name, high, low, true)
+
+#define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
+ unsigned high, low; \
+ if (brw->gen >= 8) { \
+ high = hi8; low = lo8;\
+ } else if (brw->gen >= 7) { \
+ high = hi7; low = lo7;\
+ } else if (brw->gen >= 6) { \
+ high = hi6; low = lo6;\
+ } else if (brw->gen >= 5) { \
+ high = hi5; low = lo5;\
+ } else if (brw->is_g4x) { \
+ high = hi45; low = lo45; \
+ } else { \
+ high = hi4; low = lo4;\
+ } \
+ assert(((int) high) != -1 && ((int) low) != -1); \
+
+/* A general macro for c
[Mesa-dev] [PATCH 17/19] i965: Introduce a new brw_compact_inst API.
For now nothing uses this, but we can incrementally convert.
---
src/mesa/drivers/dri/i965/brw_inst.h | 90
1 file changed, 90 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h
b/src/mesa/drivers/dri/i965/brw_inst.h
index c2dda5d..83a64fe 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -645,6 +645,96 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned
low, uint64_t value)
#undef F
#undef FC
+typedef struct {
+ uint64_t data;
+} brw_compact_inst;
+
+/**
+ * Fetch a set of contiguous bits from the compacted instruction.
+ *
+ * Bits indices range from 0..63.
+ */
+static inline unsigned
+brw_compact_inst_bits(brw_compact_inst *inst, unsigned high, unsigned low)
+{
+ const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
+
+ return (inst->data & mask) >> low;
+}
+
+/**
+ * Set bits in the compacted instruction.
+ *
+ * Bits indices range from 0..63.
+ */
+static inline void
+brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
+ uint64_t value)
+{
+ const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
+
+ /* Make sure the supplied value actually fits in the given bitfield. */
+ assert((value & (mask >> low)) == value);
+
+ inst->data = (inst->data & ~mask) | ((value << low) & mask);
+}
+
+#define F(name, high, low) \
+static inline void \
+brw_compact_inst_set_##name(struct brw_compact_instruction *insn, unsigned v) \
+{ \
+ brw_compact_inst *inst = (brw_compact_inst *)insn; \
+ brw_compact_inst_set_bits(inst, high, low, v); \
+} \
+\
+static inline unsigned \
+brw_compact_inst_##name(struct brw_compact_instruction *insn) \
+{ \
+ brw_compact_inst *inst = (brw_compact_inst *)insn; \
+ return brw_compact_inst_bits(inst, high, low); \
+}
+
+F(src1_reg_nr,63, 56)
+F(src0_reg_nr,55, 48)
+F(dst_reg_nr, 47, 40)
+F(src1_index, 39, 35)
+F(src0_index, 34, 30)
+F(cmpt_control, 29, 29) /* Same location as brw_inst */
+F(flag_subreg_nr, 28, 28) /* <= Gen6 only */
+F(cond_modifier, 27, 24) /* Same location as brw_inst */
+F(acc_wr_control, 23, 23)
+F(subreg_index, 22, 18)
+F(datatype_index, 17, 13)
+F(control_index, 12, 8)
+F(debug_control, 7, 7)
+F(opcode, 6, 0) /* Same location as brw_inst */
+
+/**
+ * Three-source instructions:
+ * @{
+ */
+F(3src_src2_reg_nr,63, 57)
+F(3src_src1_reg_nr,56, 50)
+F(3src_src0_reg_nr,49, 43)
+F(3src_src2_subreg_nr, 42, 40)
+F(3src_src1_subreg_nr, 39, 37)
+F(3src_src0_subreg_nr, 36, 34)
+F(3src_src2_rep_ctrl, 33, 33)
+F(3src_src1_rep_ctrl, 32, 32)
+F(3src_saturate, 31, 31)
+F(3src_debug_control, 30, 30)
+/* cmpt_control */
+F(3src_src0_rep_ctrl, 28, 28)
+/* Reserved */
+F(3src_dst_reg_nr, 18, 12)
+F(3src_source_index, 11, 10)
+F(3src_control_index, 9, 8)
+/* Reserved */
+/* opcode */
+/** @} */
+
+#undef F
+
#ifdef __cplusplus
}
#endif
--
1.8.3.2
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[Mesa-dev] [PATCH 18/19] i965: Convert brw_eu_compact.c to the new brw_compact_inst API.
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 82 --
1 file changed, 44 insertions(+), 38 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 3814657..769056d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -353,7 +353,7 @@ set_control_index(struct brw_context *brw,
for (int i = 0; i < 32; i++) {
if (control_index_table[i] == uncompacted) {
-dst->dw0.control_index = i;
+ brw_compact_inst_set_control_index(dst, i);
return true;
}
}
@@ -378,7 +378,7 @@ set_datatype_index(struct brw_context *brw,
for (int i = 0; i < 32; i++) {
if (datatype_table[i] == uncompacted) {
-dst->dw0.data_type_index = i;
+ brw_compact_inst_set_datatype_index(dst, i);
return true;
}
}
@@ -400,7 +400,7 @@ set_subreg_index(struct brw_context *brw,
for (int i = 0; i < 32; i++) {
if (subreg_table[i] == uncompacted) {
-dst->dw0.sub_reg_index = i;
+ brw_compact_inst_set_subreg_index(dst, i);
return true;
}
}
@@ -439,8 +439,7 @@ set_src0_index(struct brw_context *brw,
if (!get_src_index(uncompacted, &compacted))
return false;
- dst->dw0.src0_index = compacted & 0x3;
- dst->dw1.src0_index = compacted >> 2;
+ brw_compact_inst_set_src0_index(dst, compacted);
return true;
}
@@ -450,10 +449,11 @@ set_src1_index(struct brw_context *brw,
struct brw_compact_instruction *dst,
brw_inst *src, bool is_immediate)
{
+ uint16_t compacted;
+
if (is_immediate) {
- dst->dw1.src1_index = (brw_inst_imm_ud(brw, src) >> 8) & 0x1f;
+ compacted = (brw_inst_imm_ud(brw, src) >> 8) & 0x1f;
} else {
- uint16_t compacted;
uint16_t uncompacted = /* 12b */
(brw_inst_src1_vstride(brw, src) << 8) | /* 4b */
(brw_inst_src1_width(brw, src)<< 5) | /* 3b */
@@ -464,10 +464,10 @@ set_src1_index(struct brw_context *brw,
if (!get_src_index(uncompacted, &compacted))
return false;
-
- dst->dw1.src1_index = compacted;
}
+ brw_compact_inst_set_src1_index(dst, compacted);
+
return true;
}
@@ -522,29 +522,32 @@ brw_try_compact_instruction(struct brw_compile *p,
memset(&temp, 0, sizeof(temp));
- temp.dw0.opcode = brw_inst_opcode(brw, src);
- temp.dw0.debug_control = brw_inst_debug_control(brw, src);
+ brw_compact_inst_set_opcode(&temp, brw_inst_opcode(brw, src));
+ brw_compact_inst_set_debug_control(&temp, brw_inst_debug_control(brw, src));
if (!set_control_index(brw, &temp, src))
return false;
if (!set_datatype_index(brw, &temp, src))
return false;
if (!set_subreg_index(brw, &temp, src, is_immediate))
return false;
- temp.dw0.acc_wr_control = brw_inst_acc_wr_control(brw, src);
- temp.dw0.conditionalmod = brw_inst_cond_modifier(brw, src);
+ brw_compact_inst_set_acc_wr_control(&temp,
+ brw_inst_acc_wr_control(brw, src));
+ brw_compact_inst_set_cond_modifier(&temp, brw_inst_cond_modifier(brw, src));
if (brw->gen <= 6)
- temp.dw0.flag_subreg_nr = brw_inst_flag_subreg_nr(brw, src);
- temp.dw0.cmpt_ctrl = 1;
+ brw_compact_inst_set_flag_subreg_nr(&temp,
+ brw_inst_flag_subreg_nr(brw, src));
+ brw_compact_inst_set_cmpt_control(&temp, true);
if (!set_src0_index(brw, &temp, src))
return false;
if (!set_src1_index(brw, &temp, src, is_immediate))
return false;
- temp.dw1.dst_reg_nr = brw_inst_dst_da_reg_nr(brw, src);
- temp.dw1.src0_reg_nr = brw_inst_src0_da_reg_nr(brw, src);
+ brw_compact_inst_set_dst_reg_nr(&temp, brw_inst_dst_da_reg_nr(brw, src));
+ brw_compact_inst_set_src0_reg_nr(&temp, brw_inst_src0_da_reg_nr(brw, src));
if (is_immediate) {
- temp.dw1.src1_reg_nr = brw_inst_imm_ud(brw, src) & 0xff;
+ brw_compact_inst_set_src1_reg_nr(&temp, brw_inst_imm_ud(brw, src) &
0xff);
} else {
- temp.dw1.src1_reg_nr = brw_inst_src1_da_reg_nr(brw, src);
+ brw_compact_inst_set_src1_reg_nr(&temp,
+ brw_inst_src1_da_reg_nr(brw, src));
}
*dst = temp;
@@ -556,7 +559,8 @@ static void
set_uncompacted_control(struct brw_context *brw, brw_inst *dst,
struct brw_compact_instruction *src)
{
- uint32_t uncompacted = control_index_table[src->dw0.control_index];
+ uint32_t uncompacted =
+ control_index_table[brw_compact_inst_control_index(src)];
brw_inst_set_saturate(brw, dst, (uncompacted >> 16) & 0x1);
brw_inst_set_exec_size(brw, dst, (uncompacted >> 13) & 0x7);
@@ -579,7 +583,7 @@ static void
set_uncompacted_datatype(struct brw_context *brw, brw_inst *dst,
struct brw_compact_instruction *s
[Mesa-dev] [PATCH 07/19] i965: Convert fs_generator to the new brw_inst API.
From: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 5e1174c..de2f79b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -79,8 +79,8 @@ fs_generator::patch_discard_jumps_to_fb_writes()
* tests.
*/
struct brw_instruction *last_halt = gen6_HALT(p);
- last_halt->bits3.break_cont.uip = 2;
- last_halt->bits3.break_cont.jip = 2;
+ brw_inst_set_uip(brw, last_halt, 2);
+ brw_inst_set_jip(brw, last_halt, 2);
int ip = p->nr_insn;
@@ -88,9 +88,9 @@ fs_generator::patch_discard_jumps_to_fb_writes()
ip_record *patch_ip = (ip_record *)node;
struct brw_instruction *patch = &p->store[patch_ip->ip];
- assert(patch->header.opcode == BRW_OPCODE_HALT);
+ assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
/* HALT takes a half-instruction distance from the pre-incremented IP. */
- patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
+ brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * 2);
}
this->discard_halt_patches.make_empty();
@@ -217,10 +217,10 @@ fs_generator::generate_fb_write(fs_inst *inst)
v1_null_ud,
retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
brw_imm_ud(1<<26));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
- brw_last_inst->header.execution_size = BRW_EXECUTE_1;
+ brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
{
/* Don't send AA data */
fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
@@ -908,11 +908,11 @@ fs_generator::generate_varying_pull_constant_load(fs_inst
*inst,
gen6_resolve_implied_move(p, &header, inst->base_mrf);
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
- send->header.compression_control = BRW_COMPRESSION_NONE;
+ brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
brw_set_src0(p, send, header);
if (brw->gen < 6)
- send->header.destreg__conditionalmod = inst->base_mrf;
+ brw_inst_set_base_mrf(brw, send, inst->base_mrf);
/* Our surface is set up as floats, regardless of what actual data is
* stored in it.
@@ -1758,7 +1758,7 @@ fs_generator::generate_code(exec_list *instructions)
*/
assert(p->next_insn_offset == last_insn_offset + 16);
struct brw_instruction *last = &p->store[last_insn_offset / 16];
- last->header.destreg__conditionalmod = inst->conditional_mod;
+ brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
}
}
--
1.8.3.2
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[Mesa-dev] [PATCH 10/19] i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.
From: Kenneth Graunke
We're going to use fs_generator/vec4_generator for Gen8+ code soon,
thanks to the new brw_instruction API. When we do, we'll generally
want to take the Haswell paths on Gen8+ as well.
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index de2f79b..296ad49 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -421,7 +421,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg
dst, struct brw_reg src
case SHADER_OPCODE_TXD:
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients().
*/
-assert(brw->is_haswell);
+assert(brw->gen >= 8 || brw->is_haswell);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -578,7 +578,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg
dst, struct brw_reg src
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
-assert(brw->is_haswell); /* field only exists on Haswell */
+assert(brw->gen >= 8 || brw->is_haswell);
brw_ADD(p,
get_element_ud(header_reg, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
@@ -1384,7 +1384,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_MAD:
assert(brw->gen >= 6);
brw_set_default_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16 && !brw->is_haswell) {
+ if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_MAD(p, dst, src[0], src[1], src[2]);
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1399,7 +1399,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_LRP:
assert(brw->gen >= 6);
brw_set_default_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16 && !brw->is_haswell) {
+ if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_LRP(p, dst, src[0], src[1], src[2]);
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1495,7 +1495,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_BFE:
assert(brw->gen >= 7);
brw_set_default_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16 && !brw->is_haswell) {
+ if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFE(p, dst, src[0], src[1], src[2]);
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index aa041bc..f6eb3d4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -248,7 +248,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
case SHADER_OPCODE_TXD:
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients().
*/
-assert(brw->is_haswell);
+assert(brw->gen >= 8 || brw->is_haswell);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -355,7 +355,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
-assert(brw->is_haswell); /* field only exists on Haswell */
+assert(brw->gen >= 8 || brw->is_haswell);
brw_ADD(p,
get_element_ud(header, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
--
1.8.3.2
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[Mesa-dev] [PATCH 13/19] i965: Convert brw_disasm.c to the new brw_inst API.
---
src/mesa/drivers/dri/i965/brw_disasm.c | 649 -
1 file changed, 310 insertions(+), 339 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 11f53eb..0da05a2 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -29,6 +29,8 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_reg.h"
+#include "brw_inst.h"
const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
@@ -112,7 +114,7 @@ const char * const conditional_modifier[16] = {
[BRW_CONDITIONAL_U] = ".u",
};
-static const char * const negate[2] = {
+static const char * const m_negate[2] = {
[0] = "",
[1] = "-",
};
@@ -583,52 +585,53 @@ static int reg (FILE *file, unsigned _reg_file, unsigned
_reg_nr)
return err;
}
-static int dest (FILE *file, struct brw_instruction *inst)
+static int dest (FILE *file, struct brw_context *brw,
+ struct brw_instruction *inst)
{
interr = 0;
-if (inst->header.access_mode == BRW_ALIGN_1)
+if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1)
{
- if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
+ if (brw_inst_dst_address_mode(brw, inst) == BRW_ADDRESS_DIRECT)
{
- err |= reg (file, inst->bits1.da1.dest_reg_file,
inst->bits1.da1.dest_reg_nr);
+ err |= reg (file, brw_inst_dst_reg_file(brw, inst),
brw_inst_dst_da_reg_nr(brw, inst));
if (err == -1)
return 0;
- if (inst->bits1.da1.dest_subreg_nr)
- format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
-
reg_type_size[inst->bits1.da1.dest_reg_type]);
+ if (brw_inst_dst_da1_subreg_nr(brw, inst))
+ format (file, ".%d", brw_inst_dst_da1_subreg_nr(brw, inst) /
+reg_type_size[brw_inst_dst_reg_type(brw,
inst)]);
string (file, "<");
- err |= control (file, "horiz stride", horiz_stride,
inst->bits1.da1.dest_horiz_stride, NULL);
+ err |= control (file, "horiz stride", horiz_stride,
brw_inst_dst_hstride(brw, inst), NULL);
string (file, ">");
- err |= control (file, "dest reg encoding", reg_encoding,
inst->bits1.da1.dest_reg_type, NULL);
+ err |= control (file, "dest reg encoding", reg_encoding,
brw_inst_dst_reg_type(brw, inst), NULL);
}
else
{
string (file, "g[a0");
- if (inst->bits1.ia1.dest_subreg_nr)
- format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
-
reg_type_size[inst->bits1.ia1.dest_reg_type]);
- if (inst->bits1.ia1.dest_indirect_offset)
- format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
+ if (brw_inst_dst_ia_subreg_nr(brw, inst))
+ format (file, ".%d", brw_inst_dst_ia_subreg_nr(brw, inst) /
+
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
+ if (brw_inst_dst_ia1_addr_imm(brw, inst))
+ format (file, " %d", brw_inst_dst_ia1_addr_imm(brw, inst));
string (file, "]<");
- err |= control (file, "horiz stride", horiz_stride,
inst->bits1.ia1.dest_horiz_stride, NULL);
+ err |= control (file, "horiz stride", horiz_stride,
brw_inst_dst_hstride(brw, inst), NULL);
string (file, ">");
- err |= control (file, "dest reg encoding", reg_encoding,
inst->bits1.ia1.dest_reg_type, NULL);
+ err |= control (file, "dest reg encoding", reg_encoding,
brw_inst_dst_reg_type(brw, inst), NULL);
}
}
else
{
- if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
+ if (brw_inst_dst_address_mode(brw, inst) == BRW_ADDRESS_DIRECT)
{
- err |= reg (file, inst->bits1.da16.dest_reg_file,
inst->bits1.da16.dest_reg_nr);
+ err |= reg (file, brw_inst_dst_reg_file(brw, inst),
brw_inst_dst_da_reg_nr(brw, inst));
if (err == -1)
return 0;
- if (inst->bits1.da16.dest_subreg_nr)
- format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
-
reg_type_size[inst->bits1.da16.dest_reg_type]);
+ if (brw_inst_dst_da16_subreg_nr(brw, inst))
+ format (file, ".%d", brw_inst_dst_da16_subreg_nr(brw, inst) /
+reg_type_size[brw_inst_dst_reg_type(brw,
inst)]);
string (file, "<1>");
- err |= control (file, "writemask", writemask,
inst->bits1.da16.dest_writemask, NULL);
- err |= control (file, "dest reg encoding", reg_encoding,
inst->bits1.da16.dest_reg_type, NULL);
+ err |= control (file, "writemask", writemask,
brw_inst_da16_writemask(brw, inst), NULL);
[Mesa-dev] [PATCH 08/19] i965: Convert vec4_generator to the new brw_inst API.
From: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 119bcae..aa041bc 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -699,7 +699,7 @@ vec4_generator::generate_scratch_read(vec4_instruction
*inst,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (brw->gen < 6)
- send->header.destreg__conditionalmod = inst->base_mrf;
+ brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
brw_set_dp_read_message(p, send,
255, /* binding table index: stateless access */
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@@ -770,7 +770,7 @@ vec4_generator::generate_scratch_write(vec4_instruction
*inst,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (brw->gen < 6)
- send->header.destreg__conditionalmod = inst->base_mrf;
+ brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
brw_set_dp_write_message(p, send,
255, /* binding table index: stateless access */
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@@ -817,7 +817,7 @@
vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (brw->gen < 6)
- send->header.destreg__conditionalmod = inst->base_mrf;
+ brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
brw_set_dp_read_message(p, send,
surf_index,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@@ -1072,8 +1072,8 @@
vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
assert(brw->gen == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
- struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
- brw_inst->header.predicate_control = inst->predicate;
+ struct brw_instruction *if_inst = brw_IF(p, BRW_EXECUTE_8);
+ brw_inst_set_pred_control(brw, if_inst, inst->predicate);
}
break;
@@ -1268,11 +1268,11 @@ vec4_generator::generate_code(exec_list *instructions)
struct brw_instruction *last = &p->store[pre_emit_nr_insn];
if (inst->conditional_mod)
-last->header.destreg__conditionalmod = inst->conditional_mod;
+brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
if (inst->no_dd_clear)
-last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
+brw_inst_set_no_dd_clear(brw, last, true);
if (inst->no_dd_check)
-last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
+brw_inst_set_no_dd_check(brw, last, true);
}
}
--
1.8.3.2
___
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http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/19] i965: Convert brw_eu_compact.c to the new brw_inst API.
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 269 +
1 file changed, 161 insertions(+), 108 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 0ae3f2d..7e08d1d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -331,16 +331,25 @@ set_control_index(struct brw_context *brw,
struct brw_compact_instruction *dst,
struct brw_instruction *src)
{
- uint32_t *src_u32 = (uint32_t *)src;
- uint32_t uncompacted = 0;
-
- uncompacted |= ((src_u32[0] >> 8) & 0x) << 0;
- uncompacted |= ((src_u32[0] >> 31) & 0x1) << 16;
- /* On gen7, the flag register number gets integrated into the control
-* index.
+ uint32_t uncompacted = /* 17b/SNB; 19b/IVB+ */
+ (brw_inst_saturate(brw, src) << 16) | /* 1b */
+ (brw_inst_exec_size(brw, src) << 13) | /* 3b */
+ (brw_inst_pred_inv(brw, src) << 12) | /* 1b */
+ (brw_inst_pred_control(brw, src) << 8) | /* 4b */
+ (brw_inst_thread_control(brw, src) << 6) | /* 2b */
+ (brw_inst_qtr_control(brw, src)<< 4) | /* 2b */
+ (brw_inst_no_dd_check(brw, src)<< 3) | /* 1b */
+ (brw_inst_no_dd_clear(brw, src)<< 2) | /* 1b */
+ (brw_inst_mask_control(brw, src) << 1) | /* 1b */
+ (brw_inst_access_mode(brw, src)<< 0); /* 1b */
+
+ /* On gen7, the flag register and subregister numbers are integrated into
+* the control index.
*/
if (brw->gen >= 7)
- uncompacted |= ((src_u32[2] >> 25) & 0x3) << 17;
+ uncompacted |=
+ (brw_inst_flag_reg_nr(brw, src)<< 18) | /* 1b */
+ (brw_inst_flag_subreg_nr(brw, src) << 17); /* 1b */
for (int i = 0; i < 32; i++) {
if (control_index_table[i] == uncompacted) {
@@ -353,13 +362,19 @@ set_control_index(struct brw_context *brw,
}
static bool
-set_datatype_index(struct brw_compact_instruction *dst,
+set_datatype_index(struct brw_context *brw,
+ struct brw_compact_instruction *dst,
struct brw_instruction *src)
{
- uint32_t uncompacted = 0;
-
- uncompacted |= src->bits1.ud & 0x7fff;
- uncompacted |= (src->bits1.ud >> 29) << 15;
+ uint32_t uncompacted = /* 18b */
+ (brw_inst_dst_address_mode(brw, src) << 17) | /* 1b */
+ (brw_inst_dst_hstride(brw, src) << 15) | /* 2b */
+ (brw_inst_src1_reg_type(brw, src)<< 12) | /* 3b */
+ (brw_inst_src1_reg_file(brw, src)<< 10) | /* 2b */
+ (brw_inst_src0_reg_type(brw, src)<< 7) | /* 3b */
+ (brw_inst_src0_reg_file(brw, src)<< 5) | /* 2b */
+ (brw_inst_dst_reg_type(brw, src) << 2) | /* 3b */
+ (brw_inst_dst_reg_file(brw, src) << 0); /* 2b */
for (int i = 0; i < 32; i++) {
if (datatype_table[i] == uncompacted) {
@@ -372,17 +387,17 @@ set_datatype_index(struct brw_compact_instruction *dst,
}
static bool
-set_subreg_index(struct brw_compact_instruction *dst,
+set_subreg_index(struct brw_context *brw,
+ struct brw_compact_instruction *dst,
struct brw_instruction *src,
bool is_immediate)
{
- uint16_t uncompacted = 0;
-
- uncompacted |= src->bits1.da1.dest_subreg_nr << 0;
- uncompacted |= src->bits2.da1.src0_subreg_nr << 5;
+ uint16_t uncompacted =/* 15b */
+ (brw_inst_dst_da1_subreg_nr(brw, src) << 0) | /* 5b */
+ (brw_inst_src0_da1_subreg_nr(brw, src) << 5); /* 5b */
if (!is_immediate)
- uncompacted |= src->bits3.da1.src1_subreg_nr << 10;
+ uncompacted |= brw_inst_src1_da1_subreg_nr(brw, src) << 10; /* 5b */
for (int i = 0; i < 32; i++) {
if (subreg_table[i] == uncompacted) {
@@ -409,12 +424,18 @@ get_src_index(uint16_t uncompacted,
}
static bool
-set_src0_index(struct brw_compact_instruction *dst,
+set_src0_index(struct brw_context *brw,
+ struct brw_compact_instruction *dst,
struct brw_instruction *src)
{
- uint16_t compacted, uncompacted = 0;
-
- uncompacted |= (src->bits2.ud >> 13) & 0xfff;
+ uint16_t compacted;
+ uint16_t uncompacted = /* 12b */
+ (brw_inst_src0_vstride(brw, src) << 8) | /* 4b */
+ (brw_inst_src0_width(brw, src)<< 5) | /* 3b */
+ (brw_inst_src0_hstride(brw, src) << 3) | /* 2b */
+ (brw_inst_src0_address_mode(brw, src) << 2) | /* 1b */
+ (brw_inst_src0_negate(brw, src) << 1) | /* 1b */
+ (brw_inst_src0_abs(brw, src) << 0); /* 1b */
if (!get_src_index(uncompacted, &compacted))
return false;
@@ -426,15 +447,21 @@ set_src0_index(struct brw_compact_instruction *dst,
}
static bool
-set_src1_index(struct brw_compact_instruction *dst,
+set_src1_index(struct brw_context *brw,
+ struct brw_compact_
[Mesa-dev] [PATCH 19/19] i965: Replace struct brw_compact_instruction with brw_compact_inst.
---
src/mesa/drivers/dri/i965/brw_eu.c | 2 +-
src/mesa/drivers/dri/i965/brw_eu.h | 5 ++--
src/mesa/drivers/dri/i965/brw_eu_compact.c | 42 -
src/mesa/drivers/dri/i965/brw_inst.h| 6 ++---
src/mesa/drivers/dri/i965/brw_structs.h | 26 --
src/mesa/drivers/dri/i965/test_eu_compact.c | 4 +--
6 files changed, 24 insertions(+), 61 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 1a962c4..9a013c7 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -244,7 +244,7 @@ brw_disassemble(struct brw_context *brw,
fprintf(out, "0x%08x: ", offset);
if (compacted) {
-struct brw_compact_instruction *compacted = (void *)insn;
+brw_compact_inst *compacted = (void *)insn;
if (dump_hex) {
fprintf(out, "0x%08x 0x%08x ",
((uint32_t *)insn)[1],
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index eeb9223..7a6c339 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -413,9 +413,8 @@ void brw_init_compaction_tables(struct brw_context *brw);
void brw_compact_instructions(struct brw_compile *p, int start_offset,
int num_annotations, struct annotation
*annotation);
void brw_uncompact_instruction(struct brw_context *brw, brw_inst *dst,
- struct brw_compact_instruction *src);
-bool brw_try_compact_instruction(struct brw_compile *p,
- struct brw_compact_instruction *dst,
+ brw_compact_inst *src);
+bool brw_try_compact_instruction(struct brw_compile *p, brw_compact_inst *dst,
brw_inst *src);
void brw_debug_compact_uncompact(struct brw_context *brw, brw_inst *orig,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 769056d..709acb5 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -327,9 +327,7 @@ static const uint16_t *subreg_table;
static const uint16_t *src_index_table;
static bool
-set_control_index(struct brw_context *brw,
- struct brw_compact_instruction *dst,
- brw_inst *src)
+set_control_index(struct brw_context *brw, brw_compact_inst *dst, brw_inst
*src)
{
uint32_t uncompacted = /* 17b/SNB; 19b/IVB+ */
(brw_inst_saturate(brw, src) << 16) | /* 1b */
@@ -362,8 +360,7 @@ set_control_index(struct brw_context *brw,
}
static bool
-set_datatype_index(struct brw_context *brw,
- struct brw_compact_instruction *dst,
+set_datatype_index(struct brw_context *brw, brw_compact_inst *dst,
brw_inst *src)
{
uint32_t uncompacted = /* 18b */
@@ -387,9 +384,8 @@ set_datatype_index(struct brw_context *brw,
}
static bool
-set_subreg_index(struct brw_context *brw,
- struct brw_compact_instruction *dst,
- brw_inst *src, bool is_immediate)
+set_subreg_index(struct brw_context *brw, brw_compact_inst *dst, brw_inst *src,
+ bool is_immediate)
{
uint16_t uncompacted =/* 15b */
(brw_inst_dst_da1_subreg_nr(brw, src) << 0) | /* 5b */
@@ -423,9 +419,7 @@ get_src_index(uint16_t uncompacted,
}
static bool
-set_src0_index(struct brw_context *brw,
- struct brw_compact_instruction *dst,
- brw_inst *src)
+set_src0_index(struct brw_context *brw, brw_compact_inst *dst, brw_inst *src)
{
uint16_t compacted;
uint16_t uncompacted = /* 12b */
@@ -445,9 +439,8 @@ set_src0_index(struct brw_context *brw,
}
static bool
-set_src1_index(struct brw_context *brw,
- struct brw_compact_instruction *dst,
- brw_inst *src, bool is_immediate)
+set_src1_index(struct brw_context *brw, brw_compact_inst *dst, brw_inst *src,
+ bool is_immediate)
{
uint16_t compacted;
@@ -494,12 +487,11 @@ is_compactable_immediate(unsigned imm)
* brw_compact_instructions().
*/
bool
-brw_try_compact_instruction(struct brw_compile *p,
-struct brw_compact_instruction *dst,
+brw_try_compact_instruction(struct brw_compile *p, brw_compact_inst *dst,
brw_inst *src)
{
struct brw_context *brw = p->brw;
- struct brw_compact_instruction temp;
+ brw_compact_inst temp;
if (brw_inst_opcode(brw, src) == BRW_OPCODE_IF ||
brw_inst_opcode(brw, src) == BRW_OPCODE_ELSE ||
@@ -557,7 +549,7 @@ brw_try_compact_instruction(struct brw_compile *p,
static void
set_uncompacted_control(struct brw_context *brw, brw_inst *dst,
-struct brw_compact_instruction
[Mesa-dev] [PATCH 14/19] i965: Convert brw_gs_emit.c to the new brw_inst API.
---
src/mesa/drivers/dri/i965/brw_gs_emit.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c
b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index cb9dd7b..320d59c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -346,6 +346,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct
brw_ff_gs_prog_key *key,
unsigned num_verts, bool check_edge_flags)
{
struct brw_compile *p = &c->func;
+ struct brw_context *brw = p->brw;
struct brw_instruction *inst;
c->prog_data.svbi_postincrement_value = num_verts;
@@ -411,7 +412,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct
brw_ff_gs_prog_key *key,
inst = brw_MOV(p, destination_indices_uw,
brw_imm_v(key->pv_first ? 0x00010200/* (0, 2, 1) */
: 0x00020001)); /* (1, 0, 2) */
- inst->header.predicate_control = BRW_PREDICATE_NORMAL;
+ brw_inst_set_pred_control(brw, inst, BRW_PREDICATE_NORMAL);
}
brw_ADD(p, c->reg.destination_indices,
c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
@@ -501,7 +502,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct
brw_ff_gs_prog_key *key,
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
get_element_ud(c->reg.R0, 2),
brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_IF(p, BRW_EXECUTE_1);
}
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
@@ -517,7 +518,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct
brw_ff_gs_prog_key *key,
brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
get_element_ud(c->reg.R0, 2),
brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
- brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+ brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
}
brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
--
1.8.3.2
___
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[Mesa-dev] [PATCH 15/19] i965: Throw out guts of struct brw_instruction.
---
src/mesa/drivers/dri/i965/brw_structs.h | 630 +---
1 file changed, 1 insertion(+), 629 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri/i965/brw_structs.h
index 803dc6e..385bb3c 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -786,635 +786,7 @@ struct brw_urb_immediate {
struct brw_instruction
{
- struct
- {
- unsigned opcode:7;
- unsigned pad:1;
- unsigned access_mode:1;
- unsigned mask_control:1;
- unsigned dependency_control:2;
- unsigned compression_control:2; /* gen6: quarter control */
- unsigned thread_control:2;
- unsigned predicate_control:4;
- unsigned predicate_inverse:1;
- unsigned execution_size:3;
- /**
- * Conditional Modifier for most instructions. On Gen6+, this is also
- * used for the SEND instruction's Message Target/SFID.
- */
- unsigned destreg__conditionalmod:4;
- unsigned acc_wr_control:1;
- unsigned cmpt_control:1;
- unsigned debug_control:1;
- unsigned saturate:1;
- } header;
-
- union {
- struct
- {
-unsigned dest_reg_file:2;
-unsigned dest_reg_type:3;
-unsigned src0_reg_file:2;
-unsigned src0_reg_type:3;
-unsigned src1_reg_file:2;
-unsigned src1_reg_type:3;
- unsigned nibctrl:1; /* gen7+ */
-unsigned dest_subreg_nr:5;
-unsigned dest_reg_nr:8;
-unsigned dest_horiz_stride:2;
-unsigned dest_address_mode:1;
- } da1;
-
- struct
- {
-unsigned dest_reg_file:2;
-unsigned dest_reg_type:3;
-unsigned src0_reg_file:2;
-unsigned src0_reg_type:3;
-unsigned src1_reg_file:2;/* 0x0c00 */
-unsigned src1_reg_type:3;/* 0x7000 */
- unsigned nibctrl:1; /* gen7+ */
-int dest_indirect_offset:10; /* offset against the deref'd address
reg */
-unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
-unsigned dest_horiz_stride:2;
-unsigned dest_address_mode:1;
- } ia1;
-
- struct
- {
-unsigned dest_reg_file:2;
-unsigned dest_reg_type:3;
-unsigned src0_reg_file:2;
-unsigned src0_reg_type:3;
-unsigned src1_reg_file:2;
-unsigned src1_reg_type:3;
- unsigned nibctrl:1; /* gen7+ */
-unsigned dest_writemask:4;
-unsigned dest_subreg_nr:1;
-unsigned dest_reg_nr:8;
-unsigned dest_horiz_stride:2;
-unsigned dest_address_mode:1;
- } da16;
-
- struct
- {
-unsigned dest_reg_file:2;
-unsigned dest_reg_type:3;
-unsigned src0_reg_file:2;
-unsigned src0_reg_type:3;
- unsigned src1_reg_file:2;
- unsigned src1_reg_type:3;
- unsigned nibctrl:1; /* gen7+ */
-unsigned dest_writemask:4;
-int dest_indirect_offset:6;
-unsigned dest_subreg_nr:3;
-unsigned dest_horiz_stride:2;
-unsigned dest_address_mode:1;
- } ia16;
-
- struct {
-unsigned dest_reg_file:2;
-unsigned dest_reg_type:3;
-unsigned src0_reg_file:2;
-unsigned src0_reg_type:3;
-unsigned src1_reg_file:2;
-unsigned src1_reg_type:3;
-unsigned pad:1;
-
-int jump_count:16;
- } branch_gen6;
-
- struct {
- unsigned dest_reg_file:1; /* gen6, not gen7+ */
-unsigned flag_subreg_num:1;
- unsigned flag_reg_nr:1; /* gen7+ */
- unsigned pad0:1;
-unsigned src0_abs:1;
-unsigned src0_negate:1;
-unsigned src1_abs:1;
-unsigned src1_negate:1;
-unsigned src2_abs:1;
-unsigned src2_negate:1;
- unsigned src_type:2; /* gen7+ */
- unsigned dst_type:2; /* gen7+ */
- unsigned pad1:1;
- unsigned nibctrl:1; /* gen7+ */
- unsigned pad2:1;
-unsigned dest_writemask:4;
-unsigned dest_subreg_nr:3;
-unsigned dest_reg_nr:8;
- } da3src;
-
- uint32_t ud;
- } bits1;
-
-
- union {
- struct
- {
-unsigned src0_subreg_nr:5;
-unsigned src0_reg_nr:8;
-unsigned src0_abs:1;
-unsigned src0_negate:1;
-unsigned src0_address_mode:1;
-unsigned src0_horiz_stride:2;
-unsigned src0_width:3;
-unsigned src0_vert_stride:4;
-unsigned flag_subreg_nr:1;
- unsigned flag_reg_nr:1; /* gen7+ */
-unsigned pad:5;
- } da1;
-
- struct
- {
-int src0_indirect_offset:10;
-unsigned src0_subreg_nr:3;
-unsigned src0_abs:1;
-unsigned src0_negate:1;
-unsigned src0_address_mode:1;
-unsigned src0_horiz_stride:2;
-unsigned src0_width:3;
-unsigned src0_vert_stride:4;
-unsigned flag_subreg_nr:1;
- unsigned flag_reg_nr:1; /* gen7+ */
-uns
[Mesa-dev] [PATCH 12/19] i965: Pass brw rather than gen to brw_disassemble_inst().
---
src/mesa/drivers/dri/i965/brw_context.h | 4 +--
src/mesa/drivers/dri/i965/brw_disasm.c | 54 ++---
src/mesa/drivers/dri/i965/brw_eu.c | 2 +-
src/mesa/drivers/dri/i965/brw_eu_compact.c | 4 +--
src/mesa/drivers/dri/i965/test_eu_compact.c | 2 +-
5 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 283c576..5e38b6a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1573,8 +1573,8 @@ void brw_fs_alloc_reg_sets(struct intel_screen *screen);
void brw_vec4_alloc_reg_set(struct intel_screen *screen);
/* brw_disasm.c */
-int brw_disassemble_inst(FILE *file, struct brw_instruction *inst,
- int gen, bool is_compacted);
+int brw_disassemble_inst(FILE *file, struct brw_context *brw,
+ struct brw_instruction *inst, bool is_compacted);
/* brw_vs.c */
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 67b1c8e..11f53eb 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -1118,8 +1118,8 @@ static int qtr_ctrl(FILE *file, struct brw_instruction
*inst)
}
int
-brw_disassemble_inst(FILE *file,
- struct brw_instruction *inst, int gen, bool is_compacted)
+brw_disassemble_inst(FILE *file, struct brw_context *brw,
+ struct brw_instruction *inst, bool is_compacted)
{
interr = 0;
int space = 0;
@@ -1127,7 +1127,7 @@ brw_disassemble_inst(FILE *file,
if (inst->header.predicate_control) {
string (file, "(");
err |= control (file, "predicate inverse", pred_inv,
inst->header.predicate_inverse, NULL);
- format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
+ format (file, "f%d", brw->gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
if (inst->bits2.da1.flag_subreg_nr)
format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
if (inst->header.access_mode == BRW_ALIGN_1)
@@ -1158,10 +1158,10 @@ brw_disassemble_inst(FILE *file,
* control flow doesn't update flags.
*/
if (inst->header.destreg__conditionalmod &&
-(gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL &&
+(brw->gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL &&
inst->header.opcode != BRW_OPCODE_IF &&
inst->header.opcode != BRW_OPCODE_WHILE))) {
- format (file, ".f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
+ format (file, ".f%d", brw->gen >= 7 ? inst->bits2.da1.flag_reg_nr :
0);
if (inst->bits2.da1.flag_subreg_nr)
format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
}
@@ -1173,7 +1173,7 @@ brw_disassemble_inst(FILE *file,
string (file, ")");
}
-if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6)
+if (inst->header.opcode == BRW_OPCODE_SEND && brw->gen < 6)
format (file, " %d", inst->header.destreg__conditionalmod);
if (opcode[inst->header.opcode].nsrc == 3) {
@@ -1192,19 +1192,19 @@ brw_disassemble_inst(FILE *file,
if (opcode[inst->header.opcode].ndst > 0) {
pad (file, 16);
err |= dest (file, inst);
- } else if (gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE ||
+ } else if (brw->gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE ||
inst->header.opcode == BRW_OPCODE_ENDIF ||
inst->header.opcode == BRW_OPCODE_WHILE)) {
format (file, " %d", inst->bits3.break_cont.jip);
- } else if (gen == 6 && (inst->header.opcode == BRW_OPCODE_IF ||
+ } else if (brw->gen == 6 && (inst->header.opcode == BRW_OPCODE_IF ||
inst->header.opcode == BRW_OPCODE_ELSE ||
inst->header.opcode == BRW_OPCODE_ENDIF ||
inst->header.opcode == BRW_OPCODE_WHILE)) {
format (file, " %d", inst->bits1.branch_gen6.jump_count);
- } else if ((gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
+ } else if ((brw->gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
inst->header.opcode == BRW_OPCODE_CONTINUE ||
inst->header.opcode == BRW_OPCODE_HALT)) ||
- (gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) {
+ (brw->gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) {
format (file, " %d %d", inst->bits3.break_cont.uip,
inst->bits3.break_cont.jip);
} else if (inst->header.opcode == BRW_OPCODE_JMPI) {
format (file, " %d", inst->bits3.d);
@@ -1224,9 +1224,9 @@ brw_disassemble_inst(FILE *file,
inst->he
