[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #7 from charmai...@vmware.com ---

Hi Gert,

The original patch was indeed accessing the dangling pointers.
I'll have a patch tomorrow to fix the problem.
Thanks for looking into it.

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Re: [Mesa-dev] [EGL android: accquire fence implementation] i965: Queue the buffer with a sync fence for Android OS (v3.1)

[Tomasz Figa]

Hi Zhongmin,

Thanks for the patch. Please see my comments inline.

On Wed, Jul 19, 2017 at 12:22 PM, Zhongmin Wu  wrote:
> Before we queued the buffer with a invalid fence (-1), it will
> make some benchmarks failed to test such as flatland.
>
> Now we get the out fence during the flushing buffer and then pass
> it to SurfaceFlinger in eglSwapbuffer function.
>
> v2: a) Also implement the fence in cancelBuffer.
> b) The last sync fence is stored in drawable object
>rather than brw context.
> c) format clear.
>
> v3: a) Save the last fence fd in DRI Context object.
> b) Return the last fence if the batch buffer is empty and
>nothing to be flushed when _intel_batchbuffer_flush_fence
> c) Add the new interface in vbtl to set the retrieve fence
>in the egl surface. This is just for cancelBuffer.
> d) For queueBuffer, the fence is get with DRI fence interface.
>For cancelBuffer, the fence is get before the context is
>reset, and the fence is then  moved to its surface.
> v3.1 a) close fd in the new vbtl interface on none Android platform
>
> Change-Id: Ic0773c19788d612a98d1402f5b5619dab64c1bc2
> Tracked-On: https://jira01.devtools.intel.com/browse/OAM-43936
> Reported-On: https://bugs.freedesktop.org/show_bug.cgi?id=101655
> Signed-off-by: Zhongmin Wu 
> Reported-by: Li, Guangli 
> Tested-by: Marathe, Yogesh 
> ---
>  src/egl/drivers/dri2/egl_dri2.c   |   17 +-
>  src/egl/drivers/dri2/egl_dri2.h   |3 +++
>  src/egl/drivers/dri2/platform_android.c   |   30 
> ++---
>  src/egl/drivers/dri2/platform_drm.c   |1 +
>  src/egl/drivers/dri2/platform_surfaceless.c   |1 +
>  src/egl/drivers/dri2/platform_wayland.c   |2 ++
>  src/egl/drivers/dri2/platform_x11.c   |2 ++
>  src/egl/drivers/dri2/platform_x11_dri3.c  |1 +
>  src/mesa/drivers/dri/common/dri_util.c|3 +++
>  src/mesa/drivers/dri/common/dri_util.h|2 ++
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c |   25 ++---
>  11 files changed, 80 insertions(+), 7 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index 020a0bc..19d346d 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -1351,9 +1351,17 @@ dri2_make_current(_EGLDriver *drv, _EGLDisplay *disp, 
> _EGLSurface *dsurf,
> ddraw = (dsurf) ? dri2_dpy->vtbl->get_dri_drawable(dsurf) : NULL;
> rdraw = (rsurf) ? dri2_dpy->vtbl->get_dri_drawable(rsurf) : NULL;
> cctx = (dri2_ctx) ? dri2_ctx->dri_context : NULL;
> -
> +   int fence_fd = -1;
> if (old_ctx) {
>__DRIcontext *old_cctx = dri2_egl_context(old_ctx)->dri_context;
> +  if (old_dsurf) {
> + void * fence = dri2_dpy->fence->create_fence_fd(old_cctx, -1);
> + if (fence) {
> +fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen, 
> fence);
> +dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
> + }
> + dri2_dpy->vtbl->set_retrieve_fence(old_dsurf, fence_fd);

I think we don't need this callback. We can just set the fence in
old_dsurf directly, i.e.

dri2_surf_set_release_fence(surf, fence_fd)
{
   if (surf->fence_fd >= 0)
  close(surf->fence_fd);
   surf->fence_fd = fence_fd;
}

// ...

dri2_make_current()
{
// ...
  int fence_fd = -1;
  if (old_dsurf) {
 void * fence = dri2_dpy->fence->create_fence_fd(old_cctx, -1);
 if (fence) {
fence_fd =
dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen, fence);
dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
 }
 dri2_surf_set_release_fence(old_dsurf, fence_fd);
  }
// ...
}

Then we can just call dri2_surf_set_release_fence(surf, -1) in
dri2_destroy_surface() after the platform callback returns. The
platform callback must set surf->fence_fd to -1 if ownership of the FD
was given to the platform window system.

> +  }
>dri2_dpy->core->unbindContext(old_cctx);
> }
>
> @@ -1403,6 +1411,13 @@ dri2_surface_get_dri_drawable(_EGLSurface *surf)
> return dri2_surf->dri_drawable;
>  }
>
> +void
> +dri2_set_retrieve_fence(_EGLSurface *surf, int fd)
> +{
> +   close(fd);
> +   return;
> +}
> +
>  /*
>   * Called from eglGetProcAddress() via drv->API.GetProcAddress().
>   */
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index bbba7c0..b097345 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -150,6 +150,8 @@ struct dri2_egl_display_vtbl {
>   EGLuint64KHR *sbc);
>
> __DRIdrawable *(*get_dri_drawable)(_EGLSurface *surf);
> +
> +   void (*set_retrieve_fence)(_EGLSurface *surf, int fd);
>  };
>
>  struct dri2_egl_display
> @@ -314,6 

[Mesa-dev] [EGL android: accquire fence implementation] i965: Queue the buffer with a sync fence for Android OS (v3.1)

[Zhongmin Wu]

Before we queued the buffer with a invalid fence (-1), it will
make some benchmarks failed to test such as flatland.

Now we get the out fence during the flushing buffer and then pass
it to SurfaceFlinger in eglSwapbuffer function.

v2: a) Also implement the fence in cancelBuffer.
b) The last sync fence is stored in drawable object
   rather than brw context.
c) format clear.

v3: a) Save the last fence fd in DRI Context object.
b) Return the last fence if the batch buffer is empty and
   nothing to be flushed when _intel_batchbuffer_flush_fence
c) Add the new interface in vbtl to set the retrieve fence
   in the egl surface. This is just for cancelBuffer.
d) For queueBuffer, the fence is get with DRI fence interface.
   For cancelBuffer, the fence is get before the context is
   reset, and the fence is then  moved to its surface.
v3.1 a) close fd in the new vbtl interface on none Android platform

Change-Id: Ic0773c19788d612a98d1402f5b5619dab64c1bc2
Tracked-On: https://jira01.devtools.intel.com/browse/OAM-43936
Reported-On: https://bugs.freedesktop.org/show_bug.cgi?id=101655
Signed-off-by: Zhongmin Wu 
Reported-by: Li, Guangli 
Tested-by: Marathe, Yogesh 
---
 src/egl/drivers/dri2/egl_dri2.c   |   17 +-
 src/egl/drivers/dri2/egl_dri2.h   |3 +++
 src/egl/drivers/dri2/platform_android.c   |   30 ++---
 src/egl/drivers/dri2/platform_drm.c   |1 +
 src/egl/drivers/dri2/platform_surfaceless.c   |1 +
 src/egl/drivers/dri2/platform_wayland.c   |2 ++
 src/egl/drivers/dri2/platform_x11.c   |2 ++
 src/egl/drivers/dri2/platform_x11_dri3.c  |1 +
 src/mesa/drivers/dri/common/dri_util.c|3 +++
 src/mesa/drivers/dri/common/dri_util.h|2 ++
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |   25 ++---
 11 files changed, 80 insertions(+), 7 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 020a0bc..19d346d 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -1351,9 +1351,17 @@ dri2_make_current(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *dsurf,
ddraw = (dsurf) ? dri2_dpy->vtbl->get_dri_drawable(dsurf) : NULL;
rdraw = (rsurf) ? dri2_dpy->vtbl->get_dri_drawable(rsurf) : NULL;
cctx = (dri2_ctx) ? dri2_ctx->dri_context : NULL;
-
+   int fence_fd = -1;
if (old_ctx) {
   __DRIcontext *old_cctx = dri2_egl_context(old_ctx)->dri_context;
+  if (old_dsurf) {
+ void * fence = dri2_dpy->fence->create_fence_fd(old_cctx, -1);
+ if (fence) {
+fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen, 
fence);
+dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
+ }
+ dri2_dpy->vtbl->set_retrieve_fence(old_dsurf, fence_fd);
+  }
   dri2_dpy->core->unbindContext(old_cctx);
}
 
@@ -1403,6 +1411,13 @@ dri2_surface_get_dri_drawable(_EGLSurface *surf)
return dri2_surf->dri_drawable;
 }
 
+void
+dri2_set_retrieve_fence(_EGLSurface *surf, int fd)
+{
+   close(fd);
+   return;
+}
+
 /*
  * Called from eglGetProcAddress() via drv->API.GetProcAddress().
  */
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index bbba7c0..b097345 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -150,6 +150,8 @@ struct dri2_egl_display_vtbl {
  EGLuint64KHR *sbc);
 
__DRIdrawable *(*get_dri_drawable)(_EGLSurface *surf);
+
+   void (*set_retrieve_fence)(_EGLSurface *surf, int fd);
 };
 
 struct dri2_egl_display
@@ -314,6 +316,7 @@ struct dri2_egl_surface
   struct ANativeWindowBuffer *buffer;
   int age;
} color_buffers[3], *back;
+   int retrieve_fd;
 #endif
 
 #if defined(HAVE_SURFACELESS_PLATFORM)
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index cc2e4a6..b8d53b8 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -306,9 +306,16 @@ droid_window_enqueue_buffer(_EGLDisplay *disp, struct 
dri2_egl_surface *dri2_sur
 *is responsible for closing it.
 */
int fence_fd = -1;
+   _EGLContext *ctx = _eglGetCurrentContext();
+   struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx);
+   void * fence = dri2_dpy->fence->create_fence_fd(dri2_ctx->dri_context, -1);
+   if (fence) {
+  fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen,
+   fence);
+  dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
+   }
dri2_surf->window->queueBuffer(dri2_surf->window, dri2_surf->buffer,
   fence_fd);
-
dri2_surf->buffer->common.decRef(_surf->buffer->common);
dri2_surf->buffer = NULL;

[Mesa-dev] [EGL android: accquire fence implementation] i965: Queue the buffer with a sync fence for Android OS (v3)

[Zhongmin Wu]

Before we queued the buffer with a invalid fence (-1), it will
make some benchmarks failed to test such as flatland.

Now we get the out fence during the flushing buffer and then pass
it to SurfaceFlinger in eglSwapbuffer function.

v2: a) Also implement the fence in cancelBuffer.
b) The last sync fence is stored in drawable object
   rather than brw context.
c) format clear.

v3: a) Save the last fence fd in DRI Context object.
b) Return the last fence if the batch buffer is empty and
   nothing to be flushed when _intel_batchbuffer_flush_fence
c) Add the new interface in vbtl to set the retrieve fence
   in the egl surface. This is just for cancelBuffer.
d) For queueBuffer, the fence is get with DRI fence interface.
   For cancelBuffer, the fence is get before the context is
   reset, and the fence is then  moved to its surface.

Change-Id: Ic0773c19788d612a98d1402f5b5619dab64c1bc2
Tracked-On: https://jira01.devtools.intel.com/browse/OAM-43936
Reported-On: https://bugs.freedesktop.org/show_bug.cgi?id=101655
Signed-off-by: Zhongmin Wu 
Reported-by: Li, Guangli 
Tested-by: Marathe, Yogesh 
---
 src/egl/drivers/dri2/egl_dri2.c   |   16 -
 src/egl/drivers/dri2/egl_dri2.h   |3 +++
 src/egl/drivers/dri2/platform_android.c   |   30 ++---
 src/egl/drivers/dri2/platform_drm.c   |1 +
 src/egl/drivers/dri2/platform_surfaceless.c   |1 +
 src/egl/drivers/dri2/platform_wayland.c   |2 ++
 src/egl/drivers/dri2/platform_x11.c   |2 ++
 src/egl/drivers/dri2/platform_x11_dri3.c  |1 +
 src/mesa/drivers/dri/common/dri_util.c|3 +++
 src/mesa/drivers/dri/common/dri_util.h|2 ++
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |   25 ++---
 11 files changed, 79 insertions(+), 7 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 020a0bc..4c96c08 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -1351,9 +1351,17 @@ dri2_make_current(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *dsurf,
ddraw = (dsurf) ? dri2_dpy->vtbl->get_dri_drawable(dsurf) : NULL;
rdraw = (rsurf) ? dri2_dpy->vtbl->get_dri_drawable(rsurf) : NULL;
cctx = (dri2_ctx) ? dri2_ctx->dri_context : NULL;
-
+   int fence_fd = -1;
if (old_ctx) {
   __DRIcontext *old_cctx = dri2_egl_context(old_ctx)->dri_context;
+  if (old_dsurf) {
+ void * fence = dri2_dpy->fence->create_fence_fd(old_cctx, -1);
+ if (fence) {
+fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen, 
fence);
+dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
+ }
+ dri2_dpy->vtbl->set_retrieve_fence(old_dsurf, fence_fd);
+  }
   dri2_dpy->core->unbindContext(old_cctx);
}
 
@@ -1403,6 +1411,12 @@ dri2_surface_get_dri_drawable(_EGLSurface *surf)
return dri2_surf->dri_drawable;
 }
 
+void
+dri2_set_retrieve_fence(_EGLSurface *surf, int fd)
+{
+   return;
+}
+
 /*
  * Called from eglGetProcAddress() via drv->API.GetProcAddress().
  */
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index bbba7c0..b097345 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -150,6 +150,8 @@ struct dri2_egl_display_vtbl {
  EGLuint64KHR *sbc);
 
__DRIdrawable *(*get_dri_drawable)(_EGLSurface *surf);
+
+   void (*set_retrieve_fence)(_EGLSurface *surf, int fd);
 };
 
 struct dri2_egl_display
@@ -314,6 +316,7 @@ struct dri2_egl_surface
   struct ANativeWindowBuffer *buffer;
   int age;
} color_buffers[3], *back;
+   int retrieve_fd;
 #endif
 
 #if defined(HAVE_SURFACELESS_PLATFORM)
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index cc2e4a6..b8d53b8 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -306,9 +306,16 @@ droid_window_enqueue_buffer(_EGLDisplay *disp, struct 
dri2_egl_surface *dri2_sur
 *is responsible for closing it.
 */
int fence_fd = -1;
+   _EGLContext *ctx = _eglGetCurrentContext();
+   struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx);
+   void * fence = dri2_dpy->fence->create_fence_fd(dri2_ctx->dri_context, -1);
+   if (fence) {
+  fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen,
+   fence);
+  dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
+   }
dri2_surf->window->queueBuffer(dri2_surf->window, dri2_surf->buffer,
   fence_fd);
-
dri2_surf->buffer->common.decRef(_surf->buffer->common);
dri2_surf->buffer = NULL;
dri2_surf->back = NULL;
@@ -327,8 +334,10 @@ static void
 droid_window_cancel_buffer(struct 

[Mesa-dev] [PATCH 2/2] radv: port to new libdrm API.

[Dave Airlie]

From: Dave Airlie 

This bumps the libdrm requirement for amdgpu to the 2.4.82
(not yet released but soon).

Signed-off-by: Dave Airlie 
---
 configure.ac  |   2 +-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 121 --
 2 files changed, 93 insertions(+), 30 deletions(-)

diff --git a/configure.ac b/configure.ac
index c5803e0..0204ad5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -74,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
 # in the first entry.
 LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.71
-LIBDRM_AMDGPU_REQUIRED=2.4.81
+LIBDRM_AMDGPU_REQUIRED=2.4.82
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 91212d2..93243df 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -96,10 +96,6 @@ static int ring_to_hw_ip(enum ring_type ring)
}
 }
 
-static void radv_amdgpu_wait_sems(struct radv_amdgpu_ctx *ctx,
- uint32_t ip_type,
- uint32_t ring,
- struct radv_amdgpu_sem_info *sem_info);
 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
   uint32_t ip_type,
   uint32_t ring,
@@ -950,8 +946,6 @@ static int radv_amdgpu_winsys_cs_submit(struct 
radeon_winsys_ctx *_ctx,
sem_info.signal_sems = signal_sem;
sem_info.signal_sem_count = signal_sem_count;
 
-   radv_amdgpu_wait_sems(ctx, cs->hw_ip, queue_idx, _info);
-
if (!cs->ws->use_ib_bos) {
ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, 
_info, cs_array,
   cs_count, 
initial_preamble_cs, continue_preamble_cs, _fence);
@@ -1062,31 +1056,17 @@ static bool radv_amdgpu_ctx_wait_idle(struct 
radeon_winsys_ctx *rwctx,
 
 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys 
*_ws)
 {
-   int ret;
-   amdgpu_semaphore_handle sem;
-
-   ret = amdgpu_cs_create_semaphore();
-   if (ret)
+   struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
+   if (!sem)
return NULL;
+
return (struct radeon_winsys_sem *)sem;
 }
 
 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
 {
-   amdgpu_semaphore_handle sem = (amdgpu_semaphore_handle)_sem;
-   amdgpu_cs_destroy_semaphore(sem);
-}
-
-static void radv_amdgpu_wait_sems(struct radv_amdgpu_ctx *ctx,
- uint32_t ip_type,
- uint32_t ring,
- struct radv_amdgpu_sem_info *sem_info)
-{
-   for (unsigned i = 0; i < sem_info->wait_sem_count; i++) {
-   amdgpu_semaphore_handle sem = 
(amdgpu_semaphore_handle)sem_info->wait_sems[i];
-   amdgpu_cs_wait_semaphore(ctx->ctx, ip_type, 0, ring,
-sem);
-   }
+   struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
+   FREE(sem);
 }
 
 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
@@ -1095,9 +1075,12 @@ static int radv_amdgpu_signal_sems(struct 
radv_amdgpu_ctx *ctx,
   struct radv_amdgpu_sem_info *sem_info)
 {
for (unsigned i = 0; i < sem_info->signal_sem_count; i++) {
-   amdgpu_semaphore_handle sem = 
(amdgpu_semaphore_handle)sem_info->signal_sems[i];
-   amdgpu_cs_signal_semaphore(ctx->ctx, ip_type, 0, ring,
-  sem);
+   struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence 
*)sem_info->signal_sems[i];
+
+   if (sem->context)
+   return -EINVAL;
+
+   *sem = ctx->last_submission[ip_type][ring].fence;
}
return 0;
 }
@@ -1106,7 +1089,87 @@ static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx 
*ctx,
 struct amdgpu_cs_request *request,
 struct radv_amdgpu_sem_info *sem_info)
 {
-   return amdgpu_cs_submit(ctx->ctx, 0, request, 1);
+   int r;
+   int num_chunks;
+   int size;
+   bool user_fence;
+   struct drm_amdgpu_cs_chunk *chunks;
+   struct drm_amdgpu_cs_chunk_data *chunk_data;
+   struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
+   int i;
+   struct amdgpu_cs_fence *sem;
+   user_fence = (request->fence_info.handle != NULL);
+   size = request->number_of_ibs + (user_fence ? 2 : 1) + 1;
+
+   chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
+
+   size = request->number_of_ibs + (user_fence ? 1 : 0);
+
+   chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
+
+   

[Mesa-dev] [PATCH 1/2] radv: introduce some wrapper in cs code to make porting off libdrm_amdgpu easier.

[Dave Airlie]

From: Dave Airlie 

This just introduces a central semaphore info struct, and passes it around,
and introduces some wrappers that will make porting off libdrm_amdgpu easier.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 88 +--
 1 file changed, 70 insertions(+), 18 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index ffc7566..91212d2 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -75,6 +75,13 @@ radv_amdgpu_cs(struct radeon_winsys_cs *base)
return (struct radv_amdgpu_cs*)base;
 }
 
+struct radv_amdgpu_sem_info {
+   int wait_sem_count;
+   struct radeon_winsys_sem **wait_sems;
+   int signal_sem_count;
+   struct radeon_winsys_sem **signal_sems;
+};
+
 static int ring_to_hw_ip(enum ring_type ring)
 {
switch (ring) {
@@ -89,6 +96,18 @@ static int ring_to_hw_ip(enum ring_type ring)
}
 }
 
+static void radv_amdgpu_wait_sems(struct radv_amdgpu_ctx *ctx,
+ uint32_t ip_type,
+ uint32_t ring,
+ struct radv_amdgpu_sem_info *sem_info);
+static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
+  uint32_t ip_type,
+  uint32_t ring,
+  struct radv_amdgpu_sem_info *sem_info);
+static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
+struct amdgpu_cs_request *request,
+struct radv_amdgpu_sem_info *sem_info);
+
 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
 struct radv_amdgpu_fence *fence,
 struct amdgpu_cs_request *req)
@@ -647,6 +666,7 @@ static void radv_assign_last_submit(struct radv_amdgpu_ctx 
*ctx,
 
 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
int queue_idx,
+   struct radv_amdgpu_sem_info 
*sem_info,
struct radeon_winsys_cs 
**cs_array,
unsigned cs_count,
struct radeon_winsys_cs 
*initial_preamble_cs,
@@ -703,7 +723,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct 
radeon_winsys_ctx *_ctx,
ibs[0] = ((struct radv_amdgpu_cs*)initial_preamble_cs)->ib;
}
 
-   r = amdgpu_cs_submit(ctx->ctx, 0, , 1);
+   r = radv_amdgpu_cs_submit(ctx, , sem_info);
if (r) {
if (r == -ENOMEM)
fprintf(stderr, "amdgpu: Not enough memory for command 
submission.\n");
@@ -724,6 +744,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct 
radeon_winsys_ctx *_ctx,
 
 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx 
*_ctx,
 int queue_idx,
+struct radv_amdgpu_sem_info 
*sem_info,
 struct radeon_winsys_cs 
**cs_array,
 unsigned cs_count,
 struct radeon_winsys_cs 
*initial_preamble_cs,
@@ -775,7 +796,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct 
radeon_winsys_ctx *_ctx,
}
}
 
-   r = amdgpu_cs_submit(ctx->ctx, 0, , 1);
+   r = radv_amdgpu_cs_submit(ctx, , sem_info);
if (r) {
if (r == -ENOMEM)
fprintf(stderr, "amdgpu: Not enough memory for 
command submission.\n");
@@ -801,6 +822,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct 
radeon_winsys_ctx *_ctx,
 
 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
   int queue_idx,
+  struct radv_amdgpu_sem_info 
*sem_info,
   struct radeon_winsys_cs 
**cs_array,
   unsigned cs_count,
   struct radeon_winsys_cs 
*initial_preamble_cs,
@@ -880,7 +902,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
request.ibs = 
request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, 
queue_idx);
 
-   r = amdgpu_cs_submit(ctx->ctx, 0, , 1);
+   r = radv_amdgpu_cs_submit(ctx, , sem_info);
if (r) {
if (r == -ENOMEM)

[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #6 from Gert Wollny  ---
The patch didn't help on my side. 

I've added some debug output to see what is going on. In summary, stfb->iface
in st_manager.c  is not properly updated and points  to a destroyed buffer,
that is accessed in st_framebuffers_purge, see below:

valgrind  glretrace Downloads/example.trace 
==3152== Memcheck, a memory error detector
==3152== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==3152== Using Valgrind-3.13.0 and LibVEX; rerun with -h for copyright info
==3152== Command: glretrace Downloads/example.trace
==3152== 
dri_get_drawable: 0x161220b0 refcount: 1
dri_create_buffer 0x161220b0: 0x16122130
driCreateNewDrawable: 0x161220b0 refcount: 1 buffer: 0x16122130
driFetchDrawable (create): 0x16121fa0 refcount: 1
driFetchDrawable: 0x16121fa0 refcount: 2
dri_get_drawable: 0x161220b0 refcount: 2
Bind context 0x16036270 pdp 0x161220b0 prp 0x161220b0 
stdraw= 0x16122520
stread= 0x16122520
st= 0x160ecc10
stfb->iface= 0x16122130
dri_put_drawable: 0x161220b0 refcount: 1
Unbind context 0x16036270 pdp 0x161220b0 prp 0x161220b0 
dri_get_drawable: 0x162791f0 refcount: 1

dri_create_buffer 0x162791f0: 0x16279270 < create new buffer (2) 

driCreateNewDrawable: 0x162791f0 refcount: 1 buffer: 0x16279270
driFetchDrawable (create): 0x162790e0 refcount: 1
driFetchDrawable: 0x162790e0 refcount: 2
dri_get_drawable: 0x162791f0 refcount: 2
Bind context 0x16196340 pdp 0x162791f0 prp 0x162791f0 
stdraw= 0x16279550
stread= 0x16279550
st= 0x16246250

in st_framebuffers_purge; 
stfb->iface= 0x16279270 <= first use 


dri_put_drawable: 0x162791f0 refcount: 1
Unbind context 0x16196340 pdp 0x162791f0 prp 0x162791f0 
dri_get_drawable: 0x1628b1c0 refcount: 1

dri_create_buffer 0x1628b1c0: 0x1628b240   < create new buffer (3)

driCreateNewDrawable: 0x1628b1c0 refcount: 1 buffer: 0x1628b240
driFetchDrawable: 0x1628b0b0 refcount: 1
driFetchDrawable: 0x1628b0b0 refcount: 2
driReleaseDrawables; Drawable: 0x162790e0 refcount: 2
driReleaseDrawables; Readable: 0x162790e0 refcount: 1
dri2DestroyDrawable 0x162791f0
driDestroyDrawable: 0x162791f0 refcount: 1
dri_put_drawable: 0x162791f0 refcount: 0
   --- Destroy

dri_destroy_buffer 0x162791f0: 0x16279270  <== buffer (2) destroyed 


dri_get_drawable: 0x1628b1c0 refcount: 2
Bind context 0x16196340 pdp 0x1628b1c0 prp 0x1628b1c0 
stdraw= 0x1628d770
stread= 0x1628d770
st= 0x16246250

stfb->iface= 0x16279270 <== still pointing to the destroyed buffer 
should have been updated to (3) 0x1628b240

==3152== Invalid read of size 4
==3152==at 0x9CC5D04: st_framebuffers_purge (st_manager.c:510)
==3152==by 0x9CC5D04: st_api_make_current (st_manager.c:876)
==3152==by 0x9E709CD: dri_make_current (dri_context.c:278)

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[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=90264

--- Comment #79 from anonymous  ---
Have the same issue with the tabs.

Chromium 59.0.3071.104
Mesa 13.0.6
Kernel amd64 4.11.6-1

All as packaged by Debian (Debian Testing).

Here is the output of chrome://gpu https://pastebin.com/WPEp71Mk

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Re: [Mesa-dev] [PATCH] glsl: xfb_stride applies to buffers, not block members

[Timothy Arceri]

On 10/07/17 17:58, Juan A. Suarez Romero wrote:

On Mon, 2017-07-10 at 14:30 +0800, Timothy Arceri wrote:


On 8 July 2017 12:19:48 am GMT+08:00, "Juan A. Suarez Romero" 
 wrote:

When we have an interface block like:

layout (xfb_buffer = 0, xfb_offset = 0) out Block {
 vec4 var1;
layout (xfb_stride = 48) vec4 var2;
 vec4 var3;
};

According to ARB_enhanced_layouts spec:

   "The *xfb_stride* qualifier specifies how many bytes are consumed by
each captured vertex.  It applies to the transform feedback buffer
for that declaration, whether it is inherited or explicitly
declared. It can be applied to variables, blocks, block members, or
just the qualifier out. [ ...] While *xfb_stride* can be declared
multiple times for the same buffer, it is a compile-time or
link-time error to have different values specified for the stride
for the same buffer."

This means xfb_stride actually applies to the buffer, and not to the
individual components.


Right. As I understand it, it applies to the buffer but can be set via a 
qualifier on a block member as the spec quote says above.



In the above example, it means that var2 consumes 16 bytes, and var3 is
at offset 32.

This has been confirmed also by John Kessenich, the main contact for
the
ARB_enhanced_layouts specs,


What exactly did he confirm? The example you give above or just that the stride 
applies to the buffer.



Both:

* Strides applies to buffer, not to block member. Hence, var2 requires
16 bytes, not 48.

* So this means that offsets for block members are, respectively, 0, 16
and 32.


Are you saying that the qualifier should be ignored besides throwing 
link/compile errors for block members?

My assumption was it should just apply to the whole block if it was set for any 
member.



Correct. That is what I'm saying. The qualifier applies to the full
block.


The main issue this patch fixes is that right now, Mesa is returning
var3 offset as 64 = 16 + 48, being 16 the var2 offset and 48 the
stride. In other words, it is applying the stride in the block member.

The right value should be 32 (16 + 16, var2 offset and var2 size).


Apologies for the delay I've been on holiday. In this case I wonder if 
something like the following actually sets the stride correctly.


layout (xfb_buffer = 0, xfb_offset = 0) out Block {
  vec4 var1;
 layout (xfb_stride = 64) vec4 var2;
  vec4 var3;
} arr[2];

anyway this patch looks correct, thanks.

Reviewed-by: Timothy Arceri 



J.A.





I can't look at the CTS until next week.

and also because this commit fixes:


GL45.enhanced_layouts.xfb_block_member_stride

This commit is in practice a revert of 598790e8564 (glsl: apply
xfb_stride to implicit offsets for ifc block members).
---
src/compiler/glsl/ast_to_hir.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/ast_to_hir.cpp
b/src/compiler/glsl/ast_to_hir.cpp
index c338ad7..3968657 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -7372,14 +7372,13 @@
ast_process_struct_or_iface_block_members(exec_list *instructions,
  qual->offset, _offset)) {
fields[i].offset = xfb_offset;
block_xfb_offset = fields[i].offset +
-  MAX2(xfb_stride, (int) (4 *
field_type->component_slots()));
+  4 * field_type->component_slots();
 }
  } else {
 if (layout && layout->flags.q.explicit_xfb_offset) {
unsigned align = field_type->is_64bit() ? 8 : 4;
fields[i].offset = glsl_align(block_xfb_offset, align);
-   block_xfb_offset +=
-  MAX2(xfb_stride, (int) (4 *
field_type->component_slots()));
+   block_xfb_offset += 4 * field_type->component_slots();
 }
  }

--
2.9.4

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Re: [Mesa-dev] [PATCH] nir: Use nir_src_copy instead of direct assignments.

[Matt Turner]

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH] nir/vars_to_ssa: Handle missing struct members in foreach_deref_node

[Timothy Arceri]

Reviewed-by: Timothy Arceri 

On 19/07/17 09:50, Jason Ekstrand wrote:

This can happen if, for instance, you have an array of structs and there
are both direct and wildcard references to the same struct and some
members only have direct or only have indirect.
---
  src/compiler/nir/nir_lower_vars_to_ssa.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c 
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index e5a12eb..e8cfe30 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -245,8 +245,12 @@ foreach_deref_node_worker(struct deref_node *node, 
nir_deref *deref,
  
case nir_deref_type_struct: {

   nir_deref_struct *str = nir_deref_as_struct(deref->child);
- return foreach_deref_node_worker(node->children[str->index],
-  deref->child, cb, state);
+ if (node->children[str->index] &&
+ !foreach_deref_node_worker(node->children[str->index],
+deref->child, cb, state))
+return false;
+
+ return true;
}
  
default:



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Re: [Mesa-dev] [PATCH v2 3/3] glsl: disable array splitting for AoA

[Jason Ekstrand]

I sent a replacement for patch 1.  Patches 2 and 3 are

Reviewed-by: Jason Ekstrand 

We should CC stable on my replacement for 1 and 2 because these affect
Vulkan even without the AoA splitting patch.

--Jason

On Sat, Jul 15, 2017 at 12:48 AM, Timothy Arceri 
wrote:

> On Mon, Jul 3, 2017, at 10:16 AM, Jason Ekstrand wrote:
> > I'd like the chance to look at these, please.  I'm on vacation today and
> > tomorrow though.
>
> Ping!
>
> >
> >
> > On July 3, 2017 7:19:04 AM funfunc...@folklore1984.net wrote:
> >
> > > On 2017-07-03 08:47, Timothy Arceri wrote:
> > >> While it produces functioning code the pass creates worse code
> > >> for arrays of arrays. See the comment added in this patch for more
> > >> detail.
> > >>
> > >> V2: skip splitting of AoA of matrices too.
> > >
> > > Reviewed-by: Edward O'Callaghan 
> > >
> > >> ---
> > >>  src/compiler/glsl/opt_array_splitting.cpp | 23
> +++
> > >>  1 file changed, 23 insertions(+)
> > >>
> > >> diff --git a/src/compiler/glsl/opt_array_splitting.cpp
> > >> b/src/compiler/glsl/opt_array_splitting.cpp
> > >> index fb6d77b..d2e81665 100644
> > >> --- a/src/compiler/glsl/opt_array_splitting.cpp
> > >> +++ b/src/compiler/glsl/opt_array_splitting.cpp
> > >> @@ -140,6 +140,29 @@
> > >> ir_array_reference_visitor::get_variable_entry(ir_variable *var)
> > >> if (var->type->is_unsized_array())
> > >>return NULL;
> > >>
> > >> +   /* FIXME: arrays of arrays are not handled correctly by this pass
> > >> so we
> > >> +* skip it for now. While the pass will create functioning code it
> > >> actually
> > >> +* produces worse code.
> > >> +*
> > >> +* For example the array:
> > >> +*
> > >> +*int[3][2] a;
> > >> +*
> > >> +* ends up being split up into:
> > >> +*
> > >> +*int[3][2] a_0;
> > >> +*int[3][2] a_1;
> > >> +*int[3][2] a_2;
> > >> +*
> > >> +* And we end up referencing each of these new arrays for example:
> > >> +*
> > >> +*a[0][1] will be turned into a_0[0][1]
> > >> +*a[1][0] will be turned into a_1[1][0]
> > >> +*a[2][0] will be turned into a_2[2][0]
> > >> +*/
> > >> +   if (var->type->is_array() && var->type->fields.array->is_array())
> > >> +  return NULL;
> > >> +
> > >> foreach_in_list(variable_entry, entry, >variable_list) {
> > >>if (entry->var == var)
> > >>   return entry;
> > >
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
> >
>
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Re: [Mesa-dev] [PATCH 1/3] nir: NULL check lower_copies_to_load_store()

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 4:26 PM, Timothy Arceri 
wrote:

> On 19/07/17 09:17, Jason Ekstrand wrote:
>
>> On Thu, Jun 29, 2017 at 7:45 PM, Timothy Arceri > > wrote:
>>
>> Allows us to disable array spliting for arrays of arrays without
>> regressing tests such as:
>>
>> ES31-CTS.functional.shaders.arrays_of_arrays.return.explicit
>> .struct_3x1x3_fragment
>> ---
>>   src/compiler/nir/nir_lower_vars_to_ssa.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
>> b/src/compiler/nir/nir_lower_vars_to_ssa.c
>> index e5a12eb..31f7e7a 100644
>> --- a/src/compiler/nir/nir_lower_vars_to_ssa.c
>> +++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
>> @@ -441,7 +441,7 @@ static bool
>>   lower_copies_to_load_store(struct deref_node *node,
>>  struct lower_variables_state *state)
>>   {
>> -   if (!node->copies)
>> +   if (!node || !node->copies)
>>
>>
>> If we got a NULL node here, something is wrong.  I think this is just
>> papering over the issue.
>>
>
> It's possible this was only an issue before the fix in the following
> patch. I'll drop this and push to jenkins to see if this can be dropped.
>

It can't.  I tried.

I just sent a patch that fixes the iterator to never pass in NULL.  I'd
prefer we replace this patch with that one.  I've verified that it fixes
the test mentioned in the commit message.


>
>> return true;
>>
>>  struct set_entry *copy_entry;
>> --
>> 2.9.4
>>
>> ___
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>> 
>>
>>
>>
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[Mesa-dev] [PATCH] nir/vars_to_ssa: Handle missing struct members in foreach_deref_node

[Jason Ekstrand]

This can happen if, for instance, you have an array of structs and there
are both direct and wildcard references to the same struct and some
members only have direct or only have indirect.
---
 src/compiler/nir/nir_lower_vars_to_ssa.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c 
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index e5a12eb..e8cfe30 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -245,8 +245,12 @@ foreach_deref_node_worker(struct deref_node *node, 
nir_deref *deref,
 
   case nir_deref_type_struct: {
  nir_deref_struct *str = nir_deref_as_struct(deref->child);
- return foreach_deref_node_worker(node->children[str->index],
-  deref->child, cb, state);
+ if (node->children[str->index] &&
+ !foreach_deref_node_worker(node->children[str->index],
+deref->child, cb, state))
+return false;
+
+ return true;
   }
 
   default:
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH] mesa: check API profile for GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION

[Ian Romanick]

On 07/18/2017 01:20 PM, Brian Paul wrote:
> If we have a compat profile context, it means that GL_QUADS[_STRIP] are
> supported so this query makes sense.  It's also legal for 3.2 core profile
> because of a spec bug.

Do you know of any apps that depend on that spec bug?  In most similar
cases, we've taken the later spec as a clarification, and we've just
done what the later spec says.  That has happened a lot.  Table 6.45
seems to be the only place in the 3.2 core profile spec that mentions
it, and appendix section E.2.2. does say that QUADS and QUAD_STRIP are
removed.

> ---
>  src/mesa/main/get.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
> index 825ea34..68f520f 100644
> --- a/src/mesa/main/get.c
> +++ b/src/mesa/main/get.c
> @@ -1302,7 +1302,7 @@ check_extra(struct gl_context *ctx, const char *func, 
> const struct value_desc *d
>   break;
>case EXTRA_EXT_PROVOKING_VERTEX_32:
>   api_check = TRUE;
> - if (version <= 32)
> + if (ctx->API == API_OPENGL_COMPAT || version == 32)
>  api_found = ctx->Extensions.EXT_provoking_vertex;
>   break;
>case EXTRA_END:
> 

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Re: [Mesa-dev] [PATCH 1/3] nir: NULL check lower_copies_to_load_store()

[Timothy Arceri]

On 19/07/17 09:17, Jason Ekstrand wrote:
On Thu, Jun 29, 2017 at 7:45 PM, Timothy Arceri > wrote:


Allows us to disable array spliting for arrays of arrays without
regressing tests such as:


ES31-CTS.functional.shaders.arrays_of_arrays.return.explicit.struct_3x1x3_fragment
---
  src/compiler/nir/nir_lower_vars_to_ssa.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index e5a12eb..31f7e7a 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -441,7 +441,7 @@ static bool
  lower_copies_to_load_store(struct deref_node *node,
 struct lower_variables_state *state)
  {
-   if (!node->copies)
+   if (!node || !node->copies)


If we got a NULL node here, something is wrong.  I think this is just 
papering over the issue.


It's possible this was only an issue before the fix in the following 
patch. I'll drop this and push to jenkins to see if this can be dropped.




return true;

 struct set_entry *copy_entry;
--
2.9.4

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Re: [Mesa-dev] [PATCH 1/3] nir: NULL check lower_copies_to_load_store()

[Jason Ekstrand]

On Thu, Jun 29, 2017 at 7:45 PM, Timothy Arceri 
wrote:

> Allows us to disable array spliting for arrays of arrays without
> regressing tests such as:
>
> ES31-CTS.functional.shaders.arrays_of_arrays.return.
> explicit.struct_3x1x3_fragment
> ---
>  src/compiler/nir/nir_lower_vars_to_ssa.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
> b/src/compiler/nir/nir_lower_vars_to_ssa.c
> index e5a12eb..31f7e7a 100644
> --- a/src/compiler/nir/nir_lower_vars_to_ssa.c
> +++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
> @@ -441,7 +441,7 @@ static bool
>  lower_copies_to_load_store(struct deref_node *node,
> struct lower_variables_state *state)
>  {
> -   if (!node->copies)
> +   if (!node || !node->copies)
>

If we got a NULL node here, something is wrong.  I think this is just
papering over the issue.


>return true;
>
> struct set_entry *copy_entry;
> --
> 2.9.4
>
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[Mesa-dev] [PATCH] nir: Use nir_src_copy instead of direct assignments.

[Kenneth Graunke]

If the source is an indirect register, there is ralloc'd data.  Copying
with a direct assignment will copy the pointer, but the data will still
belong to the old instruction's memory context.  Since we're lowering
and throwing away instructions, that could free the data by mistake.

Instead, use nir_src_copy, which properly handles this.

This is admittedly not a common case, so I think the bug is real,
but unlikely to be hit.

Cc: mesa-sta...@lists.freedesktop.org
---
 src/compiler/nir/nir_lower_atomics.c |  2 +-
 src/compiler/nir/nir_lower_atomics_to_ssbo.c | 12 ++--
 src/compiler/nir/nir_lower_io_to_scalar.c|  4 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/compiler/nir/nir_lower_atomics.c 
b/src/compiler/nir/nir_lower_atomics.c
index 1993013f8f6..2252e1679be 100644
--- a/src/compiler/nir/nir_lower_atomics.c
+++ b/src/compiler/nir/nir_lower_atomics.c
@@ -155,7 +155,7 @@ lower_instr(nir_intrinsic_instr *instr,
 * instruction.
 */
for (unsigned i = 0; i < nir_intrinsic_infos[instr->intrinsic].num_srcs; 
i++)
-  new_instr->src[i + 1] = instr->src[i];
+  nir_src_copy(_instr->src[i + 1], >src[i], new_instr);
 
if (instr->dest.is_ssa) {
   nir_ssa_dest_init(_instr->instr, _instr->dest,
diff --git a/src/compiler/nir/nir_lower_atomics_to_ssbo.c 
b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
index fd6eefb1fd0..371eb0b9d15 100644
--- a/src/compiler/nir/nir_lower_atomics_to_ssbo.c
+++ b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
@@ -115,7 +115,7 @@ lower_instr(nir_intrinsic_instr *instr, unsigned 
ssbo_offset, nir_builder *b)
   /* remapped to ssbo_atomic_add: { buffer_idx, offset, +1 } */
   temp = nir_imm_int(b, +1);
   new_instr->src[0] = nir_src_for_ssa(buffer);
-  new_instr->src[1] = instr->src[0];
+  nir_src_copy(_instr->src[1], >src[0], new_instr);
   new_instr->src[2] = nir_src_for_ssa(temp);
   break;
case nir_intrinsic_atomic_counter_dec:
@@ -123,21 +123,21 @@ lower_instr(nir_intrinsic_instr *instr, unsigned 
ssbo_offset, nir_builder *b)
   /* NOTE semantic difference so we adjust the return value below */
   temp = nir_imm_int(b, -1);
   new_instr->src[0] = nir_src_for_ssa(buffer);
-  new_instr->src[1] = instr->src[0];
+  nir_src_copy(_instr->src[1], >src[0], new_instr);
   new_instr->src[2] = nir_src_for_ssa(temp);
   break;
case nir_intrinsic_atomic_counter_read:
   /* remapped to load_ssbo: { buffer_idx, offset } */
   new_instr->src[0] = nir_src_for_ssa(buffer);
-  new_instr->src[1] = instr->src[0];
+  nir_src_copy(_instr->src[1], >src[0], new_instr);
   break;
default:
   /* remapped to ssbo_atomic_x: { buffer_idx, offset, data, (compare)? } */
   new_instr->src[0] = nir_src_for_ssa(buffer);
-  new_instr->src[1] = instr->src[0];
-  new_instr->src[2] = instr->src[1];
+  nir_src_copy(_instr->src[1], >src[0], new_instr);
+  nir_src_copy(_instr->src[2], >src[1], new_instr);
   if (op == nir_intrinsic_ssbo_atomic_comp_swap)
- new_instr->src[3] = instr->src[2];
+ nir_src_copy(_instr->src[3], >src[2], new_instr);
   break;
}
 
diff --git a/src/compiler/nir/nir_lower_io_to_scalar.c 
b/src/compiler/nir/nir_lower_io_to_scalar.c
index f2345d58acf..fffd1d3d2bb 100644
--- a/src/compiler/nir/nir_lower_io_to_scalar.c
+++ b/src/compiler/nir/nir_lower_io_to_scalar.c
@@ -49,7 +49,7 @@ lower_load_input_to_scalar(nir_builder *b, 
nir_intrinsic_instr *intr)
   nir_intrinsic_set_base(chan_intr, nir_intrinsic_base(intr));
   nir_intrinsic_set_component(chan_intr, nir_intrinsic_component(intr) + 
i);
   /* offset */
-  chan_intr->src[0] = intr->src[0];
+  nir_src_copy(_intr->src[0], >src[0], chan_intr);
 
   nir_builder_instr_insert(b, _intr->instr);
 
@@ -84,7 +84,7 @@ lower_store_output_to_scalar(nir_builder *b, 
nir_intrinsic_instr *intr)
   /* value */
   chan_intr->src[0] = nir_src_for_ssa(nir_channel(b, value, i));
   /* offset */
-  chan_intr->src[1] = intr->src[1];
+  nir_src_copy(_intr->src[1], >src[1], chan_intr);
 
   nir_builder_instr_insert(b, _intr->instr);
}
-- 
2.13.3

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Re: [Mesa-dev] [PATCH v3 8/8] egl/wayland: Use linux-dmabuf interface for buffers

[Mike Lothian]

Hi

I'm currently getting a build failure with this patch in an out of tree
build

Making all in egl
make[3]: Entering directory
'/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src/egl'

/usr/bin/wayland-scanner code <
/usr/share/wayland-protocols/unstable/linux-dmabuf/linux-dmabuf-unstable-v1.xml
> drivers/dri2/linux-dmabuf-unstable-v1-protocol.c
/usr/bin/wayland-scanner client-header <
/usr/share/wayland-protocols/unstable/linux-dmabuf/linux-dmabuf-unstable-v1.xml
> drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h
/usr/bin/python2.7
 
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/gen_egl_dispatch.py
source \
   
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/eglFunctionList.py
\
   
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/egl.xml
\
   
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/egl_other.xml
> g_egldispatchstubs.c
/usr/bin/python2.7
 
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/gen_egl_dispatch.py
header \
   
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/eglFunctionList.py
\
   
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/egl.xml
\
   
/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/generate/egl_other.xml
> g_egldispatchstubs.h
/bin/sh: drivers/dri2/linux-dmabuf-unstable-v1-protocol.c: No such file or
directory
make[3]: *** [Makefile:1609:
drivers/dri2/linux-dmabuf-unstable-v1-protocol.c] Error 1
make[3]: *** Waiting for unfinished jobs
/bin/sh: drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h: No such
file or directory
make[3]: *** [Makefile:1613:
drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h] Error 1

I've checked and
/usr/share/wayland-protocols/unstable/linux-dmabuf/linux-dmabuf-unstable-v1.xml
does exist on my system

Cheers

Mike

On Fri, 14 Jul 2017 at 14:36 Daniel Stone  wrote:

> When available, use the zwp_linux_dambuf_v1 interface to create buffers,
> which allows multiple planes and buffer modifiers to be used.
>
> Reviewed-by: Emil Velikov 
> Signed-off-by: Daniel Stone 
> ---
>  configure.ac|   5 +-
>  src/egl/Makefile.am |  23 +++-
>  src/egl/drivers/dri2/.gitignore |   2 +
>  src/egl/drivers/dri2/egl_dri2.c |   7 ++
>  src/egl/drivers/dri2/egl_dri2.h |  10 ++
>  src/egl/drivers/dri2/platform_wayland.c | 195
> +---
>  6 files changed, 221 insertions(+), 21 deletions(-)
>  create mode 100644 src/egl/drivers/dri2/.gitignore
>
> diff --git a/configure.ac b/configure.ac
> index 46fcd8f3fe..c5803e0f6e 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -88,6 +88,7 @@ LIBOMXIL_BELLAGIO_REQUIRED=0.0
>  LIBVA_REQUIRED=0.38.0
>  VDPAU_REQUIRED=1.1
>  WAYLAND_REQUIRED=1.11
> +WAYLAND_PROTOCOLS_REQUIRED=1.8
>  XCB_REQUIRED=1.9.3
>  XCBDRI2_REQUIRED=1.8
>  XCBGLX_REQUIRED=1.8.1
> @@ -1686,7 +1687,9 @@ for plat in $platforms; do
> case "$plat" in
> wayland)
>
> -   PKG_CHECK_MODULES([WAYLAND], [wayland-client >=
> $WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED])
> +   PKG_CHECK_MODULES([WAYLAND], [wayland-client >=
> $WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED wayland-protocols >=
> $WAYLAND_PROTOCOLS_REQUIRED])
> +ac_wayland_protocols_pkgdatadir=`$PKG_CONFIG
> --variable=pkgdatadir wayland-protocols`
> +AC_SUBST(WAYLAND_PROTOCOLS_DATADIR,
> $ac_wayland_protocols_pkgdatadir)
>
> if test "x$WAYLAND_SCANNER" = "x:"; then
> AC_MSG_ERROR([wayland-scanner is needed to compile
> the wayland platform])
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index 81090387b5..19295de3ed 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -21,6 +21,8 @@
>
>  include Makefile.sources
>
> +BUILT_SOURCES =
> +
>  AM_CFLAGS = \
> -I$(top_srcdir)/include \
> -I$(top_srcdir)/src/egl/main \
> @@ -61,11 +63,27 @@ endif
>  endif
>
>  if HAVE_PLATFORM_WAYLAND
> +WL_DMABUF_XML =
> $(WAYLAND_PROTOCOLS_DATADIR)/unstable/linux-dmabuf/linux-dmabuf-unstable-v1.xml
> +
> +drivers/dri2/linux-dmabuf-unstable-v1-protocol.c: $(WL_DMABUF_XML)
> +   $(MKDIR_GEN)
> +   $(AM_V_GEN)$(WAYLAND_SCANNER) code < $< > $@
> +
> +drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h: $(WL_DMABUF_XML)
> +   $(MKDIR_GEN)
> +   $(AM_V_GEN)$(WAYLAND_SCANNER) client-header < $< > $@
> +
> +BUILT_SOURCES += \
> +   drivers/dri2/linux-dmabuf-unstable-v1-protocol.c \
> +   drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h
> +
>  AM_CFLAGS += $(WAYLAND_CFLAGS)
>  libEGL_common_la_LIBADD += $(WAYLAND_LIBS)
>  libEGL_common_la_LIBADD += $(LIBDRM_LIBS)
>  libEGL_common_la_LIBADD += $(top_builddir)/src/egl/wayland/wayland-drm/
> 

Re: [Mesa-dev] [PATCH mesa] spirv: add missing include path

[Kenneth Graunke]

On Tuesday, July 18, 2017 11:16:50 AM PDT Emil Velikov wrote:
> On 18 July 2017 at 19:03, Eric Engestrom  wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101831
> > Signed-off-by: Eric Engestrom 
> > ---
> >
> > Note: Android and SCons probably need a similar fix
> > ---
> >  src/compiler/Makefile.nir.am | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
> > index 1533ee536d..002b9fc535 100644
> > --- a/src/compiler/Makefile.nir.am
> > +++ b/src/compiler/Makefile.nir.am
> > @@ -32,6 +32,9 @@ nir_libnir_la_SOURCES =   
> > \
> > $(SPIRV_GENERATED_FILES)\
> > $(NIR_GENERATED_FILES)
> >
> > +nir_libnir_la_SOURCES = \
> > +   -I$(top_builddir)/src/compiler/spirv
> > +
> This is off - the generated file is missing the srcdir, since it
> assumes the header to be in the same directory.
> 
> Ken should have pushed a fix a second ago.
> -Emil
> ___
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Sorry, I checked the list for a fix, but missed your patch.
Hopefully it's fixed now, at any rate.

--Ken

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Re: [Mesa-dev] [PATCH 1/4] ra: Pull the body of a loop out to a helper function.

[Eric Anholt]

Eric Anholt  writes:

> I was going to indent this code another level, and decided it would be
> easier to read as a helper.

Could some other user of the RA take a look at this series?


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[Mesa-dev] [PATCH v2 2/2] configure/swr: add KNL and SKX architecture targets

[Tim Rowley]

Not built by default.
---
 configure.ac   | 22 ++--
 src/gallium/drivers/swr/Makefile.am| 38 ++
 src/gallium/drivers/swr/swr_loader.cpp | 20 ++
 3 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index 66dbc69..2e095ee 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2354,7 +2354,7 @@ dnl Architectures to build SWR library for
 AC_ARG_WITH([swr-archs],
 [AS_HELP_STRING([--with-swr-archs@<:@=DIRS...@:>@],
 [comma delimited swr architectures list, e.g.
-"avx,avx2" @<:@default="avx,avx2"@:>@])],
+"avx,avx2,knl,skx" @<:@default="avx,avx2"@:>@])],
 [with_swr_archs="$withval"],
 [with_swr_archs="avx,avx2"])
 
@@ -2518,6 +2518,20 @@ if test -n "$with_gallium_drivers"; then
 AC_SUBST([SWR_AVX2_CXXFLAGS])
 HAVE_SWR_AVX2=yes
 ;;
+xknl)
+swr_require_cxx_feature_flags "KNL" "defined(__AVX512F__) 
&& defined(__AVX512ER__)" \
+",-march=knl,-xMIC-AVX512" \
+SWR_KNL_CXXFLAGS
+AC_SUBST([SWR_KNL_CXXFLAGS])
+HAVE_SWR_KNL=yes
+;;
+xskx)
+swr_require_cxx_feature_flags "SKX" "defined(__AVX512F__) 
&& defined(__AVX512BW__)" \
+",-march=skylake-avx512,-xCORE-AVX512" \
+SWR_SKX_CXXFLAGS
+AC_SUBST([SWR_SKX_CXXFLAGS])
+HAVE_SWR_SKX=yes
+;;
 *)
 AC_MSG_ERROR([unknown SWR build architecture '$arch'])
 ;;
@@ -2525,7 +2539,9 @@ if test -n "$with_gallium_drivers"; then
 done
 
 if test "x$HAVE_SWR_AVX" != xyes -a \
-"x$HAVE_SWR_AVX2" != xyes; then
+"x$HAVE_SWR_AVX2" != xyes -a \
+"x$HAVE_SWR_KNL" != xyes -a \
+"x$HAVE_SWR_SKX" != xyes -a; then
AC_MSG_ERROR([swr enabled but no swr architectures selected])
 fi
 
@@ -2568,6 +2584,8 @@ fi
 
 AM_CONDITIONAL(HAVE_SWR_AVX, test "x$HAVE_SWR_AVX" = xyes)
 AM_CONDITIONAL(HAVE_SWR_AVX2, test "x$HAVE_SWR_AVX2" = xyes)
+AM_CONDITIONAL(HAVE_SWR_KNL, test "x$HAVE_SWR_KNL" = xyes)
+AM_CONDITIONAL(HAVE_SWR_SKX, test "x$HAVE_SWR_SKX" = xyes)
 
 dnl We need to validate some needed dependencies for renderonly drivers.
 
diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index f38ce7b..6495021 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -63,6 +63,14 @@ if HAVE_SWR_AVX2
 libmesaswr_la_CXXFLAGS += -DHAVE_SWR_AVX2
 endif
 
+if HAVE_SWR_KNL
+libmesaswr_la_CXXFLAGS += -DHAVE_SWR_KNL
+endif
+
+if HAVE_SWR_SKX
+libmesaswr_la_CXXFLAGS += -DHAVE_SWR_SKX
+endif
+
 COMMON_SOURCES = \
$(ARCHRAST_CXX_SOURCES) \
$(COMMON_CXX_SOURCES) \
@@ -263,6 +271,36 @@ libswrAVX2_la_LDFLAGS = \
$(COMMON_LDFLAGS)
 endif
 
+if HAVE_SWR_KNL
+lib_LTLIBRARIES += libswrKNL.la
+
+libswrKNL_la_CXXFLAGS = \
+   $(SWR_KNL_CXXFLAGS) \
+   -DKNOB_ARCH=KNOB_ARCH_AVX512 -DAVX512F_STRICT \
+   $(COMMON_CXXFLAGS)
+
+libswrKNL_la_SOURCES = \
+   $(COMMON_SOURCES)
+
+libswrKNL_la_LDFLAGS = \
+   $(COMMON_LDFLAGS)
+endif
+
+if HAVE_SWR_SKX
+lib_LTLIBRARIES += libswrSKX.la
+
+libswrSKX_la_CXXFLAGS = \
+   $(SWR_SKX_CXXFLAGS) \
+   -DKNOB_ARCH=KNOB_ARCH_AVX512 \
+   $(COMMON_CXXFLAGS)
+
+libswrSKX_la_SOURCES = \
+   $(COMMON_SOURCES)
+
+libswrSKX_la_LDFLAGS = \
+   $(COMMON_LDFLAGS)
+endif
+
 include $(top_srcdir)/install-gallium-links.mk
 
 # Generated gen_builder.hpp is not backwards compatible. So ship only one
diff --git a/src/gallium/drivers/swr/swr_loader.cpp 
b/src/gallium/drivers/swr/swr_loader.cpp
index 4aa850a..e205fe2 100644
--- a/src/gallium/drivers/swr/swr_loader.cpp
+++ b/src/gallium/drivers/swr/swr_loader.cpp
@@ -38,6 +38,26 @@ swr_create_screen(struct sw_winsys *winsys)
 
util_cpu_detect();
 
+   if (!strlen(filename) &&
+   util_cpu_caps.has_avx512f && util_cpu_caps.has_avx512er) {
+#if HAVE_SWR_KNL
+  fprintf(stderr, "KNL ");
+  sprintf(filename, "%s%s%s", UTIL_DL_PREFIX, "swrKNL", UTIL_DL_EXT);
+#else
+  fprintf(stderr, "KNL (not built) ");
+#endif
+   }
+
+   if (!strlen(filename) &&
+   util_cpu_caps.has_avx512f && util_cpu_caps.has_avx512bw) {
+#if HAVE_SWR_SKX
+  fprintf(stderr, "SKX ");
+  sprintf(filename, "%s%s%s", UTIL_DL_PREFIX, "swrSKX", UTIL_DL_EXT);
+#else
+  fprintf(stderr, "SKX (not built) ");
+#endif
+   }
+
if (!strlen(filename) && util_cpu_caps.has_avx2) {
 #if HAVE_SWR_AVX2
   fprintf(stderr, "AVX2 ");
-- 
2.7.4

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[Mesa-dev] [PATCH v2 0/2] swr: add knl and skx architectures

[Tim Rowley]

Patch set allows the swr architectures built to be specified at
configure time, and adds KNL and SKX as possible targets (not built
by default).

v2:
 * fix swr_archs default value, document knl,skx options
 * change loader lib selection code to make it clearer

Tim Rowley (2):
  configure/swr: configurable swr architectures
  configure/swr: add KNL and SKX architecture targets

 configure.ac   | 62 +++---
 src/gallium/drivers/swr/Makefile.am| 55 +-
 src/gallium/drivers/swr/SConscript |  1 +
 src/gallium/drivers/swr/swr_loader.cpp | 50 +++
 4 files changed, 156 insertions(+), 12 deletions(-)

-- 
2.7.4

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[Mesa-dev] [PATCH v2 1/2] configure/swr: configurable swr architectures

[Tim Rowley]

Allow configuration of the SWR architecture depend libraries
we build for with --with-swr-archs.  Maintains current behavior
by defaulting to avx,avx2.

Scons changes made to make it still build and work, but
without the changes for configuring which architectures.
---
 configure.ac   | 44 ++
 src/gallium/drivers/swr/Makefile.am| 17 -
 src/gallium/drivers/swr/SConscript |  1 +
 src/gallium/drivers/swr/swr_loader.cpp | 30 +--
 4 files changed, 80 insertions(+), 12 deletions(-)

diff --git a/configure.ac b/configure.ac
index 46fcd8f..66dbc69 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2349,6 +2349,15 @@ AC_ARG_WITH([d3d-libdir],
 [D3D_DRIVER_INSTALL_DIR="${libdir}/d3d"])
 AC_SUBST([D3D_DRIVER_INSTALL_DIR])
 
+dnl Architectures to build SWR library for
+
+AC_ARG_WITH([swr-archs],
+[AS_HELP_STRING([--with-swr-archs@<:@=DIRS...@:>@],
+[comma delimited swr architectures list, e.g.
+"avx,avx2" @<:@default="avx,avx2"@:>@])],
+[with_swr_archs="$withval"],
+[with_swr_archs="avx,avx2"])
+
 dnl
 dnl r300 doesn't strictly require LLVM, but for performance reasons we
 dnl highly recommend LLVM usage. So require it at least on x86 and x86_64
@@ -2496,10 +2505,29 @@ if test -n "$with_gallium_drivers"; then
 SWR_AVX_CXXFLAGS
 AC_SUBST([SWR_AVX_CXXFLAGS])
 
-swr_require_cxx_feature_flags "AVX2" "defined(__AVX2__)" \
-",-mavx2 -mfma -mbmi2 -mf16c,-march=core-avx2" \
-SWR_AVX2_CXXFLAGS
-AC_SUBST([SWR_AVX2_CXXFLAGS])
+swr_archs=`IFS=', '; echo $with_swr_archs`
+for arch in $swr_archs; do
+case "x$arch" in
+xavx)
+HAVE_SWR_AVX=yes
+;;
+xavx2)
+swr_require_cxx_feature_flags "AVX2" "defined(__AVX2__)" \
+",-mavx2 -mfma -mbmi2 -mf16c,-march=core-avx2" \
+SWR_AVX2_CXXFLAGS
+AC_SUBST([SWR_AVX2_CXXFLAGS])
+HAVE_SWR_AVX2=yes
+;;
+*)
+AC_MSG_ERROR([unknown SWR build architecture '$arch'])
+;;
+esac
+done
+
+if test "x$HAVE_SWR_AVX" != xyes -a \
+"x$HAVE_SWR_AVX2" != xyes; then
+   AC_MSG_ERROR([swr enabled but no swr architectures selected])
+fi
 
 HAVE_GALLIUM_SWR=yes
 ;;
@@ -2538,6 +2566,9 @@ if test "x$enable_llvm" = "xyes" -a 
"$with_gallium_drivers"; then
 llvm_add_default_components "gallium"
 fi
 
+AM_CONDITIONAL(HAVE_SWR_AVX, test "x$HAVE_SWR_AVX" = xyes)
+AM_CONDITIONAL(HAVE_SWR_AVX2, test "x$HAVE_SWR_AVX2" = xyes)
+
 dnl We need to validate some needed dependencies for renderonly drivers.
 
 if test "x$HAVE_GALLIUM_ETNAVIV" != xyes -a "x$HAVE_GALLIUM_IMX" = xyes  ; then
@@ -2977,6 +3008,11 @@ else
 echo "HUD lmsensors:   yes"
 fi
 
+echo ""
+if test "x$HAVE_GALLIUM_SWR" != x; then
+echo "SWR archs:   $swr_archs"
+fi
+
 dnl Libraries
 echo ""
 echo "Shared libs: $enable_shared"
diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 7461228..f38ce7b 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -55,6 +55,14 @@ libmesaswr_la_CXXFLAGS = \
$(SWR_AVX_CXXFLAGS) \
$(COMMON_CXXFLAGS)
 
+if HAVE_SWR_AVX
+libmesaswr_la_CXXFLAGS += -DHAVE_SWR_AVX
+endif
+
+if HAVE_SWR_AVX2
+libmesaswr_la_CXXFLAGS += -DHAVE_SWR_AVX2
+endif
+
 COMMON_SOURCES = \
$(ARCHRAST_CXX_SOURCES) \
$(COMMON_CXX_SOURCES) \
@@ -224,7 +232,10 @@ COMMON_LDFLAGS = \
$(GC_SECTIONS) \
$(NO_UNDEFINED)
 
-lib_LTLIBRARIES = libswrAVX.la libswrAVX2.la
+lib_LTLIBRARIES =
+
+if HAVE_SWR_AVX
+lib_LTLIBRARIES += libswrAVX.la
 
 libswrAVX_la_CXXFLAGS = \
$(SWR_AVX_CXXFLAGS) \
@@ -236,7 +247,10 @@ libswrAVX_la_SOURCES = \
 
 libswrAVX_la_LDFLAGS = \
$(COMMON_LDFLAGS)
+endif
 
+if HAVE_SWR_AVX2
+lib_LTLIBRARIES += libswrAVX2.la
 libswrAVX2_la_CXXFLAGS = \
$(SWR_AVX2_CXXFLAGS) \
-DKNOB_ARCH=KNOB_ARCH_AVX2 \
@@ -247,6 +261,7 @@ libswrAVX2_la_SOURCES = \
 
 libswrAVX2_la_LDFLAGS = \
$(COMMON_LDFLAGS)
+endif
 
 include $(top_srcdir)/install-gallium-links.mk
 
diff --git a/src/gallium/drivers/swr/SConscript 
b/src/gallium/drivers/swr/SConscript
index cdfb91a..a32807d 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -245,6 +245,7 @@ source += [
 
 # main SWR lib
 envSWR = envavx.Clone() # pick up the arch flag for intrinsic usage
+envSWR.Append(CPPDEFINES = ['HAVE_SWR_AVX', 'HAVE_SWR_AVX2'])
 swr = envSWR.ConvenienceLibrary(
 target = 'swr',
 source = source,
diff --git a/src/gallium/drivers/swr/swr_loader.cpp 

Re: [Mesa-dev] [PATCH 2/2] configure/swr: add KNL and SKX architecture targets

[Rowley, Timothy O]

On Jul 17, 2017, at 11:51 AM, Emil Velikov 
> wrote:

On 17 July 2017 at 15:08, Tim Rowley 
> wrote:
Not built by default.
---
configure.ac   | 16 ++
src/gallium/drivers/swr/Makefile.am| 38 ++
src/gallium/drivers/swr/swr_loader.cpp | 20 +-
3 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 3a8fa4d7ea..4437c8189d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2518,6 +2518,20 @@ if test -n "$with_gallium_drivers"; then
AC_SUBST([SWR_AVX2_CXXFLAGS])
HAVE_SWR_AVX2=yes
;;
+xknl)
+swr_require_cxx_feature_flags "KNL" "defined(__AVX512F__) 
&& defined(__AVX512ER__)" \
+",-march=knl,-xMIC-AVX512" \
+SWR_KNL_CXXFLAGS
+AC_SUBST([SWR_KNL_CXXFLAGS])
+HAVE_SWR_KNL=yes
+;;
+xskx)
+swr_require_cxx_feature_flags "SKX" "defined(__AVX512F__) 
&& defined(__AVX512BW__)" \
+",-march=skylake-avx512,-xCORE-AVX512" \
+SWR_SKX_CXXFLAGS
+AC_SUBST([SWR_SKX_CXXFLAGS])
+HAVE_SWR_SKX=yes
+;;
Please update of the help string. Otherwise these two are completely
undocumented.


Will do.

Can I bribe you to add a Travis entries for the above? If it doesn't
take too long to build, you can it squash into the existing ones.

I’ll do that in a future patch; the avx512 code in swr as it currently exists 
in mesa-master only works on icc, which isn’t one of the Travis options.  We’re 
working on a patch which enables modern clang and gcc to also build it.


Thanks
Emil

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Re: [Mesa-dev] [PATCH 5/6] radeonsi: use slot indexes for bindless handles

[Marek Olšák]

On Mon, Jul 17, 2017 at 4:01 PM, Nicolai Hähnle  wrote:
> Hi Samuel,
>
> On 07.07.2017 03:45, Samuel Pitoiset wrote:
>>
>> On 07/05/2017 01:42 PM, Nicolai Hähnle wrote:
>>>
>>> On 04.07.2017 15:05, Samuel Pitoiset wrote:

 Using VRAM address as bindless handles is not a good idea because
 we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize
 because it has no information about the pointer.

 Instead, use slots indexes like the existing descriptors.

 This improves performance with DOW3 by +7%.
>>>
>>>
>>> Wow.
>>>
>>> The thing is, burning a pair of user SGPRs for this seems a bit overkill,
>>> especially since it also hurts apps that don't use bindless at all.
>>>
>>> Do you have some examples of how LLVM fails here? Could we perhaps avoid
>>> most of the performance issues by casting 0 to an appropriate pointer type
>>> once, and then using the bindless handle as an index relative to that
>>> pointer?
>>
>>
>> Here's two shaders, 1) is with master, 2) is with this series:
>>
>> 1) https://hastebin.com/uvamarelig
>> 2) https://hastebin.com/voguqihilu
>>
>> The first shader contains a bunch of s_buffer_load_dword that the second
>> one doesn't need because CSE do its job there. This is because of IntToPtr
>> but if we use noalias, the pass is able to eliminate the redundant
>> descriptor load operations.
>
>
> So I looked into your example again in more detail, compiling both shaders
> with
>
>   llc -march=amdgcn -mcpu=tonga
>
> and also just extracting the assembly, and I think your analysis is actually
> flawed. It's true that the shader in (2) has fewer buffer loads, but the
> only buffer loads that are actually removed rather than just shuffled around
> are ones that load .y components. So basically, the reason you get fewer
> buffer loads is that you're effectly using 32 bit pointers. It's a bit
> shocking that that gives you a 7% performance improvement...
>
> If there are really examples where it makes a difference for CSE, then
> perhaps the same result could be achieved with alias/noalias metadata on the
> load/store instructions.
>
> In the meantime, perhaps a good comparison would be to use the original,
> inttoptr-based code, but only load the lower 32 bits for a handle and use
> bit shifts to get a full 64 bit pointers. That way, at least it should be
> possible to more easily find shaders where there is a genuine difference.

He probably gave you wrong shaders. If you imagine an NxN filter doing
NxN texture fetches, you should get NxN loads for the same descriptor
with inttoptr. Also, LICM won't move the descriptor loads out of
loops. Those are the biggest issues. If you can't do CSE and LICM, it
can easily make the 7% difference.

Marek
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Re: [Mesa-dev] [PATCH 1/2] configure/swr: configurable swr architectures

[Rowley, Timothy O]

On Jul 17, 2017, at 11:42 AM, Emil Velikov 
> wrote:

On 17 July 2017 at 15:08, Tim Rowley 
> wrote:
Allow configuration of the SWR architecture depend libraries
we build for with --with-swr-archs.  Maintains current behavior
by defaulting to avx,avx2.

Scons changes made to make it still build and work, but
without the changes for configuring which architectures.
---
configure.ac   | 39 ++
src/gallium/drivers/swr/Makefile.am| 17 ++-
src/gallium/drivers/swr/SConscript |  1 +
src/gallium/drivers/swr/swr_loader.cpp | 22 +++
4 files changed, 70 insertions(+), 9 deletions(-)

diff --git a/configure.ac b/configure.ac
index 46fcd8f3fe..3a8fa4d7ea 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2349,6 +2349,15 @@ AC_ARG_WITH([d3d-libdir],
[D3D_DRIVER_INSTALL_DIR="${libdir}/d3d"])
AC_SUBST([D3D_DRIVER_INSTALL_DIR])

+dnl Architectures to build SWR library for
+
+AC_ARG_WITH([swr-archs],
+[AS_HELP_STRING([--with-swr-archs@<:@=DIRS...@:>@],
+[comma delimited swr architectures list, e.g.
+"avx,avx2" @<:@default="avx,avx2"@:>@])],
+[with_swr_archs="$withval"],
+[with_swr_archs="avx avx2"])
Add the missing comma - "avx,avx2”

Will do.


+
dnl
dnl r300 doesn't strictly require LLVM, but for performance reasons we
dnl highly recommend LLVM usage. So require it at least on x86 and x86_64
@@ -2496,10 +2505,24 @@ if test -n "$with_gallium_drivers"; then
SWR_AVX_CXXFLAGS
AC_SUBST([SWR_AVX_CXXFLAGS])

-swr_require_cxx_feature_flags "AVX2" "defined(__AVX2__)" \
-",-mavx2 -mfma -mbmi2 -mf16c,-march=core-avx2" \
-SWR_AVX2_CXXFLAGS
-AC_SUBST([SWR_AVX2_CXXFLAGS])
+swr_archs=`IFS=', '; echo $with_swr_archs`
+for arch in $swr_archs; do
+case "x$arch" in
+xavx)
You want to move the AVX flag detection here, right?

No, since we need to have SWR_AVX_CXXFLAGS to build the driver proper.


+HAVE_SWR_AVX=yes
+;;
+xavx2)
+swr_require_cxx_feature_flags "AVX2" "defined(__AVX2__)" \
+",-mavx2 -mfma -mbmi2 -mf16c,-march=core-avx2" \
+SWR_AVX2_CXXFLAGS
+AC_SUBST([SWR_AVX2_CXXFLAGS])
+HAVE_SWR_AVX2=yes
+;;
+*)
+AC_MSG_ERROR([unknown SWR build architecture '$arch'])
+;;
+esac
+done

And error out if building without any arch?

Added.

HAVE_GALLIUM_SWR=yes
;;
@@ -2538,6 +2561,9 @@ if test "x$enable_llvm" = "xyes" -a 
"$with_gallium_drivers"; then
llvm_add_default_components "gallium"
fi

+AM_CONDITIONAL(HAVE_SWR_AVX, test "x$HAVE_SWR_AVX" = xyes)
+AM_CONDITIONAL(HAVE_SWR_AVX2, test "x$HAVE_SWR_AVX2" = xyes)
+
dnl We need to validate some needed dependencies for renderonly drivers.

if test "x$HAVE_GALLIUM_ETNAVIV" != xyes -a "x$HAVE_GALLIUM_IMX" = xyes  ; then
@@ -2977,6 +3003,11 @@ else
echo "HUD lmsensors:   yes"
fi

+echo ""
+if test "x$HAVE_GALLIUM_SWR" != x; then
+echo "SWR archs:   $swr_archs"
+fi
+
dnl Libraries
echo ""
echo "Shared libs: $enable_shared"
diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 74612280fe..f38ce7b1d9 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -55,6 +55,14 @@ libmesaswr_la_CXXFLAGS = \
   $(SWR_AVX_CXXFLAGS) \
   $(COMMON_CXXFLAGS)

+if HAVE_SWR_AVX
+libmesaswr_la_CXXFLAGS += -DHAVE_SWR_AVX
+endif
+
+if HAVE_SWR_AVX2
+libmesaswr_la_CXXFLAGS += -DHAVE_SWR_AVX2
+endif
+
COMMON_SOURCES = \
   $(ARCHRAST_CXX_SOURCES) \
   $(COMMON_CXX_SOURCES) \
@@ -224,7 +232,10 @@ COMMON_LDFLAGS = \
   $(GC_SECTIONS) \
   $(NO_UNDEFINED)

-lib_LTLIBRARIES = libswrAVX.la 
libswrAVX2.la
+lib_LTLIBRARIES =
+
+if HAVE_SWR_AVX
+lib_LTLIBRARIES += libswrAVX.la

libswrAVX_la_CXXFLAGS = \
   $(SWR_AVX_CXXFLAGS) \
@@ -236,7 +247,10 @@ libswrAVX_la_SOURCES = \

libswrAVX_la_LDFLAGS = \
   $(COMMON_LDFLAGS)
+endif

+if HAVE_SWR_AVX2
+lib_LTLIBRARIES += libswrAVX2.la
libswrAVX2_la_CXXFLAGS = \
   $(SWR_AVX2_CXXFLAGS) \
   -DKNOB_ARCH=KNOB_ARCH_AVX2 \
@@ -247,6 +261,7 @@ libswrAVX2_la_SOURCES = \

libswrAVX2_la_LDFLAGS = \
   $(COMMON_LDFLAGS)
+endif

include $(top_srcdir)/install-gallium-links.mk

diff --git a/src/gallium/drivers/swr/SConscript 
b/src/gallium/drivers/swr/SConscript
index cdfb91a5bb..a32807d36b 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -245,6 +245,7 @@ 

Re: [Mesa-dev] i965: Transition depth and stencil surfaces to isl

[Jason Ekstrand]

I've read through the whole thing and given reviews on about 75% of it.  I
did have some questions though.

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> First four patches are mechanical replacing intel_mipmap_tree native
> members with equivalent found in intel_mipmap_tree::surf. This helps
> to reduce back and forth churn, i.e., helps to avoid number of
> "if (mt->surf.size > 0)"-conditionals that would get dropped in the
> end. Assumption is that this mixed used of intel_mipmap_tree::surf
> and native would be short lived.
>
> Patch number five is of the same nature - it helps to re-use current
> logic without checks for isl. Once all surfaces are transitioned it
> is pretty easy to drop intel_mipmap_tree::cpp (we might even decide
> to keep it instead of calculating it on-demand).
>
> Patches 6-15, 18 and 19 in turn introduce conditional
> "if (mt->surf.size)" blocks that can't be trivially avoided. I
> considered using isl_surf::logical_level0_px/phys_level0_sa instead
> of native intel_mipmap_tree equivalent but that gets a lot more
> complicated than simply introducing the conditional blocks that one
> removes in the end.
> These patches pave the way quite a bit also for color surfaces.
>
> Patches 16 and 17 switch stencil surfaces to isl and finally the last
> does the same for depth surfaces.
>
> Topi Pohjolainen (22):
>   i965/miptree: Switch to isl_surf::msaa_layout
>   i965/miptree: Switch to isl_surf::samples
>   i965/miptree: Switch to isl_surf::tiling
>   i965/miptree: Switch to isl_surf::row_pitch
>   i965/miptree: Store chars-per-pixel even for isl based
>   i965: Prepare blit engine for isl based miptrees
>   i965/miptree: Prepare intel_miptree_copy() for isl based
>   i965/wm: Prepare image surfaces for isl based
>   i965: Prepare tex (sub)image for isl based
>   i965: Refactor miptree to isl converter and adjustment
>   i965: Prepare tex, img and rt state emission for isl based miptrees
>   i965: Prepare image setup from miptree for isl based
>   i965/fbo: Add support for isl-based miptrees in rb wrapper
>   i965/miptree: Add support for imported bo offsets for isl based
>   i965/miptree: Prepare compressed offsets for isl based
>   i965/miptree: Represent w-tiled stencil surfaces with isl
>   i965/miptree: Represent y-tiled stencil copies with isl
>   i965/miptree: Prepare aux state map for isl based
>   i965/miptree: Prepare 3D surfaces with physical 2D layout
>   intel/isl/gen4: Represent cube maps with 3D layout
>   i965: Drop redundant check for non-tiled depth buffer
>   i965: Represent depth surfaces with isl
>
>  src/intel/isl/isl.c  |  40 +-
>  src/mesa/drivers/dri/i965/brw_blorp.c|  19 +-
>  src/mesa/drivers/dri/i965/brw_clear.c|   5 +-
>  src/mesa/drivers/dri/i965/brw_context.c  |   2 +-
>  src/mesa/drivers/dri/i965/brw_meta_util.c|   2 +-
>  src/mesa/drivers/dri/i965/brw_misc_state.c   |  11 +-
>  src/mesa/drivers/dri/i965/brw_tex_layout.c   |  41 +-
>  src/mesa/drivers/dri/i965/brw_wm.c   |   6 +-
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 154 ---
>  src/mesa/drivers/dri/i965/gen6_depth_state.c |   5 +-
>  src/mesa/drivers/dri/i965/gen7_misc_state.c  |  22 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c |  31 +-
>  src/mesa/drivers/dri/i965/intel_blit.c   | 107 +++--
>  src/mesa/drivers/dri/i965/intel_blit.h   |  21 +-
>  src/mesa/drivers/dri/i965/intel_fbo.c|  19 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 505
> +--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  81 +---
>  src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |   4 +-
>  src/mesa/drivers/dri/i965/intel_pixel_copy.c |   2 +-
>  src/mesa/drivers/dri/i965/intel_pixel_read.c |  10 +-
>  src/mesa/drivers/dri/i965/intel_screen.c |  22 +-
>  src/mesa/drivers/dri/i965/intel_tex_image.c  |  36 +-
>  src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  18 +-
>  src/mesa/drivers/dri/i965/intel_tiled_memcpy.c   |  12 +-
>  src/mesa/drivers/dri/i965/intel_tiled_memcpy.h   |   4 +-
>  25 files changed, 637 insertions(+), 542 deletions(-)
>
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 22/22] i965: Represent depth surfaces with isl

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_clear.c |   5 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c  |   3 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 136
> +-
>  3 files changed, 97 insertions(+), 47 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
> b/src/mesa/drivers/dri/i965/brw_clear.c
> index 7fbaa3a47d..c310d2547a 100644
> --- a/src/mesa/drivers/dri/i965/brw_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> @@ -121,7 +121,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
> if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
>perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
>   "Possible 5%% performance win if avoided.\n",
> - mt->logical_width0, mt->logical_height0);
> + mt->surf.logical_level0_px.width,
> + mt->surf.logical_level0_px.height);
>return false;
> }
>
> @@ -149,7 +150,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
> *optimization must be disabled.
> */
>if (brw->gen == 6 &&
> -  (minify(mt->physical_width0,
> +  (minify(mt->surf.phys_level0_sa.width,
>depth_irb->mt_level - mt->first_level) % 16) != 0)
>  return false;
>break;
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index c934d0d21a..5cee93ade0 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -78,7 +78,8 @@ emit_depth_packets(struct brw_context *brw,
> OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
> OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
> OUT_BATCH(0);
> -   OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 :
> 0));
> +   OUT_BATCH(((depth - 1) << 21) |
> +  (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
> ADVANCE_BATCH();
>
> if (!hiz) {
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 702dcd8635..ea8b2662fd 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -520,43 +520,7 @@ intel_miptree_create_layout(struct brw_context *brw,
> mt->physical_height0 = height0;
> mt->physical_depth0 = depth0;
>
> -   if (needs_separate_stencil(brw, mt, format, layout_flags)) {
> -  uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
> -  if (brw->gen == 6) {
> - stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
> -  }
> -
> -  mt->stencil_mt = intel_miptree_create(brw,
> -mt->target,
> -MESA_FORMAT_S_UINT8,
> -mt->first_level,
> -mt->last_level,
> -mt->logical_width0,
> -mt->logical_height0,
> -mt->logical_depth0,
> -num_samples,
> -stencil_flags);
> -
> -  if (!mt->stencil_mt) {
> -intel_miptree_release();
> -return NULL;
> -  }
> -  mt->stencil_mt->r8stencil_needs_update = true;
> -
> -  /* Fix up the Z miptree format for how we're splitting out separate
> -   * stencil.  Gen7 expects there to be no stencil bits in its depth
> buffer.
> -   */
> -  mt->format = intel_depth_format_for_depthstencil_format(mt->
> format);
> -  mt->cpp = 4;
> -
> -  if (format == mt->format) {
> - _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
> -   _mesa_get_format_name(mt->format));
> -  }
> -   }
> -
> -   if (layout_flags & MIPTREE_LAYOUT_GEN6_HIZ_STENCIL)
> -  mt->array_layout = GEN6_HIZ_STENCIL;
> +   assert(!needs_separate_stencil(brw, mt, format, layout_flags));
>
> /*
>  * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
> @@ -829,6 +793,40 @@ fail:
> return NULL;
>  }
>
> +static bool
> +separate_stencil_surface(struct brw_context *brw,
> + struct intel_mipmap_tree *mt)
>

make_separate_stencil_surface?  Also, it seems perfectly reasonable for
this to return the miptree rather than a bool.


> +{
> +   mt->stencil_mt = make_surface(brw, mt->target, MESA_FORMAT_S_UINT8,
> + 0, mt->surf.levels - 1,
> + mt->surf.logical_level0_px.width,
> + mt->surf.logical_level0_px.height,
> +

Re: [Mesa-dev] [RFC PATCH] radeonsi: set a per-buffer flag that disables inter-process sharing (v2)

[Marek Olšák]

On Tue, Jul 18, 2017 at 5:11 PM, Michel Dänzer  wrote:
> On 18/07/17 04:08 PM, Marek Olšák wrote:
>>
>> From: Marek Olšák 
>>
>> For lower overhead in the CS ioctl.
>> Winsys allocators are not used with interprocess-sharable resources.
>>
>> v2: It shouldn't crash anymore, but the kernel will reject the new flag.
>> ---
>>   src/gallium/drivers/radeon/r600_buffer_common.c |  7 +
>>   src/gallium/drivers/radeon/radeon_winsys.h  | 20 +++---
>>   src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 36
>> -
>>   src/gallium/winsys/radeon/drm/radeon_drm_bo.c   | 27 +++
>>   4 files changed, 62 insertions(+), 28 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
>> b/src/gallium/drivers/radeon/r600_buffer_common.c
>> index dd1c209..2747ac4 100644
>> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
>> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
>> @@ -160,20 +160,27 @@ void r600_init_resource_fields(struct
>> r600_common_screen *rscreen,
>> }
>> /* Tiled textures are unmappable. Always put them in VRAM. */
>> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear)
>> ||
>> res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
>> res->domains = RADEON_DOMAIN_VRAM;
>> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
>>  RADEON_FLAG_GTT_WC;
>> }
>>   + /* Only displayable single-sample textures can be shared between
>> +* processes. */
>> +   if (res->b.b.target == PIPE_BUFFER ||
>> +   res->b.b.nr_samples >= 2 ||
>> +   rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY)
>> +   res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
>
>
> We might want to share non-displayable textures at some point for
> performance, right? Will we still be able to flag some textures as
> non-shareable in that case?

Yes if we weren't CPU-bound in 2D acceleration on VI. As long as we
are CPU-bound, GPU optimizations won't probably make much difference.

Marek
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Re: [Mesa-dev] [PATCH 21/22] i965: Drop redundant check for non-tiled depth buffer

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Depth buffers are always Y-tiled. In brw_miptree_choose_tiling()
> driver opts to use linear buffers for small and 1D but this does
> not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT
> are considered first.
>
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c   | 3 +--
>  src/mesa/drivers/dri/i965/gen6_depth_state.c | 3 +--
>  2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 0c43d2b4b2..1e3be784c5 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -383,8 +383,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
> OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
>   (depthbuffer_format << 18) |
>   (BRW_TILEWALK_YMAJOR << 26) |
> - ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
> -  << 27) |
> + (1 << 27) |
>   (depth_surface_type << 29));
>
> if (depth_mt) {
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index 8f05b4cc1a..3e3d2c629b 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -121,8 +121,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>   ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable
> */
>   ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
>   (BRW_TILEWALK_YMAJOR << 26) |
> - ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
> -  << 27) |
> + (1 << 27) |
>   (surftype << 29));
>
> /* 3DSTATE_DEPTH_BUFFER dw2 */
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 20/22] intel/isl/gen4: Represent cube maps with 3D layout

[Jason Ekstrand]

I was sure I'd written this patch at least twice but I can't find it... :-(

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/intel/isl/isl.c | 40 +++-
>  1 file changed, 35 insertions(+), 5 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 12ffe3bb51..90b36c33bc 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -548,7 +548,8 @@ isl_choose_image_alignment_el(const struct isl_device
> *dev,
>  static enum isl_dim_layout
>  isl_surf_choose_dim_layout(const struct isl_device *dev,
> enum isl_surf_dim logical_dim,
> -   enum isl_tiling tiling)
> +   enum isl_tiling tiling,
> +   isl_surf_usage_flags_t usage)
>  {
> /* Sandy bridge needs a special layout for HiZ and stencil. */
> if (ISL_DEV_GEN(dev) == 6 &&
> @@ -584,6 +585,16 @@ isl_surf_choose_dim_layout(const struct isl_device
> *dev,
>switch (logical_dim) {
>case ISL_SURF_DIM_1D:
>case ISL_SURF_DIM_2D:
> + /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
> +  *
> +  * The cube face textures are stored in the same way as 3D
> surfaces
> +  * are stored (see section 6.17.5 for details).  For cube
> surfaces,
> +  * however, the depth is equal to the number of faces (always 6)
> and
> +  * is not reduced for each MIP.
> +  */
> + if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
> +return ISL_DIM_LAYOUT_GEN4_3D;
> +
>   return ISL_DIM_LAYOUT_GEN4_2D;
>case ISL_SURF_DIM_3D:
>   return ISL_DIM_LAYOUT_GEN4_3D;
> @@ -635,8 +646,11 @@ isl_calc_phys_level0_extent_sa(const struct
> isl_device *dev,
>break;
>
> case ISL_SURF_DIM_2D:
> -  assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
> - dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
> +  if (ISL_DEV_GEN(dev) == 4 && (info->usage &
> ISL_SURF_USAGE_CUBE_BIT))
> + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);
> +  else
> + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
> +dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
>
>if (tiling == ISL_TILING_Ys && info->samples > 1)
>   isl_finishme("%s:%s: multisample TileYs layout", __FILE__,
> __func__);
> @@ -952,7 +966,11 @@ isl_calc_phys_total_extent_el_gen4_3d(
> const struct isl_format_layout *fmtl = isl_format_get_layout(info->
> format);
>
> assert(info->samples == 1);
> -   assert(phys_level0_sa->array_len == 1);
> +
> +   if (info->usage & ISL_SURF_USAGE_CUBE_BIT)
> +  assert(phys_level0_sa->array_len == 6);
> +   else
> +  assert(phys_level0_sa->array_len == 1);
>

How about:

if (info->dim != ISL_SURF_DIM_3D) {
   /* PRM quote goes here */
   assert(ISL_DEV_GEN(dev) == 4);
   assert(info->usage & ISL_SURF_USAGE_CUBE);
   assert(phys_level0_sa->array_len == 6);
} else {
   assert(phys_level0_sa->array_len == 1);
}


>
> uint32_t total_w = 0;
> uint32_t total_h = 0;
> @@ -966,6 +984,18 @@ isl_calc_phys_total_extent_el_gen4_3d(
>uint32_t level_h = isl_align_npot(isl_minify(H0, l),
> image_align_sa->h);
>uint32_t level_d = isl_align_npot(isl_minify(D0, l),
> image_align_sa->d);
>
> +  /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
> +   *
> +   * The cube face textures are stored in the same way as 3D surfaces
> +   * are stored (see section 6.17.5 for details).  For cube surfaces,
> +   * however, the depth is equal to the number of faces (always 6) and
> +   * is not reduced for each MIP.
> +   */
> +  if (info->usage & ISL_SURF_USAGE_CUBE_BIT) {
> + assert(ISL_DEV_GEN(dev) == 4);
> + level_d = 6;
> +  }
>

I don't really like using CUBE_BIT here.  I would much rather we do
something like

level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;

where A0 is declared outside the loop as the array length which must be 6.
The align isn't really needed for depth as DALIGN isn't a thing.


> +
>uint32_t max_layers_horiz = MIN(level_d, 1u << l);
>uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
>
> @@ -1427,7 +1457,7 @@ isl_surf_init_s(const struct isl_device *dev,
> isl_tiling_get_info(tiling, fmtl->bpb, _info);
>
> const enum isl_dim_layout dim_layout =
> -  isl_surf_choose_dim_layout(dev, info->dim, tiling);
> +  isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
>
> enum isl_msaa_layout msaa_layout;
> if (!isl_choose_msaa_layout(dev, info, tiling, _layout))
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 13/22] i965/fbo: Add support for isl-based miptrees in rb wrapper

[Kenneth Graunke]

On Tuesday, July 18, 2017 1:46:23 AM PDT Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_fbo.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 1fa40bb5c9..fee4b6fa8c 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -540,6 +540,10 @@ intel_renderbuffer_update_wrapper(struct brw_context 
> *brw,
>irb->layer_count = 1;
> } else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers > 
> 0) {
>irb->layer_count = image->TexObject->NumLayers;
> +   } else if (mt->surf.size > 0) {
> +  irb->layer_count = mt->surf.dim == ISL_SURF_DIM_3D ?
> +minify(mt->surf.logical_level0_px.depth, level) :
> +mt->surf.logical_level0_px.array_len;
> } else {
>irb->layer_count = mt->level[level].depth / layer_multiplier;
> }
> 

Patches 1-13 are:
Reviewed-by: Kenneth Graunke 

I don't really grok some of the rest, and it sounds like Jason's further
in reviewing this than I am, so I'll just let him handle the rest.


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Re: [Mesa-dev] [RFC PATCH] radeonsi: set a per-buffer flag that disables inter-process sharing (v2)

[Michel Dänzer]

On 18/07/17 04:08 PM, Marek Olšák wrote:

From: Marek Olšák 

For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.

v2: It shouldn't crash anymore, but the kernel will reject the new flag.
---
  src/gallium/drivers/radeon/r600_buffer_common.c |  7 +
  src/gallium/drivers/radeon/radeon_winsys.h  | 20 +++---
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 36 -
  src/gallium/winsys/radeon/drm/radeon_drm_bo.c   | 27 +++
  4 files changed, 62 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index dd1c209..2747ac4 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -160,20 +160,27 @@ void r600_init_resource_fields(struct r600_common_screen 
*rscreen,
}
  
  	/* Tiled textures are unmappable. Always put them in VRAM. */

if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 RADEON_FLAG_GTT_WC;
}
  
+	/* Only displayable single-sample textures can be shared between

+* processes. */
+   if (res->b.b.target == PIPE_BUFFER ||
+   res->b.b.nr_samples >= 2 ||
+   rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY)
+   res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;


We might want to share non-displayable textures at some point for 
performance, right? Will we still be able to flag some textures as 
non-shareable in that case?




diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 97bbe23..06b8198 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -31,20 +31,24 @@
  
  #include "amdgpu_cs.h"
  
  #include "os/os_time.h"

  #include "state_tracker/drm_driver.h"
  #include 
  #include 
  #include 
  #include 
  
+#ifndef AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING

+#define AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING (1 << 6)
+#endif


I advise against the #ifndef check for this kind of thing, because it 
prevents the preprocessor from warning about conflicting definitions.



--
Earthling Michel Dänzer|  http://www.amd.com
Libre software enthusiast  |Mesa and X developer
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Re: [Mesa-dev] [PATCH 08/22] i965/wm: Prepare image surfaces for isl based

[Kenneth Graunke]

On Tuesday, July 18, 2017 1:46:18 AM PDT Topi Pohjolainen wrote:
> There is a functional change: Before update_image_surface() didn't
> shift the number of layers for 3D, now it does like
> update_texture_image_param() did.
> 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 +++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index ab6b9cdd29..a8c40d54d8 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1632,6 +1632,23 @@ update_buffer_image_param(struct brw_context *brw,
> param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
>  }
>  
> +static unsigned
> +get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
> + unsigned level)
> +{
> +   if (target == GL_TEXTURE_CUBE_MAP)
> +  return 6;
> +
> +   if (mt->surf.size > 0) {
> +  return target == GL_TEXTURE_3D ?
> + minify(mt->surf.logical_level0_px.depth, level) :
> + mt->surf.logical_level0_px.array_len;
> +   }
> +
> +   return target == GL_TEXTURE_3D ?
> +  minify(mt->logical_depth0, level) : mt->logical_depth0;
> +}
> +
>  static void
>  update_image_surface(struct brw_context *brw,
>   struct gl_image_unit *u,
> @@ -1660,9 +1677,8 @@ update_image_surface(struct brw_context *brw,
>} else {
>   struct intel_texture_object *intel_obj = intel_texture_object(obj);
>   struct intel_mipmap_tree *mt = intel_obj->mt;
> - const unsigned num_layers = (!u->Layered ? 1 :
> -  obj->Target == GL_TEXTURE_CUBE_MAP ? 6 
> :
> -  mt->logical_depth0);
> + const unsigned num_layers = u->Layered ?
> +get_image_num_layers(mt, obj->Target, u->Level) : 1;
>  
>   struct isl_view view = {
>  .format = format,
> 

The 3D change here looks like a (good) bug fix...it might make sense to
separate that and send it to -stable...

Patches 1-8 are:
Reviewed-by: Kenneth Graunke 

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Re: [Mesa-dev] [PATCH 18/22] i965/miptree: Prepare aux state map for isl based

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 ++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index d96f5c7938..fafd0c1e59 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -696,8 +696,14 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
> const uint32_t levels = mt->last_level + 1;
>
> uint32_t total_slices = 0;
> -   for (uint32_t level = 0; level < levels; level++)
> -  total_slices += mt->level[level].depth;
> +   for (uint32_t level = 0; level < levels; level++) {
> +  if (mt->surf.size > 0)
> + total_slices += (mt->surf.dim == ISL_SURF_DIM_3D ?
> + minify(mt->surf.phys_level0_sa.depth,
> level) :
> + mt->surf.phys_level0_sa.array_len);
> +  else
> + total_slices += mt->level[level].depth;
>

The intention was always for the state map to use logical layers, not
physical.  There's no point in tracking fast-clear state for an individual
sample.  That said, that may not actually be quite correct with the current
implementation.

--Jason


> +   }
>
> const size_t per_level_array_size = levels * sizeof(enum isl_aux_state
> *);
>
> @@ -715,7 +721,16 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
> enum isl_aux_state *s = data + per_level_array_size;
> for (uint32_t level = 0; level < levels; level++) {
>per_level_arr[level] = s;
> -  for (uint32_t a = 0; a < mt->level[level].depth; a++)
> +
> +  unsigned level_depth;
> +  if (mt->surf.size > 0)
> + level_depth = mt->surf.dim == ISL_SURF_DIM_3D ?
> +  minify(mt->surf.phys_level0_sa.depth, level) :
> +  mt->surf.phys_level0_sa.array_len;
> +  else
> + level_depth = mt->level[level].depth;
> +
> +  for (uint32_t a = 0; a < level_depth; a++)
>   *(s++) = initial;
> }
> assert((void *)s == data + total_size);
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 16/22] i965/miptree: Represent w-tiled stencil surfaces with isl

[Jason Ekstrand]

Over-all, this looks fine.  However, I'd like to see a reply to my comments
on patch 4 before I give it a review.

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/gen7_misc_state.c   | 20 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c  | 26 ++
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 38
> ---
>  3 files changed, 38 insertions(+), 46 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> index 43422900e2..c0cb7470bf 100644
> --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> @@ -83,7 +83,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
>break;
> case GL_TEXTURE_3D:
>assert(mt);
> -  depth = MAX2(mt->logical_depth0, 1);
> +  depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
> +  MAX2(mt->logical_depth0, 1);
>/* fallthrough */
> default:
>surftype = translate_tex_target(gl_target);
> @@ -94,7 +95,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
>
> lod = irb ? irb->mt_level - irb->mt->first_level : 0;
>
> -   if (mt) {
> +   if (mt && mt->surf.size > 0) {
> +  width = mt->surf.logical_level0_px.width;
> +  height = mt->surf.logical_level0_px.height;
> +   } else if (mt) {
>width = mt->logical_width0;
>height = mt->logical_height0;
> }
> @@ -170,19 +174,9 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
>
>BEGIN_BATCH(3);
>OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
> -  /* The stencil buffer has quirky pitch requirements.  From the
> -   * Sandybridge PRM, Volume 2 Part 1, page 329
> (3DSTATE_STENCIL_BUFFER
> -   * dword 1 bits 16:0 - Surface Pitch):
> -   *
> -   *The pitch must be set to 2x the value computed based on
> width, as
> -   *the stencil buffer is stored with two rows interleaved.
> -   *
> -   * While the Ivybridge PRM lacks this comment, the BSpec contains
> the
> -   * same text, and experiments indicate that this is necessary.
> -   */
>OUT_BATCH(enabled |
>  mocs << 25 |
> -   (2 * stencil_mt->surf.row_pitch - 1));
> +   (stencil_mt->surf.row_pitch - 1));
>OUT_RELOC(stencil_mt->bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> 0);
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 9cb0d07688..c934d0d21a 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -111,25 +111,11 @@ emit_depth_packets(struct brw_context *brw,
> } else {
>BEGIN_BATCH(5);
>OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
> -  /* The stencil buffer has quirky pitch requirements.  From the
> Graphics
> -   * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil
> Processing
> -   * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
> -   * field "Surface Pitch":
> -   *
> -   *The pitch must be set to 2x the value computed based on
> width, as
> -   *the stencil buffer is stored with two rows interleaved.
> -   *
> -   * (Note that it is not 100% clear whether this intended to apply to
> -   * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which
> would
> -   * imply that it doesn't), however the comment appears on a
> "DevIVB+"
> -   * page (which would imply that it does).  Experiments with the
> hardware
> -   * indicate that it does.
> -   */
>OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
> -(2 * stencil_mt->surf.row_pitch - 1));
> +(stencil_mt->surf.row_pitch - 1));
>OUT_RELOC64(stencil_mt->bo,
>I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> -  OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
> +  OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
>ADVANCE_BATCH();
> }
>
> @@ -189,7 +175,8 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
>break;
> case GL_TEXTURE_3D:
>assert(mt);
> -  depth = MAX2(mt->logical_depth0, 1);
> +  depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
> +  MAX2(mt->logical_depth0, 1);
>surftype = translate_tex_target(gl_target);
>break;
> case GL_TEXTURE_1D_ARRAY:
> @@ -212,7 +199,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
>
> lod = irb ? irb->mt_level - irb->mt->first_level : 0;
>
> -   if (mt) {
> +   if (mt && mt->surf.size > 0) {
> +  width = mt->surf.logical_level0_px.width;
> +  

Re: [Mesa-dev] [PATCH 15/22] i965/miptree: Prepare compressed offsets for isl based

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index a0b129adb4..1b8c0da80d 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1462,6 +1462,15 @@ intel_miptree_get_image_offset(const struct
> intel_mipmap_tree *mt,
>isl_surf_get_image_offset_sa(>surf, level, slice, z,
> _offset_sa, _offset_sa);
>
> +  /* In case of compressed formats offsets are expected as blocks. */
> +  if (mt->compressed) {
> + const struct isl_format_layout *fmtl =
> +isl_format_get_layout(mt->surf.format);
> +
> + x_offset_sa /= fmtl->bw;
> + y_offset_sa /= fmtl->bh;
> +  }
>

I think what you probably want is to just to switch to
isl_surf_get_image_offset_el()

--Jason


> +
>*x = x_offset_sa;
>*y = y_offset_sa;
>return;
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 14/22] i965/miptree: Add support for imported bo offsets for isl based

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 879036ce77..a0b129adb4 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1435,9 +1435,22 @@ intel_miptree_get_image_offset(const struct
> intel_mipmap_tree *mt,
>GLuint level, GLuint slice,
>GLuint *x, GLuint *y)
>  {
> +   if (level == 0 && slice == 0) {
> +  *x = mt->level[0].level_x;
> +  *y = mt->level[0].level_y;
> +  return;
> +   }
> +
> if (mt->surf.size > 0) {
>uint32_t x_offset_sa, y_offset_sa;
>
> +  /* Miptree itself can have an offset only if it represents a single
> +   * slice in an imported buffer object.
> +   * See intel_miptree_create_for_dri_image().
> +   */
> +  assert(mt->level[0].level_x == 0);
> +  assert(mt->level[0].level_y == 0);
> +
>/* Given level is relative to level zero while the miptree may be
> * represent just a subset of all levels starting from
> 'first_level'.
> */
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 13/22] i965/fbo: Add support for isl-based miptrees in rb wrapper

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_fbo.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 1fa40bb5c9..fee4b6fa8c 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -540,6 +540,10 @@ intel_renderbuffer_update_wrapper(struct brw_context
> *brw,
>irb->layer_count = 1;
> } else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers
> > 0) {
>irb->layer_count = image->TexObject->NumLayers;
> +   } else if (mt->surf.size > 0) {
> +  irb->layer_count = mt->surf.dim == ISL_SURF_DIM_3D ?
> +minify(mt->surf.logical_level0_px.depth,
> level) :
> +mt->surf.logical_level0_px.array_len;
> } else {
>irb->layer_count = mt->level[level].depth / layer_multiplier;
> }
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 12/22] i965: Prepare image setup from miptree for isl based

[Jason Ekstrand]

9-12  Reviewed-by: Jason Ekstrand 

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_screen.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> b/src/mesa/drivers/dri/i965/intel_screen.c
> index 7a92ef601b..9c74d2aa54 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -412,8 +412,15 @@ intel_setup_image_from_mipmap_tree(struct
> brw_context *brw, __DRIimage *image,
>
> intel_miptree_check_level_layer(mt, level, zoffset);
>
> -   image->width = minify(mt->physical_width0, level - mt->first_level);
> -   image->height = minify(mt->physical_height0, level - mt->first_level);
> +   if (mt->surf.size > 0) {
> +  image->width = minify(mt->surf.phys_level0_sa.width,
> +level - mt->first_level);
> +  image->height = minify(mt->surf.phys_level0_sa.height,
> + level - mt->first_level);
> +   } else {
> +  image->width = minify(mt->physical_width0, level - mt->first_level);
> +  image->height = minify(mt->physical_height0, level -
> mt->first_level);
> +   }
> image->pitch = mt->surf.row_pitch;
>
> image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 19/20] nir: Optimize find_lsb/imsb/umsb error checks

[Connor Abbott]

Reviewed-by: Connor Abbott 

On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner  wrote:
> Two of the ARB_shader_ballot piglit tests hit the find_lsb case,
> removing some of the noise allowed me to better debug the test when it
> was failing.
> ---
>  src/compiler/nir/nir_opt_algebraic.py | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py 
> b/src/compiler/nir/nir_opt_algebraic.py
> index fe6e33d313..df5854270c 100644
> --- a/src/compiler/nir/nir_opt_algebraic.py
> +++ b/src/compiler/nir/nir_opt_algebraic.py
> @@ -357,6 +357,17 @@ optimizations = [
> (('~fadd', '#a', ('fadd', b, '#c')), ('fadd', ('fadd', a, c), b)),
> (('iadd', '#a', ('iadd', b, '#c')), ('iadd', ('iadd', a, c), b)),
>
> +   # By definition...
> +   (('bcsel', ('ige', ('find_lsb', a), 0), ('find_lsb', a), -1), 
> ('find_lsb', a)),
> +   (('bcsel', ('ige', ('ifind_msb', a), 0), ('ifind_msb', a), -1), 
> ('ifind_msb', a)),
> +   (('bcsel', ('ige', ('ufind_msb', a), 0), ('ufind_msb', a), -1), 
> ('ufind_msb', a)),
> +
> +   (('bcsel', ('ine', a, 0), ('find_lsb', a), -1), ('find_lsb', a)),
> +   (('bcsel', ('ine', a, 0), ('ifind_msb', a), -1), ('ifind_msb', a)),
> +   (('bcsel', ('ine', a, 0), ('ufind_msb', a), -1), ('ufind_msb', a)),
> +
> +   (('bcsel', ('ine', a, -1), ('ifind_msb', a), -1), ('ifind_msb', a)),
> +
> # Misc. lowering
> (('fmod@32', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
> 'options->lower_fmod32'),
> (('fmod@64', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
> 'options->lower_fmod64'),
> --
> 2.13.0
>
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[Mesa-dev] [PATCH mesa 4/5] wayland-egl: Make wl_egl_window a versioned struct

[Miguel A. Vico]

We need wl_egl_window to be a versioned struct in order to keep track of
ABI changes.

This change makes the first member of wl_egl_window the version number.

An heuristic in the wayland driver is added so that we don't break
backwards compatibility:

 - If the first field (version) is an actual pointer, it is an old
   implementation of wl_egl_window, and version points to the wl_surface
   proxy.

 - Else, the first field is the version number, and we have
   wl_egl_window::surface pointing to the wl_surface proxy.

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 src/egl/drivers/dri2/platform_wayland.c| 13 -
 src/egl/wayland/wayland-egl/wayland-egl-priv.h |  6 +-
 src/egl/wayland/wayland-egl/wayland-egl.c  |  6 +-
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index ee68284217..0f0a12fd80 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -41,6 +41,7 @@
 #include "egl_dri2.h"
 #include "egl_dri2_fallbacks.h"
 #include "loader.h"
+#include "eglglobals.h"
 
 #include 
 #include "wayland-drm-client-protocol.h"
@@ -100,6 +101,16 @@ destroy_window_callback(void *data)
dri2_surf->wl_win = NULL;
 }
 
+static struct wl_surface *
+get_wl_surface_proxy(struct wl_egl_window *window)
+{
+   if (_eglPointerIsDereferencable((void *)(window->version))) {
+  /* window->version points to actual wl_surface data */
+  return wl_proxy_create_wrapper((void *)(window->version));
+   }
+   return wl_proxy_create_wrapper(window->surface);
+}
+
 /**
  * Called via eglCreateWindowSurface(), drv->API.CreateWindowSurface().
  */
@@ -171,7 +182,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay 
*disp,
wl_proxy_set_queue((struct wl_proxy *)dri2_surf->wl_dpy_wrapper,
   dri2_surf->wl_queue);
 
-   dri2_surf->wl_surface_wrapper = wl_proxy_create_wrapper(window->surface);
+   dri2_surf->wl_surface_wrapper = get_wl_surface_proxy(window);
if (!dri2_surf->wl_surface_wrapper) {
   _eglError(EGL_BAD_ALLOC, "dri2_create_surface");
   goto cleanup_drm;
diff --git a/src/egl/wayland/wayland-egl/wayland-egl-priv.h 
b/src/egl/wayland/wayland-egl/wayland-egl-priv.h
index 92c31d9454..3b59908cc1 100644
--- a/src/egl/wayland/wayland-egl/wayland-egl-priv.h
+++ b/src/egl/wayland/wayland-egl/wayland-egl-priv.h
@@ -41,8 +41,10 @@
 extern "C" {
 #endif
 
+#define WL_EGL_WINDOW_VERSION 3
+
 struct wl_egl_window {
-   struct wl_surface *surface;
+   const intptr_t version;
 
int width;
int height;
@@ -55,6 +57,8 @@ struct wl_egl_window {
void *private;
void (*resize_callback)(struct wl_egl_window *, void *);
void (*destroy_window_callback)(void *);
+
+   struct wl_surface *surface;
 };
 
 #ifdef  __cplusplus
diff --git a/src/egl/wayland/wayland-egl/wayland-egl.c 
b/src/egl/wayland/wayland-egl/wayland-egl.c
index 4a4701a2de..02645549e0 100644
--- a/src/egl/wayland/wayland-egl/wayland-egl.c
+++ b/src/egl/wayland/wayland-egl/wayland-egl.c
@@ -28,6 +28,7 @@
  */
 
 #include 
+#include 
 
 #include 
 #include "wayland-egl.h"
@@ -54,6 +55,7 @@ WL_EGL_EXPORT struct wl_egl_window *
 wl_egl_window_create(struct wl_surface *surface,
 int width, int height)
 {
+   struct wl_egl_window _INIT_ = { .version = WL_EGL_WINDOW_VERSION };
struct wl_egl_window *egl_window;
 
if (width <= 0 || height <= 0)
@@ -63,6 +65,8 @@ wl_egl_window_create(struct wl_surface *surface,
if (!egl_window)
return NULL;
 
+   memcpy(egl_window, &_INIT_, sizeof *egl_window);
+
egl_window->surface = surface;
egl_window->private = NULL;
egl_window->resize_callback = NULL;
@@ -70,7 +74,7 @@ wl_egl_window_create(struct wl_surface *surface,
wl_egl_window_resize(egl_window, width, height, 0, 0);
egl_window->attached_width  = 0;
egl_window->attached_height = 0;
-   
+
return egl_window;
 }
 
-- 
2.12.2

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[Mesa-dev] [PATCH mesa 5/5] wayland-egl: Update ABI checker

[Miguel A. Vico]

This change updates wayland-egl-abi-check.c with the latest changes to
wl_egl_window.

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 .../wayland/wayland-egl/wayland-egl-abi-check.c| 78 ++
 1 file changed, 65 insertions(+), 13 deletions(-)

diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
index 1962f05850..6bdd71b6e0 100644
--- a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
+++ b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
@@ -31,7 +31,28 @@
  * DO NOT EVER CHANGE!
  */
 
+/* From: a2ab5c2588 - Miguel A. Vico : wayland-egl: Make wl_egl_window a 
versioned struct */
+#define WL_EGL_WINDOW_VERSION_v3 3
+struct wl_egl_window_v3 {
+const intptr_t version;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+
+void *private;
+void (*resize_callback)(struct wl_egl_window *, void *);
+void (*destroy_window_callback)(void *);
+
+struct wl_surface *surface;
+};
+
 /* From: 690ead4a13 - Stencel, Joanna : egl/wayland-egl: Fix for segfault in 
dri2_wl_destroy_surface. */
+#define WL_EGL_WINDOW_VERSION_v2 2
 struct wl_egl_window_v2 {
 struct wl_surface *surface;
 
@@ -123,6 +144,20 @@ struct wl_egl_window_v0 {
 }  
 \
 } while (0)
 
+#define CHECK_VERSION(A_VER, B_VER, MATCH) 
 \
+do {   
 \
+if (((MATCH)  && (WL_EGL_WINDOW_VERSION ## A_VER) !=   
 \
+ (WL_EGL_WINDOW_VERSION ## B_VER)) ||  
 \
+(!(MATCH) && (WL_EGL_WINDOW_VERSION ## A_VER) >=   
 \
+ (WL_EGL_WINDOW_VERSION ## B_VER))) {  
 \
+printf("Backards incompatible change detected!\n   "   
 \
+   "WL_EGL_WINDOW_VERSION" #A_VER " %s "   
 \
+   "WL_EGL_WINDOW_VERSION" #B_VER "\n",
 \
+   ((MATCH) ? "!=" : ">="));   
 \
+return 1;  
 \
+}  
 \
+} while (0)
+
 int main(int argc, char **argv)
 {
 /* Check wl_egl_window_v1 ABI against wl_egl_window_v0 */
@@ -149,19 +184,36 @@ int main(int argc, char **argv)
 
 CHECK_SIZE(_v1, _v2, FALSE);
 
-/* Check wl_egl_window ABI against wl_egl_window_v2 */
-CHECK_MEMBER(_v2,, surface, surface);
-CHECK_MEMBER(_v2,, width,   width);
-CHECK_MEMBER(_v2,, height,  height);
-CHECK_MEMBER(_v2,, dx,  dx);
-CHECK_MEMBER(_v2,, dy,  dy);
-CHECK_MEMBER(_v2,, attached_width,  attached_width);
-CHECK_MEMBER(_v2,, attached_height, attached_height);
-CHECK_MEMBER(_v2,, private, private);
-CHECK_MEMBER(_v2,, resize_callback, resize_callback);
-CHECK_MEMBER(_v2,, destroy_window_callback, destroy_window_callback);
-
-CHECK_SIZE(_v2,, TRUE);
+/* Check wl_egl_window_v3 ABI against wl_egl_window_v2 */
+CHECK_MEMBER(_v2, _v3, surface, version);
+CHECK_MEMBER(_v2, _v3, width,   width);
+CHECK_MEMBER(_v2, _v3, height,  height);
+CHECK_MEMBER(_v2, _v3, dx,  dx);
+CHECK_MEMBER(_v2, _v3, dy,  dy);
+CHECK_MEMBER(_v2, _v3, attached_width,  attached_width);
+CHECK_MEMBER(_v2, _v3, attached_height, attached_height);
+CHECK_MEMBER(_v2, _v3, private, private);
+CHECK_MEMBER(_v2, _v3, resize_callback, resize_callback);
+CHECK_MEMBER(_v2, _v3, destroy_window_callback, destroy_window_callback);
+
+CHECK_SIZE   (_v2, _v3, FALSE);
+CHECK_VERSION(_v2, _v3, FALSE);
+
+/* Check wl_egl_window ABI against wl_egl_window_v3 */
+CHECK_MEMBER(_v3,, version, version);
+CHECK_MEMBER(_v3,, width,   width);
+CHECK_MEMBER(_v3,, height,  height);
+CHECK_MEMBER(_v3,, dx,  dx);
+CHECK_MEMBER(_v3,, dy,  dy);
+CHECK_MEMBER(_v3,, attached_width,  attached_width);
+CHECK_MEMBER(_v3,, attached_height, attached_height);
+CHECK_MEMBER(_v3,, private, private);
+CHECK_MEMBER(_v3,, resize_callback, resize_callback);
+CHECK_MEMBER(_v3,, destroy_window_callback, destroy_window_callback);
+CHECK_MEMBER(_v3,, surface, surface);
+
+CHECK_SIZE  

[Mesa-dev] [PATCH mesa 3/5] egl: Fix _eglPointerIsDereferencable() to ignore page residency

[Miguel A. Vico]

mincore() returns 0 on success, and -1 on failure.  The last parameter
is a vector of bytes with one entry for each page queried.  mincore
returns page residency information in the first bit of each byte in the
vector.

Residency doesn't actually matter when determining whether a pointer is
dereferenceable, so the output vector can be ignored.  What matters is
whether mincore succeeds. See:

  http://man7.org/linux/man-pages/man2/mincore.2.html

Signed-off-by: Miguel A. Vico 
---
 src/egl/main/eglglobals.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index 6fdc6c31ce..9071226618 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -168,7 +168,18 @@ _eglPointerIsDereferencable(void *p)
   return EGL_FALSE;
}
 
-   return (valid & 0x01) == 0x01;
+   /* mincore() returns 0 on success, and -1 on failure.  The last parameter
+* is a vector of bytes with one entry for each page queried.  mincore
+* returns page residency information in the first bit of each byte in the
+* vector.
+*
+* Residency doesn't actually matter when determining whether a pointer is
+* dereferenceable, so the output vector can be ignored.  What matters is
+* whether mincore succeeds. See:
+*
+*   http://man7.org/linux/man-pages/man2/mincore.2.html
+*/
+   return EGL_TRUE;
 #else
return p != NULL;
 #endif
-- 
2.12.2

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[Mesa-dev] [PATCH mesa 1/5] wayland-egl: Add wl_egl_window ABI checker

[Miguel A. Vico]

Add a small ABI checker for wl_egl_window so that we can check for
backwards incompatible changes at 'make check' time.

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 src/egl/wayland/wayland-egl/Makefile.am|  10 +-
 .../wayland/wayland-egl/wayland-egl-abi-check.c| 167 +
 2 files changed, 176 insertions(+), 1 deletion(-)
 create mode 100644 src/egl/wayland/wayland-egl/wayland-egl-abi-check.c

diff --git a/src/egl/wayland/wayland-egl/Makefile.am 
b/src/egl/wayland/wayland-egl/Makefile.am
index 8c45e8e26d..74a52027c6 100644
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ b/src/egl/wayland/wayland-egl/Makefile.am
@@ -14,7 +14,15 @@ libwayland_egl_la_LDFLAGS = \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
 
-TESTS = wayland-egl-symbols-check
+TESTS =
+check_PROGRAMS =
+
+TESTS += wayland-egl-symbols-check
 EXTRA_DIST = wayland-egl-symbols-check
 
+TESTS += wayland-egl-abi-check
+check_PROGRAMS += wayland-egl-abi-check
+
+wayland_egl_abi_check_SOURCES = wayland-egl-abi-check.c
+
 include $(top_srcdir)/install-lib-links.mk
diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
new file mode 100644
index 00..1962f05850
--- /dev/null
+++ b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include  // offsetof
+#include   // printf
+
+#include "wayland-egl-priv.h" // Current struct wl_egl_window implementation
+
+/*
+ * Following are previous implementations of wl_egl_window.
+ *
+ * DO NOT EVER CHANGE!
+ */
+
+/* From: 690ead4a13 - Stencel, Joanna : egl/wayland-egl: Fix for segfault in 
dri2_wl_destroy_surface. */
+struct wl_egl_window_v2 {
+struct wl_surface *surface;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+
+void *private;
+void (*resize_callback)(struct wl_egl_window *, void *);
+void (*destroy_window_callback)(void *);
+};
+
+/* From: ca3ed3e024 - Ander Conselvan de Oliveira : egl/wayland: Don't 
invalidate drawable on swap buffers */
+struct wl_egl_window_v1 {
+struct wl_surface *surface;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+
+void *private;
+void (*resize_callback)(struct wl_egl_window *, void *);
+};
+
+/* From: 214fc6e850 - Benjamin Franzke : egl: Implement libwayland-egl */
+struct wl_egl_window_v0 {
+struct wl_surface *surface;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+};
+
+
+/* This program checks we keep a backwards-compatible struct wl_egl_window
+ * definition whenever it is modified in wayland-egl-priv.h.
+ *
+ * The previous definition should be added above as a new struct
+ * wl_egl_window_vN, and the appropriate checks should be added below
+ */
+
+#define TRUE  1
+#define FALSE 0
+
+#define MEMBER_SIZE(TYPE, MEMBER) sizeof(((TYPE *)0)->MEMBER)
+
+#define CHECK_MEMBER(A_VER, B_VER, A_MEMBER, B_MEMBER) 
 \
+do {   
 \
+if (offsetof(struct wl_egl_window ## A_VER, A_MEMBER) !=   
 \
+offsetof(struct wl_egl_window ## B_VER, B_MEMBER)) {   
 \
+printf("Backards incompatible change detected!\n   "   
 \
+   "offsetof(struct wl_egl_window" #A_VER "::" #A_MEMBER ") != 
"\
+   "offsetof(struct wl_egl_window" #B_VER "::" #B_MEMBER 
")\n");\
+return 1;  
 \
+}   

[Mesa-dev] [PATCH mesa 2/5] egl: Move _eglPointerIsDereferencable() to eglglobals.[ch]

[Miguel A. Vico]

More _eglPointerIsDereferencable() to eglglobals.[ch] and make it a
non-static function so it can be used out of egldisplay.c

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 src/egl/main/egldisplay.c | 33 -
 src/egl/main/eglglobals.c | 31 +++
 src/egl/main/eglglobals.h |  6 ++
 3 files changed, 37 insertions(+), 33 deletions(-)

diff --git a/src/egl/main/egldisplay.c b/src/egl/main/egldisplay.c
index 7aaab3c2c9..690728d2f7 100644
--- a/src/egl/main/egldisplay.c
+++ b/src/egl/main/egldisplay.c
@@ -49,10 +49,6 @@
 #include "eglsync.h"
 
 /* Includes for _eglNativePlatformDetectNativeDisplay */
-#ifdef HAVE_MINCORE
-#include 
-#include 
-#endif
 #ifdef HAVE_WAYLAND_PLATFORM
 #include 
 #endif
@@ -106,35 +102,6 @@ _eglGetNativePlatformFromEnv(void)
 
 
 /**
- * Perform validity checks on a generic pointer.
- */
-static EGLBoolean
-_eglPointerIsDereferencable(void *p)
-{
-#ifdef HAVE_MINCORE
-   uintptr_t addr = (uintptr_t) p;
-   unsigned char valid = 0;
-   const long page_size = getpagesize();
-
-   if (p == NULL)
-  return EGL_FALSE;
-
-   /* align addr to page_size */
-   addr &= ~(page_size - 1);
-
-   if (mincore((void *) addr, page_size, ) < 0) {
-  _eglLog(_EGL_DEBUG, "mincore failed: %m");
-  return EGL_FALSE;
-   }
-
-   return (valid & 0x01) == 0x01;
-#else
-   return p != NULL;
-#endif
-}
-
-
-/**
  * Try detecting native platform with the help of native display 
characteristcs.
  */
 static _EGLPlatformType
diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index baf96bb1ec..6fdc6c31ce 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -37,6 +37,12 @@
 #include "eglglobals.h"
 #include "egldisplay.h"
 #include "egldriver.h"
+#include "egllog.h"
+
+#ifdef HAVE_MINCORE
+#include 
+#include 
+#endif
 
 
 static mtx_t _eglGlobalMutex = _MTX_INITIALIZER_NP;
@@ -142,3 +148,28 @@ _eglGetClientExtensionString(void)
mtx_unlock(_eglGlobal.Mutex);
return ret;
 }
+
+EGLBoolean
+_eglPointerIsDereferencable(void *p)
+{
+#ifdef HAVE_MINCORE
+   uintptr_t addr = (uintptr_t) p;
+   unsigned char valid = 0;
+   const long page_size = getpagesize();
+
+   if (p == NULL)
+  return EGL_FALSE;
+
+   /* align addr to page_size */
+   addr &= ~(page_size - 1);
+
+   if (mincore((void *) addr, page_size, ) < 0) {
+  _eglLog(_EGL_DEBUG, "mincore failed: %m");
+  return EGL_FALSE;
+   }
+
+   return (valid & 0x01) == 0x01;
+#else
+   return p != NULL;
+#endif
+}
diff --git a/src/egl/main/eglglobals.h b/src/egl/main/eglglobals.h
index c6ef59d482..6655ccab65 100644
--- a/src/egl/main/eglglobals.h
+++ b/src/egl/main/eglglobals.h
@@ -87,4 +87,10 @@ static inline unsigned int DebugBitFromType(EGLenum type)
 extern const char *
 _eglGetClientExtensionString(void);
 
+/**
+ * Perform validity checks on a generic pointer.
+ */
+extern EGLBoolean
+_eglPointerIsDereferencable(void *p);
+
 #endif /* EGLGLOBALS_INCLUDED */
-- 
2.12.2

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[Mesa-dev] [PATCH mesa 0/5] egl/wayland: Make wl_egl_window a versioned struct

[Miguel A. Vico]

Although we've always made backwards compatible changes to wl_egl_window, we
are lacking of a versioning mechanism for EGL drivers that take a native
wl_egl_window to check what set of features are exposed/available by the given
struct.

This series of patches aim to make wl_egl_window a versioned struct in a
backwards compatible way.

Along the way, a wl_egl_window ABI checker program has been added that runs
at 'make check' time.

Also, _eglPointerIsDereferencable() is fixed to return whether is
dereferencable, regardless of memory residency.

Thanks,
Miguel.

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Re: [Mesa-dev] [PATCH 08/22] i965/wm: Prepare image surfaces for isl based

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> There is a functional change: Before update_image_surface() didn't
> shift the number of layers for 3D, now it does like
> update_texture_image_param() did.
>

I've got a patch in one of my trees to fix this same bug.

5-8 are Reviewed-by: Jason Ekstrand 


> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22
> +++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index ab6b9cdd29..a8c40d54d8 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1632,6 +1632,23 @@ update_buffer_image_param(struct brw_context *brw,
> param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
>  }
>
> +static unsigned
> +get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
> + unsigned level)
> +{
> +   if (target == GL_TEXTURE_CUBE_MAP)
> +  return 6;
> +
> +   if (mt->surf.size > 0) {
> +  return target == GL_TEXTURE_3D ?
> + minify(mt->surf.logical_level0_px.depth, level) :
> + mt->surf.logical_level0_px.array_len;
> +   }
> +
> +   return target == GL_TEXTURE_3D ?
> +  minify(mt->logical_depth0, level) : mt->logical_depth0;
> +}
> +
>  static void
>  update_image_surface(struct brw_context *brw,
>   struct gl_image_unit *u,
> @@ -1660,9 +1677,8 @@ update_image_surface(struct brw_context *brw,
>} else {
>   struct intel_texture_object *intel_obj =
> intel_texture_object(obj);
>   struct intel_mipmap_tree *mt = intel_obj->mt;
> - const unsigned num_layers = (!u->Layered ? 1 :
> -  obj->Target == GL_TEXTURE_CUBE_MAP
> ? 6 :
> -  mt->logical_depth0);
> + const unsigned num_layers = u->Layered ?
> +get_image_num_layers(mt, obj->Target, u->Level) : 1;
>
>   struct isl_view view = {
>  .format = format,
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 04/22] i965/miptree: Switch to isl_surf::row_pitch

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c   |  2 +-
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
>  src/mesa/drivers/dri/i965/gen6_depth_state.c |  2 +-
>  src/mesa/drivers/dri/i965/gen7_misc_state.c  |  4 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c |  4 +-
>  src/mesa/drivers/dri/i965/intel_blit.c   | 13 +++---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 54
> +---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 11 -
>  src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |  2 +-
>  src/mesa/drivers/dri/i965/intel_pixel_read.c |  2 +-
>  src/mesa/drivers/dri/i965/intel_screen.c |  4 +-
>  src/mesa/drivers/dri/i965/intel_tex_image.c  |  8 ++--
>  src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  2 +-
>  13 files changed, 52 insertions(+), 58 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index b0e63347ad..0c43d2b4b2 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -380,7 +380,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
>
> BEGIN_BATCH(len);
> OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
> -   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> +   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
>   (depthbuffer_format << 18) |
>   (BRW_TILEWALK_YMAJOR << 26) |
>   ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 5e4b4d626e..ab6b9cdd29 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1034,7 +1034,7 @@ gen4_update_renderbuffer_surface(struct brw_context
> *brw,
>   (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
>
> surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) |
> - (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
> + (mt->surf.row_pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
>
> surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index e042fc747e..8f05b4cc1a 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -116,7 +116,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
> OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
>
> /* 3DSTATE_DEPTH_BUFFER dw1 */
> -   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> +   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
>   (depthbuffer_format << 18) |
>   ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable
> */
>   ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> index 6c69fa8ba5..43422900e2 100644
> --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> @@ -105,7 +105,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
>
> /* 3DSTATE_DEPTH_BUFFER dw1 */
> -   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> +   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
>   (depthbuffer_format << 18) |
>   ((hiz ? 1 : 0) << 22) |
>   ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
> @@ -182,7 +182,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> */
>OUT_BATCH(enabled |
>  mocs << 25 |
> -   (2 * stencil_mt->pitch - 1));
> +   (2 * stencil_mt->surf.row_pitch - 1));
>

As with other patches, is the objective simply to switch fields or are we
also switching to the semantics of the ISL field?  If we're also switching
semantics (which is what I'd do personally), then this shouldn't be *2
anymore.  Looking through this patch, you appear to have a mix of ISL and
miptree semantics.


>OUT_RELOC(stencil_mt->bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> 0);
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 52c6dd0787..9cb0d07688 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -67,7 +67,7 @@ emit_depth_packets(struct brw_context *brw,
>   (stencil_mt != NULL && stencil_writable) << 27 |
>   (hiz ? 1 : 0) << 22 |
>   depthbuffer_format << 18 

Re: [Mesa-dev] [PATCH 1.2/8] spirv: Generate spirv_info.c

[Dylan Baker]

Quoting Jason Ekstrand (2017-07-17 10:42:05)
> Generally available things tend to be painful in Python because you have to 
> set
> the python path if you ever want to import anything that isn't in your
> directory.  That doesn't mean we shouldn't do it, just that the pain may be 
> too
> high.  Also, having a copyright block at the top of the file as suggested 
> means
> that the python file still has a copyright block.

I agree about the pain of PYTHONPATH, but putting an assignment before imports
is a really, really, really, really bad idea. In python import is an overloaded
keyword, it does two related things. It does the familiar "give me module  in
my namespace", but it also can change the semantics of the language. That's what
"from __future__ import " does, and one of the things you can change that way
is whether a string is a unicode or a bytearray in python2 (they default to
bytearrays in python2, but unicode in python3), which is something we'll want to
toggle if hybridize for python2 and 3. What would happen in this file now if we
added "from __future__ import unicode_literals" is that the COPYRIGHT would
visually look like a unicode object, but would actually be a bytearray, while
the rest of the naked strings in the file would be unicode.

What would actually be much easier, is putting the function in a mako file and
loading that, mako has filesystem based loader for such things, and injecting
mako into mako templates is pretty easy.  I'll send a patch for that.


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Re: [Mesa-dev] [PATCH 10/20] nir: Add pass to scalarize read_invocation/read_first_invocation

[Connor Abbott]

AMD will want these to be scalar too. With Ken's fix,

Reviewed-by: Connor Abbott 

On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner  wrote:
> i965 will want these to be scalar operations.
> ---
>  src/compiler/Makefile.sources  |   1 +
>  src/compiler/nir/nir.h |   2 +-
>  .../nir/nir_lower_read_invocation_to_scalar.c  | 112 
> +
>  3 files changed, 114 insertions(+), 1 deletion(-)
>  create mode 100644 src/compiler/nir/nir_lower_read_invocation_to_scalar.c
>
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index b0f1c14b87..95f64f7a91 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -229,6 +229,7 @@ NIR_FILES = \
> nir/nir_lower_passthrough_edgeflags.c \
> nir/nir_lower_patch_vertices.c \
> nir/nir_lower_phis_to_scalar.c \
> +   nir/nir_lower_read_invocation_to_scalar.c \
> nir/nir_lower_regs_to_ssa.c \
> nir/nir_lower_returns.c \
> nir/nir_lower_samplers.c \
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 401c41f155..3591048574 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -2433,7 +2433,7 @@ bool nir_move_vec_src_uses_to_dest(nir_shader *shader);
>  bool nir_lower_vec_to_movs(nir_shader *shader);
>  bool nir_lower_alu_to_scalar(nir_shader *shader);
>  bool nir_lower_load_const_to_scalar(nir_shader *shader);
> -
> +bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
>  bool nir_lower_phis_to_scalar(nir_shader *shader);
>  void nir_lower_io_to_scalar(nir_shader *shader, nir_variable_mode mask);
>
> diff --git a/src/compiler/nir/nir_lower_read_invocation_to_scalar.c 
> b/src/compiler/nir/nir_lower_read_invocation_to_scalar.c
> new file mode 100644
> index 00..edac7f5271
> --- /dev/null
> +++ b/src/compiler/nir/nir_lower_read_invocation_to_scalar.c
> @@ -0,0 +1,112 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +#include "nir_builder.h"
> +
> +/** @file nir_lower_read_invocation_to_scalar.c
> + *
> + * Replaces nir_intrinsic_read_invocation/nir_intrinsic_read_first_invocation
> + * operations with num_components != 1 with individual per-channel 
> operations.
> + */
> +
> +static void
> +lower_read_invocation_to_scalar(nir_builder *b, nir_intrinsic_instr *intrin)
> +{
> +   b->cursor = nir_before_instr(>instr);
> +
> +   nir_ssa_def *value = nir_ssa_for_src(b, intrin->src[0], 
> intrin->num_components);
> +   nir_ssa_def *reads[4];
> +
> +   for (unsigned i = 0; i < intrin->num_components; i++) {
> +  nir_intrinsic_instr *chan_intrin =
> + nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
> +  nir_ssa_dest_init(_intrin->instr, _intrin->dest,
> +1, intrin->dest.ssa.bit_size, NULL);
> +  chan_intrin->num_components = 1;
> +
> +  /* value */
> +  chan_intrin->src[0] = nir_src_for_ssa(nir_channel(b, value, i));
> +  /* invocation */
> +  if (intrin->intrinsic == nir_intrinsic_read_invocation)
> + chan_intrin->src[1] = intrin->src[1];
> +
> +  nir_builder_instr_insert(b, _intrin->instr);
> +
> +  reads[i] = _intrin->dest.ssa;
> +   }
> +
> +   nir_ssa_def_rewrite_uses(>dest.ssa,
> +nir_src_for_ssa(nir_vec(b, reads,
> +
> intrin->num_components)));
> +   nir_instr_remove(>instr);
> +}
> +
> +static bool
> +nir_lower_read_invocation_to_scalar_impl(nir_function_impl *impl)
> +{
> +   bool progress = false;
> +   nir_builder b;
> +   nir_builder_init(, impl);
> +
> +   nir_foreach_block(block, impl) {
> +  nir_foreach_instr_safe(instr, block) {
> + if (instr->type != 

Re: [Mesa-dev] [PATCH] dri: Make classic drivers allow __DRI_CTX_FLAG_NO_ERROR.

[Grigori Goronzy]

On 2017-07-18 20:25, Ian Romanick wrote:

On 07/14/2017 04:10 PM, Kenneth Graunke wrote:

Grigori recently added EGL_KHR_create_context_no_error support,
which causes EGL to pass a new __DRI_CTX_FLAG_NO_ERROR flag to
drivers when requesting an appropriate context mode.

driContextSetFlags() will already handle it properly for us, but the
classic drivers all have code to explicitly balk at unknown flags.  We
need to let it through or they'll fail to create a no_error context.


I'm almost afraid to ask... are there tests that try to create a
no_error context?



I don't think there are any yet. I have a piglit test for this which 
creates a context with EGL_khr_create_context_no_error and verifies that 
glGetError() behaves correctly in error conditions. I've used it to test 
my no_error series, but it's super hacky. Let me finish it up and I'll 
submit it in a few days.


Grigori


---
 src/mesa/drivers/dri/i915/intel_screen.c   | 2 +-
 src/mesa/drivers/dri/i965/brw_context.c| 5 +++--
 src/mesa/drivers/dri/nouveau/nouveau_context.c | 2 +-
 src/mesa/drivers/dri/r200/r200_context.c   | 2 +-
 src/mesa/drivers/dri/radeon/radeon_context.c   | 2 +-
 5 files changed, 7 insertions(+), 6 deletions(-)

Drivers other than i965 have not been tested.

diff --git a/src/mesa/drivers/dri/i915/intel_screen.c 
b/src/mesa/drivers/dri/i915/intel_screen.c

index 9e23552b998..1ac72e14a15 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -972,7 +972,7 @@ intelCreateContext(gl_api api,
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->driverPrivate;

-   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
+   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
   *error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
   return false;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c

index b23e811f305..bd26e2332c7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -813,8 +813,9 @@ brwCreateContext(gl_api api,
/* Only allow the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag if the 
kernel

 * provides us with context reset notifications.
 */
-   uint32_t allowed_flags = __DRI_CTX_FLAG_DEBUG
-  | __DRI_CTX_FLAG_FORWARD_COMPATIBLE;
+   uint32_t allowed_flags = __DRI_CTX_FLAG_DEBUG |
+__DRI_CTX_FLAG_FORWARD_COMPATIBLE |
+__DRI_CTX_FLAG_NO_ERROR;

if (screen->has_context_reset_notification)
   allowed_flags |= __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS;
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c 
b/src/mesa/drivers/dri/nouveau/nouveau_context.c

index 6ddcadce1f0..d6f9e533848 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -63,7 +63,7 @@ nouveau_context_create(gl_api api,
struct nouveau_context *nctx;
struct gl_context *ctx;

-   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
+   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
return false;
}
diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
b/src/mesa/drivers/dri/r200/r200_context.c

index aaa9b9317df..5a7f33499b1 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -189,7 +189,7 @@ GLboolean r200CreateContext( gl_api api,
int i;
int tcl_mode;

-   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
+   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
   *error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
   return false;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c 
b/src/mesa/drivers/dri/radeon/radeon_context.c

index 11afe20c6a0..5ef3467ac17 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -155,7 +155,7 @@ r100CreateContext( gl_api api,
int i;
int tcl_mode, fthrottle_mode;

-   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
+   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
   *error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
   return false;
}


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Re: [Mesa-dev] [PATCH 08/20] nir: Add intrinsics from ARB_shader_ballot

[Connor Abbott]

With Ken's suggestion,

Reviewed-by: Connor Abbott 

On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner  wrote:
> ---
>  src/compiler/glsl/glsl_to_nir.cpp | 45 
> +++
>  src/compiler/nir/nir_intrinsics.h | 13 +++
>  2 files changed, 58 insertions(+)
>
> diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
> b/src/compiler/glsl/glsl_to_nir.cpp
> index 43d7e07042..23632f27c2 100644
> --- a/src/compiler/glsl/glsl_to_nir.cpp
> +++ b/src/compiler/glsl/glsl_to_nir.cpp
> @@ -808,6 +808,15 @@ nir_visitor::visit(ir_call *ir)
>case ir_intrinsic_vote_eq:
>   op = nir_intrinsic_vote_eq;
>   break;
> +  case ir_intrinsic_ballot:
> + op = nir_intrinsic_ballot;
> + break;
> +  case ir_intrinsic_read_invocation:
> + op = nir_intrinsic_read_invocation;
> + break;
> +  case ir_intrinsic_read_first_invocation:
> + op = nir_intrinsic_read_first_invocation;
> + break;
>default:
>   unreachable("not reached");
>}
> @@ -1150,6 +1159,42 @@ nir_visitor::visit(ir_call *ir)
>   nir_ssa_dest_init(>instr, >dest, 1, 32, NULL);
>
>   instr->variables[0] = evaluate_deref(>instr, 
> ir->return_deref);
> + ir_instruction *value = (ir_instruction 
> *)ir->actual_parameters.get_head();
> +
> + instr->src[0] = 
> nir_src_for_ssa(evaluate_rvalue(value->as_rvalue()));
> +
> + nir_builder_instr_insert(, >instr);
> + break;
> +  }
> +
> +  case nir_intrinsic_ballot: {
> + nir_ssa_dest_init(>instr, >dest,
> +   ir->return_deref->type->vector_elements, 64, 
> NULL);
> +
> + ir_instruction *value = (ir_instruction 
> *)ir->actual_parameters.get_head();
> + instr->src[0] = 
> nir_src_for_ssa(evaluate_rvalue(value->as_rvalue()));
> +
> + nir_builder_instr_insert(, >instr);
> + break;
> +  }
> +  case nir_intrinsic_read_invocation: {
> + nir_ssa_dest_init(>instr, >dest,
> +   ir->return_deref->type->vector_elements, 32, 
> NULL);
> + instr->num_components = ir->return_deref->type->vector_elements;
> +
> + ir_instruction *value = (ir_instruction 
> *)ir->actual_parameters.get_head();
> + instr->src[0] = 
> nir_src_for_ssa(evaluate_rvalue(value->as_rvalue()));
> +
> + ir_instruction *invocation = (ir_instruction *)value->get_next();
> + instr->src[1] = 
> nir_src_for_ssa(evaluate_rvalue(invocation->as_rvalue()));
> +
> + nir_builder_instr_insert(, >instr);
> + break;
> +  }
> +  case nir_intrinsic_read_first_invocation: {
> + nir_ssa_dest_init(>instr, >dest,
> +   ir->return_deref->type->vector_elements, 32, 
> NULL);
> + instr->num_components = ir->return_deref->type->vector_elements;
>
>   ir_instruction *value = (ir_instruction 
> *)ir->actual_parameters.get_head();
>   instr->src[0] = 
> nir_src_for_ssa(evaluate_rvalue(value->as_rvalue()));
> diff --git a/src/compiler/nir/nir_intrinsics.h 
> b/src/compiler/nir/nir_intrinsics.h
> index 8a838df027..6c6ba4cf59 100644
> --- a/src/compiler/nir/nir_intrinsics.h
> +++ b/src/compiler/nir/nir_intrinsics.h
> @@ -94,6 +94,19 @@ BARRIER(memory_barrier)
>  INTRINSIC(shader_clock, 0, ARR(0), true, 2, 0, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
>
>  /*
> + * Shader ballot intrinsics with semantics analogous to the
> + *
> + *ballotARB()
> + *readInvocationARB()
> + *readFirstInvocationARB()
> + *
> + * GLSL functions from ARB_shader_ballot.
> + */
> +INTRINSIC(ballot, 1, ARR(1), true, 1, 0, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
> +INTRINSIC(read_invocation, 2, ARR(0, 1), true, 0, 0, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
> +INTRINSIC(read_first_invocation, 1, ARR(0), true, 0, 0, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
> +
> +/*
>   * Memory barrier with semantics analogous to the compute shader
>   * groupMemoryBarrier(), memoryBarrierAtomicCounter(), memoryBarrierBuffer(),
>   * memoryBarrierImage() and memoryBarrierShared() GLSL intrinsics.
> --
> 2.13.0
>
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Re: [Mesa-dev] [PATCH 03/22] i965/miptree: Switch to isl_surf::tiling

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:30 PM, Kenneth Graunke 
wrote:

> On Tuesday, July 18, 2017 1:46:13 AM PDT Topi Pohjolainen wrote:
> [snip]
> > diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
> b/src/mesa/drivers/dri/i965/intel_blit.h
> > index 5e4d1f5eb4..90514dc893 100644
> > --- a/src/mesa/drivers/dri/i965/intel_blit.h
> > +++ b/src/mesa/drivers/dri/i965/intel_blit.h
> > @@ -41,17 +41,32 @@ isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
> > return I915_TILING_NONE;
> >  }
> >
> > +static inline enum isl_tiling
> > +bufmgr_tiling_to_isl_tiling(unsigned tiling)
> > +{
> > +   switch (tiling) {
> > +   case I915_TILING_NONE:
> > +  return ISL_TILING_LINEAR;
> > +   case I915_TILING_X:
> > +  return ISL_TILING_X;
> > +   case I915_TILING_Y:
> > +  return ISL_TILING_Y0;
> > +   }
> > +
> > +   unreachable("Invalid tiling mode");
> > +}
> > +
>
> This doesn't appear to be used at this point.  If it's used later, great,
> but I'm not sure why you'd need a converter in this direction?
>

It's used in miptree_create_for_bo

Reviewed-by: Jason Ekstrand 
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Re: [Mesa-dev] [PATCH 03/22] i965/miptree: Switch to isl_surf::tiling

[Daniel Stone]

Hi,

On 18 July 2017 at 21:30, Kenneth Graunke  wrote:
> On Tuesday, July 18, 2017 1:46:13 AM PDT Topi Pohjolainen wrote:
> [snip]
>> diff --git a/src/mesa/drivers/dri/i965/intel_blit.h 
>> b/src/mesa/drivers/dri/i965/intel_blit.h
>> index 5e4d1f5eb4..90514dc893 100644
>> --- a/src/mesa/drivers/dri/i965/intel_blit.h
>> +++ b/src/mesa/drivers/dri/i965/intel_blit.h
>> @@ -41,17 +41,32 @@ isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
>> return I915_TILING_NONE;
>>  }
>>
>> +static inline enum isl_tiling
>> +bufmgr_tiling_to_isl_tiling(unsigned tiling)
>> +{
>> +   switch (tiling) {
>> +   case I915_TILING_NONE:
>> +  return ISL_TILING_LINEAR;
>> +   case I915_TILING_X:
>> +  return ISL_TILING_X;
>> +   case I915_TILING_Y:
>> +  return ISL_TILING_Y0;
>> +   }
>> +
>> +   unreachable("Invalid tiling mode");
>> +}
>> +
>
> This doesn't appear to be used at this point.  If it's used later, great,
> but I'm not sure why you'd need a converter in this direction?

It also belongs aside isl_tiling_to_i915_tiling() inside isl itself;
that function can itself replace isl_tiling_to_bufmgr_tiling().

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH 03/20] nir: Support lowering vote intrinsics

[Connor Abbott]

On Mon, Jul 10, 2017 at 10:18 AM, Matt Turner  wrote:
> On Thu, Jul 6, 2017 at 8:04 PM, Connor Abbott  wrote:
>> On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner  wrote:
>>> ... trivially (as allowed by the spec!) by reusing the existing
>>> nir_opt_intrinsics code.
>>> ---
>>>  src/compiler/nir/nir.h| 4 
>>>  src/compiler/nir/nir_opt_intrinsics.c | 6 +++---
>>>  2 files changed, 7 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
>>> index 44a1d0887e..401c41f155 100644
>>> --- a/src/compiler/nir/nir.h
>>> +++ b/src/compiler/nir/nir.h
>>> @@ -1821,6 +1821,10 @@ typedef struct nir_shader_compiler_options {
>>> bool lower_extract_byte;
>>> bool lower_extract_word;
>>>
>>> +   bool lower_vote_any;
>>> +   bool lower_vote_all;
>>> +   bool lower_vote_eq;
>>
>> Since there are potentially multiple ways to lower these (voteAny(x)
>> -> !voteAll(!x), using ballotARB(), etc.), and the way they're lowered
>> is a little... unexpected (although admittedly legal!), why don't we
>> use a more descriptive name, like lower_vote_*_trivial? While we're at
>> it, I highly doubt that an implementation would want this kind of
>> lowering for just one of the intrinsics, so we can merge this into a
>> single flag, say lower_vote_trivial.
>
> Thanks, both good ideas. I've replaced all three fields with a
> lower_vote_trivial field.

I had a closer look at your branch with the updated patch, and the
logic here, repeated in two places, seems backwards:

if (!val || b.shader->options->lower_vote_trivial)
   continue;

This will skip processing the instruction at all if you set
lower_vote_trivial, even if val is non-NULL, which seems like the
opposite of what you want. Also, even once you fix this:

if (!val && !b.shader->options->lower_vote_trivial)
   continue;

You'll still segfault in the vote_any/vote_all case if the source
isn't constant, since you'll try to dereference val when it doesn't
exist. You can fix this by changing the line below to:

replacement = nir_ssa_for_src(, instr->src[0], 1);

in the previous patch. I'm kinda nervous that lower_vote_trivial seems
untested, since it never would've worked as-is, but I can't see any
other problems so patches 2 & 3 get my R-b with these fixes. But you
might want to write some really simple vertex shader piglit tests,
even if you only use dynamically uniform arguments, to make sure this
is working correctly.
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Re: [Mesa-dev] [PATCH 01/22] i965/miptree: Switch to isl_surf::msaa_layout

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c |  3 +-
>  src/mesa/drivers/dri/i965/brw_tex_layout.c|  9 ++-
>  src/mesa/drivers/dri/i965/brw_wm.c|  2 +-
>  src/mesa/drivers/dri/i965/intel_fbo.c | 13 +---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 85
> +++
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 49 ---
>  6 files changed, 30 insertions(+), 131 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 11f2fae380..be310de85b 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -134,8 +134,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> unsigned start_layer, unsigned num_layers,
> struct isl_surf tmp_surfs[1])
>  {
> -   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> -   mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
> +   if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
>const unsigned num_samples = MAX2(1, mt->num_samples);
>for (unsigned i = 0; i < num_layers; i++) {
>   for (unsigned s = 0; s < num_samples; s++) {
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index c76e87bc06..91e94ee4a0 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -625,13 +625,12 @@ intel_miptree_set_total_width_height(struct
> brw_context *brw,
>break;
>
> default:
> -  switch (mt->msaa_layout) {
> -  case INTEL_MSAA_LAYOUT_UMS:
> -  case INTEL_MSAA_LAYOUT_CMS:
> +  switch (mt->surf.msaa_layout) {
> +  case ISL_MSAA_LAYOUT_ARRAY:
>   brw_miptree_layout_texture_array(brw, mt);
>   break;
> -  case INTEL_MSAA_LAYOUT_NONE:
> -  case INTEL_MSAA_LAYOUT_IMS:
> +  case ISL_MSAA_LAYOUT_NONE:
> +  case ISL_MSAA_LAYOUT_INTERLEAVED:
>   if (gen9_use_linear_1d_layout(brw, mt))
>  gen9_miptree_layout_1d(mt);
>   else if (mt->array_layout == GEN6_HIZ_STENCIL)
> diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
> b/src/mesa/drivers/dri/i965/brw_wm.c
> index 18056d51d0..9e1dcee8fd 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm.c
> @@ -400,7 +400,7 @@ brw_populate_sampler_prog_key_data(struct gl_context
> *ctx,
>  assert(brw->gen >= 7);
>  assert(intel_tex->mt->num_samples > 1);
>  assert(intel_tex->mt->mcs_buf);
> -assert(intel_tex->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
> +assert(intel_tex->mt->surf.msaa_layout ==
> ISL_MSAA_LAYOUT_ARRAY);
>  key->compressed_multisample_layout_mask |= 1 << s;
>
>  if (intel_tex->mt->num_samples >= 16) {
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index a73ca59946..3ac6892ea0 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -532,16 +532,9 @@ intel_renderbuffer_update_wrapper(struct brw_context
> *brw,
> irb->mt_level = level;
> irb->mt_layer = layer;
>
> -   int layer_multiplier;
> -   switch (mt->msaa_layout) {
> -  case INTEL_MSAA_LAYOUT_UMS:
> -  case INTEL_MSAA_LAYOUT_CMS:
> - layer_multiplier = MAX2(mt->num_samples, 1);
> - break;
> -
> -  default:
> - layer_multiplier = 1;
> -   }
> +   const unsigned layer_multiplier =
> +  mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ?
> +  MAX2(mt->num_samples, 1) : 1;
>
> if (!layered) {
>irb->layer_count = 1;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index f292d71d38..8e241b8462 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -101,42 +101,22 @@ is_mcs_supported(const struct brw_context *brw,
> mesa_format format,
>   * Determine which MSAA layout should be used by the MSAA surface being
>   * created, based on the chip generation and the surface type.
>   */
> -static enum intel_msaa_layout
> +static enum isl_msaa_layout
>  compute_msaa_layout(struct brw_context *brw, mesa_format format,
>  uint32_t layout_flags)
>  {
> /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> if (brw->gen < 7)
> -  return INTEL_MSAA_LAYOUT_IMS;
> +  return ISL_MSAA_LAYOUT_INTERLEAVED;
>
> /* In Gen7, IMS layout is only used for depth and stencil buffers. */
> switch (_mesa_get_format_base_format(format)) {
> case GL_DEPTH_COMPONENT:
> case GL_STENCIL_INDEX:
> case GL_DEPTH_STENCIL:
> -  return 

Re: [Mesa-dev] [PATCH 03/22] i965/miptree: Switch to isl_surf::tiling

[Kenneth Graunke]

On Tuesday, July 18, 2017 1:46:13 AM PDT Topi Pohjolainen wrote:
[snip]
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.h 
> b/src/mesa/drivers/dri/i965/intel_blit.h
> index 5e4d1f5eb4..90514dc893 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.h
> +++ b/src/mesa/drivers/dri/i965/intel_blit.h
> @@ -41,17 +41,32 @@ isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
> return I915_TILING_NONE;
>  }
>  
> +static inline enum isl_tiling
> +bufmgr_tiling_to_isl_tiling(unsigned tiling)
> +{
> +   switch (tiling) {
> +   case I915_TILING_NONE:
> +  return ISL_TILING_LINEAR;
> +   case I915_TILING_X:
> +  return ISL_TILING_X;
> +   case I915_TILING_Y:
> +  return ISL_TILING_Y0;
> +   }
> +
> +   unreachable("Invalid tiling mode");
> +}
> +

This doesn't appear to be used at this point.  If it's used later, great,
but I'm not sure why you'd need a converter in this direction?

Patches 1-3 are:
Reviewed-by: Kenneth Graunke 

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Re: [Mesa-dev] [PATCH 02/22] i965/miptree: Switch to isl_surf::samples

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c| 16 -
>  src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
>  src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
>  src/mesa/drivers/dri/i965/brw_tex_layout.c   |  4 +--
>  src/mesa/drivers/dri/i965/brw_wm.c   |  4 +--
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
>  src/mesa/drivers/dri/i965/intel_blit.c   |  4 +--
>  src/mesa/drivers/dri/i965/intel_fbo.c|  4 +--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 46
> 
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 
>  src/mesa/drivers/dri/i965/intel_pixel_copy.c |  2 +-
>  11 files changed, 43 insertions(+), 49 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index be310de85b..be0d41b04a 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> struct isl_surf tmp_surfs[1])
>  {
> if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
> -  const unsigned num_samples = MAX2(1, mt->num_samples);
> +  const unsigned num_samples = MAX2(1, mt->surf.samples);
>for (unsigned i = 0; i < num_layers; i++) {
>   for (unsigned s = 0; s < num_samples; s++) {
>  const unsigned phys_layer = (start_layer + i) * num_samples +
> s;
> @@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
>   * Note: if the src (or dst) is a 2D multisample array texture on Gen7+
> using
>   * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer)
> is
>   * the physical layer holding sample 0.  So, for example, if
> - * src_mt->num_samples == 4, then logical layer n corresponds to
> src_layer ==
> + * src_mt->surf.samples == 4, then logical layer n corresponds to
> src_layer ==
>   * 4*n.
>   */
>  void
> @@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
> "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
> __func__,
> -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
> -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
> mirror_x, mirror_y);
>
> @@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>  * R32_FLOAT, so only the contents of the red channel matters.
>  */
> if (brw->gen == 6 &&
> -   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
> +   src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
> src_mt->format == dst_mt->format &&
> (dst_format == MESA_FORMAT_L_FLOAT32 ||
>  dst_format == MESA_FORMAT_I_FLOAT32)) {
> @@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
> DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
> "to %dx %s mt %p %d %d (%d,%d)\n",
> __func__,
> -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> src_level, src_layer, src_x, src_y, src_width, src_height,
> -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> dst_level, dst_layer, dst_x, dst_y);
>
> struct isl_surf tmp_surfs[2];
> @@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
> struct intel_mipmap_tree *dst_mt = intel_image->mt;
>
> /* There is support for only up to eight samples. */
> -   if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
> +   if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
>return false;
>
> if (_mesa_get_format_base_format(src_rb->Format) !=
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index bd26e2332c..fffe310b97 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context
> *brw,
>rb = intel_get_renderbuffer(fb, buffers[i]);
>if (rb == NULL || rb->mt == NULL)
>   continue;
> -  if (rb->mt->num_samples <= 1) {
> +  if (rb->mt->surf.samples <= 1) {
>   assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
>  rb->layer_count == 1);
>   

Re: [Mesa-dev] [PATCH v3 1/2] gallium/util: Implement util_format_is_etc

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jul 18, 2017 at 6:01 AM,   wrote:
> From: "Wladimir J. van der Laan" 
>
> This is the equivalent of util_format_is_s3tc, but for
> ETC.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/auxiliary/util/u_format.h | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/src/gallium/auxiliary/util/u_format.h 
> b/src/gallium/auxiliary/util/u_format.h
> index d055778..2318e97 100644
> --- a/src/gallium/auxiliary/util/u_format.h
> +++ b/src/gallium/auxiliary/util/u_format.h
> @@ -496,6 +496,19 @@ util_format_is_s3tc(enum pipe_format format)
>  }
>
>  static inline boolean
> +util_format_is_etc(enum pipe_format format)
> +{
> +   const struct util_format_description *desc = 
> util_format_description(format);
> +
> +   assert(desc);
> +   if (!desc) {
> +  return FALSE;
> +   }
> +
> +   return desc->layout == UTIL_FORMAT_LAYOUT_ETC ? TRUE : FALSE;
> +}
> +
> +static inline boolean
>  util_format_is_srgb(enum pipe_format format)
>  {
> const struct util_format_description *desc = 
> util_format_description(format);
> --
> 2.7.4
>
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[Mesa-dev] [PATCH] mesa: check API profile for GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION

[Brian Paul]

If we have a compat profile context, it means that GL_QUADS[_STRIP] are
supported so this query makes sense.  It's also legal for 3.2 core profile
because of a spec bug.
---
 src/mesa/main/get.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 825ea34..68f520f 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -1302,7 +1302,7 @@ check_extra(struct gl_context *ctx, const char *func, 
const struct value_desc *d
  break;
   case EXTRA_EXT_PROVOKING_VERTEX_32:
  api_check = TRUE;
- if (version <= 32)
+ if (ctx->API == API_OPENGL_COMPAT || version == 32)
 api_found = ctx->Extensions.EXT_provoking_vertex;
  break;
   case EXTRA_END:
-- 
1.9.1

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Re: [Mesa-dev] [PATCH] gallium: auxiliary: Fix standalone Android build of u_cpu_detect (v2)

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jul 18, 2017 at 3:20 AM, Tomasz Figa  wrote:
> Commit 463b7d0332c5("gallium: Enable ARM NEON CPU detection.")
> introduced CPU feature detection based Android cpufeatures library.
> Unfortunately it also added an assumption that if PIPE_OS_ANDROID is
> defined, the library is also available, which is not true for the
> standalone build without using Android build system.
>
> Fix it by defining HAS_ANDROID_CPUFEATURES in Android.mk and replacing
> respective #ifdefs to use it instead.
>
> v2:
>  - Add a comment explaining why the separate flag is needed (Emil).
>
> Signed-off-by: Tomasz Figa 
> ---
>  src/gallium/auxiliary/Android.mk  |  1 +
>  src/gallium/auxiliary/util/u_cpu_detect.c | 11 +--
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/auxiliary/Android.mk 
> b/src/gallium/auxiliary/Android.mk
> index 356390dfde..26938384fb 100644
> --- a/src/gallium/auxiliary/Android.mk
> +++ b/src/gallium/auxiliary/Android.mk
> @@ -50,6 +50,7 @@ LOCAL_MODULE := libmesa_gallium
>  LOCAL_STATIC_LIBRARIES += libmesa_nir
>
>  LOCAL_WHOLE_STATIC_LIBRARIES += cpufeatures
> +LOCAL_CFLAGS += -DHAS_ANDROID_CPUFEATURES
>
>  # generate sources
>  LOCAL_MODULE_CLASS := STATIC_LIBRARIES
> diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c 
> b/src/gallium/auxiliary/util/u_cpu_detect.c
> index 76115bf8d5..3d6ccb5822 100644
> --- a/src/gallium/auxiliary/util/u_cpu_detect.c
> +++ b/src/gallium/auxiliary/util/u_cpu_detect.c
> @@ -67,7 +67,7 @@
>  #include 
>  #endif
>
> -#if defined(PIPE_OS_ANDROID)
> +#if defined(HAS_ANDROID_CPUFEATURES)
>  #include 
>  #endif
>
> @@ -304,7 +304,14 @@ PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
>  static void
>  check_os_arm_support(void)
>  {
> -#if defined(PIPE_OS_ANDROID)
> +   /*
> +* On Android, the cpufeatures library is preferred way of checking
> +* CPU capabilities. However, it is not available for standalone Mesa
> +* builds, i.e. when Android build system (Android.mk-based) is not
> +* used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
> +* have a separate macro that only gets enabled from respective 
> Android.mk.
> +*/
> +#if defined(HAS_ANDROID_CPUFEATURES)
> AndroidCpuFamily cpu_family = android_getCpuFamily();
> uint64_t cpu_features = android_getCpuFeatures();
>
> --
> 2.13.2.932.g7449e964c-goog
>
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Re: [Mesa-dev] [PATCH] mesa: fix GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT query

[Brian Paul]

On 07/18/2017 12:19 PM, Ian Romanick wrote:

Also... I'm not a huge fan of a Reviewed-by from someone new to the
mailing list with zero commits in Mesa resulting in an instant commit
(no offense to Neha).  That's not okay.  For the review system to have
value, we have to give people time to respond to patches.  This patch
hit the list less than 24 hours ago.


Since this is a low-impact change and reviews are sometimes slow to 
come, I figured I'd push it after I got Neha's sanity check review 
(she's been looking at provoking vertex stuff lately).  I can wait a bit 
longer next time.


-Brian

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Re: [Mesa-dev] [PATCH] mesa: fix GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT query

[Brian Paul]

On 07/18/2017 12:11 PM, Ian Romanick wrote:

On 07/17/2017 11:28 AM, Brian Paul wrote:

This query is not allowed in GL core profile 3.3 and later (since
GL_QUADS and GL_QUAD_STRIP are disallowed).  The query was (mistakenly)
supported in GL 3.2.  This fixes the glGet error test accordingly.
---
  src/mesa/main/get.c  | 12 
  src/mesa/main/get_hash_params.py |  2 +-
  2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 6ad107b..3247653 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -162,6 +162,7 @@ enum value_extra {
 EXTRA_EXT_SSBO_GS,
 EXTRA_EXT_FB_NO_ATTACH_GS,
 EXTRA_EXT_ES_GS,
+   EXTRA_EXT_PROVOKING_VERTEX_32,
  };

  #define NO_EXTRA NULL
@@ -573,6 +574,12 @@ static const int extra_EXT_shader_framebuffer_fetch[] = {
 EXTRA_END
  };

+static const int extra_EXT_provoking_vertex_32[] = {
+   EXTRA_EXT_PROVOKING_VERTEX_32,
+   EXTRA_END
+};
+
+
  /* This is the big table describing all the enums we accept in
   * glGet*v().  The table is partitioned into six parts: enums
   * understood by all GL APIs (OpenGL, GLES and GLES2), enums shared
@@ -1293,6 +1300,11 @@ check_extra(struct gl_context *ctx, const char *func, 
const struct value_desc *d
   if (_mesa_has_OES_geometry_shader(ctx))
  api_found = GL_TRUE;
   break;
+  case EXTRA_EXT_PROVOKING_VERTEX_32:
+ api_check = TRUE;
+ if (version <= 32)
+api_found = ctx->Extensions.EXT_provoking_vertex;


But we also shouldn't support it in OpenGL 3.1 because we don't expose
GL_ARB_compatibility, right?  It seems like this should check api ==
API_OPENGL_COMPAT instead.


From my additional testing, I think we need to test for 
(API_OPENGL_COMPAT || version==3.2).  That seems to match what NVIDIA does.


New patches coming.

-Brian




+ break;
case EXTRA_END:
 break;
default: /* *e is a offset into the extension struct */
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 850ce7d..9d67ca4 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -888,7 +888,7 @@ descriptor=[

  # GL_EXT_provoking_vertex
[ "PROVOKING_VERTEX_EXT", "CONTEXT_ENUM(Light.ProvokingVertex), 
extra_EXT_provoking_vertex" ],
-  [ "QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT", 
"CONTEXT_BOOL(Const.QuadsFollowProvokingVertexConvention), extra_EXT_provoking_vertex" ],
+  [ "QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT", 
"CONTEXT_BOOL(Const.QuadsFollowProvokingVertexConvention), extra_EXT_provoking_vertex_32" 
],


Wouldn't it be easier to just move this to a section that is only valid
for compatibility profile?  Though there may not be one yet...



  # GL_ARB_seamless_cube_map
[ "TEXTURE_CUBE_MAP_SEAMLESS", "CONTEXT_BOOL(Texture.CubeMapSeamless), 
extra_ARB_seamless_cube_map" ],





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[Mesa-dev] [RFC PATCH] radeonsi: set a per-buffer flag that disables inter-process sharing (v2)

[Marek Olšák]

From: Marek Olšák 

For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.

v2: It shouldn't crash anymore, but the kernel will reject the new flag.
---
 src/gallium/drivers/radeon/r600_buffer_common.c |  7 +
 src/gallium/drivers/radeon/radeon_winsys.h  | 20 +++---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 36 -
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c   | 27 +++
 4 files changed, 62 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index dd1c209..2747ac4 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -160,20 +160,27 @@ void r600_init_resource_fields(struct r600_common_screen 
*rscreen,
}
 
/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 RADEON_FLAG_GTT_WC;
}
 
+   /* Only displayable single-sample textures can be shared between
+* processes. */
+   if (res->b.b.target == PIPE_BUFFER ||
+   res->b.b.nr_samples >= 2 ||
+   rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY)
+   res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
/* If VRAM is just stolen system memory, allow both VRAM and
 * GTT, whichever has free space. If a buffer is evicted from
 * VRAM to GTT, it will stay there.
 *
 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 * placements even with a low amount of stolen VRAM.
 */
if (!rscreen->info.has_dedicated_vram &&
(rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
res->domains == RADEON_DOMAIN_VRAM) {
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 351edcd..0abcb56 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -47,20 +47,21 @@ enum radeon_bo_domain { /* bitfield */
 RADEON_DOMAIN_GTT  = 2,
 RADEON_DOMAIN_VRAM = 4,
 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
 };
 
 enum radeon_bo_flag { /* bitfield */
 RADEON_FLAG_GTT_WC =(1 << 0),
 RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
 RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
 RADEON_FLAG_SPARSE =(1 << 3),
+RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
 };
 
 enum radeon_bo_usage { /* bitfield */
 RADEON_USAGE_READ = 2,
 RADEON_USAGE_WRITE = 4,
 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
 
 /* The winsys ensures that the CS submission will be scheduled after
  * previously flushed CSs referencing this BO in a conflicting way.
  */
@@ -685,28 +686,33 @@ static inline enum radeon_bo_domain 
radeon_domain_from_heap(enum radeon_heap hea
 default:
 assert(0);
 return (enum radeon_bo_domain)0;
 }
 }
 
 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 {
 switch (heap) {
 case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
-return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
+return RADEON_FLAG_GTT_WC |
+   RADEON_FLAG_NO_CPU_ACCESS |
+   RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
 case RADEON_HEAP_VRAM:
 case RADEON_HEAP_VRAM_GTT:
 case RADEON_HEAP_GTT_WC:
-return RADEON_FLAG_GTT_WC;
+return RADEON_FLAG_GTT_WC |
+   RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
 case RADEON_HEAP_GTT:
 default:
-return 0;
+return RADEON_FLAG_NO_INTERPROCESS_SHARING;
 }
 }
 
 /* The pb cache bucket is chosen to minimize pb_cache misses.
  * It must be between 0 and 3 inclusive.
  */
 static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
 {
 switch (heap) {
 case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
@@ -724,22 +730,28 @@ static inline unsigned 
radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
 
 /* Return the heap index for winsys allocators, or -1 on failure. */
 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 enum radeon_bo_flag flags)
 {
 /* VRAM implies WC (write combining) */
 assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 /* NO_CPU_ACCESS implies VRAM only. */
 assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == 
RADEON_DOMAIN_VRAM);
 
+/* Resources with interprocess sharing don't use any winsys allocators. */
+if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
+return -1;
+
 

Re: [Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

[Connor Abbott]

With Ken's suggestion, this is

Reviewed-by: Connor Abbott 

On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner  wrote:
> These are intrinsics rather than opcodes, because they operate across
> channels.
> ---
>  src/compiler/glsl/glsl_to_nir.cpp | 22 ++
>  src/compiler/nir/nir_intrinsics.h |  5 +
>  2 files changed, 27 insertions(+)
>
> diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
> b/src/compiler/glsl/glsl_to_nir.cpp
> index 21530040a9..43d7e07042 100644
> --- a/src/compiler/glsl/glsl_to_nir.cpp
> +++ b/src/compiler/glsl/glsl_to_nir.cpp
> @@ -799,6 +799,15 @@ nir_visitor::visit(ir_call *ir)
>case ir_intrinsic_shared_atomic_comp_swap:
>   op = nir_intrinsic_shared_atomic_comp_swap;
>   break;
> +  case ir_intrinsic_vote_any:
> + op = nir_intrinsic_vote_any;
> + break;
> +  case ir_intrinsic_vote_all:
> + op = nir_intrinsic_vote_all;
> + break;
> +  case ir_intrinsic_vote_eq:
> + op = nir_intrinsic_vote_eq;
> + break;
>default:
>   unreachable("not reached");
>}
> @@ -1135,6 +1144,19 @@ nir_visitor::visit(ir_call *ir)
>   nir_builder_instr_insert(, >instr);
>   break;
>}
> +  case nir_intrinsic_vote_any:
> +  case nir_intrinsic_vote_all:
> +  case nir_intrinsic_vote_eq: {
> + nir_ssa_dest_init(>instr, >dest, 1, 32, NULL);
> +
> + instr->variables[0] = evaluate_deref(>instr, 
> ir->return_deref);
> +
> + ir_instruction *value = (ir_instruction 
> *)ir->actual_parameters.get_head();
> + instr->src[0] = 
> nir_src_for_ssa(evaluate_rvalue(value->as_rvalue()));
> +
> + nir_builder_instr_insert(, >instr);
> + break;
> +  }
>default:
>   unreachable("not reached");
>}
> diff --git a/src/compiler/nir/nir_intrinsics.h 
> b/src/compiler/nir/nir_intrinsics.h
> index 21e7d904b7..8a838df027 100644
> --- a/src/compiler/nir/nir_intrinsics.h
> +++ b/src/compiler/nir/nir_intrinsics.h
> @@ -107,6 +107,11 @@ BARRIER(memory_barrier_shared)
>  /** A conditional discard, with a single boolean source. */
>  INTRINSIC(discard_if, 1, ARR(1), false, 0, 0, 0, xx, xx, xx, 0)
>
> +/** ARB_shader_group_vote intrinsics */
> +INTRINSIC(vote_any, 1, ARR(1), true, 1, 1, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
> +INTRINSIC(vote_all, 1, ARR(1), true, 1, 1, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
> +INTRINSIC(vote_eq,  1, ARR(1), true, 1, 1, 0, xx, xx, xx, 
> NIR_INTRINSIC_CAN_ELIMINATE)
> +
>  /**
>   * Basic Geometry Shader intrinsics.
>   *
> --
> 2.13.0
>
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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #5 from charmai...@vmware.com ---

Hi Brad,

Can you try the attached patch to see if that fixes your crash?
Thanks.

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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #4 from charmai...@vmware.com ---
Created attachment 132747
  --> https://bugs.freedesktop.org/attachment.cgi?id=132747=edit
Assign a unique ID to the framebuffer interface object created in xm_st.c

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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #3 from Gert Wollny  ---
I can confirm that the trace results in a sigsegv, but with gltrace on r600g I
get a different backtrace (9ee67467c9ea + a patchset related to register
merging that shouldn't have to do anything with the bug) 

valgrind glretrace Downloads/example.trace 
==8227== Memcheck, a memory error detector
==8227== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==8227== Using Valgrind-3.13.0 and LibVEX; rerun with -h for copyright info
==8227== Command: glretrace Downloads/example.trace
==8227== 
==8227== Invalid read of size 4
==8227==at 0x9A9AC88: st_framebuffers_purge (st_manager.c:509)
==8227==by 0x9A9AC88: st_api_make_current (st_manager.c:872)
==8227==by 0x9C457CD: dri_make_current (dri_context.c:278)
==8227==by 0x9C44283: driBindContext (dri_util.c:559)
==8227==by 0x77425EA: dri2_bind_context (dri2_glx.c:154)
==8227==by 0x771930B: MakeContextCurrent (glxcurrent.c:228)
==8227==by 0x40A406: glws::makeCurrentInternal(glws::Drawable*,
glws::Context*) (glws_glx.cpp:370)
==8227==by 0x412C3E: makeCurrent (glws.hpp:213)
==8227==by 0x412C3E: glretrace::makeCurrent(trace::Call&, glws::Drawable*,
glretrace::Context*) (glretrace_ws.cpp:170)
==8227==by 0x40C8BC: retrace::retraceCall(trace::Call*)
(retrace_main.cpp:233)
==8227==by 0x40CE2F: runLeg (retrace_main.cpp:386)
==8227==by 0x40CE2F: runRace (retrace_main.cpp:364)
==8227==by 0x40CE2F: retrace::RelayRace::run() (retrace_main.cpp:505)
==8227==by 0x407D97: mainLoop (retrace_main.cpp:565)
==8227==by 0x407D97: main (retrace_main.cpp:880)
==8227==  Address 0x1604d964 is 4 bytes inside a block of size 480 free'd
==8227==at 0x4C2BD2B: free (vg_replace_malloc.c:530)
==8227==by 0x9C44F3D: dri_put_drawable.part.3 (dri_util.c:642)
==8227==by 0x7741337: dri2DestroyDrawable (dri2_glx.c:343)
==8227==by 0x773EEC9: driReleaseDrawables (dri_common.c:452)
==8227==by 0x77425C1: dri2_bind_context (dri2_glx.c:142)
==8227==by 0x771930B: MakeContextCurrent (glxcurrent.c:228)
==8227==by 0x40A406: glws::makeCurrentInternal(glws::Drawable*,
glws::Context*) (glws_glx.cpp:370)
==8227==by 0x412C3E: makeCurrent (glws.hpp:213)
==8227==by 0x412C3E: glretrace::makeCurrent(trace::Call&, glws::Drawable*,
glretrace::Context*) (glretrace_ws.cpp:170)
==8227==by 0x40C8BC: retrace::retraceCall(trace::Call*)
(retrace_main.cpp:233)
==8227==by 0x40CE2F: runLeg (retrace_main.cpp:386)
==8227==by 0x40CE2F: runRace (retrace_main.cpp:364)
==8227==by 0x40CE2F: retrace::RelayRace::run() (retrace_main.cpp:505)
==8227==by 0x407D97: mainLoop (retrace_main.cpp:565)
==8227==by 0x407D97: main (retrace_main.cpp:880)
==8227==  Block was alloc'd at
==8227==at 0x4C2CB0D: calloc (vg_replace_malloc.c:711)
==8227==by 0x9C46199: dri_create_buffer (dri_drawable.c:139)
==8227==by 0x9C49D83: dri2_create_buffer (dri2.c:2196)
==8227==by 0x9C450A3: driCreateNewDrawable (dri_util.c:671)
==8227==by 0x774127C: dri2CreateDrawable (dri2_glx.c:405)
==8227==by 0x773ED9F: driFetchDrawable (dri_common.c:410)
==8227==by 0x77425A8: dri2_bind_context (dri2_glx.c:139)
==8227==by 0x771930B: MakeContextCurrent (glxcurrent.c:228)
==8227==by 0x40A406: glws::makeCurrentInternal(glws::Drawable*,
glws::Context*) (glws_glx.cpp:370)
==8227==by 0x412C3E: makeCurrent (glws.hpp:213)
==8227==by 0x412C3E: glretrace::makeCurrent(trace::Call&, glws::Drawable*,
glretrace::Context*) (glretrace_ws.cpp:170)
==8227==by 0x40C8BC: retrace::retraceCall(trace::Call*)
(retrace_main.cpp:233)
==8227==by 0x40CE2F: runLeg (retrace_main.cpp:386)
==8227==by 0x40CE2F: runRace (retrace_main.cpp:364)
==8227==by 0x40CE2F: retrace::RelayRace::run() (retrace_main.cpp:505)
739: message: api issue 1: FBO incomplete: no attachments and default width or
height is 0 [-1]
==8227== Conditional jump or move depends on uninitialised value(s)
==8227==at 0x4C327D2: __memcmp_sse4_1 (vg_replace_strmem.c:1099)
==8227==by 0x9F12F2F: r600_set_vertex_buffers (r600_state_common.c:550)
==8227==by 0x9D4EDE0: u_vbuf_set_driver_vertex_buffers (u_vbuf.c:1116)
==8227==by 0x9D52394: u_vbuf_draw_vbo (u_vbuf.c:1140)
==8227==by 0x9A6018B: st_draw_vbo (st_draw.c:222)
==8227==by 0x9A0A379: vbo_validated_drawrangeelements
(vbo_exec_array.c:918)
==8227==by 0x9A0AB05: vbo_exec_DrawRangeElementsBaseVertex
(vbo_exec_array.c:1019)
==8227==by 0x9A0AD6A: vbo_exec_DrawRangeElements (vbo_exec_array.c:1039)
==8227==by 0x9938B6F: _mesa_unmarshal_DrawRangeElements
(marshal_generated.c:21699)
==8227==by 0x9938B6F: _mesa_unmarshal_dispatch_cmd
(marshal_generated.c:41346)
==8227==by 0x98ED96C: glthread_unmarshal_batch (glthread.c:53)
==8227==by 0x98EDC54: _mesa_glthread_finish (glthread.c:209)
==8227==by 0x98FF573: _mesa_marshal_GetError (marshal_generated.c:12286)
==8227== 

Re: [Mesa-dev] [PATCH] dri: Make classic drivers allow __DRI_CTX_FLAG_NO_ERROR.

[Ian Romanick]

On 07/14/2017 04:10 PM, Kenneth Graunke wrote:
> Grigori recently added EGL_KHR_create_context_no_error support,
> which causes EGL to pass a new __DRI_CTX_FLAG_NO_ERROR flag to
> drivers when requesting an appropriate context mode.
> 
> driContextSetFlags() will already handle it properly for us, but the
> classic drivers all have code to explicitly balk at unknown flags.  We
> need to let it through or they'll fail to create a no_error context.

I'm almost afraid to ask... are there tests that try to create a
no_error context?

> ---
>  src/mesa/drivers/dri/i915/intel_screen.c   | 2 +-
>  src/mesa/drivers/dri/i965/brw_context.c| 5 +++--
>  src/mesa/drivers/dri/nouveau/nouveau_context.c | 2 +-
>  src/mesa/drivers/dri/r200/r200_context.c   | 2 +-
>  src/mesa/drivers/dri/radeon/radeon_context.c   | 2 +-
>  5 files changed, 7 insertions(+), 6 deletions(-)
> 
> Drivers other than i965 have not been tested.
> 
> diff --git a/src/mesa/drivers/dri/i915/intel_screen.c 
> b/src/mesa/drivers/dri/i915/intel_screen.c
> index 9e23552b998..1ac72e14a15 100644
> --- a/src/mesa/drivers/dri/i915/intel_screen.c
> +++ b/src/mesa/drivers/dri/i915/intel_screen.c
> @@ -972,7 +972,7 @@ intelCreateContext(gl_api api,
> __DRIscreen *sPriv = driContextPriv->driScreenPriv;
> struct intel_screen *intelScreen = sPriv->driverPrivate;
>  
> -   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
> +   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
>*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
>return false;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> b/src/mesa/drivers/dri/i965/brw_context.c
> index b23e811f305..bd26e2332c7 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -813,8 +813,9 @@ brwCreateContext(gl_api api,
> /* Only allow the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag if the kernel
>  * provides us with context reset notifications.
>  */
> -   uint32_t allowed_flags = __DRI_CTX_FLAG_DEBUG
> -  | __DRI_CTX_FLAG_FORWARD_COMPATIBLE;
> +   uint32_t allowed_flags = __DRI_CTX_FLAG_DEBUG |
> +__DRI_CTX_FLAG_FORWARD_COMPATIBLE |
> +__DRI_CTX_FLAG_NO_ERROR;
>  
> if (screen->has_context_reset_notification)
>allowed_flags |= __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS;
> diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c 
> b/src/mesa/drivers/dri/nouveau/nouveau_context.c
> index 6ddcadce1f0..d6f9e533848 100644
> --- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
> +++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
> @@ -63,7 +63,7 @@ nouveau_context_create(gl_api api,
>   struct nouveau_context *nctx;
>   struct gl_context *ctx;
>  
> - if (flags & ~__DRI_CTX_FLAG_DEBUG) {
> + if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
>   *error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
>   return false;
>   }
> diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
> b/src/mesa/drivers/dri/r200/r200_context.c
> index aaa9b9317df..5a7f33499b1 100644
> --- a/src/mesa/drivers/dri/r200/r200_context.c
> +++ b/src/mesa/drivers/dri/r200/r200_context.c
> @@ -189,7 +189,7 @@ GLboolean r200CreateContext( gl_api api,
> int i;
> int tcl_mode;
>  
> -   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
> +   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
>*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
>return false;
> }
> diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c 
> b/src/mesa/drivers/dri/radeon/radeon_context.c
> index 11afe20c6a0..5ef3467ac17 100644
> --- a/src/mesa/drivers/dri/radeon/radeon_context.c
> +++ b/src/mesa/drivers/dri/radeon/radeon_context.c
> @@ -155,7 +155,7 @@ r100CreateContext( gl_api api,
> int i;
> int tcl_mode, fthrottle_mode;
>  
> -   if (flags & ~__DRI_CTX_FLAG_DEBUG) {
> +   if (flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
>*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
>return false;
> }
> 

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Re: [Mesa-dev] [PATCH] mesa: fix GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT query

[Ian Romanick]

Also... I'm not a huge fan of a Reviewed-by from someone new to the
mailing list with zero commits in Mesa resulting in an instant commit
(no offense to Neha).  That's not okay.  For the review system to have
value, we have to give people time to respond to patches.  This patch
hit the list less than 24 hours ago.

On 07/18/2017 11:11 AM, Ian Romanick wrote:
> On 07/17/2017 11:28 AM, Brian Paul wrote:
>> This query is not allowed in GL core profile 3.3 and later (since
>> GL_QUADS and GL_QUAD_STRIP are disallowed).  The query was (mistakenly)
>> supported in GL 3.2.  This fixes the glGet error test accordingly.
>> ---
>>  src/mesa/main/get.c  | 12 
>>  src/mesa/main/get_hash_params.py |  2 +-
>>  2 files changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
>> index 6ad107b..3247653 100644
>> --- a/src/mesa/main/get.c
>> +++ b/src/mesa/main/get.c
>> @@ -162,6 +162,7 @@ enum value_extra {
>> EXTRA_EXT_SSBO_GS,
>> EXTRA_EXT_FB_NO_ATTACH_GS,
>> EXTRA_EXT_ES_GS,
>> +   EXTRA_EXT_PROVOKING_VERTEX_32,
>>  };
>>  
>>  #define NO_EXTRA NULL
>> @@ -573,6 +574,12 @@ static const int extra_EXT_shader_framebuffer_fetch[] = 
>> {
>> EXTRA_END
>>  };
>>  
>> +static const int extra_EXT_provoking_vertex_32[] = {
>> +   EXTRA_EXT_PROVOKING_VERTEX_32,
>> +   EXTRA_END
>> +};
>> +
>> +
>>  /* This is the big table describing all the enums we accept in
>>   * glGet*v().  The table is partitioned into six parts: enums
>>   * understood by all GL APIs (OpenGL, GLES and GLES2), enums shared
>> @@ -1293,6 +1300,11 @@ check_extra(struct gl_context *ctx, const char *func, 
>> const struct value_desc *d
>>   if (_mesa_has_OES_geometry_shader(ctx))
>>  api_found = GL_TRUE;
>>   break;
>> +  case EXTRA_EXT_PROVOKING_VERTEX_32:
>> + api_check = TRUE;
>> + if (version <= 32)
>> +api_found = ctx->Extensions.EXT_provoking_vertex;
> 
> But we also shouldn't support it in OpenGL 3.1 because we don't expose
> GL_ARB_compatibility, right?  It seems like this should check api ==
> API_OPENGL_COMPAT instead.
> 
>> + break;
>>case EXTRA_END:
>>   break;
>>default: /* *e is a offset into the extension struct */
>> diff --git a/src/mesa/main/get_hash_params.py 
>> b/src/mesa/main/get_hash_params.py
>> index 850ce7d..9d67ca4 100644
>> --- a/src/mesa/main/get_hash_params.py
>> +++ b/src/mesa/main/get_hash_params.py
>> @@ -888,7 +888,7 @@ descriptor=[
>>  
>>  # GL_EXT_provoking_vertex
>>[ "PROVOKING_VERTEX_EXT", "CONTEXT_ENUM(Light.ProvokingVertex), 
>> extra_EXT_provoking_vertex" ],
>> -  [ "QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT", 
>> "CONTEXT_BOOL(Const.QuadsFollowProvokingVertexConvention), 
>> extra_EXT_provoking_vertex" ],
>> +  [ "QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT", 
>> "CONTEXT_BOOL(Const.QuadsFollowProvokingVertexConvention), 
>> extra_EXT_provoking_vertex_32" ],
> 
> Wouldn't it be easier to just move this to a section that is only valid
> for compatibility profile?  Though there may not be one yet...
> 
>>  
>>  # GL_ARB_seamless_cube_map
>>[ "TEXTURE_CUBE_MAP_SEAMLESS", "CONTEXT_BOOL(Texture.CubeMapSeamless), 
>> extra_ARB_seamless_cube_map" ],
>>
> 
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [PATCH mesa] spirv: add missing include path

[Jason Ekstrand]

On Tue, Jul 18, 2017 at 11:15 AM, Ian Romanick  wrote:

> I can believe the fix, but I don't understand why it's necessary.
> spirv_info.c includes spriv_info.h in the same manner as before
> 2dd4e2ec, and, as far as I can understand, spirv_info.c gets built in
> the same way as before.  Can someone explain to me why it broke?
> ...because I don't want to break it again.
>

Out-of-tree builds.  In that case, spirv_info.c is in the build directory
but spirv_info.h is in the source directory.

--Jason


> On 07/18/2017 11:03 AM, Eric Engestrom wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101831
> > Signed-off-by: Eric Engestrom 
> > ---
> >
> > Note: Android and SCons probably need a similar fix
> > ---
> >  src/compiler/Makefile.nir.am | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
> > index 1533ee536d..002b9fc535 100644
> > --- a/src/compiler/Makefile.nir.am
> > +++ b/src/compiler/Makefile.nir.am
> > @@ -32,6 +32,9 @@ nir_libnir_la_SOURCES =
>  \
> >   $(SPIRV_GENERATED_FILES)\
> >   $(NIR_GENERATED_FILES)
> >
> > +nir_libnir_la_SOURCES = \
> > + -I$(top_builddir)/src/compiler/spirv
> > +
> >  nir/nir_builder_opcodes.h: nir/nir_opcodes.py
> nir/nir_builder_opcodes_h.py
> >   $(MKDIR_GEN)
> >   $(PYTHON_GEN) $(srcdir)/nir/nir_builder_opcodes_h.py > $@ ||
> ($(RM) $@; false)
> >
>
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Re: [Mesa-dev] [PATCH mesa] spirv: add missing include path

[Emil Velikov]

On 18 July 2017 at 19:03, Eric Engestrom  wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101831
> Signed-off-by: Eric Engestrom 
> ---
>
> Note: Android and SCons probably need a similar fix
> ---
>  src/compiler/Makefile.nir.am | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
> index 1533ee536d..002b9fc535 100644
> --- a/src/compiler/Makefile.nir.am
> +++ b/src/compiler/Makefile.nir.am
> @@ -32,6 +32,9 @@ nir_libnir_la_SOURCES = 
>   \
> $(SPIRV_GENERATED_FILES)\
> $(NIR_GENERATED_FILES)
>
> +nir_libnir_la_SOURCES = \
> +   -I$(top_builddir)/src/compiler/spirv
> +
This is off - the generated file is missing the srcdir, since it
assumes the header to be in the same directory.

Ken should have pushed a fix a second ago.
-Emil
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Re: [Mesa-dev] [PATCH mesa] spirv: add missing include path

[Ian Romanick]

I can believe the fix, but I don't understand why it's necessary.
spirv_info.c includes spriv_info.h in the same manner as before
2dd4e2ec, and, as far as I can understand, spirv_info.c gets built in
the same way as before.  Can someone explain to me why it broke?
...because I don't want to break it again.

On 07/18/2017 11:03 AM, Eric Engestrom wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101831
> Signed-off-by: Eric Engestrom 
> ---
> 
> Note: Android and SCons probably need a similar fix
> ---
>  src/compiler/Makefile.nir.am | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
> index 1533ee536d..002b9fc535 100644
> --- a/src/compiler/Makefile.nir.am
> +++ b/src/compiler/Makefile.nir.am
> @@ -32,6 +32,9 @@ nir_libnir_la_SOURCES = 
> \
>   $(SPIRV_GENERATED_FILES)\
>   $(NIR_GENERATED_FILES)
>  
> +nir_libnir_la_SOURCES = \
> + -I$(top_builddir)/src/compiler/spirv
> +
>  nir/nir_builder_opcodes.h: nir/nir_opcodes.py nir/nir_builder_opcodes_h.py
>   $(MKDIR_GEN)
>   $(PYTHON_GEN) $(srcdir)/nir/nir_builder_opcodes_h.py > $@ || ($(RM) $@; 
> false)
> 

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[Mesa-dev] [Bug 101831] Build failure in GNOME Continuous

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101831

Kenneth Graunke  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #1 from Kenneth Graunke  ---
thanks ebassi!  this should be fixed by

commit c2bb39d8d6eaf391d917db94ca671a6261800359
Author: Kenneth Graunke 
Date:   Tue Jul 18 11:09:37 2017 -0700

build: Add $(top_srcdir)/src/compiler/spirv to AM_CPPFLAGS

feel free to reopen if it isn't fixed for you.

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Re: [Mesa-dev] [PATCH] mesa: fix GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT query

[Ian Romanick]

On 07/17/2017 11:28 AM, Brian Paul wrote:
> This query is not allowed in GL core profile 3.3 and later (since
> GL_QUADS and GL_QUAD_STRIP are disallowed).  The query was (mistakenly)
> supported in GL 3.2.  This fixes the glGet error test accordingly.
> ---
>  src/mesa/main/get.c  | 12 
>  src/mesa/main/get_hash_params.py |  2 +-
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
> index 6ad107b..3247653 100644
> --- a/src/mesa/main/get.c
> +++ b/src/mesa/main/get.c
> @@ -162,6 +162,7 @@ enum value_extra {
> EXTRA_EXT_SSBO_GS,
> EXTRA_EXT_FB_NO_ATTACH_GS,
> EXTRA_EXT_ES_GS,
> +   EXTRA_EXT_PROVOKING_VERTEX_32,
>  };
>  
>  #define NO_EXTRA NULL
> @@ -573,6 +574,12 @@ static const int extra_EXT_shader_framebuffer_fetch[] = {
> EXTRA_END
>  };
>  
> +static const int extra_EXT_provoking_vertex_32[] = {
> +   EXTRA_EXT_PROVOKING_VERTEX_32,
> +   EXTRA_END
> +};
> +
> +
>  /* This is the big table describing all the enums we accept in
>   * glGet*v().  The table is partitioned into six parts: enums
>   * understood by all GL APIs (OpenGL, GLES and GLES2), enums shared
> @@ -1293,6 +1300,11 @@ check_extra(struct gl_context *ctx, const char *func, 
> const struct value_desc *d
>   if (_mesa_has_OES_geometry_shader(ctx))
>  api_found = GL_TRUE;
>   break;
> +  case EXTRA_EXT_PROVOKING_VERTEX_32:
> + api_check = TRUE;
> + if (version <= 32)
> +api_found = ctx->Extensions.EXT_provoking_vertex;

But we also shouldn't support it in OpenGL 3.1 because we don't expose
GL_ARB_compatibility, right?  It seems like this should check api ==
API_OPENGL_COMPAT instead.

> + break;
>case EXTRA_END:
>break;
>default: /* *e is a offset into the extension struct */
> diff --git a/src/mesa/main/get_hash_params.py 
> b/src/mesa/main/get_hash_params.py
> index 850ce7d..9d67ca4 100644
> --- a/src/mesa/main/get_hash_params.py
> +++ b/src/mesa/main/get_hash_params.py
> @@ -888,7 +888,7 @@ descriptor=[
>  
>  # GL_EXT_provoking_vertex
>[ "PROVOKING_VERTEX_EXT", "CONTEXT_ENUM(Light.ProvokingVertex), 
> extra_EXT_provoking_vertex" ],
> -  [ "QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT", 
> "CONTEXT_BOOL(Const.QuadsFollowProvokingVertexConvention), 
> extra_EXT_provoking_vertex" ],
> +  [ "QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT", 
> "CONTEXT_BOOL(Const.QuadsFollowProvokingVertexConvention), 
> extra_EXT_provoking_vertex_32" ],

Wouldn't it be easier to just move this to a section that is only valid
for compatibility profile?  Though there may not be one yet...

>  
>  # GL_ARB_seamless_cube_map
>[ "TEXTURE_CUBE_MAP_SEAMLESS", "CONTEXT_BOOL(Texture.CubeMapSeamless), 
> extra_ARB_seamless_cube_map" ],
> 

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[Mesa-dev] [PATCH mesa] spirv: add missing include path

[Eric Engestrom]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101831
Signed-off-by: Eric Engestrom 
---

Note: Android and SCons probably need a similar fix
---
 src/compiler/Makefile.nir.am | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
index 1533ee536d..002b9fc535 100644
--- a/src/compiler/Makefile.nir.am
+++ b/src/compiler/Makefile.nir.am
@@ -32,6 +32,9 @@ nir_libnir_la_SOURCES =   
\
$(SPIRV_GENERATED_FILES)\
$(NIR_GENERATED_FILES)
 
+nir_libnir_la_SOURCES = \
+   -I$(top_builddir)/src/compiler/spirv
+
 nir/nir_builder_opcodes.h: nir/nir_opcodes.py nir/nir_builder_opcodes_h.py
$(MKDIR_GEN)
$(PYTHON_GEN) $(srcdir)/nir/nir_builder_opcodes_h.py > $@ || ($(RM) $@; 
false)
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [RFC PATCH] radeonsi: set a per-buffer flag that disables inter-process sharing

[Marek Olšák]

For comments only. There are some assertion failures.

Marek

On Tue, Jul 18, 2017 at 1:47 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> for lower overhead in the CS ioctl
> ---
>  src/gallium/drivers/radeon/r600_buffer_common.c | 7 +++
>  src/gallium/drivers/radeon/radeon_winsys.h  | 1 +
>  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 6 ++
>  3 files changed, 14 insertions(+)
>
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
> b/src/gallium/drivers/radeon/r600_buffer_common.c
> index dd1c209..2747ac4 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -160,20 +160,27 @@ void r600_init_resource_fields(struct 
> r600_common_screen *rscreen,
> }
>
> /* Tiled textures are unmappable. Always put them in VRAM. */
> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
> res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
> res->domains = RADEON_DOMAIN_VRAM;
> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
>  RADEON_FLAG_GTT_WC;
> }
>
> +   /* Only displayable single-sample textures can be shared between
> +* processes. */
> +   if (res->b.b.target == PIPE_BUFFER ||
> +   res->b.b.nr_samples >= 2 ||
> +   rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY)
> +   res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
> +
> /* If VRAM is just stolen system memory, allow both VRAM and
>  * GTT, whichever has free space. If a buffer is evicted from
>  * VRAM to GTT, it will stay there.
>  *
>  * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
>  * placements even with a low amount of stolen VRAM.
>  */
> if (!rscreen->info.has_dedicated_vram &&
> (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
> res->domains == RADEON_DOMAIN_VRAM) {
> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
> b/src/gallium/drivers/radeon/radeon_winsys.h
> index 351edcd..ce2fd73 100644
> --- a/src/gallium/drivers/radeon/radeon_winsys.h
> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
> @@ -47,20 +47,21 @@ enum radeon_bo_domain { /* bitfield */
>  RADEON_DOMAIN_GTT  = 2,
>  RADEON_DOMAIN_VRAM = 4,
>  RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
>  };
>
>  enum radeon_bo_flag { /* bitfield */
>  RADEON_FLAG_GTT_WC =(1 << 0),
>  RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
>  RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
>  RADEON_FLAG_SPARSE =(1 << 3),
> +RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
>  };
>
>  enum radeon_bo_usage { /* bitfield */
>  RADEON_USAGE_READ = 2,
>  RADEON_USAGE_WRITE = 4,
>  RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
>
>  /* The winsys ensures that the CS submission will be scheduled after
>   * previously flushed CSs referencing this BO in a conflicting way.
>   */
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> index 97bbe23..f97e1bf 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> @@ -31,20 +31,24 @@
>
>  #include "amdgpu_cs.h"
>
>  #include "os/os_time.h"
>  #include "state_tracker/drm_driver.h"
>  #include 
>  #include 
>  #include 
>  #include 
>
> +#ifndef AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING
> +#define AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING (1 << 6)
> +#endif
> +
>  /* Set to 1 for verbose output showing committed sparse buffer ranges. */
>  #define DEBUG_SPARSE_COMMITS 0
>
>  struct amdgpu_sparse_backing_chunk {
> uint32_t begin, end;
>  };
>
>  static struct pb_buffer *
>  amdgpu_bo_create(struct radeon_winsys *rws,
>   uint64_t size,
> @@ -395,20 +399,22 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
> amdgpu_winsys *ws,
>
> if (initial_domain & RADEON_DOMAIN_VRAM)
>request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
> if (initial_domain & RADEON_DOMAIN_GTT)
>request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
>
> if (flags & RADEON_FLAG_NO_CPU_ACCESS)
>request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
> if (flags & RADEON_FLAG_GTT_WC)
>request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> +   if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING)
> +  request.flags |= AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING;
>
> r = amdgpu_bo_alloc(ws->dev, , _handle);
> if (r) {
>fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
>fprintf(stderr, "amdgpu:size  : %"PRIu64" bytes\n", size);
>fprintf(stderr, "amdgpu:alignment : %u bytes\n", alignment);
>fprintf(stderr, "amdgpu:domains   : %u\n", initial_domain);
>goto error_bo_alloc;
>  

[Mesa-dev] [RFC PATCH] radeonsi: set a per-buffer flag that disables inter-process sharing

[Marek Olšák]

From: Marek Olšák 

for lower overhead in the CS ioctl
---
 src/gallium/drivers/radeon/r600_buffer_common.c | 7 +++
 src/gallium/drivers/radeon/radeon_winsys.h  | 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 6 ++
 3 files changed, 14 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index dd1c209..2747ac4 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -160,20 +160,27 @@ void r600_init_resource_fields(struct r600_common_screen 
*rscreen,
}
 
/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 RADEON_FLAG_GTT_WC;
}
 
+   /* Only displayable single-sample textures can be shared between
+* processes. */
+   if (res->b.b.target == PIPE_BUFFER ||
+   res->b.b.nr_samples >= 2 ||
+   rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY)
+   res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
/* If VRAM is just stolen system memory, allow both VRAM and
 * GTT, whichever has free space. If a buffer is evicted from
 * VRAM to GTT, it will stay there.
 *
 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 * placements even with a low amount of stolen VRAM.
 */
if (!rscreen->info.has_dedicated_vram &&
(rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
res->domains == RADEON_DOMAIN_VRAM) {
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 351edcd..ce2fd73 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -47,20 +47,21 @@ enum radeon_bo_domain { /* bitfield */
 RADEON_DOMAIN_GTT  = 2,
 RADEON_DOMAIN_VRAM = 4,
 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
 };
 
 enum radeon_bo_flag { /* bitfield */
 RADEON_FLAG_GTT_WC =(1 << 0),
 RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
 RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
 RADEON_FLAG_SPARSE =(1 << 3),
+RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
 };
 
 enum radeon_bo_usage { /* bitfield */
 RADEON_USAGE_READ = 2,
 RADEON_USAGE_WRITE = 4,
 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
 
 /* The winsys ensures that the CS submission will be scheduled after
  * previously flushed CSs referencing this BO in a conflicting way.
  */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 97bbe23..f97e1bf 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -31,20 +31,24 @@
 
 #include "amdgpu_cs.h"
 
 #include "os/os_time.h"
 #include "state_tracker/drm_driver.h"
 #include 
 #include 
 #include 
 #include 
 
+#ifndef AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING
+#define AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING (1 << 6)
+#endif
+
 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
 #define DEBUG_SPARSE_COMMITS 0
 
 struct amdgpu_sparse_backing_chunk {
uint32_t begin, end;
 };
 
 static struct pb_buffer *
 amdgpu_bo_create(struct radeon_winsys *rws,
  uint64_t size,
@@ -395,20 +399,22 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
 
if (initial_domain & RADEON_DOMAIN_VRAM)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
if (initial_domain & RADEON_DOMAIN_GTT)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
 
if (flags & RADEON_FLAG_NO_CPU_ACCESS)
   request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
if (flags & RADEON_FLAG_GTT_WC)
   request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+   if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING)
+  request.flags |= AMDGPU_GEM_CREATE_NO_INTERPROCESS_SHARING;
 
r = amdgpu_bo_alloc(ws->dev, , _handle);
if (r) {
   fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
   fprintf(stderr, "amdgpu:size  : %"PRIu64" bytes\n", size);
   fprintf(stderr, "amdgpu:alignment : %u bytes\n", alignment);
   fprintf(stderr, "amdgpu:domains   : %u\n", initial_domain);
   goto error_bo_alloc;
}
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v3 08/16] anv: Transition more color buffer layouts

[Nanley Chery]

On Mon, Jul 17, 2017 at 02:41:32PM -0700, Jason Ekstrand wrote:
> On Fri, Jul 14, 2017 at 2:42 AM, Nanley Chery  wrote:
> 
> > On Mon, Jul 10, 2017 at 10:14:21AM -0700, Jason Ekstrand wrote:
> > > On Wed, Jun 28, 2017 at 2:14 PM, Nanley Chery 
> > wrote:
> > >
> > > > v2: Expound on comment for the pipe controls (Jason Ekstrand).
> > > >
> > > > Signed-off-by: Nanley Chery 
> > > > ---
> > > >  src/intel/vulkan/anv_blorp.c   |   4 +-
> > > >  src/intel/vulkan/genX_cmd_buffer.c | 183
> > ++
> > > > +++
> > > >  2 files changed, 167 insertions(+), 20 deletions(-)
> > > >
> > > > diff --git a/src/intel/vulkan/anv_blorp.c
> > b/src/intel/vulkan/anv_blorp.c
> > > > index 459d57ec57..84b01e8792 100644
> > > > --- a/src/intel/vulkan/anv_blorp.c
> > > > +++ b/src/intel/vulkan/anv_blorp.c
> > > > @@ -1451,7 +1451,9 @@ anv_image_ccs_clear(struct anv_cmd_buffer
> > > > *cmd_buffer,
> > > >
> > > > struct blorp_surf surf;
> > > > get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
> > > > -image->aux_usage, );
> > > > +image->aux_usage ==
> > ISL_AUX_USAGE_CCS_E ?
> > > > +ISL_AUX_USAGE_CCS_E :
> > ISL_AUX_USAGE_CCS_D,
> > > > +);
> > > >
> > > > /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
> > > >  *
> > > > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> > > > b/src/intel/vulkan/genX_cmd_buffer.c
> > > > index decf0b28d6..1a9b841c7c 100644
> > > > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > > > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > > > @@ -524,6 +524,17 @@ genX(copy_fast_clear_dwords)(struct
> > anv_cmd_buffer
> > > > *cmd_buffer,
> > > > }
> > > >  }
> > > >
> > > > +/**
> > > > + * @brief Transitions a color buffer from one layout to another.
> > > > + *
> > > > + * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50
> > spec
> > > > for
> > > > + * more information.
> > > > + *
> > > > + * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
> > > > + * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For
> > 3D
> > > > images,
> > > > + *this represents the maximum layers to
> > transition at
> > > > each
> > > > + *specified miplevel.
> > > > + */
> > > >  static void
> > > >  transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
> > > >  const struct anv_image *image,
> > > > @@ -532,13 +543,27 @@ transition_color_buffer(struct anv_cmd_buffer
> > > > *cmd_buffer,
> > > >  VkImageLayout initial_layout,
> > > >  VkImageLayout final_layout)
> > > >  {
> > > > -   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> > > > -
> > > > -   if (image->aux_surface.isl.size == 0)
> > > > -  return;
> > > > -
> > > > -   if (initial_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
> > > > -   initial_layout != VK_IMAGE_LAYOUT_PREINITIALIZED)
> > > > +   /* Validate the inputs. */
> > > > +   assert(cmd_buffer);
> > > > +   assert(image && image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> > > > +   /* These values aren't supported for simplicity's sake. */
> > > > +   assert(level_count != VK_REMAINING_MIP_LEVELS &&
> > > > +  layer_count != VK_REMAINING_ARRAY_LAYERS);
> > > > +   /* Ensure the subresource range is valid. */
> > > > +   uint64_t last_level_num = base_level + level_count;
> > > > +   const uint32_t max_depth = anv_minify(image->extent.depth,
> > > > base_level);
> > > > +   const uint32_t image_layers = MAX2(image->array_size, max_depth);
> > > > +   assert(base_layer + layer_count  <= image_layers);
> > > > +   assert(last_level_num <= image->levels);
> > > > +   /* The spec disallows these final layouts. */
> > > > +   assert(final_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
> > > > +  final_layout != VK_IMAGE_LAYOUT_PREINITIALIZED);
> > > > +
> > > > +   /* No work is necessary if the layout stays the same or if this
> > > > subresource
> > > > +* range lacks auxiliary data.
> > > > +*/
> > > > +   if (initial_layout == final_layout ||
> > > > +   base_layer >= anv_image_aux_layers(image, base_level))
> > > >return;
> > > >
> > > > /* A transition of a 3D subresource works on all slices at a time.
> > */
> > > > @@ -549,22 +574,142 @@ transition_color_buffer(struct anv_cmd_buffer
> > > > *cmd_buffer,
> > > >
> > > > /* We're interested in the subresource range subset that has aux
> > data.
> > > > */
> > > > level_count = MIN2(level_count, anv_image_aux_levels(image));
> > > > +   layer_count = MIN2(layer_count, anv_image_aux_layers(image,
> > > > base_level));
> > > >
> > >
> > > Is this correct?  I think we want MIN2(layer_count,
> > anv_image_aux_layers()
> > > - base_layer), don't we?  This would also mean there's a bug in 

[Mesa-dev] [Bug 101831] Build failure in GNOME Continuous

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101831

Bug ID: 101831
   Summary: Build failure in GNOME Continuous
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: eba...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Mesa is currently failing to build from Git master in the GNOME continuous
builder:

spirv/spirv_info.c:23:24: fatal error: spirv_info.h: No such file or directory
compilation terminated.
Makefile:2369: recipe for target 'spirv/spirv_info.lo' failed
make[4]: *** [spirv/spirv_info.lo] Error 1

Full build log:
http://build.gnome.org/continuous/buildmaster/builds/2017/07/18/51/build/log-mesa.txt

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Re: [Mesa-dev] [PATCH] egl/dri2: remove unused buffer_count variable

[Eric Engestrom]

On 18 July 2017 09:12:50 BST, Gwan-gyeong Mun  wrote:
> It removes unused buffer_count variable from dri2_egl_surface.
> And it polishes the assert of dri2_drm_get_buffers_with_format().
> 
> Signed-off-by: Mun Gwan-gyeong 

Reviewed-by: Eric Engestrom 

> ---
>  src/egl/drivers/dri2/egl_dri2.h | 1 -
>  src/egl/drivers/dri2/platform_android.c | 5 +
>  src/egl/drivers/dri2/platform_drm.c | 3 +--
>  src/egl/drivers/dri2/platform_x11.c | 1 -
>  4 files changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/egl_dri2.h
> b/src/egl/drivers/dri2/egl_dri2.h
> index 5b3e93abe0..a8133e0e50 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -246,7 +246,6 @@ struct dri2_egl_surface
> _EGLSurface  base;
> __DRIdrawable   *dri_drawable;
> __DRIbuffer  buffers[5];
> -   int  buffer_count;
> bool have_fake_front;
>  
>  #ifdef HAVE_X11_PLATFORM
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index 13006fee87..300e2d9dbf 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -1003,16 +1003,13 @@ droid_get_buffers_with_format(__DRIdrawable *
> driDrawable,
> if (update_buffers(dri2_surf) < 0)
>return NULL;
>  
> -   dri2_surf->buffer_count =
> -  droid_get_buffers_parse_attachments(dri2_surf, attachments,
> count);
> +   *out_count = droid_get_buffers_parse_attachments(dri2_surf,
> attachments, count);
>  
> if (width)
>*width = dri2_surf->base.Width;
> if (height)
>*height = dri2_surf->base.Height;
>  
> -   *out_count = dri2_surf->buffer_count;
> -
> return dri2_surf->buffers;
>  }
>  
> diff --git a/src/egl/drivers/dri2/platform_drm.c
> b/src/egl/drivers/dri2/platform_drm.c
> index 8e12aed0b3..aa3937581a 100644
> --- a/src/egl/drivers/dri2/platform_drm.c
> +++ b/src/egl/drivers/dri2/platform_drm.c
> @@ -321,10 +321,9 @@ dri2_drm_get_buffers_with_format(__DRIdrawable
> *driDrawable,
> struct dri2_egl_surface *dri2_surf = loaderPrivate;
> int i, j;
>  
> -   dri2_surf->buffer_count = 0;
> for (i = 0, j = 0; i < 2 * count; i += 2, j++) {
>assert(attachments[i] < __DRI_BUFFER_COUNT);
> -  assert(dri2_surf->buffer_count < 5);
> +  assert(j < ARRAY_SIZE(dri2_surf->buffers));
>  
>switch (attachments[i]) {
>case __DRI_BUFFER_BACK_LEFT:
> diff --git a/src/egl/drivers/dri2/platform_x11.c
> b/src/egl/drivers/dri2/platform_x11.c
> index c10cd84fce..b01f739010 100644
> --- a/src/egl/drivers/dri2/platform_x11.c
> +++ b/src/egl/drivers/dri2/platform_x11.c
> @@ -445,7 +445,6 @@ dri2_x11_process_buffers(struct dri2_egl_surface
> *dri2_surf,
>dri2_egl_display(dri2_surf->base.Resource.Display);
> xcb_rectangle_t rectangle;
>  
> -   dri2_surf->buffer_count = count;
> dri2_surf->have_fake_front = false;
>  
> /* This assumes the DRI2 buffer attachment tokens matches the

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Re: [Mesa-dev] [v2 8/16] i965/wm: Use isl for filling tex image parameters

[Jason Ekstrand]

Both 7.5 and 8 are

Reviewed-by: Jason Ekstrand 

On Tue, Jul 18, 2017 at 12:23 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> This helps to drop dependency to miptree::total_height which is
> used in brw_miptree_get_vertical_slice_pitch().
>
> CC: Jason Ekstrand 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_tex_layout.c   |   2 +-
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 100
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h|   9 --
>  3 files changed, 19 insertions(+), 92 deletions(-)
>

It also has a nice diffstat. :-)


>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index d06d654797..c76e87bc06 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -309,7 +309,7 @@ brw_miptree_get_horizontal_slice_pitch(const struct
> brw_context *brw,
> }
>  }
>
> -unsigned
> +static unsigned
>  brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
>   const struct intel_mipmap_tree *mt,
>   unsigned level)
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index da5c5128c1..d88a2fb2be 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1633,73 +1633,6 @@ update_buffer_image_param(struct brw_context *brw,
>  }
>
>  static void
> -update_texture_image_param(struct brw_context *brw,
> -   struct gl_image_unit *u,
> -   unsigned surface_idx,
> -   struct brw_image_param *param)
> -{
> -   struct intel_mipmap_tree *mt = intel_texture_object(u->TexObj)->mt;
> -
> -   update_default_image_param(brw, u, surface_idx, param);
> -
> -   param->size[0] = minify(mt->logical_width0, u->Level);
> -   param->size[1] = minify(mt->logical_height0, u->Level);
> -   param->size[2] = (!u->Layered ? 1 :
> - u->TexObj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
> - u->TexObj->Target == GL_TEXTURE_3D ?
> - minify(mt->logical_depth0, u->Level) :
> - mt->logical_depth0);
> -
> -   intel_miptree_get_image_offset(mt, u->Level, u->_Layer,
> -  >offset[0],
> -  >offset[1]);
> -
> -   param->stride[0] = mt->cpp;
> -   param->stride[1] = mt->pitch / mt->cpp;
> -   param->stride[2] =
> -  brw_miptree_get_horizontal_slice_pitch(brw, mt, u->Level);
> -   param->stride[3] =
> -  brw_miptree_get_vertical_slice_pitch(brw, mt, u->Level);
> -
> -   if (mt->tiling == I915_TILING_X) {
> -  /* An X tile is a rectangular block of 512x8 bytes. */
> -  param->tiling[0] = _mesa_logbase2(512 / mt->cpp);
> -  param->tiling[1] = _mesa_logbase2(8);
> -
> -  if (brw->has_swizzling) {
> - /* Right shifts required to swizzle bits 9 and 10 of the memory
> -  * address with bit 6.
> -  */
> - param->swizzling[0] = 3;
> - param->swizzling[1] = 4;
> -  }
> -   } else if (mt->tiling == I915_TILING_Y) {
> -  /* The layout of a Y-tiled surface in memory isn't really
> fundamentally
> -   * different to the layout of an X-tiled surface, we simply pretend
> that
> -   * the surface is broken up in a number of smaller 16Bx32 tiles,
> each
> -   * one arranged in X-major order just like is the case for X-tiling.
> -   */
> -  param->tiling[0] = _mesa_logbase2(16 / mt->cpp);
> -  param->tiling[1] = _mesa_logbase2(32);
> -
> -  if (brw->has_swizzling) {
> - /* Right shift required to swizzle bit 9 of the memory address
> with
> -  * bit 6.
> -  */
> - param->swizzling[0] = 3;
> -  }
> -   }
> -
> -   /* 3D textures are arranged in 2D in memory with 2^lod slices per
> row.  The
> -* address calculation algorithm (emit_address_calculation() in
> -* brw_fs_surface_builder.cpp) handles this as a sort of tiling with
> -* modulus equal to the LOD.
> -*/
> -   param->tiling[2] = (u->TexObj->Target == GL_TEXTURE_3D ? u->Level :
> -   0);
> -}
> -
> -static void
>  update_image_surface(struct brw_context *brw,
>   struct gl_image_unit *u,
>   GLenum access,
> @@ -1727,6 +1660,19 @@ update_image_surface(struct brw_context *brw,
>} else {
>   struct intel_texture_object *intel_obj =
> intel_texture_object(obj);
>   struct intel_mipmap_tree *mt = intel_obj->mt;
> + const unsigned num_layers = (!u->Layered ? 1 :
> +  obj->Target == GL_TEXTURE_CUBE_MAP
> ? 6 :
> +  

Re: [Mesa-dev] [7.5/16] intel/isl: Take 3D surfaces into account in image params

[Jason Ekstrand]

I looked at Vulkan and I don't *think* this will break anything.

On Tue, Jul 18, 2017 at 12:23 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> CC: Jason Ekstrand 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/intel/isl/isl_storage_image.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/isl/isl_storage_image.c
> b/src/intel/isl/isl_storage_image.c
> index 4c56e787b5..a8aebce6d4 100644
> --- a/src/intel/isl/isl_storage_image.c
> +++ b/src/intel/isl/isl_storage_image.c
> @@ -226,8 +226,12 @@ isl_surf_fill_image_param(const struct isl_device
> *dev,
> view->base_array_layer;
> }
>
> -   isl_surf_get_image_offset_el(surf, view->base_level,
> view->base_array_layer,
> -0, >offset[0],  >offset[1]);
> +   isl_surf_get_image_offset_el(surf, view->base_level,
> +surf->dim == ISL_SURF_DIM_3D ?
> +   0 : view->base_array_layer,
> +surf->dim == ISL_SURF_DIM_3D ?
> +   view->base_array_layer : 0,
> +>offset[0],  >offset[1]);
>
> const int cpp = isl_format_get_layout(surf->format)->bpb / 8;
> param->stride[0] = cpp;
> --
> 2.11.0
>
>
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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #2 from Brad King  ---
I have a script that updates Mesa every night.  After noticing the problem I
bisected back to 147d7fb772.  I just tried with current master (a522ce9977) and
it still happens.  For reference, I'm building Mesa as follows:

./autogen.sh \
  --prefix="$prefix" \
  --enable-debug \
  --disable-dri \
  --disable-egl \
  --disable-gbm \
  --disable-gles1 \
  --disable-gles2 \
  --disable-shared-glapi \
  --with-platforms=x11 \
  --enable-glx=gallium-xlib \
  --enable-gallium-osmesa \
  --with-gallium-drivers=swrast \
  --enable-gallium-llvm=yes \
LLVM_CONFIG=/usr/bin/llvm-config-3.8 \
  --enable-llvm-shared-libs \
  --with-gl-lib-name=MesaGL \
  --with-osmesa-lib-name=MesaOSMesa &&

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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

Brian Paul  changed:

   What|Removed |Added

 CC||charmai...@vmware.com

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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

Brian Paul  changed:

   What|Removed |Added

 CC||bri...@vmware.com

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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

--- Comment #1 from Brian Paul  ---
Hi Brad,

I'm not able to repro the problem so far.  Valgrind shows no errors with your
trace.  I've both tried Mesa @ 147d7fb772 and ToT as of this morning
(a522ce997779).  I tested with the llvmpipe driver (though I don't think the
driver should matter in this case).  Any ideas?

There have been a couple bug-fix follow-on commits since 147d7fb772 so maybe
you can re-test with latest Mesa.

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[Mesa-dev] [Bug 101829] read-after-free in st_framebuffer_validate

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101829

Bug ID: 101829
   Summary: read-after-free in st_framebuffer_validate
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/swr
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: brad.k...@kitware.com
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 132745
  --> https://bugs.freedesktop.org/attachment.cgi?id=132745=edit
apitrace of test that crashes

Since commit 147d7fb772 (st/mesa: add a winsys buffers list in st_context,
2017-07-10) one of VTK's tests crashes with Mesa.  Here is output from
valgrind's memcheck tool:

Invalid read of size 4
   at 0xE986121: st_framebuffer_validate (st_manager.c:180)
   by 0xE9876C8: st_api_make_current (st_manager.c:851)
   by 0xE600FBA: XMesaMakeCurrent2 (xm_api.c:1307)
   by 0xE5FBD01: glXMakeContextCurrent (glx_api.c:1239)
   by 0x4034FAF: ??? (in
/usr/lib/x86_64-linux-gnu/qt5/plugins/xcbglintegrations/libqxcb-glx-integration.so)
   by 0x8D1ECB7: QOpenGLContext::makeCurrent(QSurface*) (in
/usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.7.1)
   by 0x8751910: QOpenGLWidget::makeCurrent() (in
/usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)
   by 0x8751EB7: ??? (in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)
   by 0x8752722: ??? (in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)
   by 0x93CF876: QObject::~QObject() (in
/usr/lib/x86_64-linux-gnu/libQt5Core.so.5.7.1)
   by 0x872D922: QWidget::~QWidget() (in
/usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)
   by 0x522767F: QVTKOpenGLWidget::~QVTKOpenGLWidget()
(QVTKOpenGLWidget.cxx:136)
 Address 0x295d09b0 is 0 bytes inside a block of size 40 free'd
   at 0x4C2CDDB: free (vg_replace_malloc.c:530)
   by 0xE602156: xmesa_destroy_st_framebuffer (xm_st.c:324)
   by 0xE5FFEC1: xmesa_free_buffer (xm_api.c:601)
   by 0xE600E19: XMesaDestroyBuffer (xm_api.c:1241)
   by 0xE6013C0: XMesaGarbageCollect (xm_api.c:1447)
   by 0xE5FC137: glXDestroyContext (glx_api.c:1426)
   by 0x4033200: ??? (in
/usr/lib/x86_64-linux-gnu/qt5/plugins/xcbglintegrations/libqxcb-glx-integration.so)
   by 0x4033228: ??? (in
/usr/lib/x86_64-linux-gnu/qt5/plugins/xcbglintegrations/libqxcb-glx-integration.so)
   by 0x8D202CA: QOpenGLContext::destroy() (in
/usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.7.1)
   by 0x8D205F6: QOpenGLContext::~QOpenGLContext() (in
/usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.7.1)
   by 0x8D20608: QOpenGLContext::~QOpenGLContext() (in
/usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.7.1)
   by 0x8722097: QWidgetPrivate::deleteTLSysExtra() (in
/usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)
 Block was alloc'd at
   at 0x4C2DBC5: calloc (vg_replace_malloc.c:711)
   by 0xE601FB5: xmesa_create_st_framebuffer (xm_st.c:285)
   by 0xE5FFD9E: create_xmesa_buffer (xm_api.c:543)
   by 0xE600A67: XMesaCreateWindowBuffer (xm_api.c:1100)
   by 0xE5FBBD7: glXMakeContextCurrent (glx_api.c:1200)
   by 0xE5FBDE6: glXMakeCurrent (glx_api.c:1273)
   by 0x4034517: ??? (in
/usr/lib/x86_64-linux-gnu/qt5/plugins/xcbglintegrations/libqxcb-glx-integration.so)
   by 0x40328B6: ??? (in
/usr/lib/x86_64-linux-gnu/qt5/plugins/xcbglintegrations/libqxcb-glx-integration.so)
   by 0x40F9040: QXcbIntegration::createPlatformOpenGLContext(QOpenGLContext*)
const (in /usr/lib/x86_64-linux-gnu/libQt5XcbQpa.so.5.7.1)
   by 0x8D208CC: QOpenGLContext::create() (in
/usr/lib/x86_64-linux-gnu/libQt5Gui.so.5.7.1)
   by 0x8750CFD: ??? (in /usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)
   by 0x8751129: QOpenGLWidget::resizeEvent(QResizeEvent*) (in
/usr/lib/x86_64-linux-gnu/libQt5Widgets.so.5.7.1)

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Re: [Mesa-dev] [PATCH] radeonsi: add back the USE_MININUM_PRIORITY flag to the low-prio compiler queue

[Nicolai Hähnle]

On 17.07.2017 17:56, Marek Olšák wrote:

From: Marek Olšák 

Accidentally removed in 9f320e0a387a1009c5218daf130b3b754a3c2800.


Reviewed-by: Nicolai Hähnle 



---
  src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 4df60b6..0bc3002 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -964,21 +964,22 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 32, num_compiler_threads,
 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
si_destroy_shader_cache(sscreen);
FREE(sscreen);
return NULL;
}
  
  	if (!util_queue_init(>shader_compiler_queue_low_priority,

 "si_shader_low",
 32, num_compiler_threads,
-UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
+UTIL_QUEUE_INIT_RESIZE_IF_FULL |
+UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
   si_destroy_shader_cache(sscreen);
   FREE(sscreen);
   return NULL;
}
  
  	si_handle_env_var_force_family(sscreen);
  
  	if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))

si_init_perfcounters(sscreen);
  




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Re: [Mesa-dev] [PATCH 3/4] docs: avoid overwrite of LD_LIBRARY_PATH during basic testing

[Andres Gomez]

On Tue, 2017-07-18 at 10:48 +0100, Emil Velikov wrote:
> On 15 July 2017 at 17:01, Andres Gomez  wrote:
> > On Mon, 2017-07-10 at 12:19 +0100, Emil Velikov wrote:
> > > On 8 July 2017 at 20:59, Andres Gomez  wrote:
> > > > The LD_LIBRARY_PATH environment variable could be already defined so
> > > > we extend it and restore it rather than just overwriting it.
> > > > 
> > > 
> > > Hmm, what are you doing to actually require LD_LIBRARY_PATH in the first 
> > > place?
> > > It makes it somewhat uneasy that one will have that in their setup.
> > 
> > My everyday's work is done in a JHBuild env that already uses this
> > variable for mesa dependencies. I would have assumed that this is
> > actually quite normal for most of mesa developers, although maybe I'm
> > wrong ...
> > 
> 
> This is the first time I hear anyone working on Mesa use JHBuild.
> There could be some though ;-)



Well, I meant that I assumed it was normal to have LD_LIBRARY_PATH
customized to point to the dependencies, not that it was normal to use
JHBuild 

> 
> > > 
> > > > Signed-off-by: Andres Gomez 
> > > > ---
> > > >  docs/releasing.html | 4 +++-
> > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/docs/releasing.html b/docs/releasing.html
> > > > index 8e6e4d1a6d..99235d8412 100644
> > > > --- a/docs/releasing.html
> > > > +++ b/docs/releasing.html
> > > > @@ -472,7 +472,8 @@ Here is one solution that I've been using.
> > > > __glxgears_cmd='glxgears 2>1 | grep -v "configuration 
> > > > file"'
> > > > __es2info_cmd='es2_info 2>1 | egrep 
> > > > "GL_VERSION|GL_RENDERER|.*dri\.so"'
> > > > __es2gears_cmd='es2gears_x11 2>1 | grep -v "configuration 
> > > > file"'
> > > > -   export LD_LIBRARY_PATH=`pwd`/test/usr/local/lib/
> > > > +   'x$LD_LIBRARY_PATH' -ne 'x'  
> > > > __old_ld='$LD_LIBRARY_PATH'  __token=':'
> > > > +   export 
> > > > LD_LIBRARY_PATH=`pwd`/test/usr/local/lib/'${__token}${__old_ld}'
> > > 
> > > AFAICT you don't need __token.
> > 
> > You do if you want to avoid adding ":" at the end when LD_LIBRARY_PATH
> > is not defined previously. It can be done in other ways but I thought
> > this to be the simplest/easiest to read.
> > 
> 
> I was thinking about adding the colon, unconditionally. AFAICT things
> work perfectly fine with it. Even if one extends LD_LIBRARY_PATH at a
> later stage.

Mmmm ... didn't think that was also valid but, I suppose why not. In
any case, it feels odd to me. I don't remember seeing env variables
like that finishing in ":" before.

Not hard thoughts on this. If you prefer to remove __token, I'm OK with
it.

> But if you really want to avoid it this is the shortest way, indeed.
> 
> -Emil
> 
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Re: [Mesa-dev] [PATCH v3 1/2] gallium/util: Implement util_format_is_etc

[Ilia Mirkin]

Reviewed-by: Ilia Mirkin 

On Tue, Jul 18, 2017 at 6:01 AM,   wrote:
> From: "Wladimir J. van der Laan" 
>
> This is the equivalent of util_format_is_s3tc, but for
> ETC.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/auxiliary/util/u_format.h | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/src/gallium/auxiliary/util/u_format.h 
> b/src/gallium/auxiliary/util/u_format.h
> index d055778..2318e97 100644
> --- a/src/gallium/auxiliary/util/u_format.h
> +++ b/src/gallium/auxiliary/util/u_format.h
> @@ -496,6 +496,19 @@ util_format_is_s3tc(enum pipe_format format)
>  }
>
>  static inline boolean
> +util_format_is_etc(enum pipe_format format)
> +{
> +   const struct util_format_description *desc = 
> util_format_description(format);
> +
> +   assert(desc);
> +   if (!desc) {
> +  return FALSE;
> +   }
> +
> +   return desc->layout == UTIL_FORMAT_LAYOUT_ETC ? TRUE : FALSE;
> +}
> +
> +static inline boolean
>  util_format_is_srgb(enum pipe_format format)
>  {
> const struct util_format_description *desc = 
> util_format_description(format);
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 4/4] dri: Add KHR_no_error toggle to driconf

[Emil Velikov]

On 18 July 2017 at 09:26, Grigori Goronzy  wrote:
> On 2017-07-17 19:21, Emil Velikov wrote:
>>
>> On 13 July 2017 at 12:09, Grigori Goronzy  wrote:
>>>
>>> On 2017-07-12 15:15, Emil Velikov wrote:


 As mentioned in earlier commit no_error should be device agnostic.
 Hence removing the st/dri bits and adding a DRI_CONF_MESA_NO_ERROR()
 line next to DRI_CONF_VBLANK_MODE seems like the better solution.

>>>
>>> Hm, driconf overrides are typically set per screen and/or driver, so that
>>> won't work. The overrides will be ignored because of screen/driver
>>> mismatch.
>>> So I think it needs to be implemented separately for each classic driver.
>>> I'll keep this part to the Gallium state tracker for now.
>>>
>> Hmm my understanding was completely different. Have you tested my
>> suggestion or this is your assumption?
>>
>
> Sure, I have tested this. Check where driParseConfigFiles() is used in the
> code. Different parts of the stack have completely separate driconf
> databases, which are associated with different "driver names" (in quotes,
> because it's a rather confusing description, given the usage). The generic
> DRI layer that handles vblank_mode uses "dri2" as "driver name". Other parts
> have other different "driver names", all of which aren't obvious or
> documented, and most of the classic Mesa drivers also have separate driconf
> databases. So I added mesa_no_error to the generic DRI layer, but it only
> produced any result when an option is added to a "dri2" section of the
> driconf XML, which makes it somewhat strange and impractical to use. Of
> course vblank_mode has the same issue. I think this isn't really a good
> design and should be addressed at same point. Maybe it could be a good
> option to move to a single global database, or a hierarchical database
> (somewhat like LDAP). There are various possible options.
>
The XML device section allows empty "driver name". Hence something
like the following should just work.
If it doesn't we have a bug somewhere. On the confusing "dri2" name:
we could purge relatively easy - but that for another day.


   
   ...
   
   
   
   ...





> At this time, for practical reasons, I think it makes sense to add the
> mesa_no_error flag at the graphics driver layer only. That makes it easy to
> override this setting with the "driconf" GUI tool and there is no obscure
> "driver name" magic going on that users should not need to know about.
>
As mentioned earlier - keeping it at Gallium level (current solution
is not at driver level) makes perfect sense.


-Emil
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Re: [Mesa-dev] [PATCH mesa] vulkan/util: fix typo in comment

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 18/07/17 11:08, Eric Engestrom wrote:

Signed-off-by: Eric Engestrom 
---
  src/vulkan/util/gen_enum_to_str.py | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vulkan/util/gen_enum_to_str.py 
b/src/vulkan/util/gen_enum_to_str.py
index fb31addf94..ef37972c20 100644
--- a/src/vulkan/util/gen_enum_to_str.py
+++ b/src/vulkan/util/gen_enum_to_str.py
@@ -19,7 +19,7 @@
  # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
  # SOFTWARE.
  
-"""Create enum to string functions for vulking using vk.xml."""

+"""Create enum to string functions for vulkan using vk.xml."""
  
  from __future__ import print_function

  import argparse



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Re: [Mesa-dev] [PATCH 1.2/8 v2] spirv: Generate spirv_info.c

[Emil Velikov]

On 17 July 2017 at 20:31, Ian Romanick  wrote:
> From: Ian Romanick 
>
> The old table based spirv_*_to_string functions would return NULL for
> any values "inside" the table that didn't have entries.  The tables also
> needed to be updated by hand each time a new spirv.h was imported.
> Generate the file instead.
>
> v2: Make this script work more like src/mesa/main/format_fallback.py.
> Suggested by Jason.  Remove SCons supports.  Suggested by Jason and
> Emil.  Put all the build work in Makefile.nir.am in lieu of adding a new
> Makefile.spirv.am.  Suggested by Emil.  Add support for Android builds
> based on code provided by Emil.
>
> Signed-off-by: Ian Romanick 
> Suggested-by: Jason Ekstrand 
For the build bits
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 1/2] egl/drm: Fix misused x and y offsets on swrast_put_image2()

[Eric Engestrom]

On Tuesday, 2017-07-18 03:11:50 +0900, Gwan-gyeong Mun wrote:
> It fixes misused x and y offsets on the calculation of the memory copy 
> regions.
> And it adds limits of the height and the width on the copy region.
> 
> Signed-off-by: Mun Gwan-gyeong 

Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform"
Cc: Giovanni Campagna 

> ---
>  src/egl/drivers/dri2/platform_drm.c | 17 +++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/platform_drm.c 
> b/src/egl/drivers/dri2/platform_drm.c
> index 4176fde7d1..36e9c74a56 100644
> --- a/src/egl/drivers/dri2/platform_drm.c
> +++ b/src/egl/drivers/dri2/platform_drm.c
> @@ -528,6 +528,9 @@ swrast_put_image2(__DRIdrawable *driDrawable,
> struct dri2_egl_surface *dri2_surf = loaderPrivate;
> int internal_stride;
> struct gbm_dri_bo *bo;
> +   int x_offset = x * 4;
> +   int copy_width = width * 4;

These `4` look a bit magical here. I also don't think only 32bpp
formats are supported here; I see GBM_FORMAT_RGB565 a few lines below
for instance.
Any chance you could get the bpp from `bo->base.format` instead?

The names could also be improved: x_bytes & width_bytes maybe?

With that addressed, both patches are
Reviewed-by: Eric Engestrom 

> +   char *src, *dst;
>  
> if (op != __DRI_SWRAST_IMAGE_OP_DRAW &&
> op != __DRI_SWRAST_IMAGE_OP_SWAP)
> @@ -542,9 +545,19 @@ swrast_put_image2(__DRIdrawable *driDrawable,
>  
> internal_stride = bo->base.stride;
>  
> +   if (height > dri2_surf->base.Height - y)
> +  height = dri2_surf->base.Height - y;
> +
> +   if (copy_width > internal_stride - x_offset)
> +  copy_width = internal_stride - x_offset;
> +
> +   dst = bo->map + x_offset + (y * internal_stride);
> +   src = data;
> +
> for (int i = 0; i < height; i++) {
> -  memcpy(bo->map + (x + i) * internal_stride + y,
> - data + i * stride, stride);
> +  memcpy(dst, src, copy_width);
> +  dst += internal_stride;
> +  src += stride;
> }
>  
> gbm_dri_bo_unmap_dumb(bo);
> -- 
> 2.13.3
> 
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[Mesa-dev] [PATCH mesa] vulkan/util: fix typo in comment

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/vulkan/util/gen_enum_to_str.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vulkan/util/gen_enum_to_str.py 
b/src/vulkan/util/gen_enum_to_str.py
index fb31addf94..ef37972c20 100644
--- a/src/vulkan/util/gen_enum_to_str.py
+++ b/src/vulkan/util/gen_enum_to_str.py
@@ -19,7 +19,7 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-"""Create enum to string functions for vulking using vk.xml."""
+"""Create enum to string functions for vulkan using vk.xml."""
 
 from __future__ import print_function
 import argparse
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH v3 2/2] etnaviv: Add support for ETC2 texture compression

[laanwj]

From: "Wladimir J. van der Laan" 

Add support for ETC2 compressed textures in the etnaviv driver.

One step closer towards GL ES 3 support.

For now, treat SRGB and RGB formats the same. It looks like these are
distinguished using a different bit in sampler state, and not part of
the format, but I have not yet been able to confirm this for sure.

(Only enabled on GC3000+ for now, as the GC2000 ETC2 decoder
implementation is buggy and we don't work around that)

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/etnaviv/etnaviv_format.c | 11 +++
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 12 +++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_format.c 
b/src/gallium/drivers/etnaviv/etnaviv_format.c
index 354dc20..492499a 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_format.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_format.c
@@ -233,6 +233,17 @@ static struct etna_format formats[PIPE_FORMAT_COUNT] = {
_T(DXT3_RGBA, DXT2_DXT3, SWIZ(X, Y, Z, W), NONE),
_T(DXT5_RGBA, DXT4_DXT5, SWIZ(X, Y, Z, W), NONE),
 
+   _T(ETC2_RGB8,   EXT_NONE | EXT_FORMAT,  SWIZ(X, 
Y, Z, W), NONE), /* Extd. format NONE doubles as ETC2_RGB8 */
+   _T(ETC2_SRGB8,  EXT_NONE | EXT_FORMAT,  SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RGB8A1, EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_SRGB8A1,EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RGBA8,  EXT_RGBA8_ETC2_EAC | EXT_FORMAT,SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_SRGBA8, EXT_RGBA8_ETC2_EAC | EXT_FORMAT,SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_R11_UNORM,  EXT_R11_EAC | EXT_FORMAT,   SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_R11_SNORM,  EXT_SIGNED_R11_EAC | EXT_FORMAT,SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RG11_UNORM, EXT_RG11_EAC | EXT_FORMAT,  SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RG11_SNORM, EXT_SIGNED_RG11_EAC | EXT_FORMAT,   SWIZ(X, 
Y, Z, W), NONE),
+
/* YUV */
_T(YUYV, YUY2, SWIZ(X, Y, Z, W), YUY2),
_T(UYVY, UYVY, SWIZ(X, Y, Z, W), NONE),
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 96f9a8e..5dc436d 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -471,9 +471,19 @@ gpu_supports_texure_format(struct etna_screen *screen, 
uint32_t fmt,
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
   supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 
-   if (fmt & EXT_FORMAT)
+   if (fmt & EXT_FORMAT) {
   supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 
+  /* ETC1 is checked above, as it has its own feature bit. ETC2 is
+   * supported with HALTI0, however that implementation is buggy in 
hardware.
+   * The blob driver does per-block patching to work around this. As this
+   * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
+   * only.
+   */
+  if (util_format_is_etc(format))
+ supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
+   }
+
if (!supported)
   return false;
 
-- 
2.7.4

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[Mesa-dev] [PATCH v3 1/2] gallium/util: Implement util_format_is_etc

[laanwj]

From: "Wladimir J. van der Laan" 

This is the equivalent of util_format_is_s3tc, but for
ETC.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/auxiliary/util/u_format.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_format.h 
b/src/gallium/auxiliary/util/u_format.h
index d055778..2318e97 100644
--- a/src/gallium/auxiliary/util/u_format.h
+++ b/src/gallium/auxiliary/util/u_format.h
@@ -496,6 +496,19 @@ util_format_is_s3tc(enum pipe_format format)
 }
 
 static inline boolean 
+util_format_is_etc(enum pipe_format format)
+{
+   const struct util_format_description *desc = 
util_format_description(format);
+
+   assert(desc);
+   if (!desc) {
+  return FALSE;
+   }
+
+   return desc->layout == UTIL_FORMAT_LAYOUT_ETC ? TRUE : FALSE;
+}
+
+static inline boolean 
 util_format_is_srgb(enum pipe_format format)
 {
const struct util_format_description *desc = 
util_format_description(format);
-- 
2.7.4

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