Re: [Mesa-dev] [PATCH v3 00/10] glsl_to_tgsi: Further improvement of lifetime tracking for register merge

[Gert Wollny]

Hi, 

I'd like to send out a ping for this series, 

many thanks, 
Gert 

Am Mittwoch, den 25.10.2017, 11:51 +0200 schrieb Gert Wollny:
> Dear all, 
> 
> this is a minor update to the patch set that adds enhanced tracking
> of IF/ELSE branches and tracking of reladdr* registers for the
> register_merge step.
> 
> So far patches 1 & 5 (now 8) are
> 
>   Reviewed-by: Nicolai Hähnle 
> 
> Changes w.r.t. v2: 
> 
> * patch 9: make the creation of register description tuples explicit
> because 
>   this is what in c++11 is actually required (This slipped before
> because it 
>   seems that g++-7.2 handles tuple initialization like it was c++17,
> also with
>   its default setting -std=c++14). 
> 
> v1: 
> 
> * patches 2-4(new): As suggested by Nikolai, these patches unify the
> test classes 
>   with respect to the different register inputs (at this point: plain
> and with 
>   swizzle). In addition, some comments are corrected and the used of
> white spaces 
>   in the test cases is made more consistent. 
> * patch 5: correct the debug output for indirect addressing. Nikolai
> suggested that 
>   another patch might be in order to properly propagate the
> information when and 
>   which address register is used, but since st_*_reg is passed
> through various 
>   levels by value, I'd prefer to deal with that in another, dedicated
> patch series.
> * patch 6: Further improve the tracking algorithm, and, as requested
> by Nikolai, 
>   rename some variables and add comments to make the algorithm
> clearer.
> * patch 7: Add yet more tests. 
> * patch 9: Update the tests to adhere to the new, unified interface. 
> * patch 10 (new): remove the no longer needed assert for the use of
> address registers 
>   in register_merge (I was considering to add this to 8, but since
> that one was already 
>   reviewed ...)
> 
> many thanks for any comments, 
> Gert
> 
> 
> Gert Wollny (10):
>   mesa/st/tests: Fix zero-byte allocation leaks
>   mesa/st/tests: unify MockCodeLine* classes
>   mesa/st/tests: base check of number of registers on opcode info
>   mesa/st/tests: cleanup whitespace usage and correct some comments
>   mesa/st/glsl_to_tgsi: Correct debug output for indirect access
>   mesa/st/glsl_to_tgsi: Add tracking of ifelse writes in register
> merging
>   mesa/st/tests: Add tests for improved tracking of temporaries
>   mesa/st/glsl_to_tgsi: Add tracking of indirect addressing registers
>   mesa/st/tests: Add tests for lifetime tracking with indirect
> addressing
>   mesa/st/glsl_to_tgsi: remove now unneeded assert.
> 
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp |1 -
>  .../state_tracker/st_glsl_to_tgsi_temprename.cpp   |  540 +++--
>  .../tests/test_glsl_to_tgsi_lifetime.cpp   | 1278
> +++-
>  3 files changed, 1401 insertions(+), 418 deletions(-)
> 
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Re: [Mesa-dev] [PATCH 08/23] gallium/aux/util/u_format_latc.c: Fix various -Wunused-param warnings,

[Gert Wollny]

Hello Brian, 

thanks for the review, one thing though ...

Am Montag, den 13.11.2017, 09:31 -0700 schrieb Brian Paul:

> Also, can you please wrap long lines at 78 columns?

I'm kind of in doubt whether the hard limit of 78 makes sense here,
i.e. when I do this then I will have to put every parameter on a single
line or break the rule that the parameters are aligned to the opening
brace of the parameter list. 

If you say that one of the two is fine then I will do this - but most
of the files in gallium/aux/util break the 78 column rule, because the
function names are very long, and some authors didn't even bother to 
break very long lines. Do you suggest that I should correct these
formattings too? I would do this in separate patches in this series
though. 

best, 
Gert  
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[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

--- Comment #3 from Tapani Pälli  ---
(In reply to Tapani Pälli from comment #1)
> This very likely bisects to commit 688d6958682f96aaeb88aa8cc23cc5c9886a6be4
> so I'm taking this bug.

Or maybe not since this was seen also with nouveau. I will anyway try to bisect
when this started.

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[Mesa-dev] [PATCH] spirv: fix typo on DO NOT EDIT header

[Alejandro Piñeiro]

Introduced on commit 157c9a13414b524ce98ea0ea07fce819efc1ba65
---
 src/compiler/spirv/spirv_info_c.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/spirv/spirv_info_c.py 
b/src/compiler/spirv/spirv_info_c.py
index 11235cfa3e4..d898bf0131b 100644
--- a/src/compiler/spirv/spirv_info_c.py
+++ b/src/compiler/spirv/spirv_info_c.py
@@ -52,7 +52,7 @@ def parse_args():
 return p.parse_args()
 
 TEMPLATE  = Template("""\
-/* DO NOT EDIT - This file generated automatically by spirv_info_c.py script */
+/* DO NOT EDIT - This file is generated automatically by spirv_info_c.py 
script */
 
 """ + COPYRIGHT + """\
 #include "spirv_info.h"
-- 
2.11.0

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[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

--- Comment #2 from Tapani Pälli  ---
BTW how did you install plasma 5.11.3? Kubuntu artful has 5.10.5 by default.

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[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

Tapani Pälli  changed:

   What|Removed |Added

 Status|NEW |ASSIGNED
   Assignee|mesa-dev@lists.freedesktop. |lem...@gmail.com
   |org |

--- Comment #1 from Tapani Pälli  ---
This very likely bisects to commit 688d6958682f96aaeb88aa8cc23cc5c9886a6be4 so
I'm taking this bug.

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Re: [Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

[Jason Ekstrand]

On November 13, 2017 22:54:02 Matt Turner  wrote:


On Mon, Nov 13, 2017 at 10:06 PM, Jason Ekstrand  wrote:

On Mon, Nov 13, 2017 at 3:23 PM, Matt Turner  wrote:


The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.

For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.

Fixes the following test on CHV, BXT, and GLK:
   KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
---
 src/intel/compiler/brw_fs_nir.cpp | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 38d0d357e8..e266837ece 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1395,10 +1395,26 @@ fs_visitor::nir_emit_alu(const fs_builder ,
nir_alu_instr *instr)

case nir_op_extract_u8:
case nir_op_extract_i8: {
-  const brw_reg_type type = brw_int_type(1, instr->op ==
nir_op_extract_i8);
   nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
   assert(byte != NULL);
-  bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+
+  /* MOV does not support a 64-bit destination and a byte source */
+  if (nir_dest_bit_size(instr->dest.dest) == 64) {



Do we also want to predicate this on "devinfo->is_cherrytrail ||
gen_device_info_is_gen9lp(devinfo)" as well as bit size?  Big-core can
handle it just fine.


Actually, the documentation says it isn't allowed:

BDW+
There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB. Use
two instructions and a word or DWord intermediate integer type.


Interesting.  Mind throwing that in the comment above?  With that,

Reviewed-by: Jason Ekstrand 

Thanks for fixing that.  I suppose we can probably revert my "fix" with the 
strides then...


--Jason


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Re: [Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

[Matt Turner]

On Mon, Nov 13, 2017 at 10:06 PM, Jason Ekstrand  wrote:
> On Mon, Nov 13, 2017 at 3:23 PM, Matt Turner  wrote:
>>
>> The MOV instruction can extract bytes to words/double words, and
>> words/double words to quadwords, but not byte to quadwords.
>>
>> For unsigned byte to quadword, we can read them as words and AND off the
>> high byte and extract to quadword in one instruction. For signed bytes,
>> we need to first sign extend to word and the sign extend that word to a
>> quadword.
>>
>> Fixes the following test on CHV, BXT, and GLK:
>>KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
>> ---
>>  src/intel/compiler/brw_fs_nir.cpp | 20 ++--
>>  1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_fs_nir.cpp
>> b/src/intel/compiler/brw_fs_nir.cpp
>> index 38d0d357e8..e266837ece 100644
>> --- a/src/intel/compiler/brw_fs_nir.cpp
>> +++ b/src/intel/compiler/brw_fs_nir.cpp
>> @@ -1395,10 +1395,26 @@ fs_visitor::nir_emit_alu(const fs_builder ,
>> nir_alu_instr *instr)
>>
>> case nir_op_extract_u8:
>> case nir_op_extract_i8: {
>> -  const brw_reg_type type = brw_int_type(1, instr->op ==
>> nir_op_extract_i8);
>>nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
>>assert(byte != NULL);
>> -  bld.MOV(result, subscript(op[0], type, byte->u32[0]));
>> +
>> +  /* MOV does not support a 64-bit destination and a byte source */
>> +  if (nir_dest_bit_size(instr->dest.dest) == 64) {
>
>
> Do we also want to predicate this on "devinfo->is_cherrytrail ||
> gen_device_info_is_gen9lp(devinfo)" as well as bit size?  Big-core can
> handle it just fine.

Actually, the documentation says it isn't allowed:

BDW+
There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB. Use
two instructions and a word or DWord intermediate integer type.
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Re: [Mesa-dev] [PATCH] st/atifs: merge gl_program and ati_fragment_shader

[Timothy Arceri]

On 14/11/17 13:30, Ian Romanick wrote:

On 11/10/2017 02:35 AM, Timothy Arceri wrote:

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 6b5c5bbb36..7c357b07ee 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2352,58 +2376,29 @@ struct gl_fragment_program_state
   */
  struct gl_compute_program_state
  {
 /** Currently enabled and valid program (including internal programs
  * and compiled shader programs).
  */
 struct gl_program *_Current;
  };
  
  
-/**

- * ATI_fragment_shader runtime state
- */
-
-struct atifs_instruction;
-struct atifs_setupinst;
-
-/**
- * ATI fragment shader
- */
-struct ati_fragment_shader
-{
-   GLuint Id;
-   GLint RefCount;
-   struct atifs_instruction *Instructions[2];
-   struct atifs_setupinst *SetupInst[2];
-   GLfloat Constants[8][4];
-   GLbitfield LocalConstDef;  /**< Indicates which constants have been set */
-   GLubyte numArithInstr[2];
-   GLubyte regsAssigned[2];
-   GLubyte NumPasses; /**< 1 or 2 */
-   GLubyte cur_pass;
-   GLubyte last_optype;
-   GLboolean interpinp1;
-   GLboolean isValid;
-   GLuint swizzlerq;
-   struct gl_program *Program;
-};
-


Other places in Mesa would do this by C-style subclassing of gl_program:

struct ati_fragment_shader {
struct gl_program Base;
struct atifs_instruction *Instructions[2];
struct atifs_setupinst *SetupInst[2];
GLfloat Constants[8][4];
GLbitfield LocalConstDef;  /**< Indicates which constants have been set */
GLubyte numArithInstr[2];
GLubyte regsAssigned[2];
GLubyte NumPasses; /**< 1 or 2 */
GLubyte cur_pass;
GLubyte last_optype;
GLboolean interpinp1;
GLboolean isValid;
GLuint swizzlerq;
};

Is there a reason to not do that here?


The st already does a C-style subclassing of gl_program, so it would 
start getting messy (which is what this patch tries to avoid in the 
first place). Also that type of subclassing is generally used for adding 
driver specific additional fields, not for specifying the basics of the 
program as we are doing here.


Having these fields inside gl_program simplifies things a bunch. Is 
there something you don't like? IMO this makes things more consistent as 
its how we handle arb programs. The final step is to make this all a 
union but that requires a bit of work on i915 and swrast,





  /**
   * Context state for GL_ATI_fragment_shader
   */
  struct gl_ati_fragment_shader_state
  {
 GLboolean Enabled;
 GLboolean Compiling;
 GLfloat GlobalConstants[8][4];
-   struct ati_fragment_shader *Current;
+   struct gl_program *Current;
  };
  
  /**

   *  Shader subroutine function definition
   */
  struct gl_subroutine_function
  {
 char *name;
 int index;
 int num_compat_types;

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[Mesa-dev] [AppVeyor] mesa master #6145 completed

[AppVeyor]

Build mesa 6145 completed



Commit fb0e9b5197 by Jason Ekstrand on 11/3/2017 11:11 PM:

i965: Track the depth and render caches separately\n\nPreviously, we just had one hash set for tracking depth and render\ncaches called brw_context::render_cache.  This is less than ideal\nbecause the depth and render caches are separate and we can't track\nmoves between the depth and the render caches.  This limitation led\nto some unnecessary flushing around the depth cache.  There are cases\n(mostly with BLORP) where we can end up touching a depth or stencil\nbuffer through the render cache.  To guard against this, blorp would\nunconditionally do a render_cache_set_check_flush on it's destination\nwhich meant that if you did any rendering (including a BLORP operation)\nto a given surface and then used it as a blorp destination, you would\nend up flushing it out of the render cache before rendering into it.\n\nThings get worse when you dig into the depth/stencil state code for\nregular GL draw calls.  Because we may end up rendering to a depth\nor stencil buffer via BLORP, we did a render_cache_set_check_flush on\nall depth and stencil buffers in brw_emit_depthbuffer to ensure that\nthey got flushed out of the render cache prior to using them for depth\nor stencil testing.  However, because we also need to track dirtiness\nfor depth and stencil so that we can implement depth and stencil\ntexturing correctly, we were adding all depth and stencil buffers to the\nrender cache set in brw_postdraw_set_buffers_need_resolve.  This meant\nthat, if anything caused 3DSTATE_DEPTH_BUFFER to get re-emitted\n(currently _NEW_BUFFERS, BRW_NEW_BATCH, and BRW_NEW_BLORP), we would\nalmost always do a full pipeline stall and render/depth cache flush.\n\nThe root cause of both of these problems is that we can't tell the\ndifference between the render and depth caches in our tracking.  This\ncommit splits our cache tracking into two sets, one for render and one\nfor depth, and properly handles transitioning between the two.  We still\nflush all the caches whenever anything needs to be flushed.  The idea is\nthat if we're going to take the hit of a flush and stall, we may as well\nflush everything in the hopes that we can avoid a flush by something\nelse later.\n\nReviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

[Jason Ekstrand]

On Mon, Nov 13, 2017 at 3:23 PM, Matt Turner  wrote:

> The MOV instruction can extract bytes to words/double words, and
> words/double words to quadwords, but not byte to quadwords.
>
> For unsigned byte to quadword, we can read them as words and AND off the
> high byte and extract to quadword in one instruction. For signed bytes,
> we need to first sign extend to word and the sign extend that word to a
> quadword.
>
> Fixes the following test on CHV, BXT, and GLK:
>KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 20 ++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index 38d0d357e8..e266837ece 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -1395,10 +1395,26 @@ fs_visitor::nir_emit_alu(const fs_builder ,
> nir_alu_instr *instr)
>
> case nir_op_extract_u8:
> case nir_op_extract_i8: {
> -  const brw_reg_type type = brw_int_type(1, instr->op ==
> nir_op_extract_i8);
>nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
>assert(byte != NULL);
> -  bld.MOV(result, subscript(op[0], type, byte->u32[0]));
> +
> +  /* MOV does not support a 64-bit destination and a byte source */
> +  if (nir_dest_bit_size(instr->dest.dest) == 64) {
>

Do we also want to predicate this on "devinfo->is_cherrytrail ||
gen_device_info_is_gen9lp(devinfo)" as well as bit size?  Big-core can
handle it just fine.


> + const brw_reg_type type = brw_int_type(2, instr->op ==
> nir_op_extract_i8);
> +
> + if (instr->op == nir_op_extract_i8) {
> +/* If we need to sign extend, extract to a word first */
> +fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
> +bld.MOV(w_temp, subscript(op[0], type, byte->u32[0]));
> +bld.MOV(result, w_temp);
> + } else {
> +/* Otherwise use an AND with 0xff and a word type */
> +bld.AND(result, subscript(op[0], type, byte->u32[0] / 2),
> brw_imm_uw(0xff));
> + }
> +  } else {
> + const brw_reg_type type = brw_int_type(1, instr->op ==
> nir_op_extract_i8);
> + bld.MOV(result, subscript(op[0], type, byte->u32[0]));
> +  }
>break;
> }
>
> --
> 2.13.6
>
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Re: [Mesa-dev] [PATCH 11/18] intel/tools/disasm: make sure that entire range is disassembled

[Rogovin, Kevin]

Your theory makes sense to me too; I suspect that something in the annotation 
code is the ultimate cause.


-Original Message-
From: Matt Turner [mailto:matts...@gmail.com] 
Sent: Monday, November 13, 2017 9:15 PM
To: Rogovin, Kevin 
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH 11/18] intel/tools/disasm: make sure that entire 
range is disassembled

On Mon, Nov 13, 2017 at 5:17 AM,   wrote:
> From: Kevin Rogovin 
>
> Without this patch, if a shader has errors, the disassembly of the 
> shader often stops after the first opcode that has errors.

I can't see anything wrong with the current code. If I'm right that
07/18 is wrong, could this be papering over the bug introduced in that patch 
which would have caused annotations to get lost?
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Re: [Mesa-dev] [PATCH 10/18] intel/tools/disasm: add gen_disasm_assembly_length function

[Rogovin, Kevin]

I need this function in order for the logger to save shader binary to disk.

-Kevin

-Original Message-
From: Matt Turner [mailto:matts...@gmail.com] 
Sent: Monday, November 13, 2017 9:43 PM
To: Rogovin, Kevin 
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH 10/18] intel/tools/disasm: add 
gen_disasm_assembly_length function

Pending the questions about 07/18, I don't think this should be necessary.
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[Mesa-dev] [AppVeyor] mesa master #6144 failed

[AppVeyor]

Build mesa 6144 failed


Commit 4b1e70cc57 by Jason Ekstrand on 11/14/2017 4:13 AM:

i965: Switch over to fully external-or-not MOCS scheme\n\nReviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH 1/2] nir: fill outputs_read field and add patch outputs read

[Dave Airlie]

From: Dave Airlie 

This is to be used for TCS optimisations on radv.
---
 src/compiler/nir/nir_gather_info.c | 29 ++---
 src/compiler/shader_info.h |  2 ++
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/compiler/nir/nir_gather_info.c 
b/src/compiler/nir/nir_gather_info.c
index 13cdae3..ab2d519 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -25,7 +25,8 @@
 #include "nir.h"
 
 static void
-set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len)
+set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
+bool is_output_read)
 {
for (int i = 0; i < len; i++) {
   assert(var->data.location != -1);
@@ -64,6 +65,14 @@ set_io_mask(nir_shader *shader, nir_variable *var, int 
offset, int len)
 shader->info.outputs_written |= bitfield;
  }
 
+ if (is_output_read) {
+if (is_patch_generic) {
+   shader->info.patch_outputs_read |= bitfield;
+} else {
+   shader->info.outputs_read |= bitfield;
+}
+ }
+
  if (var->data.fb_fetch_output)
 shader->info.outputs_read |= bitfield;
   }
@@ -75,7 +84,7 @@ set_io_mask(nir_shader *shader, nir_variable *var, int 
offset, int len)
  * represents a shader input or output.
  */
 static void
-mark_whole_variable(nir_shader *shader, nir_variable *var)
+mark_whole_variable(nir_shader *shader, nir_variable *var, bool is_output_read)
 {
const struct glsl_type *type = var->type;
 
@@ -88,7 +97,7 @@ mark_whole_variable(nir_shader *shader, nir_variable *var)
   var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
 : glsl_count_attribute_slots(type, false);
 
-   set_io_mask(shader, var, 0, slots);
+   set_io_mask(shader, var, 0, slots, is_output_read);
 }
 
 static unsigned
@@ -124,7 +133,7 @@ get_io_offset(nir_deref_var *deref)
  * occurs, then nothing will be marked and false will be returned.
  */
 static bool
-try_mask_partial_io(nir_shader *shader, nir_deref_var *deref)
+try_mask_partial_io(nir_shader *shader, nir_deref_var *deref, bool 
is_output_read)
 {
nir_variable *var = deref->var;
const struct glsl_type *type = var->type;
@@ -186,7 +195,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var 
*deref)
   return false;
}
 
-   set_io_mask(shader, var, offset, elem_width);
+   set_io_mask(shader, var, offset, elem_width, is_output_read);
return true;
 }
 
@@ -209,8 +218,13 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, 
nir_shader *shader)
 
   if (var->data.mode == nir_var_shader_in ||
   var->data.mode == nir_var_shader_out) {
- if (!try_mask_partial_io(shader, instr->variables[0]))
-mark_whole_variable(shader, var);
+ bool is_output_read = false;
+ if (var->data.mode == nir_var_shader_out &&
+ instr->intrinsic == nir_intrinsic_load_var)
+is_output_read = true;
+
+ if (!try_mask_partial_io(shader, instr->variables[0], is_output_read))
+mark_whole_variable(shader, var, is_output_read);
 
  /* We need to track which input_reads bits correspond to a
   * dvec3/dvec4 input attribute */
@@ -339,6 +353,7 @@ nir_shader_gather_info(nir_shader *shader, 
nir_function_impl *entrypoint)
shader->info.inputs_read = 0;
shader->info.outputs_written = 0;
shader->info.outputs_read = 0;
+   shader->info.patch_outputs_read = 0;
shader->info.double_inputs_read = 0;
shader->info.patch_inputs_read = 0;
shader->info.patch_outputs_written = 0;
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 5f14ad1..bcb3f0f 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -66,6 +66,8 @@ typedef struct shader_info {
uint32_t patch_inputs_read;
/* Which patch outputs are actually written */
uint32_t patch_outputs_written;
+   /* Which patch outputs are read */
+   uint32_t patch_outputs_read;
 
/* Whether or not this shader ever uses textureGather() */
bool uses_texture_gather;
-- 
2.9.5

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[Mesa-dev] [PATCH 2/2] ac/nir: don't write tcs outputs to LDS that aren't read back.

[Dave Airlie]

From: Dave Airlie 

If the TCS doesn't read back the outputs, no need to store them
to LDS in the first place. (except for tess factors).

This seems to give about 50fps (3290->3330) with tessellation demo.

I haven't tested if it impacts DoW3 at all.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3d9f613..e7133ec 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -150,6 +150,9 @@ struct nir_to_llvm_context {
unsigned tes_primitive_mode;
uint64_t tess_outputs_written;
uint64_t tess_patch_outputs_written;
+
+   uint32_t tcs_patch_outputs_read;
+   uint64_t tcs_outputs_read;
 };
 
 static inline struct nir_to_llvm_context *
@@ -2790,7 +2793,15 @@ store_tcs_output(struct nir_to_llvm_context *ctx,
const unsigned comp = instr->variables[0]->var->data.location_frac;
const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, 
ctx->stage);
const bool is_compact = instr->variables[0]->var->data.compact;
+   bool store_lds = true;
 
+   if (instr->variables[0]->var->data.patch) {
+   if (!(ctx->tcs_patch_outputs_read & (1U << 
instr->variables[0]->var->data.location)))
+   store_lds = false;
+   } else {
+   if (!(ctx->tcs_outputs_read & (1ULL << 
instr->variables[0]->var->data.location)))
+   store_lds = false;
+   }
get_deref_offset(ctx->nir, instr->variables[0],
 false, NULL, per_vertex ? _index : NULL,
 _index, _index);
@@ -2827,7 +2838,8 @@ store_tcs_output(struct nir_to_llvm_context *ctx,
continue;
LLVMValueRef value = llvm_extract_elem(>ac, src, chan - 
comp);
 
-   ac_lds_store(>ac, dw_addr, value);
+   if (store_lds || is_tess_factor)
+   ac_lds_store(>ac, dw_addr, value);
 
if (!is_tess_factor && writemask != 0xF)
ac_build_buffer_store_dword(>ac, 
ctx->hs_ring_tess_offchip, value, 1,
@@ -6550,6 +6562,9 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.gs_next_vertex = ac_build_alloca(, 
ctx.ac.i32, "gs_next_vertex");
 
ctx.gs_max_out_vertices = 
shaders[i]->info.gs.vertices_out;
+   } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
+   ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
+   ctx.tcs_patch_outputs_read = 
shaders[i]->info.patch_outputs_read;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
-- 
2.9.5

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[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

Tapani Pälli  changed:

   What|Removed |Added

 CC||lem...@gmail.com

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Re: [Mesa-dev] [PATCH 2/4] i965: Add more precise cache tracking helpers

[Jason Ekstrand]

On Mon, Nov 13, 2017 at 4:33 PM, Kenneth Graunke 
wrote:

> On Monday, November 6, 2017 1:38:55 PM PST Jason Ekstrand wrote:
> > In theory, this will let us track the depth and render caches
> > separately.  Right now, they're just wrappers around
> > brw_render_cache_set_*
> > ---
> >  src/mesa/drivers/dri/i965/brw_draw.c  | 12 +--
> >  src/mesa/drivers/dri/i965/brw_misc_state.c|  4 ++--
> >  src/mesa/drivers/dri/i965/genX_blorp_exec.c   | 10 -
> >  src/mesa/drivers/dri/i965/intel_fbo.c | 29
> +++
> >  src/mesa/drivers/dri/i965/intel_fbo.h |  6 ++
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  2 +-
> >  6 files changed, 49 insertions(+), 14 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
> b/src/mesa/drivers/dri/i965/brw_draw.c
> > index 10b6298..8920b00 100644
> > --- a/src/mesa/drivers/dri/i965/brw_draw.c
> > +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> > @@ -426,7 +426,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw,
> bool rendering)
> >  min_layer, num_layers,
> >  disable_aux);
> >
> > -  brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
> > +  brw_cache_flush_for_read(brw, tex_obj->mt->bo);
> >
> >if (tex_obj->base.StencilSampling ||
> >tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
> > @@ -450,7 +450,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw,
> bool rendering)
> >
> > intel_miptree_prepare_image(brw, tex_obj->mt);
> >
> > -   brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
> > +   brw_cache_flush_for_read(brw, tex_obj->mt->bo);
> >  }
> >   }
> >}
> > @@ -561,11 +561,11 @@ brw_postdraw_set_buffers_need_resolve(struct
> brw_context *brw)
> >  depth_written);
> >}
> >if (depth_written)
> > - brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
> > + brw_depth_cache_add_bo(brw, depth_irb->mt->bo);
> > }
> >
> > if (stencil_irb && brw->stencil_write_enabled)
> > -  brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
> > +  brw_depth_cache_add_bo(brw, stencil_irb->mt->bo);
> >
> > for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
> >struct intel_renderbuffer *irb =
> > @@ -578,7 +578,7 @@ brw_postdraw_set_buffers_need_resolve(struct
> brw_context *brw)
> >   _mesa_get_render_format(ctx, intel_rb_format(irb));
> >enum isl_format isl_format = brw_isl_format_for_mesa_
> format(mesa_format);
> >
> > -  brw_render_cache_set_add_bo(brw, irb->mt->bo);
> > +  brw_render_cache_add_bo(brw, irb->mt->bo);
> >intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
> >irb->mt_layer, irb->layer_count,
> >isl_format,
> > @@ -593,7 +593,7 @@ intel_renderbuffer_move_temp_back(struct
> brw_context *brw,
> > if (irb->align_wa_mt == NULL)
> >return;
> >
> > -   brw_render_cache_set_check_flush(brw, irb->align_wa_mt->bo);
> > +   brw_cache_flush_for_read(brw, irb->align_wa_mt->bo);
> >
> > intel_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
> >  irb->mt,
> > diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> > index 53137cc..fd96485 100644
> > --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> > @@ -333,9 +333,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
> > }
> >
> > if (depth_mt)
> > -  brw_render_cache_set_check_flush(brw, depth_mt->bo);
> > +  brw_cache_flush_for_depth(brw, depth_mt->bo);
> > if (stencil_mt)
> > -  brw_render_cache_set_check_flush(brw, stencil_mt->bo);
> > +  brw_cache_flush_for_depth(brw, stencil_mt->bo);
> >
> > brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
> >  depthbuffer_format,
> depth_surface_type,
> > diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> > index 3c7a7b4..296a83b 100644
> > --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> > +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> > @@ -215,8 +215,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
> >  * data.
> >  */
> > if (params->src.enabled)
> > -  brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
> > -   brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
> > +  brw_cache_flush_for_read(brw, params->src.addr.buffer);
> > +   brw_cache_flush_for_render(brw, params->dst.addr.buffer);
>
> This drops the cache flush, because brw_cache_flush_for_render
> is an empty function.  I don't think you intended to do that.
>

I'll just leave the 

Re: [Mesa-dev] [PATCH 1/2] radv: Free syncobj with multiple imports.

[Dave Airlie]

Reviewed-by: Dave Airlie 

On 14 November 2017 at 09:45, Bas Nieuwenhuizen  
wrote:
> Otherwise we can leak the old syncobj.
>
> Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
> ---
>  src/amd/vulkan/radv_device.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 929082182c2..4e3ad111382 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -3525,6 +3525,7 @@ VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
> RADV_FROM_HANDLE(radv_device, device, _device);
> RADV_FROM_HANDLE(radv_semaphore, sem, 
> pImportSemaphoreFdInfo->semaphore);
> uint32_t syncobj_handle = 0;
> +   uint32_t *syncobj_dst = NULL;
> assert(pImportSemaphoreFdInfo->handleType == 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
>
> int ret = device->ws->import_syncobj(device->ws, 
> pImportSemaphoreFdInfo->fd, _handle);
> @@ -3532,10 +3533,15 @@ VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
> return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
>
> if (pImportSemaphoreFdInfo->flags & 
> VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
> -   sem->temp_syncobj = syncobj_handle;
> +   syncobj_dst = >temp_syncobj;
> } else {
> -   sem->syncobj = syncobj_handle;
> +   syncobj_dst = >syncobj;
> }
> +
> +   if (*syncobj_dst)
> +   device->ws->destroy_syncobj(device->ws, *syncobj_dst);
> +
> +   *syncobj_dst = syncobj_handle;
> close(pImportSemaphoreFdInfo->fd);
> return VK_SUCCESS;
>  }
> --
> 2.15.0
>
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[Mesa-dev] [PATCH] radv: it isn't an error to not support a format or driver

[Dave Airlie]

From: Dave Airlie 

This reverts two of the vk_error changes:

reporting unsupported format is common,
and testing non-amdgpu drivers and ignoring them is also common.

Fixes: cd64a4f70 (radv: use vk_error() everywhere an error is returned)
Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_device.c  | 2 +-
 src/amd/vulkan/radv_formats.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 929082182c..a67b735373 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -196,7 +196,7 @@ radv_physical_device_init(struct radv_physical_device 
*device,
if (strcmp(version->name, "amdgpu")) {
drmFreeVersion(version);
close(fd);
-   return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
+   return VK_ERROR_INCOMPATIBLE_DRIVER;
}
drmFreeVersion(version);
 
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 7f679e8768..5c79ea7406 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -1144,7 +1144,7 @@ unsupported:
.maxResourceSize = 0,
};
 
-   return vk_error(VK_ERROR_FORMAT_NOT_SUPPORTED);
+   return VK_ERROR_FORMAT_NOT_SUPPORTED;
 }
 
 VkResult radv_GetPhysicalDeviceImageFormatProperties(
-- 
2.13.6

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Re: [Mesa-dev] [PATCH] st/atifs: merge gl_program and ati_fragment_shader

[Ian Romanick]

On 11/10/2017 02:35 AM, Timothy Arceri wrote:
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index 6b5c5bbb36..7c357b07ee 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -2352,58 +2376,29 @@ struct gl_fragment_program_state
>   */
>  struct gl_compute_program_state
>  {
> /** Currently enabled and valid program (including internal programs
>  * and compiled shader programs).
>  */
> struct gl_program *_Current;
>  };
>  
>  
> -/**
> - * ATI_fragment_shader runtime state
> - */
> -
> -struct atifs_instruction;
> -struct atifs_setupinst;
> -
> -/**
> - * ATI fragment shader
> - */
> -struct ati_fragment_shader
> -{
> -   GLuint Id;
> -   GLint RefCount;
> -   struct atifs_instruction *Instructions[2];
> -   struct atifs_setupinst *SetupInst[2];
> -   GLfloat Constants[8][4];
> -   GLbitfield LocalConstDef;  /**< Indicates which constants have been set */
> -   GLubyte numArithInstr[2];
> -   GLubyte regsAssigned[2];
> -   GLubyte NumPasses; /**< 1 or 2 */
> -   GLubyte cur_pass;
> -   GLubyte last_optype;
> -   GLboolean interpinp1;
> -   GLboolean isValid;
> -   GLuint swizzlerq;
> -   struct gl_program *Program;
> -};
> -

Other places in Mesa would do this by C-style subclassing of gl_program:

struct ati_fragment_shader {
   struct gl_program Base;
   struct atifs_instruction *Instructions[2];
   struct atifs_setupinst *SetupInst[2];
   GLfloat Constants[8][4];
   GLbitfield LocalConstDef;  /**< Indicates which constants have been set */
   GLubyte numArithInstr[2];
   GLubyte regsAssigned[2];
   GLubyte NumPasses; /**< 1 or 2 */
   GLubyte cur_pass;
   GLubyte last_optype;
   GLboolean interpinp1;
   GLboolean isValid;
   GLuint swizzlerq;
};

Is there a reason to not do that here?

>  /**
>   * Context state for GL_ATI_fragment_shader
>   */
>  struct gl_ati_fragment_shader_state
>  {
> GLboolean Enabled;
> GLboolean Compiling;
> GLfloat GlobalConstants[8][4];
> -   struct ati_fragment_shader *Current;
> +   struct gl_program *Current;
>  };
>  
>  /**
>   *  Shader subroutine function definition
>   */
>  struct gl_subroutine_function
>  {
> char *name;
> int index;
> int num_compat_types;
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Re: [Mesa-dev] [PATCH 5/5] r600: set the number type correctly for float rts in cb setup

[Roland Scheidegger]

Ping (for the series)?

Roland

Am 09.11.2017 um 20:00 schrieb srol...@vmware.com:
> From: Roland Scheidegger 
> 
> Float rts were always set as unorm instead of float.
> Not sure of the consequences, but at least it looks like the blend clamp
> would have been enabled, which is against the rules (only eg really bothered
> to even attempt to specify this correctly, r600 always used clamp anyway).
> Albeit r600 (not r700) setup still looks bugged to me due to never setting
> BLEND_FLOAT32 which must be set according to docs...
> Not sure if the hw really cares, no piglit change (on eg/juniper).
> ---
>  src/gallium/drivers/r600/evergreen_state.c |  7 ++-
>  src/gallium/drivers/r600/r600_state.c  | 10 +-
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/evergreen_state.c 
> b/src/gallium/drivers/r600/evergreen_state.c
> index ef323bf4f6..e724cb157f 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -1042,7 +1042,7 @@ static void evergreen_set_color_surface_buffer(struct 
> r600_context *rctx,
>   }
>   }
>   ntype = V_028C70_NUMBER_UNORM;
> - if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
> + if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
>   ntype = V_028C70_NUMBER_SRGB;
>   else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
>   if (desc->channel[i].normalized)
> @@ -1054,7 +1054,10 @@ static void evergreen_set_color_surface_buffer(struct 
> r600_context *rctx,
>   ntype = V_028C70_NUMBER_UNORM;
>   else if (desc->channel[i].pure_integer)
>   ntype = V_028C70_NUMBER_UINT;
> + } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
> + ntype = V_028C70_NUMBER_FLOAT;
>   }
> +
>   pitch = (pitch / 8) - 1;
>   color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
>  
> @@ -1180,6 +1183,8 @@ static void evergreen_set_color_surface_common(struct 
> r600_context *rctx,
>   ntype = V_028C70_NUMBER_UNORM;
>   else if (desc->channel[i].pure_integer)
>   ntype = V_028C70_NUMBER_UINT;
> + } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
> + ntype = V_028C70_NUMBER_FLOAT;
>   }
>  
>   if (R600_BIG_ENDIAN)
> diff --git a/src/gallium/drivers/r600/r600_state.c 
> b/src/gallium/drivers/r600/r600_state.c
> index db3d6db70b..f024987a30 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -817,7 +817,7 @@ static void r600_init_color_surface(struct r600_context 
> *rctx,
>   unsigned offset;
>   const struct util_format_description *desc;
>   int i;
> - bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
> + bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = FALSE;
>  
>   if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
>   r600_init_flushed_depth_texture(>b.b, surf->base.texture, 
> NULL);
> @@ -869,6 +869,8 @@ static void r600_init_color_surface(struct r600_context 
> *rctx,
>   ntype = V_0280A0_NUMBER_UNORM;
>   else if (desc->channel[i].pure_integer)
>   ntype = V_0280A0_NUMBER_UINT;
> + } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
> + ntype = V_0280A0_NUMBER_FLOAT;
>   }
>  
>   if (R600_BIG_ENDIAN)
> @@ -883,6 +885,11 @@ static void r600_init_color_surface(struct r600_context 
> *rctx,
>  
>   endian = r600_colorformat_endian_swap(format, do_endian_swap);
>  
> + /* blend clamp should be set for all NORM/SRGB types */
> + if (ntype == V_0280A0_NUMBER_UNORM || ntype == V_0280A0_NUMBER_SNORM ||
> + ntype == V_0280A0_NUMBER_SRGB)
> + blend_clamp = 1;
> +
>   /* set blend bypass according to docs if SINT/UINT or
>  8/24 COLOR variants */
>   if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
> @@ -916,6 +923,7 @@ static void r600_init_color_surface(struct r600_context 
> *rctx,
>ntype != V_0280A0_NUMBER_UINT &&
>ntype != V_0280A0_NUMBER_SINT) &&
>   G_0280A0_BLEND_CLAMP(color_info) &&
> + /* XXX this condition is always true since BLEND_FLOAT32 is 
> never set (bug?). */
>   !G_0280A0_BLEND_FLOAT32(color_info)) {
>   color_info |= 
> S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
>   surf->export_16bpc = true;
> 

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[Mesa-dev] [PATCH] swr/rast: Use gather instruction for i32gather_ps on simd16/avx512

[Tim Rowley]

Speed up avx512 platforms; fixes performance regression caused
by swithc to simdlib.

Cc: mesa-sta...@lists.freedesktop.org
---
 .../drivers/swr/rasterizer/common/simdlib_512_avx512.inl | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
index 95e4c31909..c13b9f616a 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
@@ -484,17 +484,7 @@ SIMD_WRAPPER_2(unpacklo_ps);
 template
 static SIMDINLINE Float SIMDCALL i32gather_ps(float const* p, Integer idx) // 
return *(float*)(((int8*)p) + (idx * ScaleT))
 {
-uint32_t *pOffsets = (uint32_t*)
-Float vResult;
-float* pResult = (float*)
-for (uint32_t i = 0; i < SIMD_WIDTH; ++i)
-{
-uint32_t offset = pOffsets[i];
-offset = offset * static_cast(ScaleT);
-pResult[i] = *(float const*)(((uint8_t const*)p + offset));
-}
-
-return vResult;
+return _mm512_i32gather_ps(idx, p, static_cast(ScaleT));
 }
 
 static SIMDINLINE Float SIMDCALL load1_ps(float const *p)  // return *p
(broadcast 1 value to all elements)
-- 
2.14.1

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[Mesa-dev] [PATCH] swr/rast: Faster emulated simd16 permute

[Tim Rowley]

Speed up simd16 frontend (default) on avx/avx2 platforms;
fixes performance regression caused by switch to simdlib.

Cc: mesa-sta...@lists.freedesktop.org
---
 .../swr/rasterizer/common/simdlib_512_emu.inl  | 34 +++---
 1 file changed, 11 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_emu.inl 
b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_emu.inl
index d6af7b1c64..44eba0b126 100644
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_emu.inl
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib_512_emu.inl
@@ -521,36 +521,24 @@ SIMD_IWRAPPER_2(packus_epi32); // See documentation 
for _mm256_packus_epi32
 
 static SIMDINLINE Integer SIMDCALL permute_epi32(Integer const , Integer 
const ) // return a[swiz[i]] for each 32-bit lane i (int32)
 {
-Integer result;
-
-// Ugly slow implementation
-uint32_t const *pA = reinterpret_cast();
-uint32_t const *pSwiz = reinterpret_cast();
-uint32_t *pResult = reinterpret_cast();
-
-for (uint32_t i = 0; i < SIMD_WIDTH; ++i)
-{
-pResult[i] = pA[0xF & pSwiz[i]];
-}
-
-return result;
+return castps_si(permute_ps(castsi_ps(a), swiz));
 }
 
 static SIMDINLINE Float SIMDCALL permute_ps(Float const , Integer const 
)// return a[swiz[i]] for each 32-bit lane i (float)
 {
-Float result;
+const auto mask = SIMD256T::set1_epi32(7);
 
-// Ugly slow implementation
-float const *pA = reinterpret_cast();
-uint32_t const *pSwiz = reinterpret_cast();
-float *pResult = reinterpret_cast();
+auto lolo = SIMD256T::permute_ps(a.v8[0], SIMD256T::and_si(swiz.v8[0], 
mask));
+auto lohi = SIMD256T::permute_ps(a.v8[1], SIMD256T::and_si(swiz.v8[0], 
mask));
 
-for (uint32_t i = 0; i < SIMD_WIDTH; ++i)
-{
-pResult[i] = pA[0xF & pSwiz[i]];
-}
+auto hilo = SIMD256T::permute_ps(a.v8[0], SIMD256T::and_si(swiz.v8[1], 
mask));
+auto hihi = SIMD256T::permute_ps(a.v8[1], SIMD256T::and_si(swiz.v8[1], 
mask));
 
-return result;
+return Float
+{
+SIMD256T::blendv_ps(lolo, lohi, 
SIMD256T::castsi_ps(SIMD256T::cmpgt_epi32(swiz.v8[0], mask))),
+SIMD256T::blendv_ps(hilo, hihi, 
SIMD256T::castsi_ps(SIMD256T::cmpgt_epi32(swiz.v8[1], mask))),
+};
 }
 
 // All of the 512-bit permute2f128_XX intrinsics do the following:
-- 
2.14.1

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Re: [Mesa-dev] [PATCH] st/atifs: merge gl_program and ati_fragment_shader

[Eric Anholt]

Miklós Máté  writes:

> On 12/11/17 00:06, Timothy Arceri wrote:
>> On 12/11/17 04:10, Miklós Máté wrote:
>>> Hi,
>>>
>>> this breaks a few things. The patch below gets rid of the assertion 
>>> failures, but the reference counting needs a proper fix, and swrast 
>>> draws blackness when ATIfs is enabled.
>>
>> Thanks for testing :) Is there something freely available I can test 
>> this with? Are your piglit tests in a state where I could pull the 
>> repo and use what you have?
> My piglit tests are about 25% complete. My progress is slow, because as 
> I go along I also fix the problems the tests find in Mesa. I can send 
> you a targz of what I have so far (mostly API sanity checks and a couple 
> of very simple render tests). I know of two games that use this 
> extension: KOTOR is not free, but Doom3 has a demo version. Set 
> r_renderer=r200 and image_useNormalCompression=2.

I'd recommend submitting tests for review as soon as you can -- you'll
probably get feedback about general structure of writing tests that will
mean less work when writing your later tests. :)


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[Mesa-dev] [PATCH v3 09/15] meson: extend install_megadrivers script to handle symmlinking

[Dylan Baker]

which is required for the gallium media state trackers.
---
 bin/install_megadrivers.py | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/bin/install_megadrivers.py b/bin/install_megadrivers.py
index a98d7dd177b..581ff9791e5 100755
--- a/bin/install_megadrivers.py
+++ b/bin/install_megadrivers.py
@@ -33,6 +33,7 @@ def main():
 parser.add_argument('megadriver')
 parser.add_argument('libdir')
 parser.add_argument('drivers', nargs='+')
+parser.add_argument('--so-version', action='append', default=[])
 args = parser.parse_args()
 
 to = os.path.join(os.environ.get('MESON_INSTALL_DESTDIR_PREFIX'), 
args.libdir)
@@ -48,6 +49,11 @@ def main():
 os.unlink(driver)
 print('installing {} to {}'.format(args.megadriver, driver))
 os.link(master, driver)
+for v in args.so_version:
+name = '{}.{}'.format(driver, v)
+if os.path.exists(name):
+os.unlink(name)
+os.symlink(driver, name)
 os.unlink(master)
 
 
-- 
2.15.0

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Re: [Mesa-dev] [PATCH 04/11] intel/tools/error: Only decode a few sections of error states.

[Kenneth Graunke]

On Sunday, November 12, 2017 1:41:29 AM PST Chris Wilson wrote:
> Quoting Kenneth Graunke (2017-11-12 08:35:05)
> > These three are the only we can reasonably decode with genxml.
> 
> Makes sense, I would recommend putting those into an array for ease of
> future expansion. Maybe also strcasecmp?
> Reviewed-by: Chris Wilson 

Yeah, that's not a bad idea.  I'll write a patch for that.

> (Note to self, aubinator will be specialiased for debugging mesa hangs;
> leaving a niche for intel_error_decode for triaging.)
> -Chris

Why do you say that?  I would like it to be generally useful for all
hangs.  We just don't want to try and use genxml to decode things that
aren't GPU commands or structures, as that will print garbage.

We probably do want to port over a "decoder" that just prints the raw
hex values for unknown sections, like intel_error_decode does.  We
probably ought to also add pretty-printers for the other sections.

We also ought to improve the decoding of the hardware context image.
Likely the best way is to add a genxml structure type for the entire
logical context image, and then use that when decoding.

I'd be happy to see non-Mesa-related improvements made to
aubinator_error_decode.


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[Mesa-dev] [PATCH v3 10/15] meson: drop gallium-media argument

[Dylan Baker]

This argument is the wrong approach for handling gallium media state
trackers, since it doesn't allow for an auto option. Instead we'll use
tristates, which do allow for auto.

This option has never been wired to anything anyway.

Signed-off-by: Dylan Baker 
---
 meson.build   | 17 -
 meson_options.txt |  6 --
 2 files changed, 23 deletions(-)

diff --git a/meson.build b/meson.build
index a93ded47093..0f6644a1be4 100644
--- a/meson.build
+++ b/meson.build
@@ -348,23 +348,6 @@ if with_dri or with_gallium
   endif
 endif
 
-with_gallium_xvmc = false
-with_gallium_vdpau = false
-with_gallium_omx = false  # this is bellagio
-with_gallium_va = false
-with_gallium_media = false
-dep_va = []
-_drivers = get_option('gallium-media')
-if _drivers != ''
-  _split = _drivers.split(',')
-  with_gallium_xvmc = _split.contains('xvmc')
-  with_gallium_vdpau = _split.contains('vdpau')
-  with_gallium_omx = _split.contains('omx')
-  with_gallium_va = _split.contains('va')
-  with_gallium_media = (with_gallium_xvmc or with_gallium_vdpau or
-with_gallium_omx or with_gallium_va)
-endif
-
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
diff --git a/meson_options.txt b/meson_options.txt
index 6c9cd33998c..119bec15709 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -49,12 +49,6 @@ option(
   value : 'auto',
   description : 'comma separated list of gallium drivers to build. If this is 
set to auto all drivers applicable to the target OS/architecture will be built'
 )
-option(
-  'gallium-media',
-  type : 'string',
-  value : '',
-  description : 'comma separated list of gallium media APIs to build 
(omx,va,vdpau,xvmc).'
-)
 option(
   'vulkan-drivers',
   type : 'string',
-- 
2.15.0

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[Mesa-dev] [PATCH v3 14/15] meson: build gallium va state tracker

[Dylan Baker]

v2: - set with_gallium_va when -Dgallium-va=true
- Fix megadrivers install
- only use cflags from pkg-config, don't add linker flags.
- Don't get version from pkg-config, it's not tracking the same
  version information.
---
 meson.build   | 41 +-
 meson_options.txt | 13 +
 src/gallium/meson.build   |  7 ++-
 src/gallium/state_trackers/va/meson.build | 39 ++
 src/gallium/targets/va/meson.build| 89 +++
 5 files changed, 187 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/state_trackers/va/meson.build
 create mode 100644 src/gallium/targets/va/meson.build

diff --git a/meson.build b/meson.build
index b1a09a0b6c9..8c20523aab0 100644
--- a/meson.build
+++ b/meson.build
@@ -487,6 +487,44 @@ if with_gallium_omx
   )
 endif
 
+dep_va = []
+_va = get_option('gallium-va')
+if _va == 'auto'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+with_gallium_va = false
+  elif not with_platform_x11
+with_gallium_va = false
+  elif not (with_gallium_r600 or with_gallium_radeonsi or with_gallium_nouveau)
+with_gallium_va = false
+  else
+dep_va = dependency('libva', version : '>= 0.38.0', required : false)
+with_gallium_va = dep_va.found()
+  endif
+elif _va == 'true'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+error('VA state tracker can only be built on unix-like OSes.')
+  elif not (with_platform_x11 or with_platform_drm)
+error('VA state tracker requires X11 or drm or wayland platform support.')
+with_gallium_va = false
+  elif not (with_gallium_r600 or with_gallium_radeonsi or with_gallium_nouveau)
+error('VA state tracker requires at least one of the following gallium 
drivers: r600, radeonsi, nouveau.')
+  endif
+  dep_va = dependency('libva', version : '>= 0.38.0')
+  with_gallium_va = true
+else
+  with_gallium_va = false
+endif
+if with_gallium_va
+  dep_va = declare_dependency(
+compile_args : dep_va.get_pkgconfig_variable('cflags').split()
+  )
+endif
+
+va_drivers_path = get_option('va-libs-path')
+if va_drivers_path == ''
+  va_drivers_path = join_paths(get_option('libdir'), 'dri')
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
@@ -994,7 +1032,8 @@ if with_platform_x11
 dep_xxf86vm = dependency('xxf86vm', required : false)
   endif
   if (with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm') or
-  (with_gallium_vdpau or with_gallium_xvmc or with_gallium_omx))
+  (with_gallium_vdpau or with_gallium_xvmc or with_gallium_omx or
+   with_gallium_xa))
 dep_xcb = dependency('xcb')
 dep_x11_xcb = dependency('x11-xcb')
 dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
diff --git a/meson_options.txt b/meson_options.txt
index 8ee216d5b8a..0a9f7a9e403 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -88,6 +88,19 @@ option(
   value : '',
   description : 'path to put omx libraries. defaults to omx-bellagio 
pkg-config pluginsdir.'
 )
+option(
+  'gallium-va',
+  type : 'combo',
+  value : 'auto',
+  choices : ['auto', 'true', 'false'],
+  description : 'enable gallium va state tracker.',
+)
+option(
+  'va-libs-path',
+  type : 'string',
+  value : '',
+  description : 'path to put va libraries. defaults to $libdir/dri.'
+)
 option(
   'vulkan-drivers',
   type : 'string',
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index c17dba51ff2..c379b600d87 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -108,6 +108,9 @@ endif
 if with_gallium_omx
   subdir('state_trackers/omx_bellagio')
 endif
+if with_gallium_va
+  subdir('state_trackers/va')
+endif
 # TODO: SWR
 # TODO: clover
 if with_dri and with_gallium
@@ -128,7 +131,9 @@ endif
 if with_gallium_omx
   subdir('targets/omx-bellagio')
 endif
-# TODO: VA
+if with_gallium_va
+  subdir('targets/va')
+endif
 # TODO: xa
 # TODO: nine
 # TODO: tests
diff --git a/src/gallium/state_trackers/va/meson.build 
b/src/gallium/state_trackers/va/meson.build
new file mode 100644
index 000..dd0d03b629a
--- /dev/null
+++ b/src/gallium/state_trackers/va/meson.build
@@ -0,0 +1,39 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, 

[Mesa-dev] [PATCH v3 08/15] autotools: change version TINY -> PATCH

[Dylan Baker]

Because patch is more common than tiny for talking about the 3rd element
of a version.

Signed-off-by: Dylan Baker 
---
 configure.ac  | 6 +++---
 src/gallium/state_trackers/xa/xa_tracker.h.in | 2 +-
 src/gallium/targets/d3dadapter9/Makefile.am   | 2 +-
 src/gallium/targets/xa/Makefile.am| 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/configure.ac b/configure.ac
index 55cf9f1d7e7..ad715885466 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2845,8 +2845,8 @@ AM_CONDITIONAL(HAVE_ARM_ASM, test "x$asm_arch" = xarm)
 
 AC_SUBST([NINE_MAJOR], 1)
 AC_SUBST([NINE_MINOR], 0)
-AC_SUBST([NINE_TINY], 0)
-AC_SUBST([NINE_VERSION], "$NINE_MAJOR.$NINE_MINOR.$NINE_TINY")
+AC_SUBST([NINE_PATCH], 0)
+AC_SUBST([NINE_VERSION], "$NINE_MAJOR.$NINE_MINOR.$NINE_PATCH")
 
 AC_SUBST([VDPAU_MAJOR], 1)
 AC_SUBST([VDPAU_MINOR], 0)
@@ -2865,7 +2865,7 @@ AC_SUBST([XVMC_MINOR], 0)
 
 AC_SUBST([XA_MAJOR], 2)
 AC_SUBST([XA_MINOR], 3)
-AC_SUBST([XA_TINY], 0)
+AC_SUBST([XA_PATCH], 0)
 AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_PATCH")
 
 AC_ARG_ENABLE(valgrind,
diff --git a/src/gallium/state_trackers/xa/xa_tracker.h.in 
b/src/gallium/state_trackers/xa/xa_tracker.h.in
index 26c4f21d0f4..fc721eed38b 100644
--- a/src/gallium/state_trackers/xa/xa_tracker.h.in
+++ b/src/gallium/state_trackers/xa/xa_tracker.h.in
@@ -38,7 +38,7 @@
 
 #define XA_TRACKER_VERSION_MAJOR @XA_MAJOR@
 #define XA_TRACKER_VERSION_MINOR @XA_MINOR@
-#define XA_TRACKER_VERSION_PATCH @XA_TINY@
+#define XA_TRACKER_VERSION_PATCH @XA_PATCH@
 
 #define XA_FLAG_SHARED (1 << 0)
 #define XA_FLAG_RENDER_TARGET  (1 << 1)
diff --git a/src/gallium/targets/d3dadapter9/Makefile.am 
b/src/gallium/targets/d3dadapter9/Makefile.am
index 9357d30332a..159c8ea3527 100644
--- a/src/gallium/targets/d3dadapter9/Makefile.am
+++ b/src/gallium/targets/d3dadapter9/Makefile.am
@@ -56,7 +56,7 @@ d3dadapter9_la_LDFLAGS = \
-shrext .so \
-module \
-no-undefined \
-   -version-number $(NINE_MAJOR):$(NINE_MINOR):$(NINE_TINY) \
+   -version-number $(NINE_MAJOR):$(NINE_MINOR):$(NINE_PATCH) \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
 
diff --git a/src/gallium/targets/xa/Makefile.am 
b/src/gallium/targets/xa/Makefile.am
index 83a05230ff8..cd9ca49f568 100644
--- a/src/gallium/targets/xa/Makefile.am
+++ b/src/gallium/targets/xa/Makefile.am
@@ -44,7 +44,7 @@ libxatracker_la_LIBADD = \
 
 libxatracker_la_LDFLAGS = \
-no-undefined \
-   -version-number $(XA_MAJOR):$(XA_MINOR):$(XA_TINY) \
+   -version-number $(XA_MAJOR):$(XA_MINOR):$(XA_PATCH) \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
 
-- 
2.15.0

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[Mesa-dev] [PATCH v3 12/15] meson: build gallium xvmc state tracker

[Dylan Baker]

v2: - set with_gallium_xvmc when -Dgallium-xvmc=true
- Install megadrivers properly
- only use cflags from pkg-config, don't add linker flags.
---
 meson.build | 40 ++-
 meson_options.txt   | 13 +
 src/gallium/meson.build |  7 ++-
 src/gallium/state_trackers/xvmc/meson.build | 53 +++
 src/gallium/targets/xvmc/meson.build| 80 +
 5 files changed, 191 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/state_trackers/xvmc/meson.build
 create mode 100644 src/gallium/targets/xvmc/meson.build

diff --git a/meson.build b/meson.build
index 289c12cd1b6..9c7a5062a7d 100644
--- a/meson.build
+++ b/meson.build
@@ -391,6 +391,44 @@ if vdpau_drivers_path == ''
   vdpau_drivers_path = join_paths(get_option('libdir'), 'vdpau')
 endif
 
+dep_xvmc = []
+_xvmc = get_option('gallium-xvmc')
+if _xvmc == 'auto'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+with_gallium_xvmc = false
+  elif not with_platform_x11
+with_gallium_xvmc = false
+  elif not (with_gallium_r600 or with_gallium_nouveau)
+with_gallium_xvmc = false
+  else
+dep_xvmc = dependency('xvmc', version : '>= 1.0.6', required : false)
+with_gallium_xvmc = dep_xvmc.found()
+  endif
+elif _xvmc == 'true'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+error('XVMC state tracker can only be build on unix-like OSes.')
+  elif not with_platform_x11
+error('XVMC state tracker requires X11 support.')
+with_gallium_xvmc = false
+  elif not (with_gallium_r600 or with_gallium_nouveau)
+error('XVMC state tracker requires at least one of the following gallium 
drivers: r600, nouveau.')
+  endif
+  dep_xvmc = dependency('xvmc', version : '>= 1.0.6')
+  with_gallium_xvmc = true
+else
+  with_gallium_xvmc = false
+endif
+if with_gallium_xvmc
+  dep_xvmc = declare_dependency(
+compile_args : dep_xvmc.get_pkgconfig_variable('cflags').split()
+  )
+endif
+
+xvmc_drivers_path = get_option('xvmc-libs-path')
+if xvmc_drivers_path == ''
+  xvmc_drivers_path = get_option('libdir')
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
@@ -898,7 +936,7 @@ if with_platform_x11
 dep_xxf86vm = dependency('xxf86vm', required : false)
   endif
   if (with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm') or
-  with_gallium_vdpau)
+  (with_gallium_vdpau or with_gallium_xvmc))
 dep_xcb = dependency('xcb')
 dep_x11_xcb = dependency('x11-xcb')
 dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
diff --git a/meson_options.txt b/meson_options.txt
index 78b78a92dbf..f0de44e751b 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -62,6 +62,19 @@ option(
   value : '',
   description : 'path to put vdpau libraries. defaults to $libdir/vdpau.'
 )
+option(
+  'gallium-xvmc',
+  type : 'combo',
+  value : 'auto',
+  choices : ['auto', 'true', 'false'],
+  description : 'enable gallium xvmc state tracker.',
+)
+option(
+  'xvmc-libs-path',
+  type : 'string',
+  value : '',
+  description : 'path to put xvmc libraries. defaults to $libdir.'
+)
 option(
   'vulkan-drivers',
   type : 'string',
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 446710e1495..a8317a53552 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -102,6 +102,9 @@ endif
 if with_gallium_vdpau
   subdir('state_trackers/vdpau')
 endif
+if with_gallium_xvmc
+  subdir('state_trackers/xvmc')
+endif
 # TODO: SWR
 # TODO: clover
 if with_dri and with_gallium
@@ -116,9 +119,11 @@ endif
 if with_gallium_vdpau
   subdir('targets/vdpau')
 endif
+if with_gallium_xvmc
+  subdir('targets/xvmc')
+endif
 # TODO: OMX
 # TODO: VA
 # TODO: xa
-# TODO: xvmc
 # TODO: nine
 # TODO: tests
diff --git a/src/gallium/state_trackers/xvmc/meson.build 
b/src/gallium/state_trackers/xvmc/meson.build
new file mode 100644
index 000..a1022c164b1
--- /dev/null
+++ b/src/gallium/state_trackers/xvmc/meson.build
@@ -0,0 +1,53 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR 

[Mesa-dev] [PATCH v3 03/15] meson: build r300 driver

[Dylan Baker]

This is build tested only

Signed-off-by: Dylan Baker 
---
 meson.build  |   6 +-
 src/gallium/drivers/r300/meson.build | 156 +++
 src/gallium/meson.build  |   9 +-
 src/gallium/targets/dri/meson.build  |  12 ++-
 4 files changed, 176 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/r300/meson.build

diff --git a/meson.build b/meson.build
index e80c128f6db..05f171e4d44 100644
--- a/meson.build
+++ b/meson.build
@@ -118,6 +118,7 @@ endif
 with_gallium = false
 with_gallium_pl111 = false
 with_gallium_radeonsi = false
+with_gallium_r300 = false
 with_gallium_nouveau = false
 with_gallium_freedreno = false
 with_gallium_softpipe = false
@@ -131,7 +132,7 @@ if _drivers == 'auto'
   if not ['darwin', 'windows'].contains(host_machine.system())
 # TODO: PPC, Sparc
 if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-  _drivers = 'radeonsi,nouveau,swrast'
+  _drivers = 'r300,radeonsi,nouveau,swrast'
 elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
   _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,swrast'
 else
@@ -145,6 +146,7 @@ if _drivers != ''
   _split = _drivers.split(',')
   with_gallium_pl111 = _split.contains('pl111')
   with_gallium_radeonsi = _split.contains('radeonsi')
+  with_gallium_r300 = _split.contains('r300')
   with_gallium_nouveau = _split.contains('nouveau')
   with_gallium_freedreno = _split.contains('freedreno')
   with_gallium_softpipe = _split.contains('swrast')
@@ -693,7 +695,7 @@ dep_libdrm_freedreno = []
 if with_amd_vk or with_gallium_radeonsi
   dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.88')
 endif
-if with_gallium_radeonsi or with_dri_r100 or with_dri_r200
+if with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or with_gallium_r300
   dep_libdrm_radeon = dependency('libdrm_radeon', version : '>= 2.4.71')
 endif
 if with_gallium_nouveau or with_dri_nouveau
diff --git a/src/gallium/drivers/r300/meson.build 
b/src/gallium/drivers/r300/meson.build
new file mode 100644
index 000..0d525d8d1b3
--- /dev/null
+++ b/src/gallium/drivers/r300/meson.build
@@ -0,0 +1,156 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_r300 = files(
+  'r300_blit.c',
+  'r300_cb.h',
+  'r300_chipset.c',
+  'r300_chipset.h',
+  'r300_context.c',
+  'r300_context.h',
+  'r300_cs.h',
+  'r300_debug.c',
+  'r300_defines.h',
+  'r300_emit.c',
+  'r300_emit.h',
+  'r300_flush.c',
+  'r300_fs.c',
+  'r300_fs.h',
+  'r300_hyperz.c',
+  'r300_public.h',
+  'r300_query.c',
+  'r300_reg.h',
+  'r300_render.c',
+  'r300_render_stencilref.c',
+  'r300_render_translate.c',
+  'r300_resource.c',
+  'r300_screen_buffer.c',
+  'r300_screen_buffer.h',
+  'r300_screen.c',
+  'r300_screen.h',
+  'r300_shader_semantics.h',
+  'r300_state.c',
+  'r300_state_derived.c',
+  'r300_state_inlines.h',
+  'r300_texture.c',
+  'r300_texture_desc.c',
+  'r300_texture_desc.h',
+  'r300_texture.h',
+  'r300_tgsi_to_rc.c',
+  'r300_tgsi_to_rc.h',
+  'r300_transfer.c',
+  'r300_transfer.h',
+  'r300_vs.c',
+  'r300_vs_draw.c',
+  'r300_vs.h',
+  'compiler/memory_pool.c',
+  'compiler/memory_pool.h',
+  'compiler/r300_fragprog.c',
+  'compiler/r300_fragprog_emit.c',
+  'compiler/r300_fragprog.h',
+  'compiler/r300_fragprog_swizzle.c',
+  'compiler/r300_fragprog_swizzle.h',
+  'compiler/r3xx_fragprog.c',
+  'compiler/r3xx_vertprog.c',
+  'compiler/r3xx_vertprog_dump.c',
+  'compiler/r500_fragprog.c',
+  'compiler/r500_fragprog_emit.c',
+  'compiler/r500_fragprog.h',
+  'compiler/radeon_code.c',
+  'compiler/radeon_code.h',
+  'compiler/radeon_compiler.c',
+  'compiler/radeon_compiler.h',
+  'compiler/radeon_compiler_util.c',
+  'compiler/radeon_compiler_util.h',
+  'compiler/radeon_dataflow.c',
+  'compiler/radeon_dataflow_deadcode.c',
+  'compiler/radeon_dataflow.h',
+  

[Mesa-dev] [PATCH v3 06/15] meson: build virgl driver

[Dylan Baker]

Build tested only.

Signed-off-by: Dylan Baker 
---
 meson.build| 16 
 src/gallium/drivers/virgl/meson.build  | 39 ++
 src/gallium/meson.build|  7 +-
 src/gallium/targets/dri/meson.build|  5 
 src/gallium/winsys/virgl/drm/meson.build   | 27 +
 src/gallium/winsys/virgl/vtest/meson.build | 26 
 6 files changed, 114 insertions(+), 6 deletions(-)
 create mode 100644 src/gallium/drivers/virgl/meson.build
 create mode 100644 src/gallium/winsys/virgl/drm/meson.build
 create mode 100644 src/gallium/winsys/virgl/vtest/meson.build

diff --git a/meson.build b/meson.build
index f33d002843e..a93ded47093 100644
--- a/meson.build
+++ b/meson.build
@@ -129,14 +129,15 @@ with_gallium_etnaviv = false
 with_gallium_imx = false
 with_gallium_i915 = false
 with_gallium_svga = false
+with_gallium_virgl = false
 _drivers = get_option('gallium-drivers')
 if _drivers == 'auto'
   if not ['darwin', 'windows'].contains(host_machine.system())
 # TODO: PPC, Sparc
 if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-  _drivers = 'r300,r600,radeonsi,nouveau,svga,swrast'
+  _drivers = 'r300,r600,radeonsi,nouveau,virgl,svga,swrast'
 elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-  _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,svga,swrast'
+  _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,virgl,svga,swrast'
 else
   error('Unknown architecture. Please pass -Dgallium-drivers to set driver 
options. Patches gladly accepted to fix this.')
 endif
@@ -159,6 +160,7 @@ if _drivers != ''
   with_gallium_imx = _split.contains('imx')
   with_gallium_i915 = _split.contains('i915')
   with_gallium_svga = _split.contains('svga')
+  with_gallium_virgl = _split.contains('virgl')
   with_gallium = true
 endif
 
@@ -273,9 +275,13 @@ else
   with_egl = false
 endif
 
-# TODO: or virgl
-if with_egl and with_gallium_radeonsi and not (with_platform_drm or 
with_platform_surfaceless)
-  error('RadeonSI requires drm or surfaceless platform when using EGL')
+if with_egl and not (with_platform_drm or with_platform_surfaceless)
+  if with_gallium_radeonsi
+error('RadeonSI requires drm or surfaceless platform when using EGL')
+  endif
+  if with_gallium_virgl
+error('Virgl requires drm or surfaceless platform when using EGL')
+  endif
 endif
 
 pre_args += '-DGLX_USE_TLS'
diff --git a/src/gallium/drivers/virgl/meson.build 
b/src/gallium/drivers/virgl/meson.build
new file mode 100644
index 000..8284f548927
--- /dev/null
+++ b/src/gallium/drivers/virgl/meson.build
@@ -0,0 +1,39 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_libvirgl = files(
+  'virgl_buffer.c',
+  'virgl_context.c',
+  'virgl_encode.c',
+  'virgl_query.c',
+  'virgl_resource.c',
+  'virgl_screen.c',
+  'virgl_streamout.c',
+  'virgl_texture.c',
+  'virgl_tgsi.c',
+)
+
+libvirgl = static_library(
+  'virgl',
+  files_libvirgl,
+  c_args : c_vis_args,
+  include_directories : inc_common,
+  dependencies : dep_libdrm,
+)
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 2a4cb66ad7a..8e8b1466f12 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -1,4 +1,5 @@
 # Copyright © 2017 Dylan Baker
+# Copyright © 2017 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -85,6 +86,11 @@ if with_gallium_svga
   subdir('drivers/svga')
   subdir('winsys/svga/drm')
 endif
+if with_gallium_virgl
+  subdir('drivers/virgl')
+  subdir('winsys/virgl/drm')
+  subdir('winsys/virgl/vtest')
+endif
 subdir('state_trackers/dri')
 if with_osmesa == 'gallium'
   subdir('state_trackers/osmesa')
@@ -94,7 +100,6 @@ if with_glx == 'gallium-xlib'
   

[Mesa-dev] [PATCH v3 15/15] meson: build gallium xa state tracker

[Dylan Baker]

v2: - set with_gallium_xa when -Dgallium-xa=true
- install pkg config file
---
 meson.build   | 22 
 meson_options.txt |  7 +++
 src/gallium/meson.build   |  7 ++-
 src/gallium/state_trackers/xa/meson.build | 45 +
 src/gallium/targets/xa/meson.build| 84 +++
 5 files changed, 164 insertions(+), 1 deletion(-)
 create mode 100644 src/gallium/state_trackers/xa/meson.build
 create mode 100644 src/gallium/targets/xa/meson.build

diff --git a/meson.build b/meson.build
index 8c20523aab0..1d29eb67bfe 100644
--- a/meson.build
+++ b/meson.build
@@ -525,6 +525,28 @@ if va_drivers_path == ''
   va_drivers_path = join_paths(get_option('libdir'), 'dri')
 endif
 
+_xa = get_option('gallium-xa')
+if _xa == 'auto'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+with_gallium_xa = false
+  elif not (with_gallium_nouveau or with_gallium_freedreno or with_gallium_i915
+or with_gallium_svga)
+with_gallium_xa = false
+  else
+with_gallium_xa = true
+  endif
+elif _xa == 'true'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+error('XA state tracker can only be built on unix-like OSes.')
+  elif not (with_gallium_nouveau or with_gallium_freedreno or with_gallium_i915
+or with_gallium_svga)
+error('XA state tracker requires at least one of the following gallium 
drivers: nouveau, freedreno, i915, svga.')
+  endif
+  with_gallium_xa = true
+else
+  with_gallium_xa = false
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
diff --git a/meson_options.txt b/meson_options.txt
index 0a9f7a9e403..bdeb1b7f587 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -101,6 +101,13 @@ option(
   value : '',
   description : 'path to put va libraries. defaults to $libdir/dri.'
 )
+option(
+  'gallium-xa',
+  type : 'combo',
+  value : 'auto',
+  choices : ['auto', 'true', 'false'],
+  description : 'enable gallium xa state tracker.',
+)
 option(
   'vulkan-drivers',
   type : 'string',
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index c379b600d87..8a072322a28 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -111,6 +111,9 @@ endif
 if with_gallium_va
   subdir('state_trackers/va')
 endif
+if with_gallium_xa
+  subdir('state_trackers/xa')
+endif
 # TODO: SWR
 # TODO: clover
 if with_dri and with_gallium
@@ -134,6 +137,8 @@ endif
 if with_gallium_va
   subdir('targets/va')
 endif
-# TODO: xa
+if with_gallium_xa
+  subdir('targets/xa')
+endif
 # TODO: nine
 # TODO: tests
diff --git a/src/gallium/state_trackers/xa/meson.build 
b/src/gallium/state_trackers/xa/meson.build
new file mode 100644
index 000..109abc10b7d
--- /dev/null
+++ b/src/gallium/state_trackers/xa/meson.build
@@ -0,0 +1,45 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+xa_version = ['2', '3', '0']
+
+xa_conf = configuration_data()
+xa_conf.set('XA_MAJOR', xa_version[0])
+xa_conf.set('XA_MINOR', xa_version[1])
+xa_conf.set('XA_PATCH', xa_version[2])
+
+xa_tracker_h = configure_file(
+  configuration : xa_conf,
+  input : 'xa_tracker.h.in',
+  output : 'xa_tracker.h',
+  install_dir : get_option('includedir'),
+)
+
+libxa_st = static_library(
+  'xa_st',
+  [xa_tracker_h, files(
+'xa_composite.c', 'xa_context.c', 'xa_renderer.c', 'xa_tgsi.c',
+'xa_tracker.c', 'xa_yuv.c',
+  )],
+  c_args : [c_vis_args, '-pedantic'],
+  include_directories : inc_common,
+)
+
+install_headers('xa_composite.h', 'xa_context.h')
diff --git a/src/gallium/targets/xa/meson.build 
b/src/gallium/targets/xa/meson.build
new file mode 100644
index 000..013b8a0
--- /dev/null
+++ b/src/gallium/targets/xa/meson.build
@@ -0,0 +1,84 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any 

[Mesa-dev] [PATCH v3 07/15] autotools: set XA versions in configure.ac and configure header file

[Dylan Baker]

Currently the versions are set in the header, and then sed is used to
extract them, so that autotools can use them elsewhere.

This is odd. Autotools is perfectly capable of configuring the header
with the versions, and then they don't need to be extracted from the
the header. This is cleaner and more obvious.

Tested with make distcheck.

v2: - Split tiny -> patch change
- Drop temporary variables
- change XA_VERSION_* -> XA_*

Signed-off-by: Dylan Baker 
Reviewed-by: Emil Velikov 
Reviewed-by: Matt Turner 
---
 configure.ac   | 14 +-
 .../state_trackers/xa/{xa_tracker.h => xa_tracker.h.in}|  6 +++---
 2 files changed, 8 insertions(+), 12 deletions(-)
 rename src/gallium/state_trackers/xa/{xa_tracker.h => xa_tracker.h.in} (98%)

diff --git a/configure.ac b/configure.ac
index 411c4f6b3e0..55cf9f1d7e7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2863,15 +2863,10 @@ AM_CONDITIONAL(HAVE_VULKAN_COMMON, test 
"x$VULKAN_DRIVERS" != "x")
 AC_SUBST([XVMC_MAJOR], 1)
 AC_SUBST([XVMC_MINOR], 0)
 
-XA_HEADER="$srcdir/src/gallium/state_trackers/xa/xa_tracker.h"
-XA_MAJOR=`grep "#define XA_TRACKER_VERSION_MAJOR" $XA_HEADER | $SED 
's/^#define XA_TRACKER_VERSION_MAJOR //'`
-XA_MINOR=`grep "#define XA_TRACKER_VERSION_MINOR" $XA_HEADER | $SED 
's/^#define XA_TRACKER_VERSION_MINOR //'`
-XA_TINY=`grep "#define XA_TRACKER_VERSION_PATCH" $XA_HEADER | $SED 's/^#define 
XA_TRACKER_VERSION_PATCH //'`
-
-AC_SUBST([XA_MAJOR], $XA_MAJOR)
-AC_SUBST([XA_MINOR], $XA_MINOR)
-AC_SUBST([XA_TINY], $XA_TINY)
-AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_TINY")
+AC_SUBST([XA_MAJOR], 2)
+AC_SUBST([XA_MINOR], 3)
+AC_SUBST([XA_TINY], 0)
+AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_PATCH")
 
 AC_ARG_ENABLE(valgrind,
   [AS_HELP_STRING([--enable-valgrind],
@@ -2953,6 +2948,7 @@ AC_CONFIG_FILES([Makefile
  src/gallium/state_trackers/va/Makefile
  src/gallium/state_trackers/vdpau/Makefile
  src/gallium/state_trackers/xa/Makefile
+ src/gallium/state_trackers/xa/xa_tracker.h
  src/gallium/state_trackers/xvmc/Makefile
  src/gallium/targets/d3dadapter9/Makefile
  src/gallium/targets/d3dadapter9/d3d.pc
diff --git a/src/gallium/state_trackers/xa/xa_tracker.h 
b/src/gallium/state_trackers/xa/xa_tracker.h.in
similarity index 98%
rename from src/gallium/state_trackers/xa/xa_tracker.h
rename to src/gallium/state_trackers/xa/xa_tracker.h.in
index 44b3eb5cbe4..26c4f21d0f4 100644
--- a/src/gallium/state_trackers/xa/xa_tracker.h
+++ b/src/gallium/state_trackers/xa/xa_tracker.h.in
@@ -36,9 +36,9 @@
 
 #include 
 
-#define XA_TRACKER_VERSION_MAJOR 2
-#define XA_TRACKER_VERSION_MINOR 3
-#define XA_TRACKER_VERSION_PATCH 0
+#define XA_TRACKER_VERSION_MAJOR @XA_MAJOR@
+#define XA_TRACKER_VERSION_MINOR @XA_MINOR@
+#define XA_TRACKER_VERSION_PATCH @XA_TINY@
 
 #define XA_FLAG_SHARED (1 << 0)
 #define XA_FLAG_RENDER_TARGET  (1 << 1)
-- 
2.15.0

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[Mesa-dev] [PATCH v3 00/15] Remaining gallium drivers + media

[Dylan Baker]

This gets most of the remaining gallium drivers building with meson (a feature
needed for SWR and clover is slated to land soon in upstream meson).  For the
most part this should be straight forward stuff

Changes since v1:
- do not link media state trackers with their frontends
- fix building media state trackers with explicitly turned on (off and auto
  worked previous)
- Split the XA autotools changes
- fix gallium media targets megadriver install
- Fix omx pluginsdir detection.

Dylan Baker (15):
  meson: add proper LLVM modules to check for RadeonSI as well
  meson: build i915g driver
  meson: build r300 driver
  meson: build r600 driver
  meson: build svga driver on linux
  meson: build virgl driver
  autotools: set XA versions in configure.ac and configure header file
  autotools: change version TINY -> PATCH
  meson: extend install_megadrivers script to handle symmlinking
  meson: drop gallium-media argument
  meson: build gallium vdpau state tracker
  meson: build gallium xvmc state tracker
  meson: build gallium omx state tracker
  meson: build gallium va state tracker
  meson: build gallium xa state tracker

 bin/install_megadrivers.py |   6 +
 configure.ac   |  18 +-
 meson.build| 261 +++--
 meson_options.txt  |  57 -
 .../gallium/drivers/i915/meson.build   |  83 ---
 src/gallium/drivers/r300/meson.build   | 156 
 src/gallium/drivers/r600/meson.build   | 128 ++
 src/gallium/drivers/svga/meson.build   |  88 +++
 .../gallium/drivers/virgl/meson.build  |  54 ++---
 src/gallium/meson.build|  67 --
 .../state_trackers/omx_bellagio/meson.build|  45 +---
 .../gallium/state_trackers/va/meson.build  |  54 ++---
 .../gallium/state_trackers/vdpau/meson.build   |  49 +---
 .../gallium/state_trackers/xa/meson.build  |  60 ++---
 .../xa/{xa_tracker.h => xa_tracker.h.in}   |   6 +-
 .../gallium/state_trackers/xvmc/meson.build|  68 +++---
 src/gallium/targets/d3dadapter9/Makefile.am|   2 +-
 src/gallium/targets/dri/meson.build|  32 ++-
 src/gallium/targets/omx-bellagio/meson.build   |  77 ++
 src/gallium/targets/va/meson.build |  89 +++
 src/gallium/targets/vdpau/meson.build  |  99 
 src/gallium/targets/xa/Makefile.am |   2 +-
 src/gallium/targets/xa/meson.build |  84 +++
 src/gallium/targets/xvmc/meson.build   |  80 +++
 .../gallium/winsys/i915/drm/meson.build|  46 +---
 .../gallium/winsys/svga/drm/meson.build|  60 ++---
 .../gallium/winsys/virgl/drm/meson.build   |  42 +---
 .../gallium/winsys/virgl/vtest/meson.build |  41 +---
 28 files changed, 1409 insertions(+), 445 deletions(-)
 copy bin/install_megadrivers.py => src/gallium/drivers/i915/meson.build (51%)
 mode change 100755 => 100644
 create mode 100644 src/gallium/drivers/r300/meson.build
 create mode 100644 src/gallium/drivers/r600/meson.build
 create mode 100644 src/gallium/drivers/svga/meson.build
 copy bin/install_megadrivers.py => src/gallium/drivers/virgl/meson.build (54%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => 
src/gallium/state_trackers/omx_bellagio/meson.build (54%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => src/gallium/state_trackers/va/meson.build 
(54%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => 
src/gallium/state_trackers/vdpau/meson.build (52%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => src/gallium/state_trackers/xa/meson.build 
(54%)
 mode change 100755 => 100644
 rename src/gallium/state_trackers/xa/{xa_tracker.h => xa_tracker.h.in} (98%)
 copy bin/install_megadrivers.py => src/gallium/state_trackers/xvmc/meson.build 
(51%)
 mode change 100755 => 100644
 create mode 100644 src/gallium/targets/omx-bellagio/meson.build
 create mode 100644 src/gallium/targets/va/meson.build
 create mode 100644 src/gallium/targets/vdpau/meson.build
 create mode 100644 src/gallium/targets/xa/meson.build
 create mode 100644 src/gallium/targets/xvmc/meson.build
 copy bin/install_megadrivers.py => src/gallium/winsys/i915/drm/meson.build 
(54%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => src/gallium/winsys/svga/drm/meson.build 
(54%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => src/gallium/winsys/virgl/drm/meson.build 
(54%)
 mode change 100755 => 100644
 copy bin/install_megadrivers.py => src/gallium/winsys/virgl/vtest/meson.build 
(54%)
 mode change 100755 => 100644

-- 
2.15.0

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[Mesa-dev] [PATCH v3 04/15] meson: build r600 driver

[Dylan Baker]

Signed-off-by: Dylan Baker 
Tested-by: Aaron Watry 
---
 meson.build  |  22 --
 src/gallium/drivers/r600/meson.build | 128 +++
 src/gallium/meson.build  |   6 +-
 src/gallium/targets/dri/meson.build  |   7 +-
 4 files changed, 154 insertions(+), 9 deletions(-)
 create mode 100644 src/gallium/drivers/r600/meson.build

diff --git a/meson.build b/meson.build
index 05f171e4d44..12816a2535f 100644
--- a/meson.build
+++ b/meson.build
@@ -119,6 +119,7 @@ with_gallium = false
 with_gallium_pl111 = false
 with_gallium_radeonsi = false
 with_gallium_r300 = false
+with_gallium_r600 = false
 with_gallium_nouveau = false
 with_gallium_freedreno = false
 with_gallium_softpipe = false
@@ -132,7 +133,7 @@ if _drivers == 'auto'
   if not ['darwin', 'windows'].contains(host_machine.system())
 # TODO: PPC, Sparc
 if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-  _drivers = 'r300,radeonsi,nouveau,swrast'
+  _drivers = 'r300,r600,radeonsi,nouveau,swrast'
 elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
   _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,swrast'
 else
@@ -147,6 +148,7 @@ if _drivers != ''
   with_gallium_pl111 = _split.contains('pl111')
   with_gallium_radeonsi = _split.contains('radeonsi')
   with_gallium_r300 = _split.contains('r300')
+  with_gallium_r600 = _split.contains('r600')
   with_gallium_nouveau = _split.contains('nouveau')
   with_gallium_freedreno = _split.contains('freedreno')
   with_gallium_softpipe = _split.contains('swrast')
@@ -678,9 +680,13 @@ dep_thread = dependency('threads')
 if dep_thread.found() and host_machine.system() == 'linux'
   pre_args += '-DHAVE_PTHREAD'
 endif
-dep_elf = dependency('libelf', required : false)
-if not dep_elf.found() and (with_amd_vk or with_gallium_radeonsi) # TODO: 
clover, r600
-  dep_elf = cc.find_library('elf')
+if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: clover
+  dep_elf = dependency('libelf', required : false)
+  if not dep_elf.found()
+dep_elf = cc.find_library('elf')
+  endif
+else
+  dep_elf = []
 endif
 dep_expat = dependency('expat')
 # this only exists on linux so either this is linux and it will be found, or
@@ -695,7 +701,8 @@ dep_libdrm_freedreno = []
 if with_amd_vk or with_gallium_radeonsi
   dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.88')
 endif
-if with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or with_gallium_r300
+if (with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or
+with_gallium_r300 or with_gallium_r600)
   dep_libdrm_radeon = dependency('libdrm_radeon', version : '>= 2.4.71')
 endif
 if with_gallium_nouveau or with_dri_nouveau
@@ -709,8 +716,11 @@ if with_gallium_freedreno
 endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
-if with_amd_vk or with_gallium_radeonsi # TODO: r600
+if with_amd_vk or with_gallium_radeonsi or with_gallium_r600
   llvm_modules += ['amdgpu', 'bitreader', 'ipo']
+  if with_gallium_r600
+llvm_modules += 'asmparser'
+  endif
 endif
 dep_llvm = []
 if with_llvm
diff --git a/src/gallium/drivers/r600/meson.build 
b/src/gallium/drivers/r600/meson.build
new file mode 100644
index 000..411b550331d
--- /dev/null
+++ b/src/gallium/drivers/r600/meson.build
@@ -0,0 +1,128 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_r600 = files(
+  'r600d_common.h',
+  'compute_memory_pool.c',
+  'compute_memory_pool.h',
+  'eg_asm.c',
+  'eg_debug.c',
+  'eg_sq.h',
+  'evergreen_compute.c',
+  'evergreen_compute.h',
+  'evergreen_compute_internal.h',
+  'evergreend.h',
+  'evergreen_hw_context.c',
+  'evergreen_state.c',
+  'r600_asm.c',
+  'r600_asm.h',
+  'r600_blit.c',
+  'r600d.h',
+  'r600_formats.h',
+  'r600_hw_context.c',
+  'r600_isa.c',
+  'r600_isa.h',
+  'r600_opcodes.h',
+  'r600_pipe.c',
+  

[Mesa-dev] [PATCH v3 02/15] meson: build i915g driver

[Dylan Baker]

Build tested only.

Signed-off-by: Dylan Baker 
---
 meson.build |  7 +++-
 src/gallium/drivers/i915/meson.build| 70 +
 src/gallium/meson.build |  7 ++--
 src/gallium/targets/dri/meson.build |  5 +++
 src/gallium/winsys/i915/drm/meson.build | 31 +++
 5 files changed, 116 insertions(+), 4 deletions(-)
 create mode 100644 src/gallium/drivers/i915/meson.build
 create mode 100644 src/gallium/winsys/i915/drm/meson.build

diff --git a/meson.build b/meson.build
index 8ea2b3e106c..e80c128f6db 100644
--- a/meson.build
+++ b/meson.build
@@ -125,6 +125,7 @@ with_gallium_vc4 = false
 with_gallium_vc5 = false
 with_gallium_etnaviv = false
 with_gallium_imx = false
+with_gallium_i915 = false
 _drivers = get_option('gallium-drivers')
 if _drivers == 'auto'
   if not ['darwin', 'windows'].contains(host_machine.system())
@@ -151,6 +152,7 @@ if _drivers != ''
   with_gallium_vc5 = _split.contains('vc5')
   with_gallium_etnaviv = _split.contains('etnaviv')
   with_gallium_imx = _split.contains('imx')
+  with_gallium_i915 = _split.contains('i915')
   with_gallium = true
 endif
 
@@ -180,12 +182,15 @@ endif
 if with_dri_swrast and with_gallium_softpipe
   error('Only one swrast provider can be built')
 endif
+if with_dri_i915 and with_gallium_i915
+  error('Only one i915 provider can be built')
+endif
 if with_gallium_imx and not with_gallium_etnaviv
   error('IMX driver requires etnaviv driver')
 endif
 
 dep_libdrm_intel = []
-if with_dri_i915
+if with_dri_i915 or with_gallium_i915
   dep_libdrm_intel = dependency('libdrm_intel', version : '>= 2.4.75')
 endif
 
diff --git a/src/gallium/drivers/i915/meson.build 
b/src/gallium/drivers/i915/meson.build
new file mode 100644
index 000..17f0f6adf8f
--- /dev/null
+++ b/src/gallium/drivers/i915/meson.build
@@ -0,0 +1,70 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_i915 = files(
+  'i915_batchbuffer.h',
+  'i915_batch.h',
+  'i915_blit.c',
+  'i915_blit.h',
+  'i915_clear.c',
+  'i915_context.c',
+  'i915_context.h',
+  'i915_debug.c',
+  'i915_debug_fp.c',
+  'i915_debug.h',
+  'i915_debug_private.h',
+  'i915_flush.c',
+  'i915_fpc_emit.c',
+  'i915_fpc.h',
+  'i915_fpc_optimize.c',
+  'i915_fpc_translate.c',
+  'i915_prim_emit.c',
+  'i915_prim_vbuf.c',
+  'i915_public.h',
+  'i915_query.c',
+  'i915_query.h',
+  'i915_reg.h',
+  'i915_resource_buffer.c',
+  'i915_resource.c',
+  'i915_resource.h',
+  'i915_resource_texture.c',
+  'i915_screen.c',
+  'i915_screen.h',
+  'i915_state.c',
+  'i915_state_derived.c',
+  'i915_state_dynamic.c',
+  'i915_state_emit.c',
+  'i915_state_fpc.c',
+  'i915_state.h',
+  'i915_state_immediate.c',
+  'i915_state_inlines.h',
+  'i915_state_sampler.c',
+  'i915_state_static.c',
+  'i915_surface.c',
+  'i915_surface.h',
+  'i915_winsys.h',
+)
+
+libi915 = static_library(
+  'i915',
+  files_i915,
+  c_args : [c_vis_args],
+  include_directories : [inc_include, inc_src, inc_gallium, inc_gallium_aux],
+)
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 7ccf4819079..715fee86d0a 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -70,17 +70,18 @@ endif
 if with_gallium_imx
   subdir('winsys/imx/drm')
 endif
-if with_glx == 'gallium-xlib'
-  subdir('winsys/sw/xlib')
+if with_gallium_i915
+  subdir('winsys/i915/drm')
+  subdir('drivers/i915')
 endif
 subdir('state_trackers/dri')
 if with_osmesa == 'gallium'
   subdir('state_trackers/osmesa')
 endif
 if with_glx == 'gallium-xlib'
+  subdir('winsys/sw/xlib')
   subdir('state_trackers/glx/xlib')
 endif
-# TODO: i915
 # TODO: SVGA
 # TODO: r300
 # TODO: r600
diff --git a/src/gallium/targets/dri/meson.build 
b/src/gallium/targets/dri/meson.build
index c591b75d037..de97e8afeaf 100644
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -107,6 +107,11 @@ if 

[Mesa-dev] [PATCH v3 13/15] meson: build gallium omx state tracker

[Dylan Baker]

v2: - set with_gallium_omx when -Dgallium-omx=true
- Fix detection of omx plugins dir
- only use cflags from pkg-config, don't add linker flags.
---
 meson.build| 60 -
 meson_options.txt  | 13 
 src/gallium/meson.build|  7 +-
 .../state_trackers/omx_bellagio/meson.build| 30 +
 src/gallium/targets/omx-bellagio/meson.build   | 77 ++
 5 files changed, 185 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/state_trackers/omx_bellagio/meson.build
 create mode 100644 src/gallium/targets/omx-bellagio/meson.build

diff --git a/meson.build b/meson.build
index 9c7a5062a7d..b1a09a0b6c9 100644
--- a/meson.build
+++ b/meson.build
@@ -429,6 +429,64 @@ if xvmc_drivers_path == ''
   xvmc_drivers_path = get_option('libdir')
 endif
 
+dep_omx = []
+_omx = get_option('gallium-omx')
+if _omx == 'auto'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+with_gallium_omx = false
+  elif not with_platform_x11
+with_gallium_omx = false
+  elif not (with_gallium_r600 or with_gallium_radeonsi or with_gallium_nouveau)
+with_gallium_omx = false
+  else
+dep_omx = dependency('libomxil-bellagio', required : false)
+with_gallium_omx = dep_omx.found()
+  endif
+elif _omx == 'true'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+error('OMX state tracker can only be built on unix-like OSes.')
+  elif not (with_platform_x11 or with_platform_drm)
+error('OMX state tracker requires X11 or drm platform support.')
+with_gallium_omx = false
+  elif not (with_gallium_r600 or with_gallium_radeonsi or with_gallium_nouveau)
+error('OMX state tracker requires at least one of the following gallium 
drivers: r600, radeonsi, nouveau.')
+  endif
+  dep_omx = dependency('libomxil-bellagio')
+  with_gallium_omx = true
+else
+  with_gallium_omx = false
+endif
+
+omx_drivers_path = get_option('omx-libs-path')
+if with_gallium_omx
+  # Figure out where to put the omx driver.
+  # FIXME: this could all be vastly simplified by adding a 'defined_variable'
+  # argument to meson's get_pkgconfig_variable method.
+  if omx_drivers_path == ''
+_omx_libdir = dep_omx.get_pkgconfig_variable('libdir')
+_omx_drivers_dir = dep_omx.get_pkgconfig_variable('pluginsdir')
+if _omx_libdir == get_option('libdir')
+  omx_drivers_path = _omx_drivers_dir
+else
+  _omx_base_dir = []
+  # This will fail on windows. Does OMX run on windows?
+  _omx_libdir = _omx_libdir.split('/')
+  _omx_drivers_dir = _omx_drivers_dir.split('/')
+  foreach o : _omx_drivers_dir
+if not _omx_libdir.contains(o)
+  _omx_base_dir += o
+endif
+  endforeach
+  omx_drivers_path = join_paths(get_option('libdir'), _omx_base_dir)
+endif
+  endif
+endif
+if with_gallium_omx
+  dep_omx = declare_dependency(
+compile_args : dep_omx.get_pkgconfig_variable('cflags').split()
+  )
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
@@ -936,7 +994,7 @@ if with_platform_x11
 dep_xxf86vm = dependency('xxf86vm', required : false)
   endif
   if (with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm') or
-  (with_gallium_vdpau or with_gallium_xvmc))
+  (with_gallium_vdpau or with_gallium_xvmc or with_gallium_omx))
 dep_xcb = dependency('xcb')
 dep_x11_xcb = dependency('x11-xcb')
 dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
diff --git a/meson_options.txt b/meson_options.txt
index f0de44e751b..8ee216d5b8a 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -75,6 +75,19 @@ option(
   value : '',
   description : 'path to put xvmc libraries. defaults to $libdir.'
 )
+option(
+  'gallium-omx',
+  type : 'combo',
+  value : 'auto',
+  choices : ['auto', 'true', 'false'],
+  description : 'enable gallium omx bellagio state tracker.',
+)
+option(
+  'omx-libs-path',
+  type : 'string',
+  value : '',
+  description : 'path to put omx libraries. defaults to omx-bellagio 
pkg-config pluginsdir.'
+)
 option(
   'vulkan-drivers',
   type : 'string',
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index a8317a53552..c17dba51ff2 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -105,6 +105,9 @@ endif
 if with_gallium_xvmc
   subdir('state_trackers/xvmc')
 endif
+if with_gallium_omx
+  subdir('state_trackers/omx_bellagio')
+endif
 # TODO: SWR
 # TODO: clover
 if with_dri and with_gallium
@@ -122,7 +125,9 @@ endif
 if with_gallium_xvmc
   subdir('targets/xvmc')
 endif
-# TODO: OMX
+if with_gallium_omx
+  subdir('targets/omx-bellagio')
+endif
 # TODO: VA
 # TODO: xa
 # TODO: nine
diff --git a/src/gallium/state_trackers/omx_bellagio/meson.build 
b/src/gallium/state_trackers/omx_bellagio/meson.build
new file mode 100644
index 000..a62a31149e2
--- /dev/null
+++ 

[Mesa-dev] [PATCH v3 11/15] meson: build gallium vdpau state tracker

[Dylan Baker]

v2: - set with_gallium_vdpau when -Dgallium-vdpau=true
- Install megadriver hard links and symlinks
- only use cflags from pkg-config, don't add linker flags.
---
 meson.build  | 46 -
 meson_options.txt| 13 
 src/gallium/meson.build  |  7 +-
 src/gallium/state_trackers/vdpau/meson.build | 32 +
 src/gallium/targets/vdpau/meson.build| 99 
 5 files changed, 195 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/state_trackers/vdpau/meson.build
 create mode 100644 src/gallium/targets/vdpau/meson.build

diff --git a/meson.build b/meson.build
index 0f6644a1be4..289c12cd1b6 100644
--- a/meson.build
+++ b/meson.build
@@ -348,6 +348,49 @@ if with_dri or with_gallium
   endif
 endif
 
+dep_vdpau = []
+_vdpau = get_option('gallium-vdpau')
+if _vdpau == 'auto'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+with_gallium_vdpau = false
+  elif not with_platform_x11
+with_gallium_vdpau = false
+  elif not (with_gallium_r300 or with_gallium_r600 or with_gallium_radeonsi or
+with_gallium_nouveau)
+with_gallium_vdpau = false
+  else
+dep_vdpau = dependency('vdpau', version : '>= 1.1', required : false)
+with_gallium_vdpau = dep_vdpau.found()
+  endif
+elif _vdpau == 'true'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+error('VDPAU state tracker can only be build on unix-like OSes.')
+  elif not with_platform_x11
+error('VDPAU state tracker requires X11 support.')
+with_gallium_vdpau = false
+  elif not (with_gallium_r300 or with_gallium_r600 or with_gallium_radeonsi or
+with_gallium_nouveau)
+error('VDPAU state tracker requires at least one of the following gallium 
drivers: r300, r600, radeonsi, nouveau.')
+  endif
+  dep_vdpau = dependency('vdpau', version : '>= 1.1')
+  with_gallium_vdpau = true
+else
+  with_gallium_vdpau = false
+endif
+if with_gallium_vdpau
+  dep_vdpau = declare_dependency(
+compile_args : dep_vdpau.get_pkgconfig_variable('cflags').split()
+  )
+endif
+
+if with_gallium_vdpau
+  pre_args += '-DHAVE_ST_VDPAU'
+endif
+vdpau_drivers_path = get_option('vdpau-libs-path')
+if vdpau_drivers_path == ''
+  vdpau_drivers_path = join_paths(get_option('libdir'), 'vdpau')
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
@@ -854,7 +897,8 @@ if with_platform_x11
 dep_xcb_glx = dependency('xcb-glx', version : '>= 1.8.1')
 dep_xxf86vm = dependency('xxf86vm', required : false)
   endif
-  if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
+  if (with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm') or
+  with_gallium_vdpau)
 dep_xcb = dependency('xcb')
 dep_x11_xcb = dependency('x11-xcb')
 dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
diff --git a/meson_options.txt b/meson_options.txt
index 119bec15709..78b78a92dbf 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -49,6 +49,19 @@ option(
   value : 'auto',
   description : 'comma separated list of gallium drivers to build. If this is 
set to auto all drivers applicable to the target OS/architecture will be built'
 )
+option(
+  'gallium-vdpau',
+  type : 'combo',
+  value : 'auto',
+  choices : ['auto', 'true', 'false'],
+  description : 'enable gallium vdpau state tracker.',
+)
+option(
+  'vdpau-libs-path',
+  type : 'string',
+  value : '',
+  description : 'path to put vdpau libraries. defaults to $libdir/vdpau.'
+)
 option(
   'vulkan-drivers',
   type : 'string',
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 8e8b1466f12..446710e1495 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -99,6 +99,9 @@ if with_glx == 'gallium-xlib'
   subdir('winsys/sw/xlib')
   subdir('state_trackers/glx/xlib')
 endif
+if with_gallium_vdpau
+  subdir('state_trackers/vdpau')
+endif
 # TODO: SWR
 # TODO: clover
 if with_dri and with_gallium
@@ -110,9 +113,11 @@ endif
 if with_glx == 'gallium-xlib'
   subdir('targets/libgl-xlib')
 endif
+if with_gallium_vdpau
+  subdir('targets/vdpau')
+endif
 # TODO: OMX
 # TODO: VA
-# TODO: vdpau
 # TODO: xa
 # TODO: xvmc
 # TODO: nine
diff --git a/src/gallium/state_trackers/vdpau/meson.build 
b/src/gallium/state_trackers/vdpau/meson.build
new file mode 100644
index 000..9678b79ef6c
--- /dev/null
+++ b/src/gallium/state_trackers/vdpau/meson.build
@@ -0,0 +1,32 @@
+# Copyright © 2017 Intel Corproration
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to 

[Mesa-dev] [PATCH v3 05/15] meson: build svga driver on linux

[Dylan Baker]

Build tested only.

Signed-off-by: Dylan Baker 
---
 meson.build |  6 ++-
 src/gallium/drivers/svga/meson.build| 88 +
 src/gallium/meson.build |  5 +-
 src/gallium/targets/dri/meson.build |  5 ++
 src/gallium/winsys/svga/drm/meson.build | 45 +
 5 files changed, 146 insertions(+), 3 deletions(-)
 create mode 100644 src/gallium/drivers/svga/meson.build
 create mode 100644 src/gallium/winsys/svga/drm/meson.build

diff --git a/meson.build b/meson.build
index 12816a2535f..f33d002843e 100644
--- a/meson.build
+++ b/meson.build
@@ -128,14 +128,15 @@ with_gallium_vc5 = false
 with_gallium_etnaviv = false
 with_gallium_imx = false
 with_gallium_i915 = false
+with_gallium_svga = false
 _drivers = get_option('gallium-drivers')
 if _drivers == 'auto'
   if not ['darwin', 'windows'].contains(host_machine.system())
 # TODO: PPC, Sparc
 if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-  _drivers = 'r300,r600,radeonsi,nouveau,swrast'
+  _drivers = 'r300,r600,radeonsi,nouveau,svga,swrast'
 elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-  _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,swrast'
+  _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,svga,swrast'
 else
   error('Unknown architecture. Please pass -Dgallium-drivers to set driver 
options. Patches gladly accepted to fix this.')
 endif
@@ -157,6 +158,7 @@ if _drivers != ''
   with_gallium_etnaviv = _split.contains('etnaviv')
   with_gallium_imx = _split.contains('imx')
   with_gallium_i915 = _split.contains('i915')
+  with_gallium_svga = _split.contains('svga')
   with_gallium = true
 endif
 
diff --git a/src/gallium/drivers/svga/meson.build 
b/src/gallium/drivers/svga/meson.build
new file mode 100644
index 000..d9a7da95a33
--- /dev/null
+++ b/src/gallium/drivers/svga/meson.build
@@ -0,0 +1,88 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_svga = files(
+  'svga_cmd.c',
+  'svga_cmd_vgpu10.c',
+  'svga_context.c',
+  'svga_draw_arrays.c',
+  'svga_draw.c',
+  'svga_draw_elements.c',
+  'svga_format.c',
+  'svga_link.c',
+  'svga_msg.c',
+  'svga_pipe_blend.c',
+  'svga_pipe_blit.c',
+  'svga_pipe_clear.c',
+  'svga_pipe_constants.c',
+  'svga_pipe_depthstencil.c',
+  'svga_pipe_draw.c',
+  'svga_pipe_flush.c',
+  'svga_pipe_fs.c',
+  'svga_pipe_gs.c',
+  'svga_pipe_misc.c',
+  'svga_pipe_query.c',
+  'svga_pipe_rasterizer.c',
+  'svga_pipe_sampler.c',
+  'svga_pipe_streamout.c',
+  'svga_pipe_vertex.c',
+  'svga_pipe_vs.c',
+  'svga_resource_buffer.c',
+  'svga_resource_buffer_upload.c',
+  'svga_resource.c',
+  'svga_resource_texture.c',
+  'svga_sampler_view.c',
+  'svga_screen.c',
+  'svga_screen_cache.c',
+  'svga_shader.c',
+  'svga_state.c',
+  'svga_state_constants.c',
+  'svga_state_framebuffer.c',
+  'svga_state_fs.c',
+  'svga_state_gs.c',
+  'svga_state_need_swtnl.c',
+  'svga_state_rss.c',
+  'svga_state_sampler.c',
+  'svga_state_tgsi_transform.c',
+  'svga_state_tss.c',
+  'svga_state_vdecl.c',
+  'svga_state_vs.c',
+  'svga_surface.c',
+  'svga_swtnl_backend.c',
+  'svga_swtnl_draw.c',
+  'svga_swtnl_state.c',
+  'svga_tgsi.c',
+  'svga_tgsi_decl_sm30.c',
+  'svga_tgsi_insn.c',
+  'svga_tgsi_vgpu10.c',
+  'svgadump/svga_dump.c',
+  'svgadump/svga_shader_dump.c',
+  'svgadump/svga_shader_op.c',
+)
+
+libsvga = static_library(
+  'svga',
+  files_svga,
+  c_args : [c_vis_args, c_msvc_compat_args],
+  include_directories : [
+inc_src, inc_include, inc_gallium, inc_gallium_aux,
+include_directories('include')
+  ],
+)
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 2568e5ddcfc..2a4cb66ad7a 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -81,6 +81,10 @@ if with_gallium_i915
   subdir('winsys/i915/drm')
   subdir('drivers/i915')
 endif
+if with_gallium_svga
+  

[Mesa-dev] [PATCH v3 01/15] meson: add proper LLVM modules to check for RadeonSI as well

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index e8467590df2..8ea2b3e106c 100644
--- a/meson.build
+++ b/meson.build
@@ -702,7 +702,7 @@ if with_gallium_freedreno
 endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
-if with_amd_vk
+if with_amd_vk or with_gallium_radeonsi # TODO: r600
   llvm_modules += ['amdgpu', 'bitreader', 'ipo']
 endif
 dep_llvm = []
-- 
2.15.0

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Re: [Mesa-dev] [PATCH 4/4] i965: Use prepare_external instead of make_shareable in setTexBuffer2

[Kenneth Graunke]

On Wednesday, November 8, 2017 3:20:47 PM PST Jason Ekstrand wrote:
> The setTexBuffer2 hook from GLX is used to implement glxBindTexImageEXT
> which has tighter restrictions than just "it's shared".  In particular,
> it says that any rendering to the image while it is bound causes the
> contents to become undefined.
> 
> The GLX_EXT_texture_from_pixmap extension provides us with an acquire
> and release in the form of glXBindTexImageEXT and glXReleaseTexImageEXT.
> The extension spec says,
> 
> "Rendering to the drawable while it is bound to a texture will leave
> the contents of the texture in an undefined state.  However, no
> synchronization between rendering and texturing is done by GLX.  It
> is the application's responsibility to implement any synchronization
> required."
> 
> From the EGL 1.4 spec for eglBindTexImage:
> 
> "After eglBindTexImage is called, the specified surface is no longer
> available for reading or writing.  Any read operation, such as
> glReadPixels or eglCopyBuffers, which reads values from any of the
> surface’s color buffers or ancillary buffers will produce
> indeterminate results.  In addition, draw operations that are done
> to the surface before its color buffer is released from the texture
> produce indeterminate results
> 
> In other words, between the bind and release calls, we effectively own
> those pixels and can assume, so long as we don't crash, that no one else
> is reading from/writing to the surface.  The GLX and EGL implementations
> call the setTexBuffer2 and releaseTexBuffer function pointers that the
> driver can hook.
> 
> In theory, this means that, between BindTexImage and ReleaseTexImage, we
> own the pixels and it should be safe to track aux usage so we
> can avoid redundant resolves so long as we start off with the right
> assumption at the start of the bind/release pair.
> 
> In practice, however, X11 has slightly different expectations.  It's
> expected that the server may be drawing to the image at the same time as
> the compositor is texturing from it.  In that case, the worst expected
> outcome should be tearing or partial rendering and not random corruption
> like we see when rendering races with scanout with CCS.  Fortunately,
> the GEM rules about texture/render dependencies save us here.  If X11
> submits work to write to a pixmap after the compositor has submitted
> work to texture from it, GEM inserts a dependency between the compositor
> and X11.  If X11 is using a high-priority context, this will cause the
> compositor to get a temporarily boosted priority while the batch from
> X11 is waiting on it.  This means that we will never have an actual race
> between X11 and the compositor so no corruption can happen.
> 
> Unfortunately, however, this means that X11 will likely be rendering to it
> between the compositor's BindTexImage and ReleaseTexImage calls.  If we
> want to avoid strange issues, we need to be a bit careful about
> resolves because we can't really transition it away from the "default"
> aux usage.  The only case where this would practically be a problem is
> with image_load_store where we have to do a full resolve in order to use
> the image via the data port.  Even there it would only be a problem if
> batches were split such that X11's rendering happens between the resolve
> and the use of it as a storage image.  However, the chances of this
> happening are very slim so we just emit a warning and hope for the best.
> 
> This commit adds a new helper intel_miptree_finish_external which resets
> all aux state to whatever ISL says is the right worst-case "default" for
> the given modifier.  It feels a little awkward to call it "finish"
> because it's actually an acquire from the perspective of the driver, but
> it matches the semantics of the other prepare/finish functions.  This
> new helper gets called in intelSetTexBuffer2 instead of make_shareable.
> We also add an intelReleaseTexBuffer (we passed NULL to releaseTexBuffer
> before) and call intel_miptree_prepare_external in it.  This probably
> does nothing most of the time but it means that the prepare/finish calls
> are properly matched.
> 
> Cc: "17.3" 
> Cc: Chad Versace 
> Cc: Daniel Stone 
> Cc: Louis-Francis Ratté-Boulianne 
> Cc: Adam Jackson 
> Cc: Chris Wilson 
> Cc: Keith Packard 
> Cc: Eric Anholt 

I'm going to go out on a limb and offer you a
Reviewed-by: Kenneth Graunke 
for the series (assuming you fix the issue Emil caught).

Hopefully some of the other fine people in the CC list have looked
at it and are happy with it as well.


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Re: [Mesa-dev] [PATCH 10/10] spirv: Generate SPIR-V builder infrastructure

[Dylan Baker]

Quoting Ian Romanick (2017-11-13 16:00:08)
> 
> That's what I had first, and it did not work in some cases.  I believe
> that list==list is only True if the elements have the same order.  This
> function only requires that both lists have the same contents without
> regard for order.  I will add a comment to that effect.

Okay, that seems good then. I would have suggested a conversion to sets, but I 
just
benchmarked it and it's 30% slower than what you have.


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Re: [Mesa-dev] [PATCH 2/4] i965: Add more precise cache tracking helpers

[Kenneth Graunke]

On Monday, November 6, 2017 1:38:55 PM PST Jason Ekstrand wrote:
> In theory, this will let us track the depth and render caches
> separately.  Right now, they're just wrappers around
> brw_render_cache_set_*
> ---
>  src/mesa/drivers/dri/i965/brw_draw.c  | 12 +--
>  src/mesa/drivers/dri/i965/brw_misc_state.c|  4 ++--
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c   | 10 -
>  src/mesa/drivers/dri/i965/intel_fbo.c | 29 
> +++
>  src/mesa/drivers/dri/i965/intel_fbo.h |  6 ++
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  2 +-
>  6 files changed, 49 insertions(+), 14 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
> b/src/mesa/drivers/dri/i965/brw_draw.c
> index 10b6298..8920b00 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -426,7 +426,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
> rendering)
>  min_layer, num_layers,
>  disable_aux);
>  
> -  brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
> +  brw_cache_flush_for_read(brw, tex_obj->mt->bo);
>  
>if (tex_obj->base.StencilSampling ||
>tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
> @@ -450,7 +450,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
> rendering)
>  
> intel_miptree_prepare_image(brw, tex_obj->mt);
>  
> -   brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
> +   brw_cache_flush_for_read(brw, tex_obj->mt->bo);
>  }
>   }
>}
> @@ -561,11 +561,11 @@ brw_postdraw_set_buffers_need_resolve(struct 
> brw_context *brw)
>  depth_written);
>}
>if (depth_written)
> - brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
> + brw_depth_cache_add_bo(brw, depth_irb->mt->bo);
> }
>  
> if (stencil_irb && brw->stencil_write_enabled)
> -  brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
> +  brw_depth_cache_add_bo(brw, stencil_irb->mt->bo);
>  
> for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
>struct intel_renderbuffer *irb =
> @@ -578,7 +578,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
> *brw)
>   _mesa_get_render_format(ctx, intel_rb_format(irb));
>enum isl_format isl_format = 
> brw_isl_format_for_mesa_format(mesa_format);
>  
> -  brw_render_cache_set_add_bo(brw, irb->mt->bo);
> +  brw_render_cache_add_bo(brw, irb->mt->bo);
>intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
>irb->mt_layer, irb->layer_count,
>isl_format,
> @@ -593,7 +593,7 @@ intel_renderbuffer_move_temp_back(struct brw_context *brw,
> if (irb->align_wa_mt == NULL)
>return;
>  
> -   brw_render_cache_set_check_flush(brw, irb->align_wa_mt->bo);
> +   brw_cache_flush_for_read(brw, irb->align_wa_mt->bo);
>  
> intel_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
>  irb->mt,
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 53137cc..fd96485 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -333,9 +333,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
> }
>  
> if (depth_mt)
> -  brw_render_cache_set_check_flush(brw, depth_mt->bo);
> +  brw_cache_flush_for_depth(brw, depth_mt->bo);
> if (stencil_mt)
> -  brw_render_cache_set_check_flush(brw, stencil_mt->bo);
> +  brw_cache_flush_for_depth(brw, stencil_mt->bo);
>  
> brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
>  depthbuffer_format, depth_surface_type,
> diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
> b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> index 3c7a7b4..296a83b 100644
> --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> @@ -215,8 +215,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
>  * data.
>  */
> if (params->src.enabled)
> -  brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
> -   brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
> +  brw_cache_flush_for_read(brw, params->src.addr.buffer);
> +   brw_cache_flush_for_render(brw, params->dst.addr.buffer);

This drops the cache flush, because brw_cache_flush_for_render
is an empty function.  I don't think you intended to do that.

You probably want brw_cache_flush_for_render to do
brw_render_cache_set_check_flush until patch 4.

Otherwise, the series is:
Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 10/10] spirv: Generate SPIR-V builder infrastructure

[Ian Romanick]

On 11/13/2017 02:01 PM, Dylan Baker wrote:
> Quoting Ian Romanick (2017-11-10 14:32:50)
> [snip]
>> +
>> +def can_have_extra_operands(name, enums):
>> +"""Determine whether an enum can have extra operands.
>> +
>> +Some enums, like SpvDecoration, can have extra operands with some 
>> values.
>> +Other enums, like SpvMemorySemantics, cannot.
>> +"""
>> +
>> +if name not in enums:
>> +return False
>> +
>> +for parameter in enums[name][1]:
>> +if len(parameter[2]) > 0:
> 
> Not using len() here would be faster:
> if parameter[2]:
> return True
> 
> Or, if you like a more functional approach you could do something like:
> return any(p[2] for p in enums[name][1])
> 
>> +return True
>> +
>> +return False
>> +
>> +def prototype_for_instruction_emit(inst, all_enums, bit_enums):
>> +parameters = ["spirv_program *prog"]
>> +
>> +if "operands" in inst:
>> +parameters = parameters + [declare_parameter(operand, all_enums, 
>> bit_enums) for operand in inst["operands"]]
>> +
>> +return textwrap.dedent("""\
>> +static inline void
>> +emit_Spv{name}({parameters})""".format(name=inst["opname"],
>> +   parameters=",\n
>> ".join(parameters)))
>> +
>> +
>> +def default_value(parameter, bit_enums):
>> +"""Determine whether an enum has a value that is the default when the 
>> enum is
>> +not specified.
>> +
>> +Some enums are almost always marked as optional on the instructions that
>> +use them.  Some of these, like SpvMemoryAccess, have a value that is
>> +assumed when the value is not specificed in the instruction.
>> +"""
>> +
>> +pass
> 
> This function appears to be unused.
> 
>> +
>> +def instruction_size(instruction, enums):
>> +"""Determine the size of an instruction based on its operands
>> +
>> +Instructions that have only operands without ? or * quantifiers are 
>> sized
>> +by the number of operands.  In addition, instructions that have certain
>> +BitEnum and ValueEnum parameters also have varying sizes.
>> +"""
>> +
>> +if "operands" not in instruction:
>> +# Instructions like OpNop that have no operands.  Handle these with 
>> a
>> +# trivial special case.
>> +return 1
>> +
>> +for operand in instruction["operands"]:
>> +if "quantifier" in operand:
>> +return 0
>> +elif operand["kind"] == "LiteralString":
>> +return 0
>> +elif operand["kind"] in enums and enums[operand["kind"]][0]:
>> +return 0
>> +
>> +return len(instruction["operands"]) + 1
>> +
>> +def optional_parameter_flag(operand, bit_enums):
>> +"""Return the name of the flag for an optional parameter, None otherwise
>> +
>> +Optional parameters are noted in the JSON with a "?" quantifier.  For 
>> some
>> +types, it is possible to infer that a value does not exist by examining
>> +the value.  For example, if a optional LiteralString parameter is NULL, 
>> it
>> +is not included.  The same applies for some BitEnum kinds such as
>> +ImageOperands. For cases where the existence cannot be infered from the
>> +value, a "has_foo" flag is added to the parameter list.
>> +
>> +This function returns either the has_foo name as a string or None.
>> +"""
>> +
>> +if operand["kind"] == "LiteralString":
>> +return None
>> +
>> +if operand["kind"] == "ImageOperands":
>> +return None
>> +
>> +if operand["kind"] in bit_enums:
>> +return None
>> +
>> +if "quantifier" not in operand or operand["quantifier"] != "?":
>> +return None
>> +
>> +return "has_" + operand_name(operand)
>> +
>> +def operand_name(operand):
>> +if operand["kind"] == "IdResult":
>> +return "result"
>> +elif operand["kind"] == "IdResultType":
>> +return "result_type"
>> +elif "name" in operand:
>> +if "quantifier" in operand and "+" in operand["name"]:
>> +return operand["kind"]
>> +elif operand["name"] == "'D~ref~'":
>> +return "deref"
>> +else:
>> +name=operand["name"].replace("'", "").replace(" ", 
>> "_").replace(".", "").replace("~","_").lower()
>> +return name if name not in ["default"] else "_" + name
>> +else:
>> +return operand["kind"]
>> +
>> +def list_is_same(a, b):
>> +if len(a) != len(b):
>> +return False
>> +
>> +for x in a:
>> +if x not in b:
>> +return False
>> +
>> +return True
> 
> is there a reason you canot just do `a == b`?

That's what I had first, and it did not work in some cases.  I believe
that list==list is only True if the elements have the same order.  This
function only requires that both lists have the same contents without
regard for order.  I will add a comment to that effect.

>> +
>> +def capabilities_are_same(enums):
>> +for parameter in enums[1:]:
>> 

Re: [Mesa-dev] [PATCH 11/11] intel/tools/error: Decode compute shaders.

[Lionel Landwerlin]

On 13/11/17 21:40, Kenneth Graunke wrote:

On Sunday, November 12, 2017 4:06:06 AM PST Lionel Landwerlin wrote:

On 12/11/17 08:35, Kenneth Graunke wrote:

This is a bit more annoying than your average shader - we need to look
at MEDIA_INTERFACE_DESCRIPTOR_LOAD in the batch buffer, then hop over
to the dynamic state buffer to read the INTERFACE_DESCRIPTOR_DATA, then
hop over to the instruction buffer to decode the program.

Now that we store all the buffers before decoding, we can actually do
this fairly easily.
---
   src/intel/tools/aubinator_error_decode.c | 49 
+++-
   1 file changed, 42 insertions(+), 7 deletions(-)

diff --git a/src/intel/tools/aubinator_error_decode.c 
b/src/intel/tools/aubinator_error_decode.c
index 09ca7c3a4ab..81418d69c9a 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -233,6 +233,17 @@ disassemble_program(struct gen_disasm *disasm, const char 
*type,
  gen_disasm_disassemble(disasm, instruction_section->data, ksp, stdout);
   }
   
+static const struct section *

+find_section(const char *str_base_address)
+{
+   uint64_t base_address = strtol(str_base_address, NULL, 16);
+   for (int s = 0; s < MAX_SECTIONS; s++) {
+  if (sections[s].gtt_offset == base_address)
+ return [s];
+   }
+   return NULL;
+}
+
   static void
   decode(struct gen_spec *spec, struct gen_disasm *disasm,
  const struct section *section)
@@ -243,6 +254,7 @@ decode(struct gen_spec *spec, struct gen_disasm *disasm,
  int length;
  struct gen_group *inst;
  const struct section *current_instruction_buffer = NULL;
+   const struct section *current_dynamic_state_buffer = NULL;
   
  for (p = data; p < end; p += length) {

 const char *color = option_full_decode ? BLUE_HEADER : NORMAL,
@@ -277,13 +289,9 @@ decode(struct gen_spec *spec, struct gen_disasm *disasm,
   
do {

   if (strcmp(iter.name, "Instruction Base Address") == 0) {
-   uint64_t instr_base_address = strtol(iter.value, NULL, 16);
-   current_instruction_buffer = NULL;
-   for (int s = 0; s < MAX_SECTIONS; s++) {
-  if (sections[s].gtt_offset == instr_base_address) {
- current_instruction_buffer = [s];
-  }
-   }
+   current_instruction_buffer = find_section(iter.value);
+} else if (strcmp(iter.name, "Dynamic State Base Address") == 0) {
+   current_dynamic_state_buffer = find_section(iter.value);
   }
} while (gen_field_iterator_next());
 } else if (strcmp(inst->name,   "WM_STATE") == 0 ||
@@ -380,6 +388,33 @@ decode(struct gen_spec *spec, struct gen_disasm *disasm,
   disassemble_program(disasm, type, current_instruction_buffer, 
ksp);
   printf("\n");
}
+  } else if (strcmp(inst->name, "MEDIA_INTERFACE_DESCRIPTOR_LOAD") == 0) {
+ struct gen_field_iterator iter;
+ gen_field_iterator_init(, inst, p, false);
+ uint64_t interface_offset = 0;
+ while (gen_field_iterator_next()) {

Don't want a do {} while() here too?

Oops, yes we do.  I'd written this, discovered the do-while problem,
rebased, wrote a separate patch to fix the earlier problems...but didn't
fix this one because it didn't exist yet...then forgot.

Fixed locally.  Look okay other than that?


Sure,

Reviewed-by: Lionel Landwerlin 

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Re: [Mesa-dev] [PATCH 09/11] intel/tools/error: Decode shaders while decoding batch commands.

[Lionel Landwerlin]

On 13/11/17 22:59, Kenneth Graunke wrote:

On Sunday, November 12, 2017 3:57:56 AM PST Lionel Landwerlin wrote:

On 12/11/17 08:35, Kenneth Graunke wrote:

This makes aubinator_error_decode's shader dumping work like aubinator.
Instead of printing them after the fact, it prints them right inside the
3DSTATE_VS/HS/DS/GS/PS packet that references them.  This saves you the
effort of cross-referencing things and jumping back and forth.

It also reduces a bunch of book-keeping, and eliminates the limitation
that we could only handle 4096 programs.  That code was also broken and
failed to print any shaders if there were under 4096 programs.
---
   src/intel/tools/aubinator_error_decode.c | 134 
+++
   1 file changed, 49 insertions(+), 85 deletions(-)

diff --git a/src/intel/tools/aubinator_error_decode.c 
b/src/intel/tools/aubinator_error_decode.c
index cea68523ae2..96b4989936e 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -221,35 +221,28 @@ struct section {
   #define MAX_SECTIONS 30
   static struct section sections[MAX_SECTIONS];
   
-struct program {

-   const char *type;
-   const char *command;
-   uint64_t command_offset;
-   uint64_t instruction_base_address;
-   uint64_t ksp;
-};
-
-#define MAX_NUM_PROGRAMS 4096
-static struct program programs[MAX_NUM_PROGRAMS];
-static int idx_program = 0, num_programs = 0;
-
-static int next_program(void)
+static void
+disassemble_program(struct gen_disasm *disasm, const char *type,
+const struct section *instruction_section,
+uint64_t ksp)
   {
-   int ret = idx_program;
-   idx_program = (idx_program + 1) % MAX_NUM_PROGRAMS;
-   num_programs = MIN(num_programs + 1, MAX_NUM_PROGRAMS);
-   return ret;
+   if (!instruction_section)
+  return;
+
+   printf("\nReferenced %s:\n", type);
+   gen_disasm_disassemble(disasm, instruction_section->data, ksp, stdout);
   }
   
   static void

-decode(struct gen_spec *spec, const struct section *section)
+decode(struct gen_spec *spec, struct gen_disasm *disasm,
+   const struct section *section)
   {
  uint64_t gtt_offset = section->gtt_offset;
  uint32_t *data = section->data;
  uint32_t *p, *end = (data + section->count);
  int length;
  struct gen_group *inst;
-   uint64_t current_instruction_base_address = 0;
+   const struct section *current_instruction_buffer = NULL;
   
  for (p = data; p < end; p += length) {

 const char *color = option_full_decode ? BLUE_HEADER : NORMAL,
@@ -284,7 +277,13 @@ decode(struct gen_spec *spec, const struct section 
*section)
   
while (gen_field_iterator_next()) {

   if (strcmp(iter.name, "Instruction Base Address") == 0) {
-   current_instruction_base_address = strtol(iter.value, NULL, 16);
+   uint64_t instr_base_address = strtol(iter.value, NULL, 16);
+   current_instruction_buffer = NULL;
+   for (int s = 0; s < MAX_SECTIONS; s++) {
+  if (sections[s].gtt_offset == instr_base_address) {

Is it a guarantee that the instruction buffer is going to be given in
its own section?

The section corresponds to a buffer marked with EXEC_OBJECT_CAPTURE, so
assuming the driver has programmed STATE_BASE_ADDRESS to the start of a
buffer, this will be true.  Otherwise, we'll get no assembly or state
dumping.

That seems like the obvious thing for a driver to do, but I suppose they
could also point it the middle of a buffer somewhere.  Mesa and SNA both
point to the start of a buffer.

I can write a follow-up patch to allow that, if you want...


Sorry, I should have looked this up.
Looking at vaapi, it seems it uses the same approach (one BO for each 
base address).

I guess we don't need bounds checking, feel free to land!




Or do we need to check bounds ?

if (instr_base_address >= sections[s].gtt_offset && inst_base_address <=
sections[s].gtt_offset + sections[s].count * 4)

Otherwise it looks fine to me :

Reviewed-by: Lionel Landwerlin 



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[Mesa-dev] [PATCH 2/2] radv: Free temporary syncobj after waiting on it.

[Bas Nieuwenhuizen]

Otherwise we leak it.

Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
---
 src/amd/vulkan/radv_device.c | 22 ++
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4e3ad111382..60f51469c43 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1833,10 +1833,6 @@ static VkResult radv_alloc_sem_counts(struct 
radv_winsys_sem_counts *counts,
 
if (sem->temp_syncobj) {
counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
-   if (reset_temp) {
-   /* after we wait on a temp import - drop it */
-   sem->temp_syncobj = 0;
-   }
}
else if (sem->syncobj)
counts->syncobj[syncobj_idx++] = sem->syncobj;
@@ -1857,6 +1853,21 @@ void radv_free_sem_info(struct radv_winsys_sem_info 
*sem_info)
free(sem_info->signal.sem);
 }
 
+
+static void radv_free_temp_syncobjs(struct radv_device *device,
+   int num_sems,
+   const VkSemaphore *sems)
+{
+   for (uint32_t i = 0; i < num_sems; i++) {
+   RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
+
+   if (sem->temp_syncobj) {
+   device->ws->destroy_syncobj(device->ws, 
sem->temp_syncobj);
+   sem->temp_syncobj = 0;
+   }
+   }
+}
+
 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
 int num_wait_sems,
 const VkSemaphore *wait_sems,
@@ -1995,6 +2006,9 @@ VkResult radv_QueueSubmit(
}
}
 
+   radv_free_temp_syncobjs(queue->device,
+   pSubmits[i].waitSemaphoreCount,
+   pSubmits[i].pWaitSemaphores);
radv_free_sem_info(_info);
free(cs_array);
}
-- 
2.15.0

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[Mesa-dev] [PATCH 1/2] radv: Free syncobj with multiple imports.

[Bas Nieuwenhuizen]

Otherwise we can leak the old syncobj.

Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
---
 src/amd/vulkan/radv_device.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 929082182c2..4e3ad111382 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3525,6 +3525,7 @@ VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_semaphore, sem, 
pImportSemaphoreFdInfo->semaphore);
uint32_t syncobj_handle = 0;
+   uint32_t *syncobj_dst = NULL;
assert(pImportSemaphoreFdInfo->handleType == 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
 
int ret = device->ws->import_syncobj(device->ws, 
pImportSemaphoreFdInfo->fd, _handle);
@@ -3532,10 +3533,15 @@ VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
 
if (pImportSemaphoreFdInfo->flags & 
VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
-   sem->temp_syncobj = syncobj_handle;
+   syncobj_dst = >temp_syncobj;
} else {
-   sem->syncobj = syncobj_handle;
+   syncobj_dst = >syncobj;
}
+
+   if (*syncobj_dst)
+   device->ws->destroy_syncobj(device->ws, *syncobj_dst);
+
+   *syncobj_dst = syncobj_handle;
close(pImportSemaphoreFdInfo->fd);
return VK_SUCCESS;
 }
-- 
2.15.0

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Re: [Mesa-dev] [PATCH 4/4] i965: Use PTE MOCS for all external buffers

[Kenneth Graunke]

On Friday, November 3, 2017 4:17:34 PM PST Jason Ekstrand wrote:
> We were already using PTE for all render targets in case one happened to
> get scanned out.  However, this still wasn't 100% correct because there
> are still possibly cases where we may want to texture from an external
> buffer even though we don't know the caching mode.  This can happen, for
> instance, on buffers imported from another GPU via prime.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691
> Cc: Kenneth Graunke 
> Cc: Chris Wilson 
> Cc: Daniel Vetter 
> Cc: Lyude Paul 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c|  7 ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 +---
>  2 files changed, 17 insertions(+), 10 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 5a86af8..626bf44 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -114,14 +114,14 @@ brw_blorp_init(struct brw_context *brw)
> brw->blorp.upload_shader = brw_blorp_upload_shader;
>  }
>  
> -static uint32_t tex_mocs[] = {
> +static uint32_t wb_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_WB,
> [9] = SKL_MOCS_WB,
> [10] = CNL_MOCS_WB,
>  };
>  
> -static uint32_t rb_mocs[] = {
> +static uint32_t pte_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_PTE,
> [9] = SKL_MOCS_PTE,
> @@ -158,7 +158,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
>.buffer = mt->bo,
>.offset = mt->offset,
>.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
> -  .mocs = is_render_target ? rb_mocs[devinfo->gen] : 
> tex_mocs[devinfo->gen],
> +  .mocs = (is_render_target || mt->bo->external) ? 
> pte_mocs[devinfo->gen] :

I think we should make this simply mt->bo->external, dropping the
is_render_target check.  The whole is_render_target notion was a bad
approximation of "is scanned out?" which unfortunately applies to
internal FBOs too.  bo->external is a much better approximation.

I would probably make that a patch 5 though, in case we get reports
that making it regresses performance by 1,000,000%...then we could
revert that separately from this important bug fix.

> +   wb_mocs[devinfo->gen],
> };
>  
> surf->aux_usage = aux_usage;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 27c241a..f174270 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -55,20 +55,25 @@
>  #include "brw_defines.h"
>  #include "brw_wm.h"
>  
> -uint32_t tex_mocs[] = {
> +uint32_t wb_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_WB,
> [9] = SKL_MOCS_WB,
> [10] = CNL_MOCS_WB,
>  };
>  
> -uint32_t rb_mocs[] = {
> +uint32_t pte_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_PTE,
> [9] = SKL_MOCS_PTE,
> [10] = CNL_MOCS_PTE,
>  };
>  
> +static inline uint32_t get_tex_mocs(struct brw_bo *bo, unsigned int gen)
> +{
> + return (bo && bo->external ? pte_mocs : wb_mocs)[gen];

Need two more spaces here.  I might just call it get_mocs().

Either way,
Reviewed-by: Kenneth Graunke 

It would also be nice to combine the various copies of these.
I would probably just make get_mocs() a static inline in brw_state.h.


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Re: [Mesa-dev] [PATCH v3 13/48] intel/fs: Use the original destination region for int MUL lowering

[Matt Turner]

On Wed, Oct 25, 2017 at 4:25 PM, Jason Ekstrand  wrote:
> Some hardware (CHV, BXT) have special restrictions on register regions
> when doing integer multiplication.  We want to respect those when we
> lower to DxW multiplication.

This is not a good commit message. I am very familiar with the CHV,
BXT restrictions you mention and I have no idea what this patch
accomplishes.

The commit message should say what the problem is and give an example,
explain how you are fixing it, and how you can reproduce the problem.
I'm going to need at least some of that information before I can look
into the SNB regression.
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Re: [Mesa-dev] [PATCH 3/4] intel/blorp: Make the MOCS setting part of blorp_address

[Kenneth Graunke]

On Friday, November 3, 2017 4:17:33 PM PST Jason Ekstrand wrote:
> This makes our MOCS settings significantly more flexible.
> ---
>  src/intel/blorp/blorp.h |  7 +--
>  src/intel/blorp/blorp_genX_exec.h   | 16 +++
>  src/intel/vulkan/anv_blorp.c| 12 ---
>  src/intel/vulkan/genX_blorp_exec.c  |  1 +
>  src/mesa/drivers/dri/i965/brw_blorp.c   | 31 
> +++--
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c | 10 ++
>  6 files changed, 44 insertions(+), 33 deletions(-)
> 
> diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
> index 9716c66..31eb1ec 100644
> --- a/src/intel/blorp/blorp.h
> +++ b/src/intel/blorp/blorp.h
> @@ -45,12 +45,6 @@ struct blorp_context {
>  
> const struct brw_compiler *compiler;
>  
> -   struct {
> -  uint32_t tex;
> -  uint32_t rb;
> -  uint32_t vb;
> -   } mocs;
> -
> bool (*lookup_shader)(struct blorp_context *blorp,
>   const void *key, uint32_t key_size,
>   uint32_t *kernel_out, void *prog_data_out);
> @@ -94,6 +88,7 @@ struct blorp_address {
> void *buffer;
> unsigned reloc_flags;
> uint32_t offset;
> +   uint32_t mocs;
>  };
>  
>  struct blorp_surf
> diff --git a/src/intel/blorp/blorp_genX_exec.h 
> b/src/intel/blorp/blorp_genX_exec.h
> index ccbfe51..f11a1cc 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -269,7 +269,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
> vb[0].VertexBufferIndex = 0;
> vb[0].BufferPitch = 3 * sizeof(float);
>  #if GEN_GEN >= 6
> -   vb[0].VertexBufferMOCS = batch->blorp->mocs.vb;
> +   vb[0].VertexBufferMOCS = vb[0].BufferStartingAddress.mocs;
>  #endif
>  #if GEN_GEN >= 7
> vb[0].AddressModifyEnable = true;
> @@ -290,7 +290,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
> vb[1].VertexBufferIndex = 1;
> vb[1].BufferPitch = 0;
>  #if GEN_GEN >= 6
> -   vb[1].VertexBufferMOCS = batch->blorp->mocs.vb;
> +   vb[0].VertexBufferMOCS = vb[1].BufferStartingAddress.mocs;

I think you mean vb[1] here!

With that fixes, patches 1-3 are
Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

[Matt Turner]

The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.

For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.

Fixes the following test on CHV, BXT, and GLK:
   KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
---
 src/intel/compiler/brw_fs_nir.cpp | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 38d0d357e8..e266837ece 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1395,10 +1395,26 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
 
case nir_op_extract_u8:
case nir_op_extract_i8: {
-  const brw_reg_type type = brw_int_type(1, instr->op == 
nir_op_extract_i8);
   nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
   assert(byte != NULL);
-  bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+
+  /* MOV does not support a 64-bit destination and a byte source */
+  if (nir_dest_bit_size(instr->dest.dest) == 64) {
+ const brw_reg_type type = brw_int_type(2, instr->op == 
nir_op_extract_i8);
+
+ if (instr->op == nir_op_extract_i8) {
+/* If we need to sign extend, extract to a word first */
+fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
+bld.MOV(w_temp, subscript(op[0], type, byte->u32[0]));
+bld.MOV(result, w_temp);
+ } else {
+/* Otherwise use an AND with 0xff and a word type */
+bld.AND(result, subscript(op[0], type, byte->u32[0] / 2), 
brw_imm_uw(0xff));
+ }
+  } else {
+ const brw_reg_type type = brw_int_type(1, instr->op == 
nir_op_extract_i8);
+ bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+  }
   break;
}
 
-- 
2.13.6

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Re: [Mesa-dev] [RFC v5 12/19] intel/isl: Add ISL tiling -> modifier conversion

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 2:02 PM, Louis-Francis Ratté-Boulianne <
l...@collabora.com> wrote:

> From: Daniel Stone 
>
> Given a tiling mode and an aux usage, return the DRM modifier.
>
> Signed-off-by: Daniel Stone 
> ---
>  src/intel/isl/isl.h |  6 +-
>  src/intel/isl/isl_drm.c | 17 +
>  2 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> index e3acb0ec28..b255f15a5d 100644
> --- a/src/intel/isl/isl.h
> +++ b/src/intel/isl/isl.h
> @@ -1551,7 +1551,7 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
>  uint32_t
>  isl_tiling_to_i915_tiling(enum isl_tiling tiling);
>
> -enum isl_tiling
> +enum isl_tiling
>  isl_tiling_from_i915_tiling(uint32_t tiling);
>
>  const struct isl_drm_modifier_info * ATTRIBUTE_CONST
> @@ -1583,6 +1583,10 @@ isl_drm_modifier_get_default_aux_state(uint64_t
> modifier)
> ISL_AUX_STATE_COMPRESSED_NO_
> CLEAR;
>  }
>
> +uint64_t ATTRIBUTE_CONST
> +isl_drm_modifier_from_tiling(enum isl_tiling tiling,
> + enum isl_aux_usage aux_usage);
> +
>  struct isl_extent2d ATTRIBUTE_CONST
>  isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
>
> diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
> index eb3c6f5913..a40142c6ec 100644
> --- a/src/intel/isl/isl_drm.c
> +++ b/src/intel/isl/isl_drm.c
> @@ -30,6 +30,10 @@
>  #include "isl.h"
>  #include "common/gen_device_info.h"
>
> +#ifndef DRM_FORMAT_MOD_INVALID
> +#define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
> +#endif
> +
>

We include the copy of drm_foucc.h we have stashed in mesa, so you can just
assume this is defined.


>  uint32_t
>  isl_tiling_to_i915_tiling(enum isl_tiling tiling)
>  {
> @@ -106,3 +110,16 @@ isl_drm_modifier_get_info(uint64_t modifier)
>
> return NULL;
>  }
> +
> +uint64_t
> +isl_drm_modifier_from_tiling(enum isl_tiling tiling,
> + enum isl_aux_usage aux_usage)
> +{
> +   for (unsigned i = 0; i < ARRAY_SIZE(modifier_info); i++) {
> +  if (modifier_info[i].tiling == tiling &&
> +  modifier_info[i].aux_usage == aux_usage)
> + return modifier_info[i].modifier;
> +   }
> +
> +   return DRM_FORMAT_MOD_INVALID;
> +}
> --
> 2.13.0
>
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Re: [Mesa-dev] [PATCH] spirv: add DO NOT EDIT warning on generated spirv_info.c

[Kenneth Graunke]

On Monday, November 13, 2017 1:30:10 PM PST Alejandro Piñeiro wrote:
> 
> On 13/11/17 20:04, Kenneth Graunke wrote:
> > On Monday, November 13, 2017 2:16:59 AM PST Alejandro Piñeiro wrote:
> >> ---
> >>  src/compiler/spirv/spirv_info_c.py | 5 -
> >>  1 file changed, 4 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/src/compiler/spirv/spirv_info_c.py 
> >> b/src/compiler/spirv/spirv_info_c.py
> >> index c5e11dfc837..11235cfa3e4 100644
> >> --- a/src/compiler/spirv/spirv_info_c.py
> >> +++ b/src/compiler/spirv/spirv_info_c.py
> >> @@ -51,7 +51,10 @@ def parse_args():
> >>  p.add_argument("out")
> >>  return p.parse_args()
> >>  
> >> -TEMPLATE  = Template(COPYRIGHT + """\
> >> +TEMPLATE  = Template("""\
> >> +/* DO NOT EDIT - This file generated automatically by spirv_info_c.py 
> >> script */
> > "is generated automatically"
> >
> > Reviewed-by: Kenneth Graunke 
> 
> Ups, I already pushed the original version with Eric Rb. Should I push a
> typo fix commit?

Feel free, or not, it's not a big deal.

--Ken


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Re: [Mesa-dev] [PATCH 09/11] intel/tools/error: Decode shaders while decoding batch commands.

[Kenneth Graunke]

On Sunday, November 12, 2017 3:57:56 AM PST Lionel Landwerlin wrote:
> On 12/11/17 08:35, Kenneth Graunke wrote:
> > This makes aubinator_error_decode's shader dumping work like aubinator.
> > Instead of printing them after the fact, it prints them right inside the
> > 3DSTATE_VS/HS/DS/GS/PS packet that references them.  This saves you the
> > effort of cross-referencing things and jumping back and forth.
> >
> > It also reduces a bunch of book-keeping, and eliminates the limitation
> > that we could only handle 4096 programs.  That code was also broken and
> > failed to print any shaders if there were under 4096 programs.
> > ---
> >   src/intel/tools/aubinator_error_decode.c | 134 
> > +++
> >   1 file changed, 49 insertions(+), 85 deletions(-)
> >
> > diff --git a/src/intel/tools/aubinator_error_decode.c 
> > b/src/intel/tools/aubinator_error_decode.c
> > index cea68523ae2..96b4989936e 100644
> > --- a/src/intel/tools/aubinator_error_decode.c
> > +++ b/src/intel/tools/aubinator_error_decode.c
> > @@ -221,35 +221,28 @@ struct section {
> >   #define MAX_SECTIONS 30
> >   static struct section sections[MAX_SECTIONS];
> >   
> > -struct program {
> > -   const char *type;
> > -   const char *command;
> > -   uint64_t command_offset;
> > -   uint64_t instruction_base_address;
> > -   uint64_t ksp;
> > -};
> > -
> > -#define MAX_NUM_PROGRAMS 4096
> > -static struct program programs[MAX_NUM_PROGRAMS];
> > -static int idx_program = 0, num_programs = 0;
> > -
> > -static int next_program(void)
> > +static void
> > +disassemble_program(struct gen_disasm *disasm, const char *type,
> > +const struct section *instruction_section,
> > +uint64_t ksp)
> >   {
> > -   int ret = idx_program;
> > -   idx_program = (idx_program + 1) % MAX_NUM_PROGRAMS;
> > -   num_programs = MIN(num_programs + 1, MAX_NUM_PROGRAMS);
> > -   return ret;
> > +   if (!instruction_section)
> > +  return;
> > +
> > +   printf("\nReferenced %s:\n", type);
> > +   gen_disasm_disassemble(disasm, instruction_section->data, ksp, stdout);
> >   }
> >   
> >   static void
> > -decode(struct gen_spec *spec, const struct section *section)
> > +decode(struct gen_spec *spec, struct gen_disasm *disasm,
> > +   const struct section *section)
> >   {
> >  uint64_t gtt_offset = section->gtt_offset;
> >  uint32_t *data = section->data;
> >  uint32_t *p, *end = (data + section->count);
> >  int length;
> >  struct gen_group *inst;
> > -   uint64_t current_instruction_base_address = 0;
> > +   const struct section *current_instruction_buffer = NULL;
> >   
> >  for (p = data; p < end; p += length) {
> > const char *color = option_full_decode ? BLUE_HEADER : NORMAL,
> > @@ -284,7 +277,13 @@ decode(struct gen_spec *spec, const struct section 
> > *section)
> >   
> >while (gen_field_iterator_next()) {
> >   if (strcmp(iter.name, "Instruction Base Address") == 0) {
> > -   current_instruction_base_address = strtol(iter.value, NULL, 
> > 16);
> > +   uint64_t instr_base_address = strtol(iter.value, NULL, 16);
> > +   current_instruction_buffer = NULL;
> > +   for (int s = 0; s < MAX_SECTIONS; s++) {
> > +  if (sections[s].gtt_offset == instr_base_address) {
> 
> Is it a guarantee that the instruction buffer is going to be given in 
> its own section?

The section corresponds to a buffer marked with EXEC_OBJECT_CAPTURE, so
assuming the driver has programmed STATE_BASE_ADDRESS to the start of a
buffer, this will be true.  Otherwise, we'll get no assembly or state
dumping.

That seems like the obvious thing for a driver to do, but I suppose they
could also point it the middle of a buffer somewhere.  Mesa and SNA both
point to the start of a buffer.

I can write a follow-up patch to allow that, if you want...

> Or do we need to check bounds ?
> 
> if (instr_base_address >= sections[s].gtt_offset && inst_base_address <= 
> sections[s].gtt_offset + sections[s].count * 4)
> 
> Otherwise it looks fine to me :
> 
> Reviewed-by: Lionel Landwerlin 


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Re: [Mesa-dev] [PATCH] threads: fix MinGW build breakage

[Rob Herring]

On Fri, Nov 10, 2017 at 12:39 PM, Jon Turney
 wrote:
> On 10/11/2017 15:42, Nicolai Hähnle wrote:
>>
>> On 10.11.2017 14:00, Jon Turney wrote:
>>>
>>> On 09/11/2017 21:41, Nicolai Hähnle wrote:

 Sorry for the mess.
>>>
>>>
>>> I'm going to suggest that the fallback declaration of timespec_get() also
>>> needs to be provided for POSIX systems which don't have it.
>>>
>>> Not noticed previously as it (or xtime_get()) doesn't seem to have had
>>> any users, prior to this series.
>>>
>>> Patch attached.
>>
>>
>> Do you have a system where this is actually needed? Currently
>> HAVE_TIMESPEC_GET is only defined in threads_win32.h, so some more detection
>> logic somewhere would be required if this actually turns out to be an issue.
>
>
> Hmm.. yes, I'd assumed that HAVE_TIMESPEC_GET was the result of an autoconf
> check, but it isn't.
>
> Cygwin doesn't (currently) have timespec_get().
>
> I'm thinking the correct solution here is actually to unconditionally
> declare timespec_get(), just like all the other C11 thread functions (and as
> the unused xtime_get() was, prior to
> f1a364878431c8c5f4fd38b40b9766449e49f552)?
>
> Revised patch attached.

That should fix Android builds.

Acked-by: Rob Herring 

Rob
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Re: [Mesa-dev] [PATCH 1/2] egl/haiku: Correct invalid void* conversion in calloc

[kallisti5]

On 2017-11-13 09:41, Brian Paul wrote:

On 11/12/2017 02:53 PM, Alexander von Gluck IV wrote:

---
  src/egl/drivers/haiku/egl_haiku.cpp | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/haiku/egl_haiku.cpp 
b/src/egl/drivers/haiku/egl_haiku.cpp

index 237cebf056..287760661e 100644
--- a/src/egl/drivers/haiku/egl_haiku.cpp
+++ b/src/egl/drivers/haiku/egl_haiku.cpp
@@ -313,7 +313,8 @@ _eglBuiltInDriver(void)
  {
CALLED();

-   _EGLDriver* driver = calloc(1, sizeof(*driver));
+   _EGLDriver* driver;
+   driver = (_EGLDriver*) calloc(1, sizeof(*driver));
if (!driver) {
_eglError(EGL_BAD_ALLOC, "_eglBuiltInDriverHaiku");
return NULL;



For both, Reviewed-by: Brian Paul 

Do you need me to push these for you?


Nah, I have access.

Thanks!

 -- Alex
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Re: [Mesa-dev] [RFC v5 11/19] vulkan/wsi: Add multiple planes to wsi_image_base

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 2:02 PM, Louis-Francis Ratté-Boulianne <
l...@collabora.com> wrote:

> From: Daniel Stone 
>
> Not currently used.
>
> Signed-off-by: Daniel Stone 
> ---
>  src/amd/vulkan/radv_wsi.c   | 13 +++--
>  src/intel/vulkan/anv_wsi.c  |  9 +
>  src/vulkan/wsi/wsi_common.h |  9 +
>  src/vulkan/wsi/wsi_common_wayland.c | 11 +++
>  src/vulkan/wsi/wsi_common_x11.c | 12 
>  5 files changed, 32 insertions(+), 22 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
> index b24cf28d42..b535dc22f4 100644
> --- a/src/amd/vulkan/radv_wsi.c
> +++ b/src/amd/vulkan/radv_wsi.c
> @@ -213,22 +213,23 @@ radv_wsi_image_create(VkDevice device_h,
> RADV_FROM_HANDLE(radv_device_memory, memory, memory_h);
> if (!radv_get_memory_fd(device, memory, ))
> goto fail_alloc_memory;
> -   wsi_image->fd = fd;
> +   wsi_image->fds[0] = fd;
> } else {
> -   wsi_image->fd = -1;
> +   wsi_image->fds[0] = -1;
> }
>
> surface = >surface;
>
> wsi_image->image = image_h;
> wsi_image->memory = memory_h;
> -   wsi_image->size = image->size;
> -   wsi_image->offset = image->offset;
> +   wsi_image->num_planes = 1;
> +   wsi_image->sizes[0] = image->size;
> +   wsi_image->offsets[0] = image->offset;
> if (device->physical_device->rad_info.chip_class >= GFX9)
> -   wsi_image->row_pitch =
> +   wsi_image->row_pitches[0] =
> surface->u.gfx9.surf_pitch * surface->bpe;
> else
> -   wsi_image->row_pitch =
> +   wsi_image->row_pitches[0] =
> surface->u.legacy.level[0].nblk_x * surface->bpe;
>
> return VK_SUCCESS;
> diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
> index 916c62cad9..ae40f1f2f4 100644
> --- a/src/intel/vulkan/anv_wsi.c
> +++ b/src/intel/vulkan/anv_wsi.c
> @@ -266,10 +266,11 @@ anv_wsi_image_create(VkDevice device_h,
>
> wsi_image->image = image_h;
> wsi_image->memory = memory_h;
> -   wsi_image->fd = fd;
> -   wsi_image->size = image->size;
> -   wsi_image->offset = 0;
> -   wsi_image->row_pitch = surface->isl.row_pitch;
> +   wsi_image->num_planes = 1;
> +   wsi_image->fds[0] = fd;
> +   wsi_image->sizes[0] = image->size;
> +   wsi_image->offsets[0] = 0;
> +   wsi_image->row_pitches[0] = surface->isl.row_pitch;
> return VK_SUCCESS;
>  fail_alloc_memory:
> anv_FreeMemory(device_h, memory_h, pAllocator);
> diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
> index 1103703b0e..b6c5a438b1 100644
> --- a/src/vulkan/wsi/wsi_common.h
> +++ b/src/vulkan/wsi/wsi_common.h
> @@ -33,10 +33,11 @@
>  struct wsi_image_base {
> VkImage image;
> VkDeviceMemory memory;
>

If any of the FDs ever point to different BOs, this will need to be
per-plane as well.


> -   uint32_t size;
> -   uint32_t offset;
> -   uint32_t row_pitch;
> -   int fd;
> +   int num_planes;
> +   uint32_t sizes[4];
> +   uint32_t offsets[4];
> +   uint32_t row_pitches[4];
> +   int fds[4];
>

Would it be better to have an array of structs rather than SOA?


>  };
>
>  struct wsi_device;
> diff --git a/src/vulkan/wsi/wsi_common_wayland.c
> b/src/vulkan/wsi/wsi_common_wayland.c
> index 36cc4d0821..a76e29d26e 100644
> --- a/src/vulkan/wsi/wsi_common_wayland.c
> +++ b/src/vulkan/wsi/wsi_common_wayland.c
> @@ -736,15 +736,18 @@ wsi_wl_image_init(struct wsi_wl_swapchain *chain,
> if (result != VK_SUCCESS)
>return result;
>
> +   /* Without passing modifiers, we can't have multi-plane RGB images. */
> +   assert(image->base.num_planes == 1);
> +
> image->buffer = wl_drm_create_prime_buffer(chain->drm_wrapper,
> -  image->base.fd, /* name */
> +  image->base.fds[0], /* name
> */
>chain->extent.width,
>chain->extent.height,
>chain->drm_format,
> -  image->base.offset,
> -  image->base.row_pitch,
> +  image->base.offsets[0],
> +  image->base.row_pitches[0],
>0, 0, 0, 0 /* unused */);
> -   close(image->base.fd);
> +   close(image->base.fds[0]);
>
> if (!image->buffer)
>goto fail_image;
> diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_
> x11.c
> index 78fd406aa1..e48d746305 100644
> --- a/src/vulkan/wsi/wsi_common_x11.c
> +++ b/src/vulkan/wsi/wsi_common_x11.c
> @@ -988,18 +988,22 @@ 

Re: [Mesa-dev] [RFC v5 10/19] vulkan/wsi: Rename needs_linear_copy to should_export

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 2:02 PM, Louis-Francis Ratté-Boulianne <
l...@collabora.com> wrote:

> From: Daniel Stone 
>
> The only use for this boolean was to decide whether or not it should
> export a dmabuf FD. Simplify things a bit by giving that directly.
>

I'm not sure how I feel about this.  To be honest, I don't really know how
the radv prime stuff works so I don't know why we even have these
parameters in the WSI interface.  My feeling is that we probably just want
to simplify the interface somehow.


>
> Signed-off-by: Daniel Stone 
> ---
>  src/amd/vulkan/radv_wsi.c   |  6 --
>  src/intel/vulkan/anv_wsi.c  | 21 +
>  src/vulkan/wsi/wsi_common.h |  2 +-
>  src/vulkan/wsi/wsi_common_wayland.c |  2 +-
>  src/vulkan/wsi/wsi_common_x11.c |  4 ++--
>  5 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
> index 2562d38e23..b24cf28d42 100644
> --- a/src/amd/vulkan/radv_wsi.c
> +++ b/src/amd/vulkan/radv_wsi.c
> @@ -142,7 +142,7 @@ static VkResult
>  radv_wsi_image_create(VkDevice device_h,
>   const VkSwapchainCreateInfoKHR *pCreateInfo,
>   const VkAllocationCallbacks* pAllocator,
> - bool needs_linear_copy,
> + bool should_export,
>   bool linear,
>   struct wsi_image_base *wsi_image)
>  {
> @@ -209,11 +209,13 @@ radv_wsi_image_create(VkDevice device_h,
>  * return the fd for the image in the no copy mode,
>  * or the fd for the linear image if a copy is required.
>  */
> -   if (!needs_linear_copy || (needs_linear_copy && linear)) {
> +   if (should_export) {
> RADV_FROM_HANDLE(radv_device_memory, memory, memory_h);
> if (!radv_get_memory_fd(device, memory, ))
> goto fail_alloc_memory;
> wsi_image->fd = fd;
> +   } else {
> +   wsi_image->fd = -1;
> }
>
> surface = >surface;
> diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
> index d520d8e3f4..916c62cad9 100644
> --- a/src/intel/vulkan/anv_wsi.c
> +++ b/src/intel/vulkan/anv_wsi.c
> @@ -172,7 +172,7 @@ static VkResult
>  anv_wsi_image_create(VkDevice device_h,
>   const VkSwapchainCreateInfoKHR *pCreateInfo,
>   const VkAllocationCallbacks* pAllocator,
> - bool different_gpu,
> + bool should_export,
>   bool linear,
>   struct wsi_image_base *wsi_image)
>  {
> @@ -250,13 +250,18 @@ anv_wsi_image_create(VkDevice device_h,
>goto fail_alloc_memory;
> }
>
> -   int fd = anv_gem_handle_to_fd(device, memory->bo->gem_handle);
> -   if (fd == -1) {
> -  /* FINISHME: Choose a better error. */
> -  result = vk_errorf(device->instance, device,
> - VK_ERROR_OUT_OF_DEVICE_MEMORY,
> - "handle_to_fd failed: %m");
> -  goto fail_alloc_memory;
> +   int fd;
> +   if (should_export) {
> +  fd = anv_gem_handle_to_fd(device, memory->bo->gem_handle);
> +  if (fd == -1) {
> + /* FINISHME: Choose a better error. */
> + result = vk_errorf(device->instance, device,
> +VK_ERROR_OUT_OF_DEVICE_MEMORY,
> +"handle_to_fd failed: %m");
> + goto fail_alloc_memory;
> +  }
> +   } else {
> +  fd = -1;
> }
>
> wsi_image->image = image_h;
> diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
> index 2a9092479d..1103703b0e 100644
> --- a/src/vulkan/wsi/wsi_common.h
> +++ b/src/vulkan/wsi/wsi_common.h
> @@ -44,7 +44,7 @@ struct wsi_image_fns {
> VkResult (*create_wsi_image)(VkDevice device_h,
>  const VkSwapchainCreateInfoKHR
> *pCreateInfo,
>  const VkAllocationCallbacks *pAllocator,
> -bool needs_linear_copy,
> +bool should_export,
>  bool linear,
>  struct wsi_image_base *image_p);
> void (*free_wsi_image)(VkDevice device,
> diff --git a/src/vulkan/wsi/wsi_common_wayland.c
> b/src/vulkan/wsi/wsi_common_wayland.c
> index 495e7068b4..36cc4d0821 100644
> --- a/src/vulkan/wsi/wsi_common_wayland.c
> +++ b/src/vulkan/wsi/wsi_common_wayland.c
> @@ -730,7 +730,7 @@ wsi_wl_image_init(struct wsi_wl_swapchain *chain,
> result = chain->base.image_fns->create_wsi_image(vk_device,
>  pCreateInfo,
>  pAllocator,
> -false,
> +true,
>  

Re: [Mesa-dev] [PATCH 01/14] anv/cmd_buffer: Advance the address when initializing clear colors

[Jason Ekstrand]

On Mon, Nov 13, 2017 at 1:30 PM, Nanley Chery  wrote:

> On Mon, Nov 13, 2017 at 08:12:41AM -0800, Jason Ekstrand wrote:
> > Found by inspection
> >
>
> Good catch.
>
> > Cc: mesa-sta...@lists.freedesktop.org
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 9 ++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index fbb5706..2564976 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -557,12 +557,13 @@ init_fast_clear_state_entry(struct anv_cmd_buffer
> *cmd_buffer,
> > /* Other combinations of auxiliary buffers and platforms require
> specific
> >  * values in the clear value dword(s).
> >  */
> > +   struct anv_address addr =
> > +  get_fast_clear_state_address(cmd_buffer->device, image, aspect,
> level,
> > +   FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
> > unsigned i = 0;
> > for (; i < cmd_buffer->device->isl_dev.ss.clear_value_size; i += 4)
> {
> >anv_batch_emit(_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi)
> {
> > - sdi.Address =
> > -get_fast_clear_state_address(cmd_buffer->device, image,
> aspect, level,
> > - FAST_CLEAR_STATE_FIELD_CLEAR_
> COLOR);
> > + sdi.Address = addr;
>
> The loop increments the variable i by 4 with every iteration. How about
> the following instead:
> sdi.Address = addr + i;
>

I really wish we could do that but it's a struct.  I could do

sdi.Address = addr;
sdi.Address.offset += i;

--Jason


> -Nanley
>
> >
> >   if (GEN_GEN >= 9) {
> >  /* MCS buffers on SKL+ can only have 1/0 clear colors. */
> > @@ -586,6 +587,8 @@ init_fast_clear_state_entry(struct anv_cmd_buffer
> *cmd_buffer,
> >  sdi.ImmediateData = 0;
> >   }
> >}
> > +
> > +  addr += 4;
>

Aparently, I didn't compile-test this because I need a .offset here. :/


> > }
> >  }
> >
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH 10/10] spirv: Generate SPIR-V builder infrastructure

[Dylan Baker]

Quoting Ian Romanick (2017-11-10 14:32:50)
[snip]
> +
> +def can_have_extra_operands(name, enums):
> +"""Determine whether an enum can have extra operands.
> +
> +Some enums, like SpvDecoration, can have extra operands with some values.
> +Other enums, like SpvMemorySemantics, cannot.
> +"""
> +
> +if name not in enums:
> +return False
> +
> +for parameter in enums[name][1]:
> +if len(parameter[2]) > 0:

Not using len() here would be faster:
if parameter[2]:
return True

Or, if you like a more functional approach you could do something like:
return any(p[2] for p in enums[name][1])

> +return True
> +
> +return False
> +
> +def prototype_for_instruction_emit(inst, all_enums, bit_enums):
> +parameters = ["spirv_program *prog"]
> +
> +if "operands" in inst:
> +parameters = parameters + [declare_parameter(operand, all_enums, 
> bit_enums) for operand in inst["operands"]]
> +
> +return textwrap.dedent("""\
> +static inline void
> +emit_Spv{name}({parameters})""".format(name=inst["opname"],
> +   parameters=",\n
> ".join(parameters)))
> +
> +
> +def default_value(parameter, bit_enums):
> +"""Determine whether an enum has a value that is the default when the 
> enum is
> +not specified.
> +
> +Some enums are almost always marked as optional on the instructions that
> +use them.  Some of these, like SpvMemoryAccess, have a value that is
> +assumed when the value is not specificed in the instruction.
> +"""
> +
> +pass

This function appears to be unused.

> +
> +def instruction_size(instruction, enums):
> +"""Determine the size of an instruction based on its operands
> +
> +Instructions that have only operands without ? or * quantifiers are sized
> +by the number of operands.  In addition, instructions that have certain
> +BitEnum and ValueEnum parameters also have varying sizes.
> +"""
> +
> +if "operands" not in instruction:
> +# Instructions like OpNop that have no operands.  Handle these with a
> +# trivial special case.
> +return 1
> +
> +for operand in instruction["operands"]:
> +if "quantifier" in operand:
> +return 0
> +elif operand["kind"] == "LiteralString":
> +return 0
> +elif operand["kind"] in enums and enums[operand["kind"]][0]:
> +return 0
> +
> +return len(instruction["operands"]) + 1
> +
> +def optional_parameter_flag(operand, bit_enums):
> +"""Return the name of the flag for an optional parameter, None otherwise
> +
> +Optional parameters are noted in the JSON with a "?" quantifier.  For 
> some
> +types, it is possible to infer that a value does not exist by examining
> +the value.  For example, if a optional LiteralString parameter is NULL, 
> it
> +is not included.  The same applies for some BitEnum kinds such as
> +ImageOperands. For cases where the existence cannot be infered from the
> +value, a "has_foo" flag is added to the parameter list.
> +
> +This function returns either the has_foo name as a string or None.
> +"""
> +
> +if operand["kind"] == "LiteralString":
> +return None
> +
> +if operand["kind"] == "ImageOperands":
> +return None
> +
> +if operand["kind"] in bit_enums:
> +return None
> +
> +if "quantifier" not in operand or operand["quantifier"] != "?":
> +return None
> +
> +return "has_" + operand_name(operand)
> +
> +def operand_name(operand):
> +if operand["kind"] == "IdResult":
> +return "result"
> +elif operand["kind"] == "IdResultType":
> +return "result_type"
> +elif "name" in operand:
> +if "quantifier" in operand and "+" in operand["name"]:
> +return operand["kind"]
> +elif operand["name"] == "'D~ref~'":
> +return "deref"
> +else:
> +name=operand["name"].replace("'", "").replace(" ", 
> "_").replace(".", "").replace("~","_").lower()
> +return name if name not in ["default"] else "_" + name
> +else:
> +return operand["kind"]
> +
> +def list_is_same(a, b):
> +if len(a) != len(b):
> +return False
> +
> +for x in a:
> +if x not in b:
> +return False
> +
> +return True

is there a reason you canot just do `a == b`?

> +
> +def capabilities_are_same(enums):
> +for parameter in enums[1:]:
> +if not list_is_same(enums[0][1], parameter[1]):
> +return False
> +
> +return True
> +
> +def render_enable_capability(capability_list, indent="   "):
> +if len(capability_list) == 0:
> +return ""
> +
> +execution_modes = ["Kernel", "Shader", "Geometry", "Tessellation"]
> +
> +if set(capability_list) <= set(execution_modes):
> +# If all of the capabilities are execution mode capabilities, then 
> one
> +# of the 

Re: [Mesa-dev] [PATCH 09/10] spirv: Generate code to track SPIR-V capability dependencies

[Dylan Baker]

Quoting Ian Romanick (2017-11-13 13:34:15)
> On 11/13/2017 10:49 AM, Dylan Baker wrote:
> > Quoting Ian Romanick (2017-11-10 14:32:49)
> > [snip]
> > 
> >> +
> >> +def collect_data(spirv):
> >> +for x in spirv["operand_kinds"]:
> >> +if x["kind"] == "Capability":
> >> +operands = x
> > 
> > This makes me nervous. dict iteration order is not guaranteed to be 
> > repeatable
> > in python. I think you should either use sorted() [for x in 
> > sorted(spirv...)],
> > or if there's only every going to be on case where x[kind] == capability 
> > use a
> > break statement and leave a comment.
> > 
> >> +
> >> +# There are some duplicate values in some of the tables (thanks 
> >> guys!), so
> >> +# filter them out.
> >> +
> >> +# by_value is a dictionary that maps values of enumerants to tuples of
> >> +# enumerant names and capabilities.
> >> +by_value = {}
> >> +
> >> +# by_name is a dictionary that maps names of enumerants to tuples of
> >> +# values and required capabilities.
> >> +by_name = {}
> >> +
> >> +for x in operands["enumerants"]:
> >> +caps = x["capabilities"] if "capabilities" in x else []
> > 
> > caps = x.get("capabilities", [])
> 
> Yeah... there are a lot of places where I can use that.
> 
> > 
> >> +
> >> +if x["value"] not in by_value:
> >> +by_value[x["value"]] = (x["enumerant"], caps)
> >> +
> >> +by_name[x["enumerant"]] = (x["value"], caps)
> >> +
> >> +# Recall that there are some duplicate values in the table.  These
> >> +# duplicate values also appear in the "capabilities" list for some
> >> +# enumerants.  Filter out the duplicates there as well.
> >> +for capability in by_name:
> >> +cap_value, dependencies = by_name[capability]
> >> +for dependency in dependencies:
> >> +dep_value, skip = by_name[dependency]
> >> +real_dependency, skip = by_value[dep_value]
> > 
> > I think you can simplify this somewhat:
> > 
> > for capability, (_, dependencies) in by_name.iteritems():
> > for dep_value, _ in dependencies.itervalues():
> > real_dependency, _ = by_value[dep_value]
> 
> Ah! _ is the idiom I was trying to remember.
> 
> >> +
> >> +# In most cases where there is a duplicate capability, things 
> >> that
> >> +# depend on one will also depend on the others.
> >> +# StorageBuffer16BitAccess and StorageUniformBufferBlock16 
> >> have
> >> +# the same value, and StorageUniform16 depends on both.
> >> +#
> >> +# There are exceptions.  ShaderViewportIndexLayerEXT and
> >> +# ShaderViewportIndexLayerNV have the same value, but
> >> +# ShaderViewportMaskNV only depends on 
> >> ShaderViewportIndexLayerNV.
> >> +#
> >> +# That's the only case so far, so emit a warning for other 
> >> cases
> >> +# that have more than one dependency.  That way we can double
> >> +# check that they are handled correctly.
> >> +
> >> +if real_dependency != dependency:
> >> +if real_dependency not in by_name[capability][1]:
> >> +if len(by_name[capability][1]) > 1:
> >> +print("Warning!  Removed {} from {}, but no name 
> >> with the same value is in the dependency list.".format(dependency, 
> >> capability))
> >> +else:
> >> +if len(by_name[capability][1]) == 1:
> >> +print("Error!  Cannot remove {} from {} because 
> >> it is the only dependency.".format(dependency, capability))
> > 
> > I think you want to add file=sys.stderr to the print command. (You might 
> > need to
> > import sys, I snipped that part of the patch already...)
> > 
> >> +exit(1)
> >> +
> >> +by_name[capability][1].remove(dependency)
> >> +
> >> +# The table generated from this data and the C code that uses it
> >> +# assumes that each capability has a single dependency.  That is
> >> +# currently the case, but it may change in the future.
> >> +if len(by_name[capability][1]) > 1:
> >> +print("Error!  Too many dependencies left for {}. 
> >> {}".format(capability, by_name[capability][1]))
> >> +exit(1)
> >> +
> >> +for cap_value in by_value:
> >> +name, skip = by_value[cap_value]
> >> +by_value[cap_value] = (name, by_name[name][1])
> >> +
> >> +return (by_name, by_value)
> >> +
> >> +TEMPLATE_H = Template(COPYRIGHT + """\
> >> +#ifndef SPIRV_CAPABILITIES_H
> >> +#define SPIRV_CAPABILITIES_H
> >> +
> >> +#include 
> >> +#include "spirv.h"
> >> +#include "util/bitset.h"
> >> +#ifndef ARRAY_SIZE
> >> +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
> >> +#endif
> >> +
> >> +#define NO_DEPENDENCY ((${"uint16_t" if len(all_values) > 256 else 
> >> "uint8_t"}) ~0)
> >> +
> >> +class 

Re: [Mesa-dev] [PATCH 11/11] intel/tools/error: Decode compute shaders.

[Kenneth Graunke]

On Sunday, November 12, 2017 4:06:06 AM PST Lionel Landwerlin wrote:
> On 12/11/17 08:35, Kenneth Graunke wrote:
> > This is a bit more annoying than your average shader - we need to look
> > at MEDIA_INTERFACE_DESCRIPTOR_LOAD in the batch buffer, then hop over
> > to the dynamic state buffer to read the INTERFACE_DESCRIPTOR_DATA, then
> > hop over to the instruction buffer to decode the program.
> >
> > Now that we store all the buffers before decoding, we can actually do
> > this fairly easily.
> > ---
> >   src/intel/tools/aubinator_error_decode.c | 49 
> > +++-
> >   1 file changed, 42 insertions(+), 7 deletions(-)
> >
> > diff --git a/src/intel/tools/aubinator_error_decode.c 
> > b/src/intel/tools/aubinator_error_decode.c
> > index 09ca7c3a4ab..81418d69c9a 100644
> > --- a/src/intel/tools/aubinator_error_decode.c
> > +++ b/src/intel/tools/aubinator_error_decode.c
> > @@ -233,6 +233,17 @@ disassemble_program(struct gen_disasm *disasm, const 
> > char *type,
> >  gen_disasm_disassemble(disasm, instruction_section->data, ksp, stdout);
> >   }
> >   
> > +static const struct section *
> > +find_section(const char *str_base_address)
> > +{
> > +   uint64_t base_address = strtol(str_base_address, NULL, 16);
> > +   for (int s = 0; s < MAX_SECTIONS; s++) {
> > +  if (sections[s].gtt_offset == base_address)
> > + return [s];
> > +   }
> > +   return NULL;
> > +}
> > +
> >   static void
> >   decode(struct gen_spec *spec, struct gen_disasm *disasm,
> >  const struct section *section)
> > @@ -243,6 +254,7 @@ decode(struct gen_spec *spec, struct gen_disasm *disasm,
> >  int length;
> >  struct gen_group *inst;
> >  const struct section *current_instruction_buffer = NULL;
> > +   const struct section *current_dynamic_state_buffer = NULL;
> >   
> >  for (p = data; p < end; p += length) {
> > const char *color = option_full_decode ? BLUE_HEADER : NORMAL,
> > @@ -277,13 +289,9 @@ decode(struct gen_spec *spec, struct gen_disasm 
> > *disasm,
> >   
> >do {
> >   if (strcmp(iter.name, "Instruction Base Address") == 0) {
> > -   uint64_t instr_base_address = strtol(iter.value, NULL, 16);
> > -   current_instruction_buffer = NULL;
> > -   for (int s = 0; s < MAX_SECTIONS; s++) {
> > -  if (sections[s].gtt_offset == instr_base_address) {
> > - current_instruction_buffer = [s];
> > -  }
> > -   }
> > +   current_instruction_buffer = find_section(iter.value);
> > +} else if (strcmp(iter.name, "Dynamic State Base Address") == 
> > 0) {
> > +   current_dynamic_state_buffer = find_section(iter.value);
> >   }
> >} while (gen_field_iterator_next());
> > } else if (strcmp(inst->name,   "WM_STATE") == 0 ||
> > @@ -380,6 +388,33 @@ decode(struct gen_spec *spec, struct gen_disasm 
> > *disasm,
> >   disassemble_program(disasm, type, current_instruction_buffer, 
> > ksp);
> >   printf("\n");
> >}
> > +  } else if (strcmp(inst->name, "MEDIA_INTERFACE_DESCRIPTOR_LOAD") == 
> > 0) {
> > + struct gen_field_iterator iter;
> > + gen_field_iterator_init(, inst, p, false);
> > + uint64_t interface_offset = 0;
> > + while (gen_field_iterator_next()) {
> 
> Don't want a do {} while() here too?

Oops, yes we do.  I'd written this, discovered the do-while problem,
rebased, wrote a separate patch to fix the earlier problems...but didn't
fix this one because it didn't exist yet...then forgot.

Fixed locally.  Look okay other than that?


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Re: [Mesa-dev] [PATCH 03/10] spirv: Import the latest 1.0.12 header and JSON from Khronos

[Ian Romanick]

On 11/12/2017 02:53 PM, Eric Engestrom wrote:
> On Friday, 2017-11-10 14:32:43 -0800, Ian Romanick wrote:
>> From: Ian Romanick 
>>
>> Signed-off-by: Ian Romanick 
>> ---
>>  src/compiler/spirv/spirv.core.grammar.json | 417 
>> -
>>  src/compiler/spirv/spirv.h |  56 ++--
>>  2 files changed, 201 insertions(+), 272 deletions(-)
>>
>> diff --git a/src/compiler/spirv/spirv.core.grammar.json 
>> b/src/compiler/spirv/spirv.core.grammar.json
>> index e2950dd..f05be1c 100644
>> --- a/src/compiler/spirv/spirv.core.grammar.json
>> +++ b/src/compiler/spirv/spirv.core.grammar.json
>> @@ -26,8 +26,8 @@
>>],
>>"magic_number" : "0x07230203",
>>"major_version" : 1,
>> -  "minor_version" : 2,
>> -  "revision" : 1,
>> +  "minor_version" : 0,
>> +  "revision" : 12,
> 
> Aren't you going backwards here?
> 1.2.1 -> 1.0.12
> 
> Seems to me like the latest is 1.2.2, is that what you meant to pull?
> https://github.com/KhronosGroup/SPIRV-Headers/tree/master/include/spirv/1.2/

Yes... it looks like this file changed from under me, and I didn't
notice while rebasing.  I'll pull the newest 1.2, and hopefully that
won't cause problems for my scripts.

>>"instructions" : [
>>  {
>>"opname" : "OpNop",
>> @@ -2410,7 +2410,7 @@
>>  { "kind" : "IdResult" },
>>  { "kind" : "IdScope","name" : "'Execution'" },
>>  { "kind" : "GroupOperation", "name" : "'Operation'" },
>> -{ "kind" : "IdRef",  "name" : "X" }
>> +{ "kind" : "IdRef",  "name" : "'X'" }
>>],
>>"capabilities" : [ "Groups" ]
>>  },
>> @@ -2434,7 +2434,7 @@
>>  { "kind" : "IdResult" },
>>  { "kind" : "IdScope","name" : "'Execution'" },
>>  { "kind" : "GroupOperation", "name" : "'Operation'" },
>> -{ "kind" : "IdRef",  "name" : "X" }
>> +{ "kind" : "IdRef",  "name" : "'X'" }
>>],
>>"capabilities" : [ "Groups" ]
>>  },
>> @@ -2446,7 +2446,7 @@
>>  { "kind" : "IdResult" },
>>  { "kind" : "IdScope","name" : "'Execution'" },
>>  { "kind" : "GroupOperation", "name" : "'Operation'" },
>> -{ "kind" : "IdRef",  "name" : "X" }
>> +{ "kind" : "IdRef",  "name" : "'X'" }
>>],
>>"capabilities" : [ "Groups" ]
>>  },
>> @@ -2458,7 +2458,7 @@
>>  { "kind" : "IdResult" },
>>  { "kind" : "IdScope","name" : "'Execution'" },
>>  { "kind" : "GroupOperation", "name" : "'Operation'" },
>> -{ "kind" : "IdRef",  "name" : "X" }
>> +{ "kind" : "IdRef",  "name" : "'X'" }
>>],
>>"capabilities" : [ "Groups" ]
>>  },
>> @@ -2470,7 +2470,7 @@
>>  { "kind" : "IdResult" },
>>  { "kind" : "IdScope","name" : "'Execution'" },
>>  { "kind" : "GroupOperation", "name" : "'Operation'" },
>> -{ "kind" : "IdRef",  "name" : "X" }
>> +{ "kind" : "IdRef",  "name" : "'X'" }
>>],
>>"capabilities" : [ "Groups" ]
>>  },
>> @@ -3013,124 +3013,6 @@
>>"capabilities" : [ "SparseResidency" ]
>>  },
>>  {
>> -  "opname" : "OpSizeOf",
>> -  "opcode" : 321,
>> -  "operands" : [
>> -{ "kind" : "IdResultType" },
>> -{ "kind" : "IdResult" },
>> -{ "kind" : "IdRef","name" : "'Pointer'" }
>> -  ],
>> -  "capabilities" : [ "Addresses" ]
>> -},
>> -{
>> -  "opname" : "OpTypePipeStorage",
>> -  "opcode" : 322,
>> -  "operands" : [
>> -{ "kind" : "IdResult" }
>> -  ],
>> -  "capabilities" : [ "PipeStorage" ]
>> -},
>> -{
>> -  "opname" : "OpConstantPipeStorage",
>> -  "opcode" : 323,
>> -  "operands" : [
>> -{ "kind" : "IdResultType" },
>> -{ "kind" : "IdResult" },
>> -{ "kind" : "LiteralInteger", "name" : "'Packet Size'" },
>> -{ "kind" : "LiteralInteger", "name" : "'Packet Alignment'" },
>> -{ "kind" : "LiteralInteger", "name" : "'Capacity'" }
>> -  ],
>> -  "capabilities" : [ "PipeStorage" ]
>> -},
>> -{
>> -  "opname" : "OpCreatePipeFromPipeStorage",
>> -  "opcode" : 324,
>> -  "operands" : [
>> -{ "kind" : "IdResultType" },
>> -{ "kind" : "IdResult" },
>> -{ "kind" : "IdRef","name" : "'Pipe Storage'" }
>> -  ],
>> -  "capabilities" : [ "PipeStorage" ]
>> -},
>> -{
>> -  "opname" : "OpGetKernelLocalSizeForSubgroupCount",
>> -  "opcode" : 325,
>> -  "operands" : [
>> -{ "kind" : "IdResultType" },
>> -{ "kind" : "IdResult" },
>> -{ "kind" : "IdRef","name" : "'Subgroup Count'" },
>> -{ "kind" : "IdRef","name" : "'Invoke'" },
>> -{ "kind" : "IdRef","name" : "'Param'" },
>> -{ "kind" : "IdRef",

Re: [Mesa-dev] [PATCH 1/3] meson: don't use build_by_default for specific gallium drivers

[Dylan Baker]

Quoting Eric Anholt (2017-11-13 13:07:31)
> Dylan Baker  writes:
> 
> > Using build_by_default : false is convenient for dependencies that can
> > be pulled in by various diverse components of the build system, the
> > gallium hardware/software drivers and state trackers do not fit that
> > description. Instead, these should be guarded using the variable that tracks
> > whether that driver should be enabled.
> >
> > This leaves a few helper libraries: trace, rbug, etc, and the generic
> > winsys bits as `build_by_default : false` because there are a large
> > number of gallium components that pull them in.
> >
> > v2: - remove build_by_default from winsys convenience libs as well.
> >
> > Signed-off-by: Dylan Baker 
> > Tested-by: Lionel Landwerlin  (v1)
> > ---
> >  src/gallium/drivers/freedreno/meson.build|  1 -
> >  src/gallium/drivers/llvmpipe/meson.build |  1 -
> >  src/gallium/drivers/nouveau/meson.build  |  1 -
> >  src/gallium/drivers/radeon/meson.build   |  1 -
> >  src/gallium/drivers/radeonsi/meson.build |  1 -
> >  src/gallium/drivers/softpipe/meson.build |  1 -
> >  src/gallium/drivers/vc5/meson.build  |  1 -
> >  src/gallium/meson.build  | 47 
> > +++-
> >  src/gallium/state_trackers/dri/meson.build   |  1 -
> >  src/gallium/winsys/amdgpu/drm/meson.build|  1 -
> >  src/gallium/winsys/freedreno/drm/meson.build |  1 -
> >  src/gallium/winsys/nouveau/drm/meson.build   |  1 -
> >  src/gallium/winsys/radeon/drm/meson.build|  1 -
> >  13 files changed, 25 insertions(+), 34 deletions(-)
> >
> > diff --git a/src/gallium/drivers/freedreno/meson.build 
> > b/src/gallium/drivers/freedreno/meson.build
> > index fe1a902e9e5..d2b901334d0 100644
> > --- a/src/gallium/drivers/freedreno/meson.build
> > +++ b/src/gallium/drivers/freedreno/meson.build
> > @@ -207,7 +207,6 @@ libfreedreno = static_library(
> >c_args : [c_vis_args],
> >cpp_args : [cpp_vis_args],
> >dependencies : [dep_libdrm, dep_libdrm_freedreno],
> > -  build_by_default : false,
> >  )
> >  
> >  ir3_compiler = executable(
> > diff --git a/src/gallium/drivers/llvmpipe/meson.build 
> > b/src/gallium/drivers/llvmpipe/meson.build
> > index ca1d2aa797b..9d0edb0ac33 100644
> > --- a/src/gallium/drivers/llvmpipe/meson.build
> > +++ b/src/gallium/drivers/llvmpipe/meson.build
> > @@ -98,7 +98,6 @@ libllvmpipe = static_library(
> >cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
> >include_directories : [inc_gallium, inc_gallium_aux, inc_include, 
> > inc_src],
> >dependencies : dep_llvm,
> > -  build_by_default : false,
> >  )
> >  
> >  if with_tests and with_gallium_softpipe and with_llvm
> > diff --git a/src/gallium/drivers/nouveau/meson.build 
> > b/src/gallium/drivers/nouveau/meson.build
> > index 2bc6142879e..59fecfc5255 100644
> > --- a/src/gallium/drivers/nouveau/meson.build
> > +++ b/src/gallium/drivers/nouveau/meson.build
> > @@ -211,7 +211,6 @@ libnouveau = static_library(
> >c_args : [c_vis_args],
> >cpp_args : [cpp_vis_args],
> >dependencies : [dep_libdrm, dep_libdrm_nouveau],
> > -  build_by_default : false,
> >  )
> >  
> >  nouveau_compiler = executable(
> > diff --git a/src/gallium/drivers/radeon/meson.build 
> > b/src/gallium/drivers/radeon/meson.build
> > index b4d2832d016..f378b12e8e8 100644
> > --- a/src/gallium/drivers/radeon/meson.build
> > +++ b/src/gallium/drivers/radeon/meson.build
> > @@ -51,5 +51,4 @@ libradeon = static_library(
> >include_directories : [
> >  inc_include, inc_src, inc_gallium, inc_gallium_aux, 
> > inc_gallium_drivers,
> >],
> > -  build_by_default : false,
> >  )
> > diff --git a/src/gallium/drivers/radeonsi/meson.build 
> > b/src/gallium/drivers/radeonsi/meson.build
> > index 4392184dbb6..974004db67f 100644
> > --- a/src/gallium/drivers/radeonsi/meson.build
> > +++ b/src/gallium/drivers/radeonsi/meson.build
> > @@ -75,5 +75,4 @@ libradeonsi = static_library(
> >c_args : [c_vis_args],
> >cpp_args : [cpp_vis_args],
> >dependencies : dep_llvm,
> > -  build_by_default : false,
> >  )
> > diff --git a/src/gallium/drivers/softpipe/meson.build 
> > b/src/gallium/drivers/softpipe/meson.build
> > index 0cef15152e2..df23533c72c 100644
> > --- a/src/gallium/drivers/softpipe/meson.build
> > +++ b/src/gallium/drivers/softpipe/meson.build
> > @@ -81,5 +81,4 @@ libsoftpipe = static_library(
> >files_softpipe,
> >include_directories : [inc_gallium_aux, inc_gallium, inc_include, 
> > inc_src],
> >c_args : [c_vis_args, c_msvc_compat_args],
> > -  build_by_default : false,
> >  )
> > diff --git a/src/gallium/drivers/vc5/meson.build 
> > b/src/gallium/drivers/vc5/meson.build
> > index d066366fcc7..61059a15560 100644
> > --- a/src/gallium/drivers/vc5/meson.build
> > +++ b/src/gallium/drivers/vc5/meson.build
> > @@ -61,5 +61,4 @@ libvc5 = static_library(
> >c_args : [c_vis_args, 

Re: [Mesa-dev] [PATCH 09/10] spirv: Generate code to track SPIR-V capability dependencies

[Ian Romanick]

On 11/13/2017 10:49 AM, Dylan Baker wrote:
> Quoting Ian Romanick (2017-11-10 14:32:49)
> [snip]
> 
>> +
>> +def collect_data(spirv):
>> +for x in spirv["operand_kinds"]:
>> +if x["kind"] == "Capability":
>> +operands = x
> 
> This makes me nervous. dict iteration order is not guaranteed to be repeatable
> in python. I think you should either use sorted() [for x in sorted(spirv...)],
> or if there's only every going to be on case where x[kind] == capability use a
> break statement and leave a comment.
> 
>> +
>> +# There are some duplicate values in some of the tables (thanks guys!), 
>> so
>> +# filter them out.
>> +
>> +# by_value is a dictionary that maps values of enumerants to tuples of
>> +# enumerant names and capabilities.
>> +by_value = {}
>> +
>> +# by_name is a dictionary that maps names of enumerants to tuples of
>> +# values and required capabilities.
>> +by_name = {}
>> +
>> +for x in operands["enumerants"]:
>> +caps = x["capabilities"] if "capabilities" in x else []
> 
> caps = x.get("capabilities", [])

Yeah... there are a lot of places where I can use that.

> 
>> +
>> +if x["value"] not in by_value:
>> +by_value[x["value"]] = (x["enumerant"], caps)
>> +
>> +by_name[x["enumerant"]] = (x["value"], caps)
>> +
>> +# Recall that there are some duplicate values in the table.  These
>> +# duplicate values also appear in the "capabilities" list for some
>> +# enumerants.  Filter out the duplicates there as well.
>> +for capability in by_name:
>> +cap_value, dependencies = by_name[capability]
>> +for dependency in dependencies:
>> +dep_value, skip = by_name[dependency]
>> +real_dependency, skip = by_value[dep_value]
> 
> I think you can simplify this somewhat:
> 
> for capability, (_, dependencies) in by_name.iteritems():
> for dep_value, _ in dependencies.itervalues():
> real_dependency, _ = by_value[dep_value]

Ah! _ is the idiom I was trying to remember.

>> +
>> +# In most cases where there is a duplicate capability, things 
>> that
>> +# depend on one will also depend on the others.
>> +# StorageBuffer16BitAccess and StorageUniformBufferBlock16 have
>> +# the same value, and StorageUniform16 depends on both.
>> +#
>> +# There are exceptions.  ShaderViewportIndexLayerEXT and
>> +# ShaderViewportIndexLayerNV have the same value, but
>> +# ShaderViewportMaskNV only depends on 
>> ShaderViewportIndexLayerNV.
>> +#
>> +# That's the only case so far, so emit a warning for other cases
>> +# that have more than one dependency.  That way we can double
>> +# check that they are handled correctly.
>> +
>> +if real_dependency != dependency:
>> +if real_dependency not in by_name[capability][1]:
>> +if len(by_name[capability][1]) > 1:
>> +print("Warning!  Removed {} from {}, but no name 
>> with the same value is in the dependency list.".format(dependency, 
>> capability))
>> +else:
>> +if len(by_name[capability][1]) == 1:
>> +print("Error!  Cannot remove {} from {} because it 
>> is the only dependency.".format(dependency, capability))
> 
> I think you want to add file=sys.stderr to the print command. (You might need 
> to
> import sys, I snipped that part of the patch already...)
> 
>> +exit(1)
>> +
>> +by_name[capability][1].remove(dependency)
>> +
>> +# The table generated from this data and the C code that uses it
>> +# assumes that each capability has a single dependency.  That is
>> +# currently the case, but it may change in the future.
>> +if len(by_name[capability][1]) > 1:
>> +print("Error!  Too many dependencies left for {}. 
>> {}".format(capability, by_name[capability][1]))
>> +exit(1)
>> +
>> +for cap_value in by_value:
>> +name, skip = by_value[cap_value]
>> +by_value[cap_value] = (name, by_name[name][1])
>> +
>> +return (by_name, by_value)
>> +
>> +TEMPLATE_H = Template(COPYRIGHT + """\
>> +#ifndef SPIRV_CAPABILITIES_H
>> +#define SPIRV_CAPABILITIES_H
>> +
>> +#include 
>> +#include "spirv.h"
>> +#include "util/bitset.h"
>> +#ifndef ARRAY_SIZE
>> +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
>> +#endif
>> +
>> +#define NO_DEPENDENCY ((${"uint16_t" if len(all_values) > 256 else 
>> "uint8_t"}) ~0)
>> +
>> +class spirv_capability_set;
>> +
>> +/**
>> + * Iterator for the enabled capabilities in a spirv_capability_set
>> + *
>> + * Roughly, this is a wrapper for the bitset iterator functions.  
>> Dereferencing
>> + * the iterator results in the \c SpvCapability where as the bitset iterator
>> + * functions provide the index in the 

Re: [Mesa-dev] [PATCH 01/14] anv/cmd_buffer: Advance the address when initializing clear colors

[Nanley Chery]

On Mon, Nov 13, 2017 at 08:12:41AM -0800, Jason Ekstrand wrote:
> Found by inspection
> 

Good catch.

> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index fbb5706..2564976 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -557,12 +557,13 @@ init_fast_clear_state_entry(struct anv_cmd_buffer 
> *cmd_buffer,
> /* Other combinations of auxiliary buffers and platforms require specific
>  * values in the clear value dword(s).
>  */
> +   struct anv_address addr =
> +  get_fast_clear_state_address(cmd_buffer->device, image, aspect, level,
> +   FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
> unsigned i = 0;
> for (; i < cmd_buffer->device->isl_dev.ss.clear_value_size; i += 4) {
>anv_batch_emit(_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
> - sdi.Address =
> -get_fast_clear_state_address(cmd_buffer->device, image, aspect, 
> level,
> - FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
> + sdi.Address = addr;

The loop increments the variable i by 4 with every iteration. How about
the following instead:
sdi.Address = addr + i;

-Nanley

>  
>   if (GEN_GEN >= 9) {
>  /* MCS buffers on SKL+ can only have 1/0 clear colors. */
> @@ -586,6 +587,8 @@ init_fast_clear_state_entry(struct anv_cmd_buffer 
> *cmd_buffer,
>  sdi.ImmediateData = 0;
>   }
>}
> +
> +  addr += 4;
> }
>  }
>  
> -- 
> 2.5.0.400.gff86faf
> 
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Re: [Mesa-dev] [PATCH] spirv: add DO NOT EDIT warning on generated spirv_info.c

[Alejandro Piñeiro]

On 13/11/17 20:04, Kenneth Graunke wrote:
> On Monday, November 13, 2017 2:16:59 AM PST Alejandro Piñeiro wrote:
>> ---
>>  src/compiler/spirv/spirv_info_c.py | 5 -
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/compiler/spirv/spirv_info_c.py 
>> b/src/compiler/spirv/spirv_info_c.py
>> index c5e11dfc837..11235cfa3e4 100644
>> --- a/src/compiler/spirv/spirv_info_c.py
>> +++ b/src/compiler/spirv/spirv_info_c.py
>> @@ -51,7 +51,10 @@ def parse_args():
>>  p.add_argument("out")
>>  return p.parse_args()
>>  
>> -TEMPLATE  = Template(COPYRIGHT + """\
>> +TEMPLATE  = Template("""\
>> +/* DO NOT EDIT - This file generated automatically by spirv_info_c.py 
>> script */
> "is generated automatically"
>
> Reviewed-by: Kenneth Graunke 

Ups, I already pushed the original version with Eric Rb. Should I push a
typo fix commit?

>
>> +
>> +""" + COPYRIGHT + """\
>>  #include "spirv_info.h"
>>  % for kind,values in info:
>>  
>>




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Re: [Mesa-dev] [PATCH 2/2] i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen9+

[Kenneth Graunke]

On Friday, November 3, 2017 3:31:42 PM PST Jason Ekstrand wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c| 9 +
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c   | 2 ++
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++--
>  3 files changed, 13 insertions(+), 2 deletions(-)

Subject is wrong, should be Gen8+ not gen9+.

Both patches are
Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

[Matt Turner]

On Mon, Nov 13, 2017 at 1:12 PM, Rogovin, Kevin  wrote:
> Hi,
>
>
>  I confess I am not 100% on this code and I did educated guessing what it is  
> trying to do; I figured it was trying to insert contents at the current index 
> i; and that ann_count is the size -after- the insert. thus I figured the 
> memmove is to move the half open interval [i, ann_count-1) to the half open 
> interval [i + 1, ann_count). The number of elements in the half open range 
> [i, ann_count - 1) is given by ann_count - i - 1.
>
> I tried changing the count from ann_count - i - 1 to ann_count - i + 1 and 
> then the disassembler crashed in annotation on the same shaders that I have 
> had it crash on before.

Interesting. Could you send me the shader binary? I'll take a look.
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Re: [Mesa-dev] [PATCH] spirv: add DO NOT EDIT warning on generated spirv_info.c

[Ian Romanick]

Hrm... I should probably add this to the generated files that I'm adding.

On 11/13/2017 02:16 AM, Alejandro Piñeiro wrote:
> ---
>  src/compiler/spirv/spirv_info_c.py | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/src/compiler/spirv/spirv_info_c.py 
> b/src/compiler/spirv/spirv_info_c.py
> index c5e11dfc837..11235cfa3e4 100644
> --- a/src/compiler/spirv/spirv_info_c.py
> +++ b/src/compiler/spirv/spirv_info_c.py
> @@ -51,7 +51,10 @@ def parse_args():
>  p.add_argument("out")
>  return p.parse_args()
>  
> -TEMPLATE  = Template(COPYRIGHT + """\
> +TEMPLATE  = Template("""\
> +/* DO NOT EDIT - This file generated automatically by spirv_info_c.py script 
> */
> +
> +""" + COPYRIGHT + """\
>  #include "spirv_info.h"
>  % for kind,values in info:
>  
> 

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Re: [Mesa-dev] [PATCH] mesa: replace GLenum with GLenum16 in common structures

[Ian Romanick]

On 11/08/2017 07:16 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> For lower CPU cache usage. All enums fit within 2 bytes.

Have you benchmarked this on anything?  My recollection is that for many
things loads and stores of 16-bit values is more expensive than 8- or
32-bit values on 64-bit architectures.  More recent CPUs may have
changed in this respect... I think that was back in the Core2 kind of
time frame, but I thought it also applied to AMD CPUs.

I've often toyed with the idea of converting a bunch of these to
zero-based enums that could be stored in uint8_t (like Gallium?), but I
just never got around to it.

> gl_context = 152400 -> 136824 bytes
> vbo_context = 22696 -> 21520 bytes

Ouch.  Just... ouch.

> ---
>  src/mesa/drivers/dri/nouveau/nv04_state_frag.c |   4 +-
>  src/mesa/drivers/dri/nouveau/nv10_state_frag.c |   4 +-
>  src/mesa/main/glheader.h   |   1 +
>  src/mesa/main/mtypes.h | 210 
> -
>  src/mesa/vbo/vbo_exec.h|   2 +-
>  src/mesa/vbo/vbo_save.h|   4 +-
>  src/mesa/vbo/vbo_save_draw.c   |   2 +-
>  7 files changed, 114 insertions(+), 113 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c 
> b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
> index 248a7d2..bfe8eae 100644
> --- a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
> +++ b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
> @@ -42,22 +42,22 @@
>   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA0
>  
>  struct combiner_state {
>   struct gl_context *ctx;
>   int unit;
>   GLboolean alpha;
>   GLboolean premodulate;
>  
>   /* GL state */
>   GLenum mode;
> - GLenum *source;
> - GLenum *operand;
> + GLenum16 *source;
> + GLenum16 *operand;
>   GLuint logscale;
>  
>   /* Derived HW state */
>   uint32_t hw;
>  };
>  
>  #define __INIT_COMBINER_ALPHA_A GL_TRUE
>  #define __INIT_COMBINER_ALPHA_RGB GL_FALSE
>  
>  /* Initialize a combiner_state struct from the texture unit
> diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c 
> b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
> index c6e4bb0..42dff08 100644
> --- a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
> +++ b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
> @@ -60,22 +60,22 @@
>  /* spare0_i = A_i * B_i + C_i * D_i */
>  #define RC_OUT_SUM   NV10_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0
>  
>  struct combiner_state {
>   struct gl_context *ctx;
>   int unit;
>   GLboolean premodulate;
>  
>   /* GL state */
>   GLenum mode;
> - GLenum *source;
> - GLenum *operand;
> + GLenum16 *source;
> + GLenum16 *operand;
>   GLuint logscale;
>  
>   /* Derived HW state */
>   uint64_t in;
>   uint32_t out;
>  };
>  
>  /* Initialize a combiner_state struct from the texture unit
>   * context. */
>  #define INIT_COMBINER(chan, ctx, rc, i) do { \
> diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
> index 3f2a923..3729604 100644
> --- a/src/mesa/main/glheader.h
> +++ b/src/mesa/main/glheader.h
> @@ -36,20 +36,21 @@
>  #define GL_GLEXT_PROTOTYPES
>  #include "GL/gl.h"
>  #include "GL/glext.h"
>  
>  
>  #ifdef __cplusplus
>  extern "C" {
>  #endif
>  
>  
> +typedef unsigned short GLenum16; /* custom Mesa type to save space */
>  typedef int GLclampx;
>  
>  
>  #ifndef GL_OES_EGL_image
>  typedef void *GLeglImageOES;
>  #endif
>  
>  
>  #ifndef GL_OES_EGL_image_external
>  #define GL_TEXTURE_EXTERNAL_OES 0x8D65
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index fd5306c..078cf20 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -375,21 +375,21 @@ struct gl_light
>  
>  
>  /**
>   * Light model state.
>   */
>  struct gl_lightmodel
>  {
> GLfloat Ambient[4];   /**< ambient color */
> GLboolean LocalViewer;/**< Local (or infinite) view point? */
> GLboolean TwoSide;/**< Two (or one) sided lighting? */
> -   GLenum ColorControl;  /**< either GL_SINGLE_COLOR
> +   GLenum16 ColorControl;/**< either GL_SINGLE_COLOR
>*or GL_SEPARATE_SPECULAR_COLOR */
>  };
>  
>  
>  /**
>   * Accumulation buffer attribute group (GL_ACCUM_BUFFER_BIT)
>   */
>  struct gl_accum_attrib
>  {
> GLfloat ClearColor[4];/**< Accumulation buffer clear color */
> @@ -411,53 +411,53 @@ union gl_color_union
>  /**
>   * Color buffer attribute group (GL_COLOR_BUFFER_BIT).
>   */
>  struct gl_colorbuffer_attrib
>  {
> GLuint ClearIndex;  /**< Index for glClear */
> union gl_color_union ClearColor;/**< Color for glClear, unclamped 
> */
> GLuint IndexMask;   /**< Color index write mask */
> GLubyte ColorMask[MAX_DRAW_BUFFERS][4]; /**< Each flag is 0xff or 0x0 */
>  
> -   

Re: [Mesa-dev] [PATCH v3 17/43] i965/fs: Enable rounding mode on f2f16 ops

[Jason Ekstrand]

On Mon, Nov 13, 2017 at 12:41 PM, Chema Casanova 
wrote:

> On 30/10/17 23:40, Jason Ekstrand wrote:
> > On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo
> > > wrote:
> >
> > From: Alejandro Piñeiro  > >
> >
> > By default we don't set the rounding mode. We only set
> > round-to-near-even or round-to-zero mode if explicitly set from nir.
> >
> > v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
> > with the rounding mode (Curro)
> >
> > Signed-off-by: Jose Maria Casanova Crespo  > >
> > Signed-off-by: Alejandro Piñeiro  > >
> > ---
> >  src/intel/compiler/brw_fs_nir.cpp | 8 
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/src/intel/compiler/brw_fs_nir.cpp
> > b/src/intel/compiler/brw_fs_nir.cpp
> > index 6908c7ea02..b356836e80 100644
> > --- a/src/intel/compiler/brw_fs_nir.cpp
> > +++ b/src/intel/compiler/brw_fs_nir.cpp
> > @@ -693,6 +693,14 @@ fs_visitor::nir_emit_alu(const fs_builder ,
> > nir_alu_instr *instr)
> >inst->saturate = instr->dest.saturate;
> >break;
> >
> > +   case nir_op_f2f16_rtne:
> > +   case nir_op_f2f16_rtz:
> > +  if (instr->op == nir_op_f2f16_rtz)
> > + bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
> > brw_imm_d(BRW_RND_MODE_RTZ));
> > +  else if (instr->op == nir_op_f2f16_rtne)
> > + bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
> > brw_imm_d(BRW_RND_MODE_RTNE));
> > +  /* fallthrough */
> >
> >
> > It might look a little nicer (though it's more lines of code) to have a
> > little brw_from_nir_rounding_mode helper and then we could have just the
> > one emit call.  I don't care too much though.
>
>
> What about this helper?
>
> static brw_rnd_mode
> brw_rnd_mode_from_nir_op (const nir_op op) {
>switch (op) {
>case nir_op_f2f16_rtz:
>   return BRW_RND_MODE_RTZ;
>case nir_op_f2f16_rtne:
>   return BRW_RND_MODE_RTNE;
>default:
>   unreachable("Operation doesn't support rounding mode");
>}
> }
>
> And ...
>
>case nir_op_f2f16_rtne:
>case nir_op_f2f16_rtz:
>   bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
>brw_imm_d(brw_rnd_mode_from_nir_op(instr->op)));
>

Sounds good to me.


> >
> > +
> >/* In theory, it would be better to use BRW_OPCODE_F32TO16.
> > Depending
> > * on the HW gen, it is a special hw opcode or just a MOV, and
> > * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
> > --
> > 2.13.6
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org  freedesktop.org>
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
> >
> >
> >
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
>
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Re: [Mesa-dev] [PATCH 08/18] intel/compiler:add function to give option to print offsets into assembly

[Rogovin, Kevin]

I am fine with that suggestion of changing the function signature and to not 
add a new one; I wanted the changes I made to be as uninvasive as possible 
which is why I added the function instead of changing an existing one.

-Kevin

-Original Message-
From: Matt Turner [mailto:matts...@gmail.com] 
Sent: Monday, November 13, 2017 9:42 PM
To: Rogovin, Kevin 
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH 08/18] intel/compiler:add function to give 
option to print offsets into assembly

On Mon, Nov 13, 2017 at 5:17 AM,   wrote:
> From: Kevin Rogovin 
>
> Signed-off-by: Kevin Rogovin 
> ---
>  src/intel/compiler/brw_eu.c | 11 ++-  
> src/intel/compiler/brw_eu.h |  3 +++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c 
> index bc297a21b3..8969ae5bda 100644
> --- a/src/intel/compiler/brw_eu.c
> +++ b/src/intel/compiler/brw_eu.c
> @@ -339,6 +339,15 @@ const unsigned *brw_get_program( struct 
> brw_codegen *p,  void  brw_disassemble(const struct gen_device_info 
> *devinfo,
>  const void *assembly, int start, int end, FILE *out)
> +{
> +   brw_disassemble_print_offset_option(devinfo, assembly, start, end, out,
> +   false); }
> +
> +void
> +brw_disassemble_print_offset_option(const struct gen_device_info *devinfo,
> +const void *assembly, int start, int end,
> +FILE *out, bool print_offsets)
>  {
> bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
>
> @@ -346,7 +355,7 @@ brw_disassemble(const struct gen_device_info *devinfo,
>const brw_inst *insn = assembly + offset;
>brw_inst uncompacted;
>bool compacted = brw_inst_cmpt_control(devinfo, insn);
> -  if (0)
> +  if (print_offsets)
>   fprintf(out, "0x%08x: ", offset);
>
>if (compacted) {
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h 
> index 95503d5513..497cf9e575 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -128,6 +128,9 @@ int brw_disassemble_inst(FILE *file, const struct 
> gen_device_info *devinfo,
>   const struct brw_inst *inst, bool 
> is_compacted);  void brw_disassemble(const struct gen_device_info *devinfo,
>   const void *assembly, int start, int end, FILE 
> *out);
> +void brw_disassemble_print_offset_option(const struct gen_device_info 
> *devinfo,
> + const void *assembly, int start, 
> int end,
> + FILE *out, bool 
> +print_offsets);

Instead of adding a new function, I'd be in favor of just adding the bool 
print_offsets parameter to brw_disassemble (before the FILE parameter). Then we 
can add an INTEL_DEBUG=print_offsets and pass INTEL_DEBUG & DEBUG_PRINT_OFFSETS 
as the argument in the existing calls.
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Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

[Rogovin, Kevin]

Hi,


 I confess I am not 100% on this code and I did educated guessing what it is  
trying to do; I figured it was trying to insert contents at the current index 
i; and that ann_count is the size -after- the insert. thus I figured the 
memmove is to move the half open interval [i, ann_count-1) to the half open 
interval [i + 1, ann_count). The number of elements in the half open range [i, 
ann_count - 1) is given by ann_count - i - 1.

I tried changing the count from ann_count - i - 1 to ann_count - i + 1 and then 
the disassembler crashed in annotation on the same shaders that I have had it 
crash on before.

 -Kevin

-Original Message-
From: Matt Turner [mailto:matts...@gmail.com] 
Sent: Monday, November 13, 2017 9:02 PM
To: Rogovin, Kevin 
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument 
on annotating error

On Mon, Nov 13, 2017 at 5:17 AM,   wrote:
> From: Kevin Rogovin 
>
> Without this fix, disassembling of GEN shaders with GPU commands that 
> the disassembler does not know would result in errors being added to 
> the annotator which would crash when more than one error was added.
>
> Signed-off-by: Kevin Rogovin 
> ---
>  src/intel/compiler/intel_asm_annotation.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/intel_asm_annotation.c 
> b/src/intel/compiler/intel_asm_annotation.c
> index b07a545a12..7aa222f04e 100644
> --- a/src/intel/compiler/intel_asm_annotation.c
> +++ b/src/intel/compiler/intel_asm_annotation.c
> @@ -181,8 +181,9 @@ annotation_insert_error(struct annotation_info 
> *annotation, unsigned offset,
>   continue;
>
>if (offset + sizeof(brw_inst) != next->offset) {
> - memmove(next, cur,
> - (annotation->ann_count - i + 2) * sizeof(struct 
> annotation));
> + int count;
> + count = annotation->ann_count - i - 1;
> + memmove(next, cur, count * sizeof(struct annotation));

I don't see how this can be right.

Take for example a case where we have ann_count == 4. We have
annotation->ann[0..4] where ann[4] is the end marker... a little
surprising. We want to insert an error annotation on an instruction in ann[2] 
but not at the end, so we need to split ann[2].

cur = 2, next = 3. We need to memmove elements 2, 3, 4 one spot later, and then 
update ann[2] and ann[3] (which after the memmove is a copy of ann[2]).

Count should be ann_count (4) - i (2) + 1 -> 3. The code currently says +2 
instead of +1 and that seems like a bug.

What do you think?
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[Mesa-dev] [Bug 103658] addrlib/gfx9/gfx9addrlib.cpp:727:50: error: expected expression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103658

Vinson Lee  changed:

   What|Removed |Added

 CC||mar...@gmail.com,
   ||nhaeh...@gmail.com
   Keywords||regression

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Re: [Mesa-dev] [PATCH 1/3] meson: don't use build_by_default for specific gallium drivers

[Eric Anholt]

Dylan Baker  writes:

> Using build_by_default : false is convenient for dependencies that can
> be pulled in by various diverse components of the build system, the
> gallium hardware/software drivers and state trackers do not fit that
> description. Instead, these should be guarded using the variable that tracks
> whether that driver should be enabled.
>
> This leaves a few helper libraries: trace, rbug, etc, and the generic
> winsys bits as `build_by_default : false` because there are a large
> number of gallium components that pull them in.
>
> v2: - remove build_by_default from winsys convenience libs as well.
>
> Signed-off-by: Dylan Baker 
> Tested-by: Lionel Landwerlin  (v1)
> ---
>  src/gallium/drivers/freedreno/meson.build|  1 -
>  src/gallium/drivers/llvmpipe/meson.build |  1 -
>  src/gallium/drivers/nouveau/meson.build  |  1 -
>  src/gallium/drivers/radeon/meson.build   |  1 -
>  src/gallium/drivers/radeonsi/meson.build |  1 -
>  src/gallium/drivers/softpipe/meson.build |  1 -
>  src/gallium/drivers/vc5/meson.build  |  1 -
>  src/gallium/meson.build  | 47 
> +++-
>  src/gallium/state_trackers/dri/meson.build   |  1 -
>  src/gallium/winsys/amdgpu/drm/meson.build|  1 -
>  src/gallium/winsys/freedreno/drm/meson.build |  1 -
>  src/gallium/winsys/nouveau/drm/meson.build   |  1 -
>  src/gallium/winsys/radeon/drm/meson.build|  1 -
>  13 files changed, 25 insertions(+), 34 deletions(-)
>
> diff --git a/src/gallium/drivers/freedreno/meson.build 
> b/src/gallium/drivers/freedreno/meson.build
> index fe1a902e9e5..d2b901334d0 100644
> --- a/src/gallium/drivers/freedreno/meson.build
> +++ b/src/gallium/drivers/freedreno/meson.build
> @@ -207,7 +207,6 @@ libfreedreno = static_library(
>c_args : [c_vis_args],
>cpp_args : [cpp_vis_args],
>dependencies : [dep_libdrm, dep_libdrm_freedreno],
> -  build_by_default : false,
>  )
>  
>  ir3_compiler = executable(
> diff --git a/src/gallium/drivers/llvmpipe/meson.build 
> b/src/gallium/drivers/llvmpipe/meson.build
> index ca1d2aa797b..9d0edb0ac33 100644
> --- a/src/gallium/drivers/llvmpipe/meson.build
> +++ b/src/gallium/drivers/llvmpipe/meson.build
> @@ -98,7 +98,6 @@ libllvmpipe = static_library(
>cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
>include_directories : [inc_gallium, inc_gallium_aux, inc_include, inc_src],
>dependencies : dep_llvm,
> -  build_by_default : false,
>  )
>  
>  if with_tests and with_gallium_softpipe and with_llvm
> diff --git a/src/gallium/drivers/nouveau/meson.build 
> b/src/gallium/drivers/nouveau/meson.build
> index 2bc6142879e..59fecfc5255 100644
> --- a/src/gallium/drivers/nouveau/meson.build
> +++ b/src/gallium/drivers/nouveau/meson.build
> @@ -211,7 +211,6 @@ libnouveau = static_library(
>c_args : [c_vis_args],
>cpp_args : [cpp_vis_args],
>dependencies : [dep_libdrm, dep_libdrm_nouveau],
> -  build_by_default : false,
>  )
>  
>  nouveau_compiler = executable(
> diff --git a/src/gallium/drivers/radeon/meson.build 
> b/src/gallium/drivers/radeon/meson.build
> index b4d2832d016..f378b12e8e8 100644
> --- a/src/gallium/drivers/radeon/meson.build
> +++ b/src/gallium/drivers/radeon/meson.build
> @@ -51,5 +51,4 @@ libradeon = static_library(
>include_directories : [
>  inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_gallium_drivers,
>],
> -  build_by_default : false,
>  )
> diff --git a/src/gallium/drivers/radeonsi/meson.build 
> b/src/gallium/drivers/radeonsi/meson.build
> index 4392184dbb6..974004db67f 100644
> --- a/src/gallium/drivers/radeonsi/meson.build
> +++ b/src/gallium/drivers/radeonsi/meson.build
> @@ -75,5 +75,4 @@ libradeonsi = static_library(
>c_args : [c_vis_args],
>cpp_args : [cpp_vis_args],
>dependencies : dep_llvm,
> -  build_by_default : false,
>  )
> diff --git a/src/gallium/drivers/softpipe/meson.build 
> b/src/gallium/drivers/softpipe/meson.build
> index 0cef15152e2..df23533c72c 100644
> --- a/src/gallium/drivers/softpipe/meson.build
> +++ b/src/gallium/drivers/softpipe/meson.build
> @@ -81,5 +81,4 @@ libsoftpipe = static_library(
>files_softpipe,
>include_directories : [inc_gallium_aux, inc_gallium, inc_include, inc_src],
>c_args : [c_vis_args, c_msvc_compat_args],
> -  build_by_default : false,
>  )
> diff --git a/src/gallium/drivers/vc5/meson.build 
> b/src/gallium/drivers/vc5/meson.build
> index d066366fcc7..61059a15560 100644
> --- a/src/gallium/drivers/vc5/meson.build
> +++ b/src/gallium/drivers/vc5/meson.build
> @@ -61,5 +61,4 @@ libvc5 = static_library(
>c_args : [c_vis_args, v3dv3_c_args],
>cpp_args : [cpp_vis_args],
>dependencies : [dep_v3dv3, dep_libdrm, dep_valgrind],
> -  build_by_default : false,
>  )
> diff --git a/src/gallium/meson.build b/src/gallium/meson.build
> index c5772b36cb6..5341e093bfb 100644
> --- a/src/gallium/meson.build
> +++ 

[Mesa-dev] [PATCH] virgl: also remove dimension on indirect.

[Dave Airlie]

From: Dave Airlie 

This fixes some dEQP tests that generated bad shaders.

Fixes: b6f6ead19 (virgl: drop const dimensions on first block.)
Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/virgl/virgl_tgsi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_tgsi.c 
b/src/gallium/drivers/virgl/virgl_tgsi.c
index aa483ad..ca05913 100644
--- a/src/gallium/drivers/virgl/virgl_tgsi.c
+++ b/src/gallium/drivers/virgl/virgl_tgsi.c
@@ -76,7 +76,6 @@ virgl_tgsi_transform_instruction(struct 
tgsi_transform_context *ctx,
for (unsigned i = 0; i < inst->Instruction.NumSrcRegs; i++) {
   if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT &&
   inst->Src[i].Register.Dimension &&
-  !inst->Src[i].Register.Indirect &&
   inst->Src[i].Dimension.Index == 0)
  inst->Src[i].Register.Dimension = 0;
}
-- 
2.9.5

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Re: [Mesa-dev] [PATCH v3 17/43] i965/fs: Enable rounding mode on f2f16 ops

[Chema Casanova]

On 30/10/17 23:40, Jason Ekstrand wrote:
> On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo
> > wrote:
> 
> From: Alejandro Piñeiro  >
> 
> By default we don't set the rounding mode. We only set
> round-to-near-even or round-to-zero mode if explicitly set from nir.
> 
> v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
>     with the rounding mode (Curro)
> 
> Signed-off-by: Jose Maria Casanova Crespo  >
> Signed-off-by: Alejandro Piñeiro  >
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index 6908c7ea02..b356836e80 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -693,6 +693,14 @@ fs_visitor::nir_emit_alu(const fs_builder ,
> nir_alu_instr *instr)
>        inst->saturate = instr->dest.saturate;
>        break;
> 
> +   case nir_op_f2f16_rtne:
> +   case nir_op_f2f16_rtz:
> +      if (instr->op == nir_op_f2f16_rtz)
> +         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
> brw_imm_d(BRW_RND_MODE_RTZ));
> +      else if (instr->op == nir_op_f2f16_rtne)
> +         bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
> brw_imm_d(BRW_RND_MODE_RTNE));
> +      /* fallthrough */
> 
> 
> It might look a little nicer (though it's more lines of code) to have a
> little brw_from_nir_rounding_mode helper and then we could have just the
> one emit call.  I don't care too much though.


What about this helper?

static brw_rnd_mode
brw_rnd_mode_from_nir_op (const nir_op op) {
   switch (op) {
   case nir_op_f2f16_rtz:
  return BRW_RND_MODE_RTZ;
   case nir_op_f2f16_rtne:
  return BRW_RND_MODE_RTNE;
   default:
  unreachable("Operation doesn't support rounding mode");
   }
}

And ...

   case nir_op_f2f16_rtne:
   case nir_op_f2f16_rtz:
  bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
   brw_imm_d(brw_rnd_mode_from_nir_op(instr->op)));


> 
> +
>        /* In theory, it would be better to use BRW_OPCODE_F32TO16.
> Depending
>         * on the HW gen, it is a special hw opcode or just a MOV, and
>         * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
> --
> 2.13.6
> 
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> 
> 
> 
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[Mesa-dev] [Bug 103586] OpenCL/Clover: AMD Turks: corrupt output buffer (depending on dimension order?)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103586

--- Comment #13 from Vedran Miletić  ---
(In reply to Dave Gilbert from comment #6)
> (In reply to Jan Vesely from comment #5)
> > (In reply to Dave Gilbert from comment #4)
> > > Created attachment 135313 [details]
> > > foo.link-0.ll
> > > 
> > > That's all 3 of the debug files it produced.
> > > (I wasn't sure which were the llvm and which the isa dumps; I guess the 
> > > asm
> > > is the isa? and the ll's are both llvm dumps?)
> > 
> > yes. the first .ll is from compilation step, the other one is from linking
> > step.
> > 
> > .ll dump looks correct.
> > .asm also looks correct.
> > 
> > you can try producing multiple asm dumps for working and non-working runs.
> > But I don't think that the llvm is the culprit here.
> > 
> > Can you try waiting for the kernel execution to complete explicitly before
> > mapping the buffer?
> > Ideally call clFinish() on line 63.
> 
> Since I'm on the C++ binding (probably a mistake) I used:
>   queue.finish();
> 
> and it seems to be working.
> 
> (This also corresponds possibly to what I'm seeing on a more complex kernel;
> with a more complex kernel I'm seeing on a whole pile of data on the last
> few Z slices as being bogus suggesting it's not finished).
> 
> Dave

This reminds me of a certain issue I experienced with OpenMM. Is it limited to
Turks, or it happens on SI+ cards?

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[Mesa-dev] [Bug 103586] OpenCL/Clover: AMD Turks: corrupt output buffer (depending on dimension order?)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103586

--- Comment #12 from Dave Gilbert  ---
(In reply to Jan Vesely from comment #11)
> (In reply to Dave Gilbert from comment #10)
> > I believe I'm still seeing this:
> > 
> > dg@hath:~/ocl2$ clinfo 
> > Number of platforms   1
> >   Platform Name   Clover
> >   Platform Vendor Mesa
> >   Platform VersionOpenCL 1.1 Mesa
> > 17.4.0-devel (git-a16dc04ad5)
> > 
> > dg@hath:~/ocl2$ echo $LD_LIBRARY_PATH 
> > /home/dg/mesa/try/lib:
> > 
> > so I *think* it's using my build.
> 
> yes, that looks OK.
> 
> > and I believe I'm still seeing it.
> > Is my test valid or do I really need that finish?
> 
> it should be OK. Can you replace the clFinish with clWaitForEvents (or the
> respective C++ method) to wait for kernel execution?
> It looks to me that clover creates new map without waiting for all the dep
> events.

It doesn't seem to help, if I add:
--- a/ocl.cpp
+++ b/ocl.cpp
@@ -74,6 +74,7 @@ static int got_dev(cl::Platform ,
std::vector , cl::Dev
 cl::Event eventBarrier2;
 queue.enqueueBarrierWithWaitList(NULL,);
 std::cerr << __func__ << "enqueueMapBuffer gave: " << err << std::endl;
+event.wait();
 eventMap.wait();
 eventBarrier2.wait();


that doesn't seem to help and I think event is the event triggered by the
kernel.

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Re: [Mesa-dev] [PATCH 09/18] intel/tools/disasm: gen_disasm_disassemble to take const void* instead of void*

[Matt Turner]

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH 10/18] intel/tools/disasm: add gen_disasm_assembly_length function

[Matt Turner]

Pending the questions about 07/18, I don't think this should be necessary.
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Re: [Mesa-dev] [PATCH 08/18] intel/compiler:add function to give option to print offsets into assembly

[Matt Turner]

On Mon, Nov 13, 2017 at 5:17 AM,   wrote:
> From: Kevin Rogovin 
>
> Signed-off-by: Kevin Rogovin 
> ---
>  src/intel/compiler/brw_eu.c | 11 ++-
>  src/intel/compiler/brw_eu.h |  3 +++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
> index bc297a21b3..8969ae5bda 100644
> --- a/src/intel/compiler/brw_eu.c
> +++ b/src/intel/compiler/brw_eu.c
> @@ -339,6 +339,15 @@ const unsigned *brw_get_program( struct brw_codegen *p,
>  void
>  brw_disassemble(const struct gen_device_info *devinfo,
>  const void *assembly, int start, int end, FILE *out)
> +{
> +   brw_disassemble_print_offset_option(devinfo, assembly, start, end, out,
> +   false);
> +}
> +
> +void
> +brw_disassemble_print_offset_option(const struct gen_device_info *devinfo,
> +const void *assembly, int start, int end,
> +FILE *out, bool print_offsets)
>  {
> bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
>
> @@ -346,7 +355,7 @@ brw_disassemble(const struct gen_device_info *devinfo,
>const brw_inst *insn = assembly + offset;
>brw_inst uncompacted;
>bool compacted = brw_inst_cmpt_control(devinfo, insn);
> -  if (0)
> +  if (print_offsets)
>   fprintf(out, "0x%08x: ", offset);
>
>if (compacted) {
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 95503d5513..497cf9e575 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -128,6 +128,9 @@ int brw_disassemble_inst(FILE *file, const struct 
> gen_device_info *devinfo,
>   const struct brw_inst *inst, bool is_compacted);
>  void brw_disassemble(const struct gen_device_info *devinfo,
>   const void *assembly, int start, int end, FILE *out);
> +void brw_disassemble_print_offset_option(const struct gen_device_info 
> *devinfo,
> + const void *assembly, int start, 
> int end,
> + FILE *out, bool print_offsets);

Instead of adding a new function, I'd be in favor of just adding the
bool print_offsets parameter to brw_disassemble (before the FILE
parameter). Then we can add an INTEL_DEBUG=print_offsets and pass
INTEL_DEBUG & DEBUG_PRINT_OFFSETS as the argument in the existing
calls.
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Re: [Mesa-dev] [PATCH] r600: don't emit atomic save if we have no atomic counters.

[Gert Wollny]

Obviously, you can now disregard my other email about the performance
regression, this fixes it. 

Tested-By: Gert Wollny 

Best wishes, 


Am Freitag, den 10.11.2017, 13:47 +1000 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> Otherwise we end up emitting the fence.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/gallium/drivers/r600/evergreen_state.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/gallium/drivers/r600/evergreen_state.c
> b/src/gallium/drivers/r600/evergreen_state.c
> index c1d13fd..30819ae 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -4634,6 +4634,9 @@ void evergreen_emit_atomic_buffer_save(struct
> r600_context *rctx,
>   unsigned reloc;
>  
>   mask = *atomic_used_mask_p;
> + if (!mask)
> + return;
> +
>   while (mask) {
>   unsigned atomic_index = u_bit_scan();
>   struct r600_shader_atomic *atomic =
> _atomics[atomic_index];
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[Mesa-dev] Performance regression, was [PATCH 09/10] r600: add support for hw atomic counters.

[Gert Wollny]

Hi Dave, 

since I'm currently experimenting with improving the performance of the
tesselation shaders on r600, I notes that this series has a negative
impact on performance, i.e. with the Unigine_Heaven benchmark I get a
10% lower frame rate that can be attributed to the newly added fence
that is created in r600_create_context (r600_pipe.c:192) (See the chunk
below). 

Considering that most programs don't need atomics, I wonder whether it
would make sense to only add this fence when the shaders involved are
actually using atomics, and I'm also wondering how the latter could
actually be made known at this point where the fence is created. 

Any pointers?

Many thanks, 
Gert  

Am Donnerstag, den 02.11.2017, 15:42 +1000 schrieb Dave Airlie:
> From: Dave Airlie 
> 

> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -186,6 +188,9 @@ static struct pipe_context
> *r600_create_context(struct pipe_screen *screen,
>      rctx->b.family == CHIP_CAICOS ||
>      rctx->b.family == CHIP_CAYMAN ||
>      rctx->b.family == CHIP_ARUBA);
> +
> + rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, 
> +PIPE_BIND_CUSTOM,  PIPE_USAGE_DEFAULT, 32);
>   break;
>   default:
>   R600_ERR("Unsupported chip class %d.\n", rctx-
> >b.chip_class);
> 
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[Mesa-dev] [PATCH 1/3] meson: don't use build_by_default for specific gallium drivers

[Dylan Baker]

Using build_by_default : false is convenient for dependencies that can
be pulled in by various diverse components of the build system, the
gallium hardware/software drivers and state trackers do not fit that
description. Instead, these should be guarded using the variable that tracks
whether that driver should be enabled.

This leaves a few helper libraries: trace, rbug, etc, and the generic
winsys bits as `build_by_default : false` because there are a large
number of gallium components that pull them in.

v2: - remove build_by_default from winsys convenience libs as well.

Signed-off-by: Dylan Baker 
Tested-by: Lionel Landwerlin  (v1)
---
 src/gallium/drivers/freedreno/meson.build|  1 -
 src/gallium/drivers/llvmpipe/meson.build |  1 -
 src/gallium/drivers/nouveau/meson.build  |  1 -
 src/gallium/drivers/radeon/meson.build   |  1 -
 src/gallium/drivers/radeonsi/meson.build |  1 -
 src/gallium/drivers/softpipe/meson.build |  1 -
 src/gallium/drivers/vc5/meson.build  |  1 -
 src/gallium/meson.build  | 47 +++-
 src/gallium/state_trackers/dri/meson.build   |  1 -
 src/gallium/winsys/amdgpu/drm/meson.build|  1 -
 src/gallium/winsys/freedreno/drm/meson.build |  1 -
 src/gallium/winsys/nouveau/drm/meson.build   |  1 -
 src/gallium/winsys/radeon/drm/meson.build|  1 -
 13 files changed, 25 insertions(+), 34 deletions(-)

diff --git a/src/gallium/drivers/freedreno/meson.build 
b/src/gallium/drivers/freedreno/meson.build
index fe1a902e9e5..d2b901334d0 100644
--- a/src/gallium/drivers/freedreno/meson.build
+++ b/src/gallium/drivers/freedreno/meson.build
@@ -207,7 +207,6 @@ libfreedreno = static_library(
   c_args : [c_vis_args],
   cpp_args : [cpp_vis_args],
   dependencies : [dep_libdrm, dep_libdrm_freedreno],
-  build_by_default : false,
 )
 
 ir3_compiler = executable(
diff --git a/src/gallium/drivers/llvmpipe/meson.build 
b/src/gallium/drivers/llvmpipe/meson.build
index ca1d2aa797b..9d0edb0ac33 100644
--- a/src/gallium/drivers/llvmpipe/meson.build
+++ b/src/gallium/drivers/llvmpipe/meson.build
@@ -98,7 +98,6 @@ libllvmpipe = static_library(
   cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
   include_directories : [inc_gallium, inc_gallium_aux, inc_include, inc_src],
   dependencies : dep_llvm,
-  build_by_default : false,
 )
 
 if with_tests and with_gallium_softpipe and with_llvm
diff --git a/src/gallium/drivers/nouveau/meson.build 
b/src/gallium/drivers/nouveau/meson.build
index 2bc6142879e..59fecfc5255 100644
--- a/src/gallium/drivers/nouveau/meson.build
+++ b/src/gallium/drivers/nouveau/meson.build
@@ -211,7 +211,6 @@ libnouveau = static_library(
   c_args : [c_vis_args],
   cpp_args : [cpp_vis_args],
   dependencies : [dep_libdrm, dep_libdrm_nouveau],
-  build_by_default : false,
 )
 
 nouveau_compiler = executable(
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index b4d2832d016..f378b12e8e8 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -51,5 +51,4 @@ libradeon = static_library(
   include_directories : [
 inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_gallium_drivers,
   ],
-  build_by_default : false,
 )
diff --git a/src/gallium/drivers/radeonsi/meson.build 
b/src/gallium/drivers/radeonsi/meson.build
index 4392184dbb6..974004db67f 100644
--- a/src/gallium/drivers/radeonsi/meson.build
+++ b/src/gallium/drivers/radeonsi/meson.build
@@ -75,5 +75,4 @@ libradeonsi = static_library(
   c_args : [c_vis_args],
   cpp_args : [cpp_vis_args],
   dependencies : dep_llvm,
-  build_by_default : false,
 )
diff --git a/src/gallium/drivers/softpipe/meson.build 
b/src/gallium/drivers/softpipe/meson.build
index 0cef15152e2..df23533c72c 100644
--- a/src/gallium/drivers/softpipe/meson.build
+++ b/src/gallium/drivers/softpipe/meson.build
@@ -81,5 +81,4 @@ libsoftpipe = static_library(
   files_softpipe,
   include_directories : [inc_gallium_aux, inc_gallium, inc_include, inc_src],
   c_args : [c_vis_args, c_msvc_compat_args],
-  build_by_default : false,
 )
diff --git a/src/gallium/drivers/vc5/meson.build 
b/src/gallium/drivers/vc5/meson.build
index d066366fcc7..61059a15560 100644
--- a/src/gallium/drivers/vc5/meson.build
+++ b/src/gallium/drivers/vc5/meson.build
@@ -61,5 +61,4 @@ libvc5 = static_library(
   c_args : [c_vis_args, v3dv3_c_args],
   cpp_args : [cpp_vis_args],
   dependencies : [dep_v3dv3, dep_libdrm, dep_valgrind],
-  build_by_default : false,
 )
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index c5772b36cb6..5341e093bfb 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -27,41 +27,44 @@ subdir('drivers/ddebug')
 subdir('drivers/noop')
 subdir('drivers/trace')
 subdir('drivers/rbug')
-subdir('drivers/radeon')
-subdir('drivers/radeonsi')
-subdir('drivers/nouveau')
-if with_gallium_freedreno
-  subdir('drivers/freedreno')

[Mesa-dev] [PATCH 2/3] meson: Don't build intel shared components by default

[Dylan Baker]

It's a neat idea, and still useful in some cases, but the intel common
code is used by i965 and anvil only, this is a little clearer.

Signed-off-by: Dylan Baker 
---
 src/intel/blorp/meson.build  | 1 -
 src/intel/common/meson.build | 1 -
 src/intel/isl/meson.build| 3 ---
 src/meson.build  | 4 +++-
 4 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/intel/blorp/meson.build b/src/intel/blorp/meson.build
index 9241535fd20..febdea97f3c 100644
--- a/src/intel/blorp/meson.build
+++ b/src/intel/blorp/meson.build
@@ -33,5 +33,4 @@ libblorp = static_library(
   [files_libblorp, nir_opcodes_h],
   include_directories : [inc_common, inc_intel],
   c_args : [c_vis_args, no_override_init_args],
-  build_by_default : false,
 )
diff --git a/src/intel/common/meson.build b/src/intel/common/meson.build
index db7d74a26d2..cbcf6647531 100644
--- a/src/intel/common/meson.build
+++ b/src/intel/common/meson.build
@@ -41,5 +41,4 @@ libintel_common = static_library(
   include_directories : [inc_common, inc_intel],
   c_args : [c_vis_args, no_override_init_args],
   dependencies : [dep_expat, dep_libdrm],
-  build_by_default : false,
 )
diff --git a/src/intel/isl/meson.build b/src/intel/isl/meson.build
index 54024b4d11b..47fd8d97c32 100644
--- a/src/intel/isl/meson.build
+++ b/src/intel/isl/meson.build
@@ -60,7 +60,6 @@ foreach g : [['40', isl_gen4_files], ['50', []], ['60', 
isl_gen6_files],
 include_directories : [inc_common, inc_intel],
 c_args : [c_vis_args, no_override_init_args,
   '-DGEN_VERSIONx10=@0@'.format(_gen)],
-build_by_default : false,
   )
   isl_gen_libs += _lib
 endforeach
@@ -88,7 +87,6 @@ libisl = static_library(
   include_directories : [inc_common, inc_intel, inc_drm_uapi],
   link_with : isl_gen_libs,
   c_args : [c_vis_args, no_override_init_args],
-  build_by_default : false,
 )
 
 if with_tests
@@ -98,7 +96,6 @@ if with_tests
 dependencies : dep_m,
 include_directories : [inc_common, inc_intel],
 link_with : [libisl, libintel_common],
-build_by_default : false,
   )
 
   test('isl_surf_get_image_offset', isl_surf_get_image_offset_test)
diff --git a/src/meson.build b/src/meson.build
index 53c8269a99e..c3b1ff00d00 100644
--- a/src/meson.build
+++ b/src/meson.build
@@ -55,7 +55,9 @@ subdir('amd')
 if with_gallium_vc4
   subdir('broadcom')
 endif
-subdir('intel')
+if with_dri_i965 or with_intel_vk
+  subdir('intel')
+endif
 subdir('mesa')
 subdir('loader')
 subdir('glx')
-- 
2.15.0

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[Mesa-dev] [PATCH 3/3] meson: Remove build_by_default from amd code

[Dylan Baker]

This is the same logic as the previous two patches.

Signed-off-by: Dylan Baker 
---
 src/amd/addrlib/meson.build | 1 -
 src/amd/common/meson.build  | 1 -
 src/meson.build | 4 +++-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/addrlib/meson.build b/src/amd/addrlib/meson.build
index 62beb0ecbc1..1a7f2fdef5d 100644
--- a/src/amd/addrlib/meson.build
+++ b/src/amd/addrlib/meson.build
@@ -57,5 +57,4 @@ libamdgpu_addrlib = static_library(
 'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
 '../common', '../../'),
   cpp_args : [cpp_vis_args, '-DBRAHMA_BUILD=1'],
-  build_by_default : false,
 )
diff --git a/src/amd/common/meson.build b/src/amd/common/meson.build
index 842b42f897e..4fd7edc5cd3 100644
--- a/src/amd/common/meson.build
+++ b/src/amd/common/meson.build
@@ -59,5 +59,4 @@ libamd_common = static_library(
   dep_valgrind],
   c_args : [c_vis_args],
   cpp_args : [cpp_vis_args],
-  build_by_default : false,
 )
diff --git a/src/meson.build b/src/meson.build
index c3b1ff00d00..9232cc4ab18 100644
--- a/src/meson.build
+++ b/src/meson.build
@@ -51,7 +51,9 @@ subdir('mapi')
 subdir('compiler')
 subdir('egl/wayland/wayland-drm')
 subdir('vulkan')
-subdir('amd')
+if with_gallium_radeonsi or with_amd_vk
+  subdir('amd')
+endif
 if with_gallium_vc4
   subdir('broadcom')
 endif
-- 
2.15.0

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Re: [Mesa-dev] [PATCH 11/18] intel/tools/disasm: make sure that entire range is disassembled

[Matt Turner]

On Mon, Nov 13, 2017 at 5:17 AM,   wrote:
> From: Kevin Rogovin 
>
> Without this patch, if a shader has errors, the disassembly of the
> shader often stops after the first opcode that has errors.

I can't see anything wrong with the current code. If I'm right that
07/18 is wrong, could this be papering over the bug introduced in that
patch which would have caused annotations to get lost?
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Re: [Mesa-dev] [PATCH] spirv: add DO NOT EDIT warning on generated spirv_info.c

[Kenneth Graunke]

On Monday, November 13, 2017 2:16:59 AM PST Alejandro Piñeiro wrote:
> ---
>  src/compiler/spirv/spirv_info_c.py | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/src/compiler/spirv/spirv_info_c.py 
> b/src/compiler/spirv/spirv_info_c.py
> index c5e11dfc837..11235cfa3e4 100644
> --- a/src/compiler/spirv/spirv_info_c.py
> +++ b/src/compiler/spirv/spirv_info_c.py
> @@ -51,7 +51,10 @@ def parse_args():
>  p.add_argument("out")
>  return p.parse_args()
>  
> -TEMPLATE  = Template(COPYRIGHT + """\
> +TEMPLATE  = Template("""\
> +/* DO NOT EDIT - This file generated automatically by spirv_info_c.py script 
> */

"is generated automatically"

Reviewed-by: Kenneth Graunke 

> +
> +""" + COPYRIGHT + """\
>  #include "spirv_info.h"
>  % for kind,values in info:
>  
> 



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Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

[Matt Turner]

On Mon, Nov 13, 2017 at 5:17 AM,   wrote:
> From: Kevin Rogovin 
>
> Without this fix, disassembling of GEN shaders with GPU commands
> that the disassembler does not know would result in errors being
> added to the annotator which would crash when more than one error
> was added.
>
> Signed-off-by: Kevin Rogovin 
> ---
>  src/intel/compiler/intel_asm_annotation.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/intel_asm_annotation.c 
> b/src/intel/compiler/intel_asm_annotation.c
> index b07a545a12..7aa222f04e 100644
> --- a/src/intel/compiler/intel_asm_annotation.c
> +++ b/src/intel/compiler/intel_asm_annotation.c
> @@ -181,8 +181,9 @@ annotation_insert_error(struct annotation_info 
> *annotation, unsigned offset,
>   continue;
>
>if (offset + sizeof(brw_inst) != next->offset) {
> - memmove(next, cur,
> - (annotation->ann_count - i + 2) * sizeof(struct 
> annotation));
> + int count;
> + count = annotation->ann_count - i - 1;
> + memmove(next, cur, count * sizeof(struct annotation));

I don't see how this can be right.

Take for example a case where we have ann_count == 4. We have
annotation->ann[0..4] where ann[4] is the end marker... a little
surprising. We want to insert an error annotation on an instruction in
ann[2] but not at the end, so we need to split ann[2].

cur = 2, next = 3. We need to memmove elements 2, 3, 4 one spot later,
and then update ann[2] and ann[3] (which after the memmove is a copy
of ann[2]).

Count should be ann_count (4) - i (2) + 1 -> 3. The code currently
says +2 instead of +1 and that seems like a bug.

What do you think?
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Re: [Mesa-dev] [PATCH 09/10] spirv: Generate code to track SPIR-V capability dependencies

[Dylan Baker]

Quoting Ian Romanick (2017-11-10 14:32:49)
[snip]

> +
> +def collect_data(spirv):
> +for x in spirv["operand_kinds"]:
> +if x["kind"] == "Capability":
> +operands = x

This makes me nervous. dict iteration order is not guaranteed to be repeatable
in python. I think you should either use sorted() [for x in sorted(spirv...)],
or if there's only every going to be on case where x[kind] == capability use a
break statement and leave a comment.

> +
> +# There are some duplicate values in some of the tables (thanks guys!), 
> so
> +# filter them out.
> +
> +# by_value is a dictionary that maps values of enumerants to tuples of
> +# enumerant names and capabilities.
> +by_value = {}
> +
> +# by_name is a dictionary that maps names of enumerants to tuples of
> +# values and required capabilities.
> +by_name = {}
> +
> +for x in operands["enumerants"]:
> +caps = x["capabilities"] if "capabilities" in x else []

caps = x.get("capabilities", [])

> +
> +if x["value"] not in by_value:
> +by_value[x["value"]] = (x["enumerant"], caps)
> +
> +by_name[x["enumerant"]] = (x["value"], caps)
> +
> +# Recall that there are some duplicate values in the table.  These
> +# duplicate values also appear in the "capabilities" list for some
> +# enumerants.  Filter out the duplicates there as well.
> +for capability in by_name:
> +cap_value, dependencies = by_name[capability]
> +for dependency in dependencies:
> +dep_value, skip = by_name[dependency]
> +real_dependency, skip = by_value[dep_value]

I think you can simplify this somewhat:

for capability, (_, dependencies) in by_name.iteritems():
for dep_value, _ in dependencies.itervalues():
real_dependency, _ = by_value[dep_value]

> +
> +# In most cases where there is a duplicate capability, things 
> that
> +# depend on one will also depend on the others.
> +# StorageBuffer16BitAccess and StorageUniformBufferBlock16 have
> +# the same value, and StorageUniform16 depends on both.
> +#
> +# There are exceptions.  ShaderViewportIndexLayerEXT and
> +# ShaderViewportIndexLayerNV have the same value, but
> +# ShaderViewportMaskNV only depends on 
> ShaderViewportIndexLayerNV.
> +#
> +# That's the only case so far, so emit a warning for other cases
> +# that have more than one dependency.  That way we can double
> +# check that they are handled correctly.
> +
> +if real_dependency != dependency:
> +if real_dependency not in by_name[capability][1]:
> +if len(by_name[capability][1]) > 1:
> +print("Warning!  Removed {} from {}, but no name 
> with the same value is in the dependency list.".format(dependency, 
> capability))
> +else:
> +if len(by_name[capability][1]) == 1:
> +print("Error!  Cannot remove {} from {} because it 
> is the only dependency.".format(dependency, capability))

I think you want to add file=sys.stderr to the print command. (You might need to
import sys, I snipped that part of the patch already...)

> +exit(1)
> +
> +by_name[capability][1].remove(dependency)
> +
> +# The table generated from this data and the C code that uses it
> +# assumes that each capability has a single dependency.  That is
> +# currently the case, but it may change in the future.
> +if len(by_name[capability][1]) > 1:
> +print("Error!  Too many dependencies left for {}. 
> {}".format(capability, by_name[capability][1]))
> +exit(1)
> +
> +for cap_value in by_value:
> +name, skip = by_value[cap_value]
> +by_value[cap_value] = (name, by_name[name][1])
> +
> +return (by_name, by_value)
> +
> +TEMPLATE_H = Template(COPYRIGHT + """\
> +#ifndef SPIRV_CAPABILITIES_H
> +#define SPIRV_CAPABILITIES_H
> +
> +#include 
> +#include "spirv.h"
> +#include "util/bitset.h"
> +#ifndef ARRAY_SIZE
> +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
> +#endif
> +
> +#define NO_DEPENDENCY ((${"uint16_t" if len(all_values) > 256 else 
> "uint8_t"}) ~0)
> +
> +class spirv_capability_set;
> +
> +/**
> + * Iterator for the enabled capabilities in a spirv_capability_set
> + *
> + * Roughly, this is a wrapper for the bitset iterator functions.  
> Dereferencing
> + * the iterator results in the \c SpvCapability where as the bitset iterator
> + * functions provide the index in the bitset.  The mapping is handled by
> + * \c spirv_capability_set.
> + */
> +class spirv_capability_set_iterator {
> +public:
> +   spirv_capability_set_iterator(const spirv_capability_set *_s);
> +   inline bool operator==(const spirv_capability_set_iterator ) const;
> +   inline bool 

Re: [Mesa-dev] [PATCH 1/2] meson: Stop requiring platforms for Vulkan

[Emil Velikov]

On 13 November 2017 at 17:37, Dylan Baker  wrote:
> I believe I copied this from autotools, does it have the same restriction?
>
It doesn't. Some ~1 ago I was under the assumption you need one (hence
I sent a patch) but it got dropped.
Likely you saw that one fly-by, pardon for the confusion.

-Emil
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Re: [Mesa-dev] [PATCH 1/2] meson: Stop requiring platforms for Vulkan

[Dylan Baker]

I can't either, so:
Reviewed-by: Dylan Baker 

Quoting Jason Ekstrand (2017-11-13 09:43:11)
> My quick attempt at grepping configure.ac didn't turn anything up.
> 
> On Mon, Nov 13, 2017 at 9:37 AM, Dylan Baker  wrote:
> 
> I believe I copied this from autotools, does it have the same restriction?
> 
> Quoting Jason Ekstrand (2017-11-11 10:32:05)
> > It should be perfectly valid to build a completely headless Vulkan
>   river.  We don't need to require a platform.
> > ---
> >  meson.build | 3 ---
> >  1 file changed, 3 deletions(-)
> >
> > diff --git a/meson.build b/meson.build
> > index 1f6658b..e4d0e0f 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -306,9 +306,6 @@ if _vulkan_drivers != ''
> >    with_intel_vk = _split.contains('intel')
> >    with_amd_vk = _split.contains('amd')
> >    with_any_vk = with_amd_vk or with_intel_vk
> > -  if not (with_platform_x11 or with_platform_wayland or
> with_platform_android)
> > -    error('Vulkan requires at least one platform (x11, wayland, 
> android)
> ')
> > -  endif
> >  endif
> >
> >  with_dri2 = (with_dri or with_any_vk) and with_dri_platform == 'drm'
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> 


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Re: [Mesa-dev] [PATCH 18/18] intel/tools: add command line GEN shader disassembler tool

[Eric Engestrom]

On Monday, 2017-11-13 15:18:06 +0200, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin 
> 
> Signed-off-by: Kevin Rogovin 
> ---
>  src/intel/Makefile.tools.am   |  21 ++-
>  src/intel/tools/.gitignore|   1 +
>  src/intel/tools/gen_shader_disassembler.c | 221 
> ++
>  3 files changed, 242 insertions(+), 1 deletion(-)
>  create mode 100644 src/intel/tools/gen_shader_disassembler.c
> 
> diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
> index dd68d8f173..71eb3253c3 100644
> --- a/src/intel/Makefile.tools.am
> +++ b/src/intel/Makefile.tools.am
> @@ -32,7 +32,8 @@ intellib_LTLIBRARIES = \
>  
>  intelbin_PROGRAMS = tools/i965_batchbuffer_dump_show \
>   tools/i965_batchbuffer_dump_show_xml \
> - tools/i965_batchbuffer_dump_show_json
> + tools/i965_batchbuffer_dump_show_json \
> + tools/gen_shader_disassembler

Could you add these to src/intel/tools/meson.build as well?
Thanks :)

>  
>  intelbin_SCRIPTS = tools/i965_batchbuffer_logger_sh
>  CLEANFILES += $(intelbin_SCRIPTS)
> @@ -111,3 +112,21 @@ tools_i965_batchbuffer_dump_show_xml_SOURCES = \
>  
>  tools_i965_batchbuffer_dump_show_json_SOURCES = \
>   tools/i965_batchbuffer_dump_show_json.cpp
> +
> +tools_gen_shader_disassembler_SOURCES = \
> + tools/gen_shader_disassembler.c \
> + tools/disasm.c \
> + tools/gen_disasm.h
> +
> +tools_gen_shader_disassembler_LDADD = \
> + common/libintel_common.la \
> + compiler/libintel_compiler.la \
> + $(top_builddir)/src/util/libmesautil.la \
> + $(PTHREAD_LIBS) \
> + $(EXPAT_LIBS) \
> + $(ZLIB_LIBS)
> +
> +tools_gen_shader_disassembler_CFLAGS = \
> + $(AM_CFLAGS) \
> + $(EXPAT_CFLAGS) \
> + $(ZLIB_CFLAGS)
> diff --git a/src/intel/tools/.gitignore b/src/intel/tools/.gitignore
> index ea4dc23c20..e9b22c89aa 100644
> --- a/src/intel/tools/.gitignore
> +++ b/src/intel/tools/.gitignore
> @@ -4,3 +4,4 @@
>  /i965_batchbuffer_dump_show
>  /i965_batchbuffer_dump_show_xml
>  /i965_batchbuffer_dump_show_json
> +/gen_shader_disassembler
> diff --git a/src/intel/tools/gen_shader_disassembler.c 
> b/src/intel/tools/gen_shader_disassembler.c
> new file mode 100644
> index 00..bd6c400fcc
> --- /dev/null
> +++ b/src/intel/tools/gen_shader_disassembler.c
> @@ -0,0 +1,221 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "compiler/brw_inst.h"
> +#include "compiler/brw_eu.h"
> +
> +static
> +void
> +print_opcodes(const void *data, int data_sz,
> +  struct gen_device_info *devinfo,
> +  bool print_offsets)
> +{
> +   for (int offset = 0; offset < data_sz;) {
> +  const brw_inst *insn = data + offset;
> +  bool compacted;
> +  brw_inst uncompacted;
> +  enum opcode opcode;
> +  const struct opcode_desc *desc;
> +
> +  if (print_offsets) {
> + printf("0x%08x: ", offset);
> +  }
> +
> +  compacted = brw_inst_cmpt_control(devinfo, insn);
> +  if (compacted) {
> + brw_compact_inst *compacted_insn;
> + compacted_insn = (void*)insn;
> + brw_uncompact_instruction(devinfo, , compacted_insn);
> + insn = 
> + offset += 8;
> +  } else {
> + offset += 16;
> +  }
> +
> +  opcode = brw_inst_opcode(devinfo, insn);
> +  desc = brw_opcode_desc(devinfo, opcode);
> +  if (desc) {
> + printf("(0x%08x) %s", opcode, desc->name);
> +  } else {
> + printf("(0x%08x) UnknownOpcode", opcode);
> +  }
> +
> +  if (compacted) {
> + printf(" {Compacted}");
> +  }
> +
> +  printf("\n");
> +   }
> +}
> +
> +static
> +void
> 

Re: [Mesa-dev] [PATCH 0/8] i965: add performance query support for Coffeelake

[Kenneth Graunke]

On Monday, November 13, 2017 6:58:28 AM PST Lionel Landwerlin wrote:
> Hi,
> 
> Although the main point of this series is to add performance queries
> for Coffeelake. This series also brings the following :
> 
>  1. Fix a number of Media/VME counters
>  2. Rename some counter descriptions
>  3. Add userspace loading of config not already present
>  4. Add newer busyness configs (allowed by 3)
> 
> Cheers,
> 
> Lionel Landwerlin (8):
>   i965: perf: update configs for loading from userspace
>   i965: perf: add support for userspace configurations
>   i965: add a debug option to disable oa config loading
>   i965: perf: update counter names on gen8/9 platforms
>   i965: fix time elapsed counter equations in VME/Media configs
>   i965: perf: add busyness metric sets on gen8/9 platforms
>   i965: perf: add support for CoffeeLake GT2
>   i965: perf: add support for CoffeeLake GT3

Patches 2-3 are
Reviewed-by: Kenneth Graunke 

and the rest are
Acked-by: Kenneth Graunke 

because I have no idea where you get this information from, so I can't
really review it.  It all looks very reasonable, though.


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Re: [Mesa-dev] [PATCH 1/5] egl: Provide meaningfull error when built w/o requested platform

[Eric Engestrom]

On Monday, 2017-11-13 14:06:10 +, Emil Velikov wrote:
> From: Emil Velikov 
> 
> The current "No EGL platform enabled." is misleading and wrong.
> We reach said code when $platform is missing.
> 
> To make this more obvious and clear provide wrappers in the header
> file, making the code a bit easier to follow.
> 
> Signed-off-by: Emil Velikov 

Thanks for the cleanup :)
Series is:
Reviewed-by: Eric Engestrom 

> ---
>  src/egl/drivers/dri2/egl_dri2.c | 12 +---
>  src/egl/drivers/dri2/egl_dri2.h | 40 
>  2 files changed, 41 insertions(+), 11 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index 8861742c17f..af821425355 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -915,33 +915,23 @@ dri2_initialize(_EGLDriver *drv, _EGLDisplay *disp)
>return EGL_FALSE;
>  
> switch (disp->Platform) {
> -#ifdef HAVE_SURFACELESS_PLATFORM
> case _EGL_PLATFORM_SURFACELESS:
>ret = dri2_initialize_surfaceless(drv, disp);
>break;
> -#endif
> -#ifdef HAVE_X11_PLATFORM
> case _EGL_PLATFORM_X11:
>ret = dri2_initialize_x11(drv, disp);
>break;
> -#endif
> -#ifdef HAVE_DRM_PLATFORM
> case _EGL_PLATFORM_DRM:
>ret = dri2_initialize_drm(drv, disp);
>break;
> -#endif
> -#ifdef HAVE_WAYLAND_PLATFORM
> case _EGL_PLATFORM_WAYLAND:
>ret = dri2_initialize_wayland(drv, disp);
>break;
> -#endif
> -#ifdef HAVE_ANDROID_PLATFORM
> case _EGL_PLATFORM_ANDROID:
>ret = dri2_initialize_android(drv, disp);
>break;
> -#endif
> default:
> -  _eglLog(_EGL_WARNING, "No EGL platform enabled.");
> +  unreachable("Callers ensure we cannot get here.");
>return EGL_FALSE;
> }
>  
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index 0ec8f44dce2..9cccf05253a 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -400,20 +400,60 @@ _EGLImage *
>  dri2_create_image_dma_buf(_EGLDisplay *disp, _EGLContext *ctx,
>EGLClientBuffer buffer, const EGLint *attr_list);
>  
> +#ifdef HAVE_X11_PLATFORM
>  EGLBoolean
>  dri2_initialize_x11(_EGLDriver *drv, _EGLDisplay *disp);
> +#else
> +static inline EGLBoolean
> +dri2_initialize_x11(_EGLDriver *drv, _EGLDisplay *disp)
> +{
> +   return _eglError(EGL_NOT_INITIALIZED, "X11 platform not built");
> +}
> +#endif
>  
> +#ifdef HAVE_DRM_PLATFORM
>  EGLBoolean
>  dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp);
> +#else
> +static inline EGLBoolean
> +dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
> +{
> +   return _eglError(EGL_NOT_INITIALIZED, "GBM/DRM platform not built");
> +}
> +#endif
>  
> +#ifdef HAVE_WAYLAND_PLATFORM
>  EGLBoolean
>  dri2_initialize_wayland(_EGLDriver *drv, _EGLDisplay *disp);
> +#else
> +static inline EGLBoolean
> +dri2_initialize_wayland(_EGLDriver *drv, _EGLDisplay *disp)
> +{
> +   return _eglError(EGL_NOT_INITIALIZED, "Wayland platform not built");
> +}
> +#endif
>  
> +#ifdef HAVE_ANDROID_PLATFORM
>  EGLBoolean
>  dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp);
> +#else
> +static inline EGLBoolean
> +dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp)
> +{
> +   return _eglError(EGL_NOT_INITIALIZED, "Android platform not built");
> +}
> +#endif
>  
> +#ifdef HAVE_SURFACELESS_PLATFORM
>  EGLBoolean
>  dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay *disp);
> +#else
> +static inline EGLBoolean
> +dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay *disp)
> +{
> +   return _eglError(EGL_NOT_INITIALIZED, "Surfaceless platform not built");
> +}
> +#endif
>  
>  void
>  dri2_flush_drawable_for_swapbuffers(_EGLDisplay *disp, _EGLSurface *draw);
> -- 
> 2.15.0
> 
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