Re: [time-nuts] More on SiLabs 5340

2018-01-30 Thread Magnus Danielson
Hi,

On 01/31/2018 04:27 AM, John Miles wrote:
> 
>> -Original Message-
>> There is a small detail that puzzles me: the ADEV for the internal
>> reference 10MHz and 30MHz bends upwards at tau greater than 0.1s.
>> Shouldn't that be visible by a change in slope in the phase noise
>> plot at ~10Hz as well?
>>
>>  Attila Kinali
> 
> 
> Linear drift (which is what's happening here) has a bigger effect on the 
> overall gestalt of an ADEV plot than it will on a phase noise plot.  This is 
> because long-term drift looks similar to DC offset or noise at extremely low 
> frequencies, both of which are attenuated by an HPF stage prior to each FFT 
> segment.  But ADEV doesn't benefit from DC removal, and since it doesn't 
> converge in the presence of drift, you get the usual upturn in the trace at 
> increasing taus. 

As ADEV is defined, it is bound to be captured by linear, and higher
terms, drift. FFT is not directly, but on the other hand sensitive to DC
shifts that usually is handled by the window function, which also helps
to work on spectral purity. None of the measures is very perfect so they
need to be handled with care.

> When you see a highly-elevated noise trace at low offset frequencies, it's 
> also a good idea to check for glitches in the 'f' measurement view, although 
> in this case the L(f) spectrum is very typical of these sorts of parts. 

Glitches can totally ruin an ADEV.

Cheers,
Magnus
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Re: [time-nuts] More on SiLabs 5340

2018-01-30 Thread John Miles

> -Original Message-
> There is a small detail that puzzles me: the ADEV for the internal
> reference 10MHz and 30MHz bends upwards at tau greater than 0.1s.
> Shouldn't that be visible by a change in slope in the phase noise
> plot at ~10Hz as well?
> 
>   Attila Kinali


Linear drift (which is what's happening here) has a bigger effect on the 
overall gestalt of an ADEV plot than it will on a phase noise plot.  This is 
because long-term drift looks similar to DC offset or noise at extremely low 
frequencies, both of which are attenuated by an HPF stage prior to each FFT 
segment.  But ADEV doesn't benefit from DC removal, and since it doesn't 
converge in the presence of drift, you get the usual upturn in the trace at 
increasing taus. 

When you see a highly-elevated noise trace at low offset frequencies, it's also 
a good idea to check for glitches in the 'f' measurement view, although in this 
case the L(f) spectrum is very typical of these sorts of parts. 

-- john, KE5FX
Miles Design LLC


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Re: [time-nuts] More on SiLabs 5340

2018-01-30 Thread Attila Kinali
Moin,

On Mon, 29 Jan 2018 15:38:33 -0500
John Ackermann N8UR  wrote:

> Today I tried replacing the crystal with a 10 MHz input, and found that 
> the evaluation board requires surgery to support that.  What I was able 
> to do, though, was feed 10 MHz into the "Input 0" port which apparently 
> disciplines the free-running crystal.  I used a 10811A fed into a 
> T2-Mini with divider removed, so all it does is provide the Wenzel 
> squaring circuit.  Results attached, added to the plots from yesterday. 
> Also attached is an ADEV plot proving that the 10 MHz is in control.

There is a small detail that puzzles me: the ADEV for the internal
reference 10MHz and 30MHz bends upwards at tau greater than 0.1s.
Shouldn't that be visible by a change in slope in the phase noise
plot at ~10Hz as well?

Attila Kinali

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
 -- Miss Matheson, The Diamond Age, Neil Stephenson
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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread jimlux

On 1/29/18 3:37 PM, Mark Goldberg wrote:

Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat
Long)". There are many sets of register values that will get you the same
output frequency and the clock builder may not give you an optimal set for
phase noise and spurs. I created a spreadsheet to calculate other sets of
values and chose one that worked the best. I just did it through trial and
error of the different sets of values I came up with until I found one with
low spurs.




We've experienced that here with other PLL chips - For the ADF4108 
integer-N PLL, sometimes there's a big difference between R odd and R 
even (the R is the reference divisor in the fout = fin * (M*B+A)/R


So you wind up fooling around with various combinations of A, B, and R 
to get the spurs where you want them (or, more commonly, to move them 
from where you don't want them)


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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread Mark Goldberg
Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat
Long)". There are many sets of register values that will get you the same
output frequency and the clock builder may not give you an optimal set for
phase noise and spurs. I created a spreadsheet to calculate other sets of
values and chose one that worked the best. I just did it through trial and
error of the different sets of values I came up with until I found one with
low spurs.

73,

Mark
W7MLG

On Mon, Jan 29, 2018 at 4:16 PM, John Ackermann N8UR  wrote:

> On 01/29/2018 04:54 PM, Chris Caudle wrote:
>
>> On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:
>>
>>> The close-in phase noise is quite amazing, but the floor is much worse
>>> than in free-run mode.
>>>
>>
>> That phase noise plot doesn't look quite right, what PLL bandwidth did you
>> set?
>>
>
> Sorry for the earlier null reply.  I just used the settings that the
> ClockBuilder software came up with (which IIRC don't offer any choices
> about loop bandwidth in the "wizard").  I haven't yet dug into the register
> options, but I'm sure that there are ways to optimize.
>
> John
>
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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread John Ackermann N8UR

On 01/29/2018 04:54 PM, Chris Caudle wrote:

On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:

The close-in phase noise is quite amazing, but the floor is much worse
than in free-run mode.


That phase noise plot doesn't look quite right, what PLL bandwidth did you
set?


Sorry for the earlier null reply.  I just used the settings that the 
ClockBuilder software came up with (which IIRC don't offer any choices 
about loop bandwidth in the "wizard").  I haven't yet dug into the 
register options, but I'm sure that there are ways to optimize.


John
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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread John Ackermann N8UR


On Jan 29, 2018, 4:54 PM, at 4:54 PM, Chris Caudle  
wrote:
>On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:
>> The close-in phase noise is quite amazing, but the floor is much
>worse
>> than in free-run mode.
>
>That phase noise plot doesn't look quite right, what PLL bandwidth did
>you
>set?
>
>-- 
>Chris Caudle
>
>
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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread Chris Caudle
On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:
> The close-in phase noise is quite amazing, but the floor is much worse
> than in free-run mode.

That phase noise plot doesn't look quite right, what PLL bandwidth did you
set?

-- 
Chris Caudle


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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread Chris Caudle
On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:
> to do, though, was feed 10 MHz into the "Input 0" port which apparently
> disciplines the free-running crystal.

It doesn't discipline the crystal oscillator, the crystal oscillator is
multiplied up and used as the clock to run a DDS block.  The 10MHz signal
you input is the reference input to a digital PLL, and the output of the
PLL modifies the tuning word of the DDS.

In free run mode it works similarly, but the tuning word never changes,
the DDS control value is chosen based on assuming that the DDS clock is
running exactly at nominal frequency.

-- 
Chris Caudle


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Re: [time-nuts] More on SiLabs 5340

2018-01-29 Thread Bob kb8tq
Hi

There may be “tweaks” to get the noise shaping working better on the 10 MHz 
input. Some PLL
chips have pre-multipliers for the reference to improve things…. the magic 
apparently works better
with a fast input …(and yes, there are good reasons why)

Bob

> On Jan 29, 2018, at 3:38 PM, John Ackermann N8UR  wrote:
> 
> I'm slowly learning how these ultra-low-jitter clock generators work. 
> Yesterday I posted some phase noise results in "free run" mode where the 48 
> MHz crystal on the evaluation board was the only reference.
> 
> Today I tried replacing the crystal with a 10 MHz input, and found that the 
> evaluation board requires surgery to support that.  What I was able to do, 
> though, was feed 10 MHz into the "Input 0" port which apparently disciplines 
> the free-running crystal.  I used a 10811A fed into a T2-Mini with divider 
> removed, so all it does is provide the Wenzel squaring circuit.  Results 
> attached, added to the plots from yesterday. Also attached is an ADEV plot 
> proving that the 10 MHz is in control.
> 
> The close-in phase noise is quite amazing, but the floor is much worse than 
> in free-run mode.  This was a very hay-wire experiment, so there are lots of 
> things that could be suboptimal.  It sure would be nice to get the best of 
> both those plots!
> 
> John
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