Re: [time-nuts] Questions about TAC frontend, and some measurements
Attila Kinali wrote: On Sun, 23 Dec 2012 22:45:40 +0100 Fabio Ebolifabi...@quipo.it wrote: Il 2012-12-23 07:42 Bruce Griffiths ha scritto: The classic TAC using current mode switching is similar to the attached circuit schematic. http://pastebin.com/EkgqmgfE I have a couple of small questions about this circuit. Why are Q2 and Q13 driven by Vth? As there are inverted versions of the Discharge and Ramp signals available, wouldn't it make sense to use those to drive Q2 and Q13? I guess it would enhance switching speed. Only if the 2 complementary signals have closely matching propagation delays. This is usually true with ECL logic but not necessarily true with CMOS logic. Also the reverse emitter base breakdown voltage of faster transistors will be exceeded with 10V pp differential drive. What is the reason behind the emitter followers Q1 and Q9? Respecitvely, why shouldnt R3/R4, R7/R8 be connected directly to V+/V-? Avoidance of saturation and ensuring sufficent headroom for the current sources/sinks. Is there a special reson why the current source around Q9 is set to 20mA and the one around Q4 to 10mA? Is it because Q14/Q15 are driven by a 20mA current source while Q18/Q19 by a 10mA source? No special reason although if the long tailed pair driving a subsequent longtailed pair has a significantly lower tail current than the driven pair the second pair will switch more slowly. Am i correct, that the only current source whos value really matters is the one around Q11? If so, wouldn't it be beneficial to use a stable reference voltage (probably coupled with the ADC reference) to be used in an opamp based current source against GND or V- and a current mirror (cascode or wilson) to drive Q18/Q19 (while leaving the other LED based current sources as they are, including Q16)? Ideally the discharge switch current source should equal twice the charge switch current source to ensure equal currents (and ideally equal voltage drops across) in the clamp diodes when the ramp capacitor is fully discharged.. A mirror uses extra matched transistors that can be avoided if an opamp and reference is used to replace the LED's together with resistor isolated feedback from the current source emitter. The ADC reference isn't always accessible particularly with an ADC embedded within a microprocessor. Attila Kinali Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
On Sun, 23 Dec 2012 22:45:40 +0100 Fabio Eboli fabi...@quipo.it wrote: Il 2012-12-23 07:42 Bruce Griffiths ha scritto: The classic TAC using current mode switching is similar to the attached circuit schematic. http://pastebin.com/EkgqmgfE I have a couple of small questions about this circuit. Why are Q2 and Q13 driven by Vth? As there are inverted versions of the Discharge and Ramp signals available, wouldn't it make sense to use those to drive Q2 and Q13? I guess it would enhance switching speed. What is the reason behind the emitter followers Q1 and Q9? Respecitvely, why shouldnt R3/R4, R7/R8 be connected directly to V+/V-? Is there a special reson why the current source around Q9 is set to 20mA and the one around Q4 to 10mA? Is it because Q14/Q15 are driven by a 20mA current source while Q18/Q19 by a 10mA source? Am i correct, that the only current source whos value really matters is the one around Q11? If so, wouldn't it be beneficial to use a stable reference voltage (probably coupled with the ADC reference) to be used in an opamp based current source against GND or V- and a current mirror (cascode or wilson) to drive Q18/Q19 (while leaving the other LED based current sources as they are, including Q16)? Attila Kinali -- There is no secret ingredient -- Po, Kung Fu Panda ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
On Thu, 3 Jan 2013 21:28:17 +0100 Attila Kinali att...@kinali.ch wrote: What is the reason behind the emitter followers Q1 and Q9? Respecitvely, why shouldnt R3/R4, R7/R8 be connected directly to V+/V-? Scratch that question. Looking at the schematics again, it became obvious. Attila Kinali -- There is no secret ingredient -- Po, Kung Fu Panda ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hello, hope you all had a happy Christmas. Back to the topic. Bob Camp asked: Hi One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that…. Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about can't get a 2 ns pulse through it goes away. I'm not suggesting you tear up what you have. It's just something else to try and compare Bob Bob, are you hinting to something like the last mail from Bruce? I.e. to use a tristate buffer to charge the capacitor? If not can you explicit what are you thinking? :) Thanks also to Alan Melia and Tom Miller for the details about bjt saturation . Bruce, about the tempco of the current generators, There is the led in series with a BE junction. The blue leds should have a tempco in mV per °C similar to th BE junction, dont know the red ones. Would it be better to use something like a 4.7 or 5.1V zener? If I remember correctly these zener voltage shuld cancel most of the BE tempco. And what about a TL431 instead of the led+bjt? The Avago diodes are pretty costly :) Is that circuit working like the internals of ECL logic families? The simplest (lowest part count and least number of power supplies) consists of a tristate buffer driving an RC circuit. The PPS signal is connected directly to the buffer input whilst the output of the PPS synchroniser (at least 2 stages to minimise the probability of metastabilty at the synchroniser output) drives the buffer tristate control input. A 2 stage syncronizer is composed of 3 FF? I.e. clock in parallel to 3 FF, PPS to the first D, Q from the first to D of the second, same from the second to the thid, and Q from the third to out. Let's assume that the inputs from PPS and 10MHz are fast enough, what can still generate metastability? Setup time violation? The RC network starts charging when the PPS signal goes high and stops when the synchroniser output goes high. The capacitor charging is nonlinear but this is easily corrected in software. The capacitor is connected between the input of a capacitive charge redistribution ADC and ground. Software correction for the effect of charging the charge ADC input capacitance is also required. I see you are stressing the fact of using a capacitive charge redistribution adc. I dont know much about the internals of the ADC devices, can you suggest a partnumber for an example? Suitable fast single gate tristate drives are readily available. With low tempco resistors and capacitors the TAC gain tempco can be 200pmm/C or less. The only disadvantages are the increased software complexity and the need for an extra bit of ADC resolution to maintain TAC resolution. The 3-state buffer + R-C seem an elegant solution for a microcontroller based thing, I'v given an eye to logic buffers, and seem that all suggest that the Hi-Z state leackage current is not very well specified, but something around 1uA, that means that cap's voltage after the pulse can rapidly (and unpredictabily?)change due to leackage. I imagine also that the leackage of the buffer will vary with temperature. The ADC of the micro is pretty fast, I shuld check the datasheet but I remember around 1uS per conversion, what would happen connecting directly the micro ADC to the charged cap? And sync the ADC to sample immediately (few uS) after the pulse. Could the loading from the s/h capacitance be corrected in fw? Bruce By the way, I updated my miserable schematic, I tried a simple mod to avoid the saturation of the switches. Only because I had it already built: http://pastebin.com/9VHkhmSv Now I'm chasing the origin of the drift variation, logging the temperatures and voltages. More on this as soon as I have some data. Thank you all, Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi You should check out the leakage of a typical tristate buffer. It's specified at a level that makes it easy to test. Most of the parts you find have very low leakage. Varicap diodes are similar in that respect, the leakage of real parts is much lower than the 1 ua you see on the old specs. The likely qualifier on all that is at room temperature. I'm sure the leakage goes a bit nuts as the parts get to 125C. Bob On Dec 26, 2012, at 5:26 AM, Fabio Eboli fabi...@quipo.it wrote: Hello, hope you all had a happy Christmas. Back to the topic. Bob Camp asked: Hi One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that…. Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about can't get a 2 ns pulse through it goes away. I'm not suggesting you tear up what you have. It's just something else to try and compare Bob Bob, are you hinting to something like the last mail from Bruce? I.e. to use a tristate buffer to charge the capacitor? If not can you explicit what are you thinking? :) Thanks also to Alan Melia and Tom Miller for the details about bjt saturation . Bruce, about the tempco of the current generators, There is the led in series with a BE junction. The blue leds should have a tempco in mV per °C similar to th BE junction, dont know the red ones. Would it be better to use something like a 4.7 or 5.1V zener? If I remember correctly these zener voltage shuld cancel most of the BE tempco. And what about a TL431 instead of the led+bjt? The Avago diodes are pretty costly :) Is that circuit working like the internals of ECL logic families? The simplest (lowest part count and least number of power supplies) consists of a tristate buffer driving an RC circuit. The PPS signal is connected directly to the buffer input whilst the output of the PPS synchroniser (at least 2 stages to minimise the probability of metastabilty at the synchroniser output) drives the buffer tristate control input. A 2 stage syncronizer is composed of 3 FF? I.e. clock in parallel to 3 FF, PPS to the first D, Q from the first to D of the second, same from the second to the thid, and Q from the third to out. Let's assume that the inputs from PPS and 10MHz are fast enough, what can still generate metastability? Setup time violation? The RC network starts charging when the PPS signal goes high and stops when the synchroniser output goes high. The capacitor charging is nonlinear but this is easily corrected in software. The capacitor is connected between the input of a capacitive charge redistribution ADC and ground. Software correction for the effect of charging the charge ADC input capacitance is also required. I see you are stressing the fact of using a capacitive charge redistribution adc. I dont know much about the internals of the ADC devices, can you suggest a partnumber for an example? Suitable fast single gate tristate drives are readily available. With low tempco resistors and capacitors the TAC gain tempco can be 200pmm/C or less. The only disadvantages are the increased software complexity and the need for an extra bit of ADC resolution to maintain TAC resolution. The 3-state buffer + R-C seem an elegant solution for a microcontroller based thing, I'v given an eye to logic buffers, and seem that all suggest that the Hi-Z state leackage current is not very well specified, but something around 1uA, that means that cap's voltage after the pulse can rapidly (and unpredictabily?)change due to leackage. I imagine also that the leackage of the buffer will vary with temperature. The ADC of the micro is pretty fast, I shuld check the datasheet but I remember around 1uS per conversion, what would happen connecting directly the micro ADC to the charged cap? And sync the ADC to sample immediately (few uS) after the pulse. Could the loading from the s/h capacitance be corrected in fw? Bruce By the way, I updated my miserable schematic, I tried a simple mod to avoid the saturation of the switches. Only because I had it already built: http://pastebin.com/9VHkhmSv Now I'm chasing the origin of the drift variation, logging the temperatures and voltages. More on this as soon as I have some data. Thank you all, Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Fabio Eboli wrote: Hello, hope you all had a happy Christmas. Back to the topic. Bob Camp asked: Hi One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that…. Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about can't get a 2 ns pulse through it goes away. I'm not suggesting you tear up what you have. It's just something else to try and compare Bob Bob, are you hinting to something like the last mail from Bruce? I.e. to use a tristate buffer to charge the capacitor? If not can you explicit what are you thinking? :) Thanks also to Alan Melia and Tom Miller for the details about bjt saturation . Bruce, about the tempco of the current generators, There is the led in series with a BE junction. The blue leds should have a tempco in mV per °C similar to th BE junction, dont know the red ones. Similar. Would it be better to use something like a 4.7 or 5.1V zener? If I remember correctly these zener voltage shuld cancel most of the BE tempco. And what about a TL431 instead of the led+bjt? The BJT is essential to ensure that the current source has a high output impedance. Opamps dont help as most have insufficient gain at high frequencies. The input capacitance of an opamp input connected directly to the current source emitter isnt conducive to a high output impedance either. Its better to drive the emitter of the second transistor with an npn emitter follower thats part of a servo loop using a suitably decoupled opamp (series resistor from the current source emitter to the inverting input of the opamp) to set the emitter current of the current source transistor. The Avago diodes are pretty costly :) Is that circuit working like the internals of ECL logic families? Yes apart from the lack of emitter follower outputs. Its called current mode logic. The simplest (lowest part count and least number of power supplies) consists of a tristate buffer driving an RC circuit. The PPS signal is connected directly to the buffer input whilst the output of the PPS synchroniser (at least 2 stages to minimise the probability of metastabilty at the synchroniser output) drives the buffer tristate control input. A 2 stage syncronizer is composed of 3 FF? No 2 FF, the first FF is just a convenient means of stretching narrow pulses and ensuring that the synchroniser input pulse width has the required duration. I.e. clock in parallel to 3 FF, PPS to the first D, Q from the first to D of the second, same from the second to the thid, and Q from the third to out. Let's assume that the inputs from PPS and 10MHz are fast enough, what can still generate metastability? Setup time violation? The RC network starts charging when the PPS signal goes high and stops when the synchroniser output goes high. The capacitor charging is nonlinear but this is easily corrected in software. The capacitor is connected between the input of a capacitive charge redistribution ADC and ground. Software correction for the effect of charging the charge ADC input capacitance is also required. I see you are stressing the fact of using a capacitive charge redistribution adc. I dont know much about the internals of the ADC devices, can you suggest a partnumber for an example? Almost any modern SAR ADC such as the LTC1282 and later. Suitable fast single gate tristate drives are readily available. With low tempco resistors and capacitors the TAC gain tempco can be 200pmm/C or less. The only disadvantages are the increased software complexity and the need for an extra bit of ADC resolution to maintain TAC resolution. The 3-state buffer + R-C seem an elegant solution for a microcontroller based thing, I'v given an eye to logic buffers, and seem that all suggest that the Hi-Z state leackage current is not very well specified, but something around 1uA, that means that cap's voltage after the pulse can rapidly (and unpredictabily?)change due to leackage. I imagine also that the leackage of the buffer will vary with temperature. Kasper Pedersen has used this technique. http://n1.taur.dk/gpsdo2a.pdf However he only used a single stage synchroniser which is far from ideal. The ADC of the micro is pretty fast, I shuld check the datasheet but I remember around 1uS per conversion, what would happen connecting directly the micro ADC to the charged cap? And sync the ADC to sample immediately (few uS) after the pulse. Could the loading from the s/h capacitance be corrected in fw? The best way is to have the ADC in sample mode whilst the capacitor is being charged. Wait sufficient time at the end of the charging process for the ADC sampler to settle and then trigger a conversion. If possible, its best for this conversion trigger to be generated by the synchroniser (use a shift register 1st 2 stages for the synchroniser prper and the following stages used to generate the required delay. The effect of the sampling capacitance can be
Re: [time-nuts] Questions about TAC frontend, and some measurements
Fabio The simplest (lowest part count and least number of power supplies) consists of a tristate buffer driving an RC circuit. The PPS signal is connected directly to the buffer input whilst the output of the PPS synchroniser (at least 2 stages to minimise the probability of metastabilty at the synchroniser output) drives the buffer tristate control input. The RC network starts charging when the PPS signal goes high and stops when the synchroniser output goes high. The capacitor charging is nonlinear but this is easily corrected in software. The capacitor is connected between the input of a capacitive charge redistribution ADC and ground. Software correction for the effect of charging the charge ADC input capacitance is also required. Suitable fast single gate tristate drives are readily available. With low tempco resistors and capacitors the TAC gain tempco can be 200pmm/C or less. The only disadvantages are the increased software complexity and the need for an extra bit of ADC resolution to maintain TAC resolution. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Fabio Eboli wrote: Il 2012-12-23 07:42 Bruce Griffiths ha scritto: The classic TAC using current mode switching is similar to the attached circuit schematic. Bruce I tried to replicate the circuit you attached, the pic was low resolution so I tried to figure the values. This is the circuit asc text http://pastebin.com/EkgqmgfE If you have time please check it, and tell me the errors, thanks. *I wish to all the members of the list a happy Christmas* Fabio. Fabio The capacitance of the BAT46 diodes is too large to be particularly useful. HSMS282x series diodes from Avago are a better choice. I can send you a Spice model for these if you want. This model can easily be added to the LTSpice diode collection. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Fabio Eboli wrote: Il 2012-12-23 11:36 Bruce Griffiths ha scritto: The simulation indicates that the TAC capacitor charging current is far from constant whilst charging. This is due to the use of saturated switches rather than current steering switches. The capacitor charging current is poorly controlled. So in this respect your circuit fails miserably. So if I'm understanding correctly, the non linearity is due to the uncontrolled current flowing from the collectors to the bases of saturated transistors, that changes the magnitude of charging current in uncontrolled way. I was trying to use a sungle supply, but now I'm starting to see the limits of my implementations. Fabio. Corrections: R6 = 250 ohm R14 = 125 ohm R10 = 250 ohm R5 = 250 ohm R2 = 2k ohm The current source tempco is around 2000ppm/C This can be reduced to about 100ppm/C (limited by hfe tempco of the transistors) by replacing the LEDS with emitter followers the base of which is driven by an opamp. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Fabio Eboli wrote: Hello, Bruce Using saturated transistors as switches in the current source and elsewhere isn't conducive to fast switching. The traditional arrangement using current mode switches is much faster and more predictable. This is something I'd like to understand better. I'm referring to this schematic here: http://www.flickr.com/photos/14336723@N08/8293076065/ Q2 and Q5 are saturating toward the end of the ramp pulse, when the ramp capacitor C1 starts to go up. I was prepared to see the circuit I designed fail miserably on switch time, but it seem to be working, as far as I could see on the DSO. As far I can understand, the fact that Q2 and Q6 don't saturate, saves the circuit, since at the end of the ramp, when Q1 and Q5 are into saturation, Q6 is able to steer the current to ground, and reverse bias BE (and CB) of Q5. Is this correct, or I was only lucky with the specific parts I used? The simulation indicates that the TAC capacitor charging current is far from constant whilst charging. This is due to the use of saturated switches rather than current steering switches. The capacitor charging current is poorly controlled. So in this respect your circuit fails miserably. bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Il 2012-12-23 11:36 Bruce Griffiths ha scritto: The simulation indicates that the TAC capacitor charging current is far from constant whilst charging. This is due to the use of saturated switches rather than current steering switches. The capacitor charging current is poorly controlled. So in this respect your circuit fails miserably. So if I'm understanding correctly, the non linearity is due to the uncontrolled current flowing from the collectors to the bases of saturated transistors, that changes the magnitude of charging current in uncontrolled way. I was trying to use a sungle supply, but now I'm starting to see the limits of my implementations. Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Il 2012-12-23 07:42 Bruce Griffiths ha scritto: The classic TAC using current mode switching is similar to the attached circuit schematic. Bruce I tried to replicate the circuit you attached, the pic was low resolution so I tried to figure the values. This is the circuit asc text http://pastebin.com/EkgqmgfE If you have time please check it, and tell me the errors, thanks. *I wish to all the members of the list a happy Christmas* Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
I answer here to Bob Bill and Magnus. Hi I think I would grab some sort of USB thermometer and start logging the room temperature. CMOS input op-amps are a pretty good way to buffer the integrating capacitor. They are cheap and have very low bias currents. Bob The suspect is temperature, the first thing I'm suspecting is the FE5680A temp coefficient. I didnt grasp the real numbers, so I tried estimating the local drift, i.e. the drift value every 2k samples. Here the results: http://www.flickr.com/photos/14336723@N08/8296002061/ The drift stays around -3.2x10^-10 then abruptly goes to -2.4x10^-10, so if the culprit is the 5680, it's frequency should change about 1x10^-10, if I didnt screw up all the calculations. Does this make sense? As for the buffer opamp, I will try with MCP6001, cheap and it's input impedance is so high I will be limited by the pcb... By the way, my LM358 seem to be injecting 1.5nA into the ramp capacitor until it levels to around 1-1.5V. Like Bob said, start logging the temperature. Since you have about 86400 s period on this behaviour, I expect that heating up in the morning (sun or just habits of humans roughly aligned with sun patterns) be the reason, so this would be temperature dependent. Plotting supply voltage may be another reason. Magnus, I will log some temperatures and voltages. scope probe set to 10x, DC coupled. Do you really get 1-2 cycle long difference measures that way? You risk a high non-linearity at the small difference side otherwise, as it takes time to wake the transistors. ... As I commented, you might want 1-2 cycles to pass, so adding a second DFF might be needed for that task. So if I'm understanding you are suggesting to measure on the second 10MHz edge, instead of the first, I would have 100 to 200nS instead of 0 to 100nS. I didnt think about this, I like the idea! Like that you try your interpolator wings! Sorry, I didnt undestand this part. I do recommend you to check out the Wenzel clock input stage, which is being deployed in the TADD-2 divider. Squares up sine clocks nicely. Cheers, Magnus Hi Fabio, I am not crazy about your 10 MHz input circuit. You might want to consider investigating John Miles input arrangement at the following web site: http://www.ke5fx.com/ac.htm I used it to drive an input to a divider chip without the output resistor or capacitor. BillWB6BNQ Magnus and Bill, the input stage I'm using was inspired by the wenzel second schematic on this page: http://www.wenzel.com/documents/waveform.html But you both are right, I'm starting to see that it's not that stable. I will try the discrete solution on the wenzel page. Is the transformer mandatory or I can avoid it? In case I have some IF-cans but I've never used and dont know much about them. Thank you all, Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi It is often harder to measure a pulse that goes from 0 to 100 ns than it is to measure one that goes from 100 to 200 ns. The resolution on the 0 to 100 measure will be 2X, but the non-linearities at zero are quite difficult to deal with. The 100 to 200 measure can get to the same resolution with some analog tricks. If you are running into an ADC, the resolution may already be good enough. There may be no benefit from making it 2X better. For the measurement you are trying to do, 0.1 ns is probably good enough. A 10 bit ADC would do that at 100 ns span. A 12 bit ADC would do it at a 200 ns span. Bob On Dec 22, 2012, at 8:34 AM, fabi...@quipo.it wrote: I answer here to Bob Bill and Magnus. Hi I think I would grab some sort of USB thermometer and start logging the room temperature. CMOS input op-amps are a pretty good way to buffer the integrating capacitor. They are cheap and have very low bias currents. Bob The suspect is temperature, the first thing I'm suspecting is the FE5680A temp coefficient. I didnt grasp the real numbers, so I tried estimating the local drift, i.e. the drift value every 2k samples. Here the results: http://www.flickr.com/photos/14336723@N08/8296002061/ The drift stays around -3.2x10^-10 then abruptly goes to -2.4x10^-10, so if the culprit is the 5680, it's frequency should change about 1x10^-10, if I didnt screw up all the calculations. Does this make sense? As for the buffer opamp, I will try with MCP6001, cheap and it's input impedance is so high I will be limited by the pcb... By the way, my LM358 seem to be injecting 1.5nA into the ramp capacitor until it levels to around 1-1.5V. Like Bob said, start logging the temperature. Since you have about 86400 s period on this behaviour, I expect that heating up in the morning (sun or just habits of humans roughly aligned with sun patterns) be the reason, so this would be temperature dependent. Plotting supply voltage may be another reason. Magnus, I will log some temperatures and voltages. scope probe set to 10x, DC coupled. Do you really get 1-2 cycle long difference measures that way? You risk a high non-linearity at the small difference side otherwise, as it takes time to wake the transistors. ... As I commented, you might want 1-2 cycles to pass, so adding a second DFF might be needed for that task. So if I'm understanding you are suggesting to measure on the second 10MHz edge, instead of the first, I would have 100 to 200nS instead of 0 to 100nS. I didnt think about this, I like the idea! Like that you try your interpolator wings! Sorry, I didnt undestand this part. I do recommend you to check out the Wenzel clock input stage, which is being deployed in the TADD-2 divider. Squares up sine clocks nicely. Cheers, Magnus Hi Fabio, I am not crazy about your 10 MHz input circuit. You might want to consider investigating John Miles input arrangement at the following web site: http://www.ke5fx.com/ac.htm I used it to drive an input to a divider chip without the output resistor or capacitor. BillWB6BNQ Magnus and Bill, the input stage I'm using was inspired by the wenzel second schematic on this page: http://www.wenzel.com/documents/waveform.html But you both are right, I'm starting to see that it's not that stable. I will try the discrete solution on the wenzel page. Is the transformer mandatory or I can avoid it? In case I have some IF-cans but I've never used and dont know much about them. Thank you all, Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Dear Fabio, On 12/22/2012 02:34 PM, fabi...@quipo.it wrote: I answer here to Bob Bill and Magnus. Hi I think I would grab some sort of USB thermometer and start logging the room temperature. CMOS input op-amps are a pretty good way to buffer the integrating capacitor. They are cheap and have very low bias currents. Bob The suspect is temperature, the first thing I'm suspecting is the FE5680A temp coefficient. When it comes to phase, your interpolator may also be sensitive. I didnt grasp the real numbers, so I tried estimating the local drift, i.e. the drift value every 2k samples. Here the results: http://www.flickr.com/photos/14336723@N08/8296002061/ The drift stays around -3.2x10^-10 then abruptly goes to -2.4x10^-10, so if the culprit is the 5680, it's frequency should change about 1x10^-10, if I didnt screw up all the calculations. Does this make sense? Sounds a bit on the high side. As for the buffer opamp, I will try with MCP6001, cheap and it's input impedance is so high I will be limited by the pcb... By the way, my LM358 seem to be injecting 1.5nA into the ramp capacitor until it levels to around 1-1.5V. Like Bob said, start logging the temperature. Since you have about 86400 s period on this behaviour, I expect that heating up in the morning (sun or just habits of humans roughly aligned with sun patterns) be the reason, so this would be temperature dependent. Plotting supply voltage may be another reason. Magnus, I will log some temperatures and voltages. Goodie. scope probe set to 10x, DC coupled. Do you really get 1-2 cycle long difference measures that way? You risk a high non-linearity at the small difference side otherwise, as it takes time to wake the transistors. ... As I commented, you might want 1-2 cycles to pass, so adding a second DFF might be needed for that task. So if I'm understanding you are suggesting to measure on the second 10MHz edge, instead of the first, I would have 100 to 200nS instead of 0 to 100nS. I didnt think about this, I like the idea! Indeed. Some even let one more edge go and measure between 200 and 300 ns. Like that you try your interpolator wings! Sorry, I didnt undestand this part. Trivial, I like that you experiment and build your own interpolator design, build experience. I do recommend you to check out the Wenzel clock input stage, which is being deployed in the TADD-2 divider. Squares up sine clocks nicely. Cheers, Magnus Hi Fabio, I am not crazy about your 10 MHz input circuit. You might want to consider investigating John Miles input arrangement at the following web site: http://www.ke5fx.com/ac.htm I used it to drive an input to a divider chip without the output resistor or capacitor. BillWB6BNQ Magnus and Bill, the input stage I'm using was inspired by the wenzel second schematic on this page: http://www.wenzel.com/documents/waveform.html But you both are right, I'm starting to see that it's not that stable. I will try the discrete solution on the wenzel page. Good. It amplifies up the clock so that you will have low jitter. Is the transformer mandatory or I can avoid it? You can avoid it, just make sure that you get the transistors properly biased, so DC blocking cap and some resistors. In case I have some IF-cans but I've never used and dont know much about them. It's relative benign transistors being used. Good luck and look forward to your progress reports. You got me inspired to try something myself. :) Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Magnus Danielson wrote: Dear Fabio, On 12/22/2012 02:34 PM, fabi...@quipo.it wrote: I answer here to Bob Bill and Magnus. Hi I think I would grab some sort of USB thermometer and start logging the room temperature. CMOS input op-amps are a pretty good way to buffer the integrating capacitor. They are cheap and have very low bias currents. Bob The suspect is temperature, the first thing I'm suspecting is the FE5680A temp coefficient. When it comes to phase, your interpolator may also be sensitive. I didnt grasp the real numbers, so I tried estimating the local drift, i.e. the drift value every 2k samples. Here the results: http://www.flickr.com/photos/14336723@N08/8296002061/ The drift stays around -3.2x10^-10 then abruptly goes to -2.4x10^-10, so if the culprit is the 5680, it's frequency should change about 1x10^-10, if I didnt screw up all the calculations. Does this make sense? Sounds a bit on the high side. As for the buffer opamp, I will try with MCP6001, cheap and it's input impedance is so high I will be limited by the pcb... By the way, my LM358 seem to be injecting 1.5nA into the ramp capacitor until it levels to around 1-1.5V. Like Bob said, start logging the temperature. Since you have about 86400 s period on this behaviour, I expect that heating up in the morning (sun or just habits of humans roughly aligned with sun patterns) be the reason, so this would be temperature dependent. Plotting supply voltage may be another reason. Magnus, I will log some temperatures and voltages. Goodie. scope probe set to 10x, DC coupled. Do you really get 1-2 cycle long difference measures that way? You risk a high non-linearity at the small difference side otherwise, as it takes time to wake the transistors. ... As I commented, you might want 1-2 cycles to pass, so adding a second DFF might be needed for that task. So if I'm understanding you are suggesting to measure on the second 10MHz edge, instead of the first, I would have 100 to 200nS instead of 0 to 100nS. I didnt think about this, I like the idea! Indeed. Some even let one more edge go and measure between 200 and 300 ns. Like that you try your interpolator wings! Sorry, I didnt undestand this part. Trivial, I like that you experiment and build your own interpolator design, build experience. I do recommend you to check out the Wenzel clock input stage, which is being deployed in the TADD-2 divider. Squares up sine clocks nicely. Cheers, Magnus Hi Fabio, I am not crazy about your 10 MHz input circuit. You might want to consider investigating John Miles input arrangement at the following web site: http://www.ke5fx.com/ac.htm I used it to drive an input to a divider chip without the output resistor or capacitor. BillWB6BNQ Magnus and Bill, the input stage I'm using was inspired by the wenzel second schematic on this page: http://www.wenzel.com/documents/waveform.html But you both are right, I'm starting to see that it's not that stable. I will try the discrete solution on the wenzel page. Good. It amplifies up the clock so that you will have low jitter. Is the transformer mandatory or I can avoid it? You can avoid it, just make sure that you get the transistors properly biased, so DC blocking cap and some resistors. In case I have some IF-cans but I've never used and dont know much about them. It's relative benign transistors being used. Good luck and look forward to your progress reports. You got me inspired to try something myself. :) Cheers, Magnus Using saturated transistors as switches in the current source and elsewhere isn't conducive to fast switching. The traditional arrangement using current mode switches is much faster and more predictable. Buffering the ramp with an opamp requires that the opamp settling time be known so that the opamp has fully settled before a sample is taken. With a charge redistribution ADC that has a sampling switch connected to a capacitor array a buffer isnt usually necessary. Bruce Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
When it comes to phase, your interpolator may also be sensitive. Dont know if I was clear enough, just in case I wasnt able to explain well before: the data I collected didnt came from the analog interpolator, but from the OutD that is a digital out. The interpolator is still in it's infancy. So if I'm understanding you are suggesting to measure on the second 10MHz edge, instead of the first, I would have 100 to 200nS instead of 0 to 100nS. I didnt think about this, I like the idea! Indeed. Some even let one more edge go and measure between 200 and 300 ns. I modified the schematic this way to use the second edge: http://www.flickr.com/photos/14336723@N08/8297438155/ Like that you try your interpolator wings! Sorry, I didnt undestand this part. Trivial, I like that you experiment and build your own interpolator design, build experience. Thanks, I like to experiment directly when I can. This puts me in front of the real problems. And by the way playing with the interpolator is something that I'm enjoing; that few transistors are making something that was sort of magic for me before: converting nanoseconds pulses in something that can be easily read. In this work I'm only starting and I'm already on the edge of my little knowledge on electronics, and I'm learning much from the resources and contributors to this list. Good luck and look forward to your progress reports. I will happily keep sharing the work. You got me inspired to try something myself. :) Wow :) Thank you, Fabio. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hello, Bruce Using saturated transistors as switches in the current source and elsewhere isn't conducive to fast switching. The traditional arrangement using current mode switches is much faster and more predictable. This is something I'd like to understand better. I'm referring to this schematic here: http://www.flickr.com/photos/14336723@N08/8293076065/ Q2 and Q5 are saturating toward the end of the ramp pulse, when the ramp capacitor C1 starts to go up. I was prepared to see the circuit I designed fail miserably on switch time, but it seem to be working, as far as I could see on the DSO. As far I can understand, the fact that Q2 and Q6 don't saturate, saves the circuit, since at the end of the ramp, when Q1 and Q5 are into saturation, Q6 is able to steer the current to ground, and reverse bias BE (and CB) of Q5. Is this correct, or I was only lucky with the specific parts I used? Buffering the ramp with an opamp requires that the opamp settling time be known so that the opamp has fully settled before a sample is taken. With a charge redistribution ADC that has a sampling switch connected to a capacitor array a buffer isnt usually necessary. Bruce I was planning to read the voltage with a microcontroller's ADC. I will set a fixed delay from the PPS rising edge and start sampling there. To do so I need that the voltage on integrating capacitor to stay reasonably stable during the delay. Fabio ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi Fabio taking BJTs deep into saturation stores a lot of charge in the collector base capacitance. this must br discharged before a state change can occur. LSTTL gets round this and gets the speed at lower currents by clamping the collector to only just in saturation with a schottky diode between base and collector. Higher speeds are obtained with a long-tail pair like configuration, which switches (diverts) the current flow between left and right transistors for the two logic states. The current and power dissipation is high but speeds 10 times saturated logic are obtainable. see ECL, MECL, or PECL logic family schematics. Alan G3NYK - Original Message - From: Fabio Eboli fabi...@quipo.it To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Saturday, December 22, 2012 11:00 PM Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements Hello, Bruce Using saturated transistors as switches in the current source and elsewhere isn't conducive to fast switching. The traditional arrangement using current mode switches is much faster and more predictable. This is something I'd like to understand better. I'm referring to this schematic here: http://www.flickr.com/photos/14336723@N08/8293076065/ Q2 and Q5 are saturating toward the end of the ramp pulse, when the ramp capacitor C1 starts to go up. I was prepared to see the circuit I designed fail miserably on switch time, but it seem to be working, as far as I could see on the DSO. As far I can understand, the fact that Q2 and Q6 don't saturate, saves the circuit, since at the end of the ramp, when Q1 and Q5 are into saturation, Q6 is able to steer the current to ground, and reverse bias BE (and CB) of Q5. Is this correct, or I was only lucky with the specific parts I used? Buffering the ramp with an opamp requires that the opamp settling time be known so that the opamp has fully settled before a sample is taken. With a charge redistribution ADC that has a sampling switch connected to a capacitor array a buffer isnt usually necessary. Bruce I was planning to read the voltage with a microcontroller's ADC. I will set a fixed delay from the PPS rising edge and start sampling there. To do so I need that the voltage on integrating capacitor to stay reasonably stable during the delay. Fabio ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Google baker clamp for more on this. Tom - Original Message - From: Alan Melia alan.me...@btinternet.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Saturday, December 22, 2012 6:28 PM Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements Hi Fabio taking BJTs deep into saturation stores a lot of charge in the collector base capacitance. this must br discharged before a state change can occur. LSTTL gets round this and gets the speed at lower currents by clamping the collector to only just in saturation with a schottky diode between base and collector. Higher speeds are obtained with a long-tail pair like configuration, which switches (diverts) the current flow between left and right transistors for the two logic states. The current and power dissipation is high but speeds 10 times saturated logic are obtainable. see ECL, MECL, or PECL logic family schematics. Alan G3NYK - Original Message - From: Fabio Eboli fabi...@quipo.it To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Saturday, December 22, 2012 11:00 PM Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements Hello, Bruce Using saturated transistors as switches in the current source and elsewhere isn't conducive to fast switching. The traditional arrangement using current mode switches is much faster and more predictable. This is something I'd like to understand better. I'm referring to this schematic here: http://www.flickr.com/photos/14336723@N08/8293076065/ Q2 and Q5 are saturating toward the end of the ramp pulse, when the ramp capacitor C1 starts to go up. I was prepared to see the circuit I designed fail miserably on switch time, but it seem to be working, as far as I could see on the DSO. As far I can understand, the fact that Q2 and Q6 don't saturate, saves the circuit, since at the end of the ramp, when Q1 and Q5 are into saturation, Q6 is able to steer the current to ground, and reverse bias BE (and CB) of Q5. Is this correct, or I was only lucky with the specific parts I used? Buffering the ramp with an opamp requires that the opamp settling time be known so that the opamp has fully settled before a sample is taken. With a charge redistribution ADC that has a sampling switch connected to a capacitor array a buffer isnt usually necessary. Bruce I was planning to read the voltage with a microcontroller's ADC. I will set a fixed delay from the PPS rising edge and start sampling there. To do so I need that the voltage on integrating capacitor to stay reasonably stable during the delay. Fabio ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that…. Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about can't get a 2 ns pulse through it goes away. I'm not suggesting you tear up what you have. It's just something else to try and compare. Bob On Dec 22, 2012, at 6:00 PM, Fabio Eboli fabi...@quipo.it wrote: Hello, Bruce Using saturated transistors as switches in the current source and elsewhere isn't conducive to fast switching. The traditional arrangement using current mode switches is much faster and more predictable. This is something I'd like to understand better. I'm referring to this schematic here: http://www.flickr.com/photos/14336723@N08/8293076065/ Q2 and Q5 are saturating toward the end of the ramp pulse, when the ramp capacitor C1 starts to go up. I was prepared to see the circuit I designed fail miserably on switch time, but it seem to be working, as far as I could see on the DSO. As far I can understand, the fact that Q2 and Q6 don't saturate, saves the circuit, since at the end of the ramp, when Q1 and Q5 are into saturation, Q6 is able to steer the current to ground, and reverse bias BE (and CB) of Q5. Is this correct, or I was only lucky with the specific parts I used? Buffering the ramp with an opamp requires that the opamp settling time be known so that the opamp has fully settled before a sample is taken. With a charge redistribution ADC that has a sampling switch connected to a capacitor array a buffer isnt usually necessary. Bruce I was planning to read the voltage with a microcontroller's ADC. I will set a fixed delay from the PPS rising edge and start sampling there. To do so I need that the voltage on integrating capacitor to stay reasonably stable during the delay. Fabio ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi I think I would grab some sort of USB thermometer and start logging the room temperature. CMOS input op-amps are a pretty good way to buffer the integrating capacitor. They are cheap and have very low bias currents. Bob On Dec 21, 2012, at 7:43 AM, fabi...@quipo.it wrote: Hello, while waiting fot the final doom, or a new job (tough times here) here is another update of the work I'm doing, sorry for the looong mail, hope I'm not boring the readers. I have a question about a some measurements I made, and I'd like an opinion about a frontend schematic I designed. First the question about the problem: in this graph (bottom right) there is the time interval between the PPS from the PA6H GPS module and the 10MHz form the FE5680A, uncrambled and corrected for linear drift. The graph periodically makes big steps, and this happens in the morning hours, in the few captures I made so far the fact happens around 6am-8am in the morning: http://www.flickr.com/photos/14336723@N08/8294131424/ another previous capture with span enough to include 2 mornings: http://www.flickr.com/photos/14336723@N08/8294131660/ I will make more tests to check if the problem is in the gps receiver or in the FE5680 or in the way I'm taking measurements. This will take a while. Maybe there is a simple explanation that I cannot see since I'm a total newbie i this field. Where should I search first for the problem? How I'm taking the measurements: the measurements are taken with the racal 1992 connected to the point OutD in the centre of the frontend I'm building: http://www.flickr.com/photos/14336723@N08/8293076065/ The OutD will spit out a short negative pulse, the width of this pulse is the same (or very near) than the phase time interval between the rising edges of the pps and the 10MHz. The counter logs the pulse width using a 100MHz scope probe set to 10x, DC coupled. The plots are made using this script I wrote for the task : http://pastebin.com/XmKQp9gR The (rude) script tries to unscramble the data, remove outliers and correct for linear drift. If it's useful I will upload the raw log data. The frontend circuit: As I wrote before I'm trying to feed a microcontroller with 10MHz from a Rb oscillator and a PPS pulse from a GPS module and see if I can obtain a good starting point for building my own GPSDO. Now I'm testing a front end that will present to the micro both the PPS and 10MHz nicely squared, and an analogue representation of the time interval between the rising pulses of the sources. What do you think of the circuit I designed? (thanks to many resources coming from this list, I passed much time on ko4bb site and many others I dont even remember, thank you all!) here the asc file for LTSpice: http://pastebin.com/94H78jxs I'm using components I had around or scavenged in scrap electronics I had. The TAC seem to work, but now I need a better opamp (the LM358 has too much current flowing in-out of the inputs), here a pair of captures taken directly from C1 capacitor, 90nS pulse: http://www.flickr.com/photos/14336723@N08/8293075961/ and a 50nS one: http://www.flickr.com/photos/14336723@N08/8294131200/ The red trace is the input GPS PPS. Fabio Eboli. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi Fabio, I am not crazy about your 10 MHz input circuit. You might want to consider investigating John Miles input arrangement at the following web site: http://www.ke5fx.com/ac.htm I used it to drive an input to a divider chip without the output resistor or capacitor. BillWB6BNQ fabi...@quipo.it wrote: Hello, while waiting fot the final doom, or a new job (tough times here) here is another update of the work I'm doing, sorry for the looong mail, hope I'm not boring the readers. I have a question about a some measurements I made, and I'd like an opinion about a frontend schematic I designed. First the question about the problem: in this graph (bottom right) there is the time interval between the PPS from the PA6H GPS module and the 10MHz form the FE5680A, uncrambled and corrected for linear drift. The graph periodically makes big steps, and this happens in the morning hours, in the few captures I made so far the fact happens around 6am-8am in the morning: http://www.flickr.com/photos/14336723@N08/8294131424/ another previous capture with span enough to include 2 mornings: http://www.flickr.com/photos/14336723@N08/8294131660/ I will make more tests to check if the problem is in the gps receiver or in the FE5680 or in the way I'm taking measurements. This will take a while. Maybe there is a simple explanation that I cannot see since I'm a total newbie i this field. Where should I search first for the problem? How I'm taking the measurements: the measurements are taken with the racal 1992 connected to the point OutD in the centre of the frontend I'm building: http://www.flickr.com/photos/14336723@N08/8293076065/ The OutD will spit out a short negative pulse, the width of this pulse is the same (or very near) than the phase time interval between the rising edges of the pps and the 10MHz. The counter logs the pulse width using a 100MHz scope probe set to 10x, DC coupled. The plots are made using this script I wrote for the task : http://pastebin.com/XmKQp9gR The (rude) script tries to unscramble the data, remove outliers and correct for linear drift. If it's useful I will upload the raw log data. The frontend circuit: As I wrote before I'm trying to feed a microcontroller with 10MHz from a Rb oscillator and a PPS pulse from a GPS module and see if I can obtain a good starting point for building my own GPSDO. Now I'm testing a front end that will present to the micro both the PPS and 10MHz nicely squared, and an analogue representation of the time interval between the rising pulses of the sources. What do you think of the circuit I designed? (thanks to many resources coming from this list, I passed much time on ko4bb site and many others I dont even remember, thank you all!) here the asc file for LTSpice: http://pastebin.com/94H78jxs I'm using components I had around or scavenged in scrap electronics I had. The TAC seem to work, but now I need a better opamp (the LM358 has too much current flowing in-out of the inputs), here a pair of captures taken directly from C1 capacitor, 90nS pulse: http://www.flickr.com/photos/14336723@N08/8293075961/ and a 50nS one: http://www.flickr.com/photos/14336723@N08/8294131200/ The red trace is the input GPS PPS. Fabio Eboli. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi Fabio, On 12/21/2012 01:43 PM, fabi...@quipo.it wrote: Hello, while waiting fot the final doom, or a new job (tough times here) here is another update of the work I'm doing, sorry for the looong mail, hope I'm not boring the readers. I have a question about a some measurements I made, and I'd like an opinion about a frontend schematic I designed. First the question about the problem: in this graph (bottom right) there is the time interval between the PPS from the PA6H GPS module and the 10MHz form the FE5680A, uncrambled and corrected for linear drift. The graph periodically makes big steps, and this happens in the morning hours, in the few captures I made so far the fact happens around 6am-8am in the morning: http://www.flickr.com/photos/14336723@N08/8294131424/ another previous capture with span enough to include 2 mornings: http://www.flickr.com/photos/14336723@N08/8294131660/ Like Bob said, start logging the temperature. Since you have about 86400 s period on this behaviour, I expect that heating up in the morning (sun or just habits of humans roughly aligned with sun patterns) be the reason, so this would be temperature dependent. Plotting supply voltage may be another reason. I will make more tests to check if the problem is in the gps receiver or in the FE5680 or in the way I'm taking measurements. This will take a while. Maybe there is a simple explanation that I cannot see since I'm a total newbie i this field. Where should I search first for the problem? If you assume temperature sensitivity, you can apply temperature on either of these parts to see what triggers the reaction. Make sure that one part settles before pushing the other, so you know what is the effect of what. How I'm taking the measurements: the measurements are taken with the racal 1992 connected to the point OutD in the centre of the frontend I'm building: http://www.flickr.com/photos/14336723@N08/8293076065/ The OutD will spit out a short negative pulse, the width of this pulse is the same (or very near) than the phase time interval between the rising edges of the pps and the 10MHz. The counter logs the pulse width using a 100MHz scope probe set to 10x, DC coupled. Do you really get 1-2 cycle long difference measures that way? You risk a high non-linearity at the small difference side otherwise, as it takes time to wake the transistors. The plots are made using this script I wrote for the task : http://pastebin.com/XmKQp9gR The (rude) script tries to unscramble the data, remove outliers and correct for linear drift. If it's useful I will upload the raw log data. The frontend circuit: As I wrote before I'm trying to feed a microcontroller with 10MHz from a Rb oscillator and a PPS pulse from a GPS module and see if I can obtain a good starting point for building my own GPSDO. Now I'm testing a front end that will present to the micro both the PPS and 10MHz nicely squared, and an analogue representation of the time interval between the rising pulses of the sources. What do you think of the circuit I designed? (thanks to many resources coming from this list, I passed much time on ko4bb site and many others I dont even remember, thank you all!) here the asc file for LTSpice: http://pastebin.com/94H78jxs I'm using components I had around or scavenged in scrap electronics I had. The TAC seem to work, but now I need a better opamp (the LM358 has too much current flowing in-out of the inputs), here a pair of captures taken directly from C1 capacitor, 90nS pulse: http://www.flickr.com/photos/14336723@N08/8293075961/ and a 50nS one: http://www.flickr.com/photos/14336723@N08/8294131200/ The red trace is the input GPS PPS. As I commented, you might want 1-2 cycles to pass, so adding a second DFF might be needed for that task. Like that you try your interpolator wings! I do recommend you to check out the Wenzel clock input stage, which is being deployed in the TADD-2 divider. Squares up sine clocks nicely. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
