[U-Boot] Pull request - microblaze
Dear Wolfgang, please pull the following changes. Thanks, Michal The following changes since commit 89c95f0cd3f8140f3b8a82a22a6a144c148d09c6: Mike Frysinger (1): asm-offsets: generate bd_t size are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Michal Simek (2): microblaze: Disabling interrupt should return 1 if was enabled microblaze: Fix bd_info pointer arch/microblaze/cpu/interrupts.c |5 - arch/microblaze/lib/board.c |8 +--- include/configs/microblaze-generic.h |8 3 files changed, 13 insertions(+), 8 deletions(-) -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] update VCMA9 port
Wolfgang Denk schrieb: Please move this line into your board config file, and drop the config.mk file. Ok, will be done. - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.muel...@elsoft.ch I understand this file was created using copy paste; why do you think it is legal to remove the original copyright notice? The actual patch looks like this: - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005 As you can see, i don't remove any copyright notice (just extending it) and i fix an obviously bad reference to SMDK2410. Dave ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-BOOT] [PATCH] bootm: replace blob_start with image_start
For uImage always has a 64 bytes header, we couldn't expect to do
the xip from the header but should xip from the image start.
The latter logic in that section is also move the image from image_start
to the load address, so sync this logic to the xip operation.
Signed-off-by: Lei Wen lei...@marvell.com
---
common/cmd_bootm.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 18019d6..81fc4be 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -344,7 +344,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end,
int boot_progress)
switch (comp) {
case IH_COMP_NONE:
- if (load == blob_start) {
+ if (load == image_start) {
printf ( XIP %s ... , type_name);
} else {
printf ( Loading %s ... , type_name);
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] asm-offsets: generate bd_t size
On Mon, Jan 10, 2011 at 2:50 AM, Michal Simek wrote: Wolfgang Denk wrote: Mike Frysinger wrote: Some ports set up the board info structure at the same time as the global data structure, and largely keep them together. So generate a define for the board info struct too. Applied, thanks. I am little bit confused. 1. Mike's patch has broken coding style in his patch (space+space15) i retained existing style on purpose. i figured Wolfgang preferred that since he wrote it that way. doesnt matter to me either way. 2. I sent that patch 3 days before Mike. (It is the longer story) http://lists.denx.de/pipermail/u-boot/2010-December/084095.html i hadnt noticed that. probably because i had already punted the e-mail a few days before i noticed i needed it. otherwise i would have s-o-b your version. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-BOOT] [PATCH] bootm: replace blob_start with image_start
On Mon, Jan 10, 2011 at 4:31 AM, Lei Wen wrote:
case IH_COMP_NONE:
- if (load == blob_start) {
+ if (load == image_start) {
printf ( XIP %s ... , type_name);
this breaks XIP uImages that are created to work with existing
u-boots. it'd be annoying to no longer be able to boot uImages that
were working, and update kernel build systems that output those uImage
formats.
so could you add your check as an additional one ?
if (load == blob_start || load == image_start) {
...
-mike
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-BOOT] [PATCH] bootm: replace blob_start with image_start
On Mon, Jan 10, 2011 at 5:45 PM, Mike Frysinger vap...@gentoo.org wrote:
On Mon, Jan 10, 2011 at 4:31 AM, Lei Wen wrote:
case IH_COMP_NONE:
- if (load == blob_start) {
+ if (load == image_start) {
printf ( XIP %s ... , type_name);
this breaks XIP uImages that are created to work with existing
u-boots. it'd be annoying to no longer be able to boot uImages that
were working, and update kernel build systems that output those uImage
formats.
so could you add your check as an additional one ?
if (load == blob_start || load == image_start) {
...
-mike
Understand...
I would submit a updated patch adopt it.
Best regards,
Lei
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] NAND: mxc_nand reads/writes only first 512 bytes of each page
On 01/09/2011 03:40 PM, Jason Liu wrote: Hi, Stefano, Hi Jason, Have you set the page_size correctly with the following register? Let's see... 49.4.3.7 Reset Control and Sourse Register - RCSR: NFC_4K This bit is used to config the NandFlash page size. It is defined by PAGE_SIZE while boot up, and it can be configured by software after boot up. 0 not 4k page 1 4k page 8 This seems ok. NFC_FMS This bit is used to config the NandFlash page size.It is defined by PAGE_SIZE while boot up,and it can be configured by software after boot up. 0 not 2k page 1 2k page That's it ! This was wrong on my board. I set the NFC_FMS bit and the whole page is now read correctly. Many thanks, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-BOOT] [PATCH V2] bootm: replace blob_start with image_start
For uImage always has a 64 bytes header, we couldn't expect to do
the xip from the header but should xip from the image start.
The latter logic in that section is also move the image from image_start
to the load address, so sync this logic to the xip operation.
Signed-off-by: Lei Wen lei...@marvell.com
---
V2: keep the original XIP setting to compare with blob_start.
This would make original uImage still could works, since
it modify the make uImage Makefile in the kernel.
common/cmd_bootm.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 18019d6..778f6a4 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -344,7 +344,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end,
int boot_progress)
switch (comp) {
case IH_COMP_NONE:
- if (load == blob_start) {
+ if (load == blob_start || load == image_start) {
printf ( XIP %s ... , type_name);
} else {
printf ( Loading %s ... , type_name);
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] common: introduce a genutils.h file
Dear Heiko Schocher, In message 4d2ab091.9030...@denx.de you wrote: Linux defines this is include/linux/kernel.h, i. e. in a pretty central place, and we should porobably do the same. How about adding it to include/common.h instead? Hmm.. I thought exactly this should not go in common.h as a result from this thread: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/78692 Well, OK. Then please let's find a better name than genutils. Eventually we should create u-boot.h (which then probably would / should include asm/u-boot.h). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Overdrawn? But I still have checks left! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFC] armv7: fixloop: don't fixup if location is NULL
Dear Minkyu Kang, In message aanlktimvxwebjuxquwfyrwhb8y-ox-gocvpfcl1_1...@mail.gmail.com you wrote: Declared function pointer. int (*test_func)(void); This results in a symbol in bss segment, right? And then, set to NULL at arch_cpu_init() Such an assignment is illegal then. Bss has not been initalized before relocation, and must not be accessed (neither read nor write). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Extended Epstein-Heisenberg Principle: In an R D orbit, only 2 of the existing 3 parameters can be defined simultaneously. The parame- ters are: task, time and resources ($). ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] asm-offsets: generate bd_t size
Dear Michal Simek, In message 4d2aba41.7030...@monstr.eu you wrote: I am little bit confused. 1. Mike's patch has broken coding style in his patch (space+space15) Indeed. Sorry for missing this. The existing code had the same issue. If you want, then please submit a patch to clean this up for the whole file. 2. I sent that patch 3 days before Mike. (It is the longer story) http://lists.denx.de/pipermail/u-boot/2010-December/084095.html I like that the patch is in mainline tree because I need it for Microblaze but I don't quite understand that you beat me about coding style and then you apply patch which has broken coding style. I don't care if that patch is Mike's or mine I would like to be sure what are that acceptance rules. Can you please tell me how this can happen? Usually I try to process incoming patches sequentially, but this is not always possible; even if I follow all mail threads this is unreliable as many people submit new versions of their patches without proper linking back to the existing threads. So even when trying to work mostly sequentially, I will frequently jump forward and backward in time. In cases like this (different patches for the same thing, submitted independently by separate people using different Subjects) it is pretty much pure chance which of the submitted patches gets picked up. For me the only important thing is that no patches get dropped unintentionally. If I remember correctly Mike's patch was part of my todo list in patchwork, which was what I processed first, completely independent of submission date. I don't remember if I moved the patch there myself, or if somebody else (Mike?) bestowed it upon me. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Nothing ever becomes real until it is experienced. - John Keats ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] asm-offsets: generate bd_t size
Dear Mike Frysinger, In message aanlktim+t7jczd2pdyacs9bpciada-cgico1coz7v...@mail.gmail.com you wrote: i hadnt noticed that. probably because i had already punted the e-mail a few days before i noticed i needed it. otherwise i would have s-o-b your version. I think you should rather send Acked-by in such cases. The Signed-off-by: tag indicates that the signer was involved in the development of the patch, or that he/she was in the patch's delivery path. If a person was not directly involved in the preparation or handling of a patch but wishes to signify and record their approval of it then they can arrange to have an Acked-by: line added to the patch's changelog. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Objects in mirror are closer than they appear. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cfi_flash: avoid flash_verbose when possible
Hi Wolfgang, On Sunday 09 January 2011 18:05:42 Wolfgang Denk wrote: The flash_verbose logic is only used by the CFI MTD layer, so if we aren't using that, disable the logic completely. Signed-off-by: Mike Frysinger vap...@gentoo.org --- drivers/mtd/cfi_flash.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) Applied, thanks. Stefan, this is somewhat global and looks simple enough - hope this is OK with you. No problem at all. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFC] armv7: fixloop: don't fixup if location is NULL
Dear Wolfgang Denk, On 10 January 2011 19:20, Wolfgang Denk w...@denx.de wrote: Dear Minkyu Kang, In message aanlktimvxwebjuxquwfyrwhb8y-ox-gocvpfcl1_1...@mail.gmail.com you wrote: Declared function pointer. int (*test_func)(void); This results in a symbol in bss segment, right? And then, set to NULL at arch_cpu_init() Such an assignment is illegal then. Bss has not been initalized before relocation, and must not be accessed (neither read nor write). Illegal? as a result, yes. But we do many things before the reloaction as arch init, board init and so on. There is possibility that the system is hang. Because of there is no protection of access the memory. This patch is for prevent it. In any case, the system must be go on. And one more thing. How about lcd_setmem function? panel_info is located at bss area, but lcd_setmem access this structure. Is it illegal? Thanks Minkyu Kang. -- from. prom. www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Small coding style fix in lib/asm-offsets.c
Signed-off-by: Stefan Roese s...@denx.de
---
lib/asm-offsets.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 6f253a6..c88f5d4 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -23,10 +23,10 @@ int main(void)
{
/* Round up to make sure size gives nice stack alignment */
DEFINE(GENERATED_GBL_DATA_SIZE,
- (sizeof(struct global_data)+15) ~15);
+ (sizeof(struct global_data) + 15) ~15);
DEFINE(GENERATED_BD_INFO_SIZE,
- (sizeof(struct bd_info)+15) ~15);
+ (sizeof(struct bd_info) + 15) ~15);
return 0;
}
--
1.7.3.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc4xx: Remove PCI support from lwmon5
On Tuesday 21 December 2010 19:03:44 Stefan Roese wrote: PCI is not used at all on lwmon5. So lets remove it. It saves space and reduces boot time a bit (approx. 50ms). Applied to u-boot-ppc4xx. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] PPC4xx: Reduce NAND TLB window size on Canyonlands
On Sunday 02 January 2011 10:07:34 Felix Radensky wrote: 16MiB NAND TLB window is way too big. Reduce it to 1KiB. Applied to u-boot-ppc4xx. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ppc4xx: Fix compilation breakage in miiphy.c
Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced a small problem in the ppc4xx miiphy.c version. This patch fixes this problem. Signed-off-by: Stefan Roese s...@denx.de Cc: Mike Frysinger vap...@gentoo.org --- arch/powerpc/cpu/ppc4xx/miiphy.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 206c476..9f8f8fa 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -100,7 +100,7 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 anar = 0x; if (exsr ESTATUS_1000XF) - anar |= ADVERTISE_1000XFULL); + anar |= ADVERTISE_1000XFULL; if (exsr ESTATUS_1000XH) anar |= ADVERTISE_1000XHALF; -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] armv7: add support for S5PC210 SoC
S5PC210 is a 32-bit RSIC and Coretex-A9 Dual Core based micro-processor.
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/cpu/armv7/s5pc2xx/Makefile | 42
arch/arm/cpu/armv7/s5pc2xx/clock.c| 220 +
arch/arm/cpu/armv7/s5pc2xx/soc.c | 30 +++
arch/arm/include/asm/arch-s5pc2xx/adc.h | 42
arch/arm/include/asm/arch-s5pc2xx/clk.h | 36
arch/arm/include/asm/arch-s5pc2xx/clock.h | 255 +
arch/arm/include/asm/arch-s5pc2xx/cpu.h | 96 +
arch/arm/include/asm/arch-s5pc2xx/gpio.h | 112 +++
arch/arm/include/asm/arch-s5pc2xx/mmc.h | 71 +++
arch/arm/include/asm/arch-s5pc2xx/pwm.h | 55 ++
arch/arm/include/asm/arch-s5pc2xx/sys_proto.h | 32 +++
arch/arm/include/asm/arch-s5pc2xx/uart.h | 55 ++
12 files changed, 1046 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/s5pc2xx/Makefile
create mode 100644 arch/arm/cpu/armv7/s5pc2xx/clock.c
create mode 100644 arch/arm/cpu/armv7/s5pc2xx/soc.c
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/adc.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/clk.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/clock.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/cpu.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/gpio.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/mmc.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/pwm.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/sys_proto.h
create mode 100644 arch/arm/include/asm/arch-s5pc2xx/uart.h
diff --git a/arch/arm/cpu/armv7/s5pc2xx/Makefile
b/arch/arm/cpu/armv7/s5pc2xx/Makefile
new file mode 100644
index 000..124c380
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pc2xx/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang mk7.k...@samsung.com
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS += clock.o soc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:$(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/s5pc2xx/clock.c
b/arch/arm/cpu/armv7/s5pc2xx/clock.c
new file mode 100644
index 000..450a630
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pc2xx/clock.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang mk7.k...@samsung.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/clk.h
+
+#ifndef CONFIG_SYS_CLK_FREQ_C210
+#define CONFIG_SYS_CLK_FREQ_C210 2400
+#endif
+
+/* s5pc210: return pll clock frequency */
+static unsigned long s5pc210_get_pll_clk(int pllreg)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(clk-apll_con0);
+ break;
+ case MPLL:
+ r = readl(clk-mpll_con0);
+
[U-Boot] [PATCH 2/2] armv7: add support for s5pc210 universal board
This patch adds support for Samsung s5pc210 universal board Signed-off-by: Minkyu Kang mk7.k...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- MAINTAINERS |5 +- MAKEALL |1 + board/samsung/universal_c210/Makefile| 51 board/samsung/universal_c210/config.mk | 24 ++ board/samsung/universal_c210/lowlevel_init.S | 395 ++ board/samsung/universal_c210/onenand.c | 34 +++ board/samsung/universal_c210/universal.c | 251 boards.cfg |1 + include/configs/s5pc210_universal.h | 248 9 files changed, 1008 insertions(+), 2 deletions(-) create mode 100644 board/samsung/universal_c210/Makefile create mode 100644 board/samsung/universal_c210/config.mk create mode 100644 board/samsung/universal_c210/lowlevel_init.S create mode 100644 board/samsung/universal_c210/onenand.c create mode 100644 board/samsung/universal_c210/universal.c create mode 100644 include/configs/s5pc210_universal.h diff --git a/MAINTAINERS b/MAINTAINERS index a5f0493..6eed120 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -672,8 +672,9 @@ Nishant Kamat nska...@ti.com Minkyu Kang mk7.k...@samsung.com - s5p_goniARM ARMV7 (S5PC110 SoC) - SMDKC100ARM ARMV7 (S5PC100 SoC) + s5p_goniARM ARMV7 (S5PC110 SoC) + SMDKC100ARM ARMV7 (S5PC100 SoC) + s5pc210_universal ARM ARMV7 (S5PC210 SoC) Frederik Kriewitz frede...@kriewitz.eu diff --git a/MAKEALL b/MAKEALL index a732e6a..a5b265f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -434,6 +434,7 @@ LIST_ARMV7=\ omap4_panda \ omap4_sdp4430 \ s5p_goni\ + s5pc210_universal \ smdkc100\ diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile new file mode 100644 index 000..0200220 --- /dev/null +++ b/board/samsung/universal_c210/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2010 Samsung Electronics +# Minkyu Kang mk7.k...@samsung.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y:= universal.o onenand.o +SOBJS := lowlevel_init.o + +SRCS:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(SOBJS) $(OBJS) + $(call cmd_link_o_target, $(SOBJS) $(OBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/samsung/universal_c210/config.mk b/board/samsung/universal_c210/config.mk new file mode 100644 index 000..0ecd716 --- /dev/null +++ b/board/samsung/universal_c210/config.mk @@ -0,0 +1,24 @@ +# +# Copyright (C) 2010 Samsung Electronics +# Kyungmin Park kyungmin.p...@samsung.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CONFIG_SYS_TEXT_BASE = 0x4480 diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
Re: [U-Boot] [PATCH] ppc4xx: Fix compilation breakage in miiphy.c
On Mon, Jan 10, 2011 at 6:58 AM, Stefan Roese wrote: Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced a small problem in the ppc4xx miiphy.c version. This patch fixes this problem. Acked-by: Mike Frysinger vap...@gentoo.org -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFC] armv7: fixloop: don't fixup if location is NULL
Dear Minkyu Kang, In message aanlktimgbjose8c+_6asuon5knnr1_uknqc=wf_ud...@mail.gmail.com you wrote: int (*test_func)(void); This results in a symbol in bss segment, right? And then, set to NULL at arch_cpu_init() Such an assignment is illegal then. Bss has not been initalized before relocation, and must not be accessed (neither read nor write). Illegal? as a result, yes. No, illegal as an action. You MUST NOT access any symbols in BSS before relocation (more precisely, before bss has been initialized). And you MUST NOT write any symbols in data segment before relocation, either. In both cases, the result of such actions is undefined behaviour. But we do many things before the reloaction as arch init, board init and so on. Of course, but as mentioned we must not read or write to symbols in bss, and we must not write to symbols in data segment. How about lcd_setmem function? panel_info is located at bss area, but lcd_setmem access this structure. Is it illegal? This must not be done before relocation. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Without followers, evil cannot spread. -- Spock, And The Children Shall Lead, stardate 5029.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3] mpc83xx: fix pcie configuration space read/write
This patch fix a problem for the pcie enumeration when the mpc83xx pcie
controller is
connected with switch or we use both of the two pcie controller
Signed-off-by: Baidu Boy liucai@gmail.com
---
Changes for V2:
- Avoid line wrap in the patch
Changes for V3
- Add space between ) and {
arch/powerpc/cpu/mpc83xx/pcie.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 46a706d..8429848 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -46,13 +46,15 @@ static struct {
#endif
};
+static u8 pcie_index = 0;
+
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose-first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- pex83xx_t *pex = immr-pciexp[bus];
+ pex83xx_t *pex = immr-pciexp[pcie_index];
struct pex_outbound_window *out_win = pex-bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) 3 | PCI_FUNC(dev);
u32 dev_base = bus 24 | devfn 16;
@@ -324,6 +326,8 @@ void mpc83xx_pcie_init(int num_buses, struct pci_region
**reg)
num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
}
- for (i = 0; i num_buses; i++)
+ for (i = 0; i num_buses; i++) {
+ pcie_index = i;
mpc83xx_pcie_init_bus(i, reg[i]);
+ }
}
--
1.7.3.1.msysgit.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3] mpc83xx: fix pcie configuration space read/write
This patch fix a problem for the pcie enumeration when the mpc83xx pcie
controller is
connected with switch or we use both of the two pcie controller
Signed-off-by: Baidu Boy liucai@gmail.com
---
Changes for V2:
- Avoid line wrap in the patch
Changes for V3
- Add space between ) and {
arch/powerpc/cpu/mpc83xx/pcie.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 46a706d..8429848 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -46,13 +46,15 @@ static struct {
#endif
};
+static u8 pcie_index = 0;
+
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose-first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- pex83xx_t *pex = immr-pciexp[bus];
+ pex83xx_t *pex = immr-pciexp[pcie_index];
struct pex_outbound_window *out_win = pex-bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) 3 | PCI_FUNC(dev);
u32 dev_base = bus 24 | devfn 16;
@@ -324,6 +326,8 @@ void mpc83xx_pcie_init(int num_buses, struct pci_region
**reg)
num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
}
- for (i = 0; i num_buses; i++)
+ for (i = 0; i num_buses; i++) {
+ pcie_index = i;
mpc83xx_pcie_init_bus(i, reg[i]);
+ }
}
--
1.7.3.1.msysgit.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [MX51EVK] u-boot ECC errors flashing NAND
Hi, I'm facing ECC errors when flashing u-boot on NAND on MX51EVK-based board. U-Boot nand write command doesn't fill out-of-band (OOB) bytes correctly. I noted this behavior after compare the same u-boot.bin image flashed via ATK (proprietary software from Freescale). I guess is something related to ECC timing. my logs: http://farm6.static.flickr.com/5130/5320148028_7da19d3cf2_o.png http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-fail.txt http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-ok.txt I also tried flash_eraseall and nandwrite -p on /dev/mtd0 from a linux instance and I got the same OOB errors. --tm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ppc4xx: Support multiple FPGAs
Add support for multiple FPGAs per board for gdsys
405ep architecture.
Signed-off-by: Dirk Eibach eib...@gdsys.de
---
arch/powerpc/include/asm/global_data.h |2 +-
board/gdsys/405ep/405ep.c | 62 +
board/gdsys/405ep/dlvision-10g.c | 214 ---
board/gdsys/405ep/io.c |8 +-
board/gdsys/405ep/iocon.c | 14 +-
board/gdsys/common/Makefile|1 +
board/gdsys/common/fpga.h | 12 +-
include/configs/dlvision-10g.h | 33 -
include/configs/io.h |7 +-
include/configs/iocon.h| 27 -
10 files changed, 275 insertions(+), 105 deletions(-)
diff --git a/arch/powerpc/include/asm/global_data.h
b/arch/powerpc/include/asm/global_data.h
index 4068e85..fb7da21 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -173,7 +173,7 @@ typedef struct global_data {
unsigned long kbd_status;
#endif
#ifdef CONFIG_405EP
- unsigned fpga_state;
+ unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last;/* trace watch-dog triggering rate */
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index c2d9455..84ea573 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -39,24 +39,26 @@
DECLARE_GLOBAL_DATA_PTR;
-int get_fpga_state(void)
+int get_fpga_state(unsigned dev)
{
- return gd-fpga_state;
+ return gd-fpga_state[dev];
}
-void print_fpga_state(void)
+void print_fpga_state(unsigned dev)
{
- if (gd-fpga_state FPGA_STATE_DONE_FAILED)
+ if (gd-fpga_state[dev] FPGA_STATE_DONE_FAILED)
puts( Waiting for FPGA-DONE timed out.\n);
- if (gd-fpga_state FPGA_STATE_REFLECTION_FAILED)
+ if (gd-fpga_state[dev] FPGA_STATE_REFLECTION_FAILED)
puts( FPGA reflection test failed.\n);
}
int board_early_init_f(void)
{
+ unsigned k;
unsigned ctr;
- gd-fpga_state = 0;
+ for (k = 0; k CONFIG_SYS_FPGA_COUNT; ++k)
+ gd-fpga_state[k] = 0;
mtdcr(UIC0SR, 0x); /* clear all ints */
mtdcr(UIC0ER, 0x); /* disable all ints */
@@ -87,13 +89,15 @@ int board_early_init_f(void)
/*
* wait for fpga-done
*/
-#warning this will not work for dlvision-10g
- ctr = 0;
- while (!(in_le16((void *)LATCH2_BASE) 0x0010)) {
- udelay(10);
- if (ctr++ 5) {
- gd-fpga_state |= FPGA_STATE_DONE_FAILED;
- break;
+ for (k = 0; k CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!(in_le16((void *)LATCH2_BASE)
+CONFIG_SYS_FPGA_DONE(k))) {
+ udelay(10);
+ if (ctr++ 5) {
+ gd-fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
}
}
@@ -104,20 +108,24 @@ int board_early_init_f(void)
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- /*
-* wait for fpga out of reset
-* fail ungraceful if fpga is not working properly
-*/
- ctr = 0;
- while (1) {
- fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
- if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
- REFLECTION_TESTPATTERN_INV)
- break;
- udelay(10);
- if (ctr++ 5) {
- gd-fpga_state |= FPGA_STATE_REFLECTION_FAILED;
- break;
+ for (k = 0; k CONFIG_SYS_FPGA_COUNT; ++k) {
+ /*
+* wait for fpga out of reset
+* fail ungraceful if fpga is not working properly
+*/
+ ctr = 0;
+ while (1) {
+ fpga_set_reg(k, CONFIG_SYS_FPGA_RFL_LOW,
+ REFLECTION_TESTPATTERN);
+ if (fpga_get_reg(k, CONFIG_SYS_FPGA_RFL_HIGH) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+ udelay(10);
+ if (ctr++ 5) {
+ gd-fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
}
}
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index e704f74..c217dfe 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -28,63 +28,98 @@
#include asm/ppc4xx-gpio.h
#include ../common/fpga.h
[U-Boot] [PATCH] ppc4xx: Support dual link OSD
Add support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach eib...@gdsys.de
---
board/gdsys/405ep/dlvision-10g.c |3 +-
board/gdsys/common/osd.c | 303 -
board/gdsys/common/osd.h |2 +-
3 files changed, 232 insertions(+), 76 deletions(-)
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index c217dfe..740cceb 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -235,7 +235,8 @@ int last_stage_init(void)
unsigned k;
for (k = 0; k CONFIG_SYS_OSD_SCREENS; ++k)
- if (!get_fpga_state(k))
+ if (!get_fpga_state(k)
+ || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
osd_probe(k);
return 0;
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 239c870..9968dbf 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -29,6 +29,12 @@
#define CH7301_I2C_ADDR 0x75
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
#define PIXCLK_640_480_60 2518
#define BASE_WIDTH 32
@@ -38,12 +44,18 @@
enum {
REG_CONTROL = 0x0010,
REG_MPC3W_CONTROL = 0x001a,
+ REG_EXT_INTERRUPT = 0x001c,
+ REG_EXT_INTERRUPT_ENABLE = 0x001e,
+ REG_IIC_WRITE_MAILBOX = 0x0030,
+ REG_IIC_WRITE_MAILBOX_EXT = 0x0032,
+ REG_IIC_READ_MAILBOX = 0x0034,
+ REG_IIC_READ_MAILBOX_EXT = 0x0036,
REG_VIDEOCONTROL = 0x0042,
- REG_OSDVERSION = 0x0100,
- REG_OSDFEATURES = 0x0102,
- REG_OSDCONTROL = 0x0104,
- REG_XY_SIZE = 0x0106,
- REG_VIDEOMEM = 0x0800,
+ REG_OSDVERSION = CONFIG_SYS_FPGA_OSD_BASE + 0x,
+ REG_OSDFEATURES = CONFIG_SYS_FPGA_OSD_BASE + 0x0002,
+ REG_OSDCONTROL = CONFIG_SYS_FPGA_OSD_BASE + 0x0004,
+ REG_XY_SIZE = CONFIG_SYS_FPGA_OSD_BASE + 0x0006,
+ REG_VIDEOMEM = CONFIG_SYS_FPGA_OSD_MEM,
};
enum {
@@ -67,6 +79,37 @@ enum {
CH7301_DSP = 0x56, /* DVI Sync polarity Register */
};
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+ while (fpga_get_reg(screen, REG_EXT_INTERRUPT) (1 12))
+ ;
+ fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX_EXT,
+ reg | (data 8));
+ fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX,
+ 0xc400 | (slave 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+ unsigned int ctr = 0;
+ while (fpga_get_reg(screen, REG_EXT_INTERRUPT) (1 12))
+ ;
+ fpga_set_reg(screen, REG_EXT_INTERRUPT, 1 14);
+ fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX_EXT, reg);
+ fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX, 0xc000 | (slave 1));
+ while (!(fpga_get_reg(screen, REG_EXT_INTERRUPT) (1 14))) {
+ udelay(10);
+ if (ctr++ 5) {
+ printf(iic receive timeout\n);
+ break;
+ }
+ }
+ return fpga_get_reg(screen, REG_IIC_READ_MAILBOX_EXT) 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
{
@@ -92,7 +135,7 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
*feedback_div = m;
}
-static void mpc92469ac_set(unsigned int fout)
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
{
unsigned int n;
unsigned int m;
@@ -114,17 +157,83 @@ static void mpc92469ac_set(unsigned int fout)
break;
}
- fpga_set_reg(REG_MPC3W_CONTROL, (bitval 9) | m);
+ fpga_set_reg(screen, REG_MPC3W_CONTROL, (bitval 9) | m);
}
+#endif
-static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+#ifdef CONFIG_SYS_ICS8N3QV01
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+ unsigned int *_mint, unsigned int *_mfrac,
+ unsigned int *_n)
+{
+ unsigned int n;
+ unsigned int foutiic;
+ unsigned int fvcoiic;
+ unsigned int mint;
+ unsigned long long mfrac;
+
+ n = 255000U / fout;
+ if ((n 1) (n 5))
+ n -= 1;
+
+ foutiic = fout - (fout / 1);
+ fvcoiic = foutiic * n;
+
+ mint = fvcoiic / 114285000;
+ if ((mint 17) || (mint 63))
+ printf(ics8n3qv01_calc_parameters: cannot determine mint\n);
+
+ mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+ / 114285000LL;
+
+ *_mint = mint;
+ *_mfrac = mfrac;
+ *_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+ unsigned int n;
+ unsigned int mint;
+ unsigned int mfrac;
+
[U-Boot] [PATCH] ppc4xx: Add DLVision-10G board support
Board support for the Guntermann Drunck DLVision-10G.
Signed-off-by: Dirk Eibach eib...@gdsys.de
---
MAINTAINERS|1 +
arch/powerpc/include/asm/global_data.h |3 +
board/gdsys/405ep/405ep.c | 38 +-
board/gdsys/405ep/Makefile |1 +
board/gdsys/405ep/dlvision-10g.c | 126 +
board/gdsys/common/fpga.h |8 +
boards.cfg |1 +
include/configs/dlvision-10g.h | 242
8 files changed, 417 insertions(+), 3 deletions(-)
create mode 100644 board/gdsys/405ep/dlvision-10g.c
create mode 100644 include/configs/dlvision-10g.h
diff --git a/MAINTAINERS b/MAINTAINERS
index ba83f71..a13812a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -142,6 +142,7 @@ Dirk Eibach eib...@gdsys.de
devconcenterPPC460EX
dlvisionPPC405EP
+ dlvision-10gPPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
diff --git a/arch/powerpc/include/asm/global_data.h
b/arch/powerpc/include/asm/global_data.h
index 2e218de..4068e85 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -172,6 +172,9 @@ typedef struct global_data {
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
+#ifdef CONFIG_405EP
+ unsigned fpga_state;
+#endif
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last;/* trace watch-dog triggering rate */
#endif
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd233..c2d9455 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,6 +26,7 @@
#include asm/processor.h
#include asm/io.h
#include asm/ppc4xx-gpio.h
+#include asm/global_data.h
#include ../common/fpga.h
@@ -36,8 +37,27 @@
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN 0x)
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(void)
+{
+ return gd-fpga_state;
+}
+
+void print_fpga_state(void)
+{
+ if (gd-fpga_state FPGA_STATE_DONE_FAILED)
+ puts( Waiting for FPGA-DONE timed out.\n);
+ if (gd-fpga_state FPGA_STATE_REFLECTION_FAILED)
+ puts( FPGA reflection test failed.\n);
+}
+
int board_early_init_f(void)
{
+ unsigned ctr;
+
+ gd-fpga_state = 0;
+
mtdcr(UIC0SR, 0x); /* clear all ints */
mtdcr(UIC0ER, 0x); /* disable all ints */
mtdcr(UIC0CR, 0x); /* set all to be non-critical */
@@ -66,10 +86,16 @@ int board_early_init_f(void)
/*
* wait for fpga-done
-* fail ungraceful if fpga is not configuring properly
*/
- while (!(in_le16((void *)LATCH2_BASE) 0x0010))
- ;
+#warning this will not work for dlvision-10g
+ ctr = 0;
+ while (!(in_le16((void *)LATCH2_BASE) 0x0010)) {
+ udelay(10);
+ if (ctr++ 5) {
+ gd-fpga_state |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
/*
* setup io-latches for boot (stop reset)
@@ -82,11 +108,17 @@ int board_early_init_f(void)
* wait for fpga out of reset
* fail ungraceful if fpga is not working properly
*/
+ ctr = 0;
while (1) {
fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
REFLECTION_TESTPATTERN_INV)
break;
+ udelay(10);
+ if (ctr++ 5) {
+ gd-fpga_state |= FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
}
return 0;
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index ed31207..169418c 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).o
COBJS-$(CONFIG_IO) += io.o
COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
COBJS := $(BOARD).o $(COBJS-y)
SOBJS =
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 000..e704f74
--- /dev/null
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann Drunck GmbH, eib...@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
Re: [U-Boot] [MX51EVK] u-boot ECC errors flashing NAND
On 01/10/2011 01:58 PM, Tiago Maluta wrote: Hi, Hi Tiago, I'm facing ECC errors when flashing u-boot on NAND on MX51EVK-based board. U-Boot nand write command doesn't fill out-of-band (OOB) bytes correctly. The mxc_nand driver in u-boot mainline does not support version 3 of the internal NFC controller we find on the i.MX51 processor. You should have patched the driver to adapt it for the i.MX51, or you are using other sources. If you have patched the actual driver, please post your patch for review. my logs: http://farm6.static.flickr.com/5130/5320148028_7da19d3cf2_o.png http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-fail.txt http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-ok.txt It seems to me you are not using u-boot mainline... Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/8] those series patches for add ben nanonote board
Thanks for keeping on working on jz4740 patchset. On 01/10/2011 01:18 AM, Xiangfu Liu wrote: Hi Wolfgang those patches are for add xburst jz4740 and Ben NanoNote(named qi_lb60) to U-Boot some info about xburst jz4740: the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box, : : Very useful comments, so such info should also be put into patch description of the relevant changes; Jz4740 SoC overview and about USB boot, respectively. FIXED in [PATCH v3] 1. describe what Jz4740 SoC 2. remove the ENDIANNESS in config.mk 3. don't breaks the 80-charcter-wide rule 4. get rid of #if 0 5. use proper I/O accessors to access registers. 6. remove C++ comments, cleanup code style. FIXED in [PATCH v4] 1. add Entry to MAINTAINERS and boards.cfg 2. add ben nanonote(qi_lb60) to Makefile 3. tested with CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el FIXED in [PATCH v5] 1. remove nand_spl/nand_boot_jz4740.c 2. some cleanup Having a quick glance, v5 still has issues (e.g. it gets split into 8 patches in an improper way). I'll have a closer look later. By the way, I've uploaded xl/jz4740-ben-nanonote-v5 branch (and older v2/v3/v4 branches as well) to make reviews easier for involved people. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8] armv7: add PL310 support to u-boot
Dear Wolfgang,
On Monday 10 January 2011 04:18 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message1293018898-13253-6-git-send-email-ane...@ti.com you wrote:
Add support for some of the key maintenance operations
- Invalidate all
- Invalidate range
- Flush(clean invalidate) all
- Flush range
Can you please use a more descriptive subject, and commit message?
I have no idea what a PL310 might be - is this a new board? Or a new
SoC? or a new Ethernet controller?
Sure. I will add a more descriptive message.
PL310 is an L2 cache controller from ARM.
And what exactly are key maintenance operations? Looks as if you
were talking about basic cache operations?
Yes. I was talking about basic cache operations. In ARM terminology the
cache operations are called cache maintenance operations.
--- /dev/null
+++ b/arch/arm/include/asm/pl310.h
...
+/* Register offsets */
+#define PL310_CACHE_TYPE0x004
+#define PL310_AUX_CTRL 0x104
+
+#define PL310_CACHE_SYNC0x730
+#define PL310_INVAL_LINE_PA 0x770
+#define PL310_INVAL_WAY 0x77C
+#define PL310_CLEAN_LINE_PA 0x7B0
+#define PL310_CLEAN_INVAL_WAY 0x7FC
+#define PL310_CLEAN_INVAL_LINE_PA 0x7F0
NAK. Please use a C struct instead.
Ok.
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -42,6 +42,7 @@ COBJS-y+= cache.o
ifndef CONFIG_SYS_NO_CP15_CACHE
COBJS-y+= cache-cp15.o
endif
+COBJS-$(CONFIG_SYS_USE_PL310) += cache-pl310.o
COBJS-y+= interrupts.o
COBJS-y+= reset.o
There is no documentation for CONFIG_SYS_USE_PL310, and there is no
use of this variable.
Also, it seems CONFIG_SYS_PL310 would be more appropriate.
I shall make it CONFIG_SYS_PL310 and add documentation.
...
+static void pl310_cache_sync(void)
+{
+__raw_writel(0, CONFIG_SYS_PL310_BASE + PL310_CACHE_SYNC);
+}
Please use a proper C struct instead of base address plus offset.
Please fix globally.
...
+for (pa = start; pa stop; pa = pa + line_size)
+__raw_writel(pa, CONFIG_SYS_PL310_BASE +
+ PL310_CLEAN_INVAL_LINE_PA);
Please use braces for multiline statements.
ok.
Best regards,
Wolfgang Denk
Best regards,
Aneesh
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [MX51EVK] u-boot ECC errors flashing NAND
I'm facing ECC errors when flashing u-boot on NAND on MX51EVK-based board. U-Boot nand write command doesn't fill out-of-band (OOB) bytes correctly. The mxc_nand driver in u-boot mainline does not support version 3 of the internal NFC controller we find on the i.MX51 processor. You should have patched the driver to adapt it for the i.MX51, or you are using other sources. If you have patched the actual driver, please post your patch for review. I'd like to adapt u-boot to work with NFC v3. Do you think it's a difficult task (and the documentation [1] available should be sufficient) ? [1] http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX51RM.pdf my logs: http://farm6.static.flickr.com/5130/5320148028_7da19d3cf2_o.png http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-fail.txt http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-ok.txt It seems to me you are not using u-boot mainline... Sorry I forgot to mention, originally I wasn't using u-boot from mainline (my tests refer to u-boot from freescale -r9.2) but I'm switching to use u-boot from mainline on the board so I'm asking here instead of freescale's channel. Whenever possible, using a free software solution is the best solution. --tm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFC] armv7: fixloop: don't fixup if location is NULL
Dear Wolfgang Denk, On 10 January 2011 21:14, Wolfgang Denk w...@denx.de wrote: Dear Minkyu Kang, In message aanlktimgbjose8c+_6asuon5knnr1_uknqc=wf_ud...@mail.gmail.com you wrote: int (*test_func)(void); This results in a symbol in bss segment, right? And then, set to NULL at arch_cpu_init() Such an assignment is illegal then. Bss has not been initalized before relocation, and must not be accessed (neither read nor write). Illegal? as a result, yes. No, illegal as an action. You MUST NOT access any symbols in BSS before relocation (more precisely, before bss has been initialized). And you MUST NOT write any symbols in data segment before relocation, either. In both cases, the result of such actions is undefined behaviour. But we do many things before the reloaction as arch init, board init and so on. Of course, but as mentioned we must not read or write to symbols in bss, and we must not write to symbols in data segment. How about lcd_setmem function? panel_info is located at bss area, but lcd_setmem access this structure. Is it illegal? This must not be done before relocation. No, please see 360 line of arch/arm/lib/board.c This function is called before relocation. And how about init_func_i2c()? This function is called twice, before the relocation and after relocation. When we use board_i2c_init function then, there is possibility that use symbols in bss because of this function is called after relocation. If we ignore this exception, it will be a big constraint. btw, there are any side effects on my patch? I think.. It is just a little safety feature. Thanks Minkyu Kang -- from. prom. www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/5] mv: seperate kirkwood and armada from common setting
-Original Message- From: Lei Wen [mailto:lei...@marvell.com] Sent: Monday, January 10, 2011 9:31 AM To: u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; adrian . wenl @ gmail . com Subject: [PATCH V2 1/5] mv: seperate kirkwood and armada from common setting Since there are lots of difference between kirkwood and armada series, it is better to seperate them but still keep the most common file shared by all marvell platform in the mv-common configure file. This patch move the kirkwood only driver definitoin in mv-common to the soc_name/config.h. This patch is tested with compilation for armada100 and guruplug. Signed-off-by: Lei Wen lei...@marvell.com --- arch/arm/include/asm/arch-armada100/config.h | 50 + arch/arm/include/asm/arch-kirkwood/config.h | 145 + include/configs/aspenite.h |1 + include/configs/mv-common.h | 147 --- ...snip... #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_STACKSIZE 0x0010 /* regular stack- 1M */ @@ -199,27 +124,32 @@ #endif #endif /* CONFIG_NR_DRAM_BANKS */ +/* Include platform Common Definations */ +#include asm/arch/config.h I think you should move this include in the beginning, if there is any specific arch specific definition that can be used further down in this file. Rest ack for the rest of the patch. Regards.. Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/5] ARM: Add Support for Marvell Pantheon Familiy SoCs
-Original Message- From: Lei Wen [mailto:lei...@marvell.com] Sent: Monday, January 10, 2011 9:31 AM To: u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; adrian . wenl @ gmail . com Subject: [PATCH V2 2/5] ARM: Add Support for Marvell Pantheon Familiy SoCs Pantheon Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/communications/marvell_panthe on_910_920_pb.pdf SoC versions Supported: 1) PANTHEON920 (TD) 2) PANTHEON910 (TTC) Signed-off-by: Lei Wen lei...@marvell.com --- arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++ arch/arm/cpu/arm926ejs/pantheon/dram.c| 130 arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 + arch/arm/include/asm/arch-pantheon/config.h | 44 ++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++ arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++ 7 files changed, 635 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c create mode 100644 arch/arm/include/asm/arch-pantheon/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile new file mode 100644 index 000..73644c7 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2010 2011 ?? Regards.. Prafulla . . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8] armv7: adapt omap4 to the new cache maintenance framework
Dear Wolfgang,
On Monday 10 January 2011 04:22 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message1293018898-13253-7-git-send-email-ane...@ti.com you wrote:
adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh Vane...@ti.com
+/*
+ * Outer cache related functions
+ */
+#ifndef CONFIG_SYS_NO_DCACHE
Do we really need such a #define? Where is CONFIG_SYS_NO_DCACHE
documented?
I shall add documentation if it doesn't exist. But I see that it's
already being used.
IMO, it's good to have this option:
1. Not all boards may like to enable data cache.
2. Disabling caches may be one thing you might want to try while
debugging issues.
3. CPUs that do not have cache operations and initialization defined
yet might want to keep it disabled.
+void v7_setup_outer_cache_ops(void)
+{
+#ifndef CONFIG_L2_OFF
Should this be CONFIG_L2_OFF or CONFIG_SYS_L2_OFF? Where is
CONFIG_SYS_L2_OFF documented?
CONFIG_L2_OFF is also aready being used. That's why I used it.
A handful of board config files are using it, but in actual code it's
only referenced by armv7 code.
Shall I change them all to CONFIG_SYS_L2_OFF
I shall add documentation.
@@ -45,3 +47,18 @@ lowlevel_init:
*/
bl s_init
pop {ip, pc}
+
+set_pl310_ctrl_reg:
+PUSH{r4-r11, lr}@ save registers - ROM code may pollute
+@ our registers
+LDR r12, =0x102 @ Set PL310 control register - value in R0
+SMC #0 @ call ROM Code API to set control register
+POP {r4-r11, pc}
Indentation by TAB, please.
Sure. I will take care in future. BTW, that was not caught by
checkpatch.pl. Is there anyway to catch such errors using some tool?
Best regards,
Wolfgang Denk
Best regards,
Aneesh
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 5/5] Pantheon: Add Board Support for Marvell dkb board
-Original Message- From: Lei Wen [mailto:lei...@marvell.com] Sent: Monday, January 10, 2011 9:31 AM To: u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; adrian . wenl @ gmail . com Subject: [PATCH V2 5/5] Pantheon: Add Board Support for Marvell dkb board DKB is a Development Board for PANTHEON TD/TTC(pxa920/pxa910) with * Processor upto 806Mhz * LPDDR1/2 * x8/x16 SLC/MLC NAND * Footprints for eMMC MMC x8 card With Peripherals: * Parallel LCD I/F * Audio codecs (88PM8607) * MIPI CSI-2 camera * Marvell 88W8787 802.11n/BT module * Marvell 2G/3G RF * Dual analog mics speakers, headset jack, LED, ambient * USB2.0 HS host, OTG (mini AB) * GPIO, GPIO expander with DIP switches for easier selection * UART serial over USB, CIR This patch adds basic board support with DRAM and UART functionality Signed-off-by: Lei Wen lei...@marvell.com --- MAINTAINERS|4 +++ board/Marvell/dkb/Makefile | 51 +++ board/Marvell/dkb/dkb.c| 53 boards.cfg |1 + include/configs/dkb.h | 64 5 files changed, 173 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dkb/Makefile create mode 100644 board/Marvell/dkb/dkb.c create mode 100644 include/configs/dkb.h diff --git a/MAINTAINERS b/MAINTAINERS index 96fad4b..0a37a01 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -839,6 +839,10 @@ Prafulla Wadaskar prafu...@marvell.com rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Lei Wen lei...@marvell.com + + dkb ARM926EJS (PANTHEON 88AP920 SOC) + Matthias Weisser weiss...@arcor.de jadecpu ARM926EJS (MB86R01 SoC) diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile new file mode 100644 index 000..8835f8e --- /dev/null +++ b/board/Marvell/dkb/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2010 Ditto Regards.. Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] Add Pantheon soc and dkb board support
-Original Message- From: Lei Wen [mailto:lei...@marvell.com] Sent: Monday, January 10, 2011 9:31 AM To: u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; adrian . wenl @ gmail . com Subject: [PATCH V2 0/5] Add Pantheon soc and dkb board support This patch set add the Pantheon soc and dkb board support. V2: This patch seris update the seperate mv_common part as suggested. Lei Wen (5): mv: seperate kirkwood and armada from common setting ARM: Add Support for Marvell Pantheon Familiy SoCs serial: add pantheon soc support mvmfp: add MFP configuration support for PANTHEON Pantheon: Add Board Support for Marvell dkb board MAINTAINERS |4 + arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++ arch/arm/cpu/arm926ejs/pantheon/dram.c| 130 arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 + arch/arm/include/asm/arch-armada100/config.h | 50 ++ arch/arm/include/asm/arch-kirkwood/config.h | 145 ++ arch/arm/include/asm/arch-pantheon/config.h | 44 ++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++ arch/arm/include/asm/arch-pantheon/mfp.h | 42 + arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++ board/Marvell/dkb/Makefile| 51 ++ board/Marvell/dkb/dkb.c | 53 +++ boards.cfg|1 + drivers/gpio/mvmfp.c |2 + drivers/serial/serial.c |2 + include/configs/aspenite.h|1 + include/configs/dkb.h | 64 include/configs/mv-common.h | 147 +++- One common feedback for all added files, copyright year needs to be changed. Regards.. Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] armv7: adapt omap3 to the new cache maintenance framework
Dear Wolfgang,
On Monday 10 January 2011 04:27 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message1293018898-13253-8-git-send-email-ane...@ti.com you wrote:
adapt omap3 to the new layered cache maintenance framework
...
+/* Declarations */
Please drop this comment. Everybody sees what this is.
ok.
+#ifndef CONFIG_L2_OFF
/*
- * Writing to AuxCR in U-boot using SMI for GP DEV
- * Currently SMI in Kernel on ES2 devices seems to have an issue
- * Once that is resolved, we can postpone this config to kernel
+ * Invalidate L2-cache from secure mode
*/
Why not change this into simple
/* Invalidate L2-cache from secure mode */
?
ok.
...
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+u32 i, num_params = *parameters;
+u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+/*
+ * copy the parameters to an un-cached area to avoid coherency
+ * issues
+ */
+for (i = 0; i num_params; i++) {
+__raw_writel(*parameters, sram_scratch_space);
+parameters++;
+sram_scratch_space++;
+}
Do you have unlimited storage there? Or should you add some check not
to exceed some maximum size?
Number of params is typically 1 or 2. We should have enough space
unless the usage is wrong.
+} else {
+struct emu_hal_params emu_romcode_params;
+emu_romcode_params.num_params = 1;
+emu_romcode_params.param1 = acr;
+omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)emu_romcode_params);
Please add a blank line between declarations and code (fix globally).
ok.
+static void omap3_setup_aux_cr(void)
+{
+/* Workaround for Cortex-A8 errata: #454179 #430973
+ * Set IBE bit
...
Incorrect multiline comment style.
Will correct it.
...
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 4a28ba1..25f54ea 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -27,6 +27,11 @@ typedef struct {
char *nand_string;
} omap3_sysinfo;
+struct __attribute__ ((__packed__)) emu_hal_params {
+u32 num_params;
+u32 param1;
+};
Why exactly do we need the __attribute__ ((__packed__)) here?
Because a pointer to it has to be passed to ROM code and ROM code
wouldn't expect any padding.
Best regards,
Wolfgang Denk
Best regards,
Aneesh
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [MX51EVK] u-boot ECC errors flashing NAND
On 01/10/2011 02:44 PM, Tiago Maluta wrote: I'd like to adapt u-boot to work with NFC v3. Do you think it's a difficult task (and the documentation [1] available should be sufficient) ? [1] http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX51RM.pdf I think there is no other documentation, except the Errata for the chip. My suggestion is to take a look at the linux driver, as NAND is already supported in mainline linux (if I am not wrong). I think you can drop the auto support in the NAND controller, as this is helpful with more as one chip. Maybe it can be added in a second time. Sorry I forgot to mention, originally I wasn't using u-boot from mainline (my tests refer to u-boot from freescale -r9.2) but I'm switching to use u-boot from mainline on the board so I'm asking here instead of freescale's channel. Whenever possible, using a free software solution is the best solution. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] Add Pantheon soc and dkb board support
On Mon, Jan 10, 2011 at 10:35 PM, Prafulla Wadaskar prafu...@marvell.com wrote: -Original Message- From: Lei Wen [mailto:lei...@marvell.com] Sent: Monday, January 10, 2011 9:31 AM To: u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; adrian . wenl @ gmail . com Subject: [PATCH V2 0/5] Add Pantheon soc and dkb board support This patch set add the Pantheon soc and dkb board support. V2: This patch seris update the seperate mv_common part as suggested. Lei Wen (5): mv: seperate kirkwood and armada from common setting ARM: Add Support for Marvell Pantheon Familiy SoCs serial: add pantheon soc support mvmfp: add MFP configuration support for PANTHEON Pantheon: Add Board Support for Marvell dkb board MAINTAINERS | 4 + arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++ arch/arm/cpu/arm926ejs/pantheon/dram.c | 130 arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 + arch/arm/include/asm/arch-armada100/config.h | 50 ++ arch/arm/include/asm/arch-kirkwood/config.h | 145 ++ arch/arm/include/asm/arch-pantheon/config.h | 44 ++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++ arch/arm/include/asm/arch-pantheon/mfp.h | 42 + arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++ board/Marvell/dkb/Makefile | 51 ++ board/Marvell/dkb/dkb.c | 53 +++ boards.cfg | 1 + drivers/gpio/mvmfp.c | 2 + drivers/serial/serial.c | 2 + include/configs/aspenite.h | 1 + include/configs/dkb.h | 64 include/configs/mv-common.h | 147 +++- One common feedback for all added files, copyright year needs to be changed. Yep, that is my mistake, I would update the patch set for it... Best regards, Lei ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] ARM: Avoid compiler optimization for usages of readb, writeb and friends.
Am 02.01.2011 22:00, schrieb Alexander Holler: On 02.01.2011 14:29, Dirk Behme wrote: On 02.01.2011 13:43, Alexander Holler wrote: Am 01.01.2011 20:21, schrieb Dirk Behme: On 01.01.2011 19:47, Alexander Holler wrote: Am 01.01.2011 19:25, schrieb Dirk Behme: On 01.01.2011 18:52, Alexander Holler wrote: Hello, Am 01.01.2011 13:04, schrieb Dirk Behme: On 22.12.2010 12:04, Alexander Holler wrote: gcc 4.5.1 seems to ignore (at least some) volatile definitions, avoid that as done in the kernel. Reading C99 6.7.3 8 and the comment 114) there, I think it is a bug of that gcc version to ignore the volatile type qualifier used e.g. in __arch_getl(). Anyway, using a definition as in the kernel headers avoids such optimizations when gcc 4.5.1 is used. Maybe the headers as used in the current linux-kernel should be used, but to avoid large changes, I've just added a small change to the current headers. Do you like to test the patch in the attachment? I named it 'v4'. After some thinking and testing, it seems to me that the volatile optimization issue this patch shall fix is only with the readx() macros. So the idea is to drop all writex() changes done in the v3 version of this patch. With dropping the writex() changes, we would drop all issues we discussed with e.g. the GCC statement-expression and the do while workaround, too. I've come across a bug which reads as the problem might be fixed in gcc 4.5.2: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45052 I will test gcc 4.5.2 in the next days. Have you been able to test v4 of the patch I sent with gcc 4.5.1? No, sorry, I don't have a test case for consequent write* and I will have to write one. ? If I remember correctly, the test case for this patch was compiling U-Boot with 4.5.1 and then check a) if it boots at Beagle (correct clock.c) b) if NAND works ok (correct omap_gpmc.c) ? No. None of those must fail when the compiler optimizes consequent write* to one write* because the compiler ignores the volatile keyword. I've only found the problem with consequent read* (in clock.c), but there might be problems with consequent write* somewhere else too. So if you remove the change for those write* some other problems might arise and just through booting a kernel those might not be found. So I think it would be dangerous to remove the change for write* when using gcc 4.5.x And because the patch fixes only write* and read* some stuff in u-boot which uses volatile in another context might still fail, therefore I vote to use the current kernel headers where other things besides read* and write* are using those barriers too. Just to understand correctly: Do you want to say that we should ignore your v3 patch http://lists.denx.de/pipermail/u-boot/2010-December/084132.html ? And that you didn't test the v4 patch http://lists.denx.de/pipermail/u-boot/2011-January/084481.html with the test you did in http://lists.denx.de/pipermail/u-boot/2010-December/084134.html (tested with both gcc 4.3.5 and gcc 4.5.1 using binutils 2.20.1) because you now think this test isn't sufficient? Sorry, but I don't understand why you are assuming that the compiler will only use those (wrong) optimizations on reads and not writes. If the compiler does the same wrong optimizations for writes (why not, if it ignores volatile), your v4 would'nt fix that. I've done now some more tests. First, the bug is fixed in gcc 4.5.2. And Indeed, gcc 4.5.0 and gcc 4.5.1 seems to ignore volatile only for reading. At least two writel() are not optimized to one when the volatile (as before) or the __asm__ __volatile__ ( : : : memory) is used. Beeing kind of a defensive programmer, I still would prefer to use have that __asm__ for write* too. That would at least prevent us from a possible bug there too. What makes me a bit nervous, is that I don't have a clue how to write a test if volatile works (without looking at the generated output). Maybe others have that problem too and therfore such a test doesn't exist in the testsuite of gcc, Regards, Alexander ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] ARM: Avoid compiler optimization for usages of readb, writeb and friends.
Dear Alexander Holler, In message 4d2b1d75.70...@ahsoftware.de you wrote: Beeing kind of a defensive programmer, I still would prefer to use have that __asm__ for write* too. That would at least prevent us from a possible bug there too. So why don't you simply test and, assuming it's working, ACK the patch I submitted yesterday? We should be on the safe side, then, and don't have to care about which mood the current compiler's optimizer might be in or what the POM is. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Suffocating together ... would create heroic camaraderie. -- Khan Noonian Singh, Space Seed, stardate 3142.8 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [MX51EVK] u-boot ECC errors flashing NAND
Hi, Tiago Maluta, 2011/1/10 Tiago Maluta tiago.mal...@gmail.com: Hi, I'm facing ECC errors when flashing u-boot on NAND on MX51EVK-based board. U-Boot nand write command doesn't fill out-of-band (OOB) bytes correctly. I noted this behavior after compare the same u-boot.bin image flashed via ATK (proprietary software from Freescale). I guess is something related to ECC timing. my logs: http://farm6.static.flickr.com/5130/5320148028_7da19d3cf2_o.png http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-fail.txt http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-ok.txt I have looked at your log and it turns out that the issued is caused that BI SWAP unbalance when you do NAND read and write. BI SWAP is used to keep the NAND bad block indicator out of factory, otherwise, the bad block indicator will be overwritten with user data. BR, Jason --tm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Small coding style fix in lib/asm-offsets.c
Stefan Roese wrote:
Signed-off-by: Stefan Roese s...@denx.de
Thanks Stefan.
Acked-by: Michal Simek mon...@monstr.eu
Michal
---
lib/asm-offsets.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 6f253a6..c88f5d4 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -23,10 +23,10 @@ int main(void)
{
/* Round up to make sure size gives nice stack alignment */
DEFINE(GENERATED_GBL_DATA_SIZE,
- (sizeof(struct global_data)+15) ~15);
+ (sizeof(struct global_data) + 15) ~15);
DEFINE(GENERATED_BD_INFO_SIZE,
- (sizeof(struct bd_info)+15) ~15);
+ (sizeof(struct bd_info) + 15) ~15);
return 0;
}
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] asm-offsets: generate bd_t size
Mike Frysinger wrote: On Mon, Jan 10, 2011 at 2:50 AM, Michal Simek wrote: Wolfgang Denk wrote: Mike Frysinger wrote: Some ports set up the board info structure at the same time as the global data structure, and largely keep them together. So generate a define for the board info struct too. Applied, thanks. I am little bit confused. 1. Mike's patch has broken coding style in his patch (space+space15) i retained existing style on purpose. i figured Wolfgang preferred that since he wrote it that way. doesnt matter to me either way. I wanted to do it in the same way but based on my experience Wolfgang would beat me that the patch has broken coding style that's why I wanted to fix it. 2. I sent that patch 3 days before Mike. (It is the longer story) http://lists.denx.de/pipermail/u-boot/2010-December/084095.html i hadnt noticed that. probably because i had already punted the e-mail a few days before i noticed i needed it. otherwise i would have s-o-b your version. No problem. I like that you find out that you need the some parameter as I. Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Blackfin: cmd_gpio port/pin naming
Am Freitag, den 07.01.2011, 17:38 -0500 schrieb Mike Frysinger:
On Friday, January 07, 2011 15:50:30 Andreas Pretzsch wrote:
the Blackfin U-Boot GPIO command (see arch/blackfin/cpu/cmd_gpio.c)
specifies the port/pin naming in the form [p][port]#, e.g. PF11.
The pin portion of the specified GPIO is limited to 0..15.
While this is correct for Blackfins with different bank names (e.g.
BF537 with PF, PG, PH), it's not sufficient for Blackfins with linear
naming like the BF561 (PF0..PF47).
if we cut out the friendly port naming, the rest of the code is no longer
Blackfin specific. so what i had been thinking of doing at some point was
dropping that as a requirement and making it a nice feature so it could be
moved into common/cmd_gpio.c for everyone to use.
Sounds like a good idea to me.
As your code already uses the Linux GPIO conventions and naming (without
the gpio_chip stuff, which is not necessary for a bootloader IMHO), it'd
be a solid base for that.
Mr. Denk, are there any plans for a generic GPIO layer in U-Boot ?
so if we rip out that part and just make it something like:
...
#ifndef name_to_gpio
#define name_to_gpio(name) simple_strtoul(name, NULL, 10)
#endif
Personally, I'd go with arch specific functions, following the Linux
codebase, something like:
#ifdef CONFIG_GENERIC_GPIO
#include asm/gpio.h
#else
static inline int name_to_gpio(char *name)
{
return simple_strtoul(name, NULL, 10);
}
...
#endif
...
ulong pin = name_to_gpio(argv[2]);
if (!gpio_is_valid(pin))
goto usage;
...
although perhaps in your case, we can just change if (pin 15) to if
(!gpio_is_valid(pin)) and forget about the people who do PF34 on parts that
only have PF0..PF15 (they'll instead get like PH4 or whatever).
Would ACK that. Won't break any (correct) scripts out in the field and
solves the BF561 gpio issue with minimal effort.
I'll send a patch the next couple of minutes.
--
carpe noctem engineering
Ingenieurbuero fuer Hard- Software-Entwicklung Andreas Pretzsch
Dipl.-Ing. (FH) Andreas Pretzsch Tel. +49-(0)731-5521572
Hahnengasse 3 Fax: +49-(0)731-5521573
89073 Ulm, Germanyemail: a...@cn-eng.de
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] asm-offsets: generate bd_t size
Dear Wolfgang, Wolfgang Denk wrote: Dear Michal Simek, In message 4d2aba41.7030...@monstr.eu you wrote: I am little bit confused. 1. Mike's patch has broken coding style in his patch (space+space15) Indeed. Sorry for missing this. The existing code had the same issue. If you want, then please submit a patch to clean this up for the whole file. 2. I sent that patch 3 days before Mike. (It is the longer story) http://lists.denx.de/pipermail/u-boot/2010-December/084095.html I like that the patch is in mainline tree because I need it for Microblaze but I don't quite understand that you beat me about coding style and then you apply patch which has broken coding style. I don't care if that patch is Mike's or mine I would like to be sure what are that acceptance rules. Can you please tell me how this can happen? Usually I try to process incoming patches sequentially, but this is not always possible; even if I follow all mail threads this is unreliable as many people submit new versions of their patches without proper linking back to the existing threads. So even when trying to work mostly sequentially, I will frequently jump forward and backward in time. In cases like this (different patches for the same thing, submitted independently by separate people using different Subjects) it is pretty much pure chance which of the submitted patches gets picked up. For me the only important thing is that no patches get dropped unintentionally. If I remember correctly Mike's patch was part of my todo list in patchwork, which was what I processed first, completely independent of submission date. I don't remember if I moved the patch there myself, or if somebody else (Mike?) bestowed it upon me. You don't need to apologize. I really appreciate your work and it is not easy to handle everything. For me is important to fix microblaze code and doesn't matter who has done that patch. My point was that you always look at coding style and would be nice to check it all the time and doesn't matter who send it even you. I understand that it is hard to check your own work. Best regards, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] ARM: Avoid compiler optimization for usages of readb, writeb and friends.
Dear Wolfgang, On 09.01.2011 23:25, Wolfgang Denk wrote: Dear Dirk Behme, In message4d1f1841.5060...@googlemail.com you wrote: Do you like to test the patch in the attachment? I named it 'v4'. Please send patches inline. After some thinking and testing, it seems to me that the volatile optimization issue this patch shall fix is only with the readx() macros. So the idea is to drop all writex() changes done in the v3 version of this patch. With dropping the writex() changes, we would drop all issues we discussed with e.g. the GCC statement-expression and the do while workaround, too. This makes no sense. Even if we experience problems only with read*() at the moment, we should to the Rigth Thing (TM) and fix both the read*() and write*() functions. The question I was thinking about with my patch was what's Right Thing? ;) It's my understanding that we don't fix read*() and write*() because they are broken. We touch them to work around a broken tool chain. We saw that this specific tool chain has issues with read*(). While working around this, we touched write*(), too. This was done in the wrong way. So while read*() was fine, write*() was accidentally broken (with all tool chains), then. So we could (a) do write*() correctly, too (as you do in your patch below) or (b) just don't touch write*() as it isn't needed to work around the read*() tool chain issue (as I proposed in my patch v4) Anyway: Please have a look a the patch I just posted, http://patchwork.ozlabs.org/patch/78056/ I'm fine with that patch. Thanks Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Blackfin: cmd_gpio port/pin naming
On Mon, Jan 10, 2011 at 10:59 AM, Andreas Pretzsch wrote: As your code already uses the Linux GPIO conventions and naming (without the gpio_chip stuff, which is not necessary for a bootloader IMHO), it'd be a solid base for that. Mr. Denk, are there any plans for a generic GPIO layer in U-Boot ? if we arent supporting gpio_chips, then there really isnt much need for common GPIO code. there is already a generic GPIO layer in U-Boot just like in Linux -- include asm/gpio.h and use the normal gpio_xxx set of functions. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Blackfin: cmd_gpio: allow port pins over 15
The pin portion of the specified GPIO was limited to 0..15. While this is correct for Blackfins with different bank names (e.g. BF537 with PF, PG, PH with 16 pins each), it's not sufficient for Blackfins with linear naming like the BF561 (PF0..PF47). Therefore check only for a valid GPIO number. Attn.: Passing a # too high for the port will wrap over to the next port(s), e.g. PA16 = PB0. Not a problem for correct scripts, though. Signed-off-by: Andreas Pretzsch a...@cn-eng.de --- arch/blackfin/cpu/cmd_gpio.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c index e96413b..9fd5a19 100644 --- a/arch/blackfin/cpu/cmd_gpio.c +++ b/arch/blackfin/cpu/cmd_gpio.c @@ -83,7 +83,11 @@ int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* grab the # portion */ ulong pin = simple_strtoul(str_pin + 1, NULL, 10); - if (pin 15) + /* Attn.: passing a # too high for the port will wrap over to +* the next port(s), e.g. PA16 = PB0. +* Check relaxed due to linear ports (e.g. PF0..PF47 @ BF561). +*/ + if (!gpio_is_valid(pin)) goto show_usage; /* grab the pin before we tweak it */ -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Blackfin: cmd_gpio port/pin naming
Am Montag, den 10.01.2011, 11:28 -0500 schrieb Mike Frysinger: On Mon, Jan 10, 2011 at 10:59 AM, Andreas Pretzsch wrote: As your code already uses the Linux GPIO conventions and naming (without the gpio_chip stuff, which is not necessary for a bootloader IMHO), it'd be a solid base for that. Mr. Denk, are there any plans for a generic GPIO layer in U-Boot ? if we arent supporting gpio_chips, then there really isnt much need for common GPIO code. there is already a generic GPIO layer in U-Boot just like in Linux -- include asm/gpio.h and use the normal gpio_xxx set of functions. Well, partly. True for Blackfin and a few ARM/AVR32/NIOS2, albeit the latter have a mixture of specific names like at91_get_gpio_value(), pin_to_controller(), kw_gpio_get_value(), etc. Therefore unifying them to common names and syntax would be the first step. Of course, the gpio_chip approach of Linux is the cleaner way, adding only a few extra bytes of code/ram. I'm fine with both. As time permits, I'm willing to help here. -- carpe noctem engineering Ingenieurbuero fuer Hard- Software-Entwicklung Andreas Pretzsch Dipl.-Ing. (FH) Andreas Pretzsch Tel. +49-(0)731-5521572 Hahnengasse 3 Fax: +49-(0)731-5521573 89073 Ulm, Germanyemail: a...@cn-eng.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFC] armv7: fixloop: don't fixup if location is NULL
Le 10/01/2011 15:04, Minkyu Kang a écrit : How about lcd_setmem function? panel_info is located at bss area, but lcd_setmem access this structure. Is it illegal? This must not be done before relocation. No, please see 360 line of arch/arm/lib/board.c This function is called before relocation. Then it cannot access panel_info, which is not there yet at the time lcd_setmem() executes. You must either move the call to lcd_setmem() to after relocation, or find a way not to depend on BSS. And how about init_func_i2c()? This function is called twice, before the relocation and after relocation. When we use board_i2c_init function then, there is possibility that use symbols in bss because of this function is called after relocation. If it is used both before and after relocation, then it has to respect the strictest case, which is before relocation, and not access BSS. If we ignore this exception, it will be a big constraint. btw, there are any side effects on my patch? I think.. It is just a little safety feature. Regardless of the patch, if your code writes to panel_info or any other BSS variable before relocation it will trash the relocation tables that exist at BSS location at this point. IOW, accessing BSS before relocation is forbidden, not just out of fancy, but for a serious reason. Thanks Minkyu Kang Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [MX51EVK] u-boot ECC errors flashing NAND
On Mon, Jan 10, 2011 at 1:21 PM, Jason Liu liu.h.ja...@gmail.com wrote: Hi, Tiago Maluta, 2011/1/10 Tiago Maluta tiago.mal...@gmail.com: Hi, I'm facing ECC errors when flashing u-boot on NAND on MX51EVK-based board. U-Boot nand write command doesn't fill out-of-band (OOB) bytes correctly. I noted this behavior after compare the same u-boot.bin image flashed via ATK (proprietary software from Freescale). I guess is something related to ECC timing. my logs: http://farm6.static.flickr.com/5130/5320148028_7da19d3cf2_o.png http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-fail.txt http://www.coding.com.br/wp-content/uploads/2011/01/nand-dump-ok.txt I have looked at your log and it turns out that the issued is caused that BI SWAP unbalance when you do NAND read and write. BI SWAP is used to keep the NAND bad block indicator out of factory, otherwise, the bad block indicator will be overwritten with user data. What's your suggestion(s) to fix that? By now I'm comparing with $KERNEL/drivers/mtd/nand/mxc_nand.c [1] to see how to add NFC v3 support on u-boot code. [1] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob_plain;f=drivers/mtd/nand/mxc_nand.c;h=214b03afdd482920adda308e51088092d884a2d1;hb=0c21e3aaf6ae85bee804a325aa29c325209180fd --tm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] powerpc: Add LINK_OFF calls in early C-code.
On Sun, 9 Jan 2011 21:48:47 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Wolfgang Denk w...@denx.de wrote on 2011/01/09 21:29:04:
Dear Joakim Tjernlund,
In message
1292838435-14958-4-git-send-email-joakim.tjernl...@transmode.se you wrote:
Only these 2 call sites depends on fixups for my mpc8321 based
board.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/cpu/mpc83xx/cpu_init.c |2 +-
arch/powerpc/lib/board.c|2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 7a1cae7..88d9dd8 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -507,7 +507,7 @@ int prt_83xx_rsr(void)
sep = ;
for (i = 0; i n; i++)
if (rsr bits[i].mask) {
- printf(%s%s, sep, bits[i].desc);
+ printf(%s%s, sep, LINK_OFF(bits[i].desc));
sep = , ;
}
Is my understanding correct that these changes are sufficient only for
your board, and only for your current configuration? And that your
code would break (resp. require more LINK_OFF fixups) if you would -
for example - decide to enable CONFIG_DISPLAY_AER_FULL in your board
configuration (cf. print_83xx_arb_event() above in the same source
file) ?
It would break only if link address != load address. That is, if you
want to use my new CONFIG_SYS_TRUE_PIC feature and be able to load
u-boot at any address regardless of link address you would
have to add LINK_OFF calls into print_83xx_arb_event() too if
you want to use it.
Doesn't this add a requirement for future generic pre-relocation code to
comply with, to avoid breaking your board?
-Scott
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/7] jz4740 nand driver
On Sun, 9 Jan 2011 18:35:56 +0800 Xiangfu Liu xian...@openmobilefree.net wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 01/05/2011 04:16 AM, Scott Wood wrote: On Wed, Dec 08, 2010 at 12:20:46AM -0600, Xiangfu Liu wrote: + writel(readl(EMC_NFECR) ~EMC_NFECR_ECCE, EMC_NFECR); readl() and other I/O accessors take pointers, not integer addresses. Hi Scott I fixed the others error, only this one I don't know how to do that. can you point me to some example. You need a pointer of appropriate type (u32, in this case) that points to the address. Usually this is done with a struct that describes the register layout (e.g. struct nfc_regs in drivers/mtd/nand/mxc_nand.c). The alternative is to cast the address to a pointer before passing it to the accessor, though Wolfgang doesn't like this. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/9] make the hwconfig buffer deeper
On Sun, 2011-01-09 at 15:00 -0600, Kumar Gala wrote: On Jan 7, 2011, at 5:23 PM, Kumar Gala wrote: On Jan 7, 2011, at 11:52 AM, Wolfgang Denk wrote: Dear York Sun, In message 1294418957.8466.8.ca...@oslab-l1 you wrote: fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=off,addr_hash=false With the buffer size 128, the sub function gets ctlr_intlv=cacheline,bank_intlv=cs0_. It is not because the buffer is not enough, but the stack has been trashed. I have debug log if you need it. This is yet another problem, then. So I figured the problem out and need to rework the hwconfig API to fix it. We need some new versions of the APIs that take a buffer for use early before boot. I've posted: http://patchwork.ozlabs.org/patch/78045/ http://patchwork.ozlabs.org/patch/78046/ Which should resolve the hwconfig issue and not require the patch to bump the size up. I have confirmed your patches. I will drop this patch and resubmit the rest. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/5] jz4740 nand spl files
On Sun, 9 Jan 2011 23:48:01 +0800 Xiangfu Liu xian...@openmobilefree.net wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Scott I don't see any of my comments on v3 addressed or responded to: http://lists.denx.de/pipermail/u-boot/2010-December/083601.html On 12/14/2010 08:05 AM, Scott Wood wrote: nand_spl/nand_boot_jz4740.c | 344 + As I asked last time, is there any reason you can't use the standard nand_boot.c? Your non-SPL NAND driver looks like the type that would work with it. thanks for point out, in next version patches, I will remove the nand_boot_jz4740.c +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) +AFLAGS+= -DCONFIG_NAND_SPL +CFLAGS+= -DCONFIG_NAND_SPL -O2 Are you sure you want -O2 and not -Os? What are the space constraints for this SPL? the nand_spl must less then 8kb. ~~~ #The boot program can load two areas of data from NAND flash to internal SRAM, one is the normal #area up to 8KB starting from NAND flash address 0, the other is the backup area up to 8KB starting #from NAND flash address 0x2000. After reset, the boot program will first read the normal area data #from NAND flash using hardware Reed-Solomon ECC. If no ECC error is detected or ECC error is #correctable, the boot program then branches to internal SRAM at 4 bytes offset. If it detects an #uncorrectable ECC error, it will continue to read the backup area of data from NAND flash using #hardware Reed-Solomon ECC. ~~~ I try to add -Os, then I got some compile error: ~~~ mipsel-openwrt-linux-gcc -g -Os -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x8010 -I/home/xiangfu/workspace/PanGu/u-boot.upstream/include -fno-builtin -ffreestanding -nostdinc -isystem /home/xiangfu/workspace/PanGu/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib/gcc/mipsel-openwrt-linux-uclibc/4.3.3/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -msoft-float -march=4kc -mtune=4kc -mabicalls -mips32 -Wall -Wstrict-prototypes -fno-stack-protector -DCONFIG_NAND_SPL -Os -c -o jz4740_nand.o jz4740_nand.c jz4740_nand.c: In function 'board_nand_init': jz4740_nand.c:298: warning: implicit declaration of function 'usb_boot' cd /home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/board/xburst/nanonote mipsel-openwrt-linux-ld -Bstatic -T /home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/board/xburst/nanonote/u-boot.lds -Ttext 0x8000 $UNDEF_SYM start.o usbboot.o nand_boot.o cpu.o jz4740.o jz_serial.o jz4740_nand.o \ -Map /home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/u-boot-spl.map \ -o /home/xiangfu/workspace/PanGu/u-boot.upstream/nand_spl/u-boot-spl jz4740.o: In function `sdram_init': jz4740.c:(.text+0x60): undefined reference to `memcpy' ~~~ Try -fno-builtin +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin + dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1 + cat $ $(nandobj)junk1 $(nandobj)junk2 + dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3 + cat $(nandobj)junk3 $(nandobj)junk3 $(nandobj)junk4 + dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5 + cat $(nandobj)junk4 $(nandobj)junk5 $(nandobj)junk6 + dd bs=1024 count=256 if=$(nandobj)junk6 of=$@ + rm -f $(nandobj)junk* Again, please explain what's going on here. Other boards don't do this. add comments in Makefile in next patches. Is there no way that can be simplified? It looks like a very elaborate and obfuscated means of getting some zero padding between the SPL and the payload. Other boards do this in a much more straightforward manner. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3] mpc83xx: fix pcie configuration space read/write
On Mon, 10 Jan 2011 20:42:28 +0800
Baidu Boy liucai@gmail.com wrote:
This patch fix a problem for the pcie enumeration when the mpc83xx pcie
controller is
connected with switch or we use both of the two pcie controller
Signed-off-by: Baidu Boy liucai@gmail.com
---
Changes for V2:
- Avoid line wrap in the patch
Changes for V3
- Add space between ) and {
What about my comments?
http://lists.denx.de/pipermail/u-boot/2011-January/084758.html
-Scott
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Art of England Magazine - March 2011 edition - Introduction AdRate Offer until 15th Jan
Hi there Happy New year from all of us over here! We're pleased to inform you that your organisation has been invited to participate in the exclusive Art of England Magazine, March 2011 edition, deadline for which is now just 4 days away. Now seven years old, the Art of England Magazine offers you an effective monthly targeted distribution throughout the UK and abroad, providing you with a lucrative reach to the elusive art and luxury market sectors (full distribution details available here). Participants range from art galleries, dealers, auctioneers, investors and associated professions, through to those who wish to contact this financially capable demographic for their products and services, enjoying the appropriate business development from our sought-after readership. The editorial content too, as you might imagine, is suitably exclusive, and commensurate with the subject matter (current edition available via website below). Regarding your organisation and your potential participation, we're pleased to tell you that the Special Introductory Rate for booking for the coming March 2011 Edition has just been extended slightly, and until 15th January 2011 we would like to offer you the extended reduced 'trial' rate of just £950.00 total for a full A4 page advertisement (list price £1250.00, usual rate card available on request), or £500.00 for a half page, or just £275.00 for a quarter! Once you have seen the effectiveness of this sales and PR channel, we would, of course, hope that you might elect to appear regularly later in subsequent editions. To book for this attractive trial rate offer for the March 2011 Edition, simply reply to this email with your preferred ad size no later than 15th January 2011 to begin reaching this high net worth audience now available to your organisation. Thanks for your time, and we hope to be welcoming you aboard very shortly! Kind regards Deni Parkes for Art of England Magazine T: +44 (0)845 80 55 173 F: +44 (0)207 183 4752 W: www.artofengland.uk.com Media Kit available on request Contracted exclusively by: SKS/Enhanced Media Communications Ltd 1 Farnham Road, Guildford, Surrey GU2 4RG UK ** You were subscribed to this offer list through one of our extensive, but discerning luxury partner networks. ** If you feel you have received this email in error, simply REPLY and SEND with the subject line intact. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Blackfin: skip RAM display for 0 mem systems
Dear Mike Frysinger,
In message 1293028907-16296-1-git-send-email-vap...@gentoo.org you wrote:
+ if (CONFIG_MEM_SIZE) {
+ printf(RAM: );
+ print_size(bd-bi_memsize, \n);
+ }
+
Side note: I see that CONFIG_MEM_SIZE is nowhere documented. Could you
please add an entry for it to the README? TIA.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Actual war is a very messy business. Very, very messy business.
-- Kirk, A Taste of Armageddon, stardate 3193.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] OMAP[34]: remove board config.mk files
Dear John Rigby, In message 1293085997-28564-1-git-send-email-john.ri...@linaro.org you wrote: and define CONFIG_SYS_TEXT_BASE in the board config files Signed-off-by: John Rigby john.ri...@linaro.org --- Changes for v2: Remove bogus tab character in define in v1. --- board/isee/igep0020/config.mk | 33 - board/isee/igep0030/config.mk | 33 - board/logicpd/am3517evm/config.mk | 30 -- board/logicpd/zoom1/config.mk | 33 - board/logicpd/zoom2/config.mk | 33 - board/overo/config.mk | 28 board/ti/beagle/config.mk | 33 - board/ti/evm/config.mk| 33 - board/ti/sdp3430/config.mk| 33 - include/configs/am3517_evm.h |2 ++ include/configs/igep0020.h|2 ++ include/configs/igep0030.h|2 ++ include/configs/omap3_beagle.h|2 ++ include/configs/omap3_evm.h |2 ++ include/configs/omap3_overo.h |2 ++ include/configs/omap3_sdp3430.h |2 ++ include/configs/omap3_zoom1.h |2 ++ include/configs/omap3_zoom2.h |2 ++ 18 files changed, 18 insertions(+), 289 deletions(-) delete mode 100644 board/isee/igep0020/config.mk delete mode 100644 board/isee/igep0030/config.mk delete mode 100644 board/logicpd/am3517evm/config.mk delete mode 100644 board/logicpd/zoom1/config.mk delete mode 100644 board/logicpd/zoom2/config.mk delete mode 100644 board/overo/config.mk delete mode 100644 board/ti/beagle/config.mk delete mode 100644 board/ti/evm/config.mk delete mode 100644 board/ti/sdp3430/config.mk Acked-by: Wolfgang Denk w...@denx.de Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Unix: Some say the learning curve is steep, but you only have to climb it once. - Karl Lehenbauer ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] lib: add crc7 from Linux
Dear Thomas Chou, In message 1293174969-18653-2-git-send-email-tho...@wytron.com.tw you wrote: Crc7 is used to compute mmc spi comamnd packet checksum. s/comamnd/sommand/ Signed-off-by: Thomas Chou tho...@wytron.com.tw Please fix the typos, and provide proper attribution where this code is coming from - see http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign for details. Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Commitment, n.: Commitment can be illustrated by a breakfast of ham and eggs. The chicken was involved, the pig was committed. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] powerpc: Add LINK_OFF calls in early C-code.
Scott Wood scottw...@freescale.com wrote on 2011/01/10 19:24:02:
On Sun, 9 Jan 2011 21:48:47 +0100
Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
Wolfgang Denk w...@denx.de wrote on 2011/01/09 21:29:04:
Dear Joakim Tjernlund,
In message
1292838435-14958-4-git-send-email-joakim.tjernl...@transmode.se you
wrote:
Only these 2 call sites depends on fixups for my mpc8321 based
board.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/powerpc/cpu/mpc83xx/cpu_init.c |2 +-
arch/powerpc/lib/board.c|2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 7a1cae7..88d9dd8 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -507,7 +507,7 @@ int prt_83xx_rsr(void)
sep = ;
for (i = 0; i n; i++)
if (rsr bits[i].mask) {
- printf(%s%s, sep, bits[i].desc);
+ printf(%s%s, sep, LINK_OFF(bits[i].desc));
sep = , ;
}
Is my understanding correct that these changes are sufficient only for
your board, and only for your current configuration? And that your
code would break (resp. require more LINK_OFF fixups) if you would -
for example - decide to enable CONFIG_DISPLAY_AER_FULL in your board
configuration (cf. print_83xx_arb_event() above in the same source
file) ?
It would break only if link address != load address. That is, if you
want to use my new CONFIG_SYS_TRUE_PIC feature and be able to load
u-boot at any address regardless of link address you would
have to add LINK_OFF calls into print_83xx_arb_event() too if
you want to use it.
Doesn't this add a requirement for future generic pre-relocation code to
comply with, to avoid breaking your board?
Yes, but I don't mind if my board breaks from time to time. After all it isn't
in u-boot so I have had to deal with quite a few breakages already.
It is my hope this new feature will spread to other boards as time
pass.
Jocke
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nios2: add gpio_free
Dear Thomas Chou, In message 1293175184-18746-1-git-send-email-tho...@wytron.com.tw you wrote: Signed-off-by: Thomas Chou tho...@wytron.com.tw --- arch/nios2/include/asm/gpio.h |6 ++ board/altera/nios2-generic/gpio.c |5 + 2 files changed, 11 insertions(+), 0 deletions(-) What is this needed for? I don;t see any callers, and the code doesn't do anything useful? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It is dangerous to be sincere unless you are also stupid. - George Bernard Shaw ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nios2: add gpio_free
On Mon, Jan 10, 2011 at 4:27 PM, Wolfgang Denk wrote: Thomas Chou wrote: Signed-off-by: Thomas Chou tho...@wytron.com.tw --- arch/nios2/include/asm/gpio.h | 6 ++ board/altera/nios2-generic/gpio.c | 5 + 2 files changed, 11 insertions(+), 0 deletions(-) What is this needed for? I don;t see any callers, and the code doesn't do anything useful? it's part of the standard GPIO API, his new OpenCores tiny_spi driver is using it, and cmd_gpio.c uses it (which is planning on moving to common code once i remove the tiny Blackfin-specific piece). -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Change the chip name to fit the eth_device struct
Dear Yanjun Yang,
In message aanlktikex3k2sks9fn92gn52dkgludzvxyxpjozx+...@mail.gmail.com you
wrote:
The eth_device.name field length is limited by NAMESIZE,
which is 16 defined in include/net.h. Unfortunately, two
of the names in lan91c96.c are beyond that.
Signed-off-by: YanJun Yang yangyj...@gmail.com
---
drivers/net/lan91c96.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
index 810079f..bd6966e 100644
--- a/drivers/net/lan91c96.c
+++ b/drivers/net/lan91c96.c
@@ -767,8 +767,8 @@ static struct id_type supported_chips[] = {
{8, LAN91C100FD},
{7, LAN91C100},
{5, LAN91C95},
- {4, LAN91C94/LAN91C96},
- {3, LAN91C90/LAN91C92},
+ {4, LAN91C94/96},
+ {3, LAN91C90/92},
Your patch is white space corrupted, applied manually.
Please use git-send-email next time.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Any sufficiently advanced technology is indistinguishable from magic.
- Arthur C. Clarke
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Make sure the chip reset and init right
Dear Yanjun Yang, In message aanlktimos07p88qyrpwl5wzd+eivrebigrqt2q8dt...@mail.gmail.com you wrote: It seems that the chip can only be reset into a known state by using attribute space. The smc_reset and smc_enable function also need more lines to make the chip work. Signed-off-by: YanJun Yang yangyj...@gmail.com --- drivers/net/lan91c96.c | 26 ++ 1 files changed, 22 insertions(+), 4 deletions(-) Your patch is white space corrupted again; we cannot apply it for testing. Please fix. + SMC_outw(dev, LAN91C96_CTR_TE_ENABLE | LAN91C96_CTR_BIT_8, LAN91C96_CONTROL); YOur patch is also line-wrapped. + udelay( 750 ); ... + udelay( 750 ); + attaddr[LAN91C96_ECOR] = ~LAN91C96_ECOR_SRESET; + udelay( 750 ); + attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE; + udelay( 750 ); + /* force 16-bit mode */ + attaddr[LAN91C96_ECSR] = ~LAN91C96_ECSR_IOIS8; + udelay( 750 ); Please omit these bogus spaces arount the function arguments. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If God had wanted us to use the metric system, Jesus would have had 10 apostles. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3 2/7] mpc8xxx: Enable ECC on/off control in hwconfig
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.
Updated hwconfig calls to use local buffer.
Syntax is
hwconfig=fsl_ddr:ecc=on
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/options.c |9 ++---
doc/README.fsl-ddr |7 +++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 0e7097b..55dff43 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -98,10 +98,13 @@ unsigned int populate_memctl_options(int
all_DIMMs_registered,
/* Operational Mode Paramters */
/* Pick ECC modes */
-#ifdef CONFIG_DDR_ECC
- popts-ECC_mode = 1; /* 0 = disabled, 1 = enabled */
-#else
popts-ECC_mode = 0; /* 0 = disabled, 1 = enabled */
+#ifdef CONFIG_DDR_ECC
+ if (hwconfig_sub_f(fsl_ddr, ecc, buf)) {
+ if (hwconfig_subarg_cmp_f(fsl_ddr, ecc, on, buf))
+ popts-ECC_mode = 1;
+ } else
+ popts-ECC_mode = 1;
#endif
popts-ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 1657ef6..9e3c539 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -78,6 +78,13 @@ If the DDR controller supports address hashing, it can be
enabled by hwconfig.
Syntax is:
hwconfig=fsl_ddr:addr_hash=true
+Memory controller ECC on/off
+
+If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
+ECC can be turned on/off by hwconfig.
+
+Syntax is
+hwconfig=fsl_ddr:ecc=off
Memory testing options for mpc85xx
==
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] v3 patch
The following is the v3 patch. Since the last version, the change to hwconfig has been dropped. Adding SPD registers has been dropped as well. Interactive debugging DDR will be submitted later after cleaning up. York Sun ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3 6/7] mpc85xx: Implement workaround for erratum DDR-A003
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c|4 ++
arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 81 +-
arch/powerpc/include/asm/fsl_ddr_sdram.h | 19 +++
include/configs/P4080DS.h|1 +
4 files changed, 104 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d73f3d7..7d9a074 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -47,6 +47,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts(Work-around for Erratum CPU22 enabled\n);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ puts(Work-around for Erratum DDR-A003 enabled\n);
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 5f1848f..1e15111 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -97,6 +97,82 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
temp_sdram_cfg = regs-ddr_sdram_cfg;
temp_sdram_cfg = ~(SDRAM_CFG_MEM_EN);
out_be32(ddr-sdram_cfg, temp_sdram_cfg);
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ if (regs-ddr_sdram_rcw_2 0x00f0) {
+ out_be32(ddr-timing_cfg_2, regs-timing_cfg_2 0xf07f);
+ out_be32(ddr-debug[2], 0x0400);
+ out_be32(ddr-ddr_zq_cntl, regs-ddr_zq_cntl 0x7fff);
+ out_be32(ddr-ddr_wrlvl_cntl, regs-ddr_wrlvl_cntl
0x7fff);
+ out_be32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2 0xffeb);
+ out_be32(ddr-mtcr, 0);
+ out_be32(ddr-debug[12], 0x0015);
+ out_be32(ddr-debug[21], 0x2400);
+ out_be32(ddr-sdram_interval, regs-ddr_sdram_interval
0x);
+ out_be32(ddr-sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI |
SDRAM_CFG_MEM_EN);
+
+ asm volatile(sync;isync);
+ while (!(in_be32(ddr-debug[1]) 0x2))
+ ;
+
+ switch (regs-ddr_sdram_rcw_2 0x00f0) {
+ case 0x:
+ out_be32(ddr-sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x0400 |
+ MD_CNTL_WRCW|
+ MD_CNTL_MD_VALUE(0x02));
+ break;
+ case 0x0010:
+ out_be32(ddr-sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x0400 |
+ MD_CNTL_WRCW|
+ MD_CNTL_MD_VALUE(0x0a));
+ break;
+ case 0x0020:
+ out_be32(ddr-sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x0400 |
+ MD_CNTL_WRCW|
+ MD_CNTL_MD_VALUE(0x12));
+ break;
+ case 0x0030:
+ out_be32(ddr-sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x0400 |
+ MD_CNTL_WRCW|
+ MD_CNTL_MD_VALUE(0x1a));
+ break;
+ default:
+ out_be32(ddr-sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL_CS0_CS1 |
+ 0x0400 |
+ MD_CNTL_WRCW|
+ MD_CNTL_MD_VALUE(0x02));
+ printf(Unsupported RC10\n);
+ break;
+ }
+
+ while (in_be32(ddr-sdram_md_cntl) 0x8000)
+ ;
+ udelay(6);
+ out_be32(ddr-sdram_cfg, temp_sdram_cfg);
+ out_be32(ddr-timing_cfg_2, regs-timing_cfg_2);
+ out_be32(ddr-debug[2], 0x0);
+ out_be32(ddr-ddr_zq_cntl, regs-ddr_zq_cntl);
+ out_be32(ddr-ddr_wrlvl_cntl, regs-ddr_wrlvl_cntl);
+ out_be32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
+
[U-Boot] [Patch v3 5/7] mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.
Enable address parity and RCW by default for RDIMMs.
Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.
Use a formula to calculate rodt_on for timing_cfg_5.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/ddr-gen3.c |6 +
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 250 -
arch/powerpc/cpu/mpc8xxx/ddr/options.c | 308 +-
arch/powerpc/include/asm/fsl_ddr_sdram.h | 18 ++
doc/README.fsl-ddr | 67 +++-
5 files changed, 595 insertions(+), 54 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 23c87af..5f1848f 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -66,6 +66,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(ddr-sdram_cfg_2, regs-ddr_sdram_cfg_2);
out_be32(ddr-sdram_mode, regs-ddr_sdram_mode);
out_be32(ddr-sdram_mode_2, regs-ddr_sdram_mode_2);
+ out_be32(ddr-sdram_mode_3, regs-ddr_sdram_mode_3);
+ out_be32(ddr-sdram_mode_4, regs-ddr_sdram_mode_4);
+ out_be32(ddr-sdram_mode_5, regs-ddr_sdram_mode_5);
+ out_be32(ddr-sdram_mode_6, regs-ddr_sdram_mode_6);
+ out_be32(ddr-sdram_mode_7, regs-ddr_sdram_mode_7);
+ out_be32(ddr-sdram_mode_8, regs-ddr_sdram_mode_8);
out_be32(ddr-sdram_md_cntl, regs-ddr_sdram_md_cntl);
out_be32(ddr-sdram_interval, regs-ddr_sdram_interval);
out_be32(ddr-sdram_data_init, regs-ddr_data_init);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3fec100..ee78caf 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -18,7 +18,28 @@
#include ddr.h
-extern unsigned int picos_to_mclk(unsigned int picos);
+#ifdef CONFIG_MPC85xx
+ #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
+#elif defined(CONFIG_MPC86xx)
+ #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
+#else
+ #error Undefined _DDR_ADDR
+#endif
+
+u32 fsl_ddr_get_version(void)
+{
+ ccsr_ddr_t *ddr;
+ u32 ver_major_minor_errata;
+
+ ddr = (void *)_DDR_ADDR;
+ ver_major_minor_errata = (in_be32(ddr-ip_rev1) 0x) 8;
+ ver_major_minor_errata |= (in_be32(ddr-ip_rev2) 0xFF00) 8;
+
+ return ver_major_minor_errata;
+}
+
+unsigned int picos_to_mclk(unsigned int picos);
+
/*
* Determine Rtt value.
*
@@ -187,7 +208,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
* Avoid writing for DDR I. The new PQ38 DDR controller
* dreams up non-zero default values to be backwards compatible.
*/
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
{
unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
@@ -204,7 +226,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
-#if defined(CONFIG_FSL_DDR3)
+#ifdef CONFIG_FSL_DDR3
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@@ -214,13 +236,21 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
* tAXPD=1, need design to confirm.
*/
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
- act_pd_exit_mclk = picos_to_mclk(tXP);
- /* Mode register MR0[A12] is '1' - fast exit */
- pre_pd_exit_mclk = act_pd_exit_mclk;
- taxpd_mclk = 1;
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
+
+ if (popts-dynamic_power == 0) {/* powerdown is not used */
+ act_pd_exit_mclk = 1;
+ pre_pd_exit_mclk = 1;
+ taxpd_mclk = 1;
+ } else {
+ /* act_pd_exit_mclk = tXARD, see above */
+ act_pd_exit_mclk = picos_to_mclk(tXP);
+ /* Mode register MR0[A12] is '1' - fast exit */
+ pre_pd_exit_mclk = act_pd_exit_mclk;
+ taxpd_mclk = 1;
+ }
#else /* CONFIG_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?
@@ -450,28 +480,34 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
/* DDR SDRAM Register Control Word */
static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t
[U-Boot] [Patch v3 3/7] corenet_ds: Enable ECC for corenet_ds
ECC can be turned on/off by hwconfig without recompiling. So enable it by default. Signed-off-by: York Sun york...@freescale.com --- include/configs/corenet_ds.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 454a30a..49f0a26 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -76,7 +76,7 @@ #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -/*#define CONFIG_DDR_ECC*/ +#defineCONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3 7/7] corenet_ds: Extend board specific parameters
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/include/asm/fsl_ddr_sdram.h |3 +
board/freescale/corenet_ds/ddr.c | 159 +++---
2 files changed, 84 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h
b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 96e308b..6c19d72 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -120,6 +120,9 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define MD_CNTL_WRCW 0x0008
#define MD_CNTL_MD_VALUE(x)(x 0x)
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN0x8000
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 85b6c78..6660b01 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -56,12 +56,14 @@ phys_size_t fixed_sdram(void)
strmhz(buf, sysinfo.freqDDRBus));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
memcpy(ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(ddr_cfg_regs, 1);
#endif
@@ -143,6 +145,7 @@ typedef struct {
u32 datarate_mhz_high;
u32 n_ranks;
u32 clk_adjust;
+ u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
@@ -162,57 +165,61 @@ typedef struct {
/* XXX: Single rank at 800 MHz is OK. */
const board_specific_parameters_t board_specific_parameters[][30] = {
{
- /* memory controller 0 */
- /*lo| hi| num| clk| cpo|wrdata|2T*/
- /* mhz| mhz|ranks|adjst|| delay| */
- { 0, 333,4,6, 7,3, 0},
- {334, 400,4,6, 9,3, 0},
- {401, 549,4,6, 11,3, 0},
- {550, 680,4,1, 10,5, 0},
- {681, 850,4,1, 12,5, 0},
- {851, 1050, 4,1, 12,5, 0},
- {1051, 1250, 4,1, 15,4, 0},
- {1251, 1350, 4,1, 15,4, 0},
- { 0, 333,2,6, 7,3, 0},
- {334, 400,2,6, 9,3, 0},
- {401, 549,2,6, 11,3, 0},
- {550, 680,2,1, 10,5, 0},
- {681, 850,2,1, 12,5, 0},
- {851, 1050, 2,1, 12,5, 0},
- {1051, 1250, 2,1, 15,4, 0},
- {1251, 1350, 2,1, 15,4, 0},
- { 0, 333,1,6, 7,3, 0},
- {334, 400,1,6, 9,3, 0},
- {401, 549,1,6, 11,3, 0},
- {550, 680,1,1, 10,5, 0},
- {681, 850,1,1, 12,5, 0}
+ /*
+* memory controller 0
+* lo| hi| num| clk| wrlvl | cpo |wrdata|2T
+* mhz| mhz|ranks|adjst| start | delay|
+*/
+ { 0, 333,4,5, 7, 0xff,2, 0},
+ {334, 400,4,5, 7, 0xff,2, 0},
+ {401, 549,4,5, 7, 0xff,2, 0},
+ {550, 680,4,5, 7, 0xff,2, 0},
+ {681, 850,4,5, 7, 0xff,2, 0},
+ {851, 1050, 4,5, 7, 0xff,2, 0},
+ {1051, 1250, 4,5, 8, 0xff,2, 0},
+ {1251, 1350, 4,5, 9, 0xff,2, 0},
+ { 0, 333,2,5, 7, 0xff,2, 0},
+ {334, 400,2,5, 7, 0xff,2, 0},
+ {401, 549,2,5, 7, 0xff,2, 0},
+ {550, 680,2,5, 7, 0xff,2, 0},
+ {681, 850,2,5, 7, 0xff,2, 0},
+ {851, 1050, 2,5, 7, 0xff,2, 0},
+ {1051, 1250, 2,5, 7, 0xff,2, 0},
+ {1251, 1350, 2,5, 7, 0xff,2, 0},
+ { 0, 333,1,5, 7, 0xff,2, 0},
+ {334, 400,1,5, 7, 0xff,2, 0},
+ {401, 549,1,5, 7, 0xff,2, 0},
+ {550, 680,1,5, 7, 0xff,2, 0},
+ {681, 850,1,5, 7, 0xff,2, 0}
},
{
- /* memory controller 1 */
- /*lo| hi| num|
[U-Boot] [Patch v3 1/7] mpc8xxx: Display RDIMM if detected
Print a message when a RDIMM is detected.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c| 18 +++---
1 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 029e566..e2e6205 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -98,7 +98,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
*dimm_params,
unsigned int tDQSQ_max_ps = 0;
unsigned int tQHS_ps = 0;
- unsigned int temp1, temp2, temp3;
+ unsigned int temp1, temp2;
unsigned int additive_latency = 0;
#if !defined(CONFIG_FSL_DDR3)
const unsigned int mclk_ps = get_memory_clk_period_ps();
@@ -215,18 +215,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
*dimm_params,
}
outpdimm-all_DIMMs_registered = 0;
+ outpdimm-all_DIMMs_unbuffered = 0;
if (temp1 !temp2) {
outpdimm-all_DIMMs_registered = 1;
- }
-
- outpdimm-all_DIMMs_unbuffered = 0;
- if (!temp1 temp2) {
+ printf(Detected RDIMM(s)\n);
+ } else if (!temp1 temp2) {
outpdimm-all_DIMMs_unbuffered = 1;
- }
-
- /* CHECKME: */
- if (!outpdimm-all_DIMMs_registered
-!outpdimm-all_DIMMs_unbuffered) {
+ printf(Detected UDIMM(s)\n);
+ } else {
printf(ERROR: Mix of registered buffered and unbuffered
DIMMs detected!\n);
}
@@ -237,7 +233,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
*dimm_params,
outpdimm-rcw[j] = dimm_params[0].rcw[j];
for (i = 1; i number_of_dimms; i++)
if (dimm_params[i].rcw[j] !=
dimm_params[0].rcw[j]) {
- temp3 = 1;
+ temp1 = 1;
break;
}
}
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3 4/7] mpc85xx: Adding more registers and options
This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.
Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 10 --
arch/powerpc/include/asm/fsl_ddr_sdram.h | 12
arch/powerpc/include/asm/immap_85xx.h| 21 ++---
board/tqc/tqm85xx/sdram.c|8
4 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index e46dcb7..23c87af 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -9,6 +9,7 @@
#include common.h
#include asm/io.h
#include asm/fsl_ddr_sdram.h
+#include asm/processor.h
#if (CONFIG_CHIP_SELECTS_PER_CTRL 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -79,6 +80,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(ddr-ddr_sr_cntr, regs-ddr_sr_cntr);
out_be32(ddr-ddr_sdram_rcw_1, regs-ddr_sdram_rcw_1);
out_be32(ddr-ddr_sdram_rcw_2, regs-ddr_sdram_rcw_2);
+ out_be32(ddr-ddr_cdr1, regs-ddr_cdr1);
+ out_be32(ddr-ddr_cdr2, regs-ddr_cdr2);
+ out_be32(ddr-err_disable, regs-err_disable);
+ out_be32(ddr-err_int_en, regs-err_int_en);
+ for (i = 0; i 32; i++)
+ out_be32(ddr-debug[i], regs-debug[i]);
/* Set, but do not enable the memory */
temp_sdram_cfg = regs-ddr_sdram_cfg;
@@ -93,8 +100,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if in_be32(ddr-sdram_cfg) 24) 0x7) == SDRAM_TYPE_DDR2)
in_be32(ddr-sdram_cfg) 0x8) {
/* set DEBUG_1[31] */
- u32 temp = in_be32(ddr-debug_1);
- out_be32(ddr-debug_1, temp | 1);
+ setbits_be32(ddr-debug[0], 1);
}
#endif
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h
b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index c6258db..462e918 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -120,6 +120,11 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
unsigned int ddr_eor;
+ unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
+ unsigned int err_disable;
+ unsigned int err_int_en;
+ unsigned int debug[32];
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
@@ -175,6 +180,7 @@ typedef struct memctl_options_s {
/* mirrior DIMMs for DDR3 */
unsigned int mirrored_dimm;
unsigned int quad_rank_present;
+ unsigned int ap_en; /* address parity enable for RDIMM */
/* Global Timing Parameters */
unsigned int cas_latency_override;
@@ -210,6 +216,12 @@ typedef struct memctl_options_s {
unsigned int zq_en;
/* Write leveling */
unsigned int wrlvl_en;
+ /* RCW override for RDIMM */
+ unsigned int rcw_override;
+ unsigned int rcw_1;
+ unsigned int rcw_2;
+ /* control register 1 */
+ unsigned int ddr_cdr1;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 30c64eb..0069d50 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -222,25 +222,8 @@ typedef struct ccsr_ddr {
u32 capture_ext_address;/* Error Extended Addr Capture */
u32 err_sbe;/* Single-Bit ECC Error Management */
u8 res11[164];
- u32 debug_1;
- u32 debug_2;
- u32 debug_3;
- u32 debug_4;
- u32 debug_5;
- u32 debug_6;
- u32 debug_7;
- u32 debug_8;
- u32 debug_9;
- u32 debug_10;
- u32 debug_11;
- u32 debug_12;
- u32 debug_13;
- u32 debug_14;
- u32 debug_15;
- u32 debug_16;
- u32 debug_17;
- u32 debug_18;
- u8 res12[184];
+ u32 debug[32]; /* debug_1 to debug_32 */
+ u8 res12[128];
} ccsr_ddr_t;
#define DDR_EOR_RD_BDW_OPT_DIS 0x8000 /* Read BDW Opt. disable */
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 503c5e5..d2af127 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -220,7 +220,7 @@ long int sdram_setup (int casl)
* 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
*training
*/
- ddr-debug_3 |= 0x0400;
+ ddr-debug[2] |=
Re: [U-Boot] [PATCH 01/28] MAINTAINERS: sort Blackfin entries
Dear Mike Frysinger, In message 1293425300-27644-2-git-send-email-vap...@gentoo.org you wrote: Signed-off-by: Mike Frysinger vap...@gentoo.org --- MAINTAINERS | 49 ++--- 1 files changed, 22 insertions(+), 27 deletions(-) Already applied. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The most difficult thing in the world is to know how to do a thing and to watch someone else doing it wrong, without commenting. -- T.H. White ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/28] Blackfin: fix bd_t handling
Dear Mike Frysinger, In message 201012271142.17334.vap...@gentoo.org you wrote: it isnt a problem to have the parens, and it keeps things sane if someone does something like: #define CONFIG_SYS_BD_INFO_ADDR SOME_DEFINE + 0x1000 This would be a violation of basic rules of defensive coding. Please drop these parens. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I'm a programmer: I don't buy software, I write it. -- Tom Christiansen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 23/28] Blackfin: bf506f-ezkit: new board port
Dear Mike Frysinger, In message 1293425300-27644-24-git-send-email-vap...@gentoo.org you wrote: Signed-off-by: Mike Frysinger vap...@gentoo.org --- board/bf506f-ezkit/Makefile | 54 +++ board/bf506f-ezkit/bf506f-ezkit.c | 27 + boards.cfg|1 + include/configs/bf506f-ezkit.h| 106 + 4 files changed, 188 insertions(+), 0 deletions(-) create mode 100644 board/bf506f-ezkit/Makefile create mode 100644 board/bf506f-ezkit/bf506f-ezkit.c create mode 100644 include/configs/bf506f-ezkit.h Entry to MAINTAINERS missing. ... +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) + +#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) Lines too long. +#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END) +#define CONFIG_SYS_MONITOR_LEN (4 * 1024) +#define CONFIG_SYS_MALLOC_LEN(4 * 1024) Sure that 4 KiB is sufficient for these two? +#undef CONFIG_BOOTM_LINUX + + +#endif Only one blank line, please. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The only way to learn a new programming language is by writing pro- grams in it.- Brian Kernighan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 27/28] Blackfin: ldrinfo: new command
Dear Mike Frysinger, In message 1293425300-27644-28-git-send-email-vap...@gentoo.org you wrote: Simple command to decode/check an LDR image before we try to boot it. Signed-off-by: Mike Frysinger vap...@gentoo.org --- common/Makefile |1 + common/cmd_ldrinfo.c | 192 ++ 2 files changed, 193 insertions(+), 0 deletions(-) create mode 100644 common/cmd_ldrinfo.c diff --git a/common/Makefile b/common/Makefile index abea91c..9cc8dd1 100644 --- a/common/Makefile +++ b/common/Makefile @@ -105,6 +105,7 @@ COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o +COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o COBJS-y += cmd_load.o COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o Please add documentation for the new CONFIG_CMD_LDRINFO option. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Life is a process, not a principle, a mystery to be lived, not a problem to be solved. - Gerard Straub, television producer and author (stolen from Frank Herbert??) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board
Dear Alex Dubov, In message 754013.38475...@web37602.mail.mud.yahoo.com you wrote: You should use get_ram_size(). I still need to call setup_ddr_tlbs because get_ram_size won't do it for me. So what get_ram_size actually does? It checks the size of available memory and performs a simple, fast and non-destuctive memory test on the way. NAK. Please use proper I/O accessors. Do you mean out_be32 and friends? Right. In which case, why are not these used when writing config values to DDR registers (for instance) even in some very recently added boards, such as p2020ds? Because this escaped review? Can you please point out where this was missed, so it can be fixed? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The universe, they said, depended for its operation on the balance of four forces which they identified as charm, persuasion, uncertainty and bloody-mindedness. -- Terry Pratchett, The Light Fantastic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board
Dear Alex Dubov, In message 294951.51594...@web37601.mail.mud.yahoo.com you wrote: Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548 processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash memory, real time clock and additional serial EEPROM on i2c bus (enabled). USB controller is available, but not presently enabled. Additional board information is available at: http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx Environment is configured to preceed the actual u-boot image so that it's located at the beginning of flash erase block (made necessary by the recent changes to the embedded environment handling). Signed-off-by: Alex Dubov oa...@yahoo.com --- MAINTAINERS|3 + board/mercury/mpq101/Makefile | 53 + board/mercury/mpq101/config.mk |6 + board/mercury/mpq101/law.c | 55 ++ board/mercury/mpq101/mpq101.c | 146 ++ board/mercury/mpq101/tlb.c | 82 boards.cfg |1 + include/configs/mpq101.h | 410 8 files changed, 756 insertions(+), 0 deletions(-) create mode 100644 board/mercury/mpq101/Makefile create mode 100644 board/mercury/mpq101/config.mk create mode 100644 board/mercury/mpq101/law.c create mode 100644 board/mercury/mpq101/mpq101.c create mode 100644 board/mercury/mpq101/tlb.c create mode 100644 include/configs/mpq101.h I'm not going to review this again. Why don't you explain what was changed compared to the previous version? Please see the second bullet at http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions for a detailed explanation. And you still have a board/mercury/mpq101/config.mk even though I asked you to get rid of it. Please also run your patch through checkpatch.pl, remove C++ comments, remove deads code, do not #undef variables that are not #defined, use TAB for vertical alignment and fix other Coding Style issues. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de How can you tell when sour cream goes bad? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-BOOT] [PATCH V2] NAND: add the ability to directly write yaffs image
On Thu, Jan 06, 2011 at 11:11:58AM +0800, Lei Wen wrote: This patch add addition suffix to nand write to give the uboot the power to directly burn the yaffs image to nand. Signed-off-by: Lei Wen lei...@marvell.com --- V2: fix compile warning, and add CONFIG_CMD_NAND_YAFFS to reduce code when not use this function. common/cmd_nand.c| 15 +- drivers/mtd/nand/nand_util.c | 63 - include/nand.h |2 +- 3 files changed, 70 insertions(+), 10 deletions(-) Applied to u-boot-nand-flash. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 23/28] Blackfin: bf506f-ezkit: new board port
On Monday, January 10, 2011 17:33:42 Wolfgang Denk wrote: Mike Frysinger you wrote: board/bf506f-ezkit/Makefile | 54 +++ board/bf506f-ezkit/bf506f-ezkit.c | 27 + boards.cfg|1 + include/configs/bf506f-ezkit.h| 106 + 4 files changed, 188 insertions(+), 0 deletions(-) create mode 100644 board/bf506f-ezkit/Makefile create mode 100644 board/bf506f-ezkit/bf506f-ezkit.c create mode 100644 include/configs/bf506f-ezkit.h Entry to MAINTAINERS missing. must of lost when rebasing +#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END) +#define CONFIG_SYS_MONITOR_LEN (4 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024) Sure that 4 KiB is sufficient for these two? yes ... the port is pretty thin -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/28] Blackfin: fix bd_t handling
On Monday, January 10, 2011 17:28:23 Wolfgang Denk wrote: Mike Frysinger wrote: it isnt a problem to have the parens, and it keeps things sane if someone does something like: #define CONFIG_SYS_BD_INFO_ADDR SOME_DEFINE + 0x1000 This would be a violation of basic rules of defensive coding. Please drop these parens. i dont see how these two statements are compatible. defensive coding would mean i keep the parens. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 27/28 v2] Blackfin: ldrinfo: new command
Simple command to decode/check an LDR image before we try to boot it.
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
v2
- add README note
README |1 +
common/Makefile |1 +
common/cmd_ldrinfo.c | 192 ++
3 files changed, 194 insertions(+), 0 deletions(-)
create mode 100644 common/cmd_ldrinfo.c
diff --git a/README b/README
index d7a23cd..0b69539 100644
--- a/README
+++ b/README
@@ -648,6 +648,7 @@ The following options need to be configured:
CONFIG_CMD_ITEST Integer/string test of 2 values
CONFIG_CMD_JFFS2* JFFS2 Support
CONFIG_CMD_KGDB * kgdb
+ CONFIG_CMD_LDRINFOldrinfo (display Blackfin loader)
CONFIG_CMD_LOADB loadb
CONFIG_CMD_LOADS loads
CONFIG_CMD_MD5SUM print md5 message digest
diff --git a/common/Makefile b/common/Makefile
index 048df0c..4555716 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -105,6 +105,7 @@ COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
+COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
COBJS-y += cmd_load.o
COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
diff --git a/common/cmd_ldrinfo.c b/common/cmd_ldrinfo.c
new file mode 100644
index 000..2aa56bd
--- /dev/null
+++ b/common/cmd_ldrinfo.c
@@ -0,0 +1,192 @@
+/*
+ * U-boot - ldrinfo
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include config.h
+#include common.h
+#include command.h
+
+#include asm/blackfin.h
+#include asm/mach-common/bits/bootrom.h
+
+static uint32_t ldrinfo_header(const void *addr)
+{
+ uint32_t skip = 0;
+
+#if defined(__ADSPBF561__)
+ /* BF56x has a 4 byte global header */
+ uint32_t header, sign;
+ static const char * const spi_speed[] = {
+ 500K, 1M, 2M, ??,
+ };
+
+ memcpy(header, addr, sizeof(header));
+
+ sign = (header GFLAG_56X_SIGN_MASK) GFLAG_56X_SIGN_SHIFT;
+ printf(Header: %08X ( %s-bit-flash wait:%i hold:%i spi:%s %s)\n,
+ header,
+ (header GFLAG_56X_16BIT_FLASH) ? 16 : 8,
+ (header GFLAG_56X_WAIT_MASK) GFLAG_56X_WAIT_SHIFT,
+ (header GFLAG_56X_HOLD_MASK) GFLAG_56X_HOLD_SHIFT,
+ spi_speed[(header GFLAG_56X_SPI_MASK) GFLAG_56X_SPI_SHIFT],
+ sign == GFLAG_56X_SIGN_MAGIC ? : !!hdrsign!! );
+
+ skip = 4;
+#endif
+
+ /* |Block @ 12345678: 12345678 12345678 12345678 12345678 | */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)
|| \
+defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
|| \
+defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__)
+ printf( Address CountFlags\n);
+#else
+ printf( BCodeAddress CountArgument\n);
+#endif
+
+ return skip;
+}
+
+struct ldr_flag {
+ uint16_t flag;
+ const char *desc;
+};
+
+static uint32_t ldrinfo_block(const void *base_addr)
+{
+ uint32_t count;
+
+ printf(Block @ %08X: , (uint32_t)base_addr);
+
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)
|| \
+defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
|| \
+defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__)
+
+ uint32_t addr, pval;
+ uint16_t flags;
+ int i;
+ static const struct ldr_flag ldr_flags[] = {
+ { BFLAG_53X_ZEROFILL,zerofill },
+ { BFLAG_53X_RESVECT, resvect },
+ { BFLAG_53X_INIT,init },
+ { BFLAG_53X_IGNORE, ignore},
+ { BFLAG_53X_COMPRESSED, compressed},
+ { BFLAG_53X_FINAL, final },
+ };
+
+ memcpy(addr, base_addr, sizeof(addr));
+ memcpy(count, base_addr+4, sizeof(count));
+ memcpy(flags, base_addr+8, sizeof(flags));
+
+ printf(%08X %08X %04X ( , addr, count, flags);
+
+ for (i = 0; i ARRAY_SIZE(ldr_flags); ++i)
+ if (flags ldr_flags[i].flag)
+ printf(%s , ldr_flags[i].desc);
+
+ pval = (flags BFLAG_53X_PFLAG_MASK) BFLAG_53X_PFLAG_SHIFT;
+ if (pval)
+ printf(gpio%i , pval);
+ pval = (flags BFLAG_53X_PPORT_MASK) BFLAG_53X_PPORT_SHIFT;
+ if (pval)
+ printf(port%c , 'e' + pval);
+
+ if (flags BFLAG_53X_ZEROFILL)
+ count = 0;
+ if (flags BFLAG_53X_FINAL)
+ count = 0;
+ else
+ count +=
[U-Boot] Unknown image format!
I am trying to switch from writing my JFFS2 filesystem to flash using an NFS mounted root filesystem to creating and installing a JFFS2 image. The reason I am doing this is so I can use sumtool on the JFFS2 image and speed up my boot time. When I use the JFFS2 image, I see the following while booting up the first time: VFS: Mounted root (jffs2 filesystem). Freeing unused kernel memory: 120k init INFO: task pdflush:9 blocked for more than 120 seconds. echo 0 /proc/sys/kernel/hung_task_timeout_secs disables this message. pdflush D 0 9 2 Call Trace: [C7C5FE10] [C000D464] __switch_to+0x4c/0x6c [C7C5FE30] [C0260590] schedule+0x1a4/0x378 [C7C5FE80] [C0262610] rwsem_down_failed_common+0xbc/0x250 [C7C5FEB0] [C0262810] rwsem_down_read_failed+0x2c/0x44 [C7C5FEE0] [C026186C] down_read+0x38/0x3c [C7C5FEF0] [C006EF3C] sync_supers+0x88/0x138 [C7C5FF10] [C00519AC] wb_kupdate+0x50/0x14c [C7C5FF70] [C005219C] pdflush+0x164/0x260 [C7C5FFD0] [C0033924] kthread+0x48/0x84 [C7C5FFF0] [C0006038] kernel_thread+0x44/0x60 *** Running rc.modules *** Running rc.serial *** Attempting to start S15inet In addition, after it does boot up and I do a write, the system hangs and u-boot won't even run after I power cycle the board. I see that when I run iminfo after downloading the image to RAM that it reports Unknown image format! : = erase fc04 ffef .. done Erased 502 sectors = tftpboot 0010 jan10am.img Using e1000#0 device TFTP from server 10.174.100.101; our IP address is 10.174.100.120 Filename 'jan10am.img'. Load address: 0x10 Loading: # # # # # # # # # # # # # # # # # # ## done Bytes transferred = 18026200(1130ed8 hex) = iminfo ## Checking Image at 0010 ... Unknown image format! Does iminfo saying Unknown image format! indicate a problem with my JFFS2 image? Could this cause the long delay when booting after Freeing unused kernel memory? I am using a 2.6.26 kernel with ppc. I see the same behavior using both u-boot-1.3.4 and u-boot-2010.09. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board
Dear Alex Dubov, In message 328503.45731...@web37602.mail.mud.yahoo.com you wrote: Can you please point out where this was missed, so it can be fixed? Some of the boards in question: atum8548 mpc8540 pm854/6 sbc8560 sbc8641d socrates mpc8536ds mpc8540ads mpc8560ads mpc8572ds mpc8610hpdc mpc8641hpcn p2020ds tqm85xx Could you please be a bit more specific, i. e. like quoting file names and line numbers? Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If it has syntax, it isn't user friendly. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boards
CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we should also allow the kernel image to be up to 16M decompressed. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- include/configs/MPC8536DS.h |3 ++- include/configs/MPC8540ADS.h |3 ++- include/configs/MPC8541CDS.h |3 ++- include/configs/MPC8544DS.h |3 ++- include/configs/MPC8548CDS.h |3 ++- include/configs/MPC8555CDS.h |3 ++- include/configs/MPC8560ADS.h |3 ++- include/configs/MPC8568MDS.h |3 ++- include/configs/MPC8569MDS.h |6 +++--- include/configs/MPC8572DS.h |3 ++- include/configs/P1022DS.h|3 ++- include/configs/P1_P2_RDB.h |3 ++- include/configs/P2020DS.h|3 ++- include/configs/corenet_ds.h |3 ++- 14 files changed, 29 insertions(+), 16 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 94a542c..d1ae35d 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -718,6 +718,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 9386f64..8b3aff8 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao x.x...@motorola.com * @@ -424,6 +424,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 12ce6f7..7101230 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -436,6 +436,7 @@ extern unsigned long get_clock_freq(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index dc821a3..62bac6d 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010 Freescale Semiconductor, Inc. + * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -456,6 +456,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4c5b998..2b4d234 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 2010 Freescale Semiconductor. + * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -494,6 +494,7 @@ extern unsigned long get_clock_freq(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 334a410..106034d 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who
Re: [U-Boot] [PATCH v2 1/7] powerpc/8xxx: Refactor SRIO initialization into common code
On Jan 9, 2011, at 3:16 PM, Kumar Gala wrote: Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_HAS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- * Removed ifdef protection around externs per Sergei applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] powerpc/85xx: Convert MPC8548CDS to use common SRIO init code
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- board/freescale/mpc8548cds/law.c |5 + board/freescale/mpc8548cds/tlb.c |9 - include/configs/MPC8548CDS.h | 15 --- 3 files changed, 13 insertions(+), 16 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/7] powerpc/85xx: Convert MPC8569MDS to use common SRIO init code
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- board/freescale/mpc8569mds/law.c |3 +-- include/configs/MPC8569MDS.h | 12 2 files changed, 9 insertions(+), 6 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] powerpc/85xx: Convert MPC8568MDS to use common SRIO init code
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- board/freescale/mpc8568mds/law.c |3 +-- include/configs/MPC8568MDS.h | 12 2 files changed, 9 insertions(+), 6 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/7] powerpc/86xx: Enable common SRIO init code
On Jan 9, 2011, at 3:16 PM, Kumar Gala wrote: Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- * Removed ifdef protection around extern per Sergei * Added missing call to srio_init arch/powerpc/cpu/mpc86xx/cpu_init.c |7 ++- arch/powerpc/cpu/mpc86xx/fdt.c|7 ++- arch/powerpc/include/asm/immap_86xx.h |4 +++- 3 files changed, 15 insertions(+), 3 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7] powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- board/freescale/mpc8641hpcn/law.c |5 + include/configs/MPC8641HPCN.h | 30 +- 2 files changed, 14 insertions(+), 21 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code
On Jan 6, 2011, at 10:58 AM, Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@kernel.crashing.org CC: Paul Gortmaker paul.gortma...@windriver.com --- board/sbc8641d/law.c |1 - include/configs/sbc8641d.h | 15 +-- 2 files changed, 9 insertions(+), 7 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/85xx: Add SRIO support to P2020DS
On Jan 6, 2011, at 11:05 AM, Kumar Gala wrote: From: Li Yang le...@freescale.com The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- include/configs/P2020DS.h | 24 +++- 1 files changed, 23 insertions(+), 1 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/7] powerpc/8xxx: Refactor SRIO initialization into common code
Dear Kumar Gala, In message 1294607813-27723-1-git-send-email-ga...@kernel.crashing.org you wrote: Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_HAS_SRIO - Chip has SRIO or not We don't use a CONFIG_SYS_HAS_* normally; can we use plain CONFIG_SYS_SRIO instead? (yes, I am aware of the CONFIG_SYS_HAS_SERDES precedent, which escaped my attantion during review - that should be fixed, too). CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) These need to be documented (README). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Wagner's music is better than it sounds. - Mark Twain ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 0/5] Add Pantheon soc and dkb board support
This patch set add the Pantheon soc and dkb board support. V2: This patch seris update the seperate mv_common part as suggested. V3: Fix config.h include place and copyright claim year. Lei Wen (5): mv: seperate kirkwood and armada from common setting ARM: Add Support for Marvell Pantheon Familiy SoCs serial: add pantheon soc support mvmfp: add MFP configuration support for PANTHEON Pantheon: Add Board Support for Marvell dkb board MAINTAINERS |4 + arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++ arch/arm/cpu/arm926ejs/pantheon/dram.c| 130 arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 + arch/arm/include/asm/arch-armada100/config.h | 50 ++ arch/arm/include/asm/arch-kirkwood/config.h | 145 ++ arch/arm/include/asm/arch-pantheon/config.h | 44 ++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++ arch/arm/include/asm/arch-pantheon/mfp.h | 42 + arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++ board/Marvell/dkb/Makefile| 51 ++ board/Marvell/dkb/dkb.c | 53 +++ boards.cfg|1 + drivers/gpio/mvmfp.c |2 + drivers/serial/serial.c |2 + include/configs/aspenite.h|1 + include/configs/dkb.h | 64 include/configs/mv-common.h | 147 +++--- 19 files changed, 1071 insertions(+), 126 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c create mode 100644 arch/arm/include/asm/arch-armada100/config.h create mode 100644 arch/arm/include/asm/arch-kirkwood/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h create mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h create mode 100644 board/Marvell/dkb/Makefile create mode 100644 board/Marvell/dkb/dkb.c create mode 100644 include/configs/dkb.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 2/5] ARM: Add Support for Marvell Pantheon Familiy SoCs
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
SoC versions Supported:
1) PANTHEON920 (TD)
2) PANTHEON910 (TTC)
Signed-off-by: Lei Wen lei...@marvell.com
---
arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++
arch/arm/cpu/arm926ejs/pantheon/dram.c| 130
arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 +
arch/arm/include/asm/arch-pantheon/config.h | 44 ++
arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++
arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++
7 files changed, 635 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile
create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c
create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c
create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c
create mode 100644 arch/arm/include/asm/arch-pantheon/config.h
create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h
create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile
b/arch/arm/cpu/arm926ejs/pantheon/Makefile
new file mode 100644
index 000..ab94985
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor www.marvell.com
+# Written-by: Lei Wen lei...@marvell.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS-y= cpu.o timer.o dram.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
new file mode 100644
index 000..9ddc77c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Lei Wen lei...@marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include asm/arch/pantheon.h
+#include asm/io.h
+
+#define UARTCLK14745KHZ(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID(18)
+#define L2C_RAM_SEL(14)
+
+int arch_cpu_init(void)
+{
+ u32 val;
+ struct panthcpu_registers *cpuregs =
+ (struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+ struct panthapb_registers *apbclkres =
+ (struct panthapb_registers*) PANTHEON_APBC_BASE;
+
+ struct panthmpmu_registers *mpmu =
+ (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+
+ /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
+ val = readl(cpuregs-cpu_conf);
+ val = val | SET_MRVL_ID;
+ writel(val, cpuregs-cpu_conf);
+
+ /* Turn on clock gating (PMUM_CCGR) */
+ writel(0x, mpmu-ccgr);
+
+ /* Turn on clock gating (PMUM_ACGR) */
+
