Re: [U-Boot] FDT driver initialization function declaration

[Simon Glass]

Hi Michal,

On Tue, Jul 10, 2012 at 3:49 PM, Michal Simek  wrote:
> On 07/10/2012 03:18 PM, Simon Glass wrote:
>>
>> Hi Michal,
>>
>>
>> On Tue, Jul 10, 2012 at 12:23 PM, Michal Simek > > wrote:
>>
>> Hi Simon, Wolfgang and others,
>>
>> just want to open new topic about FDT driver initialization function
>> declaration.
>>
>> There are some drivers which can be simple move to fdt initialization.
>> I have in my mind ethernet drivers and then systemace (I have ported
>> it).
>>
>> Ethernet drivers use include/netdev.h file where all initialization
>> functions are declared.
>>
>> For example:
>>
>> diff --git a/include/netdev.h b/include/netdev.h
>> index 4724717..96e62ee 100644
>> --- a/include/netdev.h
>> +++ b/include/netdev.h
>> @@ -105,6 +105,10 @@ int xilinx_emaclite_initialize(bd___t *bis,
>> unsigned long base_addr,
>>
>>   int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int
>> flags,
>>  unsigned long
>> ctrl_addr);
>>
>> +#ifdef CONFIG_OF_CONTROL
>> +int xilinx_emaclite_init(bd_t *bis);
>> +#endif
>>
>>
>> I don't think you need the #ifdef here.
>
>
> Probably not but why not to protect it.

Just an unnecessary #ifdef IMO.

>
>
>
>>
>> +
>>   /*
>>* As long as the Xilinx xps_ll_temac ethernet driver has not its
>> own interface
>>* exported by a public hader file, we need a global definition at
>> this point.
>>
>>
>> But where is the right place for systemace FDT initialization?
>> include/fdtdec.h?
>>
>>
>> or create new header and include it to fdtdec.h?
>>
>>
>> Yes, but don't include it in fdtdec.h. Why do you need to?
>
>
> I am not saying that I want to do, just saying that there should be one file
> which
> cover all of these. Or of course if new device model will be used this will
> be probably solved there.

Normally if there is driver code that must be called elsewhere we add
it to a header in include/. Yes the device model will change/improve
this at some point.

>
>
>>
>>
>> In this case it makes sense to add all FDT driven configuration to one
>> header file
>> to see what drivers can be used. Even for network drivers.
>> Also listing all required parameters can be capture there.
>>
>> What do you think?
>>
>>
>> That's the idea of the list of compatible strings in fdtdec.c / h.
>>
>> I would suggest for now, just doing ad-hoc init using a special function
>> call,
>
>  or whatever else makes things easy. Yes fdt can potential clean all that
> stuff up,
>  but not without the device model. I think once we have the device model we
> can revisit
>  this (and I look forward to it). For now, just think of fdt as a way of
> enabling a driver,
>  or specifying the number of ports the driver controls, rather than a way of
> deciding which
>  driver inits get called.

FDT certainly fits very nicely with device model, but it doesn't
require it. You can just have:

some_device_probe(const void *blob)

and call that from somewhere to make it look in the FDT for its info
and initialize if it finds it.

>
> Going to delay this FDT stuff till I get some more information about new
> device-model.
>
> Thanks for your comments,
>
> Michal
>
> --
> Michal Simek, Ing. (M.Eng)
> w: www.monstr.eu p: +42-0-721842854
> Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
> Microblaze U-BOOT custodian

Regards,
Simon
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Re: [U-Boot] [PATCH 1/2 v2] SDHC/MMC: fix the wrong infomation after change SD card

[Marek Vasut]

Dear Andy Fleming,

> On Wed, Jul 11, 2012 at 4:29 AM, Huang Changming-R66093
> 
>  wrote:
> > Hi, Andy,
> > There is not any feedback for very long time,
> > Could it be applied to the u-boot?
> 
> I'm afraid I have to reject this patch. We need to find a better
> solution to the two problems:
> 
> 1) We want to change cards and still have mmc commands work
> 2) We don't want eMMC devices to be slowed down by constantly
> re-initializing their cards.
> 
> Normally, I would err on the side of #1, but there's a simple
> workaround. If you replace the card, execute "mmc rescan", and the
> card will be reinitialized. Please let me know if that workaround
> doesn't work. I hope, in the future, we'll have some code which makes
> both possible, by being able to detect that a card has been changed,
> but for now I think the current system is reasonably satisfactory to
> both cases #1 and #2.

Andy, I don't want to be a bastard, but do you happen to be overloaded? Or what 
is the exact reason your replies to patches are so slow?

Best regards,
Marek Vasut
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Re: [U-Boot] uboot for zyxel nsa320

[Luka Perkov]

Hi,

On Fri, Jul 13, 2012 at 12:43:13PM -0500, kqt4a...@gmail.com wrote:
> I have a new Zyxel NSA320. It is unmodified. At the uboot prompt I
> printenv and save all environment variables. Next I pulled code from
> https://github.com/psch2/uboot-nsa320, compiled and used kwboot to
> load new uboot. No problems so far. Now if I reload all environment
> variables I saved and boot the kernel loads but does not execute.
> Any ideas?
> 
> NSA320> boot
> 
> NAND read: device 0 offset 0xc8, size 0xa0
> 10485760 bytes read: OK
> ## Booting kernel from Legacy Image at 0200 ...
> Image Name: Linux-2.6.31.8
> Image Type: ARM Linux Kernel Image (uncompressed)
> Data Size: 5909960 Bytes = 5.6 MiB
> Load Address: 8000
> Entry Point: 8000
> Verifying Checksum ... OK
> Loading Kernel Image ... OK
> OK
> 
> Starting kernel ...
> 
> Uncompressing 
> Linux...
> done, booting the kernel.

You are probably missing console=ttyS0,115200 in your bootargs
environment variable. What is the output of "printenv" ?

Luka
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Scott Wood]

On 07/13/2012 06:01 PM, Wolfgang Denk wrote:
> Dear Timur Tabi,
> 
> In message <500098f6.8050...@freescale.com> you wrote:
>>
>> I honestly don't see what's wrong with checking the CRC in the old
>> location, and using it if it's valid.  Like I said, we already
> 
> You are interpreting something which can be random data.
> 
>> if (e.version == 0)
>>  crc_offset = 0x72;
>>
>> So here we're reading the 'version' field before we validate the data,
>> because we need to check the version to know where the CRC is.
> 
> Argh.  More crap ...

And how would you do it?  You have to look at *something* first, and
whatever that is could be a coincidence if you think people are going to
stuff arbitrary data into the EEPROM.

-Scott

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Wolfgang Denk]

Dear Timur Tabi,

In message <500098f6.8050...@freescale.com> you wrote:
> 
> I honestly don't see what's wrong with checking the CRC in the old
> location, and using it if it's valid.  Like I said, we already

You are interpreting something which can be random data.

> if (e.version == 0)
>   crc_offset = 0x72;
> 
> So here we're reading the 'version' field before we validate the data,
> because we need to check the version to know where the CRC is.

Argh.  More crap ...

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Wolfgang Denk]

Dear Scott Wood,

In message <500096e0.9010...@freescale.com> you wrote:
>
> If not, and Wolfgang still refuses to accept this, what about checking
> the old location on a CRC fail, and if the old CRC passes, don't
> automatically use it but print a message telling the user that they
> probably need to run the migration command?

Yes, that appears to be a good idea.


Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Scott Wood]

On 07/13/2012 05:46 PM, Timur Tabi wrote:
> Scott Wood wrote:
>> But you continue to generate v1 EEPROMs.  If we get the people who
>> define the format to accept v2, then we can generate v2 after the fix is
>> applied, and the (very small) risk of a real CRC failure combined with a
>> spurious CRC success in the old location would only apply on EEPROMs
>> which haven't been saved since the update.
> 
> Again, I'm confused.  Why would we bump the version to v2?  What is
> different in V2 compared to V1?

I'm pretty sure I've explained it adequately a couple times over.

Nothing is different in the spec between v1 and v2 except the version
number.  However, if you see v2 you can assume it didn't come from an
implementation with this bug.

> It's highly unlikely that there will ever be a V2.  The only reason we
> went from V0 to V1 is to allow for more than 8 MAC addresses.  Now the
> entire EEPROM is filled with MAC addresses, and so we've reached the hard
> limit of 31.  We would need to switch to a new EEPROM device in order to
> handle more, and none of the other information in the EEPROM is used by
> U-Boot.

I wasn't suggesting that v2 be used to expand the number of addresses.

-Scott

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Timur Tabi]

Scott Wood wrote:
> But you continue to generate v1 EEPROMs.  If we get the people who
> define the format to accept v2, then we can generate v2 after the fix is
> applied, and the (very small) risk of a real CRC failure combined with a
> spurious CRC success in the old location would only apply on EEPROMs
> which haven't been saved since the update.

Again, I'm confused.  Why would we bump the version to v2?  What is
different in V2 compared to V1?

It's highly unlikely that there will ever be a V2.  The only reason we
went from V0 to V1 is to allow for more than 8 MAC addresses.  Now the
entire EEPROM is filled with MAC addresses, and so we've reached the hard
limit of 31.  We would need to switch to a new EEPROM device in order to
handle more, and none of the other information in the EEPROM is used by
U-Boot.

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Scott Wood]

On 07/13/2012 05:22 PM, Timur Tabi wrote:
> Scott Wood wrote:
> 
>> I know the spec wouldn't change, except the version number.  But as I
>> said above, there would be no known v2 implementations with the bug.
>> You would only check the bad CRC location if you see v1 data, because
>> there are known buggy v1 implementations.
> 
> I already have that:
> 
>   if ((e.version == NXID_VERSION) && (crc != be32_to_cpup(crcp))) {
> 
> NXID_VERSION is equal to 1, so we only do the check for the old CRC if we
> have a v1 EEPROM.

But you continue to generate v1 EEPROMs.  If we get the people who
define the format to accept v2, then we can generate v2 after the fix is
applied, and the (very small) risk of a real CRC failure combined with a
spurious CRC success in the old location would only apply on EEPROMs
which haven't been saved since the update.

-Scott

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[U-Boot] [PATCH 1/2] spi: microblaze: Adds driver for Xilinx SPI controller

[Stephan Linz]

This is an improved version of the driver patch original
submitted by Graeme Smecher 

The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
  use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
  use the new register struct instead
- move default SPI controller configuration from
  spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP

Come from:
http://patchwork.ozlabs.org/patch/71797/

Applied with:
git apply -v --whitespace=fix --reject \
U-Boot-Adds-driver-for-Xilinx-xps_spi-SPI-controller.patch

Fix manual:
drivers/spi/Makefile

Signed-off-by: Stephan Linz 
---
 drivers/spi/Makefile |1 +
 drivers/spi/xilinx_spi.c |  210 ++
 drivers/spi/xilinx_spi.h |  135 +
 3 files changed, 346 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/xilinx_spi.c
 create mode 100644 drivers/spi/xilinx_spi.h

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c967d87..3ae38e5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
 COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
+COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
new file mode 100644
index 000..4d83bd3
--- /dev/null
+++ b/drivers/spi/xilinx_spi.c
@@ -0,0 +1,210 @@
+/*
+ * Xilinx SPI driver
+ *
+ * supports 8 bit SPI transfers only, with or w/o FIFO
+ *
+ * based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2010 Thomas Chou 
+ * Copyright (c) 2010 Graeme Smecher 
+ * Copyright (c) 2012 Stephan Linz 
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:[0]/ip_documentation/xps_spi.pdf
+ * [0]/ip_documentation/axi_spi_ds742.pdf
+ */
+#include 
+#include 
+#include 
+#include 
+
+#include "xilinx_spi.h"
+
+#ifndef CONFIG_SYS_XILINX_SPI_LIST
+#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
+#endif
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#endif
+
+#define XILSPI_SPICR_DFLT_ON   (SPICR_MANUAL_SS | \
+SPICR_MASTER_MODE | \
+SPICR_SPE)
+
+#define XILSPI_SPICR_DFLT_OFF  (SPICR_MASTER_INHIBIT | \
+SPICR_MANUAL_SS)
+
+#define XILSPI_MAX_XFER_BITS   8
+
+static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
+
+__attribute__((weak))
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+   return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
+}
+
+__attribute__((weak))
+void spi_cs_activate(struct spi_slave *slave)
+{
+   struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+   writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
+}
+
+__attribute__((weak))
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+   struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+   writel(SPISSR_OFF, &xilspi->regs->spissr);
+}
+
+void spi_init(void)
+{
+   /* do nothing */
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+   /* xilinx spi core does not support programmable speed */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+   struct xilinx_spi_slave *xilspi;
+   struct xilinx_spi_reg *regs;
+
+   if (!spi_cs_is_valid(bus, cs)) {
+   printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
+   __func__, bus, cs);
+   return NULL;
+   }
+
+   xilspi = malloc(sizeof(*xilspi));
+   if (!xilspi) {
+   printf("XILSPI error: %s: malloc of SPI structure failed\n",
+   __func__);
+   return NULL;
+   }
+   xilspi->slave.bus = bus;
+   xilspi->slave.cs = cs;
+   xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
+   xilspi->freq = max_hz;
+   xilspi->mode = mode;
+   debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
+   bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
+
+   return &xilspi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+   struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+   free(xilspi);
+}
+
+int spi_claim_bus(struct spi_slave *slav

[U-Boot] [PATCH 2/2] microblaze: Wire up SPI driver

[Stephan Linz]

Depending on XILINX_SPI_FLASH_BASEADDR enable SPI flash
and environment in SPI flash.

Expected values from xparameters.h are:
- XILINX_SPI_FLASH_BASEADDR
- XILINX_SPI_FLASH_MAX_FREQ
- XILINX_SPI_FLASH_CS

Signed-off-by: Stephan Linz 
---
 include/configs/microblaze-generic.h |   55 --
 1 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index 56dcc02..87e7951 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -36,14 +36,22 @@
 #define CONFIG_OF_EMBED1
 #define CONFIG_DEFAULT_DEVICE_TREE microblaze
 
-/* linear flash memory */
+/* linear and spi flash memory */
 #ifdef XILINX_FLASH_START
 #defineFLASH
+#undef SPIFLASH
 #undef RAMENV  /* hold environment in flash */
 #else
+#ifdef XILINX_SPI_FLASH_BASEADDR
 #undef FLASH
+#defineSPIFLASH
+#undef RAMENV  /* hold environment in flash */
+#else
+#undef FLASH
+#undef SPIFLASH
 #defineRAMENV  /* hold environment in RAM */
 #endif
+#endif
 
 /* uart */
 #ifdef XILINX_UARTLITE_BASEADDR
@@ -218,20 +226,51 @@
 #  define CONFIG_ENV_SIZE  0x1000
 #  define CONFIG_ENV_ADDR  (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
 
-# else /* !RAMENV */
+# else /* FLASH && !RAMENV */
 #  define CONFIG_ENV_IS_IN_FLASH   1
 /* 128K(one sector) for env */
 #  define CONFIG_ENV_SECT_SIZE 0x2
 #  define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
 #  define CONFIG_ENV_SIZE  0x2
-# endif /* !RAMBOOT */
+# endif /* FLASH && !RAMBOOT */
 #else /* !FLASH */
+
+#ifdef SPIFLASH
+# define CONFIG_SYS_NO_FLASH   1
+# define CONFIG_SYS_SPI_BASE   XILINX_SPI_FLASH_BASEADDR
+# define CONFIG_XILINX_SPI 1
+# define CONFIG_SPI1
+# define CONFIG_SPI_FLASH  1
+# define CONFIG_SPI_FLASH_STMICRO  1
+# define CONFIG_SF_DEFAULT_MODESPI_MODE_3
+# define CONFIG_SF_DEFAULT_SPEED   XILINX_SPI_FLASH_MAX_FREQ
+# define CONFIG_SF_DEFAULT_CS  XILINX_SPI_FLASH_CS
+
+# ifdefRAMENV
+#  define CONFIG_ENV_IS_NOWHERE1
+#  define CONFIG_ENV_SIZE  0x1000
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+# else /* SPIFLASH && !RAMENV */
+#  define CONFIG_ENV_IS_IN_SPI_FLASH   1
+#  define CONFIG_ENV_SPI_MODE  SPI_MODE_3
+#  define CONFIG_ENV_SPI_MAX_HZCONFIG_SF_DEFAULT_SPEED
+#  define CONFIG_ENV_SPI_CSCONFIG_SF_DEFAULT_CS
+/* 128K(two sectors) for env */
+#  define CONFIG_ENV_SECT_SIZE 0x1
+#  define CONFIG_ENV_SIZE  (2 * CONFIG_ENV_SECT_SIZE)
+/* Warning: adjust the offset in respect of other flash content and size */
+#  define CONFIG_ENV_OFFSET(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
+# endif /* SPIFLASH && !RAMBOOT */
+#else /* !SPIFLASH */
+
 /* ENV in RAM */
 # define CONFIG_SYS_NO_FLASH   1
 # define CONFIG_ENV_IS_NOWHERE 1
 # define CONFIG_ENV_SIZE   0x1000
 # define CONFIG_ENV_ADDR   (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+#endif /* !SPIFLASH */
 #endif /* !FLASH */
 
 /* system ace */
@@ -306,6 +345,15 @@
 #  define CONFIG_CMD_SAVEENV
 #  define CONFIG_CMD_SAVES
 # endif
+
+#else
+#if defined(SPIFLASH)
+# define CONFIG_CMD_SF
+
+# if !defined(RAMENV)
+#  define CONFIG_CMD_SAVEENV
+#  define CONFIG_CMD_SAVES
+# endif
 #else
 # undef CONFIG_CMD_IMLS
 # undef CONFIG_CMD_FLASH
@@ -313,6 +361,7 @@
 # undef CONFIG_CMD_UBI
 # undef CONFIG_CMD_UBIFS
 #endif
+#endif
 
 #if defined(CONFIG_CMD_JFFS2)
 # define CONFIG_MTD_PARTITIONS
-- 
1.7.0.4

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Timur Tabi]

Scott Wood wrote:

> I know the spec wouldn't change, except the version number.  But as I
> said above, there would be no known v2 implementations with the bug.
> You would only check the bad CRC location if you see v1 data, because
> there are known buggy v1 implementations.

I already have that:

if ((e.version == NXID_VERSION) && (crc != be32_to_cpup(crcp))) {

NXID_VERSION is equal to 1, so we only do the check for the old CRC if we
have a v1 EEPROM.

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Scott Wood]

On 07/13/2012 04:53 PM, Timur Tabi wrote:
> Scott Wood wrote:
> 
>> Timur, I know you said you don't control the format, but could you ask
>> for a version number bump so that going forward there's a way to
>> unambiguously mark the contents as "good" (the spec wouldn't change, but
>> there would be no known implementations of v2 with this bug)?
> 
> I'm not sure what you mean.  The specification for v1 has always said that
> the CRC is at address 0xFC.  I just wrote the code wrong.  I was always
> under the impression that I was writing the CRC at 0xFC, until York
> pointed that out to me last year.  As far as the specification is
> concerned, nothing has changed.

I know the spec wouldn't change, except the version number.  But as I
said above, there would be no known v2 implementations with the bug.
You would only check the bad CRC location if you see v1 data, because
there are known buggy v1 implementations.

>> If not, and Wolfgang still refuses to accept this, what about checking
>> the old location on a CRC fail, and if the old CRC passes, don't
>> automatically use it but print a message telling the user that they
>> probably need to run the migration command?
> 
> I honestly don't see what's wrong with checking the CRC in the old
> location, and using it if it's valid.

Neither do I; I was just suggesting a compromise should Wolfgang
maintain his opposition.

-Scott

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[U-Boot] Please pull u-boot-mmc.git

[Andy Fleming]

  Merge branch 'master' of git://git.denx.de/u-boot-i2c (2012-07-12 08:17:29 
+0200)

are available in the git repository at:

  git://www.denx.de/git/u-boot-mmc.git master

Eric Nelson (1):
  i.MX: fsl_esdhc: allow use with cache enabled.

Jaehoon Chung (1):
  mmc: remove the hard setting for tran_speed

Jerry Huang (2):
  SD/MMC: check the card status during erase operation
  FSL/eSDHC: enable the clock to detect the SD card

Łukasz Majewski (1):
  mmc:fix Call mmc_init() when executing mmc_get_dev()

 drivers/mmc/fsl_esdhc.c |   20 +++-
 drivers/mmc/mmc.c   |   23 ---
 2 files changed, 35 insertions(+), 8 deletions(-)

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Timur Tabi]

Scott Wood wrote:

> Timur, I know you said you don't control the format, but could you ask
> for a version number bump so that going forward there's a way to
> unambiguously mark the contents as "good" (the spec wouldn't change, but
> there would be no known implementations of v2 with this bug)?

I'm not sure what you mean.  The specification for v1 has always said that
the CRC is at address 0xFC.  I just wrote the code wrong.  I was always
under the impression that I was writing the CRC at 0xFC, until York
pointed that out to me last year.  As far as the specification is
concerned, nothing has changed.

> If not, and Wolfgang still refuses to accept this, what about checking
> the old location on a CRC fail, and if the old CRC passes, don't
> automatically use it but print a message telling the user that they
> probably need to run the migration command?

I honestly don't see what's wrong with checking the CRC in the old
location, and using it if it's valid.  Like I said, we already
automagically update EEPROMs from version 0 to version 1.  The existing
code already checks a version number to determine where the CRC is:

/*
 * If we've read an NXID v0 EEPROM, then we need to set the CRC offset
 * to where it is in v0.
 */
if (e.version == 0)
crc_offset = 0x72;

So here we're reading the 'version' field before we validate the data,
because we need to check the version to know where the CRC is.

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Scott Wood]

On 07/13/2012 04:25 PM, Wolfgang Denk wrote:
> Dear Tabi Timur-B04825,
> 
> In message <50001038.50...@freescale.com> you wrote:
>>>
>> York is mistaken.  The CRC was always at location 0xFC, but for some 
>> reason, when I wrote the code, I put it at 0xCC.  Now I'm fixing it, and 
>> providing some backwards compatibility to avoid causing problems for 
>> people who upgrade U-Boot on existing boards.  I don't see how this is 
>> controversial in any way.
> 
> In case you have an EEPROM with correct layout (CRC at 0xFC) but
> incorrect CRC, you will access random data and interpret this as CRC.
> This is provoking undefined behaviour.
> 
> Yes, it is inlikely that you happen to find a matching CRC in such a
> case, but it is possible.
> 
> Undefined behaviour is something you must avoid.

Is it any more likely that this will happen, than that you'll see
arbitrary data accidentally match a magic number that identifies a data
format?

> If you want, then rather provide an update tool that theuser can use
> (manually!) to update, but this should be done once, and with explicit
> confirmation from the user, never automagically.

In the real world, this will result in more problems than Timur's
approach (even if the "problems" are just increased support burden from
users asking why ethernet isn't working any more).  The odds of a user
screwing up (or simply not being aware that this update of U-Boot
requires special migration steps) is much more than one in four billion.
 Perhaps this could be limited to boards that are known to have had the
bug in the past?

Timur, I know you said you don't control the format, but could you ask
for a version number bump so that going forward there's a way to
unambiguously mark the contents as "good" (the spec wouldn't change, but
there would be no known implementations of v2 with this bug)?

If not, and Wolfgang still refuses to accept this, what about checking
the old location on a CRC fail, and if the old CRC passes, don't
automatically use it but print a message telling the user that they
probably need to run the migration command?

-Scott

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Timur Tabi]

Wolfgang Denk wrote:
> Well, if it's really so unimportant and used in only a small number
> of boards, then just omit this broken code that provokes the
> undefined behaviour.

As I said before, we need to support situations where people upgrade their
U-Boot.  When the EEPROM is read, the CRC is checked in both locations.
If it's valid in either, then we assume the data is valid and continue.

When the user wants to write back the EEPROM (via the "mac save" command),
the CRC is written only at the proper location (0xFC).  This "fixes" the
EEPROM, and the code will never read the CRC from the wrong location (0xCC).

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Wolfgang Denk]

Dear Timur Tabi,

In message <50009349.9000...@freescale.com> you wrote:
> 
> > In case you have an EEPROM with correct layout (CRC at 0xFC) but
> > incorrect CRC, you will access random data and interpret this as CRC.
> > This is provoking undefined behaviour.
> 
> True, but it doesn't matter.  The EEPROM is not that important, and the
> odds of screwing this up is one in four billion.
> 
> > If you want, then rather provide an update tool that theuser can use
> > (manually!) to update, but this should be done once, and with explicit
> > confirmation from the user, never automagically.
> 
> Considering how unimportant the EEPROM really is, I don't see the point in
> making it so complicated.  We already automagically upgrade the board from
> NXID v0 to NXID v1.  Now we automagically fix boards that have the CRC in
> the wrong place.
> 
> Anyway, I don't see why it's so controversial.  This code is only used on
> a small number of Freescale reference boards.

Well, if it's really so unimportant and used in only a small number
of boards, then just omit this broken code that provokes the
undefined behaviour.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
The main thing is the play itself. I swear that greed for  money  has
nothing  to  do with it, although heaven knows I am sorely in need of
money.   - Feodor Dostoyevsky
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Re: [U-Boot] [PATCH 1/2 v2] SDHC/MMC: fix the wrong infomation after change SD card

[Andy Fleming]

On Wed, Jul 11, 2012 at 4:29 AM, Huang Changming-R66093
 wrote:
> Hi, Andy,
> There is not any feedback for very long time,
> Could it be applied to the u-boot?


I'm afraid I have to reject this patch. We need to find a better
solution to the two problems:

1) We want to change cards and still have mmc commands work
2) We don't want eMMC devices to be slowed down by constantly
re-initializing their cards.

Normally, I would err on the side of #1, but there's a simple
workaround. If you replace the card, execute "mmc rescan", and the
card will be reinitialized. Please let me know if that workaround
doesn't work. I hope, in the future, we'll have some code which makes
both possible, by being able to detect that a card has been changed,
but for now I think the current system is reasonably satisfactory to
both cases #1 and #2.

Andy
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Timur Tabi]

Wolfgang Denk wrote:

> In case you have an EEPROM with correct layout (CRC at 0xFC) but
> incorrect CRC, you will access random data and interpret this as CRC.
> This is provoking undefined behaviour.

True, but it doesn't matter.  The EEPROM is not that important, and the
odds of screwing this up is one in four billion.

> If you want, then rather provide an update tool that theuser can use
> (manually!) to update, but this should be done once, and with explicit
> confirmation from the user, never automagically.

Considering how unimportant the EEPROM really is, I don't see the point in
making it so complicated.  We already automagically upgrade the board from
NXID v0 to NXID v1.  Now we automagically fix boards that have the CRC in
the wrong place.

Anyway, I don't see why it's so controversial.  This code is only used on
a small number of Freescale reference boards.

-- 
Timur Tabi
Linux kernel developer at Freescale

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Re: [U-Boot] Doubt on uboot code

[Wolfgang Denk]

Dear VISWANADHULA BALAJI,

In message  
you wrote:
>
>  I have the U-boot source code of SAMSUNG EXYNOS SMDKV310 board. When i

Where did you get this code from?

>"bl1.bin responsibility is to load the second stage bootloader from
> the sd card to SD RAM".*I have the doubt in the bl1.bin file *how the above
> mentioned transforming  is done from the following device copy function.
> 
>#define SDMMC_ReadBlocks_eMMC_ByCPU(uNumOfBlks, uDstAddr) \
> (((void(*)(u32, u32*))(*((u32
> *)EXT_eMMC43_BL2_ByCPU_ADDRESS)))(uNumOfBlks, uDstAddr))

None of this is in mainline U-Boot.  We cannot help you with that.
Please contact the technical support of wherever you got the code
from.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Remember that Beethoven wrote his first symphony in C ...
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Re: [U-Boot] [PATCH v2 4/7] dfu: MMC specific routines for DFU operation

[Andy Fleming]

>> > Generally it is in my opinion a good way to go.
>> >
>> > However, why we aren't first writing sanity checks for passed arguments?
>>
>> Simply because I didn't want to ask you to do a lot more unrelated work
>>
>> :)  If you want to split and check the mmc (and fatwrite) argueuments
>>
>> and then make the DFU series depend on that, by all means please do so!
>
> Would be cool indeed.
>
>> > We are adding one more level of abstraction, but don't think of the main
>> > problem (checking values of passed arguments)?
>> >
>> > Anyway we shall wait for Marek's opinion.
>>
>> Yes, a good idea as well.
>
> My opinion is that if you'll do the sanity checks, that'd be good. We're right
> before .07 release anyway, so the patches will hit the next merge window. Are
> you up for doing a lot of unrelated work to make this proper?


I agree with the general sense that adding sanity checking would be
good. Just because I was too lazy to add them, doesn't mean I was
right. ;)

Andy
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Wolfgang Denk]

Dear Tabi Timur-B04825,

In message <5000106b.5090...@freescale.com> you wrote:
>
> > It will work by chance, accessing random data.  This is crap.
> 
> It is not crap, and it will not work by chance.  It is not accessing 
> random data, it is accessing the CRC in the old location, just like the 
> current code does today.

If you have the CRC at 0xFC, and the CRC is incorrect, then it _will_
access random data, and result inundefined behaviour. Yes, this _is_ a
crappy design.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
"There are three principal ways to lose money: wine, women,  and  en-
gineers.  While  the first two are more pleasant, the third is by far
the more certain."  -- Baron Rothschild, ca. 1800
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Wolfgang Denk]

Dear Tabi Timur-B04825,

In message <50001038.50...@freescale.com> you wrote:
> >
> York is mistaken.  The CRC was always at location 0xFC, but for some 
> reason, when I wrote the code, I put it at 0xCC.  Now I'm fixing it, and 
> providing some backwards compatibility to avoid causing problems for 
> people who upgrade U-Boot on existing boards.  I don't see how this is 
> controversial in any way.

In case you have an EEPROM with correct layout (CRC at 0xFC) but
incorrect CRC, you will access random data and interpret this as CRC.
This is provoking undefined behaviour.

Yes, it is inlikely that you happen to find a matching CRC in such a
case, but it is possible.

Undefined behaviour is something you must avoid.


If you want, then rather provide an update tool that theuser can use
(manually!) to update, but this should be done once, and with explicit
confirmation from the user, never automagically.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[York Sun]

On Fri, 2012-07-13 at 05:12 -0700, Tabi Timur-B04825 wrote:
> sun york-R58495 wrote:
> 
> > I agree it was a broken design. Now we are using all available space
> > and put CRC to the very end. It is not perfect but should work.
> 
> *sigh*
> 
> The design was never broken, the code was just wrong.  The CRC has always 
> supposed to have been at the end.
> 
Sorry, I meant the design was broken when I implemented it. I didn't put
the CRC to a fixed location.

York



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[U-Boot] [PATCH] part_mac: dcache: allocate cacheline-aligned buffers

[Benoît Thébaudeau]

This patch forces the correct alignment for DMA operations of buffers used by
part_mac.c.

Signed-off-by: Benoît Thébaudeau 
Cc: Wolfgang Denk 
---
 {u-boot.orig => u-boot}/disk/part_mac.c |   68 +++
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git u-boot.orig/disk/part_mac.c u-boot/disk/part_mac.c
index c1afc8c..cb443ac 100644
--- u-boot.orig/disk/part_mac.c
+++ u-boot/disk/part_mac.c
@@ -60,23 +60,23 @@ static int part_mac_read_pdb (block_dev_desc_t *dev_desc, 
int part, mac_partitio
  */
 int test_part_mac (block_dev_desc_t *dev_desc)
 {
-   mac_driver_desc_t   ddesc;
-   mac_partition_t mpart;
+   ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
+   ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ulong i, n;
 
-   if (part_mac_read_ddb (dev_desc, &ddesc)) {
+   if (part_mac_read_ddb (dev_desc, ddesc)) {
/* error reading Driver Desriptor Block, or no valid Signature 
*/
return (-1);
}
 
n = 1;  /* assuming at least one partition */
for (i=1; i<=n; ++i) {
-   if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)&mpart) 
!= 1) ||
-   (mpart.signature != MAC_PARTITION_MAGIC) ) {
+   if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)mpart) 
!= 1) ||
+   (mpart->signature != MAC_PARTITION_MAGIC) ) {
return (-1);
}
/* update partition count */
-   n = mpart.map_count;
+   n = mpart->map_count;
}
return (0);
 }
@@ -85,20 +85,20 @@ int test_part_mac (block_dev_desc_t *dev_desc)
 void print_part_mac (block_dev_desc_t *dev_desc)
 {
ulong i, n;
-   mac_driver_desc_t   ddesc;
-   mac_partition_t mpart;
+   ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
+   ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ldiv_t mb, gb;
 
-   if (part_mac_read_ddb (dev_desc, &ddesc)) {
+   if (part_mac_read_ddb (dev_desc, ddesc)) {
/* error reading Driver Desriptor Block, or no valid Signature 
*/
return;
}
 
-   n  = ddesc.blk_count;
+   n  = ddesc->blk_count;
 
-   mb = ldiv(n, ((1024 * 1024) / ddesc.blk_size)); /* MB */
+   mb = ldiv(n, ((1024 * 1024) / ddesc->blk_size)); /* MB */
/* round to 1 digit */
-   mb.rem *= 10 * ddesc.blk_size;
+   mb.rem *= 10 * ddesc->blk_size;
mb.rem += 512 * 1024;
mb.rem /= 1024 * 1024;
 
@@ -112,10 +112,10 @@ void print_part_mac (block_dev_desc_t *dev_desc)
"DeviceType=0x%x, DeviceId=0x%x\n\n"
"   #: type name"
"   length   base   (size)\n",
-   ddesc.blk_size,
-   ddesc.blk_count,
+   ddesc->blk_size,
+   ddesc->blk_count,
mb.quot, mb.rem, gb.quot, gb.rem,
-   ddesc.dev_type, ddesc.dev_id
+   ddesc->dev_type, ddesc->dev_id
);
 
n = 1;  /* assuming at least one partition */
@@ -124,25 +124,25 @@ void print_part_mac (block_dev_desc_t *dev_desc)
char c;
 
printf ("%4ld: ", i);
-   if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)&mpart) 
!= 1) {
+   if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)mpart) 
!= 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
dev_desc->dev, i);
return;
}
 
-   if (mpart.signature != MAC_PARTITION_MAGIC) {
+   if (mpart->signature != MAC_PARTITION_MAGIC) {
printf ("** Bad Signature on %d:%ld - "
"expected 0x%04x, got 0x%04x\n",
-   dev_desc->dev, i, MAC_PARTITION_MAGIC, 
mpart.signature);
+   dev_desc->dev, i, MAC_PARTITION_MAGIC, 
mpart->signature);
return;
}
 
/* update partition count */
-   n = mpart.map_count;
+   n = mpart->map_count;
 
c  = 'k';
-   bytes  = mpart.block_count;
-   bytes /= (1024 / ddesc.blk_size);  /* kB; assumes blk_size == 
512 */
+   bytes  = mpart->block_count;
+   bytes /= (1024 / ddesc->blk_size);  /* kB; assumes blk_size == 
512 */
if (bytes >= 1024) {
bytes >>= 10;
c = 'M';
@@ -153,10 +153,10 @@ void print_part_mac (block_dev_desc_t *dev_desc)
}
 
printf ("%20.32s %-18.32s %10u @ %-10u (%3ld%c)\n",
-   mpart.type,
-   mpart.name,
-   mpart.block_count,
-   mpart.star

[U-Boot] [PATCH u-boot-arm/next 2/2] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Javier Martinez Canillas]

This patch adds SPL support for IGEP-based boards.

Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.

Signed-off-by: Javier Martinez Canillas 
---
 board/isee/igep0020/config.mk  |   33 
 board/isee/igep0020/igep0020.c |   34 -
 board/isee/igep0030/config.mk  |   33 
 board/isee/igep0030/igep0030.c |   34 -
 include/configs/igep00x0.h |   65 
 5 files changed, 131 insertions(+), 68 deletions(-)
 delete mode 100644 board/isee/igep0020/config.mk
 delete mode 100644 board/isee/igep0030/config.mk

diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
deleted file mode 100644
index 7964621..000
--- a/board/isee/igep0020/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, 
-#
-# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000' (bank0)
-# A000/ (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 971e31b..40436d6 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -58,6 +58,38 @@ int board_init(void)
return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+   u32 *mr)
+{
+   *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+   *mcfg = MICRON_V_MCFG_165(512 << 20);
+   *ctrla = MICRON_V_ACTIMA_165;
+   *ctrlb = MICRON_V_ACTIMB_165;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+#else
+   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_165;
+   *ctrlb = NUMONYX_V_ACTIMB_165;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+#endif
+}
+#endif
+
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
@@ -91,7 +123,7 @@ static void setup_net_chip(void)
 }
 #endif
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
omap_mmc_init(0, 0, 0);
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
deleted file mode 100644
index 059a878..000
--- a/board/isee/igep0030/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, 
-#
-# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000' (bank0)
-# A000/ (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 653c1b5..41a7548 100644
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep

[U-Boot] [PATCH u-boot-arm/next 1/2] OMAP3: igep00x0: Add config option to choose flash storage memory

[Javier Martinez Canillas]

IGEP-based boards can have two different flash memories, a OneNAND or a
NAND device. Add a configuration option for to choose which memory to use.

Signed-off-by: Javier Martinez Canillas 
---
 board/isee/igep0020/igep0020.h |4 
 board/isee/igep0030/igep0030.h |4 
 boards.cfg |6 --
 include/configs/igep00x0.h |   19 +++
 4 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
index 3d6e15f..3335ecc 100644
--- a/board/isee/igep0020/igep0020.h
+++ b/board/isee/igep0020/igep0020.h
@@ -26,7 +26,11 @@
 const omap3_sysinfo sysinfo = {
DDR_STACKED,
"IGEP v2 board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
"ONENAND",
+#else
+   "NAND",
+#endif
 };
 
 static void setup_net_chip(void);
diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h
index b7ce5aa..a93339d 100644
--- a/board/isee/igep0030/igep0030.h
+++ b/board/isee/igep0030/igep0030.h
@@ -26,7 +26,11 @@
 const omap3_sysinfo sysinfo = {
DDR_STACKED,
"OMAP3 IGEP module",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
"ONENAND",
+#else
+   "NAND",
+#endif
 };
 
 /*
diff --git a/boards.cfg b/boards.cfg
index 9efdc6d..7463896 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -224,8 +224,10 @@ cm_t35   arm armv7   
cm_t35  -
 omap3_overo  arm armv7   overo   - 
 omap3
 omap3_pandoraarm armv7   pandora - 
 omap3
 dig297   arm armv7   dig297  
comelitomap3
-igep0020 arm armv7   igep0020isee  
 omap3  igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020
-igep0030 arm armv7   igep0030isee  
 omap3  igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030
+igep0020 arm armv7   igep0020isee  
 omap3  igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
+igep0020_nandarm armv7   igep0020isee  
 omap3  igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
+igep0030 arm armv7   igep0030isee  
 omap3  igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
+igep0030_nandarm armv7   igep0030isee  
 omap3  igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
 am3517_evm   arm armv7   am3517evm   
logicpdomap3
 mt_ventoux   arm armv7   mt_ventoux  
teejet omap3
 omap3_zoom1  arm armv7   zoom1   
logicpdomap3
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index a0a23a7..d8e87c3 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -105,7 +105,12 @@
 #define CONFIG_CMD_FAT /* FAT support  */
 #define CONFIG_CMD_I2C /* I2C serial bus support   */
 #define CONFIG_CMD_MMC /* MMC support  */
+#ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_CMD_ONENAND /* ONENAND support  */
+#endif
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_CMD_NAND
+#endif
 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
@@ -244,6 +249,7 @@
  * FLASH and environment organization
  */
 
+#ifdef CONFIG_BOOT_ONENAND
 #define PISMO1_ONEN_SIZE   GPMC_SIZE_128M /* Configure the PISMO */
 
 #define CONFIG_SYS_ONENAND_BASEONENAND_MAP
@@ -253,6 +259,19 @@
 #define CONFIG_ENV_IS_IN_ONENAND   1
 #define CONFIG_ENV_SIZE(512 << 10) /* Total Size 
Environment */
 #define CONFIG_ENV_ADDRONENAND_ENV_OFFSET
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+#define PISMO1_NAND_SIZE   GPMC_SIZE_128M /* Configure the PISMO */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_BASE   NAND_BASE
+#define GPMC_NAND_ECC_LP_x16_LAYOUT1
+#define CONFIG_ENV_OFFSET  0x26 /* environment starts here */
+#define CONFIG_ENV_IS_IN_NAND  1
+#define CONFIG_ENV_SIZE(512 << 10) /* Total Size 
Environment */
+#define CONFIG_ENV_ADDRNAND_ENV_OFFSET
+#define CONFIG_SYS_MAX_NAND_DEVICE  1
+#endif
 
 /*
  * Size of malloc() pool
-- 
1.7.7.6

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[U-Boot] uboot for zyxel nsa320

[kqt4at5v]

I have a new Zyxel NSA320. It is unmodified. At the uboot prompt I 
printenv and save all environment variables. Next I pulled code from 
https://github.com/psch2/uboot-nsa320, compiled and used kwboot to load 
new uboot. No problems so far. Now if I reload all environment variables I 
saved and boot the kernel loads but does not execute. Any ideas?


NSA320> boot

NAND read: device 0 offset 0xc8, size 0xa0
10485760 bytes read: OK
## Booting kernel from Legacy Image at 0200 ...
Image Name: Linux-2.6.31.8
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 5909960 Bytes = 5.6 MiB
Load Address: 8000
Entry Point: 8000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing 
Linux... 
done, booting the kernel.



Richard

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[U-Boot] [PATCH 2/2] sf: stmicro: add support N25Q128 parts

[Stephan Linz]

Adds support for Numonyx's N25Q128 SPI flash. These devices
are used on (among others) Avnet Spartan-6 LX9 micro-evaluation
boards. Tested with "sf" commands and CONFIG_ENV_IS_IN_SPI_FLASH.

Signed-off-by: Stephan Linz 
---
 drivers/mtd/spi/stmicro.c |7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 4bee9ce..50b8aad 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -111,6 +111,13 @@ static const struct stmicro_spi_flash_params 
stmicro_spi_flash_table[] = {
.nr_sectors = 64,
.name = "M25P128",
},
+   {
+   .id = 0xba18,
+   .page_size = 256,
+   .pages_per_sector = 256,
+   .nr_sectors = 256,
+   .name = "N25Q128",
+   },
 };
 
 static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len)
-- 
1.7.0.4

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[U-Boot] [PATCH 1/2] sf: stmicro: support JEDEC standard two-byte signature

[Stephan Linz]

There are more than the M25Pxx serial flashs that can be
used with the stmicro driver, for example: the M25PXxx or
N25Qxx serie. All these chips have burned in the original
stmicro manufacture id 0x20 together with a standard
two-byte signature.

In preperation to support all these chips the stmicro driver
have to decode the full two-byte signature.

Signed-off-by: Stephan Linz 
---
 drivers/mtd/spi/stmicro.c |   24 
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index a9b33cf..4bee9ce 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -47,7 +47,7 @@
 #define CMD_M25PXX_RES 0xab/* Release from DP, and Read Signature 
*/
 
 struct stmicro_spi_flash_params {
-   u8 idcode1;
+   u16 id;
u16 page_size;
u16 pages_per_sector;
u16 nr_sectors;
@@ -56,56 +56,56 @@ struct stmicro_spi_flash_params {
 
 static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = {
{
-   .idcode1 = 0x11,
+   .id = 0x2011,
.page_size = 256,
.pages_per_sector = 128,
.nr_sectors = 4,
.name = "M25P10",
},
{
-   .idcode1 = 0x15,
+   .id = 0x2015,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 32,
.name = "M25P16",
},
{
-   .idcode1 = 0x12,
+   .id = 0x2012,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 4,
.name = "M25P20",
},
{
-   .idcode1 = 0x16,
+   .id = 0x2016,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 64,
.name = "M25P32",
},
{
-   .idcode1 = 0x13,
+   .id = 0x2013,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 8,
.name = "M25P40",
},
{
-   .idcode1 = 0x17,
+   .id = 0x2017,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 128,
.name = "M25P64",
},
{
-   .idcode1 = 0x14,
+   .id = 0x2014,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 16,
.name = "M25P80",
},
{
-   .idcode1 = 0x18,
+   .id = 0x2018,
.page_size = 256,
.pages_per_sector = 1024,
.nr_sectors = 64,
@@ -139,13 +139,13 @@ struct spi_flash *spi_flash_probe_stmicro(struct 
spi_slave *spi, u8 * idcode)
 
for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) {
params = &stmicro_spi_flash_table[i];
-   if (params->idcode1 == idcode[2]) {
+   if (params->id == ((idcode[1] << 8) | idcode[2]))
break;
-   }
}
 
if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
-   debug("SF: Unsupported STMicro ID %02x\n", idcode[1]);
+   debug("SF: Unsupported STMicro ID %02x%02x\n",
+   idcode[1], idcode[2]);
return NULL;
}
 
-- 
1.7.0.4

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[U-Boot] __led_set usage is inconsistent

[Holger Freyther]

Hi,

I hope that this is not a common question. I have read doc/README.LED,
compiled in the GPIO LED driver, provided my GPIO number, enabled the
LED command and then noticed that "led 0 on" didn't do what I wanted.

It appears that the semantic of "state" in __led_set(mask, state) is
used in two different ways.

1.) status_led_set is using STATUS_LED_ON|STATUS_LED_OFF for the state
parameter.
2.) cmd_led.c is using 0|1 when calling __led_set.


The confusing is in the implementation as well.
1.) drivers/misc/gpio_led.c expects it to be STATUS_LED_*
2.) board/ti/beagle/led.c wants 0|1


Which part of the code is right? Will a patch to use an enum for the
state be appreciated?

holger

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Re: [U-Boot] [V2 04/15] S3C64XX: add pwm for s3c64xx support

[Zhong Hongbo]

resend again, I receive Message undeliverable

On 07/14/2012 12:11 AM, Zhong Hongbo wrote:
> From: Zhong Hongbo 
> 
> Signed-off-by: Zhong Hongbo 
> ---
> Change for V2:
>   - Change the type of the return value from unsinged int
> to unsinged long for s3c64xx_get_base_nand function.
> ---
>  arch/arm/cpu/arm1176/s3c64xx/Makefile   |1 +
>  arch/arm/cpu/arm1176/s3c64xx/pwm.c  |  189 
> +++
>  arch/arm/include/asm/arch-s3c64xx/pwm.h |   70 ++
>  arch/arm/include/asm/arch-s3c64xx/s3c6400.h |   56 ++---
>  arch/arm/include/asm/arch-s3c64xx/s3c64x0.h |   59 -
>  include/configs/smdk6400.h  |3 +
>  6 files changed, 272 insertions(+), 106 deletions(-)
>  create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c
>  create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h
>  delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
> 
> diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile 
> b/arch/arm/cpu/arm1176/s3c64xx/Makefile
> index 0785b19..93f 100644
> --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
> +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
> @@ -32,6 +32,7 @@ SOBJS   = reset.o
>  
>  COBJS-$(CONFIG_S3C6400)  += cpu_init.o speed.o
>  COBJS-y  += timer.o
> +COBJS-$(CONFIG_PWM) += pwm.o
>  
>  OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
>  
> diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c 
> b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
> new file mode 100644
> index 000..d1d70ff
> --- /dev/null
> +++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
> @@ -0,0 +1,189 @@
> +/*
> + * Copyright (C) 2012
> + *
> + * Zhong Hongbo 
> + *
> + * based on arch/arm/cpu/armv7/s5p-common/sromc.c
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +int pwm_enable(int pwm_id)
> +{
> + const struct s3c_timer *pwm =
> + (struct s3c_timer *)s3c64xx_get_base_timer();
> + unsigned long tcon;
> +
> + tcon = readl(&pwm->tcon);
> + tcon |= TCON_START(pwm_id);
> +
> + writel(tcon, &pwm->tcon);
> +
> + return 0;
> +}
> +
> +void pwm_disable(int pwm_id)
> +{
> + const struct s3c_timer *pwm =
> + (struct s3c_timer *)s3c64xx_get_base_timer();
> + unsigned long tcon;
> +
> + tcon = readl(&pwm->tcon);
> + tcon &= ~TCON_START(pwm_id);
> +
> + writel(tcon, &pwm->tcon);
> +}
> +
> +static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
> +{
> + unsigned long tin_parent_rate;
> + unsigned int div;
> +
> + tin_parent_rate = get_PCLK();
> +
> + for (div = 2; div <= 16; div *= 2) {
> + if ((tin_parent_rate / (div << 16)) < freq)
> + return tin_parent_rate / div;
> + }
> +
> + return tin_parent_rate / 16;
> +}
> +
> +#define NS_IN_HZ (10UL)
> +
> +int pwm_config(int pwm_id, int duty_ns, int period_ns)
> +{
> + const struct s3c_timer *pwm =
> + (struct s3c_timer *)s3c64xx_get_base_timer();
> + unsigned int offset;
> + unsigned long tin_rate;
> + unsigned long tin_ns;
> + unsigned long period;
> + unsigned long tcon;
> + unsigned long tcnt;
> + unsigned long tcmp;
> +
> + /*
> +  * We currently avoid using 64bit arithmetic by using the
> +  * fact that anything faster than 1GHz is easily representable
> +  * by 32bits.
> +  */
> + if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
> + return -ERANGE;
> +
> + if (duty_ns > period_ns)
> + return -EINVAL;
> +
> + period = NS_IN_HZ / period_ns;
> +
> + /* Check to see if we are changing the clock rate of the PWM */
> + tin_rate = pwm_calc_tin(pwm_id, period);
> +
> + tin_ns = NS_IN_HZ / tin_rate;
> + tcnt = period_ns / tin_ns;
> +
> + /* Note, counters count down */
> + tcmp = duty_ns / tin_ns;
> + tcmp = tcnt - tcmp;
> +
> + /*
> +  * the pwm hw only checks the compare register after a decrement,
> +  * so the pin never toggles if tcmp = tcnt
> +  */
> + if (tcmp == tcnt)
> + tcmp--;
> +
> + if (tcmp 

[U-Boot] [V2 15/15] S3C6400: Remove the unused variable for S3C6400

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- None.
---
 include/configs/smdk6400.h |   15 ---
 1 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 46241e2..b8b9d1a 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -108,9 +108,6 @@
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NAND
-#if defined(CONFIG_BOOT_ONENAND)
-#define CONFIG_CMD_ONENAND
-#endif
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
@@ -266,13 +263,6 @@
 48, 49, 50, 51, 52, 53, 54, 55, \
 56, 57, 58, 59, 60, 61, 62, 63}
 
-/* None of these are currently implemented. Left from the original Samsung
- * version for reference
-#define CONFIG_BOOT_NOR
-#define CONFIG_BOOT_MOVINAND
-#define CONFIG_BOOT_ONENAND
-*/
-
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND
 #define CONFIG_SPL_NAND_SIMPLE
@@ -283,11 +273,6 @@
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
 #define CONFIG_NAND_S3C64XX
-/* Unimplemented or unsupported. See comment above.
-#define CONFIG_ONENAND
-#define CONFIG_MOVINAND
-*/
-
 /* Settings as above boot configuration */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_BOOTARGS"console=ttySAC,115200"
-- 
1.7.5.4

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[U-Boot] [V2 14/15] S3C64XX: Move s3c6400.h to cpu.h to support s3c6410 board

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- New.
---
 arch/arm/cpu/arm1176/s3c64xx/pwm.c  |2 +-
 arch/arm/cpu/arm1176/s3c64xx/reset.S|2 +-
 arch/arm/cpu/arm1176/s3c64xx/speed.c|2 +-
 arch/arm/cpu/arm1176/s3c64xx/srom.c |2 +-
 arch/arm/cpu/arm1176/s3c64xx/timer.c|2 +-
 arch/arm/include/asm/arch-s3c64xx/cpu.h |   83 ++
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |   84 ---
 board/samsung/smdk6400/lowlevel_init.S  |2 +-
 board/samsung/smdk6400/mem_init.S   |2 +-
 board/samsung/smdk6400/smdk6400.c   |2 +-
 drivers/mtd/nand/s3c64xx.c  |2 +-
 drivers/serial/s3c64xx.c|2 +-
 drivers/usb/host/s3c64xx-hcd.c  |2 +-
 13 files changed, 94 insertions(+), 95 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-s3c64xx/cpu.h
 delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c6400.h

diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c 
b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
index d1d70ff..02822fc 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/pwm.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
@@ -28,7 +28,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 int pwm_enable(int pwm_id)
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S 
b/arch/arm/cpu/arm1176/s3c64xx/reset.S
index 9e5ee84..ee96d6c 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S
@@ -21,7 +21,7 @@
  * MA 02111-1307 USA
  */
 
-#include 
+#include 
 
 .globl reset_cpu
 reset_cpu:
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c 
b/arch/arm/cpu/arm1176/s3c64xx/speed.c
index 05b44b9..5e68090 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -32,7 +32,7 @@
 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 #define APLL 0
diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c 
b/arch/arm/cpu/arm1176/s3c64xx/srom.c
index f1b2b34..92fb7af 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/srom.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c
@@ -25,7 +25,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 /*
  * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the
  * band width control and bank control registers
diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c 
b/arch/arm/cpu/arm1176/s3c64xx/timer.c
index 47d7731..eebd0c0 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -25,7 +25,7 @@
 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/arch/arm/include/asm/arch-s3c64xx/cpu.h 
b/arch/arm/include/asm/arch-s3c64xx/cpu.h
new file mode 100644
index 000..5c8dd9d
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/cpu.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2007
+ * Byungjae Lee, Samsung Erectronics, bj...@samsung.com.
+ *  - only support for S3C6400
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/
+ * NAME: s3c64XX.h
+ *
+ * Based on S3C64XX User's manual Rev 0.0
+ /
+
+#ifndef __ASM_ARCH_CPU_H__
+#define __ASM_ARCH_CPU_H__
+
+#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
+#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
+#endif
+
+#define S3C64XX_UART_CHANNELS  3
+#define S3C64XX_SPI_CHANNELS   2
+
+#include 
+
+#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
+#define ELFIN_GPIO_BASE0x7f008000
+#define ELFIN_SROM_BASE0x7000
+#define ELFIN_DMC0_BASE0x7e00
+#define ELFIN_DMC1_BASE0x7e001000
+#define ELFIN_MEM_SYS_CFG  0x7e00f120
+#define ELFIN_NAND_BASE0x7020
+#define ELFIN_VIC0_BASE_ADDR   0x7120
+#define ELFIN_VIC1_BASE_ADDR   0x7130
+#define ELFIN_WATCHDOG_BASE0x7E004000
+#define ELFIN_UART_BASE0x7F005000
+#define ELFIN_TIMER_BASE   0x7F006000
+
+#ifndef __ASSEMBLY__
+static inline unsigned int s3c64xx_get_base_uart(void)
+{
+   return ELFIN_UART_BASE;
+}
+
+static inline unsigned int s3c64xx_

[U-Boot] [V2 13/15] S3C6400: clear memory init variable

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- None.
---
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |  173 +--
 board/samsung/smdk6400/lowlevel_init.S  |   13 +--
 board/samsung/smdk6400/mem_init.S   |  114 +-
 3 files changed, 63 insertions(+), 237 deletions(-)

diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h 
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 8d12cfa..6e22cd5 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -41,189 +41,18 @@
 #include 
 
 #define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/*
- * GPIO
- */
 #define ELFIN_GPIO_BASE0x7f008000
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG  0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT  (1 << 12)
-
-/*
- * Memory controller
- */
 #define ELFIN_SROM_BASE0x7000
-
-/*
- * SDRAM Controller
- */
 #define ELFIN_DMC0_BASE0x7e00
 #define ELFIN_DMC1_BASE0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS  0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD   0x08
-#define INDEX_DMC_MEMORY_CFG   0x0C
-#define INDEX_DMC_REFRESH_PRD  0x10
-#define INDEX_DMC_CAS_LATENCY  0x14
-#define INDEX_DMC_T_DQSS   0x18
-#define INDEX_DMC_T_MRD0x1C
-#define INDEX_DMC_T_RAS0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD0x28
-#define INDEX_DMC_T_RFC0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR0x44
-#define INDEX_DMC_T_ESR0x48
-#define INDEX_DMC_MEMORY_CFG2  0x4C
-#define INDEX_DMC_CHIP_0_CFG   0x200
-#define INDEX_DMC_CHIP_1_CFG   0x204
-#define INDEX_DMC_CHIP_2_CFG   0x208
-#define INDEX_DMC_CHIP_3_CFG   0x20C
-#define INDEX_DMC_USER_STATUS  0x300
-#define INDEX_DMC_USER_CONFIG  0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0   0x0c
-#define DMC_NOP1   0x1c
-#define DMC_PA00x00/* Precharge all */
-#define DMC_PA10x10
-#define DMC_AR00x04/* Autorefresh */
-#define DMC_AR10x14
-#define DMC_SDR_MR00x080032/* MRS, CAS 3,  Burst Length 4 */
-#define DMC_SDR_MR10x180032
-#define DMC_DDR_MR00x080162
-#define DMC_DDR_MR10x180162
-#define DMC_mDDR_MR0   0x080032/* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1   0x180032
-#define DMC_mSDR_EMR0  0x0a/* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1  0x1a
-#define DMC_DDR_EMR0   0x09
-#define DMC_DDR_EMR1   0x19
-#define DMC_mDDR_EMR0  0x0a/*  DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1  0x1a
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips= 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst= 3'b010(burst 4)
- * stop_mem_clock  = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd  = 6'b00_(0 cycle for auto power-down)
- * ap_bit  = 1'b0 (bit position of auto-precharge is 10)
- * row_bits= 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- *  row bank control, bank address 0x3000_ ~ 0x37ff_
- *  CHIP_[n]_CFG=0x30F8,  30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
+#define ELFIN_MEM_SYS_CFG  0x7e00f120
 #define ELFIN_NAND_BASE0x7020
-
-/*
- * Interrupt
- */
 #define ELFIN_VIC0_BASE_ADDR   0x7120
 #define ELFIN_VIC1_BASE_ADDR   0x7130
-
-/*
- * Watchdog timer
- */
 #define ELFIN_WATCHDOG_BASE0x7E004000
-
-/*
- * UART
- */
 #define ELFIN_UART_BASE0x7F005000
-
-/*
- * PWM timer
- */
 #define ELFIN_TIMER_BASE   0x7F006000
 
-/*---
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG   0x00010012  /* burst 4, 13-bit row, 10-bit col */
-#define DMC1_MEM_CFG2  0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_~0x57ff_ (128 MiB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH   7800/* ns */
-#define DDR_tRAS   45  /* ns (min: 45ns)*/
-#define DDR_tRC68  /* ns (min: 67.5ns)*/
-#define DDR_tRCD   23  /* ns (min: 22.5ns)*/
-#define DDR_tRFC   80  /* ns (min: 80ns)*/
-#define DDR_tRP23  /* ns (min: 22.

[U-Boot] [V2 12/15] S3c64xx: clear GPIO, Interrupt, Watchdog variable.

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- None.
---
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |  260 ---
 board/samsung/smdk6400/lowlevel_init.S  |   23 ++--
 2 files changed, 11 insertions(+), 272 deletions(-)

diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h 
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index b1537c1..8d12cfa 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -47,172 +47,6 @@
  */
 #define ELFIN_GPIO_BASE0x7f008000
 
-#define GPACON_OFFSET  0x00
-#define GPADAT_OFFSET  0x04
-#define GPAPUD_OFFSET  0x08
-#define GPACONSLP_OFFSET   0x0C
-#define GPAPUDSLP_OFFSET   0x10
-#define GPBCON_OFFSET  0x20
-#define GPBDAT_OFFSET  0x24
-#define GPBPUD_OFFSET  0x28
-#define GPBCONSLP_OFFSET   0x2C
-#define GPBPUDSLP_OFFSET   0x30
-#define GPCCON_OFFSET  0x40
-#define GPCDAT_OFFSET  0x44
-#define GPCPUD_OFFSET  0x48
-#define GPCCONSLP_OFFSET   0x4C
-#define GPCPUDSLP_OFFSET   0x50
-#define GPDCON_OFFSET  0x60
-#define GPDDAT_OFFSET  0x64
-#define GPDPUD_OFFSET  0x68
-#define GPDCONSLP_OFFSET   0x6C
-#define GPDPUDSLP_OFFSET   0x70
-#define GPECON_OFFSET  0x80
-#define GPEDAT_OFFSET  0x84
-#define GPEPUD_OFFSET  0x88
-#define GPECONSLP_OFFSET   0x8C
-#define GPEPUDSLP_OFFSET   0x90
-#define GPFCON_OFFSET  0xA0
-#define GPFDAT_OFFSET  0xA4
-#define GPFPUD_OFFSET  0xA8
-#define GPFCONSLP_OFFSET   0xAC
-#define GPFPUDSLP_OFFSET   0xB0
-#define GPGCON_OFFSET  0xC0
-#define GPGDAT_OFFSET  0xC4
-#define GPGPUD_OFFSET  0xC8
-#define GPGCONSLP_OFFSET   0xCC
-#define GPGPUDSLP_OFFSET   0xD0
-#define GPHCON0_OFFSET 0xE0
-#define GPHCON1_OFFSET 0xE4
-#define GPHDAT_OFFSET  0xE8
-#define GPHPUD_OFFSET  0xEC
-#define GPHCONSLP_OFFSET   0xF0
-#define GPHPUDSLP_OFFSET   0xF4
-#define GPICON_OFFSET  0x100
-#define GPIDAT_OFFSET  0x104
-#define GPIPUD_OFFSET  0x108
-#define GPICONSLP_OFFSET   0x10C
-#define GPIPUDSLP_OFFSET   0x110
-#define GPJCON_OFFSET  0x120
-#define GPJDAT_OFFSET  0x124
-#define GPJPUD_OFFSET  0x128
-#define GPJCONSLP_OFFSET   0x12C
-#define GPJPUDSLP_OFFSET   0x130
-#define MEM0DRVCON_OFFSET  0x1D0
-#define MEM1DRVCON_OFFSET  0x1D4
-#define GPKCON0_OFFSET 0x800
-#define GPKCON1_OFFSET 0x804
-#define GPKDAT_OFFSET  0x808
-#define GPKPUD_OFFSET  0x80C
-#define GPLCON0_OFFSET 0x810
-#define GPLCON1_OFFSET 0x814
-#define GPLDAT_OFFSET  0x818
-#define GPLPUD_OFFSET  0x81C
-#define GPMCON_OFFSET  0x820
-#define GPMDAT_OFFSET  0x824
-#define GPMPUD_OFFSET  0x828
-#define GPNCON_OFFSET  0x830
-#define GPNDAT_OFFSET  0x834
-#define GPNPUD_OFFSET  0x838
-#define GPOCON_OFFSET  0x140
-#define GPODAT_OFFSET  0x144
-#define GPOPUD_OFFSET  0x148
-#define GPOCONSLP_OFFSET   0x14C
-#define GPOPUDSLP_OFFSET   0x150
-#define GPPCON_OFFSET  0x160
-#define GPPDAT_OFFSET  0x164
-#define GPPPUD_OFFSET  0x168
-#define GPPCONSLP_OFFSET   0x16C
-#define GPPPUDSLP_OFFSET   0x170
-#define GPQCON_OFFSET  0x180
-#define GPQDAT_OFFSET  0x184
-#define GPQPUD_OFFSET  0x188
-#define GPQCONSLP_OFFSET   0x18C
-#define GPQPUDSLP_OFFSET   0x190
-
-#define EINTPEND_OFFSET0x924
-
-#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP_REG  __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP_REG  __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP_REG  __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP_REG  __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP_REG  __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP_REG  __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + G

[U-Boot] [V2 11/15] S3C64XX: Switch to use read/writel to operation clock system

[Zhong Hongbo]

From: Zhong Hongbo 

Switch to use read/writel function and clear the relevant variable.

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- merge clock patch.
- Change the type of return for s3c64xx_get_base_clock function.
---
 arch/arm/cpu/arm1176/s3c64xx/reset.S|4 +-
 arch/arm/cpu/arm1176/s3c64xx/speed.c|   50 +--
 arch/arm/include/asm/arch-s3c64xx/clock.h   |  147 ++
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |  219 +--
 board/samsung/smdk6400/lowlevel_init.S  |   64 -
 drivers/usb/host/s3c64xx-hcd.c  |   30 -
 6 files changed, 243 insertions(+), 271 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h

diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S 
b/arch/arm/cpu/arm1176/s3c64xx/reset.S
index eae572e..9e5ee84 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S
@@ -26,9 +26,9 @@
 .globl reset_cpu
 reset_cpu:
ldr r1, =ELFIN_CLOCK_POWER_BASE
-   ldr r2, [r1, #SYS_ID_OFFSET]
+   ldr r2, [r1, #0x118]@ SYS_ID_OFFSET
ldr r3, =0x
and r2, r3, r2, lsr #12
-   str r2, [r1, #SW_RST_OFFSET]
+   str r2, [r1, #0x114]@ SW_RST_OFFSET
 _loop_forever:
b   _loop_forever
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c 
b/arch/arm/cpu/arm1176/s3c64xx/speed.c
index 11962ac..05b44b9 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -31,12 +31,13 @@
  */
 
 #include 
+#include 
 #include 
+#include 
 
 #define APLL 0
 #define MPLL 1
 #define EPLL 2
-
 /* - */
 /*
  * NOTE: This describes the proper use of this file.
@@ -50,17 +51,20 @@
 
 static ulong get_PLLCLK(int pllreg)
 {
+   struct s3c64xx_clock *clk =
+   (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
ulong r, m, p, s;
 
switch (pllreg) {
case APLL:
-   r = APLL_CON_REG;
+   r = readl(&clk->apll_con);
break;
case MPLL:
-   r = MPLL_CON_REG;
+   r = readl(&clk->mpll_con);
break;
case EPLL:
-   r = EPLL_CON0_REG;
+   r = readl(&clk->epll_con0);
break;
default:
hang();
@@ -76,9 +80,11 @@ static ulong get_PLLCLK(int pllreg)
 /* return ARMCORE frequency */
 ulong get_ARMCLK(void)
 {
+   struct s3c64xx_clock *clk =
+   (struct s3c64xx_clock *)s3c64xx_get_base_clock();
ulong div;
 
-   div = CLK_DIV0_REG;
+   div = readl(&clk->clk_div0);
 
return get_PLLCLK(APLL) / ((div & 0x7) + 1);
 }
@@ -92,16 +98,20 @@ ulong get_FCLK(void)
 /* return HCLK frequency */
 ulong get_HCLK(void)
 {
+   struct s3c64xx_clock *clk =
+   (struct s3c64xx_clock *)s3c64xx_get_base_clock();
ulong fclk;
+   ulong other;
 
-   uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-   uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
+   uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1;
+   uint hclk_div = ((readl(&clk->clk_div0) >> 8) & 0x1) + 1;
 
/*
 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
 */
-   if (OTHERS_REG & 0x80)
+   other = readl(&clk->others);
+   if (other & 0x80)
fclk = get_FCLK();  /* SYNC Mode*/
else
fclk = get_PLLCLK(MPLL);/* ASYNC Mode   */
@@ -112,11 +122,15 @@ ulong get_HCLK(void)
 /* return PCLK frequency */
 ulong get_PCLK(void)
 {
+   struct s3c64xx_clock *clk =
+   (struct s3c64xx_clock *)s3c64xx_get_base_clock();
ulong fclk;
-   uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-   uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
+   uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1;
+   uint pre_div = ((readl(&clk->clk_div0) >> 12) & 0xf) + 1;
+   ulong other;
 
-   if (OTHERS_REG & 0x80)
+   other = readl(&clk->others);
+   if (other & 0x80)
fclk = get_FCLK();  /* SYNC Mode*/
else
fclk = get_PLLCLK(MPLL);/* ASYNC Mode   */
@@ -132,14 +146,20 @@ ulong get_UCLK(void)
 
 int print_cpuinfo(void)
 {
-   printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 100);
+   struct s3c64xx_clock *clk =
+   (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+   ulong other;
+
+   printf("\nCPU: S3C64XX@%luMHz\n", get_ARMCLK() / 100);
printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
   get_FCLK() / 100, get_HCLK() / 100,
   get_PCLK() / 100);
 
-   if (OTHERS_REG & 0x80)
-   printf

[U-Boot] [V2 10/15] S3C64XX: Change SROM init to use read/write operation

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- Change the type of return for s3c64xx_get_base_sromc function.
---
 arch/arm/cpu/arm1176/s3c64xx/Makefile   |2 +-
 arch/arm/cpu/arm1176/s3c64xx/srom.c |   51 +++
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |   13 +++
 arch/arm/include/asm/arch-s3c64xx/sromc.h   |   49 +
 board/samsung/smdk6400/smdk6400.c   |   38 ++--
 include/configs/smdk6400.h  |1 +
 6 files changed, 134 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c
 create mode 100644 arch/arm/include/asm/arch-s3c64xx/sromc.h

diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile 
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 2f37431..28786bf 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -30,7 +30,7 @@ LIB   = $(obj)lib$(SOC).o
 
 SOBJS  = reset.o
 
-COBJS-$(CONFIG_S3C64XX)+= speed.o
+COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o
 COBJS-y+= timer.o
 COBJS-$(CONFIG_PWM) += pwm.o
 
diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c 
b/arch/arm/cpu/arm1176/s3c64xx/srom.c
new file mode 100644
index 000..f1b2b34
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012
+ * Zhong Hongbo 
+ * base on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+/*
+ * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank   - SROM
+ * srom_bw_conf  - SMC Band witdh reg configuration value
+ * srom_bc_conf  - SMC Bank Control reg configuration value
+ */
+void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+   u32 tmp;
+   struct s3c64xx_sromc *srom =
+   (struct s3c64xx_sromc *)s3c64xx_get_base_sromc();
+
+   /* Configure SMC_BW register to handle proper SROMC bank */
+   tmp = srom->bw;
+   tmp &= ~(0xF << (srom_bank * 4));
+   tmp |= srom_bw_conf;
+
+   writel(tmp, &srom->bw);
+
+   /* Configure SMC_BC register */
+   writel(srom_bc_conf, &srom->bc[srom_bank]);
+}
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h 
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index b884763..d2ee9d2 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -471,14 +471,6 @@
  */
 #define ELFIN_SROM_BASE0x7000
 
-#define SROM_BW_REG__REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG   __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG   __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG   __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG   __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG   __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG   __REG(ELFIN_SROM_BASE + 0x18)
-
 /*
  * SDRAM Controller
  */
@@ -722,6 +714,11 @@ static inline unsigned long s3c64xx_get_base_timer(void)
 {
return ELFIN_TIMER_BASE;
 }
+
+static inline unsigned long s3c64xx_get_base_sromc(void)
+{
+   return ELFIN_SROM_BASE;
+}
 #endif
 
 #endif /*__S3C6400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c64xx/sromc.h 
b/arch/arm/include/asm/arch-s3c64xx/sromc.h
new file mode 100644
index 000..fcad635
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/sromc.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo 
+ *
+ * base on arch/arm/include/asm/arch-s5pc1xx/sromc.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; i

[U-Boot] [V2 09/15] arm1176: Fixed No relocation.

[Zhong Hongbo]

From: Zhong Hongbo 

When It do not need to relocat for u-boot,
the offset(r9) of relocation should be set zero.

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- This fix is seprated from nand_spl patch.
---
 arch/arm/cpu/arm1176/start.S |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 26a3533..de2cb39 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -252,6 +252,7 @@ stack_setup:
 
adr r0, _start
cmp r0, r6
+   mov r9, #0
beq clear_bss   /* skip relocation */
mov r1, r6  /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
-- 
1.7.5.4

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[U-Boot] [V2 08/15] S3C6400: Adopt SPL framwork to support spl for nand flash

[Zhong Hongbo]

From: Zhong Hongbo 

Adopt the new SPL framework to implement the SPL booting of
the nand flash for S3C6400.

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- seprate some code.
---
 arch/arm/cpu/arm1176/start.S|   16 +---
 board/samsung/smdk6400/Makefile |   29 +-
 board/samsung/smdk6400/lowlevel_init.S  |   18 ++--
 board/samsung/smdk6400/smdk6400_nand_spl.c  |   61 ++--
 board/samsung/smdk6400/tools/mksmdk6400_image.c |  117 +++
 drivers/mtd/nand/s3c64xx.c  |4 +-
 include/configs/smdk6400.h  |   21 +++--
 7 files changed, 219 insertions(+), 47 deletions(-)
 create mode 100644 board/samsung/smdk6400/tools/mksmdk6400_image.c

diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 848144a..26a3533 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -51,7 +51,7 @@
 
 .globl _start
 _start: b  reset
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -164,7 +164,7 @@ cpu_init_crit:
 * When booting from NAND - it has definitely been a reset, so, no need
 * to flush caches and disable the MMU
 */
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
 * flush v4 I/D caches
 */
@@ -356,21 +356,14 @@ clbss_l:str   r2, [r0]/* clear 
loop...*/
cmp r0, r1
bne clbss_l
 
-#ifndef CONFIG_NAND_SPL
bl coloured_LED_init
bl red_led_on
 #endif
-#endif
 
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
-#ifdef CONFIG_NAND_SPL
-   ldr pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
@@ -383,7 +376,6 @@ _nand_boot: .word nand_boot
 
 _board_init_r_ofs:
.word board_init_r - _start
-#endif
 
 _rel_dyn_start_ofs:
.word __rel_dyn_start - _start
@@ -397,7 +389,7 @@ _mmu_table_base:
.word mmu_table
 #endif
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 /*
  * we assume that cache operation is done before. (eg. cleanup_before_linux())
  * actually, we don't need to do anything about cache if not use d-cache in
@@ -575,4 +567,4 @@ fiq:
get_bad_stack
bad_save_user_regs
bl  do_fiq
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile
index 645c8e2..f7fa667 100644
--- a/board/samsung/smdk6400/Makefile
+++ b/board/samsung/smdk6400/Makefile
@@ -28,15 +28,34 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS-y:= smdk6400.o
+endif
+
 SOBJS  := lowlevel_init.o mem_init.o
 
-SRCS:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS-y))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y += smdk6400_nand_spl.o
+endif
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+
+ALL:=   $(obj).depend $(LIB)
+
+ifdef CONFIG_SPL_BUILD
+ALL+= $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
+all:   $(ALL)
+
+$(LIB):$(OBJS)
+   $(call cmd_link_o_target, $(OBJS))
 
-$(LIB):$(obj).depend $(SOBJS) $(OBJS)
-   $(call cmd_link_o_target, $(SOBJS) $(OBJS))
+ifdef CONFIG_SPL_BUILD
+$(OBJTREE)/tools/mk$(BOARD)spl:tools/mksmdk6400_image.c
+   $(HOSTCC) tools/mksmdk6400_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+endif
 
 #
 
diff --git a/board/samsung/smdk6400/lowlevel_init.S 
b/board/samsung/smdk6400/lowlevel_init.S
index 1142be1..6cc7567 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -83,18 +83,12 @@ lowlevel_init:
str r3, [r0, #oVECTADDR]
str r3, [r1, #oVECTADDR]
 
+#ifdef CONFIG_SPL_BUILD
/* init system clock */
bl system_clock_init
 
-#ifndef CONFIG_NAND_SPL
-   /* for UART */
-   bl uart_asm_init
-#endif
-
-#ifdef CONFIG_BOOT_NAND
/* simple init for NAND */
bl nand_asm_init
-#endif
 
/* Memory subsystem address 0x7e00f120 */
ldr r0, =ELFIN_MEM_SYS_CFG
@@ -104,6 +98,12 @@ lowlevel_init:
str r1, [r0]
 
bl  mem_ctrl_asm_init
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+   /* for UART */
+   bl uart_asm_init
+#endif
 
 /* Wakeup support. Don't know if it's going to be used, untested. */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
@@ -243,7 +243,7 @@ wait_for_async:
mov pc, lr
 
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 /*
  * uart_asm_init: Initialize UART's pins
  */
@@ -

[U-Boot] [V2 07/15] S3C6400: Delete nand_spl for S3C6400

[Zhong Hongbo]

From: Zhong Hongbo 

The old spl use nand_spl directory file to support
nand flash boot. We will adopt the new SPL framework
to implement it.

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- None.
---
 board/samsung/smdk6400/config.mk   |   28 ---
 boards.cfg |4 +-
 include/configs/smdk6400.h |2 +-
 nand_spl/board/samsung/smdk6400/Makefile   |  117 
 nand_spl/board/samsung/smdk6400/config.mk  |   40 --
 nand_spl/board/samsung/smdk6400/u-boot.lds |   78 --
 6 files changed, 3 insertions(+), 266 deletions(-)
 delete mode 100644 board/samsung/smdk6400/config.mk
 delete mode 100644 nand_spl/board/samsung/smdk6400/Makefile
 delete mode 100644 nand_spl/board/samsung/smdk6400/config.mk
 delete mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds

diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk
deleted file mode 100644
index 93a1a0d..000
--- a/board/samsung/smdk6400/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, 
-# David Mueller, ELSOFT AG, 
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, 
-#
-# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-
-# On SMDK6400 we use the 64 MB SDRAM bank at
-#
-# 0x5000 to 0x5800
-#
-# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
-#
-# we load ourselves to 0x57e0 without MMU
-# with MMU, load address is changed to 0xc7e0
-#
-# download area is 0x5000c000
-
-ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT)
-else
-CONFIG_SYS_TEXT_BASE = 0
-endif
diff --git a/boards.cfg b/boards.cfg
index a6ca01f..cc18700 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -47,8 +47,8 @@ flea3arm arm1136 -
   CarMedi
 mx35pdk  arm arm1136 -   
freescale  mx35
 apollon arm arm1136 apollon
 -  omap24xx
 omap2420h4   arm arm1136 -   ti
 omap24xx
-smdk6400 arm arm1176 smdk6400
samsungs3c64xx  smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e0
-smdk6400_nousb   arm arm1176 smdk6400
samsungs3c64xx  smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e0
+smdk6400 arm arm1176 smdk6400
samsungs3c64xx  smdk6400:SYS_TEXT_BASE=0x57e0
+smdk6400_nousb   arm arm1176 smdk6400
samsungs3c64xx  smdk6400:SYS_TEXT_BASE=0xc7e0
 tnetv107x_evmarm arm1176 tnetv107xevmti
 tnetv107x
 integratorap_cm720t  arm arm720t integrator  
armltd -   integratorap:CM720T
 integratorap_cm920t  arm arm920t integrator  
armltd -   integratorap:CM920T
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 3642a5c..06b85bf 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -54,7 +54,7 @@
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ1200
 
-#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc000)
+#if !defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_TEXT_BASE >= 0xc000)
 #define CONFIG_ENABLE_MMU
 #endif
 
diff --git a/nand_spl/board/samsung/smdk6400/Makefile 
b/nand_spl/board/samsung/smdk6400/Makefile
deleted file mode 100644
index c9e75ba..000
--- a/nand_spl/board/samsung/smdk6400/Makefile
+++ /dev/null
@@ -1,117 +0,0 @@
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, s...@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, 
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_NAND_SPL= y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj:= $(OBJTREE)/nand_spl/
-
-

[U-Boot] [V2 06/15] S3C64xx: mov cpu_init.S to the board directory

[Zhong Hongbo]

From: Zhong Hongbo 

It just only do the memory init. The memory depend on the
design of board.

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- None.
---
 arch/arm/cpu/arm1176/s3c64xx/Makefile   |2 +-
 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S |  135 ---
 board/samsung/smdk6400/Makefile |2 +-
 board/samsung/smdk6400/mem_init.S   |  135 +++
 4 files changed, 137 insertions(+), 137 deletions(-)
 delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
 create mode 100644 board/samsung/smdk6400/mem_init.S

diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile 
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 93f..2f37431 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -30,7 +30,7 @@ LIB   = $(obj)lib$(SOC).o
 
 SOBJS  = reset.o
 
-COBJS-$(CONFIG_S3C6400)+= cpu_init.o speed.o
+COBJS-$(CONFIG_S3C64XX)+= speed.o
 COBJS-y+= timer.o
 COBJS-$(CONFIG_PWM) += pwm.o
 
diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S 
b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
deleted file mode 100644
index df88cba..000
--- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, 
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include 
-#include 
-
-   .globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-   /* DMC1 base address 0x7e001000 */
-   ldr r0, =ELFIN_DMC1_BASE
-
-   ldr r1, =0x4
-   str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-   ldr r1, =DMC_DDR_REFRESH_PRD
-   str r1, [r0, #INDEX_DMC_REFRESH_PRD]
-
-   ldr r1, =DMC_DDR_CAS_LATENCY
-   str r1, [r0, #INDEX_DMC_CAS_LATENCY]
-
-   ldr r1, =DMC_DDR_t_DQSS
-   str r1, [r0, #INDEX_DMC_T_DQSS]
-
-   ldr r1, =DMC_DDR_t_MRD
-   str r1, [r0, #INDEX_DMC_T_MRD]
-
-   ldr r1, =DMC_DDR_t_RAS
-   str r1, [r0, #INDEX_DMC_T_RAS]
-
-   ldr r1, =DMC_DDR_t_RC
-   str r1, [r0, #INDEX_DMC_T_RC]
-
-   ldr r1, =DMC_DDR_t_RCD
-   ldr r2, =DMC_DDR_schedule_RCD
-   orr r1, r1, r2
-   str r1, [r0, #INDEX_DMC_T_RCD]
-
-   ldr r1, =DMC_DDR_t_RFC
-   ldr r2, =DMC_DDR_schedule_RFC
-   orr r1, r1, r2
-   str r1, [r0, #INDEX_DMC_T_RFC]
-
-   ldr r1, =DMC_DDR_t_RP
-   ldr r2, =DMC_DDR_schedule_RP
-   orr r1, r1, r2
-   str r1, [r0, #INDEX_DMC_T_RP]
-
-   ldr r1, =DMC_DDR_t_RRD
-   str r1, [r0, #INDEX_DMC_T_RRD]
-
-   ldr r1, =DMC_DDR_t_WR
-   str r1, [r0, #INDEX_DMC_T_WR]
-
-   ldr r1, =DMC_DDR_t_WTR
-   str r1, [r0, #INDEX_DMC_T_WTR]
-
-   ldr r1, =DMC_DDR_t_XP
-   str r1, [r0, #INDEX_DMC_T_XP]
-
-   ldr r1, =DMC_DDR_t_XSR
-   str r1, [r0, #INDEX_DMC_T_XSR]
-
-   ldr r1, =DMC_DDR_t_ESR
-   str r1, [r0, #INDEX_DMC_T_ESR]
-
-   ldr r1, =DMC1_MEM_CFG
-   str r1, [r0, #INDEX_DMC_MEMORY_CFG]
-
-   ldr r1, =DMC1_MEM_CFG2
-   str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
-
-   ldr r1, =DMC1_CHIP0_CFG
-   str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
-
-   ldr r1, =DMC_DDR_32_CFG
-   str r1, [r0, #INDEX_DMC_USER_CONFIG]
-
-   /* DMC0 DDR Chip 0 configuration direct command reg */
-   ldr r1, =DMC_NOP0
-   str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-   /* Precharge All */
-   ldr r1, =DMC_PA0
-   str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-   /* Auto Refresh 2 time */
-   ldr r1, =DMC_AR0
-   str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-   str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-   /* MRS */
-   ldr r1, =DMC_mDDR_EMR0
-   str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-   /* Mode Reg */
-   ldr r1, =DMC_mDDR_MR0
-   str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-   /* Enable DMC1 */
-   mov r1, #0x0
-   str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-check_dmc1_ready:
-   ldr r1, [r0, #INDEX_DMC_

[U-Boot] [V2 05/15] S3C64XX: reference s5p cpu time system for s3c64xx timer

[Zhong Hongbo]

From: Zhong Hongbo 

The old s3c64xx timer is not work normal, Adopt s5p time design,
It work perfect.

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- Delete const key word for the variable of struct s3c_timer.
---
 arch/arm/cpu/arm1176/s3c64xx/timer.c |  193 --
 1 files changed, 93 insertions(+), 100 deletions(-)

diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c 
b/arch/arm/cpu/arm1176/s3c64xx/timer.c
index f16a37b..47d7731 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -1,23 +1,8 @@
 /*
- * (C) Copyright 2003
- * Texas Instruments 
+ * Copyright (C) 2012
+ * Zhong Hongbo 
  *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH 
- * Marius Groeger 
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH 
- * Alex Zuepke 
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, 
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. 
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, 
+ * based on arch/arm/cpu/armv7/s5p-common/timer.c
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -39,64 +24,29 @@
  */
 
 #include 
-#include 
+#include 
 #include 
-#include 
-
-static ulong timer_load_val;
+#include 
+#include 
 
-#define PRESCALER  167
+DECLARE_GLOBAL_DATA_PTR;
 
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
-   return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
+static unsigned long get_current_tick(void);
 
 /* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
+static inline struct s3c_timer *s3c_get_base_timer(void)
 {
-   s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-   return timers->TCNTO4;
+   return (struct s3c_timer *)s3c64xx_get_base_timer();
 }
 
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
 int timer_init(void)
 {
-   s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-   /* use PWM Timer 4 because it has no output */
-   /*
-* We use the following scheme for the timer:
-* Prescaler is hard fixed at 167, divider at 1/4.
-* This gives at PCLK frequency 66MHz approx. 10us ticks
-* The timer is set to wrap after 100s, at 66MHz this obviously
-* happens after 10,000,000 ticks. A long variable can thus
-* keep values up to 40,000s, i.e., 11 hours. This should be
-* enough for most uses:-) Possible optimizations: select a
-* binary-friendly frequency, e.g., 1ms / 128. Also calculate
-* the prescaler automatically for other PCLK frequencies.
-*/
-   timers->TCFG0 = PRESCALER << 8;
-   if (timer_load_val == 0) {
-   timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
-   timers->TCFG1 = (timers->TCFG1 & ~0xf) | 0x2;
-   }
-
-   /* load value for 10 ms timeout */
-   lastdec = timers->TCNTB4 = timer_load_val;
-   /* auto load, manual update of Timer 4 */
-   timers->TCON = (timers->TCON & ~0x0070) | TCON_4_AUTO |
-   TCON_4_UPDATE;
+   /* PWM Timer 4 */
+   pwm_init(4, MUX_DIV_2, 0);
+   pwm_config(4, 0, 0);
+   pwm_enable(4);
 
-   /* auto load, start Timer 4 */
-   timers->TCON = (timers->TCON & ~0x0070) | TCON_4_AUTO | COUNT_4_ON;
-   timestamp = 0;
+   reset_timer_masked();
 
return 0;
 }
@@ -104,57 +54,100 @@ int timer_init(void)
 /*
  * timer without interrupts
  */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+unsigned long get_timer(unsigned long base)
 {
-   ulong now = read_timer();
+   return get_timer_masked() - base;
+}
 
-   if (lastdec >= now) {
-   /* normal mode */
-   timestamp += lastdec - now;
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+   struct s3c_timer *timer = s3c_get_base_timer();
+   unsigned long tmo, tmp, count_value;
+
+   count_value = readl(&timer->tcntb4);
+
+   if (usec >= 1000) {
+   /*
+* if "big" number, spread normalization
+* to seconds
+* 1. start to normalize for usec to ticks per sec
+* 2. find number of "ticks" to wait to achieve target
+* 3. finish normalize.
+*/
+   tmo = usec / 1000;
+   tmo *= (CONFIG_SYS_HZ * count_value);
+   tmo /= 1000;
} else {
-   /* we have an overflow ... */
-   timestamp += lastdec + timer_load_val - now;
+   /* else small number, don't kill it prior to HZ multiply */
+   tmo = usec * CONFIG_SYS_HZ * count_value;
+   tmo /= (1000 

[U-Boot] [V2 04/15] S3C64XX: add pwm for s3c64xx support

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- Change the type of the return value from unsinged int
  to unsinged long for s3c64xx_get_base_nand function.
---
 arch/arm/cpu/arm1176/s3c64xx/Makefile   |1 +
 arch/arm/cpu/arm1176/s3c64xx/pwm.c  |  189 +++
 arch/arm/include/asm/arch-s3c64xx/pwm.h |   70 ++
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |   56 ++---
 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h |   59 -
 include/configs/smdk6400.h  |3 +
 6 files changed, 272 insertions(+), 106 deletions(-)
 create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c
 create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h
 delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h

diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile 
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 0785b19..93f 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -32,6 +32,7 @@ SOBJS = reset.o
 
 COBJS-$(CONFIG_S3C6400)+= cpu_init.o speed.o
 COBJS-y+= timer.o
+COBJS-$(CONFIG_PWM) += pwm.o
 
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 
diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c 
b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
new file mode 100644
index 000..d1d70ff
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2012
+ *
+ * Zhong Hongbo 
+ *
+ * based on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int pwm_enable(int pwm_id)
+{
+   const struct s3c_timer *pwm =
+   (struct s3c_timer *)s3c64xx_get_base_timer();
+   unsigned long tcon;
+
+   tcon = readl(&pwm->tcon);
+   tcon |= TCON_START(pwm_id);
+
+   writel(tcon, &pwm->tcon);
+
+   return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+   const struct s3c_timer *pwm =
+   (struct s3c_timer *)s3c64xx_get_base_timer();
+   unsigned long tcon;
+
+   tcon = readl(&pwm->tcon);
+   tcon &= ~TCON_START(pwm_id);
+
+   writel(tcon, &pwm->tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+   unsigned long tin_parent_rate;
+   unsigned int div;
+
+   tin_parent_rate = get_PCLK();
+
+   for (div = 2; div <= 16; div *= 2) {
+   if ((tin_parent_rate / (div << 16)) < freq)
+   return tin_parent_rate / div;
+   }
+
+   return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (10UL)
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+   const struct s3c_timer *pwm =
+   (struct s3c_timer *)s3c64xx_get_base_timer();
+   unsigned int offset;
+   unsigned long tin_rate;
+   unsigned long tin_ns;
+   unsigned long period;
+   unsigned long tcon;
+   unsigned long tcnt;
+   unsigned long tcmp;
+
+   /*
+* We currently avoid using 64bit arithmetic by using the
+* fact that anything faster than 1GHz is easily representable
+* by 32bits.
+*/
+   if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+   return -ERANGE;
+
+   if (duty_ns > period_ns)
+   return -EINVAL;
+
+   period = NS_IN_HZ / period_ns;
+
+   /* Check to see if we are changing the clock rate of the PWM */
+   tin_rate = pwm_calc_tin(pwm_id, period);
+
+   tin_ns = NS_IN_HZ / tin_rate;
+   tcnt = period_ns / tin_ns;
+
+   /* Note, counters count down */
+   tcmp = duty_ns / tin_ns;
+   tcmp = tcnt - tcmp;
+
+   /*
+* the pwm hw only checks the compare register after a decrement,
+* so the pin never toggles if tcmp = tcnt
+*/
+   if (tcmp == tcnt)
+   tcmp--;
+
+   if (tcmp < 0)
+   tcmp = 0;
+
+   /* Update the PWM register block. */
+   offset = pwm_id * 3;
+   if (pwm_id < 4) {
+   writel(tcnt, &pwm->tcntb0 + offset);
+   writel(tcmp, &pwm->tcmpb0 + offset);
+   }
+
+   tcon = readl(&pwm->tcon);
+   tco

[U-Boot] [V2 03/15] S3C64XX: Use readl/writel to operate uart

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- Change the type of the return value from unsinged int
   to unsinged long for s3c64xx_get_base_uart function.
- Delete const for the local variable.
---
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |   65 +--
 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h |   31 -
 arch/arm/include/asm/arch-s3c64xx/uart.h|   54 ++
 board/samsung/smdk6400/lowlevel_init.S  |8 ---
 drivers/serial/s3c64xx.c|   50 +
 5 files changed, 87 insertions(+), 121 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-s3c64xx/uart.h

diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h 
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index d6c5dd9..77b9509 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -582,62 +582,6 @@
  */
 #define ELFIN_UART_BASE0x7F005000
 
-#define ELFIN_UART0_OFFSET 0x
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET   0x00
-#define UCON_OFFSET0x04
-#define UFCON_OFFSET   0x08
-#define UMCON_OFFSET   0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET  0x18
-#define UMSTAT_OFFSET  0x1C
-#define UTXH_OFFSET0x20
-#define URXH_OFFSET0x24
-#define UBRDIV_OFFSET  0x28
-#define UDIVSLOT_OFFSET0x2C
-#define UINTP_OFFSET   0x30
-#define UINTSP_OFFSET  0x34
-#define UINTM_OFFSET   0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG  __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG   __REG(0x7F005010)
-#define UERSTAT0_REG   __REG(0x7F005014)
-#define UFSTAT0_REG__REG(0x7F005018)
-#define UMSTAT0_REG__REG(0x7F00501c)
-#define UTXH0_REG  __REG(0x7F005020)
-#define URXH0_REG  __REG(0x7F005024)
-#define UBRDIV0_REG__REG(0x7F005028)
-#define UDIVSLOT0_REG  __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG__REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG  __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG   __REG(0x7F005410)
-#define UERSTAT1_REG   __REG(0x7F005414)
-#define UFSTAT1_REG__REG(0x7F005418)
-#define UMSTAT1_REG__REG(0x7F00541c)
-#define UTXH1_REG  __REG(0x7F005420)
-#define URXH1_REG  __REG(0x7F005424)
-#define UBRDIV1_REG__REG(0x7F005428)
-#define UDIVSLOT1_REG  __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG__REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY   (1 << 2)
-#define UTRSTAT_RX_READY   (1 << 0)
-#define UART_ERR_MASK  0xF
-
 /*
  * PWM timer
  */
@@ -804,17 +748,12 @@
 #define DMC_DDR_USER_CONFIG1
 
 #ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
-   S3C64XX_UART0,
-   S3C64XX_UART1,
-   S3C64XX_UART2,
-};
 
 #include "s3c64x0.h"
 
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+static inline unsigned long s3c64xx_get_base_uart(void)
 {
-   return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+   return ELFIN_UART_BASE;
 }
 
 static inline unsigned long s3c64xx_get_base_nand(void)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h 
b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
index 0bbf1d0..7add68c 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
@@ -40,37 +40,6 @@
 
 #include 
 
-/* UART (see manual chapter 11) */
-typedef struct {
-   volatile u32ULCON;
-   volatile u32UCON;
-   volatile u32UFCON;
-   volatile u32UMCON;
-   volatile u32UTRSTAT;
-   volatile u32UERSTAT;
-   volatile u32UFSTAT;
-   volatile u32UMSTAT;
-#ifdef __BIG_ENDIAN
-   volatile u8 res1[3];
-   volatile u8 UTXH;
-   volatile u8 res2[3];
-   volatile u8 URXH;
-#else /* Little Endian */
-   volatile u8 UTXH;
-   volatile u8 res1[3];
-   volatile u8 URXH;
-   volatile u8 res2[3];
-#endif
-   volatile u32UBRDIV;
-#ifdef __BIG_ENDIAN
-   volatile u8 res3[2];
-   volatile u16UDIVSLOT;
-#else
-   volatile u16UDIVSLOT;
-   volatile u8 res3[2];
-#endif
-} s3c64xx_uart;
-
 /* PWM TIMER (see manual chapter 10)

[U-Boot] [V2 02/15] S3C64XX: Switch to use readl/writel to operate nand flash

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- Change the type of the return value from unsinged int
  to unsinged long for s3c64xx_get_base_nand function.
- Delete const for the local variable.
---
 arch/arm/include/asm/arch-s3c64xx/nand.h|   69 +++
 arch/arm/include/asm/arch-s3c64xx/s3c6400.h |   79 ++-
 board/samsung/smdk6400/lowlevel_init.S  |8 ++--
 drivers/mtd/nand/s3c64xx.c  |   58 +---
 4 files changed, 116 insertions(+), 98 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h

diff --git a/arch/arm/include/asm/arch-s3c64xx/nand.h 
b/arch/arm/include/asm/arch-s3c64xx/nand.h
new file mode 100644
index 000..51e4d34
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/nand.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_NAND_H__
+#define __ASM_ARCH_NAND_H__
+
+#define NFCONF_ECC_4BIT(1<<24)
+
+#define NFCONT_ECC_ENC (1<<18)
+#define NFCONT_WP  (1<<16)
+#define NFCONT_MECCLOCK(1<<7)
+#define NFCONT_SECCLOCK(1<<6)
+#define NFCONT_INITMECC(1<<5)
+#define NFCONT_INITSECC(1<<4)
+#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT  (1<<2)
+#define NFCONT_CS  (1<<1)
+#define NFCONT_ENABLE  (1<<0)
+
+#define NFSTAT_ECCENCDONE  (1<<7)
+#define NFSTAT_ECCDECDONE  (1<<6)
+#define NFSTAT_RnB (1<<0)
+
+#define NFESTAT0_ECCBUSY   (1<<31)
+
+#ifndef __ASSEMBLY__
+/* NAND FLASH */
+struct s3c64xx_nand {
+   u32 nfconf;
+   u32 nfcont;
+   u32 nfcmmd;
+   u32 nfaddr;
+   u32 nfdata;
+   u32 nfmeccdata0;
+   u32 nfmeccdata1;
+   u32 nfseccdata0;
+   u32 nfsblk;
+   u32 nfeblk;
+   u32 nfstat;
+   u32 nfestat0;
+   u32 nfestat1;
+   u32 nfmecc0;
+   u32 nfmecc1;
+   u32 nfsecc;
+   u32 nfmlcbitpt;
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h 
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 10b3324..d6c5dd9 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -556,80 +556,6 @@
  */
 #define ELFIN_NAND_BASE0x7020
 
-#define NFCONF_OFFSET  0x00
-#define NFCONT_OFFSET  0x04
-#define NFCMMD_OFFSET  0x08
-#define NFADDR_OFFSET  0x0c
-#define NFDATA_OFFSET  0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET  0x20
-#define NFEBLK_OFFSET  0x24
-#define NFSTAT_OFFSET  0x28
-#define NFESTAT0_OFFSET0x2c
-#define NFESTAT1_OFFSET0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET  0x3c
-#define NFMLCBITPT_OFFSET  0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0   (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1   (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC (EL

[U-Boot] [V2 01/15] SMDK6400: Move smdk6400 board from Makefile to boards.cfg

[Zhong Hongbo]

From: Zhong Hongbo 

Signed-off-by: Zhong Hongbo 
---
Change for V2:
- None
---
 Makefile |   20 
 board/samsung/smdk6400/config.mk |4 +---
 boards.cfg   |2 ++
 include/configs/smdk6400.h   |2 +-
 4 files changed, 4 insertions(+), 24 deletions(-)

diff --git a/Makefile b/Makefile
index 0197239..e3af33f 100644
--- a/Makefile
+++ b/Makefile
@@ -695,26 +695,6 @@ SX1_config:unconfig
fi;
@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
 
-#
-## ARM1176 Systems
-#
-smdk6400_noUSB_config  \
-smdk6400_config:   unconfig
-   @mkdir -p $(obj)include $(obj)board/samsung/smdk6400
-   @mkdir -p $(obj)nand_spl/board/samsung/smdk6400
-   @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
-   @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-   @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then   
\
-   echo "RAM_TEXT = 0x57e0" >> 
$(obj)board/samsung/smdk6400/config.tmp;\
-   else
\
-   echo "RAM_TEXT = 0xc7e0" >> 
$(obj)board/samsung/smdk6400/config.tmp;\
-   fi
-   @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
-   @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-
-#
-#
-
 clean:
@rm -f $(obj)examples/standalone/82559_eeprom \
   $(obj)examples/standalone/atmel_df_pow2\
diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk
index 6f04c2f..93a1a0d 100644
--- a/board/samsung/smdk6400/config.mk
+++ b/board/samsung/smdk6400/config.mk
@@ -21,10 +21,8 @@
 #
 # download area is 0x5000c000
 
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
 ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
+CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT)
 else
 CONFIG_SYS_TEXT_BASE = 0
 endif
diff --git a/boards.cfg b/boards.cfg
index 9205070..a6ca01f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -47,6 +47,8 @@ flea3arm arm1136 -
   CarMedi
 mx35pdk  arm arm1136 -   
freescale  mx35
 apollon arm arm1136 apollon
 -  omap24xx
 omap2420h4   arm arm1136 -   ti
 omap24xx
+smdk6400 arm arm1176 smdk6400
samsungs3c64xx  smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e0
+smdk6400_nousb   arm arm1176 smdk6400
samsungs3c64xx  smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e0
 tnetv107x_evmarm arm1176 tnetv107xevmti
 tnetv107x
 integratorap_cm720t  arm arm720t integrator  
armltd -   integratorap:CM720T
 integratorap_cm920t  arm arm920t integrator  
armltd -   integratorap:CM920T
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 04caeef..47326d6 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -54,7 +54,7 @@
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ1200
 
-#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc000)
+#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc000)
 #define CONFIG_ENABLE_MMU
 #endif
 
-- 
1.7.5.4

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[U-Boot] V2 S3c64xx: Switch all I/O to use readl/writel functio and Clear variable

[Zhong Hongbo]

V2:
1. Modify the type of return for s3c64xx_get_base_nand
2. Add patch 0014 to support s3c6410 board
3. Adjust patch for mix content.

V1:
This serial patch intent to:
1. Switch all I/O to use readl/writel function
2. Change nand_spl to use SPL framework
3. S3C64XX serial includes s3c6400 and s3c6410,
Here seprate cpu and board file to support to board's of s3c6410.


I test this patch on my s3c6410 development board. the log as following:

U-Boot 2012.04.01-10905-g9fa0c77 (Jul 07 2012 - 15:50:57) for SMDK6400


CPU: S3C64XX@532MHz
 Fclk = 532MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode) 
Board:   DMATEK6410
DRAM:  128 MiB
WARNING: Caches not enabled
NAND:  128 MiB
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   dm9000
Hit any key to stop autoboot:  0 
DMATEK6410 #


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Re: [U-Boot] [PATCH] cfb_console: Add support for some ANSI terminal escape codes

[Pali Rohár]

On Sunday 01 July 2012 12:34:49 Pali Rohár wrote:
> Hello,
>
> I'm sending new patch which add support for ANSI terminal in
> cfb_console driver. This patch comes from RX-51 patch series,
> but more cfb patches were commited to u-boot git. This is last
> patch for cfb driver, so I'm sending it separatly. Changes
> from last version: this patch is rebased on top of u-boot
> master and has fixed comment style problems.
>

I know that now is time for summmer holiday. When you have time,
look at my patch and write me if is OK now.

--
Pali Rohár
pali.ro...@gmail.com

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[U-Boot] Doubt on uboot code

[VISWANADHULA BALAJI]

Hi,

  Thank you for your reply.

 I have the U-boot source code of SAMSUNG EXYNOS SMDKV310 board. When i
compiled the U-boot source code I got uboot.bin file and bl1.bin file.
Actually bl1.bin file is extracted from the uboot.bin file by using the
mkbl2 tool(tool's source code is present in the U-boot source itself)and
used as a first stage bootloader.Uboot.bin file is used as a second stage
bootloader.

   "bl1.bin responsibility is to load the second stage bootloader from
the sd card to SD RAM".*I have the doubt in the bl1.bin file *how the above
mentioned transforming  is done from the following device copy function.

   #define SDMMC_ReadBlocks_eMMC_ByCPU(uNumOfBlks, uDstAddr) \
(((void(*)(u32, u32*))(*((u32
*)EXT_eMMC43_BL2_ByCPU_ADDRESS)))(uNumOfBlks, uDstAddr))

The above MACRO is the Physical adress which is mapped to IRAM

The above indirect function is present in the following source code path

 board/samsung/smdkv310/lowlevel_init.S.


Actually I have to design the IROM code similar to SAMSUNG EXYNOS SOC.
Please Help me in this.



Thanks

Balaji
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[U-Boot] [PATCH] dts/Makefile: Turn off system-/gcc-specific predefined macros

[Horst Kronstorfer]

Add '-undef' to DTS_CPPFLAGS to avoid unwanted expansion of dts content
that matches system-specific or gcc-specific predefined macros.

Example: A number of PowerPC related *.dts files in the kernel define a
property named 'linux,network-index' which (w/o '-undef') is expanded to
'1,network-index' by the preprocessor because of '#define linux 1.'

With '-undef' in place only the standard predefined macros are visible:

 $ gcc -dM -E -undef - 
---
 dts/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dts/Makefile b/dts/Makefile
index 402dfe1..3c6bc18 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -36,7 +36,7 @@ $(error Your architecture does not have device tree support 
enabled. \
 Please define CONFIG_ARCH_DEVICE_TREE))
 
 # We preprocess the device tree file provide a useful define
-DTS_CPPFLAGS := 
-DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\"
+DTS_CPPFLAGS := -undef 
-DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\"
 
 all:   $(obj).depend $(LIB)
 
-- 
1.7.11.2

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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Tabi Timur-B04825]

sun york-R58495 wrote:

> I agree it was a broken design. Now we are using all available space
> and put CRC to the very end. It is not perfect but should work.

*sigh*

The design was never broken, the code was just wrong.  The CRC has always 
supposed to have been at the end.

-- 
Timur Tabi
Linux kernel developer at Freescale


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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Tabi Timur-B04825]

Wolfgang Denk wrote:
>> >My patch provides transparent updates to handle it.  It will read broken
>> >EEPROMs and verify the CRC in the old location, and if you have re-save
>> >the EEPROM, it will put the CRC in the right place.

> It will work by chance, accessing random data.  This is crap.

It is not crap, and it will not work by chance.  It is not accessing 
random data, it is accessing the CRC in the old location, just like the 
current code does today.

-- 
Timur Tabi
Linux kernel developer at Freescale


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Re: [U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location

[Tabi Timur-B04825]

Wolfgang Denk wrote:
> This is a totally broken design then, when you have a growing data
> structure where vital information fields get shifted.  In such case,
> the CRC should have been at the beginning, so it never changes
> location. Or even better, you should not have used a binary data
> structure at all (guess why the environment in U-Boot has been
> implemented the way it is).

York is mistaken.  The CRC was always at location 0xFC, but for some 
reason, when I wrote the code, I put it at 0xCC.  Now I'm fixing it, and 
providing some backwards compatibility to avoid causing problems for 
people who upgrade U-Boot on existing boards.  I don't see how this is 
controversial in any way.

-- 
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Linux kernel developer at Freescale


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Re: [U-Boot] [PATCH 3/3] mxc_i2c: remove setting speed at each start

[Marek Vasut]

Dear Wolfgang Denk,

> Dear Marek Vasut,
> 
> In message <201207131238.11964.ma...@denx.de> you wrote:
> > > > Ok, everything was already clear, and I can also add my:
> > > > 
> > > > Acked-by: Stefano Babic 
> > > 
> > > Same for this one: Is this applied anywhere? It doesn't seem to be part
> > > of v2012.07-rc1?
> > > 
> > > Best regards
> > 
> > Stefano, once you're out of mont blanc, can you apply this please?
> 
> This is in mainline:
> 
> 9ca37d7   2012-07-11 10:54:52 +0200   mxc_i2c: remove setting speed at each
> start

Ok, sorry for the noise then.

> Best regards,
> 
> Wolfgang Denk

Best regards,
Marek Vasut
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Re: [U-Boot] [U-Boot-DM] FDT driver initialization function declaration

[Tomas Hlavacek]

On Thu, Jul 12, 2012 at 10:22 AM, Michal Simek  wrote:
>
>
>> thats what platform_data is for, if i understand what you mean
>>
>
> That's my understanding too. But the point is how it is passed to the
> driver itself
> because I didn't see any pointer to it there.
>
>
I had an impression that platform data are and should be static and
therefore universally visible/known...?

Tomas

-- 
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[U-Boot] [PATCH] Add support for DS1388.

[Kenth Eriksson]

Support for DS1388 is added by extending the DS1337 driver. DS1388 is similar 
to DS1337. The time registers are offset by 1 (due to support for hundreds of 
seconds), and there is no century bit. The configuration and trickle charge 
registers are also different. Tested on hardware with Freescale P2010 and 
DS1388.

Signed-off-by: Kenth Eriksson 
---
 drivers/rtc/Makefile |1 +
 drivers/rtc/ds1337.c |   26 ++
 2 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index faf4fcd..9cfdbf9 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_RTC_DS1307) += ds1307.o
 COBJS-$(CONFIG_RTC_DS1338) += ds1307.o
 COBJS-$(CONFIG_RTC_DS1337) += ds1337.o
 COBJS-$(CONFIG_RTC_DS1374) += ds1374.o
+COBJS-$(CONFIG_RTC_DS1388) += ds1337.o
 COBJS-$(CONFIG_RTC_DS1556) += ds1556.o
 COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
 COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 5bb9f94..4c98732 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -37,6 +37,7 @@
 /*
  * RTC register addresses
  */
+#if defined CONFIG_RTC_DS1337
 #define RTC_SEC_REG_ADDR   0x0
 #define RTC_MIN_REG_ADDR   0x1
 #define RTC_HR_REG_ADDR0x2
@@ -47,6 +48,18 @@
 #define RTC_CTL_REG_ADDR   0x0e
 #define RTC_STAT_REG_ADDR  0x0f
 #define RTC_TC_REG_ADDR0x10
+#elif defined CONFIG_RTC_DS1388
+#define RTC_SEC_REG_ADDR   0x1
+#define RTC_MIN_REG_ADDR   0x2
+#define RTC_HR_REG_ADDR0x3
+#define RTC_DAY_REG_ADDR   0x4
+#define RTC_DATE_REG_ADDR  0x5
+#define RTC_MON_REG_ADDR   0x6
+#define RTC_YR_REG_ADDR0x7
+#define RTC_CTL_REG_ADDR   0x0c
+#define RTC_STAT_REG_ADDR  0x0b
+#define RTC_TC_REG_ADDR0x0a
+#endif
 
 /*
  * RTC control register bits
@@ -87,6 +100,11 @@ int rtc_get (struct rtc_time *tmp)
mon_cent = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
 
+   /* No century bit, assume year 2000 */
+#ifdef CONFIG_RTC_DS1388
+   mon_cent |= 0x80;
+#endif
+
debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
year, mon_cent, mday, wday, hour, min, sec, control, status);
@@ -151,6 +169,7 @@ int rtc_set (struct rtc_time *tmp)
  * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
  * off the OSC output.
  */
+
 #ifdef CONFIG_SYS_RTC_DS1337_NOOSC
  #define RTC_DS1337_RESET_VAL \
(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
@@ -159,10 +178,17 @@ int rtc_set (struct rtc_time *tmp)
 #endif
 void rtc_reset (void)
 {
+#ifdef CONFIG_SYS_RTC_DS1337
rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
+#elif defined CONFIG_SYS_RTC_DS1388
+   rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
+#endif
 #ifdef CONFIG_SYS_DS1339_TCR_VAL
rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
 #endif
+#ifdef CONFIG_SYS_DS1388_TCR_VAL
+   rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL);
+#endif
 }
 
 
-- 
1.7.3.4

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Re: [U-Boot] [PATCH 3/3] mxc_i2c: remove setting speed at each start

[Wolfgang Denk]

Dear Marek Vasut,

In message <201207131238.11964.ma...@denx.de> you wrote:
> 
> > > Ok, everything was already clear, and I can also add my:
> > > 
> > > Acked-by: Stefano Babic 
> > 
> > Same for this one: Is this applied anywhere? It doesn't seem to be part
> > of v2012.07-rc1?
> > 
> > Best regards
> 
> Stefano, once you're out of mont blanc, can you apply this please?

This is in mainline:

9ca37d7   2012-07-11 10:54:52 +0200   mxc_i2c: remove setting speed at each 
start


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
The rule on staying alive as a program manager is to give 'em a  num-
ber or give 'em a date, but never give 'em both at once.
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Re: [U-Boot] [U-Boot-DM] FDT driver initialization function declaration

[Marek Vasut]

Dear Tomas Hlavacek,

> On Thu, Jul 12, 2012 at 10:22 AM, Michal Simek  wrote:
> >> thats what platform_data is for, if i understand what you mean
> > 
> > That's my understanding too. But the point is how it is passed to the
> > driver itself
> > because I didn't see any pointer to it there.
> 
> I had an impression that platform data are and should be static and
> therefore universally visible/known...?

Passed through struct driver_info * which is in turn available through struct 
instance *

> Tomas

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] mxc_i2c: remove setting speed at each start

[Marek Vasut]

Dear Dirk Behme,

[...]

> > Ok, everything was already clear, and I can also add my:
> > 
> > Acked-by: Stefano Babic 
> 
> Same for this one: Is this applied anywhere? It doesn't seem to be part
> of v2012.07-rc1?
> 
> Best regards

Stefano, once you're out of mont blanc, can you apply this please?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] NET: NE2000: Cleanup IO accessors

[Marek Vasut]

Dear Joe Hershberger,

> Hi Marek,
> 
> On Fri, Dec 16, 2011 at 2:36 PM, Marek Vasut  wrote:
> >> On Friday 16 December 2011 13:13:33 Marek Vasut wrote:
> >> > On Friday 16 December 2011 12:33:53 Mike Frysinger wrote:
> >> > > rename ISA_OFFSET to CONFIG_NE2000_IO_OFFSET, then move the "2" to
> >> > > CONFIG_NE2000_IO_STRIDE, and move them both to the board config
> >> > > header. then you get one unified set:
> >> > > 
> >> > > #define DP_IN(_b_, _o_, _d_) \
> >> > > 
> >> > >   (_d_) = readw((void *)((_b_) + ((_o_) * CONFIG_NE2000_IO_STRIDE) +
> >> > >   \
> >> > >   
> >> > >   CONFIG_NE2000_IO_OFFSET));
> >> > > 
> >> > > etc...
> >> > > 
> >> > > if you really wanted to clean up the driver, the DP_XXX funcs would
> >> > > get turned into C code as static inline helpers, and the base +
> >> > > register offset would get turned into a C struct.
> >> > 
> >> > Ok, so if you had two different piece of hardware that had different
> >> > NE2000_IO_OFFSET and STRIDE, running the same u-boot, how'd you handle
> >> > it ?
> >> 
> >> do you actually have this issue ?  there are plenty of theoretical
> >> situations like this which would break a significant number (majority?)
> >> of drivers in the tree.  so unless this is a real case, i'd ignore it
> >> for now and stick with what optimizes away to no overhead.
> > 
> > Sadly, I almost do. Not now of course, but eventually, I'll be there :-(
> 
> Are you planning to improve this patch?

No, I'll eventually rework this one alongside the whole DM crap.

> I think at the very least you should have a compile option to enable
> this "functional interface" presumably behind a macro, but every user
> of NE2000 should not have to pay the price.  However, like Mike
> suggested, you should only add this complexity if you actually have
> this problem on a board.
> 
> Thanks,
> -Joe

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH V2] i.MX: fsl_esdhc: allow use with cache enabled.

[Marek Vasut]

Dear Dirk Behme,

[...]

> >> I'm not likely to have any time until after FTF next week.
> >> 
> >> Any chance that a PPC maintainer can chime in here?
> > 
> > I think WD applied the cache stub patch already. Can you try now please?
> 
> Ping ;)
> 
> Thanks

Adding our human interactions expert into CC :)

Best regards,
Marek Vasut
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Re: [U-Boot] FDT driver initialization function declaration

[Marek Vasut]

Dear Michal Simek,

> On 07/10/2012 05:11 PM, Marek Vasut wrote:
> > Dear Michal Simek,
> > 
> >> Dear Wolfgang,
> >> 
> >> On 07/10/2012 03:03 PM, Wolfgang Denk wrote:
> >>> Dear Michal Simek,
> >>> 
> >>> In message<4ffc1ef8.9060...@monstr.eu>   you wrote:
>  The hardest part I have identify on microblaze was about u-boot
>  variables. Because based on information from device-tree you can
>  choose where variables should be stored and also this memory should
>  be accessible before u-boot try to read variables. It mean in very
>  early state.
> >>> 
> >>> Device initialization before relocation is already hard enough;
> >>> resources are very limited then.  You will add the additional need to
> >>> have the FDT library available then, too.   Not to mention that you
> >>> need to load the DT blob, too.
> >>> 
> >>> This will be a lot of added complexity.
> >> 
> >> Do you have any timeframe for this work?
> >> Or any expectation when this work should be merged to mainline?
> > 
> > 6 months, 2 releases ... or so. We booted it as a university project to
> > maximize the gain.
> 
> ok. Sounds good. Do you have any repo somewhere?
> I would like to look at it.

There's not much code yet. As for the docs, see git://git.denx.de/u-boot-
marex.git the "dm" branch

> Thanks,
> Michal

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 4/7] dfu: MMC specific routines for DFU operation

[Marek Vasut]

Dear Tom Rini,

> On Thu, Jul 12, 2012 at 02:39:27PM +0200, Lukasz Majewski wrote:
> > On Wed, 11 Jul 2012 04:54:31 -0700
> > 
> > Tom Rini  wrote:
> > > On Tue, Jul 10, 2012 at 12:38:54PM +0200, Lukasz Majewski wrote:
> > > > Hi Tom,
> > > > 
> > > > > On Wed, Jul 04, 2012 at 05:48:39PM +0200, Lukasz Majewski wrote:
> > > > > > Support for MMC storage devices to work with DFU framework.
> > > > > > 
> > > > > > Signed-off-by: Lukasz Majewski 
> > > > > > Signed-off-by: Kyungmin Park 
> > > > > > Cc: Marek Vasut 
> > > > > 
> > > > > [snip]
> > > > > 
> > > > > > +   case RAW_ADDR:
> > > > > > +   sprintf(cmd_buf, "mmc write 0x%x %x %x",
> > > > > > (unsigned int) buf,
> > > > > > +   dfu->data.mmc.lba_start,
> > > > > > dfu->data.mmc.lba_size);
> > > > > > +   break;
> > > > > > +   case FAT:
> > > > > > +   sprintf(cmd_buf, "fatwrite mmc %d:%d 0x%x %s
> > > > > > %lx",
> > > > > > +   dfu->data.mmc.dev, dfu->data.mmc.part,
> > > > > > +   (unsigned int) buf, dfu->name, *len);
> > > > > > +   break;
> > > > > > +   default:
> > > > > > +   printf("%s: Wrong layout!\n", __func__);
> > > > > > +   }
> > > > > > +
> > > > > > +   debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
> > > > > > +   run_command(cmd_buf, 0);
> > > > > 
> > > > > If we try and take the long-view here, that fatwrite/mmc write
> > > > > don't perform a lot of sanity checking on input isn't good.  Lots
> > > > > of commands I believe don't, but we can start somewhere.
> > > > 
> > > > Yes, indeed they don't. But I think, that it is a deeper problem.
> > > > 
> > > > When one looks into the cmd_mmc.c, the code is not checking the
> > > > correctness of passed data. It performs strncmp, then simple_strtoul
> > > > and with this parameter calls mmc->block_dev.block_read().
> > > > 
> > > > But I'm a bit concern if adding function:
> > > > 
> > > > do_mmcops_check(unsigned int lba_start, unsigned int lba_end, ...)
> > > > to
> > > > 
> > > > do_mmcops(argc, argv) {
> > > > 
> > > > int i = simple_strtol(argv[]);
> > > > return do_mmcops_check(i);
> > > > 
> > > > }
> > > 
> > > Well, what I was suggesting would be:
> > > 
> > > do_mmcops_real(uint lba_start, ...) { .. most of do_mmcops today .. }
> > > do_mmcops_from_cmd(argc, argv) {
> > > 
> > >  ... convert user input today, maybe try and sanity check input
> > > 
> > > tomorrow ..
> > > }
> > > 
> > > And then dfu calls do_mmcops_real(lba_start, ...).  A further clean-up
> > > would be to make the interface the command uses to perform checking of
> > > the arguments passed.  Does this make sense?
> > 
> > Generally it is in my opinion a good way to go.
> > 
> > However, why we aren't first writing sanity checks for passed arguments?
> 
> Simply because I didn't want to ask you to do a lot more unrelated work
> 
> :)  If you want to split and check the mmc (and fatwrite) argueuments
> 
> and then make the DFU series depend on that, by all means please do so!

Would be cool indeed.

> > We are adding one more level of abstraction, but don't think of the main
> > problem (checking values of passed arguments)?
> > 
> > Anyway we shall wait for Marek's opinion.
> 
> Yes, a good idea as well.

My opinion is that if you'll do the sanity checks, that'd be good. We're right 
before .07 release anyway, so the patches will hit the next merge window. Are 
you up for doing a lot of unrelated work to make this proper?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/2 v3] FSL/eSDHC: enable the clock to detect the SD card

[Marek Vasut]

Dear Huang Changming-R66093,

> Hi, Andy
> There is not any feedback for very long time,
> Could it be applied to u-boot?

Could it be we have a maintainer problem and unhappy contributor problem in 
here?

> Best Regards
> Jerry Huang
> 
> > -Original Message-
> > From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
> > On Behalf Of Huang Changming-R66093
> > Sent: Monday, May 21, 2012 10:35 AM
> > To: Wood Scott-B07421
> > Cc: Marek Vasut; u-boot@lists.denx.de; Andy Fleming
> > Subject: Re: [U-Boot] [PATCH 2/2 v3] FSL/eSDHC: enable the clock to
> > detect the SD card
> > 
> > 
> > 
> > Best Regards
> > Jerry Huang
> > 
> > > -Original Message-
> > > From: Wood Scott-B07421
> > > Sent: Friday, May 18, 2012 11:55 PM
> > > To: Huang Changming-R66093
> > > Cc: u-boot@lists.denx.de; Marek Vasut; Andy Fleming
> > > Subject: Re: [U-Boot] [PATCH 2/2 v3] FSL/eSDHC: enable the clock to
> > > detect the SD card
> > > 
> > > On 05/18/2012 04:57 AM, chang-ming.hu...@freescale.com wrote:
> > > > From: Jerry Huang 
> > > > 
> > > > For FSL low-end processors (VVN2.2), in order to detect the SD card,
> > > > we should enable PEREN, HCKEN and IPGEN to enable the clock.
> > > > Otherwise, after booting the u-boot, and then inserting the SD card,
> > > > the SD card can't be detected.
> > > > For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used.
> > > > And when accessing to these reserved bit, no any impact happened.
> > > 
> > > Again, have you talked to a hardware designer and confirmed that
> > > there's no impact from setting these bits on chips where they're
> > > reserved?  Just because you don't notice any obvious impact doesn't
> > > mean it's totally safe.
> > 
> > Do you read the FSL SDHC driver? If not, please read it first.
> > Without my this patch, FSL SDHC driver has done it as I mentioned.
> > The committer provided the patch to support VVN2.3 should talk to the
> > hardware designer, And he think it is safe. Otherwise he should detect
> > the VVN to do the different thing.
> > The below is the code driver enable these bit:
> > In function set_sysctl:
> > clk = SYSCTL_PEREN | SYSCTL_CKEN;
> > in function esdhc_init:
> > esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
> > 
> > My work is just to pick up the codes from the driver and do it again in
> > function fsl_esdhc_initialize:
> > esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
> > 
> > | SYSCTL_IPGEN | SYSCTL_CKEN);
> > 
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot

Best regards,
Marek Vasut
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Re: [U-Boot] problem on BL1.bin

[Chander Kashyap]

Hi Balaji,

On 13 July 2012 11:04, VISWANADHULA BALAJI  wrote:
> Hi All,
>
> Iam using smdkv310 board of SAMSUNG EXYNOS SOC. How bl1.bin file copy the
> uboot.bin file from SD/MMC card to DDR2 RAM.
>
> by using the following device copy functions
>
> #define SDMMC_ReadBlocks_eMMC_ByCPU(uNumOfBlks, uDstAddr) \
> (((void(*)(u32, u32*))(*((u32
> *)EXT_eMMC43_BL2_ByCPU_ADDRESS)))(uNumOfBlks, uDstAddr))
>
Which file contain this code. As far as i can see there is no such
code in mainline u-boot for smdkv310.
What is the source of u-boot you are working on?
> The  macro EXT_eMMC43_BL2_ByCPU_ADDRESS  is mapped to the IRAM physical
> adress
>
> Please anybody can help me.
>
>
> Thanks
>
> Balaji
>
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>



-- 
with warm regards,
Chander Kashyap
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Re: [U-Boot] ksz9021 phy support

[Dirk Behme]

On 13.07.2012 10:20, Schneider, Kolja wrote:

Hi Troy,

is here any specific reason for the "disable_giga" switch in the ksz9021 phy 
driver? We're just having some issues here, most of the times we don't get the link up 
with a gigabit connection. Anything else that caused trouble on your side, apart from the 
PHY ID mess?


The first versions of the SabreLite had an hardware issue:

"The current schematic has the center tap pin 9 of the MAG/JAC USB combo 
to 3.3 filtered supply. Letting this pin float solves the problem."


https://wiki.linaro.org/Boards/MX6QSabreLite -> Gigabit Ethernet issue

Best regards

Dirk
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[U-Boot] ksz9021 phy support

[Schneider, Kolja]

Hi Troy,

is here any specific reason for the "disable_giga" switch in the ksz9021 phy 
driver? We're just having some issues here, most of the times we don't get the 
link up with a gigabit connection. Anything else that caused trouble on your 
side, apart from the PHY ID mess?

:) Kolja

Kolja Schneider, Software Design
MEN Mikro Elektronik GmbH
Neuwieder Straße 3-7
90411 Nürnberg, Germany
Phone +49-911-99 33 5-251
Fax +49-911-99 33 5-910
kolja.schnei...@men.de
www.men.de
MEN Mikro Elektronik GmbH - Manfred Schmitz (CTO), Udo Fuchs (CFO) - 
Handelsregister/Trade Register AG Nürnberg HRB 5540
Please consider the environment before printing this e-mail

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