[U-Boot] [PATCH v5 25/28] freescale/qixis: Add support for booting from NAND
From: Scott Wood
Use "qixis_reset nand" to reset the board to boot from NAND.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/freescale/common/qixis.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index a49e300..9f6b0e7 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -138,24 +138,23 @@ void qixis_bank_reset(void)
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
}
-/* Set the boot bank to the power-on default bank */
-void clear_altbank(void)
+static void __maybe_unused set_lbmap(int lbmap)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
- reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
+ reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
QIXIS_WRITE(brdcfg[0], reg);
}
-/* Set the boot bank to the alternate bank */
-void set_altbank(void)
+static void __maybe_unused set_rcw_src(int rcw_src)
{
u8 reg;
- reg = QIXIS_READ(brdcfg[0]);
- reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
- QIXIS_WRITE(brdcfg[0], reg);
+ reg = QIXIS_READ(dutcfg[1]);
+ reg = (reg & ~1) | (rcw_src & 1);
+ QIXIS_WRITE(dutcfg[1], reg);
+ QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
}
static void qixis_dump_regs(void)
@@ -201,11 +200,22 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
int i;
if (argc <= 1) {
- clear_altbank();
+ set_lbmap(QIXIS_LBMAP_DFLTBANK);
qixis_reset();
} else if (strcmp(argv[1], "altbank") == 0) {
- set_altbank();
+ set_lbmap(QIXIS_LBMAP_ALTBANK);
qixis_bank_reset();
+ } else if (strcmp(argv[1], "nand") == 0) {
+#ifdef QIXIS_LBMAP_NAND
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_NAND);
+ set_rcw_src(QIXIS_RCW_SRC_NAND);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf("Not implemented\n");
+#endif
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
"1min", "2min", "4min", "8min"};
@@ -244,6 +254,7 @@ U_BOOT_CMD(
"Reset the board using the FPGA sequencer",
"- hard reset to default bank\n"
"qixis_reset altbank - reset to alternate bank\n"
+ "qixis_reset nand - reset to nand\n"
"qixis watchdog - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
--
1.7.9.5
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[U-Boot] [PATCH v5 27/28] ls2085a: esdhc: Add esdhc support for ls2085a
From: Yangbo Lu
This patch adds esdhc support for ls2085a.
Signed-off-by: Yangbo Lu
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 +++
arch/arm/cpu/armv8/fsl-lsch3/fdt.c |7 +
arch/arm/include/asm/arch-fsl-lsch3/config.h |2 ++
drivers/mmc/fsl_esdhc.c | 36 --
include/configs/ls2085a_common.h |5 ++--
include/configs/ls2085aqds.h | 19 +-
include/configs/ls2085ardb.h | 11 +++-
include/fsl_esdhc.h |4 +++
8 files changed, 88 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 22b5fb2..e738c49 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -13,6 +13,9 @@
#include
#include
#include
+#ifdef CONFIG_FSL_ESDHC
+#include
+#endif
#include "cpu.h"
#include "mp.h"
#include "speed.h"
@@ -416,6 +419,13 @@ int print_cpuinfo(void)
}
#endif
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int error = 0;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index 42c5b58..d370023 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -7,6 +7,9 @@
#include
#include
#include
+#ifdef CONFIG_FSL_ESDHC
+#include
+#endif
#include "mp.h"
#ifdef CONFIG_MP
@@ -65,4 +68,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl,ns16550",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
+
+#if defined(CONFIG_FSL_ESDHC)
+ fdt_fixup_esdhc(blob, bd);
+#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 77c20ab..ca8d38c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -31,6 +31,7 @@
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x0030)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x0031)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x0037)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x0114)
#define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0124)
#define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR +
0x011C0500)
#define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR +
0x011C0600)
@@ -110,6 +111,7 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_ESDHC_LE
/* IFC */
#define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5e270d..7528b9d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -105,7 +105,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) ||
defined(CONFIG_LS102XA)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
+ defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -183,7 +184,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-
+#ifdef CONFIG_LS2085A
+ dma_addr_t addr;
+#endif
uint wml_value;
wml_value = data->blocksize/4;
@@ -194,8 +197,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+ addr = virt_to_phys((void *)(data->dest));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
+#else
esdhc_write32(®s->dsaddr, (u32)data->dest);
#endif
+#endif
} else {
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
flush_dcache_range((ulong)data->src,
@@ -212,8 +223,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+ addr = virt_t
[U-Boot] [PATCH v5 28/28] armv8/fsl-lsch3: Implement workaround for I2C issue
This erratum requires setting GLITCH_EN bit in debug register.
Signed-off-by: York Sun
CC: Heiko Schocher
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
Add comment to I2C workaround
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index ca00108..7cbf43c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -37,11 +37,45 @@ static void erratum_rcw_src(void)
#endif
}
+#define I2C_DEBUG_REG 0x6
+#define I2C_GLITCH_EN 0x8
+/*
+ * This erratum indicates setting glitch_en bit enables
+ * digital glitch filter for improved stability.
+ */
+static void erratum_i2c(void)
+{
+ u8 __iomem *ptr;
+#ifdef CONFIG_SYS_I2C
+#ifdef I2C1_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C2_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C3_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C4_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#endif
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
+ erratum_i2c();
}
#ifdef CONFIG_SPL_BUILD
--
1.7.9.5
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[U-Boot] [PATCH v5 26/28] armv8/ls2085ardb: Enable NAND SPL support
From: Scott Wood
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5:
Fix signed-off-by signature
Update LS2085ARDB README to include instructions to form NAND image
Changes in v4:
Update MAINTAINERS file
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig |1 +
board/freescale/ls2085ardb/MAINTAINERS |1 +
board/freescale/ls2085ardb/README | 19 +++
board/freescale/ls2085ardb/ddr.c |4
configs/ls2085ardb_nand_defconfig |4
include/configs/ls2085ardb.h | 40
6 files changed, 64 insertions(+), 5 deletions(-)
create mode 100644 configs/ls2085ardb_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f73541c..cf291c8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config TARGET_LS2085ARDB
bool "Support ls2085ardb"
select ARM64
select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
help
Support for Freescale LS2085ARDB platform.
The LS2085A Reference design board (RDB) is a high-performance
diff --git a/board/freescale/ls2085ardb/MAINTAINERS
b/board/freescale/ls2085ardb/MAINTAINERS
index 436039f..d5cce40 100644
--- a/board/freescale/ls2085ardb/MAINTAINERS
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/freescale/ls2085ardb/
F: board/freescale/ls2085a/ls2085ardb.c
F: include/configs/ls2085ardb.h
F: configs/ls2085ardb_defconfig
+F: configs/ls2085ardb_nand_defconfig
diff --git a/board/freescale/ls2085ardb/README
b/board/freescale/ls2085ardb/README
index cfd5185..5a5171c 100644
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2085ardb/README
@@ -107,3 +107,22 @@ Booting Options
---
a) NOR boot
b) NAND boot
+
+Generage NAND image
+---
+To form the NAND image, build u-boot with LS2085ARDB_NAND_defconfig.
+Append u-boot-with-spl.bin after RCW image. The RCW image should
+have these PBI commands
+
+1) CCSR 4-byte write to 0x00e00404, data=0x
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+3) Block Copy: SRC=0x0104, SRC_ADDR=0x00c0, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+
+These PBI commands set the bootloc registers to OCRAM address 0x1800a000
+and the SPL image is copied from the combined image into OCRAM.
+
+The SRC_ADDR should match the size of RCW image, i.e. it is the offset
+of u-boot-with-spl.bin in the NAND image. If putting RCW in a separated
+block is desired, the offset needs adjustment. Padding between the end
+of RCW and the start of u-boot image may be required.
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
index 6cd5e8b..8d71ae1 100644
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2085ardb/ddr.c
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
puts("Initializing DDRusing SPD\n");
dram_size = fsl_ddr_sdram();
+#endif
return dram_size;
}
diff --git a/configs/ls2085ardb_nand_defconfig
b/configs/ls2085ardb_nand_defconfig
new file mode 100644
index 000..39ba8c5
--- /dev/null
+++ b/configs/ls2085ardb_nand_defconfig
@@ -0,0 +1,4 @@
++S:CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
++S:CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085ARDB=y
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 0a5873b..e97f054 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK0x04
+#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_RST_CTL_RESET0x31
#define QIXIS_RST_CTL_RESET_EN 0x30
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RCW_SRC_NAND 0x119
#defineQIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
@@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void);
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONF
[U-Boot] [PATCH v5 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Bhupesh Sharma Signed-off-by: Scott Wood --- Changes in v5: Fix Kconfig help for inconsistent SoC name s/LS2080/LS2085/g Changes in v4: Fix board README for inconsistent SoC name Fix comments in board header file Changes in v3: None Changes in v2: None arch/arm/Kconfig | 11 + arch/arm/cpu/armv8/fsl-lsch3/README |4 +- board/freescale/ls2085ardb/Kconfig| 16 ++ board/freescale/ls2085ardb/MAINTAINERS|7 + board/freescale/ls2085ardb/Makefile |8 + board/freescale/ls2085ardb/README | 109 ++ board/freescale/ls2085ardb/ddr.c | 192 ++ board/freescale/ls2085ardb/ddr.h | 92 + board/freescale/ls2085ardb/ls2085ardb.c | 249 +++ board/freescale/ls2085ardb/ls2085ardb_qixis.h | 20 ++ configs/ls2085ardb_defconfig |3 + include/configs/ls2085ardb.h | 266 + 12 files changed, 975 insertions(+), 2 deletions(-) create mode 100644 board/freescale/ls2085ardb/Kconfig create mode 100644 board/freescale/ls2085ardb/MAINTAINERS create mode 100644 board/freescale/ls2085ardb/Makefile create mode 100644 board/freescale/ls2085ardb/README create mode 100644 board/freescale/ls2085ardb/ddr.c create mode 100644 board/freescale/ls2085ardb/ddr.h create mode 100644 board/freescale/ls2085ardb/ls2085ardb.c create mode 100644 board/freescale/ls2085ardb/ls2085ardb_qixis.h create mode 100644 configs/ls2085ardb_defconfig create mode 100644 include/configs/ls2085ardb.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f4a7851..6ba4b8d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -658,6 +658,16 @@ config TARGET_LS2085AQDS development platform that supports the QorIQ LS2085A Layerscape Architecture processor. +config TARGET_LS2085ARDB + bool "Support ls2085ardb" + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS2085ARDB platform. + The LS2085A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2085A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -804,6 +814,7 @@ source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls2085aqds/Kconfig" +source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 817ea1b..4f36e2a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -38,7 +38,7 @@ Flash Layout 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) (2) A typical layout of various images (including Linux and other firmware images) -is shown below considering a 128MB NOR flash device present on QDS +is shown below considering a 128MB NOR flash device present on QDS and RDB boards: - > 0x5_8800_ --- | .. Unused .. (7M) | | @@ -86,7 +86,7 @@ Flash Layout | RCW and PBI (1M)| | - > 0x5_8000_ --- - 128-MB NOR flash layout for QDS board + 128-MB NOR flash layout for QDS and RDB boards Environment Variables = diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2085ardb/Kconfig new file mode 100644 index 000..85a3dcd --- /dev/null +++ b/board/freescale/ls2085ardb/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS2085ARDB + +config SYS_BOARD + default "ls2085ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-lsch3" + +config SYS_CONFIG_NAME + default "ls2085ardb" + +endif diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS new file mode 100644 index 000..436039f --- /dev/null +++ b/board/freescale/ls2085ardb/MAINTAINERS @@ -0,0 +1,7 @@ +LS2085A BOARD +M: Prabhakar Kushwaha +S: Maintained +F: board/freescale/ls2085ardb/ +F: board/freescale/ls2085a/ls2085ardb.c +F: include/configs/ls2085ardb.h +F: configs/ls2085ardb_defconfig diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile new file mode 100644 index 000..0bfe21c --- /dev/null +++ b/board/freescale/ls20
[U-Boot] [PATCH v5 24/28] armv8/ls2085aqds: NAND boot support
From: Scott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5:
Update LS2085AQDS README to include instructions to form NAND image
Changes in v4:
Update MAINTAINERS file
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig |1 +
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 48
arch/arm/cpu/armv8/u-boot-spl.lds| 77 ++
arch/arm/include/asm/arch-fsl-lsch3/config.h |9 +++
arch/arm/lib/crt0_64.S |7 +++
board/freescale/ls2085aqds/MAINTAINERS |1 +
board/freescale/ls2085aqds/README| 19 +++
board/freescale/ls2085aqds/ddr.c |4 ++
common/spl/spl.c |2 +-
common/spl/spl_nand.c|2 +-
configs/ls2085aqds_nand_defconfig|4 ++
drivers/misc/fsl_ifc.c | 12
drivers/mtd/nand/fsl_ifc_spl.c |2 +-
include/configs/ls2085a_common.h | 29 ++
include/configs/ls2085aqds.h | 50 +++--
15 files changed, 259 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds
create mode 100644 configs/ls2085aqds_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6ba4b8d..f73541c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
bool "Support ls2085aqds"
select ARM64
select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
help
Support for Freescale LS2085AQDS platform
The LS2085A Development System (QDS) is a high-performance
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 17700ef..ca00108 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -6,8 +6,13 @@
#include
#include
+#include
+#include
#include
#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
static void erratum_a008751(void)
{
@@ -18,8 +23,51 @@ static void erratum_a008751(void)
#endif
}
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+ u32 val;
+
+ val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+ val &= ~DCFG_PORSR1_RCW_SRC;
+ val |= DCFG_PORSR1_RCW_SRC_NOR;
+ out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
+ erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+ board_early_init_f();
+ timer_init();
+ env_init();
+ gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+
+ serial_init();
+ console_init_f();
+ dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
new file mode 100644
index 000..4df339c
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2013
+ * David Feng
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * (C) Copyright 2010
+ * Texas Instruments,
+ * Aneesh V
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64",
"elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ .text : {
+ . = ALIGN(8);
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ .rodata : {
+ . = ALIGN(8);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } >.sram
+
+ .data : {
+ . = ALIGN(8);
+ *(.data*)
+ } >.sram
+
+ .u_boot_list : {
+ . = ALIGN(8);
+ KEEP(*(SORT(.u_boot_list*)));
+ } >.sram
+
+ .image_copy_end : {
+ . = ALIGN(8);
+ *(.__image_copy_end)
+ } >.sram
+
+ .end : {
+ . = ALIGN(8);
+ *(.__end)
+ } >.sram
+
+ .bss_start : {
+ . = ALIGN(8);
+ KEEP(*
[U-Boot] [PATCH v5 22/28] board/ls2085qds: Add support ethernet
From: Prabhakar Kushwaha
Add support of ethernet:
- eth.c: mapping lane to slot for (0x2A, 0x07)
- ls2085a.c: To enable/disable dpmac and get link type
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/freescale/ls2085aqds/Makefile |1 +
board/freescale/ls2085aqds/eth.c | 380 +
board/freescale/ls2085aqds/ls2085aqds.c | 13 -
board/freescale/ls2085aqds/ls2085aqds_qixis.h |4 +
drivers/net/ldpaa_eth/Makefile|1 +
drivers/net/ldpaa_eth/ls2085a.c | 83 ++
include/configs/ls2085aqds.h | 19 ++
7 files changed, 488 insertions(+), 13 deletions(-)
create mode 100644 board/freescale/ls2085aqds/eth.c
create mode 100644 drivers/net/ldpaa_eth/ls2085a.c
diff --git a/board/freescale/ls2085aqds/Makefile
b/board/freescale/ls2085aqds/Makefile
index f174f33..da69a7d 100644
--- a/board/freescale/ls2085aqds/Makefile
+++ b/board/freescale/ls2085aqds/Makefile
@@ -6,3 +6,4 @@
obj-y += ls2085aqds.o
obj-y += ddr.o
+obj-y += eth.o
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
new file mode 100644
index 000..5ba4770
--- /dev/null
+++ b/board/freescale/ls2085aqds/eth.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../common/qixis.h"
+
+#include "ls2085aqds_qixis.h"
+
+
+#ifdef CONFIG_FSL_MC_ENET
+ /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ * Bank 1 -> Lanes A, B, C, D, E, F, G, H
+ * Bank 2 -> Lanes A,B, C, D, E, F, G, H
+ */
+
+ /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+ * means that the mapping must be determined dynamically, or that the lane
+ * maps to something other than a board slot.
+ */
+
+static u8 lane_to_slot_fsm2[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+ SGMII_CARD_PORT1_PHY_ADDR,
+ SGMII_CARD_PORT2_PHY_ADDR,
+ SGMII_CARD_PORT3_PHY_ADDR,
+ SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE 0x
+#define EMI1_SLOT1 0
+#define EMI1_SLOT2 1
+#define EMI1_SLOT3 2
+#define EMI1_SLOT4 3
+#define EMI1_SLOT5 4
+#define EMI1_SLOT6 5
+#define EMI2 6
+#define SFP_TX 1
+
+static const char * const mdio_names[] = {
+ "LS2085A_QDS_MDIO0",
+ "LS2085A_QDS_MDIO1",
+ "LS2085A_QDS_MDIO2",
+ "LS2085A_QDS_MDIO3",
+ "LS2085A_QDS_MDIO4",
+ "LS2085A_QDS_MDIO5",
+ DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls2085a_qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+{
+ u8 brdcfg9;
+
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
+ brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls2085a_qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval <= 5) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+int devad, int regnum)
+{
+ struct ls2085a_qds_mdio *priv = bus->priv;
+
+ ls2085a_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls2085a_qds_mdio *priv = bus->priv;
+
+ ls2085a_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls2085a_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls2085a_qds_mdio_init(char *realbusname, u8 muxv
[U-Boot] [PATCH v5 23/28] driver/ifc: Add 64KB page support
From: Jaiprakash Singh
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv7/ls102xa/clock.c|4 +-
arch/arm/cpu/armv8/fsl-lsch3/speed.c |4 +-
arch/powerpc/cpu/mpc85xx/cpu_init_early.c |8 +--
arch/powerpc/cpu/mpc85xx/speed.c |4 +-
board/freescale/bsc9132qds/bsc9132qds.c |4 +-
board/freescale/c29xpcie/c29xpcie.c |4 +-
board/freescale/p1010rdb/p1010rdb.c |5 +-
board/freescale/p1010rdb/spl.c|4 +-
drivers/mtd/nand/fsl_ifc_nand.c | 53 ++
drivers/mtd/nand/fsl_ifc_spl.c| 23 ++--
include/fsl_ifc.h | 84 +++--
11 files changed, 126 insertions(+), 71 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
index 8f80c61..7a337e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -20,7 +20,7 @@ void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
@@ -74,7 +74,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_be32(&ifc_regs->ifc_ccr);
+ ccr = in_be32(&ifc_regs.gregs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 2b140cd..cac4f92 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -26,7 +26,7 @@ void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_le32(&ifc_regs->ifc_ccr);
+ ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 5ca9bf5..235a635 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_A003399_NOR_WORKAROUND
void setup_ifc(void)
{
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 _mas0, _mas1, _mas2, _mas3, _mas7;
phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
@@ -70,9 +70,9 @@ void setup_ifc(void)
#endif
/* Change flash's physical address */
- ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
- ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
- ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+ ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+ ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+ ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
return ;
}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e24b857..321ade2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -28,7 +28,7 @@ void get_sys_info(sys_info_t *sys_info)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
@@ -597,7 +597,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_FSL_IFC)
- ccr = ifc_in32(&ifc_regs->ifc_ccr);
+
[U-Boot] [PATCH v5 21/28] drivers/fsl-mc: Autoload AOIP image from NOR flash
From: "J. German Rivera"
Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time.
Signed-off-by: J. German Rivera
[York Sun: This is a debug commit. Will drop once AIOP is loaded by Linux]
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/net/fsl-mc/mc.c | 24
include/configs/ls2085a_common.h |2 ++
include/configs/ls2085aqds.h |3 +++
include/configs/ls2085ardb.h |3 +++
4 files changed, 32 insertions(+)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index c5c44bc..e6f6d55 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -298,6 +298,24 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
return 0;
}
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
+{
+ void *aiop_img;
+
+ /*
+* Load the MC AIOP image in the MC private DRAM block:
+*/
+
+ aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
+ mc_copy_image("MC AIOP image",
+ (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+ mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+
+ return 0;
+}
+#endif
+
/**
* Return the MC boot timeout value in milliseconds
*/
@@ -454,6 +472,12 @@ int mc_init(void)
if (error != 0)
goto out;
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+ error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
+ if (error != 0)
+ goto out;
+#endif
+
debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
dump_mc_ccsr_regs(mc_ccsr_regs);
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 29a86f6..44c6845 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -166,6 +166,8 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET0x00F0
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH0x2
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET0x00F2
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x20
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x1f80
/* Carve out a DDR region which will not be used by u-boot/Linux */
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index b1d2d48..a807640 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -218,6 +218,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_LS_MC_DPC_IN_NOR
#define CONFIG_SYS_LS_MC_DPC_ADDR 0x58080ULL
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x58090ULL
+
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 9c6f3ed..0a5873b 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -201,6 +201,9 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_LS_MC_DPC_IN_NOR
#define CONFIG_SYS_LS_MC_DPC_ADDR 0x58080ULL
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x58090ULL
+
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
--
1.7.9.5
___
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[U-Boot] [PATCH v5 11/28] driver/ldpaa_eth: Update ldpaa ethernet driver
From: Prabhakar Kushwaha
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.
Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.
Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.
Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.
Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: pankaj chauhan
Signed-off-by: Roy Pledge
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/net/ldpaa_eth/ldpaa_eth.c | 62 +++--
1 file changed, 38 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index b79942f..9015e4f 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -15,6 +15,7 @@
#include "ldpaa_eth.h"
+#undef CONFIG_PHYLIB
static int init_phy(struct eth_device *dev)
{
/*TODO for external PHY */
@@ -33,8 +34,6 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
struct qbman_release_desc releasedesc;
struct qbman_swp *swp = dflt_dpio->sw_portal;
- invalidate_dcache_all();
-
fd_addr = ldpaa_fd_get_addr(fd);
fd_offset = ldpaa_fd_get_offset(fd);
fd_length = ldpaa_fd_get_len(fd);
@@ -62,6 +61,7 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
NetReceive((uint8_t *)(fd_addr) + fd_offset, fd_length);
error:
+ flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE);
qbman_release_desc_clear(&releasedesc);
qbman_release_desc_set_bpid(&releasedesc, dflt_dpbp->dpbp_attr.bpid);
do {
@@ -76,22 +76,29 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
- int i = 5, err = 0, status;
+ int i = 5, err = 0, status, loop = 20;
static struct qbman_pull_desc pulldesc;
struct qbman_swp *swp = dflt_dpio->sw_portal;
- qbman_pull_desc_clear(&pulldesc);
- qbman_pull_desc_set_numframes(&pulldesc, 1);
- qbman_pull_desc_set_fq(&pulldesc, priv->rx_dflt_fqid);
-
while (--i) {
+ qbman_pull_desc_clear(&pulldesc);
+ qbman_pull_desc_set_numframes(&pulldesc, 1);
+ qbman_pull_desc_set_fq(&pulldesc, priv->rx_dflt_fqid);
+
err = qbman_swp_pull(swp, &pulldesc);
if (err < 0) {
printf("Dequeue frames error:0x%08x\n", err);
continue;
}
- dq = qbman_swp_dqrr_next(swp);
+ do {
+ loop--;
+ dq = qbman_swp_dqrr_next(swp);
+
+ if (!loop)
+ break;
+ } while (!dq);
+
if (dq) {
/* Check for valid frame. If not sent a consume
* confirmation to QBMAN otherwise give it to NADK
@@ -128,7 +135,6 @@ static void ldpaa_eth_tx_conf(struct ldpaa_eth_priv *priv,
struct qbman_release_desc releasedesc;
struct qbman_swp *swp = dflt_dpio->sw_portal;
- invalidate_dcache_all();
fd_addr = ldpaa_fd_get_addr(fd);
@@ -159,22 +165,29 @@ static int ldpaa_eth_pull_dequeue_tx_conf(struct
ldpaa_eth_priv *priv)
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
int err = 0;
- int i = 5, status;
+ int i = 5, status, loop = 20;
static struct qbman_pull_desc pulldesc;
struct qbman_swp *swp = dflt_dpio->sw_portal;
- qbman_pull_desc_clear(&pulldesc);
- qbman_pull_desc_set_numframes(&pulldesc, 1);
- qbman_pull_desc_set_fq(&pulldesc, priv->tx_conf_fqid);
-
while (--i) {
+ qbman_pull_desc_clear(&pulldesc);
+ qbman_pull_desc_set_numframes(&pulldesc, 1);
+ qbman_pull_desc_set_fq(&pulldesc, priv->tx_conf_fqid);
+
err = qbman_swp_pull(swp, &pulldesc);
if (err < 0) {
printf("Dequeue TX conf frames error:0x%08x\n", err);
continue;
}
- dq = qbman_swp_dqrr_next(swp);
+ do {
+ loop--;
+ dq = qbman_swp_dqrr_next(swp);
+
+
[U-Boot] [PATCH v5 15/28] net/memac_phy: reuse driver for little endian SoCs
From: Shaohui Xie
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.
Signed-off-by: Shaohui Xie
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-fsl-lsch3/config.h |1 +
drivers/net/Makefile |1 +
drivers/net/fm/eth.c |2 +-
drivers/net/fm/memac.c|2 +-
drivers/net/fm/memac_phy.c| 62 ++---
drivers/net/vsc9953.c |2 +-
{arch/powerpc/include/asm => include}/fsl_memac.h |0
7 files changed, 46 insertions(+), 24 deletions(-)
rename {arch/powerpc/include/asm => include}/fsl_memac.h (100%)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 98db1ef..684c70f 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -109,6 +109,7 @@
/* IFC */
#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5497934..d871093 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -66,4 +66,5 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o
xilinx_ll_temac_mdio.o \
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
+obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 1d1089d..a7a5c69 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -15,7 +15,7 @@
#include
#include
#include
-#include
+#include
#include "fm.h"
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 60e898c..81a64bf 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,7 @@
#include
#include
#include
-#include
+#include
#include "fm.h"
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index a155d89..4ab78e6 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -10,9 +10,28 @@
#include
#include
#include
-#include
+#include
#include
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+#define memac_out_32(a, v) out_le32(a, v)
+#define memac_clrbits_32(a, v) clrbits_le32(a, v)
+#define memac_setbits_32(a, v) setbits_le32(a, v)
+#else
+#define memac_out_32(a, v) out_be32(a, v)
+#define memac_clrbits_32(a, v) clrbits_be32(a, v)
+#define memac_setbits_32(a, v) setbits_be32(a, v)
+#endif
+
+static u32 memac_in_32(u32 *reg)
+{
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+ return in_le32(reg);
+#else
+ return in_be32(reg);
+#endif
+}
+
/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
@@ -28,31 +47,31 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr,
int dev_addr,
if (dev_addr == MDIO_DEVAD_NONE) {
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
- clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
+ memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
} else
- setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
+ memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
/* Wait till the bus is free */
- while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
- out_be32(®s->mdio_ctl, mdio_ctl);
+ memac_out_32(®s->mdio_ctl, mdio_ctl);
/* Set the register address */
if (c45)
- out_be32(®s->mdio_addr, regnum & 0x);
+ memac_out_32(®s->mdio_addr, regnum & 0x);
/* Wait till the bus is free */
- while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Write the value to the register */
- out_be32(®s->mdio_data, MDIO_DATA(value));
+ memac_out_32(®s->mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write is complete */
- while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
+ while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
;
[U-Boot] [PATCH v5 18/28] driver/ldpaa: Add support of WRIOP static data structure
From: Prabhakar Kushwaha
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.
Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c |7 +-
arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 24
drivers/net/ldpaa_eth/Makefile|2 +-
drivers/net/ldpaa_eth/ldpaa_eth.h |4 -
drivers/net/ldpaa_eth/ldpaa_wriop.c | 146 +
include/fsl-mc/ldpaa_wriop.h | 70 ++
7 files changed, 250 insertions(+), 6 deletions(-)
create mode 100644 drivers/net/ldpaa_eth/ldpaa_wriop.c
create mode 100644 include/fsl-mc/ldpaa_wriop.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
index 78b9210..02ca126 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_SYS_FSL_SRDS_1
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
@@ -86,8 +87,12 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32
sd_prctl_shift,
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
- else
+ else {
serdes_prtcl_map[lane_prtcl] = 1;
+#ifdef CONFIG_FSL_MC_ENET
+ wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+#endif
+ }
}
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 684c70f..403b2ef 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -38,6 +38,9 @@
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B8)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA)
/* SP (Cortex-A5) related */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index 91cf68b..d6bee60 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -47,6 +47,30 @@ struct ccsr_gur {
u32 devdisr5; /* Device disable control 5 */
u32 devdisr6; /* Device disable control 6 */
u32 devdisr7; /* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x0001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x0002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x0004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x0008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x0010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x0020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x0040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x0080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x0100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x0200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x0400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x0800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x1000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x2000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x4000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x8000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x0001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x0002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x0004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x0008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x0010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x0020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x0040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x0080
u8 res_08c[0x90-0x8c];
u32 coredisru; /* uppper portion for support of 64 cores */
u32 coredisrl; /* lower portion for support of 64 cores */
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 3b1a60b..d32d67e 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Layerscape LDPAA driver
+obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
diff --git a/drivers/net/ldpaa_eth/ldpaa_e
[U-Boot] [PATCH v5 19/28] armv8/ls2085aqds: Add support of LS2085AQDS platform
The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Bhupesh Sharma --- Changes in v5: Fix board README for inconsistent SoC name Fix comment in board header file s/LS2080/LS2085/g Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/Kconfig | 11 + arch/arm/cpu/armv8/fsl-lsch3/README | 70 +- board/freescale/ls2085aqds/Kconfig| 16 ++ board/freescale/ls2085aqds/MAINTAINERS|7 + board/freescale/ls2085aqds/Makefile |8 + board/freescale/ls2085aqds/README | 129 +++ board/freescale/ls2085aqds/ddr.c | 192 + board/freescale/ls2085aqds/ddr.h | 92 board/freescale/ls2085aqds/ls2085aqds.c | 287 + board/freescale/ls2085aqds/ls2085aqds_qixis.h | 26 +++ configs/ls2085aqds_defconfig |3 + include/configs/ls2085a_common.h | 38 +++- include/configs/ls2085aqds.h | 283 include/fsl_ddr_sdram.h |1 + 14 files changed, 1148 insertions(+), 15 deletions(-) create mode 100644 board/freescale/ls2085aqds/Kconfig create mode 100644 board/freescale/ls2085aqds/MAINTAINERS create mode 100644 board/freescale/ls2085aqds/Makefile create mode 100644 board/freescale/ls2085aqds/README create mode 100644 board/freescale/ls2085aqds/ddr.c create mode 100644 board/freescale/ls2085aqds/ddr.h create mode 100644 board/freescale/ls2085aqds/ls2085aqds.c create mode 100644 board/freescale/ls2085aqds/ls2085aqds_qixis.h create mode 100644 configs/ls2085aqds_defconfig create mode 100644 include/configs/ls2085aqds.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b9ebee1..f4a7851 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -648,6 +648,16 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY +config TARGET_LS2085AQDS + bool "Support ls2085aqds" + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS2085AQDS platform + The LS2085A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS2085A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -793,6 +803,7 @@ source "board/denx/m53evk/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" +source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index f781620..817ea1b 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -11,28 +11,82 @@ for example LS2085A. Flash Layout -A typical layout of various images (including Linux and other firmware images) -is shown below considering a 32MB NOR flash device: + +(1) A typical layout of various images (including Linux and other firmware images) + is shown below considering a 32MB NOR flash device present on most + pre-silicon platforms (simulator and emulator): - - | linux | + | FIT Image | + | (linux + DTB + RFS) | - > 0x0120_ - | Debug Server| + | Debug Server FW | - > 0x00C0_ - | AIOP SW | + | AIOP FW | - > 0x0070_ | MC FW | - > 0x006C_ - | MC Data Path Layout | + | MC DPL Blob | - > 0x0020_ - | BootLoader | + | BootLoader + Env| - > 0x_1000 | PBI | - > 0x_0080 | RCW | - > 0x_ - 32-MB NOR flash layout + 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) + +(2) A typical layout of various images (including Linux and other firmware images) +is shown below considering a 128MB NOR flash device present on QDS +boards: + - > 0x5_8800_ --- + | .. Unused .. (7M) | | + - > 0x5_8790_ | + | FIT Image (linux + DTB + RFS)
[U-Boot] [PATCH v5 13/28] net/phy/cortina: Fix compilation warning
From: pankaj chauhan
Fix comilation warning which is emitted when
firmware address is more than 32 bit.
Signed-off-by: pankaj chauhan
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/net/phy/cortina.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 254f056..3a2b3bb 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -186,8 +186,8 @@ void cs4340_upload_firmware(struct phy_device *phydev)
while (*addr != 0x0a) {
line_temp[i++] = *addr++;
if (0x50 < i) {
- printf("Not found Cortina PHY ucode at 0x%x\n",
- CONFIG_CORTINA_FW_ADDR);
+ printf("Not found Cortina PHY ucode at 0x%p\n",
+ (char *)CONFIG_CORTINA_FW_ADDR);
return;
}
}
--
1.7.9.5
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[U-Boot] [PATCH v5 17/28] armv8/fsl-lsch3: Enable system error aborts
From: Scott Wood
This lets us see the problems (close to) when they happen,
rather than Linux hanging when it enables them prior to having a
working console.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 07064a3..22b5fb2 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -263,6 +263,10 @@ int arch_cpu_init(void)
__asm_invalidate_tlb_all();
early_mmu_setup();
set_sctlr(get_sctlr() | CR_C);
+
+ /* Enable system error aborts */
+ asm volatile("msr daifclr, #4" : : : "memory");
+
return 0;
}
--
1.7.9.5
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[U-Boot] [PATCH v5 16/28] armv8/fsl-ch3: Add support to print RCW configuration
From: Bhupesh Sharma
This patch adds support to print out the Reset Configuration Word
information.
Signed-off-by: Bhupesh Sharma
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index caa48f2..07064a3 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -371,6 +371,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
@@ -394,6 +395,19 @@ int print_cpuinfo(void)
printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
puts("\n");
+ /* Display the RCW, so that no one gets confused as to what RCW
+* we're actually using for this boot.
+*/
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_le32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %02x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
return 0;
}
#endif
--
1.7.9.5
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[U-Boot] [PATCH v5 14/28] drivers/fsl-mc: Changed MC firmware loading for new boot architecture
From: "J. German Rivera"
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
flib functions.
Signed-off-by: J. German Rivera
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/README |8 +
drivers/net/fsl-mc/mc.c | 494 ++-
include/configs/ls2085a_common.h|6 +-
include/configs/ls2085a_emu.h | 13 +-
include/configs/ls2085a_simu.h |5 +
5 files changed, 395 insertions(+), 131 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
index 99fc39a..f781620 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -33,3 +33,11 @@ is shown below considering a 32MB NOR flash device:
- > 0x_
32-MB NOR flash layout
+
+Environment Variables
+=
+mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+ the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+mcmemsize: MC DRAM block size. If this variable is not defined, the value
+ CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 2a2b0af..c5c44bc 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -3,7 +3,6 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
-
#include
#include
#include
@@ -15,14 +14,64 @@
#include
#include
+#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK(~(MC_RAM_BASE_ADDR_ALIGNMENT -
1))
+#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
+
+#define MC_MEM_SIZE_ENV_VAR"mcmemsize"
+#define MC_BOOT_TIMEOUT_ENV_VAR"mcboottimeout"
+
DECLARE_GLOBAL_DATA_PTR;
static int mc_boot_status;
struct fsl_mc_io *dflt_mc_io = NULL;
uint16_t dflt_dprc_handle = 0;
struct fsl_dpbp_obj *dflt_dpbp = NULL;
struct fsl_dpio_obj *dflt_dpio = NULL;
-uint16_t dflt_dpio_handle = NULL;
+uint16_t dflt_dpio_handle = 0;
+
+#ifdef DEBUG
+void dump_ram_words(const char *title, void *addr)
+{
+ int i;
+ uint32_t *words = addr;
+
+ printf("Dumping beginning of %s (%p):\n", title, addr);
+ for (i = 0; i < 16; i++)
+ printf("%#x ", words[i]);
+
+ printf("\n");
+}
+void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
+{
+ printf("MC CCSR registers:\n"
+ "reg_gcr1 %#x\n"
+ "reg_gsr %#x\n"
+ "reg_sicbalr %#x\n"
+ "reg_sicbahr %#x\n"
+ "reg_sicapr %#x\n"
+ "reg_mcfbalr %#x\n"
+ "reg_mcfbahr %#x\n"
+ "reg_mcfapr %#x\n"
+ "reg_psr %#x\n",
+ mc_ccsr_regs->reg_gcr1,
+ mc_ccsr_regs->reg_gsr,
+ mc_ccsr_regs->reg_sicbalr,
+ mc_ccsr_regs->reg_sicbahr,
+ mc_ccsr_regs->reg_sicapr,
+ mc_ccsr_regs->reg_mcfbalr,
+ mc_ccsr_regs->reg_mcfbahr,
+ mc_ccsr_regs->reg_mcfapr,
+ mc_ccsr_regs->reg_psr);
+}
+#else
+
+#define dump_ram_words(title, addr)
+#define dump_mc_ccsr_regs(mc_ccsr_regs)
+
+#endif /* DEBUG */
+
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
/**
* Copying MC firmware or DPL image to DDR
*/
@@ -31,6 +80,7 @@ static int mc_copy_image(const char *title,
{
debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+ flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
return 0;
}
@@ -92,22 +142,254 @@ int parse_mc_firmware_fit_image(const void
**raw_image_addr,
return 0;
}
+#endif
+
+/*
+ * Calculates the values to be used to specify the address range
+ * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
+ * It returns the highest 512MB-aligned address within the given
+ * address range, in '*aligned_base_addr', and the number of 256 MiB
+ * blocks in it, in 'num_256mb_blocks'.
+ */
+static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
+ size_t mc_ram_size,
+ u64 *aligned_base_addr,
+ u8 *num_256mb_blocks)
+{
+ u64 addr;
+ u16 num_blocks;
+
+ if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
+ printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
+ mc_ram_size);
+ return -EINVAL;
+ }
+
+ num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
+ if (n
[U-Boot] [PATCH v5 09/28] armv8/ls2085a: Add workaround for USB erratum A-008751
From: Scott Wood
Without this "USB may not work" according to the erratum text, though I
did not notice a problem without it.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 11 +++
arch/arm/include/asm/arch-fsl-lsch3/config.h |5 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 242a865..17700ef 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -7,8 +7,19 @@
#include
#include
#include
+#include
+
+static void erratum_a008751(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
+#endif
+}
void fsl_lsch3_early_init_f(void)
{
+ erratum_a008751();
init_early_memctl_regs(); /* tighten IFC timing */
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 9121452..a81e3ed 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -124,6 +124,10 @@
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+/* Supplemental Configuration */
+#define SCFG_BASE 0x01fc
+#define SCFG_USB3PRM1CR0x000
+
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
@@ -138,6 +142,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
--
1.7.9.5
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[U-Boot] [PATCH v5 12/28] armv8: Add SerDes framework for Layerscape Architecture
From: Minghuan Lian
Add support of SerDes framework for Layerscape Architecture.
- Add support of 2 SerDes block
- Add SerDes protocol parsing and detection
- Create table of SerDes protocol supported by LS2085A
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Minghuan Lian
---
Changes in v5:
s/LayerScape/Layerscape/g
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/Makefile |1 +
arch/arm/cpu/armv8/fsl-lsch3/cpu.c|4 +
arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 110 +++
arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117 +
arch/arm/include/asm/arch-fsl-lsch3/config.h |4 +
arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h |5 +
include/configs/ls2085a_common.h |5 +
8 files changed, 313 insertions(+)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index 6542590..9f7815b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -8,5 +8,6 @@ obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
obj-y += speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 595dbd1..caa48f2 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include "cpu.h"
#include "mp.h"
#include "speed.h"
@@ -415,6 +416,9 @@ int arch_early_init_r(void)
if (rv)
printf("Did not wake secondary cores\n");
+#ifdef CONFIG_SYS_HAS_SERDES
+ fsl_serdes_init();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
new file mode 100644
index 000..78b9210
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ ret |= serdes1_prtcl_map[device];
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ ret |= serdes2_prtcl_map[device];
+#endif
+
+ return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg = in_le32(&gur->rcwsr[28]);
+ int i;
+
+ switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ case FSL_SRDS_1:
+ cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+ break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+ case FSL_SRDS_2:
+ cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+ break;
+#endif
+ default:
+ printf("invalid SerDes%d\n", sd);
+ break;
+ }
+ /* Is serdes enabled at all? */
+ if (cfg == 0)
+ return -ENODEV;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_get_prtcl(sd, cfg, i) == device)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+ u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg;
+ int lane;
+
+ memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+ cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+ cfg >>= sd_prctl_shift;
+ printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+ if (!is_serdes_prtcl_valid(sd, cfg))
+ printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+ if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+ debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+ else
+ serdes_prtcl_map[lane_prtcl] = 1;
+ }
+}
+
+void fsl_serdes_init(void)
+{
[U-Boot] [PATCH v5 10/28] armv8/fsl-lsch3: Use correct compatible for serial clock fixup
From: Scott Wood The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood Signed-off-by: York Sun --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/armv8/fsl-lsch3/fdt.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index 7eb9b6a..42c5b58 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -62,7 +62,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_SYS_NS16550 - do_fixup_by_compat_u32(blob, "ns16550", + do_fixup_by_compat_u32(blob, "fsl,ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif } -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 06/28] armv8/fsl-lsch3: Set nodes in DVM domain
From: Scott Wood This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood Signed-off-by: York Sun --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |9 + arch/arm/include/asm/arch-fsl-lsch3/config.h |6 ++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 53bdb44..018c617 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -15,6 +15,15 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* Add fully-coherent masters to DVM domain */ + ldr x1, =CCI_MN_BASE + ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] + str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] +1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] + mvn x0, x3 + tst x0, x3 /* Wait for domain addition to complete */ + b.ne1b + /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE ldr w0, [x1, #0x10] diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 518e59c..9121452 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -118,6 +118,12 @@ #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x14ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x16ULL +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE0x0400 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 08/28] fsl-lsch3: Introduce place for common early SoC init
From: Scott Wood
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/Makefile |1 +
arch/arm/cpu/armv8/fsl-lsch3/soc.c| 14 ++
arch/arm/include/asm/arch-fsl-lsch3/soc.h |8
board/freescale/ls2085a/ls2085a.c |4 ++--
4 files changed, 25 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index f920eeb..6542590 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -6,6 +6,7 @@
obj-y += cpu.o
obj-y += lowlevel.o
+obj-y += soc.o
obj-y += speed.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
new file mode 100644
index 000..242a865
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+void fsl_lsch3_early_init_f(void)
+{
+ init_early_memctl_regs(); /* tighten IFC timing */
+}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
new file mode 100644
index 000..16b723d
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+void fsl_lsch3_early_init_f(void);
+
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index 19f5a7b..dd0acf2 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -31,8 +32,7 @@ int board_init(void)
int board_early_init_f(void)
{
- init_early_memctl_regs(); /* tighten IFC timing */
-
+ fsl_lsch3_early_init_f();
return 0;
}
--
1.7.9.5
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[U-Boot] [PATCH v5 03/28] armv8/fsl-lsch3: Fix platform clock calculation
Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/speed.c |7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 72cd999..2b140cd 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -86,6 +86,8 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
+ /* Platform clock is half of platform PLL */
+ sys_info->freq_systembus /= 2;
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -102,10 +104,7 @@ void get_sys_info(struct sys_info *sys_info)
offsetof(struct ccsr_clk_cluster_group,
pllngsr[i%3].gsr));
ratio[i] = (in_le32(offset) >> 1) & 0x3f;
- if (ratio[i] > 4)
- freq_c_pll[i] = sysclk * ratio[i];
- else
- freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+ freq_c_pll[i] = sysclk * ratio[i];
}
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
--
1.7.9.5
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[U-Boot] [PATCH v5 02/28] armv8/ls2085a: Update common header file
From: Prabhakar Kushwaha ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable "loadb" command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Scott Wood Signed-off-by: Bhupesh Sharma Signed-off-by: Minghuan Lian --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: Rebase after adding macros CONFIG_SYS_I2C_MXC_I2C3 in another patch set arch/arm/include/asm/arch-fsl-lsch3/config.h | 11 ++ include/configs/ls2085a_common.h | 142 ++ include/configs/ls2085a_emu.h| 62 +++ include/configs/ls2085a_simu.h | 117 + 4 files changed, 222 insertions(+), 110 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 2d461d9..518e59c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -108,6 +108,16 @@ /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x270) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x10ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x12ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x14ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x16ULL + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -119,6 +129,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #endif diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 1f1eddb..5721b18 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -23,7 +23,7 @@ #define CONFIG_ARCH_MISC_INIT /* Link Definitions */ -#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SYS_TEXT_BASE 0x3010 #ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH @@ -47,8 +47,6 @@ #define CONFIG_SYS_FSL_DDR3/* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ @@ -72,7 +70,6 @@ #define CONFIG_SYS_DP_DDR_BASE_PHY 0 #define CONFIG_DP_DDR_CTRL 2 #define CONFIG_DP_DDR_NUM_CTRLS1 -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 1200/* 12MHz */ @@ -86,8 +83,6 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C3/* enable I2C bus 3 */ #define CONFIG_SYS_I2C_MXC_I2C4/* enable I2C bus 4 */ -#define CONFIG_SYS_MXC_I2C1_SPEED 4000 -#define CONFIG_SYS_MXC_I2C2_SPEED 4000 /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -101,8 +96,7 @@ /* IFC */ #define CONFIG_FSL_IFC -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + /* * During booting, CS0 needs to be at the region of 0x3000, i.e. the IFC * address 0. But this region is limited to 256MB. To accommodate bigger NOR @@ -116,125 +110,55 @@ #define CONFIG_SYS_FLASH_BASE_PHYS 0x8000 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16
[U-Boot] [PATCH v5 05/28] armv8/ls2085a: Add support for reset request
From: pankaj chauhan
Add support for reset_cpu() by asserting RESET_REQ_B.
Signed-off-by: pankaj chauhan
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 +++
board/freescale/ls2085a/ls2085a.c |7 ---
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index e985181..0e5aa5c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -419,3 +419,14 @@ int timer_init(void)
return 0;
}
+
+void reset_cpu(ulong addr)
+{
+ u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+ u32 val;
+
+ /* Raise RESET_REQ_B */
+ val = in_le32(rstcr);
+ val |= 0x02;
+ out_le32(rstcr, val);
+}
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index bd016e9..19f5a7b 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,13 +55,6 @@ int dram_init(void)
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(ulong addr)
-{
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
--
1.7.9.5
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[U-Boot] [PATCH v5 07/28] armv8/fsl-lsch3: Update early MMU table
During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.
Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 56 +---
common/board_r.c |6
2 files changed, 45 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 0e5aa5c..595dbd1 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -25,8 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Level 0 IA[39], table address @0
- * Level 1 IA[31:30], table address @01000, 0x2000
- * Level 2 IA[29:21], table address @0x3000
+ * Level 1 IA[31:30], table address @0x1000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000, 0x4000
+ * Address above 0x5000 is free for other purpose.
*/
#define SECTION_SHIFT_L0 39UL
@@ -61,12 +62,12 @@ static inline void early_mmu_setup(void)
{
int el;
u64 i;
- u64 section_l1t0, section_l1t1, section_l2;
+ u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1;
u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
- u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
-
+ u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+ u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
level0_table[0] =
(u64)level1_table_0 | PMD_TYPE_TABLE;
@@ -80,21 +81,25 @@ static inline void early_mmu_setup(void)
*/
section_l1t0 = 0;
section_l1t1 = BLOCK_SIZE_L0;
- section_l2 = 0;
+ section_l2t0 = 0;
+ section_l2t1 = CONFIG_SYS_FLASH_BASE;
for (i = 0; i < 512; i++) {
set_pgtable_section(level1_table_0, i, section_l1t0,
MT_DEVICE_NGNRNE);
set_pgtable_section(level1_table_1, i, section_l1t1,
MT_NORMAL);
- set_pgtable_section(level2_table, i, section_l2,
+ set_pgtable_section(level2_table_0, i, section_l2t0,
+ MT_DEVICE_NGNRNE);
+ set_pgtable_section(level2_table_1, i, section_l2t1,
MT_DEVICE_NGNRNE);
section_l1t0 += BLOCK_SIZE_L1;
section_l1t1 += BLOCK_SIZE_L1;
- section_l2 += BLOCK_SIZE_L2;
+ section_l2t0 += BLOCK_SIZE_L2;
+ section_l2t1 += BLOCK_SIZE_L2;
}
level1_table_0[0] =
- (u64)level2_table | PMD_TYPE_TABLE;
+ (u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[1] =
0x4000 | PMD_SECT_AF | PMD_TYPE_SECT |
PMD_ATTRINDX(MT_DEVICE_NGNRNE);
@@ -105,17 +110,34 @@ static inline void early_mmu_setup(void)
0xc000 | PMD_SECT_AF | PMD_TYPE_SECT |
PMD_ATTRINDX(MT_NORMAL);
- /* Rewrite table to enable cache */
- set_pgtable_section(level2_table,
+ /* Rewerite table to enable cache for OCRAM */
+ set_pgtable_section(level2_table_0,
CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
CONFIG_SYS_FSL_OCRAM_BASE,
MT_NORMAL);
- for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
-i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
->> SECTION_SHIFT_L2; i++) {
- section_l2 = i << SECTION_SHIFT_L2;
- set_pgtable_section(level2_table, i,
- section_l2, MT_NORMAL);
+
+#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY)
+ /* Rewrite table to enable cache for two entries (4MB) */
+ section_l2t1 = CONFIG_SYS_IFC_BASE;
+ set_pgtable_section(level2_table_0,
+ section_l2t1 >> SECTION_SHIFT_L2,
+ section_l2t1,
+ MT_NORMAL);
+ section_l2t1 += BLOCK_SIZE_L2;
+ set_pgtable_section(level2_table_0,
+ section_l2t1 >> SECTION_SHIFT_L2,
+ section_l2t1,
+ MT_NORMAL);
+#endif
+
+
[U-Boot] [PATCH v5 0/28] Adding LS2085AQDS and RDB
This set adds necessary support in common ls2085a support and board support for QDS and RDB. Changes in v5: Re-generate patches using patman default flags s/LayerScape/Layerscape/g Fix board README for inconsistent SoC name Fix comment in board header file s/LS2080/LS2085/g Fix Kconfig help for inconsistent SoC name Update LS2085AQDS README to include instructions to form NAND image Update LS2085ARDB README to include instructions to form NAND image Changes in v4: Remove temporary variable cntfrq. Fix board README for inconsistent SoC name Fix comments in board header file Update MAINTAINERS file Update MAINTAINERS file Changes in v3: Move secondary core fix to mp.c. Replace hard-coded value with COUNTER_FREQUENCY. Changes in v2: Rebase after adding macros CONFIG_SYS_I2C_MXC_I2C3 in another patch set Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined. Add comment to I2C workaround Bhupesh Sharma (1): armv8/fsl-ch3: Add support to print RCW configuration J. German Rivera (2): drivers/fsl-mc: Changed MC firmware loading for new boot architecture drivers/fsl-mc: Autoload AOIP image from NOR flash Jaiprakash Singh (1): driver/ifc: Add 64KB page support Minghuan Lian (1): armv8: Add SerDes framework for Layerscape Architecture Prabhakar Kushwaha (4): armv8/ls2085a: Update common header file driver/ldpaa_eth: Update ldpaa ethernet driver driver/ldpaa: Add support of WRIOP static data structure board/ls2085qds: Add support ethernet Scott Wood (8): armv8/fsl-lsch3: Set nodes in DVM domain fsl-lsch3: Introduce place for common early SoC init armv8/ls2085a: Add workaround for USB erratum A-008751 armv8/fsl-lsch3: Use correct compatible for serial clock fixup armv8/fsl-lsch3: Enable system error aborts armv8/ls2085aqds: NAND boot support freescale/qixis: Add support for booting from NAND armv8/ls2085ardb: Enable NAND SPL support Shaohui Xie (1): net/memac_phy: reuse driver for little endian SoCs Yangbo Lu (1): ls2085a: esdhc: Add esdhc support for ls2085a York Sun (7): armv8/fsl-lsch3: Implement workaround for erratum A008585 armv8/fsl-lsch3: Fix platform clock calculation armv8/ls2085a: Fix generic timer clock source armv8/fsl-lsch3: Update early MMU table armv8/ls2085aqds: Add support of LS2085AQDS platform armv8/ls2085ardb: Add support of LS2085ARDB platform armv8/fsl-lsch3: Implement workaround for I2C issue pankaj chauhan (2): armv8/ls2085a: Add support for reset request net/phy/cortina: Fix compilation warning README|8 + arch/arm/Kconfig | 24 + arch/arm/cpu/armv7/ls102xa/clock.c|4 +- arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 + arch/arm/cpu/armv8/fsl-lsch3/README | 78 +++- arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 123 - arch/arm/cpu/armv8/fsl-lsch3/fdt.c|9 +- arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 115 + arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 15 + arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117 + arch/arm/cpu/armv8/fsl-lsch3/mp.c |7 + arch/arm/cpu/armv8/fsl-lsch3/mp.h |1 + arch/arm/cpu/armv8/fsl-lsch3/soc.c| 107 + arch/arm/cpu/armv8/fsl-lsch3/speed.c | 11 +- arch/arm/cpu/armv8/generic_timer.c| 11 + arch/arm/cpu/armv8/u-boot-spl.lds | 77 arch/arm/include/asm/arch-fsl-lsch3/config.h | 42 ++ arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 +++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 29 ++ arch/arm/include/asm/arch-fsl-lsch3/soc.h |8 + arch/arm/lib/crt0_64.S|7 + arch/powerpc/cpu/mpc85xx/cpu_init_early.c |8 +- arch/powerpc/cpu/mpc85xx/speed.c |4 +- board/freescale/bsc9132qds/bsc9132qds.c |4 +- board/freescale/c29xpcie/c29xpcie.c |4 +- board/freescale/common/qixis.c| 31 +- board/freescale/ls2085a/ls2085a.c | 29 +- board/freescale/ls2085aqds/Kconfig| 16 + board/freescale/ls2085aqds/MAINTAINERS|8 + board/freescale/ls2085aqds/Makefile |9 + board/freescale/ls2085aqds/README | 148 ++ board/freescale/ls2085aqds/ddr.c | 196 board/freescale/ls2085aqds/ddr.h | 92 board/freescale/ls2085aqds/eth.c | 380 +++ board/freescale/ls2085aqds/ls2085aqds.c | 274 +++ board/freescale/ls2085aqds/ls2085aqds_qixis.h | 30 ++ board/freescale/ls2085ardb/Kconfig| 16 + board/freescale/ls2085ardb/MAINTAINERS|8 + board/freescale/ls2085ardb/Makefile |8 + board/fr
[U-Boot] [PATCH v5 04/28] armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun
CC: Mark Rutland
---
Changes in v5: None
Changes in v4:
Remove temporary variable cntfrq.
Changes in v3:
Move secondary core fix to mp.c.
Replace hard-coded value with COUNTER_FREQUENCY.
Changes in v2:
Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.
README |8
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |6 ++
arch/arm/cpu/armv8/fsl-lsch3/mp.c |7 +++
arch/arm/cpu/armv8/fsl-lsch3/mp.h |1 +
board/freescale/ls2085a/ls2085a.c | 18 --
include/configs/ls2085a_common.h|6 +-
7 files changed, 51 insertions(+), 19 deletions(-)
diff --git a/README b/README
index e710226..f063a74 100644
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
+
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
+
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd147..e985181 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
return 0;
}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+ unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+ /* Enable timebase for all clusters.
+* It is safe to do so even some clusters are not enabled.
+*/
+ out_le32(cltbenr, 0xf);
+
+ /* Enable clock for timer
+* This is a global setting.
+*/
+ out_le32(cntcr, 0x1);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 886576e..53bdb44 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -224,6 +224,9 @@ ENTRY(secondary_boot_func)
/* physical address of this cpus spin table element */
add x11, x1, x0
+ ldr x0, =__real_cntfrq
+ ldr x0, [x0]
+ msr cntfrq_el0, x0 /* set with real frequency */
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
@@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1)
/* 64 bit alignment for elements accessed as data */
.align 4
+ .global __real_cntfrq
+__real_cntfrq:
+ .quad COUNTER_FREQUENCY
.globl __secondary_boot_code_size
.type __secondary_boot_code_size, %object
/* Secondary Boot Code ends here */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index ce9c0c1..da7853a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void)
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
+#ifdef COUNTER_FREQUENCY_REAL
+ /* update for secondary cores */
+ __real_cntfrq = COUNTER_FREQUENCY_REAL;
+ flush_dcache_range((unsigned long)&__real_cntfrq,
+ (unsigned long)&__real_cntfrq + 8);
+#endif
+
cores = cpu_mask();
/* Clear spin table so that secondary processors
* observe the correct value after waking up from wfe.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 66144d6..c985d6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -26,6 +26,7 @@
#define id_to_core(x) ((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
extern u64 __spin_table[];
+extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
int fsl_lsch3_wake_seconday_cores(void);
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board
[U-Boot] [PATCH v5 01/28] armv8/fsl-lsch3: Implement workaround for erratum A008585
Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/generic_timer.c | 11 +++
arch/arm/include/asm/arch-fsl-lsch3/config.h |1 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/arm/cpu/armv8/generic_timer.c
index 223b95e..8e60bae 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -25,7 +25,18 @@ unsigned long get_tbclk(void)
unsigned long timer_read_counter(void)
{
unsigned long cntpct;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+ /* This erratum number needs to be confirmed to match ARM document */
+ unsigned long temp;
+#endif
isb();
asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+ asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
+ while (temp != cntpct) {
+ asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+ asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
+ }
+#endif
return cntpct;
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 1d2a7fa..2d461d9 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -120,6 +120,7 @@
#ifdef CONFIG_LS2085A
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
--
1.7.9.5
___
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Re: [U-Boot] [PATCH v4 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On 03/20/2015 05:33 PM, Scott Wood wrote: > On Fri, 2015-03-20 at 17:29 -0700, York Sun wrote: >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index f4a7851..7478eb4 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -658,6 +658,16 @@ config TARGET_LS2085AQDS >>development platform that supports the QorIQ LS2085A >>Layerscape Architecture processor. >> >> +config TARGET_LS2085ARDB >> +bool "Support ls2085ardb" >> +select ARM64 >> +select ARMV8_MULTIENTRY >> +help >> + Support for Freescale LS2085ARDB platform. >> + The LS2080A Reference design board (RDB) is a high-performance >> + development platform that supports the QorIQ LS2085A >> + LayerScape Architecture processor. >> + > > s/LayerScape/Layerscape/ > >> diff --git a/board/freescale/ls2085aqds/README >> b/board/freescale/ls2085ardb/README >> similarity index 73% >> copy from board/freescale/ls2085aqds/README >> copy to board/freescale/ls2085ardb/README >> index a4d7b53..cfd5185 100644 >> --- a/board/freescale/ls2085aqds/README >> +++ b/board/freescale/ls2085ardb/README >> @@ -1,10 +1,8 @@ >> Overview >> >> -The LS2080A Development System (QDS) is a high-performance computing, >> -evaluation, and development platform that supports the QorIQ LS2080A >> -LayerScape Architecture processor. The LS2080AQDS provides validation and >> -SW development platform for the Freescale LS2080A processor series, with >> -a complete debugging environment. >> +The LS2085A Reference Design (RDB) is a high-performance computing, >> +evaluation, and development platform that supports the QorIQ LS2085A >> +Layerscape Architecture processor. > > "LayerScape" and 2080 should be fixed in the QDS patch as well. > >> @@ -113,25 +105,25 @@ unsigned long get_board_ddr_clk(void); >> #define CONFIG_SYS_NAND_CSOR(CSOR_NAND_ECC_ENC_EN /* ECC on encode */ >> \ >> | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ >> | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ >> -| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ >> -| CSOR_NAND_PGS_2K /* Page Size = 2K */ \ >> -| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ >> -| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ >> +| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ >> +| CSOR_NAND_PGS_4K /* Page Size = 4K */ \ >> +| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ >> +| CSOR_NAND_PB(128))/*Pages Per Block = >> 128*/ > > From this it looks like the QDS patch still has a comment/code > inconsistency with RAL. > Let me re-generate the patch using patman, without -C --find-copies-harder flag so they don't show as copy-n-modify. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On Fri, 2015-03-20 at 17:29 -0700, York Sun wrote: > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index f4a7851..7478eb4 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -658,6 +658,16 @@ config TARGET_LS2085AQDS > development platform that supports the QorIQ LS2085A > Layerscape Architecture processor. > > +config TARGET_LS2085ARDB > + bool "Support ls2085ardb" > + select ARM64 > + select ARMV8_MULTIENTRY > + help > + Support for Freescale LS2085ARDB platform. > + The LS2080A Reference design board (RDB) is a high-performance > + development platform that supports the QorIQ LS2085A > + LayerScape Architecture processor. > + s/LayerScape/Layerscape/ > diff --git a/board/freescale/ls2085aqds/README > b/board/freescale/ls2085ardb/README > similarity index 73% > copy from board/freescale/ls2085aqds/README > copy to board/freescale/ls2085ardb/README > index a4d7b53..cfd5185 100644 > --- a/board/freescale/ls2085aqds/README > +++ b/board/freescale/ls2085ardb/README > @@ -1,10 +1,8 @@ > Overview > > -The LS2080A Development System (QDS) is a high-performance computing, > -evaluation, and development platform that supports the QorIQ LS2080A > -LayerScape Architecture processor. The LS2080AQDS provides validation and > -SW development platform for the Freescale LS2080A processor series, with > -a complete debugging environment. > +The LS2085A Reference Design (RDB) is a high-performance computing, > +evaluation, and development platform that supports the QorIQ LS2085A > +Layerscape Architecture processor. "LayerScape" and 2080 should be fixed in the QDS patch as well. > @@ -113,25 +105,25 @@ unsigned long get_board_ddr_clk(void); > #define CONFIG_SYS_NAND_CSOR(CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ > | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ > | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ > - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ > - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ > - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ > - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ > + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ > + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ > + | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ > + | CSOR_NAND_PB(128))/*Pages Per Block = > 128*/ >From this it looks like the QDS patch still has a comment/code inconsistency with RAL. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
The LS2080ARDB is a evaluation platform that supports LS2080A
family SoCs. This patch add sbasic support for the platform.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Bhupesh Sharma
Signed-off-by: Scott Wood
---
Changes in v4:
Fix board README for inconsistent SoC name
Fix comments in board header file
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig | 11 +++
arch/arm/cpu/armv8/fsl-lsch3/README|4 +-
board/freescale/{ls2085aqds => ls2085ardb}/Kconfig |6 +-
board/freescale/ls2085ardb/MAINTAINERS |7 ++
.../freescale/{ls2085aqds => ls2085ardb}/Makefile |2 +-
board/freescale/{ls2085aqds => ls2085ardb}/README | 48 -
board/freescale/{ls2085aqds => ls2085ardb}/ddr.c |0
board/freescale/{ls2085aqds => ls2085ardb}/ddr.h |6 +-
.../ls2085aqds.c => ls2085ardb/ls2085ardb.c} | 54 +++---
.../ls2085ardb_qixis.h}| 12 +---
...qds_ddr4_nor_defconfig => ls2085ardb_defconfig} |2 +-
include/configs/{ls2085aqds.h => ls2085ardb.h} | 75
12 files changed, 82 insertions(+), 145 deletions(-)
copy board/freescale/{ls2085aqds => ls2085ardb}/Kconfig (66%)
create mode 100644 board/freescale/ls2085ardb/MAINTAINERS
copy board/freescale/{ls2085aqds => ls2085ardb}/Makefile (81%)
copy board/freescale/{ls2085aqds => ls2085ardb}/README (73%)
copy board/freescale/{ls2085aqds => ls2085ardb}/ddr.c (100%)
copy board/freescale/{ls2085aqds => ls2085ardb}/ddr.h (93%)
copy board/freescale/{ls2085aqds/ls2085aqds.c => ls2085ardb/ls2085ardb.c} (76%)
copy board/freescale/{ls2085aqds/ls2085aqds_qixis.h =>
ls2085ardb/ls2085ardb_qixis.h} (61%)
copy configs/{ls1021aqds_ddr4_nor_defconfig => ls2085ardb_defconfig} (66%)
copy include/configs/{ls2085aqds.h => ls2085ardb.h} (79%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f4a7851..7478eb4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -658,6 +658,16 @@ config TARGET_LS2085AQDS
development platform that supports the QorIQ LS2085A
Layerscape Architecture processor.
+config TARGET_LS2085ARDB
+ bool "Support ls2085ardb"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2085ARDB platform.
+ The LS2080A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2085A
+ LayerScape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -804,6 +814,7 @@ source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
+source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/mx23evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
index 817ea1b..4f36e2a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -38,7 +38,7 @@ Flash Layout
32-MB NOR flash layout for pre-silicon platforms (simulator and
emulator)
(2) A typical layout of various images (including Linux and other firmware
images)
-is shown below considering a 128MB NOR flash device present on QDS
+is shown below considering a 128MB NOR flash device present on QDS and RDB
boards:
- > 0x5_8800_ ---
| .. Unused .. (7M) | |
@@ -86,7 +86,7 @@ Flash Layout
| RCW and PBI (1M)| |
- > 0x5_8000_ ---
- 128-MB NOR flash layout for QDS board
+ 128-MB NOR flash layout for QDS and RDB boards
Environment Variables
=
diff --git a/board/freescale/ls2085aqds/Kconfig
b/board/freescale/ls2085ardb/Kconfig
similarity index 66%
copy from board/freescale/ls2085aqds/Kconfig
copy to board/freescale/ls2085ardb/Kconfig
index deb640d..85a3dcd 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2085ardb/Kconfig
@@ -1,8 +1,8 @@
-if TARGET_LS2085AQDS
+if TARGET_LS2085ARDB
config SYS_BOARD
- default "ls2085aqds"
+ default "ls2085ardb"
config SYS_VENDOR
default "freescale"
@@ -11,6 +11,6 @@ config SYS_SOC
default "fsl-lsch3"
config SYS_CONFIG_NAME
- default "ls2085aqds"
+ default "ls2085ardb"
endif
diff --git a/board/freescale/ls2085ardb/MAINTAINERS
b/board/freescale/ls2085ardb/MAINTAINERS
new file mode 100644
index 000..436039f
--- /dev/null
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS2085A BOARD
+M: Prabhakar Kushwaha
+S: Maintained
+F: board/freescale/ls2085ardb
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On Fri, 2015-03-20 at 20:18 -0400, Tom Rini wrote: > On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote: > > On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote: > > > On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote: > > > > > > [snip] > > > > It would also be nice to sort out loading the environment during SPL. > > > > > > *ears perk up*. Please elaborate :) We have SPL environment support, > > > we have SPL NAND Environment support today. It doesn't get passed along > > > to the running U-Boot and it's used for some limited cases (network and > > > redundancy). I'd like to hear about more and better ways of using it. > > > > In common/spl/spl_nand.c, why does it only load the environment when > > CONFIG_NAND_ENV_DST is defined, yet it never uses the value of > > CONFIG_NAND_ENV_DST? I also don't see any boards definind > > CONFIG_NAND_ENV_DST (apparently the only one that ever used it was > > smdk6400 which has been removed). > > > > Is there some other way that the environment is supposed to be getting > > loaded from NAND (rather than using the default environment) during SPL? > > Yeah, it's loaded via env_init() being called (see spl_net.c or > board/ti/). The NAND version of env_init() does not access NAND. It loads from CONFIG_NAND_ENV_DST (but again, no board sets that) or from an embedded environment. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote: > On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote: > > On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote: > > > > [snip] > > > It would also be nice to sort out loading the environment during SPL. > > > > *ears perk up*. Please elaborate :) We have SPL environment support, > > we have SPL NAND Environment support today. It doesn't get passed along > > to the running U-Boot and it's used for some limited cases (network and > > redundancy). I'd like to hear about more and better ways of using it. > > In common/spl/spl_nand.c, why does it only load the environment when > CONFIG_NAND_ENV_DST is defined, yet it never uses the value of > CONFIG_NAND_ENV_DST? I also don't see any boards definind > CONFIG_NAND_ENV_DST (apparently the only one that ever used it was > smdk6400 which has been removed). > > Is there some other way that the environment is supposed to be getting > loaded from NAND (rather than using the default environment) during SPL? Yeah, it's loaded via env_init() being called (see spl_net.c or board/ti/). -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On 03/20/2015 05:12 PM, Scott Wood wrote: > On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote: >> >> On 03/20/2015 04:01 PM, Scott Wood wrote: >>> On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define CONFIG_DDR_CLK_FREQ 1 #define COUNTER_FREQUENCY_REAL(CONFIG_SYS_CLK_FREQ/4) >>> >>> Why? >> >> The timer clock source is not a fixed clock. It derives from system clock, >> dividing by 4. For this board, the system clock is fixed on board. But I >> don't >> think the timer clock should be hard-coded. > > I was referring to the DDR clock change. DDR reference clock is fixed on RDB. > @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RST_CTL_RESET_EN0x30 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 >>> >>> Is this really a difference between the two boards? >>> >> >> RDB is designed to be compatible in many ways to QDS, but it is still >> different. >> The QIXIS is compatible with most common registers, but not all of them. > > OK. I wasn't sure if it was just something that got added by someone > working on RDB, that also exists on QDS. > The RST_CTL_RESET_EN bit? It was enabled by default on QDS, but disable on RDB. We need to enable it in order to use "reset" command. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote: > > On 03/20/2015 04:01 PM, Scott Wood wrote: > > On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: > >> #ifndef __ASSEMBLY__ > >> unsigned long get_board_sys_clk(void); > >> -unsigned long get_board_ddr_clk(void); > >> #endif > >> > >> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() > >> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() > >> +#define CONFIG_DDR_CLK_FREQ 1 > >> #define COUNTER_FREQUENCY_REAL(CONFIG_SYS_CLK_FREQ/4) > > > > Why? > > The timer clock source is not a fixed clock. It derives from system clock, > dividing by 4. For this board, the system clock is fixed on board. But I don't > think the timer clock should be hard-coded. I was referring to the DDR clock change. > >> @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); > >> #define QIXIS_LBMAP_DFLTBANK 0x00 > >> #define QIXIS_LBMAP_ALTBANK 0x04 > >> #define QIXIS_RST_CTL_RESET 0x31 > >> +#define QIXIS_RST_CTL_RESET_EN0x30 > >> #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 > >> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 > >> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 > > > > Is this really a difference between the two boards? > > > > RDB is designed to be compatible in many ways to QDS, but it is still > different. > The QIXIS is compatible with most common registers, but not all of them. OK. I wasn't sure if it was just something that got added by someone working on RDB, that also exists on QDS. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On 03/20/2015 04:01 PM, Scott Wood wrote: > On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: >> The LS2080ARDB is a evaluation platform that supports LS2080A >> family SoCs. This patch add sbasic support for the platform. > > s/2080/2085/ > >> diff --git a/board/freescale/ls2085aqds/Makefile >> b/board/freescale/ls2085ardb/Makefile >> similarity index 81% >> copy from board/freescale/ls2085aqds/Makefile >> copy to board/freescale/ls2085ardb/Makefile >> index f174f33..0bfe21c 100644 >> --- a/board/freescale/ls2085aqds/Makefile >> +++ b/board/freescale/ls2085ardb/Makefile >> @@ -4,5 +4,5 @@ >> # SPDX-License-Identifier: GPL-2.0+ >> # >> >> -obj-y += ls2085aqds.o >> +obj-y += ls2085ardb.o >> obj-y += ddr.o >> diff --git a/board/freescale/ls2085aqds/README >> b/board/freescale/ls2085ardb/README >> similarity index 73% >> copy from board/freescale/ls2085aqds/README >> copy to board/freescale/ls2085ardb/README >> index a4d7b53..19f9d2a 100644 >> --- a/board/freescale/ls2085aqds/README >> +++ b/board/freescale/ls2085ardb/README >> @@ -1,10 +1,8 @@ >> Overview >> >> -The LS2080A Development System (QDS) is a high-performance computing, >> +The LS2080A Reference Design (RDB) is a high-performance computing, >> evaluation, and development platform that supports the QorIQ LS2080A >> -LayerScape Architecture processor. The LS2080AQDS provides validation and >> -SW development platform for the Freescale LS2080A processor series, with >> -a complete debugging environment. >> +LayerScape Architecture processor. > > I don't think Layerscape is supposed to be capitalized that way. > >> LS2085A SoC Overview >> -- >> @@ -50,14 +48,11 @@ The LS2085A SoC includes the following function and >> features: >> - Service processor (SP) provides pre-boot initialization and secure-boot >>capabilities >> >> - LS2080AQDS board Overview >> + LS2080aRDB board Overview > > Inconsistent capitalization > >> #ifndef __ASSEMBLY__ >> unsigned long get_board_sys_clk(void); >> -unsigned long get_board_ddr_clk(void); >> #endif >> >> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() >> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() >> +#define CONFIG_DDR_CLK_FREQ 1 >> #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) > > Why? The timer clock source is not a fixed clock. It derives from system clock, dividing by 4. For this board, the system clock is fixed on board. But I don't think the timer clock should be hard-coded. > >> @@ -30,8 +32,8 @@ unsigned long get_board_ddr_clk(void); >> #define CONFIG_MEM_INIT_VALUE 0xdeadbeef >> #define SPD_EEPROM_ADDRESS1 0x51 >> #define SPD_EEPROM_ADDRESS2 0x52 >> -#define SPD_EEPROM_ADDRESS3 0x53 >> -#define SPD_EEPROM_ADDRESS4 0x54 >> +#define SPD_EEPROM_ADDRESS3 0x54 >> +#define SPD_EEPROM_ADDRESS4 0x53/* Bard error */ >> #define SPD_EEPROM_ADDRESS5 0x55 >> #define SPD_EEPROM_ADDRESS6 0x56/* dummy address */ >> #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 > > I suspect this should be s/Bard/Board/ Right. > >> @@ -114,24 +106,24 @@ unsigned long get_board_ddr_clk(void); >> | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ >> | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ >> | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ >> -| CSOR_NAND_PGS_2K /* Page Size = 2K */ \ >> -| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ >> -| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ >> +| CSOR_NAND_PGS_4K /* Page Size = 2K */ \ >> +| CSOR_NAND_SPRZ_224/* Spare size = 64 */ \ >> +| CSOR_NAND_PB(128))/*Pages Per Block = 64*/ > > Comments don't match code. Result of squashing. Will fix in next version. > >> @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); >> #define QIXIS_LBMAP_DFLTBANK0x00 >> #define QIXIS_LBMAP_ALTBANK 0x04 >> #define QIXIS_RST_CTL_RESET 0x31 >> +#define QIXIS_RST_CTL_RESET_EN 0x30 >> #define QIXIS_RCFG_CTL_RECONFIG_IDLE0x20 >> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 >> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 > > Is this really a difference between the two boards? > RDB is designed to be compatible in many ways to QDS, but it is still different. The QIXIS is compatible with most common registers, but not all of them. I will send out a new version soon. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: serial: remove bogus include
On 20 March 2015 at 09:24, Tom Rini wrote: > On Fri, Mar 20, 2015 at 01:24:45PM +0900, Masahiro Yamada wrote: > >> Serial-uclass should be generically implemented without depending >> a particular hardware. Fortunately, nothing in include/ns16550.h is >> referenced from drivers/serial/serial-uclass.c, so remove this bogus >> include. >> >> Signed-off-by: Masahiro Yamada > > Reviewed-by: Tom Rini Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] exynos5: add trace feature #ifdef in exynos5-common.h
On 13 March 2015 at 02:48, Inha Song wrote: > We can enable / disable trace feature from the FTRACE config options. > To enable, compile U-Boot with FTRACE=1. > > This patch add #ifdef FTRACE in exynos5-common.h for enable/disable > to use FTRACE configs instead of having to change board config files. > > Signed-off-by: Inha Song > --- > include/configs/exynos5-common.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 21/22] dm: x86: pci: Convert chromebook_link to use driver model for pci
On 5 March 2015 at 12:25, Simon Glass wrote: > Move chromebook_link over to driver model for PCI. > > This involves: > - adding a uclass for platform controller hub > - removing most of the existing PCI driver > - adjusting how CPU init works to use driver model instead > - rename the lpc compatible string (it will be removed later) > > This does not really take advantage of driver model fully, but it does work. > Furture work will improve the code structure to remove many of the explicit > calls to init the board. > > Signed-off-by: Simon Glass Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 22/22] dm: pci: Add driver model tests for PCI
On 5 March 2015 at 12:25, Simon Glass wrote: > Add some basic tests to check that things work as expected with sandbox. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > test/dm/Makefile | 1 + > test/dm/pci.c| 59 > > test/dm/test.dts | 17 > 3 files changed, 77 insertions(+) > create mode 100644 test/dm/pci.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 16/22] dm: sandbox: pci: Add a PCI emulation uclass
On 5 March 2015 at 12:25, Simon Glass wrote: > Since sandbox does not have real devices (unless it borrows those from the > host) it must use emulations. Provide a uclass which permits PCI operations > to be passed through to an emulation device. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/pci/Makefile | 1 + > drivers/pci/pci-emul-uclass.c | 67 ++ > include/dm/uclass-id.h| 1 + > include/pci.h | 108 > ++ > 4 files changed, 177 insertions(+) > create mode 100644 drivers/pci/pci-emul-uclass.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 20/22] dm: x86: pci: Convert coreboot to use driver model for pci
On 5 March 2015 at 12:25, Simon Glass wrote: > Move coreboot-x86 over to driver model for PCI. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/cpu/coreboot/pci.c | 63 > ++--- > arch/x86/dts/chromebook_link.dts| 7 + > board/google/chromebook_link/link.c | 9 ++ > configs/coreboot-x86_defconfig | 1 + > include/dm/uclass-id.h | 1 + > 5 files changed, 34 insertions(+), 47 deletions(-) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 18/22] dm: sandbox: pci: Enable PCI for sandbox
On 5 March 2015 at 12:25, Simon Glass wrote: > Enable PCI options so that sandbox can be used for testing this bus with > driver model. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > configs/sandbox_defconfig | 3 +++ > include/configs/sandbox.h | 4 > 2 files changed, 7 insertions(+) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 19/22] dm: x86: pci: Add a PCI driver for driver model
On 5 March 2015 at 12:25, Simon Glass wrote: > Add a simple x86 PCI driver which uses standard functions provided by the > architecture. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/cpu/pci.c | 40 > arch/x86/include/asm/pci.h | 8 > arch/x86/lib/Makefile | 2 ++ > drivers/pci/Makefile | 1 + > drivers/pci/pci_x86.c | 24 > 5 files changed, 75 insertions(+) > create mode 100644 drivers/pci/pci_x86.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 17/22] dm: sandbox: Add a emulated PCI device as an example
On 5 March 2015 at 12:25, Simon Glass wrote: > This device sits on the sandbox PCI bus and provides a case-swapping > service for sandbox. It illustrates the use of both PCI I/O and PCI > memory accesses. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/misc/Makefile| 1 + > drivers/misc/swap_case.c | 285 > +++ > 2 files changed, 286 insertions(+) > create mode 100644 drivers/misc/swap_case.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 15/22] dm: sandbox: Add a simple PCI driver
On 5 March 2015 at 12:25, Simon Glass wrote: > Add a driver which can access emulations of devices and make them available > in sandbox. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/pci/Kconfig | 10 ++ > drivers/pci/Makefile | 1 + > drivers/pci/pci_sandbox.c | 79 > +++ > 3 files changed, 90 insertions(+) > create mode 100644 drivers/pci/pci_sandbox.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 11/22] dm: Show both allocated and requested seq numbers in 'dm uclass'
On 5 March 2015 at 12:25, Simon Glass wrote: > Both of these values are useful for understanding what is going on, so show > them both. > > The requested number comes from a device tree alias. The allocated one is > set up when the device is activated, and is unique throughout the uclass. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > test/dm/cmd_dm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 14/22] dm: sandbox: pci: Add PCI support for sandbox
On 5 March 2015 at 12:25, Simon Glass wrote: > Add the required header information, device tree nodes and I/O accessor > functions to support PCI on sandbox. All devices are emulated by drivers > which can be added as required for testing or development. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 13/22] dm: pci: Add a uclass for PCI
On 5 March 2015 at 12:25, Simon Glass wrote: > Add a uclass for PCI controllers and a generic one for PCI devices. Adjust > the 'pci' command and the existing PCI support to work with this new uclass. > Keep most of the compatibility code in a separate file so that it can be > removed one day. > > TODO: Add more header file comments to the new parts of pci.h > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > common/board_r.c | 2 + > common/cmd_pci.c | 14 +- > doc/driver-model/pci-info.txt | 70 + > drivers/pci/Kconfig | 12 + > drivers/pci/Makefile | 8 +- > drivers/pci/pci-uclass.c | 639 > ++ > drivers/pci/pci_auto.c| 16 +- > drivers/pci/pci_compat.c | 43 +++ > include/dm/uclass-id.h| 2 + > include/pci.h | 289 ++- > 10 files changed, 1081 insertions(+), 14 deletions(-) > create mode 100644 doc/driver-model/pci-info.txt > create mode 100644 drivers/pci/pci-uclass.c > create mode 100644 drivers/pci/pci_compat.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 10/22] dm: core: Add a uclass pre_probe() method for devices
On 5 March 2015 at 12:25, Simon Glass wrote: > Some uclasses want to set up a device before it is probed. Add a method > for this. > > An example is with PCI, where a PCI uclass wants to set up its private > data for later use. This allows the device's uclass() method to make calls > whcih use that data (for example, read PCI memory regions from device > tree, set up bus numbers). > > Signed-off-by: Simon Glass > --- > > Changes in v2: None Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 09/22] dm: core: Mark device as active before calling its probe() method
On 5 March 2015 at 12:25, Simon Glass wrote: > At present the device is not active when the probe() method is called. But > some probe() methods want to set up the device and this can involve > accessing it through normal methods. For example a PCI bus may wish to > set up its PCI parameters using calls to pci_hose_write_config_dword() and > similar. > > At present this does not work because every such call within the probe() > method sees that the device is not active and attempts to probe it. > > Already we mark the device as probed before calling the uclass post_probe() > method. This is a subtle change but I believe the new approach is better. > Since the scope of the change is only the probe() method and all its callees > it should still be within the control of the board author. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/core/device.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 12/22] dm: pci: Move common PCI functions into their own file
On 5 March 2015 at 12:25, Simon Glass wrote: > Driver model will share many functions with the existing PCI implementation. > Move these into their own file to avoid duplication and confusion. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/pci/Makefile | 2 +- > drivers/pci/pci.c| 281 + > drivers/pci/pci_common.c | 292 > +++ > include/pci.h| 14 +++ > 4 files changed, 313 insertions(+), 276 deletions(-) > create mode 100644 drivers/pci/pci_common.c Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 08/22] dm: core: Add dev_get_uclass_priv() to access uclass private data
On 5 March 2015 at 12:25, Simon Glass wrote: > Add a convenience function to access the private data that a uclass stores > for each of its devices. Convert over most existing uses for consistency > and to provide an example for others. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > common/cmd_sf.c| 2 +- > common/cros_ec.c | 2 +- > drivers/core/device.c | 10 ++ > drivers/gpio/at91_gpio.c | 2 +- > drivers/gpio/bcm2835_gpio.c| 2 +- > drivers/gpio/gpio-uclass.c | 22 +++--- > drivers/gpio/intel_ich6_gpio.c | 2 +- > drivers/gpio/mxc_gpio.c| 2 +- > drivers/gpio/omap_gpio.c | 2 +- > drivers/gpio/s5p_gpio.c| 2 +- > drivers/gpio/sandbox.c | 6 +++--- > drivers/gpio/sunxi_gpio.c | 2 +- > drivers/gpio/tegra_gpio.c | 2 +- > drivers/i2c/i2c-uclass.c | 6 +++--- > drivers/i2c/sandbox_i2c.c | 2 +- > drivers/misc/cros_ec.c | 6 +++--- > drivers/misc/cros_ec_i2c.c | 2 +- > drivers/misc/cros_ec_sandbox.c | 2 +- > drivers/misc/cros_ec_spi.c | 4 ++-- > drivers/mtd/spi/sf-uclass.c| 2 +- > drivers/mtd/spi/sf_probe.c | 8 > drivers/serial/serial-uclass.c | 4 ++-- > drivers/spi/spi-uclass.c | 4 ++-- > include/dm/device.h| 10 ++ > include/i2c.h | 8 > test/dm/core.c | 2 +- > test/dm/test-uclass.c | 4 ++-- > 27 files changed, 71 insertions(+), 51 deletions(-) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/22] Correct map_sysmem() logic in do_mem_mw()
On 9 March 2015 at 03:06, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> This function does not unmap what it maps. Correct it.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2: None
>>
>> common/cmd_mem.c | 7 ---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/common/cmd_mem.c b/common/cmd_mem.c
>> index bcb3ee3..855aa57 100644
>> --- a/common/cmd_mem.c
>> +++ b/common/cmd_mem.c
>> @@ -165,7 +165,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int
>> argc, char * const argv[])
>> #endif
>> ulong addr, count;
>> int size;
>> - void *buf;
>> + void *buf, *start;
>> ulong bytes;
>>
>> if ((argc < 3) || (argc > 4))
>> @@ -197,7 +197,8 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int
>> argc, char * const argv[])
>> }
>>
>> bytes = size * count;
>> - buf = map_sysmem(addr, bytes);
>> + start = map_sysmem(addr, bytes);
>> + buf = start;
>> while (count-- > 0) {
>> if (size == 4)
>> *((u32 *)buf) = (u32)writeval;
>> @@ -211,7 +212,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int
>> argc, char * const argv[])
>> *((u8 *)buf) = (u8)writeval;
>> buf += size;
>> }
>> - unmap_sysmem(buf);
>> + unmap_sysmem(start);
>> return 0;
>> }
>>
>> --
>
> Reviewed-by: Bin Meng
Applied to u-boot-dm/next.
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Re: [U-Boot] [PATCH v2 07/22] fdt: Tighten up error handling in fdtdec_get_pci_addr()
On 9 March 2015 at 03:09, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> This function returns -ENOENT when the property is missing (which the caller
>> might forgive) and also when the property is present but incorrectly
>> formatted (which many callers would like to report).
>>
>> Update the error return value to allow these different situations to be
>> distinguished.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Add -ve sign before ENXIO
>>
>> include/fdtdec.h | 4 +++-
>> lib/fdtdec.c | 4 +++-
>> 2 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 21bd6bb..6944048 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -327,7 +327,9 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int
>> node,
>> * @param type pci address type (FDT_PCI_SPACE_xxx)
>> * @param prop_namename of property to find
>> * @param addr returns pci address in the form of fdt_pci_addr
>> - * @return 0 if ok, negative on error
>> + * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the
>> + * format of the property was invalid, -ENXIO if the requested
>> + * address type was not found
>> */
>> int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
>> const char *prop_name, struct fdt_pci_addr *addr);
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index e47fa96..9212f03 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -160,8 +160,10 @@ int fdtdec_get_pci_addr(const void *blob, int node,
>> enum fdt_pci_space type,
>> }
>> }
>>
>> - if (i == num)
>> + if (i == num) {
>> + ret = -ENXIO;
>> goto fail;
>> + }
>>
>> return 0;
>> } else {
>> --
>
> Reviewed-by: Bin Meng
Applied to u-boot-dm/next.
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Re: [U-Boot] [PATCH v2 04/22] dm: Add a new CPU init function which can use driver model
On 9 March 2015 at 03:02, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> Since driver model is set up after arch_cpu_init(), that function cannot
>> use drivers. Add a new arch_cpu_init_dm() function which is called
>> immediately after driver model is ready, and can reference devices.
>>
>> This can be used to probe essential devices for the CPU.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Add a new patch with a CPU init function which can use driver model
>>
>> common/board_f.c | 6 ++
>> include/common.h | 11 +++
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/common/board_f.c b/common/board_f.c
>> index 4d8b8a6..8bbece2 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -787,6 +787,11 @@ __weak int reserve_arch(void)
>> return 0;
>> }
>>
>> +__weak int arch_cpu_init_dm(void)
>> +{
>> + return 0;
>> +}
>> +
>> static init_fnc_t init_sequence_f[] = {
>> #ifdef CONFIG_SANDBOX
>> setup_ram_buf,
>> @@ -807,6 +812,7 @@ static init_fnc_t init_sequence_f[] = {
>> fdtdec_check_fdt,
>> #endif
>> initf_dm,
>> + arch_cpu_init_dm,
>> #if defined(CONFIG_BOARD_EARLY_INIT_F)
>> board_early_init_f,
>> #endif
>> diff --git a/include/common.h b/include/common.h
>> index 77c55c6..f95 100644
>> --- a/include/common.h
>> +++ b/include/common.h
>> @@ -253,6 +253,17 @@ int update_flash_size(int flash_size);
>> int arch_early_init_r(void);
>>
>> /**
>> + * arch_cpu_init_dm() - init CPU after driver model is available
>> + *
>> + * This is called immediately after driver model is available before
>> + * relocation. This is similar to arch_cpu_init() but is able to reference
>> + * devices
>> + *
>> + * @return 0 if OK, -ve on error
>> + */
>> +int arch_cpu_init_dm(void);
>> +
>> +/**
>> * Reserve all necessary stacks
>> *
>> * This is used in generic board init sequence in common/board_f.c. Each
>> --
>
> Reviewed-by: Bin Meng
Applied to u-boot-dm/next.
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Re: [U-Boot] [PATCH v2 05/22] x86: Split up arch_cpu_init()
On 9 March 2015 at 03:06, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> At present we do more in this function than we should. Split out the
>> post-driver-model part into a separate function.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Use the new arch_cpu_init_dm() function instead of something x86-specific
>>
>> arch/x86/cpu/ivybridge/cpu.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
>> index 5fd3753..e6ef481 100644
>> --- a/arch/x86/cpu/ivybridge/cpu.c
>> +++ b/arch/x86/cpu/ivybridge/cpu.c
>> @@ -116,6 +116,14 @@ static void set_spi_speed(void)
>>
>> int arch_cpu_init(void)
>> {
>> + post_code(POST_CPU_INIT);
>> + timer_set_base(rdtsc());
>> +
>> + return x86_cpu_init_f();
>> +}
>> +
>> +int arch_cpu_init_dm(void)
>> +{
>> const void *blob = gd->fdt_blob;
>> struct pci_controller *hose;
>> int node;
>> --
>
> Reviewed-by: Bin Meng
Applied to u-boot-dm/next.
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Re: [U-Boot] [PATCH v2 02/22] fdt: Export fdtdec_get_number() for general use
On 6 March 2015 at 08:43, Tom Rini wrote: > On Thu, Mar 05, 2015 at 12:25:14PM -0700, Simon Glass wrote: > >> This function is missing a prototype but is more widey useful. Add it. >> >> Signed-off-by: Simon Glass > > Reviewed-by: Tom Rini Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 03/22] x86: Add a x86_ prefix to the x86-specific PCI functions
On 5 March 2015 at 12:25, Simon Glass wrote: > These functions currently use a generic name, but they are for x86 only. > This may introduce confusion and prevents U-Boot from using these names > more widely. > > In fact it should be possible to remove these at some point and use > generic functions, but for now, rename them. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > Changes in v2: None Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: Add ramboot and nfsboot commands in x86-common.h
On 11 March 2015 at 23:08, Bin Meng wrote: > It is very common in the debug stage to test U-Boot loading a linux > kernel. The commands to boot linux kernel with ramdisk and nfs as the > root are common to all x86 targets, so it makes sense to add them as > the U-Boot default environment in x86-common.h. > > Signed-off-by: Bin Meng > --- > > include/configs/x86-common.h | 31 +-- > 1 file changed, 29 insertions(+), 2 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/22] Add driver model support for PCI
Hi, On 5 March 2015 at 12:25, Simon Glass wrote: > > This series is a collection of changes in core DM, sandbox, x86 and PCI code > to implement a PCI uclass and associated operations. Some basic tests are > provided as well. > > As is becoming common with DM conversions, the existing structure (here > struct pci_controller) becomes per-bus uclass data. This allows the concept > of a 'hose' (generally a PCI host controller and a bus) to continue to exist > in the interim, even if it should not be needed in the end. This makes it > much easier to convert over existing code. > > PCI buses are not scanned in the bind() method but only later when probe() > is called. This will be automatic if you access a bus, but it does mean that > if PCI is not used it will not be touched, in keeping with U-Boot's lazy- > init philosophy. > > The existing 'pciauto' bus configuration code is still used, although it now > uses DM underneath. It works exclusively by reading and writing PCI config > and does not refer to DM data structures. The one change is to drop use of > the hose->current_busno field which is no longer required. The fact that > file works largely as before is an indication that a good level of > compatibility is achieved between DM and legacy PCI. > > In order to support testing of PCI I/O and memory space, support has been > added to sandbox to allow mapping of these. This allows commands like 'md' > and 'iod' to display data from mapped PCI devices. Similarly, it is possible > to make changes to this space. This support relies on the existing > map_sysmem() and unmap_sysmem() calls which are now fairly widespread in > U-Boot. > > Apart from the driver model tests (run with ./test/dm/test-dm.sh) you can > try out these commands which use the new 'swap_case' test device: > > ../u-boot -d b/sandbox/u-boot.dtb > > => iow.b 2000 2 > => iod.b 2000 > : 02 > => mw.l 1000 64436241 > => md.l 1000 1 > 1000: 44634261 aBcD > => > > This shows an I/O access to 2000, setting the value 2 which means to > swap the case. Then 'AbCd' is written to the memory space at 1000 and > 'aBcD' is read back. > > The 'pci' command can be used as before. > > Most existing PCI functions (in pci.h) still work, but route through driver > model. The file drivers/pci/pci.c is replaced when driver model is enabled > so not everything is present. A new pci_common.c file holds functions common > to driver model and the old system, and pci_compat.c contains functions I > would like to eventually deprecate. > > Two x86 boards (coreboot and chromebook_link) are converted over to use > driver model for PCI. > > Core driver model changes include: > - Addition of a new pre_probe() method for the uclass to set up devices just > before the device's probe() method is called > - A change in the ordering of when a device is marked as probed > - A dev_get_uclass_priv() accessor > - A tweak to the 'dm uclass' command to improve sequence number display > > Notably missing from this series are functions to access PCI devices using > a 'struct udevice *'. Where there is no device tree entry for a bus device, > a generic PCI device is created in driver model to mirror the device, as > with I2C and SPI. Future work could add more real devices to x86 and create > a demand for these sorts of functions. Also we might store things like the > PCI base address registers (BARs) in data structures if there is a need. > These things are probably best developed as a need arises to avoid creating > infrastructure and overhead that may not be used. > > This series is available at u-boot-dm.git branch pci-working. > > Changes in v2: > - Update root node #size=cells to 1 in this patch > - Add a new patch with a CPU init function which can use driver model > - Use the new arch_cpu_init_dm() function instead of something x86-specific > - Add -ve sign before ENXIO I'm going to go ahead and apply this to u-boot-dm/next along with the x86 panther series (which it depends on). > > Simon Glass (22): > sandbox: Update device tree 'reg' properties for I2C and SPI > fdt: Export fdtdec_get_number() for general use > x86: Add a x86_ prefix to the x86-specific PCI functions > dm: Add a new CPU init function which can use driver model > x86: Split up arch_cpu_init() > Correct map_sysmem() logic in do_mem_mw() > fdt: Tighten up error handling in fdtdec_get_pci_addr() > dm: core: Add dev_get_uclass_priv() to access uclass private data > dm: core: Mark device as active before calling its probe() method > dm: core: Add a uclass pre_probe() method for devices > dm: Show both allocated and requested seq numbers in 'dm uclass' > dm: pci: Move common PCI functions into their own file > dm: pci: Add a uclass for PCI > dm: sandbox: pci: Add PCI support for sandbox > dm: sandbox: Add a simple PCI driver > dm: sandbox: pci: Add a PCI emulation uclass > dm: sandbox: Add a emulated PCI device as an
Re: [U-Boot] [PATCH v2 6/6] x86: Add support for panther (Asus Chromebox)
On 2 March 2015 at 12:40, Simon Glass wrote: > Support running U-Boot as a coreboot payload. Tested peripherals include: > > - Video (HDMI and DisplayPort) > - SATA disk > - Gigabit Ethernet > - SPI flash > > USB3 does not work. This may be a problem with the USB3 PCI driver or > something in the USB3 stack and has not been investigated So far this is > disabled. The SD card slot also does not work. > > For video, coreboot will need to run the OPROM to set this up. > > With this board, bare support (running without coreboot) is not available > as yet. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Update Kconfig and MAINTAINERS file to build bare > - Use "intel,haswell" as the compatible name Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/22] sandbox: Update device tree 'reg' properties for I2C and SPI
On 9 March 2015 at 02:57, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> We should have a size value for these. Add one in each case. This will
>> be needed for PCI.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Update root node #size=cells to 1 in this patch
>>
>> arch/sandbox/dts/sandbox.dts | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
>> index 9ce31bf..d090ba8 100644
>> --- a/arch/sandbox/dts/sandbox.dts
>> +++ b/arch/sandbox/dts/sandbox.dts
>> @@ -2,7 +2,7 @@
>>
>> / {
>> #address-cells = <1>;
>> - #size-cells = <0>;
>> + #size-cells = <1>;
>>
>> chosen {
>> stdout-path = "/serial";
>> @@ -144,7 +144,7 @@
>> i2c@0 {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> - reg = <0>;
>> + reg = <0 0>;
>> compatible = "sandbox,i2c";
>> clock-frequency = <40>;
>> eeprom@2c {
>> @@ -161,7 +161,7 @@
>> spi@0 {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> - reg = <0>;
>> + reg = <0 0>;
>> compatible = "sandbox,spi";
>> cs-gpios = <0>, <&gpio_a 0>;
>> flash@0 {
>> --
>
> Reviewed-by: Bin Meng
Applied to u-boot-dm/next.
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Re: [U-Boot] [PATCH v2 4/6] x86: spi: Add support for lynxpoint
On 2 March 2015 at 12:40, Simon Glass wrote: > Add Lynxpoint to the driver so that the Asus Chromebox can be supported. > > Signed-off-by: Simon Glass > Reviewed-by: Jagannadha Sutradharudu Teki > --- > > Changes in v2: None > > drivers/spi/ich.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/6] x86: Move common Chromebook config into a separate file
On 2 March 2015 at 12:40, Simon Glass wrote: > Since Chromebooks mostly have similar configuration, put it in a common > file. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > Changes in v2: None > > include/configs/chromebook_link.h | 61 +-- > include/configs/x86-chromebook.h | 68 > +++ > 2 files changed, 69 insertions(+), 60 deletions(-) > create mode 100644 include/configs/x86-chromebook.h Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/6] x86: pci: Add PCI IDs for lynxpoint
On 2 March 2015 at 12:40, Simon Glass wrote: > Add some new device IDs used by this haswell-based chipset. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > Changes in v2: > - Put this patch before the one that needs it > > include/pci_ids.h | 2 ++ > 1 file changed, 2 insertions(+) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/6] x86: Support machines with >4GB of RAM
On 3 March 2015 at 00:56, Lukasz Majewski wrote:
> Hi Simon,
>
>> Some systems have more than 4GB of RAM. U-Boot can only place things
>> below 4GB so any memory above that should not be used. Ignore any
>> such memory so that the memory size will not exceed the maximum.
>>
>> This prevents gd->ram_size exceeding 4GB which causes problems for PCI
>> devices which use DMA.
>>
>> Signed-off-by: Simon Glass
>> Reviewed-by: Bin Meng
>> ---
>>
>> Changes in v2: None
>>
>> arch/x86/cpu/coreboot/sdram.c | 6 --
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/cpu/coreboot/sdram.c
>> b/arch/x86/cpu/coreboot/sdram.c index e98a230..9c3ab81 100644
>> --- a/arch/x86/cpu/coreboot/sdram.c
>> +++ b/arch/x86/cpu/coreboot/sdram.c
>> @@ -90,7 +90,8 @@ int dram_init(void)
>> struct memrange *memrange = &lib_sysinfo.memrange[i];
>> unsigned long long end = memrange->base +
>> memrange->size;
>> - if (memrange->type == CB_MEM_RAM && end > ram_size)
>> + if (memrange->type == CB_MEM_RAM && end > ram_size &&
>> + memrange->base < (1ULL << 32))
>> ram_size = end;
>> }
>> gd->ram_size = ram_size;
>> @@ -108,7 +109,8 @@ void dram_init_banksize(void)
>> for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++)
>> { struct memrange *memrange = &lib_sysinfo.memrange[i];
>>
>> - if (memrange->type == CB_MEM_RAM) {
>> + if (memrange->type == CB_MEM_RAM &&
>> + memrange->base < (1ULL << 32)) {
>> gd->bd->bi_dram[j].start =
>> memrange->base; gd->bd->bi_dram[j].size = memrange->size;
>> j++;
>
> Reviewed-by: Lukasz Majewski
Applied to u-boot-dm/next.
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Re: [U-Boot] [PATCH v2 2/6] x86: video: Allow keyboard presence to be controlled by device tree
On 2 March 2015 at 12:40, Simon Glass wrote: > At present a VGA console assumes a keyboard unless a CONFIG option is set. > This difference can be dealt with by a device tree option, allowing boards > that are otherwise the same to use the same configuration. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Correct #ifdef setup to avoid build errors on non-x86 boards > > doc/README.fdt-control | 16 > drivers/video/cfb_console.c | 29 + > 2 files changed, 37 insertions(+), 8 deletions(-) Applied to u-boot-dm/next. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 09/27] net: Remove the bd* parameter from net stack functions
Hi Joe, On 11 March 2015 at 17:44, Joe Hershberger wrote: > This value is not used by the network stack and is available in the > global data, so stop passing it around. For the one legacy function > that still expects it (init op on old Ethernet drivers) pass in the > global pointer version directly to avoid changing that interface. > > Signed-off-by: Joe Hershberger > Reported-by: Simon Glass > Reviewed-by: Simon Glass > > --- > > Changes in v6: > -Fix compile errors for other boards due to removed parameters Unfortunately this causes several build failures: 38: net: Remove the bd* parameter from net stack functions powerpc: + PLU405 PMC440 sc3 neo acadia csb472 devconcenter sequoia arches lwmon5 t3corp walnut PMC405DE redwood katmai gdppc440etx p3p440 sycamore MIP405 zeus rainier_ramboot canyonlands MIP405T haleakala dlvision csb272 xpedite1000 io yosemite yucca makalu sequoia_ramboot dlvision-10g pcs440ep CPCI4052 sbc405 iocon ebony glacier_ramboot VOM405 bamboo luan io64 PIP405 intip glacier lcd4_lwmon5 bubinga yellowstone icon kilauea rainier e.g: $ buildman -b dm-push -s PLU405 -e ... 38: net: Remove the bd* parameter from net stack functions powerpc: + PLU405 +../drivers/net/4xx_enet.c: In function 'mal_err': +../drivers/net/4xx_enet.c:1734:2: error: too many arguments to function 'eth_init' +../include/net.h:169:5: note: declared here +make[2]: *** [drivers/net/4xx_enet.o] Error 1 +make[1]: *** [drivers/net] Error 2 +make: *** [sub-make] Error 2 ... Can you please check this and respin? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: > The LS2080ARDB is a evaluation platform that supports LS2080A > family SoCs. This patch add sbasic support for the platform. s/2080/2085/ > diff --git a/board/freescale/ls2085aqds/Makefile > b/board/freescale/ls2085ardb/Makefile > similarity index 81% > copy from board/freescale/ls2085aqds/Makefile > copy to board/freescale/ls2085ardb/Makefile > index f174f33..0bfe21c 100644 > --- a/board/freescale/ls2085aqds/Makefile > +++ b/board/freescale/ls2085ardb/Makefile > @@ -4,5 +4,5 @@ > # SPDX-License-Identifier: GPL-2.0+ > # > > -obj-y += ls2085aqds.o > +obj-y += ls2085ardb.o > obj-y += ddr.o > diff --git a/board/freescale/ls2085aqds/README > b/board/freescale/ls2085ardb/README > similarity index 73% > copy from board/freescale/ls2085aqds/README > copy to board/freescale/ls2085ardb/README > index a4d7b53..19f9d2a 100644 > --- a/board/freescale/ls2085aqds/README > +++ b/board/freescale/ls2085ardb/README > @@ -1,10 +1,8 @@ > Overview > > -The LS2080A Development System (QDS) is a high-performance computing, > +The LS2080A Reference Design (RDB) is a high-performance computing, > evaluation, and development platform that supports the QorIQ LS2080A > -LayerScape Architecture processor. The LS2080AQDS provides validation and > -SW development platform for the Freescale LS2080A processor series, with > -a complete debugging environment. > +LayerScape Architecture processor. I don't think Layerscape is supposed to be capitalized that way. > LS2085A SoC Overview > -- > @@ -50,14 +48,11 @@ The LS2085A SoC includes the following function and > features: > - Service processor (SP) provides pre-boot initialization and secure-boot >capabilities > > - LS2080AQDS board Overview > + LS2080aRDB board Overview Inconsistent capitalization > #ifndef __ASSEMBLY__ > unsigned long get_board_sys_clk(void); > -unsigned long get_board_ddr_clk(void); > #endif > > #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() > -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() > +#define CONFIG_DDR_CLK_FREQ 1 > #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) Why? > @@ -30,8 +32,8 @@ unsigned long get_board_ddr_clk(void); > #define CONFIG_MEM_INIT_VALUE0xdeadbeef > #define SPD_EEPROM_ADDRESS1 0x51 > #define SPD_EEPROM_ADDRESS2 0x52 > -#define SPD_EEPROM_ADDRESS3 0x53 > -#define SPD_EEPROM_ADDRESS4 0x54 > +#define SPD_EEPROM_ADDRESS3 0x54 > +#define SPD_EEPROM_ADDRESS4 0x53/* Bard error */ > #define SPD_EEPROM_ADDRESS5 0x55 > #define SPD_EEPROM_ADDRESS6 0x56/* dummy address */ > #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 I suspect this should be s/Bard/Board/ > @@ -114,24 +106,24 @@ unsigned long get_board_ddr_clk(void); > | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ > | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ > | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ > - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ > - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ > - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ > + | CSOR_NAND_PGS_4K /* Page Size = 2K */ \ > + | CSOR_NAND_SPRZ_224/* Spare size = 64 */ \ > + | CSOR_NAND_PB(128))/*Pages Per Block = 64*/ Comments don't match code. > @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); > #define QIXIS_LBMAP_DFLTBANK 0x00 > #define QIXIS_LBMAP_ALTBANK 0x04 > #define QIXIS_RST_CTL_RESET 0x31 > +#define QIXIS_RST_CTL_RESET_EN 0x30 > #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 > #define QIXIS_RCFG_CTL_RECONFIG_START0x21 > #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE0x08 Is this really a difference between the two boards? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/8] lpc32xx: mtd: nand: add MLC NAND controller
On Fri, 2015-03-20 at 10:35 +0100, Albert ARIBAUD wrote:
> Hi Scott,
>
> Le Thu, 19 Mar 2015 16:39:42 -0500, Scott Wood
> a écrit :
>
> > On Wed, 2015-03-18 at 10:04 +0100, Albert ARIBAUD (3ADEV) wrote:
> > > +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
> > > +{
> > > + int block_good;
> >
> > bool?
> >
> > > + struct lpc32xx_oob oob;
> > > + unsigned int page, left;
> > > +
> > > + /* if starting mid-block consider block good */
> > > + block_good = 1;
> > > +
> > > + for (page = offs / BYTES_PER_PAGE,
> > > + left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
> > > + left && (page < PAGES_PER_CHIP_MAX); page++) {
> > > + /* read inband and oob page data anyway */
> > > + int res = read_single_page(dst, page, &oob);
> > > + /* return error if a good block's page was not readable */
> > > + if ((res < 0) && block_good)
> > > + return -1;
> >
> > Why even try to read it if it's been marked bad?
>
> Actually, at this point, we may not know yet if the block is good or
> bad, since we might be reading a page of it for the first time. Will
> fix, see below.
>
> > > + /* if first page in a block, update 'block good' status */
> >
> > The non-SPL driver appears to be checking the last two pages in the
> > block, not the first page.
>
> Thanks for pointing out this discrepancy.
>
> I took the first page option here after checking the NAND's datasheet,
> which says that for factory bad block marking at least, while all pages
> in a bad block /should/ bear the bad block marker, only the first one is
> /guaranteed/ to have it. The driver might have inherited the 'last page'
> option from the previous NAND chip used, or from a mistake of my own.
Are there any plans for this controller to be used with different chips?
> BTW, is there a standard way to ask a NAND chip which page(s) in a bad
> block should be checked?
Yes and no:
http://lists.infradead.org/pipermail/linux-mtd/2011-November/038419.html
> > > + if ((page % PAGES_PER_BLOCK) == 0) {
> > > + /* assume block is good */
> > > + block_good = 1;
> > > + /* if page could not be read, assume block is bad */
> > > + if (res < 0)
> > > + block_good = 0;
> >
> > No. A block is to be skipped if and only if it has a bad block marker.
> > ECC errors should not be silently ignored just because they happen on
> > the first page of a block. If the writer of this data didn't skip the
> > block, then skipping it when reading will result in unusable data
> > regardless of the underlying ECC problem.
>
> You're correct of course.
>
> However, I do want the SPL chainloading to be as resilient as
> possible, and we have established that it will have to read some part
> of a bad block -- possibly resulting in a read failure -- before
> knowing that the block is bad, which means it may have to finally
> ignore the read failure.
FWIW, the eLBC/IFC SPL functions have the same problem regarding halting
on an ECC error before checking the bad block status. Instead it should
return an error code, and let the caller halt after it's sure it's not
marked bad.
> I guess I could wait to declare the block good or bad until I could
> read at least one if its pages (actually, one of its pages' OOB data)
> properly, only bail out if the OOB says the block is supposed to be
> good.
>
> Now, if none of the block's pages could be read, this still prevents us
> from knowing whether these read failures are catastrophic.
>
> If the block was actually bad and skipped, then the resulting image
> might be intact, will pass the checksum test, and will run; if the
> block was actually good, SPL will detect it and not boot the corrupt
> image -- except if the completely unreadable good block was the first
> one, which holds the signature and checksum, in which case SPL will
> fall back to considering a raw, unsigned, unverifiable image, and will
> jump into corrupt code.
>
> This may happen; but I think the probability of having a completely
> unreadable sector is very low, and the probability of this sector being
> the first one of the image is very low too [1].
>
> Which leads me to two possible courses of action:
>
> - consider the risk even though the probabilities are very low, thus
> consider any totally unreadable sector as good, and bail out in this
> case, or
I was thinking instead to distinguish between a hard failure where you
got no data from the NAND (e.g. a timeout), versus an ECC failure. In
the later case you can still look in the OOB for a bad block marker.
> - add an option to SPL that prevents common/spl/spl.c from falling back
> to running the image as raw if no signature is found, and consider
> any totally unreadable sector as bad and therefore ignore the read
> errors. Either the sector was actually good, and SPL will catch the
> image as corrupt or missing a signature
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote: > > On 03/20/2015 02:15 PM, Scott Wood wrote: > > On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote: > >> From: Scott Wood > >> > >> This adds NAND boot support for LS2085AQDS, using SPL framework. > >> > >> To form a NAND image, append u-boot-with-spl.bin after a proper > >> nand boot RCW and flash to the beginning of NAND. > > > > Do we want to do it this way, or should we keep the RCW in a separate > > block? > > I would like to see RCW in a separated block. OK. In that case the offsets in this patch will need to change. > > What constitutes a "proper nand boot RCW" (those were not my words)? > > There are details in this patch regarding offsets that need to match > > details in the PBI (which is more than just RCW). > > It is not your original words. Yours was "To form a NAND image, append > u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the > beginning > of NAND.". I try to make the message generic. A proper nand boot RCW means the > RCW should contains PBI commands to set bootloc and block copy the image. > Since > RCW is not in the scope of u-boot, I cannot refer to any specific file. Yes, I know you can't refer to the file, but it needs to be made clear what the expectations of that PBI file are. > Do you want to include an RCW file into u-boot, like those for powerpc boards? Not really. I'd rather have rcw.git published for all use cases (like http://git.freescale.com/git/cgit.cgi/layerscape/ls1021a/rcw.git/ but updated for ls2085a and without the repository being chip-specific (at least in name)). On PPC we had to have U-Boot do it because the U-Boot image itself had to be encoded in the PBI. That thankfully isn't the case here. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote: > On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote: > > [snip] > > It would also be nice to sort out loading the environment during SPL. > > *ears perk up*. Please elaborate :) We have SPL environment support, > we have SPL NAND Environment support today. It doesn't get passed along > to the running U-Boot and it's used for some limited cases (network and > redundancy). I'd like to hear about more and better ways of using it. In common/spl/spl_nand.c, why does it only load the environment when CONFIG_NAND_ENV_DST is defined, yet it never uses the value of CONFIG_NAND_ENV_DST? I also don't see any boards definind CONFIG_NAND_ENV_DST (apparently the only one that ever used it was smdk6400 which has been removed). Is there some other way that the environment is supposed to be getting loaded from NAND (rather than using the default environment) during SPL? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On 03/20/2015 02:33 PM, Scott Wood wrote: > On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote: >> >> On 03/20/2015 02:15 PM, Scott Wood wrote: >>> On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote: From: Scott Wood This adds NAND boot support for LS2085AQDS, using SPL framework. To form a NAND image, append u-boot-with-spl.bin after a proper nand boot RCW and flash to the beginning of NAND. >>> >>> Do we want to do it this way, or should we keep the RCW in a separate >>> block? >> >> I would like to see RCW in a separated block. > > OK. In that case the offsets in this patch will need to change. > >>> What constitutes a "proper nand boot RCW" (those were not my words)? >>> There are details in this patch regarding offsets that need to match >>> details in the PBI (which is more than just RCW). >> >> It is not your original words. Yours was "To form a NAND image, append >> u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the >> beginning >> of NAND.". I try to make the message generic. A proper nand boot RCW means >> the >> RCW should contains PBI commands to set bootloc and block copy the image. >> Since >> RCW is not in the scope of u-boot, I cannot refer to any specific file. > > Yes, I know you can't refer to the file, but it needs to be made clear > what the expectations of that PBI file are. I think a proper solution would be to put detail instruction into board README file by adding To form the NAND image, append u-boot-with-spl.bin after RCW image. The RCW image should have these PBI commands CCSR 4-byte write to 0x00e00404, data=0x CCSR 4-byte write to 0x00e00400, data=0x1800a000 Block Copy: SRC=0x0104, SRC_ADDR=0x00c0, DEST_ADDR=0x1800a000, BLOCK_SIZE=0x00014000 We need to revise the SRS_ADDR if moving u-boot to a separated block. Please advise what address is appropriate. Please also advise the BLOCK_SIZE. Does it need to be fixed, or min(0x14000, sizeof(u-boot-spl.bin))? > >> Do you want to include an RCW file into u-boot, like those for powerpc >> boards? > > Not really. I'd rather have rcw.git published for all use cases (like > http://git.freescale.com/git/cgit.cgi/layerscape/ls1021a/rcw.git/ but > updated for ls2085a and without the repository being chip-specific (at > least in name)). > > On PPC we had to have U-Boot do it because the U-Boot image itself had > to be encoded in the PBI. That thankfully isn't the case here. This is good. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote: [snip] > It would also be nice to sort out loading the environment during SPL. *ears perk up*. Please elaborate :) We have SPL environment support, we have SPL NAND Environment support today. It doesn't get passed along to the running U-Boot and it's used for some limited cases (network and redundancy). I'd like to hear about more and better ways of using it. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On 03/20/2015 02:15 PM, Scott Wood wrote: > On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote: >> From: Scott Wood >> >> This adds NAND boot support for LS2085AQDS, using SPL framework. >> >> To form a NAND image, append u-boot-with-spl.bin after a proper >> nand boot RCW and flash to the beginning of NAND. > > Do we want to do it this way, or should we keep the RCW in a separate > block? I would like to see RCW in a separated block. > > What constitutes a "proper nand boot RCW" (those were not my words)? > There are details in this patch regarding offsets that need to match > details in the PBI (which is more than just RCW). It is not your original words. Yours was "To form a NAND image, append u-boot-with-spl.bin after PBL_0x3_0x07_1333_nand.bin and flash to the beginning of NAND.". I try to make the message generic. A proper nand boot RCW means the RCW should contains PBI commands to set bootloc and block copy the image. Since RCW is not in the scope of u-boot, I cannot refer to any specific file. Do you want to include an RCW file into u-boot, like those for powerpc boards? > > It would also be nice to sort out loading the environment during SPL. That can be an additional patch when you have it. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote: > From: Scott Wood > > This adds NAND boot support for LS2085AQDS, using SPL framework. > > To form a NAND image, append u-boot-with-spl.bin after a proper > nand boot RCW and flash to the beginning of NAND. Do we want to do it this way, or should we keep the RCW in a separate block? What constitutes a "proper nand boot RCW" (those were not my words)? There are details in this patch regarding offsets that need to match details in the PBI (which is more than just RCW). It would also be nice to sort out loading the environment during SPL. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] x86: Add Intel Topcliff PCH Gigabit Ethernet support
Hi Joe, On 20 March 2015 at 13:18, Joe Hershberger wrote: > Hi Simon, > > On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote: >> >> This series adds a new ethernet driver for the GMAC found on Intel >> Topcliff >> Platform Controller Hub and enable its support on Intel Crown Bay board. >> >> The series also did some clean up work below: >> - Introduce ETH_FCS_LEN macro as it is often used by some ethernet drivers >> - Remove any local version of ETH_FCS_LEN from various places >> - Update README.drivers.eth for up-to-date mdio APIs >> >> >> Bin Meng (4): >> net: Add ethernet FCS length macro in net.h >> net: Update README.drivers.eth to mention latest APIs >> net: Add Intel Topcliff GMAC driver >> x86: crownbay: Enable Intel Topcliff GMAC support > > I assume it is preferable to pull this through the x86 tree. Let me know > either way. Yes, will do. But I suspect it should be converted to driver model. Let's see. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Serial number support, obtained from SID bits and passed through ATAG
Hi,
Thanks for the patch, I've 1 comment inline, please send
a version with that fixed then I'll queue it up for merging upstream.
On 18-03-15 20:46, Paul Kocialkowski wrote:
Signed-off-by: Paul Kocialkowski
---
board/sunxi/board.c| 33 ++---
include/configs/sunxi-common.h | 1 +
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index becdc8b..0355de5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -248,13 +248,34 @@ int g_dnl_board_usb_cable_connected(void)
}
#endif
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial_string = getenv("serial#");
+ unsigned long long serial;
+
+ if (serial_string) {
+ serial = simple_strtoull(serial_string, NULL, 16);
+
+ serialnr->high = (unsigned int) (serial >> 32);
+ serialnr->low = (unsigned int) (serial & 0x);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
+
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
- unsigned int sid[4];
+ char serial_string[17] = { 0 };
+ unsigned int sid[4] = { 0 };
+ int ret;
+
+ ret = sunxi_get_sid(sid);
- if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 &&
- sid[0] != 0 && sid[3] != 0) {
+ if (!getenv("ethaddr") && ret == 0 && sid[0] != 0 && sid[3] != 0) {
uint8_t mac_addr[6];
mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
@@ -267,6 +288,12 @@ int misc_init_r(void)
eth_setenv_enetaddr("ethaddr", mac_addr);
}
You should check for get_sid succeeding before calling snprintf, also since
your buffer is always large enough, there is no need to use or error check
snprintf, and last you should check for serial# not already being set so that
the user can override it if he wants.
+ ret = snprintf(serial_string, sizeof(serial_string), "%08x%08x",
+ sid[0], sid[3]);
+
+ if (ret > 0)
+ setenv("serial#", serial_string);
+
IOW, you should replace the above with:
if (!getenv("serial#") && ret == 0) {
sprintf(serial_string, "%08x%08x", sid[0], sid[3]);
setenv("serial#", serial_string);
}
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
#endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ffd9f5c..61a45e1 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -98,6 +98,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
/* mmc config */
#if !defined(CONFIG_UART0_PORT_F)
Otherwise this looks good.
Regards,
Hans
p.s.
A quick grep on serial# shows the following:
board/gateworks/gw_ventana/gw_ventana.c
1202: * serial# env var
1207: char *serial = getenv("serial#");
1432: setenv("serial#", str);
1512: fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1513: strlen(getenv("serial#")) + 1);
Which may be used as an example for devicetree support, or not,
the first thing to do would be to write a
Documentation/devicetree/bindings/system-serial.txt
patch for the kernel and send that to the devicetree list for
review, once that is accepted we can actually start implementing
it.
Regards,
Hans
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[U-Boot] [PATCH v4 26/28] armv8/ls2085ardb: Enable NAND SPL support
From: Scott Wood
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command.
Signed-off-by: Scott Wood
Singed-off-by: York Sun
---
Changes in v4:
Update MAINTAINERS file
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig |1 +
board/freescale/ls2085ardb/MAINTAINERS |1 +
board/freescale/ls2085ardb/ddr.c |4
configs/ls2085ardb_nand_defconfig |4
include/configs/ls2085ardb.h | 40
5 files changed, 45 insertions(+), 5 deletions(-)
create mode 100644 configs/ls2085ardb_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 46a48a0..7cbbf37 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config TARGET_LS2085ARDB
bool "Support ls2085ardb"
select ARM64
select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
help
Support for Freescale LS2085ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
diff --git a/board/freescale/ls2085ardb/MAINTAINERS
b/board/freescale/ls2085ardb/MAINTAINERS
index 436039f..d5cce40 100644
--- a/board/freescale/ls2085ardb/MAINTAINERS
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/freescale/ls2085ardb/
F: board/freescale/ls2085a/ls2085ardb.c
F: include/configs/ls2085ardb.h
F: configs/ls2085ardb_defconfig
+F: configs/ls2085ardb_nand_defconfig
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
index 6cd5e8b..8d71ae1 100644
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2085ardb/ddr.c
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
puts("Initializing DDRusing SPD\n");
dram_size = fsl_ddr_sdram();
+#endif
return dram_size;
}
diff --git a/configs/ls2085ardb_nand_defconfig
b/configs/ls2085ardb_nand_defconfig
new file mode 100644
index 000..39ba8c5
--- /dev/null
+++ b/configs/ls2085ardb_nand_defconfig
@@ -0,0 +1,4 @@
++S:CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
++S:CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085ARDB=y
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 24400e4..34aa3e5 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK0x04
+#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_RST_CTL_RESET0x31
#define QIXIS_RST_CTL_RESET_EN 0x30
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RCW_SRC_NAND 0x119
#defineQIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
@@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void);
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1536 * 1024)
+#define CONFIG_ENV_SECT_SIZE 0x2
+#define CONFIG_ENV_SIZE0x2000
+#define CONFIG_SPL_PAD_TO 0x7ff40
+#define CONFIG_SYS_NAND_U_BOOT_OFFS(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
@@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void)
[U-Boot] [PATCH v4 04/28] armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun
CC: Mark Rutland
---
Changes in v4:
Remove temporary variable cntfrq.
Changes in v3:
Move secondary core fix to mp.c.
Replace hard-coded value with COUNTER_FREQUENCY.
Changes in v2:
Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.
README |8
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |6 ++
arch/arm/cpu/armv8/fsl-lsch3/mp.c |7 +++
arch/arm/cpu/armv8/fsl-lsch3/mp.h |1 +
board/freescale/ls2085a/ls2085a.c | 18 --
include/configs/ls2085a_common.h|6 +-
7 files changed, 51 insertions(+), 19 deletions(-)
diff --git a/README b/README
index e710226..f063a74 100644
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
+
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
+
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd147..e985181 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
return 0;
}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+ unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+ /* Enable timebase for all clusters.
+* It is safe to do so even some clusters are not enabled.
+*/
+ out_le32(cltbenr, 0xf);
+
+ /* Enable clock for timer
+* This is a global setting.
+*/
+ out_le32(cntcr, 0x1);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 886576e..53bdb44 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -224,6 +224,9 @@ ENTRY(secondary_boot_func)
/* physical address of this cpus spin table element */
add x11, x1, x0
+ ldr x0, =__real_cntfrq
+ ldr x0, [x0]
+ msr cntfrq_el0, x0 /* set with real frequency */
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
@@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1)
/* 64 bit alignment for elements accessed as data */
.align 4
+ .global __real_cntfrq
+__real_cntfrq:
+ .quad COUNTER_FREQUENCY
.globl __secondary_boot_code_size
.type __secondary_boot_code_size, %object
/* Secondary Boot Code ends here */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index ce9c0c1..da7853a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void)
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
+#ifdef COUNTER_FREQUENCY_REAL
+ /* update for secondary cores */
+ __real_cntfrq = COUNTER_FREQUENCY_REAL;
+ flush_dcache_range((unsigned long)&__real_cntfrq,
+ (unsigned long)&__real_cntfrq + 8);
+#endif
+
cores = cpu_mask();
/* Clear spin table so that secondary processors
* observe the correct value after waking up from wfe.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 66144d6..c985d6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -26,6 +26,7 @@
#define id_to_core(x) ((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
extern u64 __spin_table[];
+extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
int fsl_lsch3_wake_seconday_cores(void);
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board/freescale/ls2085a/l
[U-Boot] [PATCH v4 24/28] armv8/ls2085aqds: NAND boot support
From: Scott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper
nand boot RCW and flash to the beginning of NAND.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v4:
Update MAINTAINERS file
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig |1 +
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 48
arch/arm/cpu/armv8/u-boot-spl.lds| 77 ++
arch/arm/include/asm/arch-fsl-lsch3/config.h |9 +++
arch/arm/lib/crt0_64.S |7 +++
board/freescale/ls2085aqds/MAINTAINERS |1 +
board/freescale/ls2085aqds/ddr.c |4 ++
common/spl/spl.c |2 +-
common/spl/spl_nand.c|2 +-
configs/ls2085aqds_nand_defconfig|4 ++
drivers/misc/fsl_ifc.c | 12
drivers/mtd/nand/fsl_ifc_spl.c |2 +-
include/configs/ls2085a_common.h | 29 ++
include/configs/ls2085aqds.h | 50 +++--
14 files changed, 240 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds
create mode 100644 configs/ls2085aqds_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7478eb4..46a48a0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
bool "Support ls2085aqds"
select ARM64
select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
help
Support for Freescale LS2085AQDS platform
The LS2085A Development System (QDS) is a high-performance
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 17700ef..ca00108 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -6,8 +6,13 @@
#include
#include
+#include
+#include
#include
#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
static void erratum_a008751(void)
{
@@ -18,8 +23,51 @@ static void erratum_a008751(void)
#endif
}
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+ u32 val;
+
+ val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+ val &= ~DCFG_PORSR1_RCW_SRC;
+ val |= DCFG_PORSR1_RCW_SRC_NOR;
+ out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
+ erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+ board_early_init_f();
+ timer_init();
+ env_init();
+ gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+
+ serial_init();
+ console_init_f();
+ dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
new file mode 100644
index 000..4df339c
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2013
+ * David Feng
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * (C) Copyright 2010
+ * Texas Instruments,
+ * Aneesh V
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64",
"elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ .text : {
+ . = ALIGN(8);
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ .rodata : {
+ . = ALIGN(8);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } >.sram
+
+ .data : {
+ . = ALIGN(8);
+ *(.data*)
+ } >.sram
+
+ .u_boot_list : {
+ . = ALIGN(8);
+ KEEP(*(SORT(.u_boot_list*)));
+ } >.sram
+
+ .image_copy_end : {
+ . = ALIGN(8);
+ *(.__image_copy_end)
+ } >.sram
+
+ .end : {
+ . = ALIGN(8);
+ *(.__end)
+ } >.sram
+
+ .bss_start : {
+ . = ALIGN(8);
+ KEEP(*(.__bss_start));
+ } >.sdram
+
+ .bss : {
+ *(.bss*)
+
Re: [U-Boot] [PATCH 4/4] x86: crownbay: Enable Intel Topcliff GMAC support
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote: > > Intel Crown Bay board has one ethernet port connected from Intel > Topcliff PCH. Enable it in the board configuration. > > Signed-off-by: Bin Meng > > --- Reviewed-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] net: Add Intel Topcliff GMAC driver
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote: > > Add a new driver for the Gigabit Ethernet MAC found on Intel Topcliff > Platform Controller Hub. Tested under 10/100 half/full duplex and 1000 > full duplex modes using ping and tftpboot commands. > > Signed-off-by: Bin Meng > --- Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] net: Update README.drivers.eth to mention latest APIs
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote: > > README.drivers.eth still refers to the deprecated miiphy_register(). > Update the doc to mention new APIs mdio_alloc() and mdio_register(). > > Signed-off-by: Bin Meng > --- Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] net: Add ethernet FCS length macro in net.h
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote: > > Some ethernet drivers use their own version of ethernet FCS length > macro which is really common. We define ETH_FCS_LEN in net.h and > replace those custom versions in various places. > > Signed-off-by: Bin Meng > --- Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] x86: Add Intel Topcliff PCH Gigabit Ethernet support
Hi Simon, On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote: > > This series adds a new ethernet driver for the GMAC found on Intel Topcliff > Platform Controller Hub and enable its support on Intel Crown Bay board. > > The series also did some clean up work below: > - Introduce ETH_FCS_LEN macro as it is often used by some ethernet drivers > - Remove any local version of ETH_FCS_LEN from various places > - Update README.drivers.eth for up-to-date mdio APIs > > > Bin Meng (4): > net: Add ethernet FCS length macro in net.h > net: Update README.drivers.eth to mention latest APIs > net: Add Intel Topcliff GMAC driver > x86: crownbay: Enable Intel Topcliff GMAC support I assume it is preferable to pull this through the x86 tree. Let me know either way. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 04/28] armv8/ls2085a: Fix generic timer clock source
On 03/20/2015 11:29 AM, Mark Rutland wrote: >> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c >> b/arch/arm/cpu/armv8/fsl-lsch3/mp.c >> index ce9c0c1..5338fe6 100644 >> --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c >> +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c >> @@ -30,6 +30,13 @@ int fsl_lsch3_wake_seconday_cores(void) >> u32 cores, cpu_up_mask = 1; >> int i, timeout = 10; >> u64 *table = get_spin_tbl_addr(); >> +#ifdef COUNTER_FREQUENCY_REAL >> +unsigned long cntfrq = COUNTER_FREQUENCY_REAL; >> + >> +__real_cntfrq = cntfrq; /* update for secondary cores */ > > Do you need the temporary cntfrq variable? Can't you just have: > > __real_cntfrq = COUNTER_FREQUENCY_REAL; Yes, I can. It was cut and paste. I will fix it. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] mmc: Continue polling MMC card for OCR only if it is still not ready
On 3/19/2015 6:51 PM, peng@freescale.com wrote:
> Hi, Andrew
>
> There is already a patch to fix this issue.
> Patchwork: https://patchwork.ozlabs.org/patch/451775/
>
> Regards,
> Peng.
>
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Andrew
> Gabbasov
> Sent: Thursday, March 19, 2015 8:44 PM
> To: u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH 4/6] mmc: Continue polling MMC card for OCR only if
> it is still not ready
>
> Some MMC cards come to ready state quite quickly, so that the respective flag
> appears to be set in mmc_send_op_cond already. In this case trying to
> continue polling the card with CMD1 in mmc_complete_op_cond is incorrect and
> may lead to unpredictable results. So check the flag before polling and skip
> it appropriately.
>
> Signed-off-by: Andrew Gabbasov
> ---
> drivers/mmc/mmc.c | 20 +++-
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d073d79..42af47c
> 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -403,15 +403,17 @@ static int mmc_complete_op_cond(struct mmc *mmc)
> int err;
>
> mmc->op_cond_pending = 0;
> - start = get_timer(0);
> - do {
> - err = mmc_send_op_cond_iter(mmc, 1);
> - if (err)
> - return err;
> - if (get_timer(start) > timeout)
> - return UNUSABLE_ERR;
> - udelay(100);
> - } while (!(mmc->ocr & OCR_BUSY));
> + if (!(mmc->ocr & OCR_BUSY)) {
> + start = get_timer(0);
> + do {
> + err = mmc_send_op_cond_iter(mmc, 1);
> + if (err)
> + return err;
> + if (get_timer(start) > timeout)
> + return UNUSABLE_ERR;
> + udelay(100);
> + } while (!(mmc->ocr & OCR_BUSY));
> + }
>
> if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
> cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
> --
Here's another patch that solves the problem a little earlier. It has this
disadvantage of being
slightly bigger,
though it makes the code look better.
https://github.com/boundarydevices/u-boot-imx6/commit/c0260ca
I'll ack any version as they all seem to solve the problem.
Troy
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Re: [U-Boot] [PATCH 06/13] net: rtl8169: Build warning fixes for 64-bit
Hi Thierry, On Fri, Mar 20, 2015 at 6:41 AM, Thierry Reding wrote: > > From: Thierry Reding > > Turn ioaddr into an unsigned long rather than a sized 32-bit variable. > While at it, fix a couple of pointer to integer cast size mismatch > warnings by casting through unsigned long going from pointers to > integers and vice versa. > > Cc: Joe Hershberger > Signed-off-by: Thierry Reding Fixed checkpatch failures and applied to next, thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 04/28] armv8/ls2085a: Fix generic timer clock source
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c > b/arch/arm/cpu/armv8/fsl-lsch3/mp.c > index ce9c0c1..5338fe6 100644 > --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c > +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c > @@ -30,6 +30,13 @@ int fsl_lsch3_wake_seconday_cores(void) > u32 cores, cpu_up_mask = 1; > int i, timeout = 10; > u64 *table = get_spin_tbl_addr(); > +#ifdef COUNTER_FREQUENCY_REAL > + unsigned long cntfrq = COUNTER_FREQUENCY_REAL; > + > + __real_cntfrq = cntfrq; /* update for secondary cores */ Do you need the temporary cntfrq variable? Can't you just have: __real_cntfrq = COUNTER_FREQUENCY_REAL; > + flush_dcache_range((unsigned long)&__real_cntfrq, > +(unsigned long)&__real_cntfrq + 8); This looks fine, as does the rest of the patch. So either way: Acked-by: Mark Rutland Thanks, Mark. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/6] ARM: tegra: Disable SPL and non-cached memory on 64-bit
On 03/20/2015 11:09 AM, Tom Rini wrote: On Fri, Mar 20, 2015 at 10:26:12AM -0600, Stephen Warren wrote: On 03/20/2015 06:24 AM, Thierry Reding wrote: From: Thierry Reding For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in AArch64 mode so that we don't need the SPL. Non-cached memory is not implemented (yet) for 64-bit ARM. diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h +#ifndef CONFIG_ARM64 #ifndef CONFIG_SPL_BUILD #define CONFIG_USE_ARCH_MEMCPY #endif +#endif We don't need SPL, but that stanza used to enable ARCH_MEMCPY *except* for SPL. I would expect we still want ARCH_MEMCPY on ARM64, where presumably ifndef CONFIG_SPL_BUILD will always be true? First we need arch memcpy/memset for aarch64 copied over (and maybe update the 32bit one and get everyone using them). Oh, that's missing? OK, it makes sense to disable it. However, the commit description probably shouldn't imply this is related to having SPL or not, but rather that ARM64 doesn't support ARCH_MEMCPY yet? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 04/28] armv8/ls2085a: Fix generic timer clock source
> >> +int timer_init(void)
> >> +{
> >> + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> >> + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
> >> +#ifdef COUNTER_FREQUENCY_REAL
> >> + unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
> >> +
> >> + /* Update with accurate clock frequency */
> >> + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
> >
> > The commit message says that this can only be determined at runtime, but
> > this looks like we're writing a compile-time static value.
> >
>
> The macro COUNTER_FREQUENCY_REA is (CONFIG_SYS_CLK_FREQ/4), where
> CONFIG_SYS_CLK_FREQ is a function call get_board_sys_clk().
Ah, that sounds fine to me then.
> >> + __real_cntfrq = cntfrq; /* update for secondary cores */
> >
> > Do we need anything in the way or barriers and/or cache flushing to
> > ensure that this is visible to the secondary CPUs? Or is the MMU off at
> > this point?
>
> It is flushed before booting secondary cores. But I am relying on the trick of
> enabling cache on flash. It may not be as reliable if someone decide to
> disable
> the cache to begin with. I will move the code to somewhere safe in next
> version.
Ok.
> >> + .global __real_cntfrq
> >> +__real_cntfrq:
> >> + .quad 0x17d7840 /* 25MHz */
> >
> > I think this would be better as COUNTER_FREQUENCY, so as to avoid
> > duplicating the value.
>
> Good idea. Will fix in next version.
Great!
Mark.
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Re: [U-Boot] [PATCH 6/6] armv8: Allow SoCs to override the generic timer
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> Some SoCs come with a custom timer interface, so allow them to use that
> instead.
>
> Cc: Albert Aribaud
> Cc: Marc Zyngier
> Signed-off-by: Thierry Reding
> ---
> arch/arm/cpu/armv8/generic_timer.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/generic_timer.c
> b/arch/arm/cpu/armv8/generic_timer.c
> index 223b95e210ed..ab8573fc7cef 100644
> --- a/arch/arm/cpu/armv8/generic_timer.c
> +++ b/arch/arm/cpu/armv8/generic_timer.c
> @@ -9,6 +9,7 @@
> #include
> #include
>
> +#ifndef CONFIG_SYS_TIMER_COUNTER
> /*
> * Generic timer implementation of get_tbclk()
> */
> @@ -29,3 +30,4 @@ unsigned long timer_read_counter(void)
> asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
> return cntpct;
> }
> +#endif
>
Does it mean that in this case, the generic timers are not in a working
state? For ARMv8, it would make a lot more sense to make sure that the
basic CPU stuff is actually in a working state, and avoid the madness
that we have on ARMv7...
Thanks,
M.
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Re: [U-Boot] [PATCH 4/6] armv8/mmu: Set bits marked RES1 in TCR
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
> but should be written as 1.
>
> For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
>
> Cc: Albert Aribaud
> Cc: Marc Zyngier
> Signed-off-by: Thierry Reding
> ---
> arch/arm/cpu/armv8/cache_v8.c| 6 +++---
> arch/arm/include/asm/armv8/mmu.h | 4
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 254a629a3b8c..f9b04057f696 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -50,15 +50,15 @@ static void mmu_setup(void)
> el = current_el();
> if (el == 1) {
> set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> - TCR_FLAGS | TCR_EL1_IPS_BITS,
> + TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
> MEMORY_ATTRIBUTES);
> } else if (el == 2) {
> set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> - TCR_FLAGS | TCR_EL2_IPS_BITS,
> + TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
> MEMORY_ATTRIBUTES);
> } else {
> set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
> - TCR_FLAGS | TCR_EL3_IPS_BITS,
> + TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
> MEMORY_ATTRIBUTES);
> }
> /* enable the mmu */
> diff --git a/arch/arm/include/asm/armv8/mmu.h
> b/arch/arm/include/asm/armv8/mmu.h
> index 6d42f5533a74..8e577b34e4ba 100644
> --- a/arch/arm/include/asm/armv8/mmu.h
> +++ b/arch/arm/include/asm/armv8/mmu.h
> @@ -109,6 +109,10 @@
> TCR_IRGN_WBWA | \
> TCR_T0SZ(VA_BITS))
>
> +#define TCR_EL1_RSVD (1 << 31)
> +#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
> +#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
> +
> #ifndef __ASSEMBLY__
> void set_pgtable_section(u64 *page_table, u64 index,
>u64 section, u64 memory_type);
>
Acked-by: Marc Zyngier
M.
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Re: [U-Boot] [PATCH] net/phy/realtek: Disable interrupt on Realtek Ethernet PHY drivers
Hi Codrin, On Wed, Mar 4, 2015 at 2:46 AM, Codrin Constantin Ciubotariu < codrin.ciubota...@freescale.com> wrote: > > Hi, > > Anyone has any comments on this? Please share your thoughts. Looks good to me. > > -Original Message- > > From: Codrin Ciubotariu [mailto:codrin.ciubota...@freescale.com] > > Sent: Friday, February 13, 2015 2:48 PM > > To: u-boot@lists.denx.de > > Cc: Sun York-R58495; Ciubotariu Codrin Constantin-B43658 > > Subject: [PATCH] net/phy/realtek: Disable interrupt on Realtek Ethernet PHY > > drivers > > > > Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have interrupts > > enabled by default. If the interrupt is not treated later by the OS and the > > PHY's interrupt line is enabled and shared with other interrupts, the system > > will get an interrupt storm. > > This patch disables the interrupt for PHY devices that use one of the current > > Realtek Ethernet PHY drivers. > > Some of Realtek Ethernet PHYs, such as RTL8211B(L) have the interrupt masked. In > > this case, the functionality of the PHY should not be afected since this patch > > brings INER and INSR registers to their default values. > > > > Signed-off-by: Codrin Ciubotariu > > Change-Id: Ic5e353da24f8fec335e446098ed863991a64 Applied to next, Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 04/28] armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun
CC: Mark Rutland
---
Changes in v3:
Move secondary core fix to mp.c.
Replace hard-coded value with COUNTER_FREQUENCY.
Changes in v2:
Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined.
README |8
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |6 ++
arch/arm/cpu/armv8/fsl-lsch3/mp.c |7 +++
arch/arm/cpu/armv8/fsl-lsch3/mp.h |1 +
board/freescale/ls2085a/ls2085a.c | 18 --
include/configs/ls2085a_common.h|6 +-
7 files changed, 51 insertions(+), 19 deletions(-)
diff --git a/README b/README
index e710226..f063a74 100644
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
+
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
+
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd147..e985181 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
return 0;
}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+ unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+ /* Enable timebase for all clusters.
+* It is safe to do so even some clusters are not enabled.
+*/
+ out_le32(cltbenr, 0xf);
+
+ /* Enable clock for timer
+* This is a global setting.
+*/
+ out_le32(cntcr, 0x1);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 886576e..53bdb44 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -224,6 +224,9 @@ ENTRY(secondary_boot_func)
/* physical address of this cpus spin table element */
add x11, x1, x0
+ ldr x0, =__real_cntfrq
+ ldr x0, [x0]
+ msr cntfrq_el0, x0 /* set with real frequency */
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
@@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1)
/* 64 bit alignment for elements accessed as data */
.align 4
+ .global __real_cntfrq
+__real_cntfrq:
+ .quad COUNTER_FREQUENCY
.globl __secondary_boot_code_size
.type __secondary_boot_code_size, %object
/* Secondary Boot Code ends here */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index ce9c0c1..5338fe6 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -30,6 +30,13 @@ int fsl_lsch3_wake_seconday_cores(void)
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
+#ifdef COUNTER_FREQUENCY_REAL
+ unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+ __real_cntfrq = cntfrq; /* update for secondary cores */
+ flush_dcache_range((unsigned long)&__real_cntfrq,
+ (unsigned long)&__real_cntfrq + 8);
+#endif
cores = cpu_mask();
/* Clear spin table so that secondary processors
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 66144d6..c985d6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -26,6 +26,7 @@
#define id_to_core(x) ((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
extern u64 __spin_table[];
+extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
int fsl_lsch3_wake_seconday_cores(void);
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
Re: [U-Boot] [PATCH 3/6] armv8/mmu: Clean up TCR programming
On 20/03/15 11:47, Thierry Reding wrote: > From: Thierry Reding > > Use the inner shareable attribute for memory, which makes more sense > considering that this code is called when caches are being enabled. > > While at it, fix the values for the shareability attribute field to > match the documentation. > > Cc: Albert Aribaud > Cc: Marc Zyngier > Signed-off-by: Thierry Reding > --- > arch/arm/include/asm/armv8/mmu.h | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/include/asm/armv8/mmu.h > b/arch/arm/include/asm/armv8/mmu.h > index 4b9cb5296572..6d42f5533a74 100644 > --- a/arch/arm/include/asm/armv8/mmu.h > +++ b/arch/arm/include/asm/armv8/mmu.h > @@ -93,8 +93,8 @@ > #define TCR_ORGN_WBNWA (3 << 10) > #define TCR_ORGN_MASK(3 << 10) > #define TCR_SHARED_NON (0 << 12) > -#define TCR_SHARED_OUTER (1 << 12) > -#define TCR_SHARED_INNER (2 << 12) > +#define TCR_SHARED_OUTER (2 << 12) > +#define TCR_SHARED_INNER (3 << 12) > #define TCR_TG0_4K (0 << 14) > #define TCR_TG0_64K (1 << 14) > #define TCR_TG0_16K (2 << 14) > @@ -102,9 +102,9 @@ > #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ > #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ > > -/* PTWs cacheable, inner/outer WBWA and non-shareable */ > +/* PTWs cacheable, inner/outer WBWA and inner shareable */ > #define TCR_FLAGS(TCR_TG0_64K | \ > - TCR_SHARED_NON |\ > + TCR_SHARED_INNER | \ > TCR_ORGN_WBWA | \ > TCR_IRGN_WBWA | \ > TCR_T0SZ(VA_BITS)) > Acked-by: Marc Zyngier One thing though: the architecture doesn't mandate 64k pages to be implemented by the HW. Actually, it doesn't mandate any particular page size, you just have to implement at least one (4k, 16k or 64k). It would be good to test if 64k pages are implemented (by testing ID_AA64MMFR0_EL1) and not try to enable caches if not, possibly displaying a warning for the unsuspecting u-boot hacker. Thanks, M. -- Jazz is not dead. It just smells funny... ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] armv8/cache: Fix page table creation
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> While generating the page tables, a running integer index is shifted by
> SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
> The page tables therefore alias to the same 8 sections and cause U-Boot
> to hang once the MMU is enabled.
>
> Fix this by making the index a 64-bit unsigned integer and so avoid the
> overflow.
>
> Cc: Albert Aribaud
> Cc: Marc Zyngier
> Signed-off-by: Thierry Reding
Acked-by: Marc Zyngier
> ---
> arch/arm/cpu/armv8/cache_v8.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index c5ec5297cd39..254a629a3b8c 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -25,9 +25,9 @@ void set_pgtable_section(u64 *page_table, u64 index, u64
> section,
> /* to activate the MMU we need to set up virtual memory */
> static void mmu_setup(void)
> {
> - int i, j, el;
> bd_t *bd = gd->bd;
> - u64 *page_table = (u64 *)gd->arch.tlb_addr;
> + u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
> + int el;
>
> /* Setup an identity-mapping for all spaces */
> for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
>
--
Jazz is not dead. It just smells funny...
___
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