[U-Boot] [PATCH v2] gpio: lpc32xx: Use priv_data instead of platdata
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin axel@ingics.com
---
v2: Update commit log to mention that using priv_data for runtime state
which was stored in platdata.
drivers/gpio/lpc32xx_gpio.c | 39 +++
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
index 96b3125..8a9826e 100644
--- a/drivers/gpio/lpc32xx_gpio.c
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -37,7 +37,7 @@
#define LPC32XX_GPIOS 128
-struct lpc32xx_gpio_platdata {
+struct lpc32xx_gpio_priv {
struct gpio_regs *regs;
/* GPIO FUNCTION: SEE WARNING #2 */
signed char function[LPC32XX_GPIOS];
@@ -60,8 +60,8 @@ struct lpc32xx_gpio_platdata {
static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata-regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv-regs;
port = GPIO_TO_PORT(offset);
mask = GPIO_TO_MASK(offset);
@@ -83,7 +83,7 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev,
unsigned offset)
}
/* GPIO FUNCTION: SEE WARNING #2 */
- gpio_platdata-function[offset] = GPIOF_INPUT;
+ gpio_priv-function[offset] = GPIOF_INPUT;
return 0;
}
@@ -95,8 +95,8 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev,
unsigned offset)
static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
{
int port, rank, mask, value;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata-regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv-regs;
port = GPIO_TO_PORT(offset);
@@ -130,8 +130,8 @@ static int lpc32xx_gpio_get_value(struct udevice *dev,
unsigned offset)
static int gpio_set(struct udevice *dev, unsigned gpio)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata-regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv-regs;
port = GPIO_TO_PORT(gpio);
mask = GPIO_TO_MASK(gpio);
@@ -162,8 +162,8 @@ static int gpio_set(struct udevice *dev, unsigned gpio)
static int gpio_clr(struct udevice *dev, unsigned gpio)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata-regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv-regs;
port = GPIO_TO_PORT(gpio);
mask = GPIO_TO_MASK(gpio);
@@ -208,8 +208,8 @@ static int lpc32xx_gpio_direction_output(struct udevice
*dev, unsigned offset,
int value)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata-regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv-regs;
port = GPIO_TO_PORT(offset);
mask = GPIO_TO_MASK(offset);
@@ -231,7 +231,7 @@ static int lpc32xx_gpio_direction_output(struct udevice
*dev, unsigned offset,
}
/* GPIO FUNCTION: SEE WARNING #2 */
- gpio_platdata-function[offset] = GPIOF_OUTPUT;
+ gpio_priv-function[offset] = GPIOF_OUTPUT;
return lpc32xx_gpio_set_value(dev, offset, value);
}
@@ -251,8 +251,8 @@ static int lpc32xx_gpio_direction_output(struct udevice
*dev, unsigned offset,
static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- return gpio_platdata-function[offset];
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ return gpio_priv-function[offset];
}
static const struct dm_gpio_ops gpio_lpc32xx_ops = {
@@ -265,7 +265,7 @@ static const struct dm_gpio_ops gpio_lpc32xx_ops = {
static int lpc32xx_gpio_probe(struct udevice *dev)
{
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev-uclass_priv;
if (dev-of_offset == -1) {
@@ -274,12 +274,11 @@ static int lpc32xx_gpio_probe(struct udevice *dev)
}
/* set base address for GPIO registers */
- gpio_platdata-regs = (struct gpio_regs *)GPIO_BASE;
+ gpio_priv-regs = (struct
Re: [U-Boot] [PATCH v2 3/4] mtd: nand: mxs: Add comment for calculating ECC strength
Hello Jörg,
Am 13.04.2015 22:17, schrieb Jörg Krause:
Signed-off-by: Jörg Krause joerg.krause@embedded.rocks
---
drivers/mtd/nand/mxs_nand.c | 7 +++
1 file changed, 7 insertions(+)
nitpick only ...
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 912fed8..76e47ab 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -148,6 +148,13 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t
page_data_size,
{
int ecc_strength;
+ /* Determine the ECC layout with the formula:
wrong comment style ... please fix also in patch 4/4... thanks.
bye,
Heiko
+* ECC bits per chunk = (total page spare data bits) /
+* (bits per ECC level) / (chunks per page)
+* where:
+* total page spare data bits =
+* (page oob size - meta data size) * (bits per byte)
+*/
ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
/ (MXS_NAND_BITS_PER_ECC_LEVEL *
mxs_nand_ecc_chunk_cnt(page_data_size));
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [RESEND PATCH v4 2/3] mtd, nand: move common functions from cmd_nand.c to common place
Hello Scott, Am 13.04.2015 22:32, schrieb Scott Wood: On Sun, 2015-04-12 at 10:12 +0200, Heiko Schocher wrote: @@ -595,7 +491,10 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(\nNAND %s: , cmd); /* skip first two or three arguments, look for offset and size */ if (arg_off_size(argc - o, argv + o, dev, off, size, -maxsize) != 0) + maxsize, MTD_DEV_TYPE_NAND, nand_info[dev].size) != 0) Please keep the continuation line aligned with the arguments, not the function name (here and elsewhere). Good catch! Fixed. Wait for more comments before posting v5 ... bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] zynq: Add Zynq PicoZed board support
The PicoZed is a System-on-Module board which is marketed as part of
the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000
processor.
This patch adds support that covers all the variants of the PicoZed
including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This
patch set however only covers support for the System-on-Module and does
not cover any extra components that are available on carrier boards
(except those that are fanned out of the module itself).
More information on this board, its variants and available carrier
boards is available at: http://zedboard.org/product/picozed
Signed-off-by: Nathan Rossi nathan.ro...@xilinx.com
---
arch/arm/cpu/armv7/zynq/Kconfig |4
arch/arm/dts/Makefile |1 +
arch/arm/dts/zynq-picozed.dts | 23 +++
configs/zynq_picozed_defconfig |6 ++
include/configs/zynq_picozed.h | 28
5 files changed, 62 insertions(+)
create mode 100644 arch/arm/dts/zynq-picozed.dts
create mode 100644 configs/zynq_picozed_defconfig
create mode 100644 include/configs/zynq_picozed.h
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig
index 3a52535..26e570e 100644
--- a/arch/arm/cpu/armv7/zynq/Kconfig
+++ b/arch/arm/cpu/armv7/zynq/Kconfig
@@ -9,6 +9,9 @@ config TARGET_ZYNQ_ZED
config TARGET_ZYNQ_MICROZED
bool Zynq MicroZed
+config TARGET_ZYNQ_PICOZED
+ bool Zynq PicoZed
+
config TARGET_ZYNQ_ZC70X
bool Zynq ZC702/ZC706 Board
@@ -32,6 +35,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default zynq_zed if TARGET_ZYNQ_ZED
default zynq_microzed if TARGET_ZYNQ_MICROZED
+ default zynq_picozed if TARGET_ZYNQ_PICOZED
default zynq_zc70x if TARGET_ZYNQ_ZC70X
default zynq_zc770 if TARGET_ZYNQ_ZC770
default zynq_zybo if TARGET_ZYNQ_ZYBO
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f897e6d..aadbd0c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -44,6 +44,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zed.dtb \
zynq-zybo.dtb \
zynq-microzed.dtb \
+ zynq-picozed.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts
new file mode 100644
index 000..686b98f
--- /dev/null
+++ b/arch/arm/dts/zynq-picozed.dts
@@ -0,0 +1,23 @@
+/*
+ * Avnet PicoZed board DTS
+ *
+ * Copyright (C) 2015 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+/dts-v1/;
+#include zynq-7000.dtsi
+
+/ {
+ model = Zynq PicoZed Board;
+ compatible = xlnx,zynq-picozed, xlnx,zynq-7000;
+
+ aliases {
+ serial0 = uart1;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0 0x4000;
+ };
+};
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
new file mode 100644
index 000..8a4916a
--- /dev/null
+++ b/configs/zynq_picozed_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
++S:CONFIG_TARGET_ZYNQ_PICOZED=y
+CONFIG_OF_CONTROL=n
+CONFIG_DEFAULT_DEVICE_TREE=zynq-picozed
diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h
new file mode 100644
index 000..337457c
--- /dev/null
+++ b/include/configs/zynq_picozed.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2015 Xilinx, Inc.
+ *
+ * Configuration for PicoZed
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_PICOZED_H
+#define __CONFIG_ZYNQ_PICOZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_USB
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include configs/zynq-common.h
+
+#endif /* __CONFIG_ZYNQ_PICOZED_H */
--
1.7.10.4
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[U-Boot] [PATCH v4 0/9] Allow sandbox to use config_distro_bootcmd
Testing whether images will correctly boot with the standard distro bootcmds can be rather time-consuming as it tends to require flashing the images and booting on a device. Ditto for testing changes to config_distro_bootcmd. Adding support for sandbox to run distro bootcmds makes things a lot more convenient. Version 4 is mostly a rebase on u-boot-dm/next as requested by Simon. As this branch now has networking support one extra patch had to be added to setup default PXE client architectures for intel. Changes in v4: - New patch to setup PXE client arch on intel systems - Adapt to sandbox networking support Changes in v3: - Fill in *start and *end with proper values - Improve deprecated sb command short line - Don't document subcommands for sb anymore Changes in v2: - Minor comment coding style improvement - Move into sandbox/lib/bootm.c - convert to u-boot coding style - Remove unneeded cast - Prevent uncessary casts - Always unmap mapped sysmem - Consistently use base variable to refer to unmapped memory - Various coding style fixes Sjoerd Simons (9): sandbox: only do sandboxfs for hostfs interface sandbox: Split bootm code out into lib/bootm sandbox: Add support for bootz sandbox: Renamed sb command to host sandbox: Implement host dev [device] config_distro_bootcmd.h: Add shared block definition for the host interface pxe: Ensure all memory access is to mapped memory config: Add default client arch defines for intel architectures sandbox: add config_distro_defaults and config_distro_bootcmd arch/sandbox/cpu/cpu.c | 12 --- arch/sandbox/lib/Makefile| 1 + arch/sandbox/lib/bootm.c | 63 ++ common/Makefile | 2 +- common/cmd_host.c| 176 +++ common/cmd_pxe.c | 86 --- common/cmd_sandbox.c | 126 fs/sandbox/sandboxfs.c | 6 +- include/config_distro_bootcmd.h | 13 +++ include/config_distro_defaults.h | 4 + include/configs/sandbox.h| 31 +-- 11 files changed, 342 insertions(+), 178 deletions(-) create mode 100644 arch/sandbox/lib/bootm.c create mode 100644 common/cmd_host.c delete mode 100644 common/cmd_sandbox.c -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] run the u-boot for taihu board within qemu
Hi, Trying to run the u-boot for taihu board within qemu. but i get some error. I am using u-boot-latest and qemu-1.6.1. Command: make distclean make mrproper make ARCH=powerpc CROSS_COMPILE=/tools/bin/powerpc-linux- taihu_defconfig make ARCH=powerpc CROSS_COMPILE=/tools/bin/powerpc-linux- dd if=/dev/zero of=flash.img bs=1M count=512 dd if=u-boot.bin of=flash.img conv=notrunc qemu-system-ppc -M taihu -m 200 -nographic -pflash flash.img then i get taihu_405ep_init: register cpu ppc4xx_opba_init: offset ef600600 ppc405_gpio_init: offset ef600700 ppc4xx_gpt_init: offset ef60 taihu_405ep_init: register BIOS Load BIOS from file taihu_405ep_init: register CPLD taihu_405ep_init: Done OCM update ISA ( ) DSA ( ) Setup PPC405EP clocks - sysclk VCO 0 PLL out Hz CPU PLB 1666 OPB 833 EBC 833 MAL 833 PCI 1666 UART0 260416 UART1 260416 qemu: fatal: Trying to execute code outside RAM or ROM at 0x0700 How can I solve the error? Your feedback would help me a lot. Thanks in advance, Yours sincerely, Yanzhao Feng fengyanz...@tju.edu.cn ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2][v6] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
We have understood what Scott was suggesting but still need to try the changes suggested by him. We haven't started on it yet. Regards, Aneesh Bansal -Original Message- From: Sun York-R58495 Sent: Monday, April 13, 2015 10:03 PM To: Bansal Aneesh-B39320; u-boot@lists.denx.de Cc: Wood Scott-B07421; Gupta Ruchika-R66431 Subject: Re: [PATCH 1/2][v6] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Aneesh, On 03/04/2015 11:38 PM, Aneesh Bansal wrote: Secure Boot Target is added for NAND for P3041. Changes: In PowerPC, the core begins execution from address 0xFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on this SRAM at location 0xBFF4 with entry point as 0xBFFC. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com --- Changes in v6: Changed the version in Patchset. Are we closed on this patch discussion? I see open discussion for v4 patch after you posted v6. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/4] mtd: nand: mxs: Calculate ECC strength dynamically
Hello Jörg, Am 13.04.2015 22:17, schrieb Jörg Krause: This series of patches are based on the patch of Peng Fan: https://patchwork.ozlabs.org/patch/422756/ Patch 1 is the originally patch from Peng Fan, Patch 2 and 3 add minor changes to 1 and patch 4 adds the ECC strength calculation to tools/mxsboot to be aligned with the changes made in patch 1 to 3. Instead of hard-coding every possible oob size / ECC strength combination calculate the ECC strength dynamically to be aligned with the Linux Kernel MTD NAND driver. Also adds the calculation to tools/mxsboot to be aligned with the U-Boot MTD NAND driver. Obviously, we have some code redundancy here in mxs_nand.c and mxsboot.c. Jörg Krause (3): mtd: nand: mxs: Replace magic number for bits per ECC level with macro mtd: nand: mxs: Add comment for calculating ECC strength tools: mxsboot: Calculate ECC strength dynamically Peng Fan (1): mtd:mxs:nand calculate ecc strength dynamically drivers/mtd/nand/mxs_nand.c | 36 +++- tools/mxsboot.c | 39 --- 2 files changed, 39 insertions(+), 36 deletions(-) Tried this patches on the aristainetos2 board. UBI on the nand works nice with this patches, so: Acked-by: Heiko Schocher h...@denx.de This patchset replaces my patch: Patchwork [U-Boot] mxs_nand: Fix ECC strength for NAND flash with OOB size of 256 http://patchwork.ozlabs.org/patch/460462/ bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/4] mtd: nand: mxs: Add comment for calculating ECC strength
Hello Heiko,
On Di, 2015-04-14 at 08:12 +0200, Heiko Schocher wrote:
Hello Jörg,
Am 13.04.2015 22:17, schrieb Jörg Krause:
Signed-off-by: Jörg Krause joerg.krause@embedded.rocks
---
drivers/mtd/nand/mxs_nand.c | 7 +++
1 file changed, 7 insertions(+)
nitpick only ...
I'm unsure what this comment means translated to German. Something
like small changes only?
diff --git a/drivers/mtd/nand/mxs_nand.c
b/drivers/mtd/nand/mxs_nand.c
index 912fed8..76e47ab 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -148,6 +148,13 @@ static inline uint32_t
mxs_nand_get_ecc_strength(uint32_t page_data_size,
{
int ecc_strength;
+ /* Determine the ECC layout with the formula:
wrong comment style ... please fix also in patch 4/4... thanks.
Checkpatch did not complain and I did not know there is a coding style
for comments. Should it be:
/*
* Determine the ECC layout...
Bye
Jörg
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Re: [U-Boot] [PATCH v2 3/4] mtd: nand: mxs: Add comment for calculating ECC strength
Hello Jörg,
Am 14.04.2015 08:29, schrieb Jörg Krause:
Hello Heiko,
On Di, 2015-04-14 at 08:12 +0200, Heiko Schocher wrote:
Hello Jörg,
Am 13.04.2015 22:17, schrieb Jörg Krause:
Signed-off-by: Jörg Krause joerg.krause@embedded.rocks
---
drivers/mtd/nand/mxs_nand.c | 7 +++
1 file changed, 7 insertions(+)
nitpick only ...
I'm unsure what this comment means translated to German. Something
like small changes only?
Yes, something like pingelig
diff --git a/drivers/mtd/nand/mxs_nand.c
b/drivers/mtd/nand/mxs_nand.c
index 912fed8..76e47ab 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -148,6 +148,13 @@ static inline uint32_t
mxs_nand_get_ecc_strength(uint32_t page_data_size,
{
int ecc_strength;
+ /* Determine the ECC layout with the formula:
wrong comment style ... please fix also in patch 4/4... thanks.
Checkpatch did not complain and I did not know there is a coding style
for comments. Should it be:
/*
* Determine the ECC layout...
Yes.
See: linux:/Documentation/CodingStyle search for
The preferred style for long (multi-line) comments is
bye,
Heiko
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[U-Boot] [PATCH] vexpress64: use DM for all vexpress64 boards
Commit d8bafe1310487ba0e0785997726b4792072178d3
ARMv8: enable DM in vexpress64 board only enabled DM
for the simulated vexpress64 board (FVP) with the
hardcoded clock value for the simulated board, causing
a console regression on the Juno board which was using
a different clock setting.
Fix this by enabling DM for all vexpress64 boards,
defining the clock frequency per-board, deleting the
static array of PL01x ports from the config file and
relying solely on the port defined in the boardfile
using platform data.
Cc: David Feng feng...@phytium.com.cn
Signed-off-by: Linus Walleij linus.wall...@linaro.org
---
board/armltd/vexpress64/vexpress64.c | 2 +-
include/configs/vexpress_aemv8a.h| 20
2 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/board/armltd/vexpress64/vexpress64.c
b/board/armltd/vexpress64/vexpress64.c
index 13dd6674363c..7cb4e0021f66 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct pl01x_serial_platdata serial_platdata = {
.base = V2M_UART0,
.type = TYPE_PL011,
- .clock = 2400 * 1000,
+ .clock = CONFIG_PL011_CLOCK,
};
U_BOOT_DEVICE(vexpress_serials) = {
diff --git a/include/configs/vexpress_aemv8a.h
b/include/configs/vexpress_aemv8a.h
index 3fda20a8f6c8..032010bb9e02 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -8,10 +8,9 @@
#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H
-#define CONFIG_DM
-
-/* We use generic board for v8 Versatile Express */
+/* We use generic board and device manager for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
@@ -134,27 +133,16 @@
#endif
/* PL011 Serial Configuration */
-#define CONFIG_BAUDRATE115200
-#ifdef CONFIG_DM
#define CONFIG_DM_SERIAL
-#define CONFIG_PL01X_SERIAL
-#else
-#define CONFIG_SYS_SERIAL0 V2M_UART0
-#define CONFIG_SYS_SERIAL1 V2M_UART1
+#define CONFIG_BAUDRATE115200
#define CONFIG_CONS_INDEX 0
+#define CONFIG_PL01X_SERIAL
#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7273800
#else
#define CONFIG_PL011_CLOCK 2400
#endif
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
-(void *)CONFIG_SYS_SERIAL1}
-#endif
-
-#define CONFIG_BAUDRATE115200
-#define CONFIG_SYS_SERIAL0 V2M_UART0
-#define CONFIG_SYS_SERIAL1 V2M_UART1
/* Command line configuration */
#define CONFIG_MENU
--
1.9.3
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[U-Boot] [PATCH v2 0/3] ARM: zynq: include ps7_init_gpl.c/h of Zed, MicroZed, ZC702, ZC706
Masahiro Yamada (3):
ARM: zynq: drop legacy ps7_init.c/h support
ARM: zynq: use separate configuration for ZC702 and ZC706
ARM: zynq: add default ps7_init_gpl.c/h for Zed, MicroZed, ZC70x
arch/arm/cpu/armv7/zynq/Kconfig|19 +-
arch/arm/cpu/armv7/zynq/spl.c | 2 +-
board/xilinx/zynq/Makefile |20 +-
.../zynq/MicroZed_hw_platform/ps7_init_gpl.c | 12978 ++
.../zynq/MicroZed_hw_platform/ps7_init_gpl.h | 130 +
board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c | 13311 +++
board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h | 130 +
board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c | 13218 ++
board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h | 130 +
.../zynq/{ = custom_hw_platform}/.gitignore | 1 -
board/xilinx/zynq/legacy.c | 2 -
board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c | 12876 ++
board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h | 130 +
.../{zynq_zc70x_defconfig = zynq_zc702_defconfig} | 2 +-
configs/zynq_zc706_defconfig |11 +
doc/README.zynq|15 +-
16 files changed, 52952 insertions(+), 23 deletions(-)
create mode 100644 board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
create mode 100644 board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
create mode 100644 board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
create mode 100644 board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
create mode 100644 board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
create mode 100644 board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
rename board/xilinx/zynq/{ = custom_hw_platform}/.gitignore (56%)
delete mode 100644 board/xilinx/zynq/legacy.c
create mode 100644 board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
create mode 100644 board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
rename configs/{zynq_zc70x_defconfig = zynq_zc702_defconfig} (88%)
create mode 100644 configs/zynq_zc706_defconfig
--
1.9.1
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[U-Boot] [PATCH v2 2/3] ARM: zynq: use separate configuration for ZC702 and ZC706
Separate CONFIG_TARGET_ZYNQ_{ZC702,ZC706} which is necessary
for the next commit. Adjust doc/README.zynq too.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2: None
arch/arm/cpu/armv7/zynq/Kconfig| 9 ++---
configs/{zynq_zc70x_defconfig = zynq_zc702_defconfig} | 2 +-
configs/zynq_zc706_defconfig | 11 +++
doc/README.zynq| 15 ---
4 files changed, 22 insertions(+), 15 deletions(-)
rename configs/{zynq_zc70x_defconfig = zynq_zc702_defconfig} (88%)
create mode 100644 configs/zynq_zc706_defconfig
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig
index 3a52535..ab4768a 100644
--- a/arch/arm/cpu/armv7/zynq/Kconfig
+++ b/arch/arm/cpu/armv7/zynq/Kconfig
@@ -9,8 +9,11 @@ config TARGET_ZYNQ_ZED
config TARGET_ZYNQ_MICROZED
bool Zynq MicroZed
-config TARGET_ZYNQ_ZC70X
- bool Zynq ZC702/ZC706 Board
+config TARGET_ZYNQ_ZC702
+ bool Zynq ZC702 Board
+
+config TARGET_ZYNQ_ZC706
+ bool Zynq ZC706 Board
config TARGET_ZYNQ_ZC770
bool Zynq ZC770 Board
@@ -32,7 +35,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default zynq_zed if TARGET_ZYNQ_ZED
default zynq_microzed if TARGET_ZYNQ_MICROZED
- default zynq_zc70x if TARGET_ZYNQ_ZC70X
+ default zynq_zc70x if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
default zynq_zc770 if TARGET_ZYNQ_ZC770
default zynq_zybo if TARGET_ZYNQ_ZYBO
diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc702_defconfig
similarity index 88%
rename from configs/zynq_zc70x_defconfig
rename to configs/zynq_zc702_defconfig
index 44f3ae0..93641cd 100644
--- a/configs/zynq_zc70x_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,7 +1,7 @@
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC70X=y
+CONFIG_TARGET_ZYNQ_ZC702=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE=zynq-zc702
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
new file mode 100644
index 000..821bd82
--- /dev/null
+++ b/configs/zynq_zc706_defconfig
@@ -0,0 +1,11 @@
+CONFIG_SPL=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC706=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE=zynq-zc706
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/doc/README.zynq b/doc/README.zynq
index 043c970..b89c39e 100644
--- a/doc/README.zynq
+++ b/doc/README.zynq
@@ -17,9 +17,8 @@ Xilinx Zynq-7000 All Programmable SoCs enable extensive
system level
differentiation, integration, and flexibility through hardware, software,
and I/O programmability.
-* zc70x
- - zc702 (single qspi, gem0, mmc) [1]
- - zc706 (dual parallel qspi, gem0, mmc) [2]
+* zc702 (single qspi, gem0, mmc) [1]
+* zc706 (dual parallel qspi, gem0, mmc) [2]
* zed (single qspi, gem0, mmc) [3]
* microzed (single qspi, gem0, mmc) [4]
* zc770
@@ -30,16 +29,10 @@ and I/O programmability.
3. Building
- # Configure for zc70x board
- $ make zynq_zc70x_config
- Configuring for zynq_zc70x board...
-
- # Building default dts for zc702 board
+ ex. configure and build for zc702 board
+ $ make zynq_zc702_config
$ make
- # Building specified dts for zc706 board
- $ make DEVICE_TREE=zynq-zc706
-
4. Bootmode
Zynq has a facility to read the bootmode from the slcr bootmode register
--
1.9.1
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[U-Boot] [GIT] Pull request: u-boot-dfu
The following changes since commit 7704fdbda3afb3d3bb0749378f444c71f92fb9ca: usb: gadget: thor: Claim EP after allocating it in thor gadget (2015-04-14 05:48:12 +0200) are available in the git repository at: git://git.denx.de/u-boot-dfu.git for you to fetch changes up to a32d27912961040230320268d6cde80e9442dc33: fastboot: Proper download gadget unregister and clear when cable is missing (2015-04-14 10:19:05 +0200) Alexey Firago (1): fastboot: add support for reboot-bootloader command Fabio Estevam (1): cmd_usb_mass_storage: Use 'USB Mass Storage' in the help text Heiko Schocher (1): dfu: cmd: trigger watchdog before calling usb_gadget_handle_interrupts Michael Scott (1): fastboot: check for alias when looking up partition by name Paul Kocialkowski (1): fastboot: Proper download gadget unregister and clear when cable is missing common/cmd_dfu.c| 2 ++ common/cmd_fastboot.c | 2 ++ common/cmd_usb_mass_storage.c | 2 +- common/fb_mmc.c | 26 -- doc/README.android-fastboot | 9 + drivers/usb/gadget/f_fastboot.c | 13 + 6 files changed, 51 insertions(+), 3 deletions(-) Tested at: Exynos4210 - Trats board -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] ARMv8: replace CONFIG_ARM64 with builtin __aarch64__
Hello feng...@phytium.com.cn, On Tue, 3 Feb 2015 16:10:25 +0800, feng...@phytium.com.cn feng...@phytium.com.cn wrote: From: David Feng feng...@phytium.com.cn This patch replace CONFIG_ARM64 with gcc builtin __aarch64__. CONFIG_ARM64 is still needed in makefile and config.mk. Maybe them could be replace with something like *_V8 later. If CONFIG_ARM64 is still needed, then it will remain available, so there is no /need/ to replace it in source code. There may be an /interest/ in replacing it though, but it is not stated here. What would this be? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] ARM: zynq: drop legacy ps7_init.c/h support
We are about to change the location for ps7_init files, breaking the
current work-flows. It is good time to drop the legacy ps7_init.c/h
support.
Going forward, please use ps7_init_gpl.c/h all the time.
If you are still using old Xilinx tools that are only able to
generate ps7_init.c/h, rename them into ps7_init_gpl.c/h.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Suggested-by: Sören Brinkmann soren.brinkm...@xilinx.com
---
Changes in v2:
- Newly added
arch/arm/cpu/armv7/zynq/spl.c | 2 +-
board/xilinx/zynq/.gitignore | 1 -
board/xilinx/zynq/Makefile| 4 +---
board/xilinx/zynq/legacy.c| 2 --
4 files changed, 2 insertions(+), 7 deletions(-)
delete mode 100644 board/xilinx/zynq/legacy.c
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index b80c357..13025f0 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -85,6 +85,6 @@ __weak void ps7_init(void)
{
/*
* This function is overridden by the one in
-* board/xilinx/zynq/ps7_init.c, if it exists.
+* board/xilinx/zynq/ps7_init_gpl.c, if it exists.
*/
}
diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore
index 7c36bc9..c455361 100644
--- a/board/xilinx/zynq/.gitignore
+++ b/board/xilinx/zynq/.gitignore
@@ -1,2 +1 @@
-ps7_init.[ch]
ps7_init_gpl.[ch]
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 3b1eb4f..054c3d8 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -9,9 +9,7 @@ obj-y := board.o
# Please copy ps7_init_gpl.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
- $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c),
ps7_init_gpl.o, \
- $(if $(wildcard $(srctree)/$(src)/ps7_init.c),
ps7_init.o legacy.o))
+ $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o)
# Suppress warning: function declaration isn't a prototype
CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
-CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes
diff --git a/board/xilinx/zynq/legacy.c b/board/xilinx/zynq/legacy.c
deleted file mode 100644
index 4ae913e..000
--- a/board/xilinx/zynq/legacy.c
+++ /dev/null
@@ -1,2 +0,0 @@
-
-#warning usage of ps7_init files is deprecated please use ps7_init_gpl
--
1.9.1
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[U-Boot] [PATCH] ARM: UniPhier: add initrd_high and fdt_high environments
With FIT boot, U-boot puts a device tree and an initramdisk at the tail of the memory. Some UniPhier boards have a large amount of memory. For those boards, a device tree and an initramdisk are located out of reach of the Linux kernel causing a kernel panic if CONFIG_VMSPLIT_3G is defined in the kernel side. Add initrd_high and fdt_high to prevent them from going too high. Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com --- include/configs/uniphier.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index d4688c5..dea340f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -236,6 +236,8 @@ netdev=eth0\0 \ image_offset=0x0008\0 \ image_size=0x00f0\0 \ + initrd_high=0xa000\0 \ + fdt_high=0xa000\0 \ verify=n\0\ nandupdate=nand erase 0 0x10\ tftpboot u-boot-spl.bin \ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] board/t102x: use fdt_setprop_string instead of fdt_setprop
Use fdt_setprop_string instead of fdt_setprop to fix string length.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
board/freescale/t102xqds/eth_t102xqds.c | 9 +
board/freescale/t102xrdb/eth_t102xrdb.c | 4 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/board/freescale/t102xqds/eth_t102xqds.c
b/board/freescale/t102xqds/eth_t102xqds.c
index 7723f58..441d6a3 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -172,8 +172,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat,
phys_addr_t addr,
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
if (port == FM1_DTSEC3) {
fdt_set_phy_handle(fdt, compat, addr, rgmii_phy2);
- fdt_setprop(fdt, offset, phy-connection-type,
- rgmii, 5);
+ fdt_setprop_string(fdt, offset, phy-connection-type,
+ rgmii);
fdt_status_okay_by_alias(fdt, emi1_rgmii1);
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
@@ -207,7 +207,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat,
phys_addr_t addr,
break;
}
fdt_delprop(fdt, offset, phy-connection-type);
- fdt_setprop(fdt, offset, phy-connection-type, qsgmii, 6);
+ fdt_setprop_string(fdt, offset, phy-connection-type,
+ qsgmii);
fdt_status_okay_by_alias(fdt, emi1_slot2);
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* XFI interface */
@@ -219,7 +220,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat,
phys_addr_t addr,
/* no PHY for XFI */
fdt_delprop(fdt, offset, phy-handle);
fdt_setprop(fdt, offset, fixed-link, f_link, sizeof(f_link));
- fdt_setprop(fdt, offset, phy-connection-type, xgmii, 5);
+ fdt_setprop_string(fdt, offset, phy-connection-type, xgmii);
}
}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c
b/board/freescale/t102xrdb/eth_t102xrdb.c
index dd386bc..856ec6e 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -133,8 +133,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat,
phys_addr_t addr,
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII))
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, sg_2500_aqr105_phy4);
- fdt_setprop(fdt, offset, phy-connection-type,
- sgmii-2500, 10);
+ fdt_setprop_string(fdt, offset, phy-connection-type,
+ sgmii-2500);
fdt_status_disabled_by_alias(fdt, xg_aqr105_phy3);
}
#endif
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
Hello, On 15-04-14 09:06:27, Peter Chen wrote: Hi! Stefano, maybe you can pick 1,2,3,4,6 right away for next? This way, we can solve 5/6 separately, since it might need some further dicussion. I don't want that patch to block the rest of the series though. The sixth patch has some minor dependencies on the fifth patch like some #defines and configuration we enable for Colibri. In case the fifth patch will require some more discussion and time, then I guess I will need to rework the sixth patch and then everything related to USB can go in a later patch. The rework will be minor. So the v3 will be without USB support Well, if you want to rework the 6th patch, that'd be very nice of you :) Yes sure. Will put the USB support in the end or not, the first patches can go in atleast since there seem to be no complaints on them so far. and USB will go in later once this gets applied. Perhaps we will send the USB along with some more other featureset addition like gpio support for Vybrid which my colleague did recently along with some driver model/dt stuff. My impression is that the USB is just a matter of figuring out where the PHY registers go -- whether in arch/arm/include/imx-common or into include/usb/ . I'd be more inclined for the later, since the PHY regs looks like chipidea IP specific thing, but I might be wrong. I would say it looks like chipidea specific but I have not looked at IPs other than Freescale controllers to be sure. I think it's CI-specific indeed, thus include/usb/ . +CC Peter, who might chime in whether the PHY is CI-specific or IMX-specific. Which PHY? Vybrid? In Linux kernel, it belongs to mxs PHY. The same controller can integrate different PHYs. Yeah. Is the PHY MXS/IMX/VF specific or can that PHY be found even on other SoCs not manufactured by Freescale ? This mxs PHY is from SigmaTel, I only see this PHY is used at FSL SoCs, but not sure if others use it. So Chipidea IP with the SigmaTel phy. It might be better to have the regs-usbphy.h viz. register phy definitions in imx-common then since it is not clear if SoC's other than Freescale's use the same phy. Marek, what do you think? - Sanchayan. Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/13] arm: armada-xp: Move SoC headers to mach-mvebu/include/mach
Move arch/arm/include/asm/arch-armada-xp/*
- arch/arm/mach-mvebu/include/mach/*
Additionally the SYS_SOC is renamed from armada-xp to mvebu. With this
change all these files can better be shared with other, newer Mavell
MVEBU SoC's. Like the upcoming Armada 38x support.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2: None
arch/arm/Makefile | 2 +-
.../{include/asm/arch-armada-xp = mach-mvebu/include/mach}/config.h| 0
arch/arm/{include/asm/arch-armada-xp = mach-mvebu/include/mach}/cpu.h | 0
arch/arm/{include/asm/arch-armada-xp = mach-mvebu/include/mach}/soc.h | 0
board/Marvell/db-mv784mp-gp/Kconfig | 2 +-
board/maxbcm/Kconfig| 2 +-
6 files changed, 3 insertions(+), 3 deletions(-)
rename arch/arm/{include/asm/arch-armada-xp =
mach-mvebu/include/mach}/config.h (100%)
rename arch/arm/{include/asm/arch-armada-xp = mach-mvebu/include/mach}/cpu.h
(100%)
rename arch/arm/{include/asm/arch-armada-xp = mach-mvebu/include/mach}/soc.h
(100%)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7bd53c5..32c152d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -85,7 +85,7 @@ libs-y += arch/arm/imx-common/
endif
endif
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
+ifneq (,$(filter $(SOC), mvebu kirkwood))
libs-y += arch/arm/mvebu-common/
endif
diff --git a/arch/arm/include/asm/arch-armada-xp/config.h
b/arch/arm/mach-mvebu/include/mach/config.h
similarity index 100%
rename from arch/arm/include/asm/arch-armada-xp/config.h
rename to arch/arm/mach-mvebu/include/mach/config.h
diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
similarity index 100%
rename from arch/arm/include/asm/arch-armada-xp/cpu.h
rename to arch/arm/mach-mvebu/include/mach/cpu.h
diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
similarity index 100%
rename from arch/arm/include/asm/arch-armada-xp/soc.h
rename to arch/arm/mach-mvebu/include/mach/soc.h
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig
b/board/Marvell/db-mv784mp-gp/Kconfig
index 98aa10a..d0b426e 100644
--- a/board/Marvell/db-mv784mp-gp/Kconfig
+++ b/board/Marvell/db-mv784mp-gp/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default Marvell
config SYS_SOC
- default armada-xp
+ default mvebu
config SYS_CONFIG_NAME
default db-mv784mp-gp
diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig
index d833ca0..e86aa16 100644
--- a/board/maxbcm/Kconfig
+++ b/board/maxbcm/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
default maxbcm
config SYS_SOC
- default armada-xp
+ default mvebu
config SYS_CONFIG_NAME
default maxbcm
--
2.3.5
___
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[U-Boot] [PATCH v2 03/13] arm: mvebu: Move mvebu-common into mach-mvebu
Now that the mach-mvebu directory exists and is used by Armada XP we can
move the mvebu-common files into this directory as well.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2: None
arch/arm/Makefile | 4 ++--
arch/arm/mach-mvebu/Makefile| 17 -
arch/arm/{mvebu-common = mach-mvebu}/dram.c| 0
arch/arm/{mvebu-common = mach-mvebu}/gpio.c| 0
arch/arm/{mvebu-common = mach-mvebu}/mbus.c| 0
arch/arm/{mvebu-common = mach-mvebu}/serdes/Makefile | 0
.../serdes/board_env_spec.h | 0
.../serdes/high_speed_env_lib.c | 0
.../serdes/high_speed_env_spec.c| 0
.../serdes/high_speed_env_spec.h| 0
arch/arm/{mvebu-common = mach-mvebu}/timer.c | 0
arch/arm/{mvebu-common = mach-mvebu}/u-boot-spl.lds| 0
board/maxbcm/maxbcm.c | 2 +-
include/configs/db-mv784mp-gp.h | 2 +-
include/configs/maxbcm.h| 2 +-
15 files changed, 21 insertions(+), 6 deletions(-)
rename arch/arm/{mvebu-common = mach-mvebu}/dram.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/gpio.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/mbus.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/Makefile (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/board_env_spec.h (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/high_speed_env_lib.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/high_speed_env_spec.c
(100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/high_speed_env_spec.h
(100%)
rename arch/arm/{mvebu-common = mach-mvebu}/timer.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/u-boot-spl.lds (100%)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 32c152d..c7ce6ef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -85,8 +85,8 @@ libs-y += arch/arm/imx-common/
endif
endif
-ifneq (,$(filter $(SOC), mvebu kirkwood))
-libs-y += arch/arm/mvebu-common/
+ifneq (,$(filter $(SOC), kirkwood))
+libs-y += arch/arm/mach-mvebu/
endif
# deprecated
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 737159b..4f477cd 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,9 +1,24 @@
#
-# Copyright (C) 2014 Stefan Roese s...@denx.de
+# Copyright (C) 2014-2015 Stefan Roese s...@denx.de
#
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_KIRKWOOD
+
+obj-y = dram.o
+obj-y += gpio.o
+obj-y += timer.o
+
+else
+
obj-y = cpu.o
+obj-y += dram.o
+obj-y += gpio.o
+obj-y += mbus.o
+obj-y += timer.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+
+obj-y += serdes/
+endif
diff --git a/arch/arm/mvebu-common/dram.c b/arch/arm/mach-mvebu/dram.c
similarity index 100%
rename from arch/arm/mvebu-common/dram.c
rename to arch/arm/mach-mvebu/dram.c
diff --git a/arch/arm/mvebu-common/gpio.c b/arch/arm/mach-mvebu/gpio.c
similarity index 100%
rename from arch/arm/mvebu-common/gpio.c
rename to arch/arm/mach-mvebu/gpio.c
diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mach-mvebu/mbus.c
similarity index 100%
rename from arch/arm/mvebu-common/mbus.c
rename to arch/arm/mach-mvebu/mbus.c
diff --git a/arch/arm/mvebu-common/serdes/Makefile
b/arch/arm/mach-mvebu/serdes/Makefile
similarity index 100%
rename from arch/arm/mvebu-common/serdes/Makefile
rename to arch/arm/mach-mvebu/serdes/Makefile
diff --git a/arch/arm/mvebu-common/serdes/board_env_spec.h
b/arch/arm/mach-mvebu/serdes/board_env_spec.h
similarity index 100%
rename from arch/arm/mvebu-common/serdes/board_env_spec.h
rename to arch/arm/mach-mvebu/serdes/board_env_spec.h
diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_lib.c
b/arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
similarity index 100%
rename from arch/arm/mvebu-common/serdes/high_speed_env_lib.c
rename to arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_spec.c
b/arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
similarity index 100%
rename from arch/arm/mvebu-common/serdes/high_speed_env_spec.c
rename to arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_spec.h
b/arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
similarity index 100%
rename from arch/arm/mvebu-common/serdes/high_speed_env_spec.h
rename to arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
diff --git a/arch/arm/mvebu-common/timer.c b/arch/arm/mach-mvebu/timer.c
similarity index 100%
rename from arch/arm/mvebu-common/timer.c
rename to arch/arm/mach-mvebu/timer.c
diff --git a/arch/arm/mvebu-common/u-boot-spl.lds
b/arch/arm/mach-mvebu/u-boot-spl.lds
similarity index 100%
rename from
[U-Boot] U-Boot mini summit
Hi everybody, there were some rumours about next U-Boot mini summit and why there is not yet a date. The reason is that we at DENX are thinking about, taking into account that the U-Boot community is steadily increased, which is the best location for the next summit. We know that a lot of you are in US or, generally, outside Europe and maybe it is time to ask everybody where the next summit will take place - and maybe the result will not be in Europe. Surely, the summit should be part of an Event organized by the Linux Foundation, and taking into account the embedded nature of the bootloader, there are two possible candidates: - ELCE in Dublin, 5-7 October 2015 - ELC in San Diego, 4-6 April 2016 Wolfgang has prepared a doodle survey to collect availability and preferences. Feel free to add your name to the event(s) you would like to participate. http://doodle.com/8mf8xhhbsugtirpa This survey runs until 10, May 2015 - after that we will know where to meet for the U-Boot summit. Thanks everybody for improving U-Boot ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/13] arm: mvebu: Change header macros from ARMADA_XP to MVEBU
Since these files will be used for other MVEBU SoC's, lets reflect this in the headers marcos as well. Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: None arch/arm/mach-mvebu/include/mach/config.h | 6 +++--- arch/arm/mach-mvebu/include/mach/cpu.h| 6 +++--- arch/arm/mach-mvebu/include/mach/soc.h| 8 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index f9fd424..01b725b 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -12,8 +12,8 @@ * It supports common definitions for Armada XP platforms */ -#ifndef _ARMADA_XP_CONFIG_H -#define _ARMADA_XP_CONFIG_H +#ifndef _MVEBU_CONFIG_H +#define _MVEBU_CONFIG_H #include asm/arch/soc.h @@ -83,4 +83,4 @@ #define CONFIG_SYS_I2C_SPEED 10 #endif -#endif /* _ARMADA_XP_CONFIG_H */ +#endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 4f5ff96..297ac52 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier:GPL-2.0+ */ -#ifndef _ARMADA_XP_CPU_H -#define _ARMADA_XP_CPU_H +#ifndef _MVEBU_CPU_H +#define _MVEBU_CPU_H #include asm/system.h @@ -120,4 +120,4 @@ int serdes_phy_config(void); */ int ddr3_init(void); #endif /* __ASSEMBLY__ */ -#endif /* _ARMADA_XP_CPU_H */ +#endif /* _MVEBU_CPU_H */ diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 963e7ac..202d5b8 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -8,8 +8,8 @@ * SPDX-License-Identifier:GPL-2.0+ */ -#ifndef _ASM_ARCH_ARMADA_XP_H -#define _ASM_ARCH_ARMADA_XP_H +#ifndef _MVEBU_SOC_H +#define _MVEBU_SOC_H #define SOC_MV78460_ID 0x7846 @@ -49,9 +49,9 @@ /* Armada XP GbE controller has 4 ports */ #define MAX_MVNETA_DEVS4 -/* Kirkwood CPU memory windows */ +/* MVEBU CPU memory windows */ #define MVCPU_WIN_CTRL_DATACPU_WIN_CTRL_DATA #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE -#endif /* _ASM_ARCH_ARMADA_XP_H */ +#endif /* _MVEBU_SOC_H */ -- 2.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 08/13] arm: mvebu: Add basic Armada 38x support
This patch adds support for the Marvell Armada 38x SoC family.
Supported peripherals are:
- UART
- Ethernet (mvneta)
- I2C
- SPI (including SPI NOR flash)
Tested on Marvell DB-88F6820-GP evaluation board.
Signed-off-by: Stefan Roese s...@denx.de
---
Changes in v2:
- Made mvebu_soc_family() globally available so that it can be called
from mbus.c
- Add PL310 L2 cache base address
arch/arm/mach-mvebu/cpu.c | 73 ++
arch/arm/mach-mvebu/include/mach/cpu.h | 7
arch/arm/mach-mvebu/include/mach/soc.h | 9 +
3 files changed, 73 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1cf70a9..eca5e21 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Stefan Roese s...@denx.de
+ * Copyright (C) 2014-2015 Stefan Roese s...@denx.de
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored)
;
}
+int mvebu_soc_family(void)
+{
+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) 16) 0x;
+
+ if (devid == SOC_MV78460_ID)
+ return MVEBU_SOC_AXP;
+
+ if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
+ devid == SOC_88F6828_ID)
+ return MVEBU_SOC_A38X;
+
+ return MVEBU_SOC_UNKNOWN;
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
@@ -52,23 +66,48 @@ int print_cpuinfo(void)
case SOC_MV78460_ID:
puts(MV78460-);
break;
- default:
- puts(Unknown-);
+ case SOC_88F6810_ID:
+ puts(MV88F6810-);
break;
- }
-
- switch (revid) {
- case 1:
- puts(A0\n);
+ case SOC_88F6820_ID:
+ puts(MV88F6820-);
break;
- case 2:
- puts(B0\n);
+ case SOC_88F6828_ID:
+ puts(MV88F6828-);
break;
default:
- puts(??\n);
+ puts(Unknown-);
break;
}
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ switch (revid) {
+ case 1:
+ puts(A0\n);
+ break;
+ case 2:
+ puts(B0\n);
+ break;
+ default:
+ printf(?? (%x)\n, revid);
+ break;
+ }
+ }
+
+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+ switch (revid) {
+ case MV_88F68XX_Z1_ID:
+ puts(Z1\n);
+ break;
+ case MV_88F68XX_A0_ID:
+ puts(A0\n);
+ break;
+ default:
+ printf(?? (%x)\n, revid);
+ break;
+ }
+ }
+
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -145,11 +184,13 @@ int arch_cpu_init(void)
*/
mvebu_mbus_probe(NULL, 0);
- /*
-* Now the SDRAM access windows can be reconfigured using
-* the information in the SDRAM scratch pad registers
-*/
- update_sdram_window_sizes();
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ /*
+* Now the SDRAM access windows can be reconfigured using
+* the information in the SDRAM scratch pad registers
+*/
+ update_sdram_window_sizes();
+ }
/*
* Finally the mbus windows can be configured with the
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
index 297ac52..3b48460 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -56,6 +56,12 @@ enum cpu_attrib {
CPU_ATTR_DEV_CS3 = 0x37,
};
+enum {
+ MVEBU_SOC_AXP,
+ MVEBU_SOC_A38X,
+ MVEBU_SOC_UNKNOWN,
+};
+
/*
* Default Device Address MAP BAR values
*/
@@ -106,6 +112,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
/*
* Highspeed SERDES PHY config init, ported from bin_hdr
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index f3e0398..0a9307c 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -12,6 +12,13 @@
#define _MVEBU_SOC_H
#define SOC_MV78460_ID 0x7846
+#define SOC_88F6810_ID 0x6810
+#define SOC_88F6820_ID 0x6820
+#define SOC_88F6828_ID 0x6828
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID 0x0
+#define MV_88F68XX_A0_ID 0x4
/* TCLK Core Clock definition */
#ifndef
[U-Boot] [PATCH v2 09/13] arm: mvebu: Change network init code to allow a more flexible setup
With the introduction of the Armada 38x support, its necessary to change
the mvneta ethernet driver init call from always 4 times to a
configurable value. Lets make this init call more flexible by moving
the actually used devices to the config header.
Additionally this patch takes care of the slightly different base
addresses for the ethernet controllers on A38x.
Signed-off-by: Stefan Roese s...@denx.de
---
Changes in v2: None
arch/arm/mach-mvebu/cpu.c | 20
board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 3 ++-
include/configs/db-mv784mp-gp.h | 2 +-
include/configs/maxbcm.h| 2 +-
4 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index eca5e21..8058fad 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -216,10 +216,22 @@ int arch_misc_init(void)
#ifdef CONFIG_MVNETA
int cpu_eth_init(bd_t *bis)
{
- mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
- mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
- mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
- mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
+ u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
+ MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
+ u8 phy_addr[] = CONFIG_PHY_ADDR;
+ int i;
+
+ /*
+* Only Armada XP supports all 4 ethernet interfaces. A38x has
+* slightly different base addresses for its 2-3 interfaces.
+*/
+ if (mvebu_soc_family() != MVEBU_SOC_AXP) {
+ enet_base[1] = MVEBU_EGIGA2_BASE;
+ enet_base[2] = MVEBU_EGIGA3_BASE;
+ }
+
+ for (i = 0; i ARRAY_SIZE(phy_addr); i++)
+ mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
return 0;
}
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index b3dae89..00ca878 100644
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -86,7 +86,8 @@ int checkboard(void)
/* Configure and enable MV88E1545 PHY */
void reset_phy(void)
{
- u16 devadr = CONFIG_PHY_BASE_ADDR;
+ u8 phy_addr[] = CONFIG_PHY_ADDR;
+ u16 devadr = phy_addr[0];
char *name = neta0;
u16 reg;
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 24cd42f..8b94454 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -53,7 +53,7 @@
#define CONFIG_ENV_SECT_SIZE (64 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR 0x10
+#define CONFIG_PHY_ADDR{ 0x10, 0x11, 0x12, 0x13 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT 8000/* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 496c2bd..db6a400 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -53,7 +53,7 @@
#define CONFIG_ENV_SECT_SIZE (64 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR 0x0
+#define CONFIG_PHY_ADDR{ 0x0, 0x1, 0x2, 0x3 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define PHY_ANEG_TIMEOUT 8000/* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R
--
2.3.5
___
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http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/13] Add Marvell Armada A38x 88F6820 SoC support
This patch series adds support for the Marvell Armada A38x SoC's. Specifically
the 88F6820 / 88F6828.
Basic support for the DB-88F6820-GP evaluation board is added. Supporting the
following interfaces:
- UART
- SPI (including SPI NOR flash)
- I2C
- Ethernet (neta)
One big part of this new SoC support is the move of the already exisiting
Armada XP support into the mach-mvebu directory. With this move its
easier to re-use this code for the A38x, which is pretty similar to the
AXP.
Thanks,
Stefan
Changes in v2:
- Made mvebu_soc_family() globally available so that it can be called
from mbus.c
- Add PL310 L2 cache base address
- Update to 256KiB env sector as required for M25P128
- Add I2C IO expander initialization (fan etc)
- Enable PL310 L2 cache as this is needed for correct caching OPs
Stefan Roese (13):
arm: armada-xp: Move SoC sources to mach-mvebu
arm: armada-xp: Move SoC headers to mach-mvebu/include/mach
arm: mvebu: Move mvebu-common into mach-mvebu
arm: mvebu: Change header macros from ARMADA_XP to MVEBU
arm: mvebu: Remove unreferenced define
arm: mvebu: Only define MV88F78X60 for Armada XP
arm: mvebu: Move CONFIG_SPL_LDSCRIPT to common header
arm: mvebu: Add basic Armada 38x support
arm: mvebu: Change network init code to allow a more flexible setup
arm: mvebu: Add dynamic SoC detection to mbus driver
arm: mvebu: mv-common.h: Add CONFIG_PREBOOT
arm: mvebu: Add d-cache invalidate before enabling the d-cache
arm: mvebu: Add Armada A38x DB-88F6820-GP board support
arch/arm/Kconfig | 6 ++
arch/arm/Makefile | 5 +-
arch/arm/cpu/armv7/Makefile| 1 -
arch/arm/cpu/armv7/armada-xp/Makefile | 9 --
arch/arm/mach-mvebu/Makefile | 24 +
arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/cpu.c | 96 +++
arch/arm/{mvebu-common = mach-mvebu}/dram.c | 0
arch/arm/{mvebu-common = mach-mvebu}/gpio.c | 0
.../include/mach}/config.h | 15 ++-
.../include/mach}/cpu.h| 13 ++-
.../include/mach}/soc.h| 20 ++--
.../armv7/armada-xp = mach-mvebu}/lowlevel_spl.S | 0
arch/arm/{mvebu-common = mach-mvebu}/mbus.c | 5 +-
.../{mvebu-common = mach-mvebu}/serdes/Makefile | 0
.../serdes/board_env_spec.h| 0
.../serdes/high_speed_env_lib.c| 0
.../serdes/high_speed_env_spec.c | 0
.../serdes/high_speed_env_spec.h | 0
arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/spl.c | 0
arch/arm/{mvebu-common = mach-mvebu}/timer.c | 0
.../{mvebu-common = mach-mvebu}/u-boot-spl.lds| 0
board/Marvell/db-88f6820-gp/Kconfig| 15 +++
board/Marvell/db-88f6820-gp/Makefile | 7 ++
board/Marvell/db-88f6820-gp/binary.0 | 16
board/Marvell/db-88f6820-gp/db-88f6820-gp.c| 103 +
board/Marvell/db-88f6820-gp/kwbimage.cfg | 12 +++
board/Marvell/db-mv784mp-gp/Kconfig| 2 +-
board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c| 3 +-
board/maxbcm/Kconfig | 2 +-
board/maxbcm/maxbcm.c | 2 +-
configs/db-88f6820-gp_defconfig| 2 +
include/configs/db-88f6820-gp.h| 72 ++
include/configs/db-mv784mp-gp.h| 3 +-
include/configs/maxbcm.h | 3 +-
include/configs/mv-common.h| 1 +
35 files changed, 380 insertions(+), 57 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/armada-xp/Makefile
create mode 100644 arch/arm/mach-mvebu/Makefile
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/cpu.c (71%)
rename arch/arm/{mvebu-common = mach-mvebu}/dram.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/gpio.c (100%)
rename arch/arm/{include/asm/arch-armada-xp =
mach-mvebu/include/mach}/config.h (86%)
rename arch/arm/{include/asm/arch-armada-xp = mach-mvebu/include/mach}/cpu.h
(93%)
rename arch/arm/{include/asm/arch-armada-xp = mach-mvebu/include/mach}/soc.h
(81%)
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/lowlevel_spl.S (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/mbus.c (99%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/Makefile (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/board_env_spec.h (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/high_speed_env_lib.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/high_speed_env_spec.c
(100%)
rename arch/arm/{mvebu-common = mach-mvebu}/serdes/high_speed_env_spec.h
(100%)
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/spl.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/timer.c (100%)
rename arch/arm/{mvebu-common = mach-mvebu}/u-boot-spl.lds (100%)
create
[U-Boot] [PATCH v2 05/13] arm: mvebu: Remove unreferenced define
MAX_MVNETA_DEVS is not used anywhere in U-Boot. So lets remove it. Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: None arch/arm/mach-mvebu/include/mach/soc.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 202d5b8..f3e0398 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -46,9 +46,6 @@ #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK0xFF00 -/* Armada XP GbE controller has 4 ports */ -#define MAX_MVNETA_DEVS4 - /* MVEBU CPU memory windows */ #define MVCPU_WIN_CTRL_DATACPU_WIN_CTRL_DATA #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE -- 2.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 11/13] arm: mvebu: mv-common.h: Add CONFIG_PREBOOT
This enables the usage of the preboot environment variable on Marvell boards. Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: None include/configs/mv-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 721b75d..51436da 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -57,6 +57,7 @@ 115200,230400, 460800, 921600 } /* auto boot */ #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ +#define CONFIG_PREBOOT /* * For booting Linux, the board info and command line data -- 2.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 07/13] arm: mvebu: Move CONFIG_SPL_LDSCRIPT to common header
This way, new MVEBU boards don't need to specifiy the common location for the SPL linker script. Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: None arch/arm/mach-mvebu/include/mach/config.h | 5 + include/configs/db-mv784mp-gp.h | 1 - include/configs/maxbcm.h | 1 - 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 86a0aed..b326ec0 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -85,4 +85,9 @@ #define CONFIG_SYS_I2C_SPEED 10 #endif +/* Common SPL configuration */ +#ifndef CONFIG_SPL_LDSCRIPT +#define CONFIG_SPL_LDSCRIPTarch/arm/mach-mvebu/u-boot-spl.lds +#endif + #endif /* __MVEBU_CONFIG_H */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 860e5f6..24cd42f 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -100,7 +100,6 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LDSCRIPTarch/arm/mach-mvebu/u-boot-spl.lds /* SPL related SPI defines */ #define CONFIG_SPL_SPI_SUPPORT diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 90b5912..496c2bd 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -100,7 +100,6 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LDSCRIPTarch/arm/mach-mvebu/u-boot-spl.lds /* SPL related SPI defines */ #define CONFIG_SPL_SPI_SUPPORT -- 2.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 12/13] arm: mvebu: Add d-cache invalidate before enabling the d-cache
This solves some RX problems that have been seen, when using the
mvneta ethernet driver. The cache needs to be reset into a clean
state before using it.
Signed-off-by: Stefan Roese s...@denx.de
---
Changes in v2: None
arch/arm/mach-mvebu/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 8058fad..04681fc 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -240,6 +240,9 @@ int cpu_eth_init(bd_t *bis)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
+ /* Avoid problem with e.g. neta ethernet driver */
+ invalidate_dcache_all();
+
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
--
2.3.5
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[U-Boot] [PATCH v2 01/13] arm: armada-xp: Move SoC sources to mach-mvebu
Move arch/arm/cpu/armv7armada-xp/* - arch/arm/mach-mvebu/*
Since this platform will be extended to support other Marvell SoC's as
well, lets rename it directly to mvebu.
This will be used by the upcoming Armada 38x suport (A38x).
Signed-off-by: Stefan Roese s...@denx.de
Cc: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2: None
arch/arm/Makefile | 1 +
arch/arm/cpu/armv7/Makefile | 1 -
arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/Makefile | 0
arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/cpu.c | 0
arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/lowlevel_spl.S | 0
arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/spl.c | 0
6 files changed, 1 insertion(+), 1 deletion(-)
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/Makefile (100%)
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/cpu.c (100%)
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/lowlevel_spl.S (100%)
rename arch/arm/{cpu/armv7/armada-xp = mach-mvebu}/spl.c (100%)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bd4749c..7bd53c5 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -48,6 +48,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_KEYSTONE)+= keystone
# TODO: rename CONFIG_KIRKWOOD - CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_ARMADA_XP)+= mvebu
# TODO: rename CONFIG_TEGRA - CONFIG_ARCH_TEGRA
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X - CONFIG_ARCH_ORION5X
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 21fc03b..2028e8c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -38,7 +38,6 @@ obj-y += s5p-common/
endif
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
-obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile
b/arch/arm/mach-mvebu/Makefile
similarity index 100%
rename from arch/arm/cpu/armv7/armada-xp/Makefile
rename to arch/arm/mach-mvebu/Makefile
diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/mach-mvebu/cpu.c
similarity index 100%
rename from arch/arm/cpu/armv7/armada-xp/cpu.c
rename to arch/arm/mach-mvebu/cpu.c
diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
b/arch/arm/mach-mvebu/lowlevel_spl.S
similarity index 100%
rename from arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
rename to arch/arm/mach-mvebu/lowlevel_spl.S
diff --git a/arch/arm/cpu/armv7/armada-xp/spl.c b/arch/arm/mach-mvebu/spl.c
similarity index 100%
rename from arch/arm/cpu/armv7/armada-xp/spl.c
rename to arch/arm/mach-mvebu/spl.c
--
2.3.5
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[U-Boot] [PATCH v2 13/13] arm: mvebu: Add Armada A38x DB-88F6820-GP board support
This patch adds support for the Marvell DB-88F6820-GP Armada A38x evaluation board. Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash) Please note that this board support right now only supports the main U-Boot. Without the bin_hdr integration (DDR training etc). This will be added in a few days / weeks to complete this board port. But till then this U-Boot version can be run on the target via the original Marvell U-Boot via this command: tftpboot 400 db-88f6820-gp/u-boot.bin;go 400 Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: - Update to 256KiB env sector as required for M25P128 - Add I2C IO expander initialization (fan etc) - Enable PL310 L2 cache as this is needed for correct caching OPs arch/arm/Kconfig| 6 ++ board/Marvell/db-88f6820-gp/Kconfig | 15 board/Marvell/db-88f6820-gp/Makefile| 7 ++ board/Marvell/db-88f6820-gp/binary.0| 16 + board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 103 board/Marvell/db-88f6820-gp/kwbimage.cfg| 12 configs/db-88f6820-gp_defconfig | 2 + include/configs/db-88f6820-gp.h | 72 +++ 8 files changed, 233 insertions(+) create mode 100644 board/Marvell/db-88f6820-gp/Kconfig create mode 100644 board/Marvell/db-88f6820-gp/Makefile create mode 100644 board/Marvell/db-88f6820-gp/binary.0 create mode 100644 board/Marvell/db-88f6820-gp/db-88f6820-gp.c create mode 100644 board/Marvell/db-88f6820-gp/kwbimage.cfg create mode 100644 configs/db-88f6820-gp_defconfig create mode 100644 include/configs/db-88f6820-gp.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..96b3f0c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -118,6 +118,11 @@ config KIRKWOOD bool Marvell Kirkwood select CPU_ARM926EJS +config TARGET_DB_88F6820_GP + bool Support DB-88F6820-GP + select CPU_V7 + select SUPPORT_SPL + config TARGET_DB_MV784MP_GP bool Support db-mv784mp-gp select CPU_V7 @@ -780,6 +785,7 @@ source board/BuR/kwb/Kconfig source board/BuR/tseries/Kconfig source board/CarMediaLab/flea3/Kconfig source board/Marvell/aspenite/Kconfig +source board/Marvell/db-88f6820-gp/Kconfig source board/Marvell/db-mv784mp-gp/Kconfig source board/Marvell/gplugd/Kconfig source board/altera/socfpga/Kconfig diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig new file mode 100644 index 000..b2e9115 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DB_88F6820_GP + +config SYS_BOARD + default db-88f6820-gp + +config SYS_VENDOR + default Marvell + +config SYS_SOC + default mvebu + +config SYS_CONFIG_NAME + default db-88f6820-gp + +endif diff --git a/board/Marvell/db-88f6820-gp/Makefile b/board/Marvell/db-88f6820-gp/Makefile new file mode 100644 index 000..58d40dd --- /dev/null +++ b/board/Marvell/db-88f6820-gp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese s...@denx.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-88f6820-gp.o diff --git a/board/Marvell/db-88f6820-gp/binary.0 b/board/Marvell/db-88f6820-gp/binary.0 new file mode 100644 index 000..57a4cbf --- /dev/null +++ b/board/Marvell/db-88f6820-gp/binary.0 @@ -0,0 +1,16 @@ + +WARNING: + +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. + +In a few weeks, mainline U-Boot will get support to generate the +bin_hdr with the DDR training code itself. By implementing this code +as SPL U-Boot. Then this file will not be needed any more and will +get removed. diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c new file mode 100644 index 000..51ac495 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2015 Stefan Roese s...@denx.de + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include i2c.h +#include miiphy.h +#include asm/io.h +#include asm/arch/cpu.h +#include asm/arch/soc.h + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr)(1UL (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * u-boot-2013.01-2014_T3.0 + */ +#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \ + (~(BIT(1) | BIT(4) | BIT(6) |
[U-Boot] [PATCH v2 10/13] arm: mvebu: Add dynamic SoC detection to mbus driver
This enables the mbus driver to also support other, newer Armada SoC platforms. Like the newly added Armada 38x support. Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: None arch/arm/mach-mvebu/mbus.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 05c9ef2..72cbd21 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -341,9 +341,8 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) w = mbus_dram_info.cs[cs++]; w-cs_index = i; w-mbus_attr = 0xf ~(1 i); -#if defined(CONFIG_ARMADA_XP) - w-mbus_attr |= ATTR_HW_COHERENCY; -#endif + if (mvebu_soc_family() == MVEBU_SOC_AXP) + w-mbus_attr |= ATTR_HW_COHERENCY; w-base = base DDR_BASE_CS_LOW_MASK; w-size = (size | ~DDR_SIZE_MASK) + 1; } -- 2.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/13] arm: mvebu: Only define MV88F78X60 for Armada XP
This define is used by the DDR training code for Armada XP. With the upcoming addition of Armada 38x support, lets only define it for Armada XP in this common header. Signed-off-by: Stefan Roese s...@denx.de --- Changes in v2: None arch/arm/mach-mvebu/include/mach/config.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 01b725b..86a0aed 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -9,7 +9,7 @@ /* * This file should be included in board config header file. * - * It supports common definitions for Armada XP platforms + * It supports common definitions for MVEBU platforms */ #ifndef _MVEBU_CONFIG_H @@ -17,7 +17,9 @@ #include asm/arch/soc.h +#if defined(CONFIG_ARMADA_XP) #define MV88F78X60 /* for the DDR training bin_hdr code */ +#endif #define CONFIG_SYS_CACHELINE_SIZE 32 -- 2.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2
-Original Message- From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Alison Wang Sent: Thursday, March 12, 2015 9:02 AM To: Sun York-R58495; u-boot@lists.denx.de; Jin Zhengxiong-R64188 Subject: [U-Boot] [PATCH v2 2/2] arm: ls102xa: Enable regulation of outstanding read transactions for slave interface S2 Patch subject is too long. Please try to make it = 78 charecters. This patch will enable regulation of outstanding read transactions for slave interface S2 for silicon VER1.0. It is already a patch. So please avoid This patch --prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On Tue, 2015-04-14 at 16:33 +0200, Jan Kiszka wrote: On 2015-04-14 16:30, Ian Campbell wrote: On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Can this be done selectively for the TK1 only? Well, you might need to add the mechanism for inserting it into the default bootenv, but I don't think that should be too hard at either the tegra or more generic levels. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2] ARM: tegra: enable STDIO deregistration
From: Stephen Warren swar...@nvidia.com At the very least when USB keyboard support is enabled, we need to enable CONFIG_SYS_STDIO_DEREGISTER, so the usb reset is able to re-scan USB ports and find new devices. Enable it everywhere per request from Simon Glass. Signed-off-by: Stephen Warren swar...@nvidia.com --- v2: Always enable the option, and hence do so in a different file. Since v1 missed the v2015.04 release, here's v2 that implements the post release request from Simon right from the get-go. --- include/configs/tegra-common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2cf1f68404b1..7ae179235484 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -89,6 +89,9 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_STDIO_DEREGISTER +#endif /* * Miscellaneous configurable options -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 2015-04-14 16:40, Ian Campbell wrote: On Tue, 2015-04-14 at 16:33 +0200, Jan Kiszka wrote: On 2015-04-14 16:30, Ian Campbell wrote: On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Can this be done selectively for the TK1 only? Well, you might need to add the mechanism for inserting it into the default bootenv, but I don't think that should be too hard at either the tegra or more generic levels. Maybe this already works: diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8be..c1f6c24 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -56,6 +56,7 @@ fdt_high=\0 \ initrd_high=\0 \ BOOTENV \ + bootm_boot_mode=sec\0 \ BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) Will test later. Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2] nand: fix buffer alignment in new verification feature
From: Stephen Warren swar...@nvidia.com On systems with caches enabled, NAND I/O may need to flush/invalidate the cache during read/write operations. For this to work correctly, all buffers must be cache-aligned. Fix nand_verify*() to allocate aligned buffers. This prevents cache alignment warnings from being spewed when using U-Boot to write an updated version of itself to flash on NVIDIA Tegra Seaboard (after perturbation of stack/data layout in current u-boot-dm/next branch). I have validatd (executed) nand_verify(), but I don't think I've executed nand_verify_page_oob(); testing of that would be useful. Cc: Peter Tyser pty...@xes-inc.com Cc: Heiko Schocher h...@denx.de Cc: Scott Wood scottw...@freescale.com Fixes: 59b5a2ad83df (nand: Add verification functions) Signed-off-by: Stephen Warren swar...@nvidia.com --- v2: Use memalign() rather than ALLOC_CACHE_ALIGN_BUFFER() so that the buffer is allocated from the heap not on the stack, to reduce stack usage. --- drivers/mtd/nand/nand_util.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 12dd26a33fac..ee2c24df3b85 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -483,7 +483,7 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs) memcpy(vops, ops, sizeof(vops)); - vops.datbuf = malloc(verlen); + vops.datbuf = memalign(ARCH_DMA_MINALIGN, verlen); if (!vops.datbuf) return -ENOMEM; @@ -520,7 +520,7 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) int rval = 0; size_t verofs; size_t verlen = nand-writesize; - uint8_t *verbuf = malloc(verlen); + uint8_t *verbuf = memalign(ARCH_DMA_MINALIGN, verlen); if (!verbuf) return -ENOMEM; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/10] sunxi: Introduce a hidden ARCH_SUN6I Kconfig bool
sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
watchdog, etc.
This commit introduces a new hidden ARCH_SUN6I Kconfig bool which can be
used to check for these features avoiding the need for an ever growing list
of #if defined CONFIG_MACH_SUN?I conditionals as we add support for more
new style sunxi SoCs.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c| 18 +-
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 +-
arch/arm/cpu/armv7/sunxi/usbc.c | 4 ++--
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 12 ++--
arch/arm/include/asm/arch-sunxi/mmc.h | 3 +--
arch/arm/include/asm/arch-sunxi/timer.h | 8
board/sunxi/Kconfig | 9 +
board/sunxi/gmac.c | 6 +++---
drivers/mmc/sunxi_mmc.c | 3 +--
drivers/video/sunxi_display.c | 10 +-
10 files changed, 41 insertions(+), 34 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6471c6b..30d5974 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -173,7 +173,15 @@ void board_init_f(ulong dummy)
void reset_cpu(ulong addr)
{
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) ||
defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_ARCH_SUN6I
+ static const struct sunxi_wdog *wdog =
+((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)-wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_CFG_RESET, wdog-cfg);
+ writel(WDT_MODE_EN, wdog-mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, wdog-ctl);
+#else
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)-wdog;
@@ -185,14 +193,6 @@ void reset_cpu(ulong addr)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, wdog-mode);
}
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
- static const struct sunxi_wdog *wdog =
-((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)-wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_CFG_RESET, wdog-cfg);
- writel(WDT_MODE_EN, wdog-mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, wdog-ctl);
#endif
}
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index b6cb9de..c3ec20d 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -76,7 +76,7 @@ int print_cpuinfo(void)
int sunxi_get_sid(unsigned int *sid)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_ARCH_SUN6I
#ifdef CONFIG_AXP221_POWER
return axp221_get_sid(sid);
#else
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index 80e4fc9..85b3448 100644
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -218,7 +218,7 @@ void sunxi_usbc_enable(int index)
setbits_le32(ccm-usb_clk_cfg, sunxi_usbc-usb_rst_mask);
setbits_le32(ccm-ahb_gate0, sunxi_usbc-ahb_clk_mask);
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_ARCH_SUN6I
setbits_le32(ccm-ahb_reset0_cfg, sunxi_usbc-ahb_clk_mask);
#endif
@@ -238,7 +238,7 @@ void sunxi_usbc_disable(int index)
if (sunxi_usbc-id != 0)
sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN);
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_ARCH_SUN6I
clrbits_le32(ccm-ahb_reset0_cfg, sunxi_usbc-ahb_clk_mask);
#endif
clrbits_le32(ccm-ahb_gate0, sunxi_usbc-ahb_clk_mask);
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index dae6069..3360e87 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -37,7 +37,7 @@
#define SUNXI_MMC1_BASE0x01c1
#define SUNXI_MMC2_BASE0x01c11000
#define SUNXI_MMC3_BASE0x01c12000
-#if !defined CONFIG_MACH_SUN6I !defined CONFIG_MACH_SUN8I
+#ifndef CONFIG_ARCH_SUN6I
#define SUNXI_USB0_BASE0x01c13000
#define SUNXI_USB1_BASE0x01c14000
#endif
@@ -45,15 +45,15 @@
#define SUNXI_HDMI_BASE0x01c16000
#define SUNXI_SPI2_BASE0x01c17000
#define SUNXI_SATA_BASE0x01c18000
-#if !defined CONFIG_MACH_SUN6I !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_ARCH_SUN6I
+#define SUNXI_USB0_BASE0x01c19000
+#define SUNXI_USB1_BASE
[U-Boot] [PATCH 02/10] sunxi: usbc: Remove unused irq field
We do not use irqs in u-boot so remove the unused irq field, and all the
#ifdef-ery around the irq initialization.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/usbc.c | 16
1 file changed, 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index a0e9604..80e4fc9 100644
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -42,38 +42,22 @@ static struct sunxi_usbc_hcd {
int ahb_clk_mask;
int gpio_vbus;
int gpio_vbus_det;
- int irq;
int id;
} sunxi_usbc_hcd[] = {
{
.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
.ahb_clk_mask = 1 AHB_GATE_OFFSET_USB0,
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
- .irq = 71,
-#else
- .irq = 38,
-#endif
.id = 0,
},
{
.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
.ahb_clk_mask = 1 AHB_GATE_OFFSET_USB_EHCI0,
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
- .irq = 72,
-#else
- .irq = 39,
-#endif
.id = 1,
},
#if (CONFIG_USB_MAX_CONTROLLER_COUNT 1)
{
.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
.ahb_clk_mask = 1 AHB_GATE_OFFSET_USB_EHCI1,
-#ifdef CONFIG_MACH_SUN6I
- .irq = 74,
-#else
- .irq = 40,
-#endif
.id = 2,
}
#endif
--
2.3.4
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Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 2015-04-14 16:30, Ian Campbell wrote: On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Can this be done selectively for the TK1 only? Also, Thierry, what is the time frame for the upstream fix? Is it lined up for 4.1? Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10] sunxi: Also set Auxiliary Ctl SMP bit in SPL
There is no reason not to and this make the #ifdef-ery easier to read. Signed-off-by: Hans de Goede hdego...@redhat.com --- arch/arm/cpu/armv7/sunxi/board.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index c1b4cf5..6471c6b 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -94,8 +94,9 @@ void s_init(void) * access gets messed up (seems cache related) */ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); #endif -#if !defined CONFIG_SPL_BUILD (defined CONFIG_MACH_SUN7I || \ - defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) +#if defined CONFIG_MACH_SUN6I || \ +defined CONFIG_MACH_SUN7I || \ +defined CONFIG_MACH_SUN8I /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( mrc p15, 0, r0, c1, c0, 1\n -- 2.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/10] sunxi: Add softwinner astar mid756 A33 tablet board defconfig
From: Vishnu Patekar vishnupatekar0...@gmail.com The Astar MID756 is a 7 tablet using the A33 SoC with a 800x480 LCD screen, 512M RAM, 8G ROM and integrated sdio wifi. Also see: http://linux-sunxi.org/Softwinner_astar-rda Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com Signed-off-by: Hans de Goede hdego...@redhat.com --- board/sunxi/MAINTAINERS| 5 + configs/Astar_MID756_defconfig | 25 + 2 files changed, 30 insertions(+) create mode 100644 configs/Astar_MID756_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index f368d6f..eb3675f 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -61,6 +61,11 @@ M: Paul Kocialkowski cont...@paulk.fr S: Maintained F: configs/Ampe_A76_defconfig +Astar MID756 BOARD +M: VishnuPatekar vishnupatekar0...@gmail.com +S: Maintained +F: configs/Astar_MID756_defconfig + COLOMBUS BOARD M: Maxime Ripard maxime.rip...@free-electrons.com S: Maintained diff --git a/configs/Astar_MID756_defconfig b/configs/Astar_MID756_defconfig new file mode 100644 index 000..2634a27 --- /dev/null +++ b/configs/Astar_MID756_defconfig @@ -0,0 +1,25 @@ +# The Astar MID756 is a 7 tablet using the A33 SoC with a 800x480 LCD screen, +# 512M RAM, 8G ROM and integrated sdio wifi. +# +# Also see: http://linux-sunxi.org/Softwinner_astar-rda +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5 +CONFIG_FDTFILE=sun8i-a33-astar-mid756.dtb +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN=AXP0-VBUS-ENABLE +CONFIG_USB0_VBUS_DET=AXP0-VBUS-DETECT +CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0 +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER=PH7 +CONFIG_VIDEO_LCD_BL_EN=PH6 +CONFIG_VIDEO_LCD_BL_PWM=PH0 +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=480 +# zq = 0x3bbb +CONFIG_DRAM_ZQ=15291 +# Wifi power +CONFIG_AXP221_DLDO1_VOLT=3300 +# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP +CONFIG_AXP221_ALDO1_VOLT=3000 -- 2.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/4] mtd: nand: mxs: Add comment for calculating ECC strength
Hello Heiko,
On Di, 2015-04-14 at 10:02 +0200, Heiko Schocher wrote:
Hello Jörg,
Am 14.04.2015 08:29, schrieb Jörg Krause:
Hello Heiko,
On Di, 2015-04-14 at 08:12 +0200, Heiko Schocher wrote:
Hello Jörg,
Am 13.04.2015 22:17, schrieb Jörg Krause:
Signed-off-by: Jörg Krause joerg.krause@embedded.rocks
---
drivers/mtd/nand/mxs_nand.c | 7 +++
1 file changed, 7 insertions(+)
nitpick only ...
I'm unsure what this comment means translated to German. Something
like small changes only?
Yes, something like pingelig
Okay, now I understand the translation but not the meaning. Do you
mean that this patch should be squashed into patch 1 for example?
diff --git a/drivers/mtd/nand/mxs_nand.c
b/drivers/mtd/nand/mxs_nand.c
index 912fed8..76e47ab 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -148,6 +148,13 @@ static inline uint32_t
mxs_nand_get_ecc_strength(uint32_t page_data_size,
{
int ecc_strength;
+ /* Determine the ECC layout with the formula:
wrong comment style ... please fix also in patch 4/4... thanks.
Checkpatch did not complain and I did not know there is a coding
style
for comments. Should it be:
/*
* Determine the ECC layout...
Yes.
See: linux:/Documentation/CodingStyle search for
The preferred style for long (multi-line) comments is
Thanks! So shall I send a v3 for this patch or will this be fixed by a
maintainer?
Best regards
Jörg Krause
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Re: [U-Boot] [PATCH v2 2/3] ARM: zynq: use separate configuration for ZC702 and ZC706
On Tue, 2015-04-14 at 04:50PM +0900, Masahiro Yamada wrote:
Separate CONFIG_TARGET_ZYNQ_{ZC702,ZC706} which is necessary
for the next commit. Adjust doc/README.zynq too.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2: None
arch/arm/cpu/armv7/zynq/Kconfig| 9 ++---
configs/{zynq_zc70x_defconfig = zynq_zc702_defconfig} | 2 +-
configs/zynq_zc706_defconfig | 11 +++
doc/README.zynq| 15 ---
4 files changed, 22 insertions(+), 15 deletions(-)
rename configs/{zynq_zc70x_defconfig = zynq_zc702_defconfig} (88%)
create mode 100644 configs/zynq_zc706_defconfig
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig
index 3a52535..ab4768a 100644
--- a/arch/arm/cpu/armv7/zynq/Kconfig
+++ b/arch/arm/cpu/armv7/zynq/Kconfig
@@ -9,8 +9,11 @@ config TARGET_ZYNQ_ZED
config TARGET_ZYNQ_MICROZED
bool Zynq MicroZed
-config TARGET_ZYNQ_ZC70X
- bool Zynq ZC702/ZC706 Board
+config TARGET_ZYNQ_ZC702
+ bool Zynq ZC702 Board
+
+config TARGET_ZYNQ_ZC706
+ bool Zynq ZC706 Board
Is there a good way to make this more friendly towards a user who is
familiar with the current flow? By simply removing it, we'll get plenty
of support requests asking what happened. Also, it would void all the
documentation we have in wikis etc. A more soft migration path would be
better.
Sören
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[U-Boot] [PATCH 10/10] sunxi: Add Ippo_q8h_v1_2_a33_1024x600 defconfig
Add a defconfig for generic 7 tablets using the Ippo q8h v1.2 pcb, with an A33 SoC (the pcb can take an A23 or an A33), and a 1024x600 LCD. Signed-off-by: Hans de Goede hdego...@redhat.com --- board/sunxi/MAINTAINERS | 1 + configs/Ippo_q8h_v1_2_a33_1024x600_defconfig | 23 +++ 2 files changed, 24 insertions(+) create mode 100644 configs/Ippo_q8h_v1_2_a33_1024x600_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index eb3675f..9f6bd13 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -38,6 +38,7 @@ F:configs/qt840a_defconfig F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h F: configs/Ippo_q8h_v1_2_defconfig +F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki nao...@gmail.com diff --git a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig new file mode 100644 index 000..52a390d --- /dev/null +++ b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig @@ -0,0 +1,23 @@ +# This is a defconfig for generic 7 tablets using the Ippo q8h v1.2 pcb, +# with an A33 SoC (the pcb can take an A23 or an A33), and a 1024x600 LCD +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5 +CONFIG_FDTFILE=sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN=AXP0-VBUS-ENABLE +CONFIG_USB0_VBUS_DET=AXP0-VBUS-DETECT +CONFIG_VIDEO_LCD_MODE=x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0 +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER=PH7 +CONFIG_VIDEO_LCD_BL_EN=PH6 +CONFIG_VIDEO_LCD_BL_PWM=PH0 +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=480 +# zq = 0x3bbb +CONFIG_DRAM_ZQ=15291 +# Wifi power +CONFIG_AXP221_DLDO1_VOLT=3300 +# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP +CONFIG_AXP221_ALDO1_VOLT=3000 -- 2.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/10] sunxi: Fix end of kernel memory alignment for A33
For unknown reasons the A33 needs the end of the memory we report to the
kernel to be aligned to a multiple of 4 MiB. Without this things will hang
when we hand over control to the kernel.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/sunxi_display.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index e132b75..7a63094 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -1275,6 +1275,15 @@ int sunxi_simplefb_setup(void *blob)
*/
start = gd-bd-bi_dram[0].start;
size = gd-bd-bi_dram[0].size - sunxi_display.fb_size;
+ /*
+* For unknown reasons the A33 needs the end of the memory we report to
+* the kernel to be aligned to a multiple of 4 MiB. Without this things
+* will hang when we hand over control to the kernel.
+*/
+#ifdef CONFIG_MACH_SUN8I_A33
+ size = ~(4 * 1024 * 1024 - 1);
+#endif
+
ret = fdt_fixup_memory_banks(blob, start, size, 1);
if (ret) {
eprintf(Cannot setup simplefb: Error reserving memory\n);
--
2.3.4
___
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[U-Boot] [PATCH 08/10] sunxi: Add basic A33 basic support
From: Vishnu Patekar vishnupatekar0...@gmail.com
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 4
arch/arm/cpu/armv7/sunxi/board.c| 8 +---
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++
arch/arm/cpu/armv7/sunxi/rsb.c | 2 +-
arch/arm/cpu/armv7/sunxi/usbc.c | 8
board/sunxi/Kconfig | 19 ++-
board/sunxi/board.c | 4 ++--
drivers/power/Kconfig | 4 ++--
drivers/usb/musb-new/musb_regs.h| 5 +
drivers/video/sunxi_display.c | 3 +++
include/configs/sunxi-common.h | 3 ++-
11 files changed, 48 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index b2e5e5d..b299635 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -16,15 +16,18 @@ obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I_A23) += prcm.o
+obj-$(CONFIG_MACH_SUN8I_A33) += prcm.o
obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN8I_A23) += rsb.o
+obj-$(CONFIG_MACH_SUN8I_A33) += rsb.o
obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN8I_A23) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN8I_A33) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
ifndef CONFIG_SPL_BUILD
@@ -39,5 +42,6 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
+obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-y += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 7ce79af..283e3ab 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,7 +46,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I_A23)
+#if defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
#else
@@ -70,7 +70,8 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 defined(CONFIG_MACH_SUN8I_A23)
+#elif CONFIG_CONS_INDEX == 5 \
+(defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33))
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
@@ -96,7 +97,8 @@ void s_init(void)
#endif
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
-defined CONFIG_MACH_SUN8I_A23
+defined CONFIG_MACH_SUN8I_A23 || \
+defined CONFIG_MACH_SUN8I_A33
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
mrc p15, 0, r0, c1, c0, 1\n
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 6143038..fda62ab 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -66,6 +66,8 @@ int print_cpuinfo(void)
puts(CPU: Allwinner A20 (SUN7I)\n);
#elif defined CONFIG_MACH_SUN8I_A23
puts(CPU: Allwinner A23 (SUN8I)\n);
+#elif defined CONFIG_MACH_SUN8I_A33
+ puts(CPU: Allwinner A33 (SUN8I)\n);
#else
#warning Please update cpu_info.c with correct CPU information
puts(CPU: SUNXI Family\n);
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index d8d4957..076592b 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void);
static void rsb_cfg_io(void)
{
-#if defined CONFIG_MACH_SUN8I_A23
+#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index 85b3448..515549d 100644
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -28,7 +28,11 @@
#endif
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
+#ifdef CONFIG_MACH_SUN8I_A33
+#define SUNXI_USB_CSR
[U-Boot] [PATCH 04/10] sunxi: s/sun8i/sun8i_a23/
This is a preparation patch for adding A33 support, which will have a mach
name of sun8i-a33.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 8
arch/arm/cpu/armv7/sunxi/board.c | 8
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 +-
.../cpu/armv7/sunxi/{dram_sun8i.c = dram_sun8i_a23.c}| 0
arch/arm/cpu/armv7/sunxi/rsb.c| 2 +-
arch/arm/include/asm/arch-sunxi/clock.h | 3 ++-
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 +++---
arch/arm/include/asm/arch-sunxi/dram.h| 4 ++--
.../asm/arch-sunxi/{dram_sun8i.h = dram_sun8i_a23.h} | 0
board/sunxi/Kconfig | 15 ---
board/sunxi/board.c | 4 ++--
configs/Ippo_q8h_v1_2_defconfig | 2 +-
configs/Ippo_q8h_v5_defconfig | 2 +-
drivers/power/Kconfig | 4 ++--
include/configs/sunxi-common.h| 2 +-
15 files changed, 32 insertions(+), 30 deletions(-)
rename arch/arm/cpu/armv7/sunxi/{dram_sun8i.c = dram_sun8i_a23.c} (100%)
rename arch/arm/include/asm/arch-sunxi/{dram_sun8i.h = dram_sun8i_a23.h}
(100%)
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 4bb12ad..b2e5e5d 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -15,16 +15,16 @@ obj-y += dram_helpers.o
obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
-obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN8I_A23) += prcm.o
obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
-obj-$(CONFIG_MACH_SUN8I) += rsb.o
+obj-$(CONFIG_MACH_SUN8I_A23) += rsb.o
obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN8I_A23) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
ifndef CONFIG_SPL_BUILD
@@ -38,6 +38,6 @@ obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
+obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-y += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 30d5974..7ce79af 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,7 +46,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN8I_A23)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
#else
@@ -70,7 +70,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 defined(CONFIG_MACH_SUN8I)
+#elif CONFIG_CONS_INDEX == 5 defined(CONFIG_MACH_SUN8I_A23)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
@@ -89,14 +89,14 @@ void spl_board_load_image(void)
void s_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
-defined CONFIG_MACH_SUN8I
+defined CONFIG_MACH_SUN8I_A23
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
mrc p15, 0, r0, c1, c0, 1\n
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index c3ec20d..6143038 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -64,7 +64,7 @@ int print_cpuinfo(void)
}
#elif defined CONFIG_MACH_SUN7I
puts(CPU: Allwinner A20 (SUN7I)\n);
-#elif defined CONFIG_MACH_SUN8I
+#elif defined CONFIG_MACH_SUN8I_A23
puts(CPU: Allwinner A23 (SUN8I)\n);
#else
#warning Please update cpu_info.c
[U-Boot] [PATCH 05/10] sunxi: Add support for A33 PLL11 (second DRAM pll)
Add support for the new second DRAM PLL found on the A33 SoC.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 18 +++
arch/arm/include/asm/arch-sunxi/clock.h | 3 ++-
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 33 +++
3 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index e2a7867..3bfa122 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -170,6 +170,24 @@ void clock_set_pll5(unsigned int clk, bool
sigma_delta_enable)
udelay(5500);
}
+#ifdef CONFIG_MACH_SUN8I_A33
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (sigma_delta_enable)
+ writel(CCM_PLL11_PATTERN, ccm-pll5_pattern_cfg);
+
+ writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
+ (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
+ CCM_PLL11_CTRL_N(clk / 2400), ccm-pll11_cfg);
+
+ while (readl(ccm-pll11_cfg) CCM_PLL11_CTRL_UPD)
+ ;
+}
+#endif
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index ad4fb26..8d1eebe 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -16,7 +16,8 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN6I) || \
-defined(CONFIG_MACH_SUN8I_A23)
+defined(CONFIG_MACH_SUN8I_A23) || \
+defined(CONFIG_MACH_SUN8I_A33)
#include asm/arch/clock_sun6i.h
#elif defined(CONFIG_MACH_SUN9I)
#include asm/arch/clock_sun9i.h
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d625970..c88b140 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -31,7 +31,7 @@ struct sunxi_ccm_reg {
u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
u32 pll9_cfg; /* 0x44 pll9 control */
u32 pll10_cfg; /* 0x48 pll10 control */
- u32 reserved8;
+ u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */
u32 cpu_axi_cfg;/* 0x50 CPU/AXI divide ratio */
u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
u32 apb2_div; /* 0x58 APB2 divide ratio */
@@ -63,7 +63,8 @@ struct sunxi_ccm_reg {
u32 reserved12[7];
u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
- u32 reserved13[2];
+ u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
+ u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
u32 dram_clk_gate; /* 0x100 DRAM module gating */
u32 be0_clk_cfg;/* 0x104 BE0 module clock */
u32 be1_clk_cfg;/* 0x108 BE1 module clock */
@@ -126,7 +127,9 @@ struct sunxi_ccm_reg {
u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
- u32 reserved22[5];
+ u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
+ u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
+ u32 reserved22[3];
u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
@@ -195,6 +198,11 @@ struct sunxi_ccm_reg {
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL11_CTRL_N(n)n) - 1) 0x3f) 8)
+#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 24)
+#define CCM_PLL11_CTRL_UPD (0x1 30)
+#define CCM_PLL11_CTRL_EN (0x1 31)
+
#define AHB1_ABP1_DIV_DEFAULT 0x2020
#define AXI_GATE_OFFSET_DRAM 0
@@ -216,6 +224,7 @@ struct sunxi_ccm_reg {
/* ahb_gate1 offsets */
#define AHB_GATE_OFFSET_DRC0 25
+#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
@@ -248,12 +257,23 @@ struct sunxi_ccm_reg {
#define MDFS_CLK_DEFAULT 0x8102 /* PLL6 / 3 */
+#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK (0xf 0)
#define CCM_DRAMCLK_CFG_DIV0(x)((x - 1) 8)
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf 8)
#define CCM_DRAMCLK_CFG_UPD(0x1 16)
#define CCM_DRAMCLK_CFG_RST
Re: [U-Boot] [PATCH v3 1/3] dm: usb: Move descriptor setup code into its own function
On 04/13/2015 09:19 PM, Simon Glass wrote: usb_new_device() is far too long and does far too much. As a first step, move the code that does initial setup and reads a descriptor into its own function called usb_setup_descriptor(). For XHCI the init order is different - we set up the device but don't actually read the descriptor until after we set an address. Support this option as a parameter to usb_setup_descriptor(). Avoid changing this torturous code more than necessary to make it easy to review. The series, Tested-by: Stephen Warren swar...@nvidia.com Note that what I actually tested was the commits in u-boot-dm/next, which in another email you mentioned included these patches. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/2] i2c: sunxi: Support every i2c controller on each supported platform
This version is ready for merging by the way. I didn't use Kconfig after all, since all the Marvell boards are including this through config.h and I didn't feel like moving it all to Kconfig. Moreover, this doesn't use DM and apparently, only I2C drivers that use DM are in Kconfig now. Also, I don't think it makes sense to make twsi0 more privileged than the other controllers. Users might just need to enable, say, controller 1, without enabling controller 0 on sunxi. Le vendredi 10 avril 2015 à 23:09 +0200, Paul Kocialkowski a écrit : Changes since v4: * Got rid of Kconfig after all * Only build mvtwsi when at least one controller is enabled on sunxi * Controller 0 doesn't have to be enabled in particular Changes since v3: * Kconfig support for MVTWSI * Only enable twsi0 by default for platforms that always use it for the AXP * Remove enabling other I2C busses by default on boards that expose them on pin headers since those might be used for some other functionalities Changes since v2: * I2C/TWI busses enable for Cubietruck as well Changes since v1: * Kconfig option to enable I2C/TWI controllers 1-4 (when applicable) * Following patch to enable exposed busses on a few community-supported single-board-computers This series adds support for every i2c controller found on sun4i/sun5i/sun6i/sun7i/sun8i platforms and shouldn't break support for Marvell platforms (orion5x, kirkwood, armada xp) the driver was originally written for. Regarding sunxi, I double-checked that this doesn't conflict with VIDEO_LCD_PANEL_I2C. I would be interested in having this tested on sun8i (A23), since I changed TWI0 muxing (to PH2-PH3 instead of PB0-PB1), according to the user manual and what is being done on the upstream Linux kernel. I2C was either not working before, or it was being muxed correctly by the bootrom, probably to communicate with the AXP, which luckily made it work in U-Boot too, since the I/O base address was already correct. My use case here is that I'm writing a slave-side bitbang i2c implementation (with an Arduino) for a school project, using a Cubieboard2 as master and U-Boot as POC. However, only TWI1 was available through the expansion pins, hence the need for this series. signature.asc Description: This is a digitally signed message part ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 04/14/2015 08:30 AM, Ian Campbell wrote: On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Yes, if there's already an environment variable that controls the behaviour, that'd be even better. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 04/14/2015 08:12 AM, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. So we can either leave out the last patch for now and wait until the cpu-idle fix is upstream or tell the people picking upstream u-boot to turn either virt support in u-boot on or CPU_IDLE in the kernel off (just tell me where to put such a note). We should definitely not enable support by default if it requires kernel changes. If someone wants to use the feature, they should edit the source to enable it. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 04/14/2015 08:45 AM, Jan Kiszka wrote: On 2015-04-14 16:40, Ian Campbell wrote: On Tue, 2015-04-14 at 16:33 +0200, Jan Kiszka wrote: On 2015-04-14 16:30, Ian Campbell wrote: On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Can this be done selectively for the TK1 only? Well, you might need to add the mechanism for inserting it into the default bootenv, but I don't think that should be too hard at either the tegra or more generic levels. Maybe this already works: diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8be..c1f6c24 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -56,6 +56,7 @@ fdt_high=\0 \ initrd_high=\0 \ BOOTENV \ + bootm_boot_mode=sec\0 \ BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) That will add the variable for all boards, even when the feature isn't enabled. You should either: * Modify jetson-tk1.h to add that value to BOARD_EXTRA_ENV_SETTINGS. * Better: Modify tegra-common-post.h to do something like: #ifdef whatever_enables_the_psci_feature_etc #define PSCI_EXTRA_ENV_SETTINGS bootm_boot_mode=sec\0 #else #define PSCI_EXTRA_ENV_SETTINGS #endif ... and add PSCI_EXTRA_ENV_SETTINGS into the value of CONFIG_EXTRA_ENV_SETTINGS. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 10/13] arm: mvebu: Add dynamic SoC detection to mbus driver
Dear Stefan Roese, On Tue, 14 Apr 2015 12:46:52 +0200, Stefan Roese wrote: + if (mvebu_soc_family() == MVEBU_SOC_AXP) + w-mbus_attr |= ATTR_HW_COHERENCY; Why is this Armada XP specific? Both Armada XP and Armada 38x support HW I/O coherency. But are you actually using HW I/O coherency in U-Boot for Armada XP ? It would probably be simpler to not use HW I/O coherency at all in U-Boot, be it for AXP or A38x. Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. So we can either leave out the last patch for now and wait until the cpu-idle fix is upstream or tell the people picking upstream u-boot to turn either virt support in u-boot on or CPU_IDLE in the kernel off (just tell me where to put such a note). Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 2015-04-14 16:50, Stephen Warren wrote: On 04/14/2015 08:45 AM, Jan Kiszka wrote: On 2015-04-14 16:40, Ian Campbell wrote: On Tue, 2015-04-14 at 16:33 +0200, Jan Kiszka wrote: On 2015-04-14 16:30, Ian Campbell wrote: On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote: On 2015-04-14 16:06, Stephen Warren wrote: On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. Sorry, forgot to mention: I can't flip the default behaviour to leave virtualization support off only for the TK1. That's a generic default. Would enabling it in the compile but adding bootm_boot_mode=sec to the default environment (so it isn't used by default) be considered sufficiently backwards compatible? Can this be done selectively for the TK1 only? Well, you might need to add the mechanism for inserting it into the default bootenv, but I don't think that should be too hard at either the tegra or more generic levels. Maybe this already works: diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8be..c1f6c24 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -56,6 +56,7 @@ fdt_high=\0 \ initrd_high=\0 \ BOOTENV \ +bootm_boot_mode=sec\0 \ BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) That will add the variable for all boards, even when the feature isn't enabled. You should either: * Modify jetson-tk1.h to add that value to BOARD_EXTRA_ENV_SETTINGS. That issue should affect more boards than the TK1. * Better: Modify tegra-common-post.h to do something like: #ifdef whatever_enables_the_psci_feature_etc #define PSCI_EXTRA_ENV_SETTINGS bootm_boot_mode=sec\0 #else #define PSCI_EXTRA_ENV_SETTINGS #endif ... and add PSCI_EXTRA_ENV_SETTINGS into the value of CONFIG_EXTRA_ENV_SETTINGS. Yep, makes sense. Thanks, Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/10] sunxi: Add a33 dram init code
From: Vishnu Patekar vishnupatekar0...@gmail.com
Based on Allwinner dram init code from the a33 bsp:
https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c
Initial u-boot port by Vishnu Patekar, major cleanup / rewrite by
Hans de Goede.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c| 363 +++
arch/arm/include/asm/arch-sunxi/dram.h | 2 +
arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h | 179 +++
3 files changed, 544 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c
new file mode 100644
index 000..987fc5d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c
@@ -0,0 +1,363 @@
+/*
+ * Sun8i a33 platform dram controller init.
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang wangfl...@allwinnertech.com
+ * (C) Copyright 2015 Vishnu Patekar vishnupatekar0...@gmail.com
+ * (C) Copyright 2015 Hans de Goede hdego...@redhat.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/dram.h
+#include asm/arch/prcm.h
+
+/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
+#define DRAM_CLK_MUL 2
+#define DRAM_CLK_DIV 4
+#define DRAM_SIGMA_DELTA_ENABLE 1
+#define DRAM_ODT_EN 0
+
+struct dram_para {
+ u8 cs1;
+ u8 seq;
+ u8 bank;
+ u8 rank;
+ u8 rows;
+ u8 bus_width;
+ u16 page_size;
+};
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_CS1_CONTROL(para-cs1) | MCTL_CR_UNKNOWN |
+ MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+ (para-seq ? MCTL_CR_SEQUENCE : 0) |
+ ((para-bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
+ MCTL_CR_PAGE_SIZE(para-page_size) | MCTL_CR_ROW(para-rows) |
+ MCTL_CR_BANK(para-bank) | MCTL_CR_RANK(para-rank),
+ mctl_com-cr);
+}
+
+static void auto_detect_dram_size(struct dram_para *para)
+{
+ u8 orig_rank = para-rank;
+ int rows, columns;
+
+ /* Row detect */
+ para-page_size = 512;
+ para-seq = 1;
+ para-rows = 16;
+ para-rank = 1;
+ mctl_set_cr(para);
+ for (rows = 11 ; rows 16 ; rows++) {
+ if (mctl_mem_matches(1 (rows + 9))) /* row-column */
+ break;
+ }
+
+ /* Column (page size) detect */
+ para-rows = 11;
+ para-page_size = 8192;
+ mctl_set_cr(para);
+ for (columns = 9 ; columns 13 ; columns++) {
+ if (mctl_mem_matches(1 columns))
+ break;
+ }
+
+ para-seq = 0;
+ para-rank = orig_rank;
+ para-rows = rows;
+ para-page_size = 1 columns;
+ mctl_set_cr(para);
+}
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq =
+ CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
+
+ return (ctrl_freq * nanoseconds + 999) / 1000;
+}
+
+static void auto_set_timing_para(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ u32 reg_val;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc= ns_to_t(350);
+
+ /* Fixed timing parameters */
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1;/* 1us */
+
+ u8 twtp = tcwl + 2 +
Re: [U-Boot] [PATCH v6 00/15] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
On 04/14/2015 07:46 AM, Tom Rini wrote: On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote: Changes in v6: - rebased over master - included Thierry's SMMU enabling patch - moved activation patch at the end so that it can be held back This version can also be found at https://github.com/siemens/u-boot/tree/jetson-tk1-v6. So what level of coordination do we need on applying this series so that kernels (both old and new) can continue to function? And perhaps README updates or similar? Thanks! Hopefully this series doesn't change anything by default, and simply allows people to turn on support for booting kernels in non-secure mode if they want to? If so, there shouldn't be any co-ordination required. If it changes the default behaviour, co-ordination is probably required, and that'd be a bad thing. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
