[U-Boot] [PATCH 1/5] drivers:usb:dwc3: Add DWC3 controller driver support

[Ramneek Mehresh]

Add support for DWC3 XHCI controller driver

Signed-off-by: Ramneek Mehresh 
---
 drivers/usb/host/Makefile|  1 +
 drivers/usb/host/xhci-dwc3.c | 74 
 include/linux/usb/dwc3.h |  4 +++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/usb/host/xhci-dwc3.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7658f87..c0d95cf 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
new file mode 100644
index 000..a50d81a
--- /dev/null
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * DWC3 controller driver
+ *
+ * Author: Ramneek Mehresh
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+   clrsetbits_le32(&dwc3_reg->g_ctl,
+   DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+   DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+   /* Before Resetting PHY, put Core in Reset */
+   setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+   /* reset USB3 phy - if required */
+   usb_phy_reset(dwc3_reg);
+
+   /* After PHYs are stable we can take Core out of reset state */
+   clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+   u32 reg;
+   u32 revision;
+   unsigned int dwc3_hwparams1;
+
+   revision = readl(&dwc3_reg->g_snpsid);
+   /* This should read as U3 followed by revision number */
+   if ((revision & DWC3_GSNPSID_MASK) != 0x5533) {
+   puts("this is not a DesignWare USB3 DRD Core\n");
+   return -1;
+   }
+
+   dwc3_core_soft_reset(dwc3_reg);
+
+   dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+   reg = readl(&dwc3_reg->g_ctl);
+   reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+   reg &= ~DWC3_GCTL_DISSCRAMBLE;
+   switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+   case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+   reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+   break;
+   default:
+   debug("No power optimization available\n");
+   }
+
+   /*
+* WORKAROUND: DWC3 revisions <1.90a have a bug
+* where the device can fail to connect at SuperSpeed
+* and falls back to high-speed mode which causes
+* the device to enter a Connect/Disconnect loop
+*/
+   if ((revision & DWC3_REVISION_MASK) < 0x190a)
+   reg |= DWC3_GCTL_U2RSTECN;
+
+   writel(reg, &dwc3_reg->g_ctl);
+
+   return 0;
+}
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..c21878c 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -191,4 +191,8 @@ struct dwc3 {   /* 
offset: 0xC100 */
 #define DWC3_DCTL_CSFTRST  (1 << 30)
 #define DWC3_DCTL_LSFTRST  (1 << 29)
 
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void usb_phy_reset(struct dwc3 *dwc3_reg);
 #endif /* __DWC3_H_ */
-- 
1.8.3.1

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[U-Boot] [PATCH 2/5][v3]drivers:usb:fsl: Add XHCI driver support

[Ramneek Mehresh]

Add xhci driver support for all FSL socs

Signed-off-by: Ramneek Mehresh 
---
Changes for v3:
- use FSL_USB_XHCI_ADDR for controller addr
- corrected multiline comment

 drivers/usb/host/Makefile|   1 +
 drivers/usb/host/xhci-fsl.c  | 109 +++
 include/linux/usb/xhci-fsl.h |  54 +
 3 files changed, 164 insertions(+)
 create mode 100644 drivers/usb/host/xhci-fsl.c
 create mode 100644 include/linux/usb/xhci-fsl.h

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c0d95cf..7c94439 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..f624c90
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+   return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+   /* Assert USB3 PHY reset */
+   setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+   /* Assert USB2 PHY reset */
+   setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+   mdelay(200);
+
+   /* Clear USB3 PHY reset */
+   clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+   /* Clear USB2 PHY reset */
+   clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+   int ret = 0;
+
+   ret = dwc3_core_init(fsl_xhci->dwc3_reg);
+   if (ret) {
+   debug("%s:failed to initialize core\n", __func__);
+   return ret;
+   }
+
+   /* We are hard-coding DWC3 core to Host Mode */
+   dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+   return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+   /*
+* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs.
+*/
+   return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+   struct fsl_xhci *ctx = &fsl_xhci;
+   int ret = 0;
+
+   ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
+   ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+
+   ret = board_usb_init(index, USB_INIT_HOST);
+   if (ret != 0) {
+   puts("Failed to initialize board for USB\n");
+   return ret;
+   }
+
+   ret = fsl_xhci_core_init(ctx);
+   if (ret < 0) {
+   puts("Failed to initialize xhci\n");
+   return ret;
+   }
+
+   *hccr = (struct xhci_hccr *)ctx->hcd;
+   *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+   + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+   debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+   return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+   struct fsl_xhci *ctx = &fsl_xhci;
+
+   fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK   0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK  0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERONBIT(14)
+#define USB3_PHY_TX_POWERONBIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET BIT(17)
+#define USBOTGS

[U-Boot] [PATCH 3/5] arch:arm:fsl: Add XHCI support for LS1021A

[Ramneek Mehresh]

Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh 
---
 arch/arm/include/asm/arch-ls102xa/config.h|  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 6561ce6..f672341 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 
0x011c0500)
 #define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR + 
0x011d0500)
 #define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x0210)
 #define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 3a64afc..b5f570e 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -538,4 +538,14 @@ struct ccsr_cci400 {
} pcounter[4];  /* Performance Counter */
u8 res_e004[0x1 - 0xe004];
 };
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE  0x310
+#define FSL_OCP1_SCP_BASE  0x4a084c00
+#define FSL_OTG_WRAPPER_BASE   0x4A02
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR  CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR  0
+#define FSL_USB_XHCI_ADDR  {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+   CONFIG_SYS_FSL_XHCI_USB2_ADDR}
 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
-- 
1.8.3.1

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[U-Boot] [PATCH 4/5][v3]include:configs:ls1021atwr: Enable USB IP support

[Ramneek Mehresh]

Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform

Signed-off-by: Ramneek Mehresh 
---
Changes for v3:
- corrected multiline comment
- moved out xhci controller soc specific
  base addresse(s) to soc file

 include/configs/ls1021atwr.h | 38 ++
 1 file changed, 38 insertions(+)

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..a96bc22 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,44 @@
 #define CONFIG_SYS_INIT_RAM_SIZE   OCRAM_SIZE
 
 /*
+ * USB
+ */
+
+/*
+ * EHCI Support - disbaled by default as
+ * there is no signal coming out of soc on
+ * this board for this controller. However,
+ * the silicon still has this controller,
+ * and anyone can use this controller by
+ * taking signals out on their board.
+ */
+
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/* XHCI Support - enabled by default */
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
  * Generic Timer Definitions
  */
 #define GENERIC_TIMER_CLK  1250
-- 
1.8.3.1

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[U-Boot] [PATCH 5/5] include:configs:ls1021aqds: Enable USB IP support

[Ramneek Mehresh]

Enable USB IP support for both EHCI and XHCI for
ls1021aqds platform

Signed-off-by: Ramneek Mehresh 
---
 include/configs/ls1021aqds.h | 22 +-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5de416d..1aa2f94 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -423,19 +423,31 @@ unsigned long get_board_ddr_clk(void);
 /*
  * USB
  */
-#define CONFIG_HAS_FSL_DR_USB
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
 
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
 
-#ifdef CONFIG_USB_EHCI
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_CMD_EXT2
 #endif
-#endif
 
 /*
  * Video
-- 
1.8.3.1

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Re: [U-Boot] [PATCH 08/20] dm: Implement a CPU uclass

[Bin Meng]

Hi Simon,

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> It is useful to be able to keep track of the available CPUs in a multi-CPU
> system. This uclass is mostly intended for use with SMP systems.
>
> The uclass provides methods for getting basic information about each CPU.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/Kconfig  |  2 ++
>  drivers/Makefile |  1 +
>  drivers/cpu/Kconfig  |  8 +
>  drivers/cpu/Makefile |  7 
>  drivers/cpu/cpu-uclass.c | 61 +++
>  include/cpu.h| 84 
> 
>  include/dm/uclass-id.h   |  1 +
>  7 files changed, 164 insertions(+)
>  create mode 100644 drivers/cpu/Kconfig
>  create mode 100644 drivers/cpu/Makefile
>  create mode 100644 drivers/cpu/cpu-uclass.c
>  create mode 100644 include/cpu.h
>
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index 941aa0c..1f40887 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -2,6 +2,8 @@ menu "Device Drivers"
>
>  source "drivers/core/Kconfig"
>
> +source "drivers/cpu/Kconfig"
> +
>  source "drivers/demo/Kconfig"
>
>  source "drivers/pci/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 5ef58c0..405b64b 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -3,6 +3,7 @@ obj-$(CONFIG_DM_DEMO) += demo/
>  obj-$(CONFIG_BIOSEMU) += bios_emulator/
>  obj-y += block/
>  obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
> +obj-$(CONFIG_CPU) += cpu/

Should it be CONFIG_DM_CPU?

>  obj-y += crypto/
>  obj-$(CONFIG_FPGA) += fpga/
>  obj-y += hwmon/
> diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
> new file mode 100644
> index 000..23745e3
> --- /dev/null
> +++ b/drivers/cpu/Kconfig
> @@ -0,0 +1,8 @@
> +config CPU
> +   bool "Enable CPU drivers using Driver Model"
> +   help
> + This allows drivers to be provided for CPUs and their type to be
> + specified in the board's device tree. For boards which support
> + multiple CPUs, they normally have to be set up in U-Boot so that
> + they can work correctly in the OS. This provides a framework for
> + finding out information about available CPUs and making changes.
> diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
> new file mode 100644
> index 000..8710160
> --- /dev/null
> +++ b/drivers/cpu/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2015 Google, Inc
> +# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> +#
> +# SPDX-License-Identifier:  GPL-2.0+
> +#
> +obj-$(CONFIG_CPU) += cpu-uclass.o
> diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
> new file mode 100644
> index 000..ab18ee2
> --- /dev/null
> +++ b/drivers/cpu/cpu-uclass.c
> @@ -0,0 +1,61 @@
> +/*
> + * Copyright (C) 2015 Google, Inc
> + * Written by Simon Glass 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +int cpu_get_desc(struct udevice *dev, char *buf, int size)
> +{
> +   struct cpu_ops *ops = cpu_get_ops(dev);
> +
> +   if (!ops->get_desc)
> +   return -ENOSYS;
> +
> +   return ops->get_desc(dev, buf, size);
> +}
> +
> +int cpu_get_info(struct udevice *dev, struct cpu_info *info)
> +{
> +   struct cpu_ops *ops = cpu_get_ops(dev);
> +
> +   if (!ops->get_desc)
> +   return -ENOSYS;
> +
> +   return ops->get_info(dev, info);
> +}
> +
> +U_BOOT_DRIVER(cpu_bus) = {
> +   .name   = "cpu_bus",
> +   .id = UCLASS_SIMPLE_BUS,
> +   .per_child_platdata_auto_alloc_size = sizeof(struct cpu_platdata),
> +};
> +
> +static int uclass_cpu_init(struct uclass *uc)
> +{
> +   struct udevice *dev;
> +   int node;
> +   int ret;
> +
> +   node = fdt_path_offset(gd->fdt_blob, "/cpus");
> +   if (node < 0)
> +   return 0;
> +
> +   ret = device_bind_driver_to_node(dm_root(), "cpu_bus", "cpus", node,
> +&dev);
> +
> +   return ret;
> +}
> +
> +UCLASS_DRIVER(cpu) = {
> +   .id = UCLASS_CPU,
> +   .name   = "cpu",
> +   .flags  = DM_UC_FLAG_SEQ_ALIAS,
> +   .init   = uclass_cpu_init,
> +};
> diff --git a/include/cpu.h b/include/cpu.h
> new file mode 100644
> index 000..46467d0
> --- /dev/null
> +++ b/include/cpu.h
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + * Written by Simon Glass 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef __cpu_h
> +#define __cpu_h

Should be capital letters.

> +
> +/**
> + * struct cpu_platdata - platform data for a CPU
> + *
> + * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU
> + * device.
> + *
> + * @cpu_id:Platform-specific way of identifying the CPU.
> + */
> +struct cpu_platdata {
> +   int cpu_id;
> +};
> +
> +/* CPU features - mostly just a placeholder for now */
> +enum {
> +   CPU_FEAT_L1_

Re: [U-Boot] [PATCH 09/20] Add a 'cpu' command to print CPU information

[Bin Meng]

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> Add a simple command which provides access to a list of available CPUs along
> with descriptions and basic information.
>
> Signed-off-by: Simon Glass 
> ---
>
>  common/Kconfig   |   8 
>  common/Makefile  |   1 +
>  common/cmd_cpu.c | 113 
> +++
>  3 files changed, 122 insertions(+)
>  create mode 100644 common/cmd_cpu.c
>
> diff --git a/common/Kconfig b/common/Kconfig
> index 5d7e48a..15759f7 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -31,6 +31,14 @@ config CMD_CONSOLE
> help
>   Print console devices and information.
>
> +config CMD_CPU
> +   bool "cpu"
> +   help
> + Print information about available CPUs. This normally shows the
> + number of CPUs, type (e.g. manufacturer, architecture, product or
> + internal name) and clock frequency. Other information may be
> + available depending on the CPU driver.
> +
>  config CMD_LICENSE
> bool "license"
> help
> diff --git a/common/Makefile b/common/Makefile
> index fba3830..9084c73 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -74,6 +74,7 @@ obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
>  obj-$(CONFIG_CMD_CLK) += cmd_clk.o
>  obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
>  obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
> +obj-$(CONFIG_CMD_CPU) += cmd_cpu.o
>  obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
>  obj-$(CONFIG_CMD_DATE) += cmd_date.o
>  obj-$(CONFIG_CMD_DEMO) += cmd_demo.o
> diff --git a/common/cmd_cpu.c b/common/cmd_cpu.c
> new file mode 100644
> index 000..c3e229f
> --- /dev/null
> +++ b/common/cmd_cpu.c
> @@ -0,0 +1,113 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + * Written by Simon Glass 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
> +   "L1 cache",
> +   "MMU",
> +};
> +
> +static int print_cpu_list(bool detail)
> +{
> +   struct udevice *dev;
> +   struct uclass *uc;
> +   char buf[100];
> +   int ret;
> +
> +   ret = uclass_get(UCLASS_CPU, &uc);
> +   if (ret) {
> +   printf("Cannot find CPU uclass\n");
> +   return ret;
> +   }
> +   uclass_foreach_dev(dev, uc) {
> +   struct cpu_platdata *plat = dev_get_parent_platdata(dev);
> +   struct cpu_info info;
> +   bool first;
> +   int i;
> +
> +   ret = cpu_get_desc(dev, buf, sizeof(buf));
> +   printf("%3d: %-10s %s\n", dev->seq, dev->name,
> +  ret ? "" : buf);
> +   if (!detail)
> +   continue;
> +   ret = cpu_get_info(dev, &info);
> +   if (ret) {
> +   printf("\t(no detail available");
> +   if (ret != -ENOSYS)
> +   printf(": err=%d\n", ret);
> +   printf(")\n");
> +   continue;
> +   }
> +   printf("\tID = %d, freq = ", plat->cpu_id);
> +   print_freq(info.cpu_freq, "");
> +   first = true;
> +   for (i = 0; i < CPU_FEAT_COUNT; i++) {
> +   if (info.features & (1 << i)) {
> +   printf("%s%s", first ? ": " : ", ",
> +  cpu_feature_name[i]);
> +   first = false;
> +   }
> +   }
> +   printf("\n");
> +   }
> +
> +   return 0;
> +}
> +
> +static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc, char *const 
> argv[])
> +{
> +   if (print_cpu_list(false))
> +   return CMD_RET_FAILURE;
> +
> +   return 0;
> +}
> +
> +static int do_cpu_detail(cmd_tbl_t *cmdtp, int flag, int argc,
> +char *const argv[])
> +{
> +   if (print_cpu_list(true))
> +   return CMD_RET_FAILURE;
> +
> +   return 0;
> +}
> +
> +static cmd_tbl_t cmd_cpu_sub[] = {
> +   U_BOOT_CMD_MKENT(list, 2, 1, do_cpu_list, "", ""),
> +   U_BOOT_CMD_MKENT(detail, 4, 0, do_cpu_detail, "", ""),
> +};
> +
> +/*
> + * Process a cpu sub-command
> + */
> +static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc,
> +  char * const argv[])
> +{
> +   cmd_tbl_t *c = NULL;
> +
> +   /* Strip off leading 'cpu' command argument */
> +   argc--;
> +   argv++;
> +
> +   if (argc)
> +   c = find_cmd_tbl(argv[0], cmd_cpu_sub, 
> ARRAY_SIZE(cmd_cpu_sub));
> +
> +   if (c)
> +   return c->cmd(cmdtp, flag, argc, argv);
> +   else
> +   return CMD_RET_USAGE;
> +}
> +
> +U_BOOT_CMD(
> +   cpu, 2, 1, do_cpu,
> +   "display information about CPUs",
> +   "list   - list available CPUs\n"
> +   "cpu detail  

Re: [U-Boot] [PATCH 10/20] x86: Add atomic operations

[Bin Meng]

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> Add a subset of this header file from Linux 4.0 to support atomic operations
> in U-Boot.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/atomic.h | 115 
> ++
>  1 file changed, 115 insertions(+)
>  create mode 100644 arch/x86/include/asm/atomic.h
>
> diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
> new file mode 100644
> index 000..806f787
> --- /dev/null
> +++ b/arch/x86/include/asm/atomic.h
> @@ -0,0 +1,115 @@
> +#ifndef _ASM_X86_ATOMIC_H
> +#define _ASM_X86_ATOMIC_H
> +
> +#include 
> +#include 
> +#include 
> +
> +typedef struct { volatile int counter; } atomic_t;
> +
> +/*
> + * Atomic operations that C can't guarantee us.  Useful for
> + * resource counting etc..
> + */
> +
> +#define ATOMIC_INIT(i) { (i) }
> +
> +/**
> + * atomic_read - read atomic variable
> + * @v: pointer of type atomic_t
> + *
> + * Atomically reads the value of @v.
> + */
> +static inline int atomic_read(const atomic_t *v)
> +{
> +   return ACCESS_ONCE((v)->counter);
> +}
> +
> +/**
> + * atomic_set - set atomic variable
> + * @v: pointer of type atomic_t
> + * @i: required value
> + *
> + * Atomically sets the value of @v to @i.
> + */
> +static inline void atomic_set(atomic_t *v, int i)
> +{
> +   v->counter = i;
> +}
> +
> +/**
> + * atomic_add - add integer to atomic variable
> + * @i: integer value to add
> + * @v: pointer of type atomic_t
> + *
> + * Atomically adds @i to @v.
> + */
> +static inline void atomic_add(int i, atomic_t *v)
> +{
> +   asm volatile(LOCK_PREFIX "addl %1,%0"
> +: "+m" (v->counter)
> +: "ir" (i));
> +}
> +
> +/**
> + * atomic_sub - subtract integer from atomic variable
> + * @i: integer value to subtract
> + * @v: pointer of type atomic_t
> + *
> + * Atomically subtracts @i from @v.
> + */
> +static inline void atomic_sub(int i, atomic_t *v)
> +{
> +   asm volatile(LOCK_PREFIX "subl %1,%0"
> +: "+m" (v->counter)
> +: "ir" (i));
> +}
> +
> +/**
> + * atomic_inc - increment atomic variable
> + * @v: pointer of type atomic_t
> + *
> + * Atomically increments @v by 1.
> + */
> +static inline void atomic_inc(atomic_t *v)
> +{
> +   asm volatile(LOCK_PREFIX "incl %0"
> +: "+m" (v->counter));
> +}
> +
> +/**
> + * atomic_dec - decrement atomic variable
> + * @v: pointer of type atomic_t
> + *
> + * Atomically decrements @v by 1.
> + */
> +static inline void atomic_dec(atomic_t *v)
> +{
> +   asm volatile(LOCK_PREFIX "decl %0"
> +: "+m" (v->counter));
> +}
> +
> +/**
> + * atomic_inc_short - increment of a short integer
> + * @v: pointer to type int
> + *
> + * Atomically adds 1 to @v
> + * Returns the new value of @u
> + */
> +static inline short int atomic_inc_short(short int *v)
> +{
> +   asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
> +   return *v;
> +}
> +
> +/* These are x86-specific, used by some header files */
> +#define atomic_clear_mask(mask, addr)  \
> +   asm volatile(LOCK_PREFIX "andl %0,%1"   \
> +: : "r" (~(mask)), "m" (*(addr)) : "memory")
> +
> +#define atomic_set_mask(mask, addr)\
> +   asm volatile(LOCK_PREFIX "orl %0,%1"\
> +: : "r" ((unsigned)(mask)), "m" (*(addr))  \
> +: "memory")
> +
> +#endif /* _ASM_X86_ATOMIC_H */
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 11/20] x86: Add defines for fixed MTRRs

[Bin Meng]

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> Add MSR numbers for the fixed MTRRs.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/mtrr.h | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
> index fda4eae..3841593 100644
> --- a/arch/x86/include/asm/mtrr.h
> +++ b/arch/x86/include/asm/mtrr.h
> @@ -34,6 +34,20 @@
>  /* Number of MTRRs supported */
>  #define MTRR_COUNT 8
>
> +#define NUM_FIXED_RANGES 88
> +#define RANGES_PER_FIXED_MTRR 8
> +#define MTRR_FIX_64K_0_MSR 0x250
> +#define MTRR_FIX_16K_8_MSR 0x258
> +#define MTRR_FIX_16K_A_MSR 0x259
> +#define MTRR_FIX_4K_C_MSR 0x268
> +#define MTRR_FIX_4K_C8000_MSR 0x269
> +#define MTRR_FIX_4K_D_MSR 0x26a
> +#define MTRR_FIX_4K_D8000_MSR 0x26b
> +#define MTRR_FIX_4K_E_MSR 0x26c
> +#define MTRR_FIX_4K_E8000_MSR 0x26d
> +#define MTRR_FIX_4K_F_MSR 0x26e
> +#define MTRR_FIX_4K_F8000_MSR 0x26f
> +
>  #if !defined(__ASSEMBLER__)
>
>  /**
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 12/20] x86: Add an mfence macro

[Bin Meng]

Hi Simon,

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> Provide access to this x86 instruction from C code.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/cpu.h | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
> index c839291..37aa6b9 100644
> --- a/arch/x86/include/asm/cpu.h
> +++ b/arch/x86/include/asm/cpu.h
> @@ -151,6 +151,11 @@ static inline int flag_is_changeable_p(uint32_t flag)
> return ((f1^f2) & flag) != 0;
>  }
>
> +static inline void mfence(void)
> +{
> +   __asm__ __volatile__("mfence\t\n" : : : "memory");

Do we need "\t\n"?

> +}
> +
>  /**
>   * cpu_enable_paging_pae() - Enable PAE-paging
>   *
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 13/20] x86: Store the GDT pointer in global_data

[Bin Meng]

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> When we start up additional CPUs we want them to use the same Global
> Descriptor Table. Store the address of this in global_data so we can
> reference it later.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/cpu.c | 1 +
>  arch/x86/include/asm/global_data.h | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
> index 13b3baa..74bfed2 100644
> --- a/arch/x86/cpu/cpu.c
> +++ b/arch/x86/cpu/cpu.c
> @@ -133,6 +133,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
>
>  void setup_gdt(gd_t *id, u64 *gdt_addr)
>  {
> +   id->arch.gdt = gdt_addr;
> /* CS: code, read/execute, 4 GB, base 0 */
> gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xf);
>
> diff --git a/arch/x86/include/asm/global_data.h 
> b/arch/x86/include/asm/global_data.h
> index 5ee06eb..4d9eac6 100644
> --- a/arch/x86/include/asm/global_data.h
> +++ b/arch/x86/include/asm/global_data.h
> @@ -68,6 +68,7 @@ struct arch_global_data {
> /* MRC training data to save for the next boot */
> char *mrc_output;
> unsigned int mrc_output_len;
> +   void *gdt;  /* Global descriptor table */
>  };
>
>  #endif
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v3] sf: Fix to compute proper sector_size

[Jagan Teki]

On 27 April 2015 at 21:06, Jagannadha Sutradharudu Teki
 wrote:
> Upto now flash sector_size is assigned from params which isn't
> necessarily a sector size from vendor, so based on the SECT_*
> flags from flash_params the erase_size will compute and it will
> become the sector_size finally.
>
> Bug report (from Bin Meng):
> => sf probe
> SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
> total 2 MiB, mapped at ffe0
>
> => sf erase 0 +100
> SF: 65536 bytes @ 0x0 Erased: OK
>
> Signed-off-by: Jagannadha Sutradharudu Teki 
> Reported-by: Bin Meng 
> Tested-by: Bin Meng 
> ---
> Changes for v3:
> - Updated comments
> Changes for v2:
> - Minimize the code logic
>
>  drivers/mtd/spi/sf_internal.h | 3 ++-
>  drivers/mtd/spi/sf_probe.c| 3 +++
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> index bd834dc..4158e13 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -119,7 +119,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
> size_t len,
>   * @name:  Device name 
> ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
>   * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
>   * @ext_jedec: Device ext_jedec ID
> - * @sector_size:   Sector size of this device
> + * @sector_size:   Isn't necessarily a sector size from vendor,
> + * the size listed here is what works with CMD_ERASE_64K
>   * @nr_sectors:No.of sectors on this device
>   * @e_rd_cmd:  Enum list for read commands
>   * @flags: Important param, for flash specific behaviour
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index de8d0b7..3f6b882 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -184,6 +184,9 @@ static int spi_flash_validate_params(struct spi_slave 
> *spi, u8 *idcode,
> flash->erase_size = flash->sector_size;
> }
>
> +   /* Now erase size becomes valid sector size */
> +   flash->sector_size = flash->erase_size;
> +
> /* Look for the fastest read cmd */
> cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
> if (cmd) {
> --
> 1.9.1
>

Applied to u-boot-spi/master

thanks!
-- 
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Re: [U-Boot] [PATCH v2 1/2] dm: sf: Save flash flags to struct spi_flash

[Jagan Teki]

On 24 April 2015 at 17:21, Bin Meng  wrote:
> Add a new member 'flags' in struct spi_flash to store the flash flags
> during spi_flash_validate_params().
>
> Signed-off-by: Bin Meng 
>
> ---
>
> Changes in v2:
> - New patch to save flash flags to struct spi_flash
>
>  drivers/mtd/spi/sf_probe.c | 3 +++
>  include/spi_flash.h| 1 +
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index d19138d..ac93114 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -132,6 +132,9 @@ static int spi_flash_validate_params(struct spi_slave 
> *spi, u8 *idcode,
> flash->name = params->name;
> flash->memory_map = spi->memory_map;
> flash->dual_flash = flash->spi->option;
> +#ifdef CONFIG_DM_SPI_FLASH
> +   flash->flags = params->flags;
> +#endif
>
> /* Assign spi_flash ops */
>  #ifndef CONFIG_DM_SPI_FLASH
> diff --git a/include/spi_flash.h b/include/spi_flash.h
> index 218283f..ddce22a 100644
> --- a/include/spi_flash.h
> +++ b/include/spi_flash.h
> @@ -65,6 +65,7 @@ struct spi_flash {
>  #ifdef CONFIG_DM_SPI_FLASH
> struct spi_slave *spi;
> struct udevice *dev;
> +   u16 flags;
>  #else
> struct spi_slave *spi;
>  #endif
> --
> 1.8.2.1
>

Issue with patch, re-based on current.

Applied to u-boot-spi/master

thanks!
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Re: [U-Boot] "Writing to MMC(%d)... failed"

[Przemyslaw Marczak]

Hello Nathan,

Sorry, I didn't reply last time, becouse I'm quite busy.

On 04/28/2015 07:39 AM, Nathan wrote:

Still not sure where the problem lies. I thought I found an issue, but
it didn't fix anything and caused a different issue.

At first, after plugging in a bunch of printfs, I thought it was a
simple issue in the dts (it appears not to be the issue):
*
Getting a little back into it, I find an issue in:
"./lib/libfdt/fdt_ro.c"
   "fdt_path_offset()" where "-FDT_ERR_BADPATH" is returned for "path"
= "sdhci@1253"
when:
"./lib/fdtdec.c"
   "fdtdec_add_aliases_for_id()" is examining "mmc2"

"fdt_path_offset()"
   "_fdt_nodename_eq()" finds "aliases"

But the issue comes from
"./lib/libfdt/fdt_ro.c"
   "_fdt_string_eq()"
where
"p" = "mmc2" <> "s" = "sdhci@1253"

What I'm noticing different in the "exynos4412-odroid.dts" (odroid u2)
and "exynos54xx.dtsi" is the "/" for the alias paths "mmc2" and
"mmc4".
*


If I good remember, Exynos 54xx doesn't support sdhci, it has only dw mmc.



The problem with that "finding" was:
"fdtdec_add_aliases_for_id: warning: alias 'mmc2' points to a node
'sdhci@1253' that is missing or is not compatible  with
'samsung,exynos-dwmmc'"
Not sure why it would even mention dwmmc for mmc2 when it is specified
"exynos-mmc" in "exynos4.dtsi"

A common issue with or without the slash is:
"_gpio_request_by_name_nodev: Node 'sdhci@1253', property
'pwr-gpios', failed to request GPIO index 0: -2"



The "pwr-gpio" is okay - the pin is not defined and not required here.

For this board's config, there are two mmc drivers:
- exynos dwmmc(mmc/exynos_dw_mmc.c) - channel 0 - for eMMC card slot
- s5p sdhci(mmc/s5p_sdhci.c) - channel 2 - for SD card slot
Each driver has it's own compatible id, which you can see in the array:
lib/fdtdec.c - > compat_names[COMPAT_COUNT]

Note: This is quite different like for the drivers, which support the 
driver model. We don't bind those drivers with the driver model yet.


So now we init those drivers, by call the board_mmc_init() in 
board/samsung/common/board.c - as you probably know - most of samsung 
boards in U-Boot uses this common file, beside it's own board file.
If you not sure where to find the function, you can check, which common 
files are compiled for your config:

cd board/samsung
find -name "*.o"


I think the kicker is "No match for node 'sdhci@1253'".
I even manually set/forced the "status=okay" in the dts, but it still
says it's disabled.

I shall continue to pursue this, working my way back from
"lists_bind_fdt()" in "lists.c"




And now, back to the issue with the warning, which you mentioned. This 
is okay. I'm sure, that sdhci driver init is fine. You can study the 
function: fdtdec_add_aliases_for_id() from lib/fdtdec.c
Remember, that this is the first introduced method for init the drivers 
with the FDT support. But we are going to move all subsystems into the 
driver model.


Let's look at the fdtdec_add_aliases_for_id():
- first we find all compatible nodes,
- next we have an array "nodes[maxcount]" with the compatible nodes only
- and next we look for the "path" for our "mmc*" aliases, but only for 
the compatible we can meet the condition: if (nodes[j] == node).

This is way you get the warning when init DWMMC driver.
This is ok.

Which compiler are you using?
We often use this U-Boot with SD cards and no one have such issue before.
What about your power supply?
Do you have eMMC card?
Any other accessory is connected?

Can you send me your binary (u-boot-dtb.bin)?

Best regards,
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Re: [U-Boot] [PATCH v2 2/2] dm: sf: Make SST flash write op work again

[Jagan Teki]

On 24 April 2015 at 17:21, Bin Meng  wrote:
> With SPI flash moving to driver model, commit fbb0991 "dm: Convert
> spi_flash_probe() and 'sf probe' to use driver model" ignored the
> SST flash-specific write op (byte program & word program), which
> actually broke the SST flash from wroking.
>
> This commit makes SST flash work again under driver model, by adding
> SST flash-specific handling in the spi_flash_std_write().
>
> Signed-off-by: Bin Meng 
>
> ---
>
> Changes in v2:
> - Instead of creating an SST flash-specifc driver to handle the write
>   op, handle that in the standard spi_flash_std_write().
> - Drop the crownbay.dts update patch
>
>  drivers/mtd/spi/sf_probe.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index ac93114..038fe2d 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -472,6 +472,15 @@ int spi_flash_std_write(struct udevice *dev, u32 offset, 
> size_t len,
>  {
> struct spi_flash *flash = dev_get_uclass_priv(dev);
>
> +#if defined(CONFIG_SPI_FLASH_SST)
> +   if (flash->flags & SST_WR) {
> +   if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
> +   return sst_write_bp(flash, offset, len, buf);
> +   else
> +   return sst_write_wp(flash, offset, len, buf);
> +   }
> +#endif
> +
> return spi_flash_cmd_write_ops(flash, offset, len, buf);
>  }
>
> --
> 1.8.2.1
>

Applied to u-boot-spi/master

thanks!
-- 
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Re: [U-Boot] [PATCH 14/20] x86: Provide access to the IDT

[Bin Meng]

Hi Simon,

On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass  wrote:
> Add a function to return the address of the Interrupt Descriptor Table.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/interrupts.c| 5 +
>  arch/x86/include/asm/interrupt.h | 2 ++
>  2 files changed, 7 insertions(+)
>
> diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
> index a21d2a6..c777d36 100644
> --- a/arch/x86/cpu/interrupts.c
> +++ b/arch/x86/cpu/interrupts.c
> @@ -147,6 +147,11 @@ int cpu_init_interrupts(void)
> return 0;
>  }
>
> +void *x86_get_idt(void)
> +{
> +   return &idt_ptr;
> +}
> +

idt_ptr is not declared as static, so this is unneeded? Or should we
change it to static?

>  void __do_irq(int irq)
>  {
> printf("Unhandled IRQ : %d\n", irq);
> diff --git a/arch/x86/include/asm/interrupt.h 
> b/arch/x86/include/asm/interrupt.h
> index 25abde7..0a75f89 100644
> --- a/arch/x86/include/asm/interrupt.h
> +++ b/arch/x86/include/asm/interrupt.h
> @@ -38,4 +38,6 @@ extern char exception_stack[];
>   */
>  void configure_irq_trigger(int int_num, bool is_level_triggered);
>
> +void *x86_get_idt(void);
> +
>  #endif
> --

Regards,
Bin
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[U-Boot] Pull request: u-boot-spi/master

[Jagannadha Sutradharudu Teki]

Hi Tom,

Please pick this PR.

thanks!
Jagan.

The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06:

  serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-spi.git master

for you to fetch changes up to c650ca7b4c160193791dc7a52381c71c6a29e871:

  sf: Fix to compute proper sector_size (2015-04-28 13:31:36 +0530)


Bin Meng (2):
  dm: sf: Save flash flags to struct spi_flash
  dm: sf: Make SST flash write op work again

David Dueck (1):
  spi: omap3: Fix timeout handling

Jagannadha Sutradharudu Teki (2):
  Revert "spi: add config option to enable the WP pin function on st micron 
flashes"
  sf: Fix to compute proper sector_size

Pavel Machek (1):
  spi flash: fix trivial problems

Peng Fan (1):
  mtd: spi: check return value of spi_setup_slave

Simon Glass (1):
  dm: spi: Correct SPI claim/release_bus() methods

Siva Durga Prasad Paladugu (3):
  sf: Correct the macros as per new array fast read command
  sf: Poll both the read status and flag status
  zynq: spi: Remove unnecessary error condition

Stefan Roese (1):
  cmd_sf: Fix problem with "sf update" and unaligned length

 README| 11 --
 common/cmd_sf.c   | 16 +++---
 drivers/mtd/spi/sf_internal.h |  7 ++-
 drivers/mtd/spi/sf_ops.c  | 32 +---
 drivers/mtd/spi/sf_probe.c| 49 +--
 drivers/spi/exynos_spi.c  |  6 --
 drivers/spi/omap3_spi.c   | 20 +++---
 drivers/spi/spi-uclass.c  |  4 ++--
 drivers/spi/tegra114_spi.c|  3 ++-
 drivers/spi/tegra20_sflash.c  |  3 ++-
 drivers/spi/tegra20_slink.c   |  3 ++-
 drivers/spi/zynq_spi.c|  3 ---
 include/spi.h | 21 ++-
 include/spi_flash.h   |  9 
 14 files changed, 93 insertions(+), 94 deletions(-)
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Re: [U-Boot] installing u-boot on a virtual x86 machine

[Bin Meng]

Hi Francesco,

On Tue, Apr 28, 2015 at 4:23 PM, Francesco Lucconi  wrote:
> Yes, I've readed the README.x86 document provided from uboot, I've created
> my u-boot-dtb.bin following the rules of coreboot-x86 recipe.
> I suppose I have to apply several tunings since I'm working with a PC with
> i7-2600 Intel Core CPU, right?
> Here you have the screenshots of some starting phases on virtualbox platform
> (I've attached the files even if I think they don't give many information).
>

Looks like the 'error' message is printed by the MBR loader codes. Can
you point us the source of the MBR?

>
> 2015-04-27 17:50 GMT+02:00 Simon Glass :
>>
>> Hi Francesco,
>>
>> On 27 April 2015 at 00:56, Francesco Lucconi  wrote:
>> >
>> > 2015-04-25 1:04 GMT+02:00 Bin Meng :
>> >>
>> >> Hi Francesco,
>> >>
>> >> On Fri, Apr 24, 2015 at 3:20 PM, Francesco Lucconi 
>> >> wrote:
>> >> > I'm Francesco Lucconi from Italy, and I'm involved into a x86 project
>> >> > where
>> >> > my issue is to compile a u-boot (I'm currently using uboot-2015.01)
>> >> > and
>> >> > to
>> >> > install it into a VID (virtual image disk) of virtualbox.
>> >> >
>> >> >
>> >> > I've already tuned the MBR, registering two FAT16 partitions, one for
>> >> > u-boot and the other one for future kernel uImage and firmware
>> >> > development.
>> >> > In this moment I figured out that I've installed correctly the MBR
>> >> > cause
>> >> > I
>> >> > can see on the display strings I've applied on the MBR source code
>> >> > but
>> >> > it
>> >> > seems that u-boot.bin code doesn't run correctly, the system hangs
>> >> > out
>> >> > Could you give me any tips I didn't notice before?
>> >>
>> >> Could you elaborate more on what BIOS is being used, and what MBR
>> >> codes is that? Is it grub?
>> >>
>> >>
>> >> Regards,
>> >> Bin
>> >
>> >
>> > @Simon Glass: About u-boot I'm using coreboot_x86 config, and with
>> > u-boot.srec I noticed that I received several prints of startup ( like
>> > this
>> > ".." ) but later the virtual machine hangs up.
>>
>> Did you follow the instruction sin README.x86? Can you provide console
>> output?
>> >
>> > @Bin Meng: I'm using BIOS embedded of Virtualbox platform and I've
>> > customized the 512 bytes MBR data with several debug prints and with the
>> > partitions table based on the features of my FAT16 partitions.
>> >
>> > Regards,
>> > Francesco
>> >
>>

Regards,
Bin
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Re: [U-Boot] installing u-boot on a virtual x86 machine

[Francesco Lucconi]

Yes, I've readed the README.x86 document provided from uboot, I've created
my u-boot-dtb.bin following the rules of coreboot-x86 recipe.
I suppose I have to apply several tunings since I'm working with a PC with
i7-2600 Intel Core CPU, right?
Here you have the screenshots of some starting phases on virtualbox
platform (I've attached the files even if I think they don't give many
information).



2015-04-27 17:50 GMT+02:00 Simon Glass :

> Hi Francesco,
>
> On 27 April 2015 at 00:56, Francesco Lucconi  wrote:
> >
> > 2015-04-25 1:04 GMT+02:00 Bin Meng :
> >>
> >> Hi Francesco,
> >>
> >> On Fri, Apr 24, 2015 at 3:20 PM, Francesco Lucconi 
> >> wrote:
> >> > I'm Francesco Lucconi from Italy, and I'm involved into a x86 project
> >> > where
> >> > my issue is to compile a u-boot (I'm currently using uboot-2015.01)
> and
> >> > to
> >> > install it into a VID (virtual image disk) of virtualbox.
> >> >
> >> >
> >> > I've already tuned the MBR, registering two FAT16 partitions, one for
> >> > u-boot and the other one for future kernel uImage and firmware
> >> > development.
> >> > In this moment I figured out that I've installed correctly the MBR
> cause
> >> > I
> >> > can see on the display strings I've applied on the MBR source code but
> >> > it
> >> > seems that u-boot.bin code doesn't run correctly, the system hangs
> >> > out
> >> > Could you give me any tips I didn't notice before?
> >>
> >> Could you elaborate more on what BIOS is being used, and what MBR
> >> codes is that? Is it grub?
> >>
> >>
> >> Regards,
> >> Bin
> >
> >
> > @Simon Glass: About u-boot I'm using coreboot_x86 config, and with
> > u-boot.srec I noticed that I received several prints of startup ( like
> this
> > ".." ) but later the virtual machine hangs up.
>
> Did you follow the instruction sin README.x86? Can you provide console
> output?
> >
> > @Bin Meng: I'm using BIOS embedded of Virtualbox platform and I've
> > customized the 512 bytes MBR data with several debug prints and with the
> > partitions table based on the features of my FAT16 partitions.
> >
> > Regards,
> > Francesco
> >
>
> Regards,
> Simon
>
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Re: [U-Boot] [UBOOT PATCH] ci_udc: Update the ci_udc driver to support bulk transfers

[Michal Simek]

On 09/05/2014 08:46 AM, Siva Durga Prasad Paladugu wrote:
> Update the ci_udc driver to support bulk transfer
> and also added capability of having multiple dtds
> if requested data is more thank 16K.
> These changes are tested for both the DFU and lthor.
> 
> Signed-off-by: Siva Durga Prasad Paladugu 
> ---
>  drivers/usb/gadget/ci_udc.c |  135 
> +--
>  drivers/usb/gadget/ci_udc.h |1 +
>  2 files changed, 117 insertions(+), 19 deletions(-)

Marek and Lukasz: Any update on this one?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform




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Re: [U-Boot] [PATCH 07/10] sunxi: Fix end of kernel memory alignment for A33

[Mark Rutland]

Hi Hans,

> So it seems that I'm not the only one seeing this, and I've been wrongly
> blaming it on the A33, instead it seems to be a kernel bug, triggered
> on my A33 due to the display resolution it has.
> 
> For details see:
> 
> http://www.spinics.net/lists/arm-kernel/msg413811.html

That's good news; far less scary than a HW issue.

Would you mind replying on that thread to give it a bit more visibility?

Thanks,
Mark.
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Re: [U-Boot] Intel Galileo on u-boot

[Bin Meng]

Hi Fei,

On Tue, Apr 28, 2015 at 7:36 AM, WANG FEI  wrote:
> Meng Bin,
>
> I remember few weeks I've built a u-boot binary for Galileo, but I remember
> the generated u-boot.bin is not 256/512/1024/2048K, it possible is about
> 384K, is it correct? I want to use the u-boot you built as a reference.
>

No, it should be 1MB. Did you turn on BUILD_ROM as documented in README.x86?

> I've successfully built a coreboot image with CAR enabled, console function
> only enabled partly due to some issue, it looks the "va_arg" in printf() has
> something wrong, I guess it's a compiler issue - maybe Quark SoC does not
> support some special instruments. Did you get the similar issue when porting
> u-boot?
>

The Quark integrates a CPU which has the 486 ISA. What compiler flag
did you pass when you build coreboot?

Regards,
Bin
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[U-Boot] [PATCH] x86: Correct the typo in write_tables()

[Bin Meng]

It should be #ifdef instead of #if.

Signed-off-by: Bin Meng 
---

 arch/x86/lib/tables.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index b390a4b..0836e1e 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -23,7 +23,7 @@ void write_tables(void)
 {
u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR;
 
-#if CONFIG_GENERATE_PIRQ_TABLE
+#ifdef CONFIG_GENERATE_PIRQ_TABLE
rom_table_end = write_pirq_routing_table(rom_table_end);
rom_table_end = ALIGN(rom_table_end, 1024);
 #endif
-- 
1.8.2.1

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Re: [U-Boot] installing u-boot on a virtual x86 machine

[Bin Meng]

Hi Francesco,

On Tue, Apr 28, 2015 at 4:40 PM, Francesco Lucconi  wrote:
> Here you have the 512 bytes of MBR within the Virtual Disk Image (VID) of
> virtualbox. As you can notice there's not clearly the string "Error!"
> mentioned on previous screenshot.
> About MBR building to ease the procedure, I've created the MBR code
> automatically with PartitionGuru application...
>

Could you please provide detailed setup instructions (like how you
generated the u-boot binary, how you setup the virtual machine and
MBR, etc), so that I can have a try in my environment?

And please stop top posting.

> 2015-04-28 10:25 GMT+02:00 Bin Meng :
>>
>> Hi Francesco,
>>
>> On Tue, Apr 28, 2015 at 4:23 PM, Francesco Lucconi 
>> wrote:
>> > Yes, I've readed the README.x86 document provided from uboot, I've
>> > created
>> > my u-boot-dtb.bin following the rules of coreboot-x86 recipe.
>> > I suppose I have to apply several tunings since I'm working with a PC
>> > with
>> > i7-2600 Intel Core CPU, right?
>> > Here you have the screenshots of some starting phases on virtualbox
>> > platform
>> > (I've attached the files even if I think they don't give many
>> > information).
>> >
>>
>> Looks like the 'error' message is printed by the MBR loader codes. Can
>> you point us the source of the MBR?
>>
>> >
>> > 2015-04-27 17:50 GMT+02:00 Simon Glass :
>> >>
>> >> Hi Francesco,
>> >>
>> >> On 27 April 2015 at 00:56, Francesco Lucconi  wrote:
>> >> >
>> >> > 2015-04-25 1:04 GMT+02:00 Bin Meng :
>> >> >>
>> >> >> Hi Francesco,
>> >> >>
>> >> >> On Fri, Apr 24, 2015 at 3:20 PM, Francesco Lucconi
>> >> >> 
>> >> >> wrote:
>> >> >> > I'm Francesco Lucconi from Italy, and I'm involved into a x86
>> >> >> > project
>> >> >> > where
>> >> >> > my issue is to compile a u-boot (I'm currently using
>> >> >> > uboot-2015.01)
>> >> >> > and
>> >> >> > to
>> >> >> > install it into a VID (virtual image disk) of virtualbox.
>> >> >> >
>> >> >> >
>> >> >> > I've already tuned the MBR, registering two FAT16 partitions, one
>> >> >> > for
>> >> >> > u-boot and the other one for future kernel uImage and firmware
>> >> >> > development.
>> >> >> > In this moment I figured out that I've installed correctly the MBR
>> >> >> > cause
>> >> >> > I
>> >> >> > can see on the display strings I've applied on the MBR source code
>> >> >> > but
>> >> >> > it
>> >> >> > seems that u-boot.bin code doesn't run correctly, the system hangs
>> >> >> > out
>> >> >> > Could you give me any tips I didn't notice before?
>> >> >>
>> >> >> Could you elaborate more on what BIOS is being used, and what MBR
>> >> >> codes is that? Is it grub?
>> >> >>
>> >> >>
>> >> >> Regards,
>> >> >> Bin
>> >> >
>> >> >
>> >> > @Simon Glass: About u-boot I'm using coreboot_x86 config, and with
>> >> > u-boot.srec I noticed that I received several prints of startup (
>> >> > like
>> >> > this
>> >> > ".." ) but later the virtual machine hangs up.
>> >>
>> >> Did you follow the instruction sin README.x86? Can you provide console
>> >> output?
>> >> >
>> >> > @Bin Meng: I'm using BIOS embedded of Virtualbox platform and I've
>> >> > customized the 512 bytes MBR data with several debug prints and with
>> >> > the
>> >> > partitions table based on the features of my FAT16 partitions.
>> >> >
>> >> > Regards,
>> >> > Francesco
>> >> >
>> >>
>>

Regards,
Bin
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Re: [U-Boot] installing u-boot on a virtual x86 machine

[Francesco Lucconi]

2015-04-28 12:45 GMT+02:00 Bin Meng :

> Hi Francesco,
>
> On Tue, Apr 28, 2015 at 4:40 PM, Francesco Lucconi 
> wrote:
> > Here you have the 512 bytes of MBR within the Virtual Disk Image (VID) of
> > virtualbox. As you can notice there's not clearly the string "Error!"
> > mentioned on previous screenshot.
> > About MBR building to ease the procedure, I've created the MBR code
> > automatically with PartitionGuru application...
> >
>
> Could you please provide detailed setup instructions (like how you
> generated the u-boot binary, how you setup the virtual machine and
> MBR, etc), so that I can have a try in my environment?
>
> And please stop top posting.
>
>
U-boot setup:

1. cd uboot-2015.01/
2. CROSS_COMPILE=/path_to_my_i386_toolchain/i386-linux-uclibc- make
ARCH=x86 coreboot-x86_defconfig u-boot-dtb.bin

Virtualbox setup:

1. I've created a VID disk with size 64 MB with virtualbox
2. I've created a unique FAT16 primary partition and automatically the 512
MBR bytes content with PartitionGuru application, and I've loaded
u-boot-dtb.bin within its content
3. I've created a VM machine (type: Other, version: Other/Unknown) and I've
registered the VID disk as its storage disk managed by the SCSI controller

I'm confident that MBR data has been created coherently with virtual disk
geometry because earlier I have formatted the FAT16 partition and I've
installed a test tool; after this MBR loads it without any error, this
proofs that the partitions table has been filled correctly.




> > 2015-04-28 10:25 GMT+02:00 Bin Meng :
> >>
> >> Hi Francesco,
> >>
> >> On Tue, Apr 28, 2015 at 4:23 PM, Francesco Lucconi 
> >> wrote:
> >> > Yes, I've readed the README.x86 document provided from uboot, I've
> >> > created
> >> > my u-boot-dtb.bin following the rules of coreboot-x86 recipe.
> >> > I suppose I have to apply several tunings since I'm working with a PC
> >> > with
> >> > i7-2600 Intel Core CPU, right?
> >> > Here you have the screenshots of some starting phases on virtualbox
> >> > platform
> >> > (I've attached the files even if I think they don't give many
> >> > information).
> >> >
> >>
> >> Looks like the 'error' message is printed by the MBR loader codes. Can
> >> you point us the source of the MBR?
> >>
> >> >
> >> > 2015-04-27 17:50 GMT+02:00 Simon Glass :
> >> >>
> >> >> Hi Francesco,
> >> >>
> >> >> On 27 April 2015 at 00:56, Francesco Lucconi 
> wrote:
> >> >> >
> >> >> > 2015-04-25 1:04 GMT+02:00 Bin Meng :
> >> >> >>
> >> >> >> Hi Francesco,
> >> >> >>
> >> >> >> On Fri, Apr 24, 2015 at 3:20 PM, Francesco Lucconi
> >> >> >> 
> >> >> >> wrote:
> >> >> >> > I'm Francesco Lucconi from Italy, and I'm involved into a x86
> >> >> >> > project
> >> >> >> > where
> >> >> >> > my issue is to compile a u-boot (I'm currently using
> >> >> >> > uboot-2015.01)
> >> >> >> > and
> >> >> >> > to
> >> >> >> > install it into a VID (virtual image disk) of virtualbox.
> >> >> >> >
> >> >> >> >
> >> >> >> > I've already tuned the MBR, registering two FAT16 partitions,
> one
> >> >> >> > for
> >> >> >> > u-boot and the other one for future kernel uImage and firmware
> >> >> >> > development.
> >> >> >> > In this moment I figured out that I've installed correctly the
> MBR
> >> >> >> > cause
> >> >> >> > I
> >> >> >> > can see on the display strings I've applied on the MBR source
> code
> >> >> >> > but
> >> >> >> > it
> >> >> >> > seems that u-boot.bin code doesn't run correctly, the system
> hangs
> >> >> >> > out
> >> >> >> > Could you give me any tips I didn't notice before?
> >> >> >>
> >> >> >> Could you elaborate more on what BIOS is being used, and what MBR
> >> >> >> codes is that? Is it grub?
> >> >> >>
> >> >> >>
> >> >> >> Regards,
> >> >> >> Bin
> >> >> >
> >> >> >
> >> >> > @Simon Glass: About u-boot I'm using coreboot_x86 config, and with
> >> >> > u-boot.srec I noticed that I received several prints of startup (
> >> >> > like
> >> >> > this
> >> >> > ".." ) but later the virtual machine hangs up.
> >> >>
> >> >> Did you follow the instruction sin README.x86? Can you provide
> console
> >> >> output?
> >> >> >
> >> >> > @Bin Meng: I'm using BIOS embedded of Virtualbox platform and I've
> >> >> > customized the 512 bytes MBR data with several debug prints and
> with
> >> >> > the
> >> >> > partitions table based on the features of my FAT16 partitions.
> >> >> >
> >> >> > Regards,
> >> >> > Francesco
> >> >> >
> >> >>
> >>
>
> Regards,
> Bin
>
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Re: [U-Boot] [PATCH] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

[Codrin Constantin Ciubotariu]

> 
>  #ifdef CONFIG_FMAN_ENET
>  #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
> -#define CONFIG_SYS_SGMII1_PHY_ADDR   0x03
> +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
> +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
> +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
> +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
> +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
> +#endif

The PHY address for SGMII PHY connected to FM1@DTSEC3 on T1040D4RDB should be 
0x01, not 0x02 (CONFIG_SYS_SGMII1_PHY_ADDR).

Best regards,
Codrin
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Re: [U-Boot] [PATCH v2] dm: sf: Add Atmel DataFlash spi flash driver

[Jagan Teki]

On 27 April 2015 at 08:56, haikun.w...@freescale.com
 wrote:
> On 4/24/2015 11:55 PM, Simon Glass wrote:
>> Hi Haikun,
>>
>> On 24 April 2015 at 07:22, Haikun Wang  wrote:
>>> Atmel DataFlash chips have commands different from common spi
>>> flash commands.
>>> Atmel DataFlash also have special page-size.
>>> This driver add support for accessing Atmel DataFlash.
>>> It is based on the Driver Model.
>>>
>>> Signed-off-by: Haikun Wang 
>>> ---
>>> Verified with AT45DB021B.
>>>
>>> Changes in v2:
>>> - 1. Correct comment style
>>> - 2. Use get_timer in dataflash_waitready to check whether timeout
>>> - 3. Remove struct spi_flash * in struct dataflash, and get it from 
>>> udevice->uclass_priv
>>> - 4. Replace spi_flash_write_common with spi_flash_cmd_write
>>> - 5. Replace spi_flash_read with spi_flash_cmd_read
>>> - 6. Change type of varible "status" form char to u8 in dataflash_status
>>> - 7. Change add_dataflash's argument type due to 
>>> - 8. Add claim_bus and release_bus in erase/write/read due to 
>>>
>>> Changes in v1: None
>>>   drivers/mtd/spi/Makefile|   1 +
>>>   drivers/mtd/spi/spi_dataflash.c | 704 
>>> 
>>>   2 files changed, 705 insertions(+)
>>>   create mode 100644 drivers/mtd/spi/spi_dataflash.c

Has this drivers/mtd/spi area is meant for 'spi flash" please use 'sf'
which is the notation
used most of the files to identify it's an spi flash stuff.

>>
>> Reviewed-by: Simon Glass 
>>
>> See a small questoin below.
>>
>>>
>>> diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
>>> index c61b784..42acd24 100644
>>> --- a/drivers/mtd/spi/Makefile
>>> +++ b/drivers/mtd/spi/Makefile
>>> @@ -15,6 +15,7 @@ endif
>>>   #ifndef CONFIG_DM_SPI
>>>   obj-$(CONFIG_SPI_FLASH) += sf_probe.o
>>>   #endif
>>> +obj-$(CONFIG_DM_SPI_DATAFLASH) += spi_dataflash.o
>>>   obj-$(CONFIG_CMD_SF) += sf.o
>>>   obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
>>>   obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
>>> diff --git a/drivers/mtd/spi/spi_dataflash.c 
>>> b/drivers/mtd/spi/spi_dataflash.c
>>> new file mode 100644
>>> index 000..c68cf2e
>>> --- /dev/null
>>> +++ b/drivers/mtd/spi/spi_dataflash.c
>>> @@ -0,0 +1,704 @@
>>> +/*
>>> + *
>>> + * Atmel DataFlash probing
>>> + *
>>> + * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
>>> + * Haikun Wang (haikun.w...@freescale.com)
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> +*/
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +#include "sf_internal.h"
>>> +
>>> +/*
>>> + * DataFlash is a kind of SPI flash.  Most AT45 chips have two buffers in
>>> + * each chip, which may be used for double buffered I/O; but this driver
>>> + * doesn't (yet) use these for any kind of i/o overlap or prefetching.
>>> + *
>>> + * Sometimes DataFlash is packaged in MMC-format cards, although the
>>> + * MMC stack can't (yet?) distinguish between MMC and DataFlash
>>> + * protocols during enumeration.
>>> + */
>>> +
>>> +/* reads can bypass the buffers */
>>> +#define OP_READ_CONTINUOUS 0xE8
>>> +#define OP_READ_PAGE   0xD2
>>> +
>>> +/* group B requests can run even while status reports "busy" */
>>> +#define OP_READ_STATUS 0xD7/* group B */
>>> +
>>> +/* move data between host and buffer */
>>> +#define OP_READ_BUFFER10xD4/* group B */
>>> +#define OP_READ_BUFFER20xD6/* group B */
>>> +#define OP_WRITE_BUFFER1   0x84/* group B */
>>> +#define OP_WRITE_BUFFER2   0x87/* group B */
>>> +
>>> +/* erasing flash */
>>> +#define OP_ERASE_PAGE  0x81
>>> +#define OP_ERASE_BLOCK 0x50
>>> +
>>> +/* move data between buffer and flash */
>>> +#define OP_TRANSFER_BUF1   0x53
>>> +#define OP_TRANSFER_BUF2   0x55
>>> +#define OP_MREAD_BUFFER1   0xD4
>>> +#define OP_MREAD_BUFFER2   0xD6
>>> +#define OP_MWERASE_BUFFER1 0x83
>>> +#define OP_MWERASE_BUFFER2 0x86
>>> +#define OP_MWRITE_BUFFER1  0x88/* sector must be pre-erased */
>>> +#define OP_MWRITE_BUFFER2  0x89/* sector must be pre-erased */
>>> +
>>> +/* write to buffer, then write-erase to flash */
>>> +#define OP_PROGRAM_VIA_BUF10x82
>>> +#define OP_PROGRAM_VIA_BUF20x85
>>> +
>>> +/* compare buffer to flash */
>>> +#define OP_COMPARE_BUF10x60
>>> +#define OP_COMPARE_BUF20x61
>>> +
>>> +/* read flash to buffer, then write-erase to flash */
>>> +#define OP_REWRITE_VIA_BUF10x58
>>> +#define OP_REWRITE_VIA_BUF20x59
>>> +
>>> +/*
>>> + * newer chips report JEDEC manufacturer and device IDs; chip
>>> + * serial number and OTP bits; and per-sector writeprotect.
>>> + */
>>> +#define OP_READ_ID 0x9F
>>> +#define OP_READ_SECURITY   0x77
>>> +#define OP_WRITE_SECURITY_REVC 0x9A
>>> +#define OP_WRITE_SECURITY  0x9B/* revision D */
>>> +
>>> +
>>> +struct dataflash {
>>> +   

[U-Boot] [PATCH] ARM: cache-cp15: Make sure EAE is not enabled

[Tomeu Vizoso]

This could happen if we are being chainloaded by Coreboot with LPAE
enabled, as is the case on the Tegra-based Chromebooks.

Signed-off-by: Tomeu Vizoso 
---
 arch/arm/lib/cache-cp15.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0291afa..78fb429 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -96,6 +96,10 @@ static inline void mmu_setup(void)
dram_bank_mmu_setup(i);
}
 
+   /* Make sure EAE is not enabled */
+   asm volatile("mcr p15, 0, %0, c2, c0, 2"
+: : "r" (0) : "memory");
+
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
 : : "r" (gd->arch.tlb_addr) : "memory");
-- 
2.3.6

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[U-Boot] Hi, guys.

[Wandy Lau]

I am new to this project. But I am so interested with it and I want to dive
into it. Where should I start ?

-- 
This is my life,but world of us~~
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Re: [U-Boot] [PATCH] dm: core: Correct bug introduced in uclass_first/next_device()

[Simon Glass]

Hi,

On 24 April 2015 at 22:33, Simon Glass  wrote:
> These functions now rely on uclass_find_first/next_device() and assume that
> they will either return failure (-ve error code) or a device. In fact,
> coming to the end of a list is not considered failure and they return 0
> in that case.
>
> The logic to deal with this was replaced in commit acb9ca2a with just using
> uclass_get_device_tail(). Add back the missing logic. This bug was
> caught by unit tests but since they were broken for other reasons at the
> time, this was not noticed.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/core/uclass.c | 5 +
>  1 file changed, 5 insertions(+)

Applied to u-boot-dm.

I'll pull this in soon since it does break a number of things.

Regards,
Simon
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[U-Boot] [UBOOT PATCH] mtd: nand: Increase max sizes of OOB and Page size

[Siva Durga Prasad Paladugu]

From: Siva Durga Prasad Paladugu 

Increase max sizes for OOB, Page size and eccpos to
suit for Micron MT29F32G08 part

Signed-off-by: Siva Durga Prasad Paladugu 
---
 include/linux/mtd/mtd.h  | 2 +-
 include/linux/mtd/nand.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 8666413..2c9ea2f 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -101,7 +101,7 @@ struct mtd_oob_ops {
 #ifdef CONFIG_SYS_NAND_MAX_ECCPOS
 #define MTD_MAX_ECCPOS_ENTRIES_LARGE   CONFIG_SYS_NAND_MAX_ECCPOS
 #else
-#define MTD_MAX_ECCPOS_ENTRIES_LARGE   640
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE   680
 #endif
 
 /*
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index bc927ec..58a0767 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -64,8 +64,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, 
uint64_t len);
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE   744
-#define NAND_MAX_PAGESIZE  8192
+#define NAND_MAX_OOBSIZE   1216
+#define NAND_MAX_PAGESIZE  16384
 #endif
 
 /*
-- 
2.1.1

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[U-Boot] [UBOOT PATCH] arasan: nfc: Add initial nand driver support for arasan

[Siva Durga Prasad Paladugu]

Added initial nand driver support for arasan nand flash
controller.This supports nand erase,nand read, nand write
This uses the hardware ECC for read and write operations

Signed-off-by: Siva Durga Prasad Paladugu 
---
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/arasan_nfc.c | 1187 +
 2 files changed, 1188 insertions(+)
 create mode 100644 drivers/mtd/nand/arasan_nfc.c

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 347ea62..9080835 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
 obj-$(CONFIG_NAND_DOCG4) += docg4.o
+obj-$(CONFIG_ARASAN_NFC) += arasan_nfc.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
new file mode 100644
index 000..3eaab8f
--- /dev/null
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -0,0 +1,1187 @@
+/*
+ * Arasan NAND Flash Controller Driver
+ *
+ * Copyright (C) 2014 - 2015 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct arasan_nand_info {
+#ifdef CONFIG_MTD_PARTITIONS
+   struct mtd_partition*parts;
+#endif
+   void __iomem*nand_base;
+   u32 page;
+};
+
+struct nand_regs {
+   u32 pkt_reg;
+   u32 memadr_reg1;
+   u32 memadr_reg2;
+   u32 cmd_reg;
+   u32 pgm_reg;
+   u32 intsts_enr;
+   u32 intsig_enr;
+   u32 intsts_reg;
+   u32 rdy_busy;
+   u32 cms_sysadr_reg;
+   u32 flash_sts_reg;
+   u32 tmg_reg;
+   u32 buf_dataport;
+   u32 ecc_reg;
+   u32 ecc_errcnt_reg;
+   u32 ecc_sprcmd_reg;
+   u32 errcnt_1bitreg;
+   u32 errcnt_2bitreg;
+   u32 errcnt_3bitreg;
+   u32 errcnt_4bitreg;
+   u32 dma_sysadr0_reg;
+   u32 dma_bufbdry_reg;
+   u32 cpu_rls_reg;
+   u32 errcnt_5bitreg;
+   u32 errcnt_6bitreg;
+   u32 errcnt_7bitreg;
+   u32 errcnt_8bitreg;
+   u32 data_if_reg;
+};
+#define arasan_nand_base ((struct nand_regs *)ARASAN_NAND_BASEADDR)
+
+struct arasan_nand_command_format {
+   u8 cmd1;
+   u8 cmd2;
+   u8 addr_cycles;
+   u32 pgm;
+};
+
+#define ONDIE_ECC_FEATURE_ADDR 0x90
+
+#define ARASAN_PROG_RD_MASK0x0001
+#define ARASAN_PROG_BLK_ERS_MASK   0x0004
+#define ARASAN_PROG_RD_ID_MASK 0x0040
+#define ARASAN_PROG_RD_STS_MASK0x0008
+#define ARASAN_PROG_PG_PROG_MASK   0x0010
+#define ARASAN_PROG_RD_PARAM_PG_MASK   0x0080
+#define ARASAN_PROG_RST_MASK   0x0100
+#define ARASAN_PROG_GET_FTRS_MASK  0x0200
+#define ARASAN_PROG_SET_FTRS_MASK  0x0400
+#define ARASAN_PROG_CHNG_ROWADR_END_MASK   0x0040
+
+#define ARASAN_NAND_CMD_ECC_ON_MASK0x8000
+#define ARASAN_NAND_CMD_CMD12_MASK 0x
+#define ARASAN_NAND_CMD_PG_SIZE_MASK   0x380
+#define ARASAN_NAND_CMD_PG_SIZE_SHIFT  23
+#define ARASAN_NAND_CMD_CMD2_SHIFT 8
+#define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x7000
+#define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT28
+
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK0x
+#define ARASAN_NAND_MEM_ADDR1_COL_MASK 0x
+#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT   16
+#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK0xFF
+#define ARASAN_NAND_MEM_ADDR2_CS_MASK  0xC000
+#define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE00
+#define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT25
+
+#define ARASAN_NAND_INT_STS_ERR_EN_MASK0x10
+#define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK   0x08
+#define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK0x02
+#define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK0x01
+#define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
+
+#define ARASAN_NAND_PKT_REG_PKT_CNT_MASK   0xFFF000
+#define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK  0x7FF
+#define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT   12
+
+#define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
+#define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
+#define ARASAN_NAND_COL_ADDR_CYCL_SHIFT4
+
+#define ARASAN_NAND_PKTSIZE_1K 1024
+#define ARASAN_NAND_PKTSIZE_512512
+
+#define ARASAN_NAND_POLL_TIMEOUT   100
+#define ARASAN_NAND_INVALID_ADDR_CYCL  0xFF
+
+struct arasan_nand_command_format *curr_cmd;
+
+typedef enum {
+   NAND_ADDR_CYCL_NONE,
+   NAND_ADDR_CYCL_ONE,
+   NAND_ADDR_CYCL_ROW,
+   NAND_ADDR_CYCL_COL,
+   NAND_ADDR_CYCL_BOTH,
+} addr_cycles_t;
+
+static struct arasan_nand_command_format arasan_nand_commands[] = {
+   {N

Re: [U-Boot] [U-Boot 0/7] dm: spi: Convert few drivers to driver model

[Siva Durga Prasad Paladugu]

Hi Jagan,

I didn't get chance to look at the series. Could you give me some time till 
next week as I am little busy this week.

Regards,
Siva

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, April 27, 2015 8:32 PM
> To: u-boot@lists.denx.de; Siva Durga Prasad Paladugu
> Cc: Jagannadha Sutradharudu Teki; Michal Simek
> Subject: Re: [U-Boot 0/7] dm: spi: Convert few drivers to driver model
>
> Hi Siva Durga Prasad,
>
> On 23 April 2015 at 19:45, Jagannadha Sutradharudu Teki
>  wrote:
> > Driver model conversion, patches. - drivers/spi/zynq_spi.c and
> > drivers/spi/xilinx_spi.c
> >
> > thanks!
> > --
> > Jagan.
> >
> > Jagannadha Sutradharudu Teki (7):
> >   dm: spi: zynq_spi: Convert to driver model
> >   zynq: Kconfig: Enable dm spi and spi_flash
> >   dts: zynq: Add zynq spi controller nodes
> >   spi: zynq_spi: Add fdt support in driver
> >   dts: zynq: Enable spi1 for zc770_xm010 board
> >   dm: spi: xilinx_spi: Convert to driver model
> >   spi: xilinx_spi: Add asm/io.h include file
>
> Can you just test and let me know any comments from your side.
>
> >
> >  arch/arm/Kconfig  |   2 +
> >  arch/arm/dts/zynq-7000.dtsi   |  26 +++
> >  arch/arm/dts/zynq-zc770-xm010.dts |   4 +
> >  arch/arm/include/asm/arch-zynq/hardware.h |   2 -
> >  doc/device-tree-bindings/spi/spi-zynq.txt |  29 +++
> >  drivers/spi/xilinx_spi.c  | 213 +++-
> >  drivers/spi/zynq_spi.c| 312 
> > ++
> >  7 files changed, 372 insertions(+), 216 deletions(-)  create mode
> > 100644 doc/device-tree-bindings/spi/spi-zynq.txt
> >
> > --
> > 1.9.1
> >
>
> thanks!
> --
> Jagan.


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Re: [U-Boot] [U-Boot 0/7] dm: spi: Convert few drivers to driver model

[Jagan Teki]

Hi Siva,

On 28 April 2015 at 18:21, Siva Durga Prasad Paladugu
 wrote:
> Hi Jagan,
>
> I didn't get chance to look at the series. Could you give me some time till 
> next week as I am little busy this week.

No issues, If something that I send it for v2 I will let you know.

>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Monday, April 27, 2015 8:32 PM
>> To: u-boot@lists.denx.de; Siva Durga Prasad Paladugu
>> Cc: Jagannadha Sutradharudu Teki; Michal Simek
>> Subject: Re: [U-Boot 0/7] dm: spi: Convert few drivers to driver model
>>
>> Hi Siva Durga Prasad,
>>
>> On 23 April 2015 at 19:45, Jagannadha Sutradharudu Teki
>>  wrote:
>> > Driver model conversion, patches. - drivers/spi/zynq_spi.c and
>> > drivers/spi/xilinx_spi.c
>> >
>> > thanks!
>> > --
>> > Jagan.
>> >
>> > Jagannadha Sutradharudu Teki (7):
>> >   dm: spi: zynq_spi: Convert to driver model
>> >   zynq: Kconfig: Enable dm spi and spi_flash
>> >   dts: zynq: Add zynq spi controller nodes
>> >   spi: zynq_spi: Add fdt support in driver
>> >   dts: zynq: Enable spi1 for zc770_xm010 board
>> >   dm: spi: xilinx_spi: Convert to driver model
>> >   spi: xilinx_spi: Add asm/io.h include file
>>
>> Can you just test and let me know any comments from your side.
>>
>> >
>> >  arch/arm/Kconfig  |   2 +
>> >  arch/arm/dts/zynq-7000.dtsi   |  26 +++
>> >  arch/arm/dts/zynq-zc770-xm010.dts |   4 +
>> >  arch/arm/include/asm/arch-zynq/hardware.h |   2 -
>> >  doc/device-tree-bindings/spi/spi-zynq.txt |  29 +++
>> >  drivers/spi/xilinx_spi.c  | 213 +++-
>> >  drivers/spi/zynq_spi.c| 312 
>> > ++
>> >  7 files changed, 372 insertions(+), 216 deletions(-)  create mode
>> > 100644 doc/device-tree-bindings/spi/spi-zynq.txt
>> >
>> > --
>> > 1.9.1

thanks!
-- 
Jagan.
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Re: [U-Boot] [PATCH 4/4 v2] x86: minnowmax: initialize the pin-muxing from device tree

[Simon Glass]

On 25 April 2015 at 14:18, Gabriel Huau  wrote:
> Signed-off-by: Gabriel Huau 
> ---
> Changes for v2:
> - Fix ordering of include header
>
>  board/intel/minnowmax/minnowmax.c | 9 +
>  include/configs/minnowmax.h   | 1 +
>  2 files changed, 10 insertions(+)
>
> diff --git a/board/intel/minnowmax/minnowmax.c 
> b/board/intel/minnowmax/minnowmax.c
> index 6e82b16..0244d35 100644
> --- a/board/intel/minnowmax/minnowmax.c
> +++ b/board/intel/minnowmax/minnowmax.c
> @@ -5,6 +5,7 @@
>   */
>
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -14,6 +15,14 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +int arch_early_init_r(void)
> +{
> +   /* do the pin-muxing */
> +   gpio_ich6_pinctrl_init();
> +
> +   return 0;
> +}
> +
>  int board_early_init_f(void)
>  {
> lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
> index 823e051..3c7b266 100644
> --- a/include/configs/minnowmax.h
> +++ b/include/configs/minnowmax.h
> @@ -15,6 +15,7 @@
>
>  #define CONFIG_SYS_MONITOR_LEN (1 << 20)
>  #define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_ARCH_EARLY_INIT_R
>
>  #define CONFIG_NR_DRAM_BANKS   1

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

[Simon Glass]

Hi Gabriel,

On 25 April 2015 at 14:17, Gabriel Huau  wrote:
> Every pin can be configured now from the device tree. A dt-bindings
> has been added to describe the different property available.
>
> Signed-off-by: Gabriel Huau 
> ---
> Changes for v2:
> - Clean commit message
> - Rename compatible string 'ich6' to 'x86'
> - Fix coding style
> - Create a dt-bindinds documentation
> - Move x86-gpio defines to a specific header
> - Reorder the functions to avoid the need for forward declarations
> - Rename double underscore functions to only one
> - Create a specific function to configure one pin
> - Use a define to prevent build/support issues with other x86 CPU that
> doesn't have a IOBASE.

I have a few minor comments below. Do you know how to access the GPIO
pings on the top connector of the Minnowboard MAX? I'd like to figure
out the pin names for those in U-Boot and that would allow me to test
a few things.

>
>  arch/x86/dts/minnowmax.dts |  21 ++
>  arch/x86/include/asm/arch-baytrail/gpio.h  |   1 +
>  arch/x86/include/asm/gpio.h|   1 +
>  .../gpio/intel,x86-pinctrl.txt |  31 +++
>  drivers/gpio/intel_ich6_gpio.c | 234 
> ++---
>  include/dt-bindings/gpio/x86-gpio.h|  36 
>  6 files changed, 295 insertions(+), 29 deletions(-)
>  create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
>  create mode 100644 include/dt-bindings/gpio/x86-gpio.h
>
> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> index c73e421..ea10963 100644
> --- a/arch/x86/dts/minnowmax.dts
> +++ b/arch/x86/dts/minnowmax.dts
> @@ -6,6 +6,8 @@
>
>  /dts-v1/;
>
> +#include 
> +
>  /include/ "skeleton.dtsi"
>  /include/ "serial.dtsi"
>
> @@ -21,6 +23,25 @@
> silent_console = <0>;
> };
>
> +   pch_pinctrl {
> +   compatible = "intel,x86-pinctrl";
> +   pin_usb_host_en0@0 {
> +   gpio-offset = <0x80 8>;
> +   pad-offset = <0x260>;
> +   mode-gpio;
> +   output-value = <1>;
> +   direction = ;
> +   };
> +
> +   pin_usb_host_en1@0 {
> +   gpio-offset = <0x80 9>;
> +   pad-offset = <0x258>;
> +   mode-gpio;
> +   output-value = <1>;
> +   direction = ;
> +   };
> +   };
> +
> gpioa {
> compatible = "intel,ich6-gpio";
> u-boot,dm-pre-reloc;
> diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h 
> b/arch/x86/include/asm/arch-baytrail/gpio.h
> index 4e8987c..85a65a8 100644
> --- a/arch/x86/include/asm/arch-baytrail/gpio.h
> +++ b/arch/x86/include/asm/arch-baytrail/gpio.h
> @@ -9,5 +9,6 @@
>
>  /* Where in config space is the register that points to the GPIO registers? 
> */
>  #define PCI_CFG_GPIOBASE 0x48
> +#define PCI_CFG_IOBASE   0x4c

Can we put this in the device tree as a property of the pch_pinctrl
node? If you like we could do it later.

>
>  #endif /* _X86_ARCH_GPIO_H_ */
> diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
> index 1099427..ed85b08 100644
> --- a/arch/x86/include/asm/gpio.h
> +++ b/arch/x86/include/asm/gpio.h
> @@ -147,6 +147,7 @@ struct pch_gpio_map {
> } set3;
>  };
>
> +int gpio_ich6_pinctrl_init(void);
>  void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
>  void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
>
> diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt 
> b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
> new file mode 100644
> index 000..45ab1af
> --- /dev/null
> +++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
> @@ -0,0 +1,31 @@
> +Intel x86 PINCTRL/GPIO controller
> +
> +Pin-muxing on x86 can be described with a node for the PINCTRL master
> +node and a set of child nodes for each pin on the SoC.
> +
> +The PINCTRL master node requires the following properties:
> +- compatible : "intel,x86-pinctrl"
> +
> +Pin nodes must be children of the pinctrl master node and can
> +contain the following properties:
> +- pad-offset- (required) offset in the IOBASE for the pin to 
> configured.
> +- gpio-offset   - (required) offset in the GPIOBASE for the pin to 
> configured and
> +   also the bit shift in this register.
> +- mode-gpio- (optional) standalone property to force the 
> pin into GPIO mode.
> +- mode-func- (optional) function number to assign to the 
> pin. if 'mode-gpio'
> +   is set, this property will be ignored.
> +in case of 'mode-gpio' property set:
> +- output-value - (optional) this set the default output val

Re: [U-Boot] [PATCH 2/4 v2] x86: minnowmax: add GPIO banks in the device tree

[Simon Glass]

On 26 April 2015 at 07:54, Bin Meng  wrote:
> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau  wrote:
>> There are 6 banks:
>> 4 banks for CORE: available in S0 mode
>> 2 banks for SUS (Suspend): available in S0-S5 mode
>>
>> Signed-off-by: Gabriel Huau 
>> ---
>> Changes for v2:
>> - Fix typo in the commit message
>>
>>  arch/x86/dts/minnowmax.dts | 42 ++
>>  1 file changed, 42 insertions(+)
>>
>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>> index 8f34369..c73e421 100644
>> --- a/arch/x86/dts/minnowmax.dts
>> +++ b/arch/x86/dts/minnowmax.dts
>> @@ -21,6 +21,48 @@
>> silent_console = <0>;
>> };
>>
>> +   gpioa {
>> +   compatible = "intel,ich6-gpio";
>> +   u-boot,dm-pre-reloc;
>> +   reg = <0 0x20>;
>> +   bank-name = "A";
>> +   };
>> +
>> +   gpiob {
>> +   compatible = "intel,ich6-gpio";
>> +   u-boot,dm-pre-reloc;
>> +   reg = <0x20 0x20>;
>> +   bank-name = "B";
>> +   };
>> +
>> +   gpioc {
>> +   compatible = "intel,ich6-gpio";
>> +   u-boot,dm-pre-reloc;
>> +   reg = <0x40 0x20>;
>> +   bank-name = "C";
>> +   };
>> +
>> +   gpiod {
>> +   compatible = "intel,ich6-gpio";
>> +   u-boot,dm-pre-reloc;
>> +   reg = <0x60 0x20>;
>> +   bank-name = "D";
>> +   };
>> +
>> +   gpioe {
>> +   compatible = "intel,ich6-gpio";
>> +   u-boot,dm-pre-reloc;
>> +   reg = <0x80 0x20>;
>> +   bank-name = "E";
>> +   };
>> +
>> +   gpiof {
>> +   compatible = "intel,ich6-gpio";
>> +   u-boot,dm-pre-reloc;
>> +   reg = <0xA0 0x20>;
>> +   bank-name = "F";
>> +   };
>> +
>> chosen {
>> stdout-path = "/serial";
>> };
>> --
>
> Reviewed-by: Bin Meng 

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/4 v3] x86: baytrail: fix the GPIOBASE address

[Simon Glass]

On 26 April 2015 at 07:52, Bin Meng  wrote:
> Hi Gabriel,
>
> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau  wrote:
>> The correct GPIOBASE address on the baytrail is 0x48
>>
>> Signed-off-by: Gabriel Huau 
>> ---
>
> Reviewed-by: Bin Meng 

Acked-by: Simon Glass 

>
> Please edit your commit message in the v2 to include such tags like
> Acked-by, Reviewed-by, etc so that we know the patch status.

Also you could take a look at patman which automates the creation of
change lists, checking patches, etc.

>
>> Changes for v2:
>> - Add a commit message
>>
>> Changes for v3:
>> - Fix patch number
>>
>>  arch/x86/include/asm/arch-baytrail/gpio.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h 
>> b/arch/x86/include/asm/arch-baytrail/gpio.h
>> index ab4e059..4e8987c 100644
>> --- a/arch/x86/include/asm/arch-baytrail/gpio.h
>> +++ b/arch/x86/include/asm/arch-baytrail/gpio.h
>> @@ -8,6 +8,6 @@
>>  #define _X86_ARCH_GPIO_H_
>>
>>  /* Where in config space is the register that points to the GPIO registers? 
>> */
>> -#define PCI_CFG_GPIOBASE 0x44
>> +#define PCI_CFG_GPIOBASE 0x48
>>
>>  #endif /* _X86_ARCH_GPIO_H_ */
>> --
>
> Regards,
> Bin

Regards,
Simon
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Re: [U-Boot] [PATCH 1/5] drivers:usb:dwc3: Add DWC3 controller driver support

[Marek Vasut]

On Tuesday, April 28, 2015 at 09:12:09 AM, Ramneek Mehresh wrote:
> Add support for DWC3 XHCI controller driver
> 
> Signed-off-by: Ramneek Mehresh 

Applied all, thanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [UBOOT PATCH] ci_udc: Update the ci_udc driver to support bulk transfers

[Marek Vasut]

On Tuesday, April 28, 2015 at 10:59:16 AM, Michal Simek wrote:
> On 09/05/2014 08:46 AM, Siva Durga Prasad Paladugu wrote:
> > Update the ci_udc driver to support bulk transfer
> > and also added capability of having multiple dtds
> > if requested data is more thank 16K.
> > These changes are tested for both the DFU and lthor.
> > 
> > Signed-off-by: Siva Durga Prasad Paladugu 
> > ---
> > 
> >  drivers/usb/gadget/ci_udc.c |  135
> >  +-- drivers/usb/gadget/ci_udc.h
> >  |1 +
> >  2 files changed, 117 insertions(+), 19 deletions(-)
> 
> Marek and Lukasz: Any update on this one?

I wanted to pick this, but I cannot apply this on u-boot-usb/master . Can
you please rebase this and repost ? In case Lukasz doesn't pick it, I will.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 6/6] sunxi: axp: Remove non driver-model support from the axp gpio code

[Simon Glass]

On 28 April 2015 at 00:24, Hans de Goede  wrote:
> Hi Simon,
>
> Thanks for the reviews.
>
>
> On 28-04-15 05:20, Simon Glass wrote:
>>
>> Hi Hans,
>>
>> On 26 April 2015 at 03:51, Hans de Goede  wrote:
>>>
>>> Now that all sunxi boards are using driver-model for gpio (*), we can
>>> remove
>>> the non driver-model support from the axp gpio code, and the glue to call
>>> into the axp gpio code from the sunxi_gpio non driver-model code.
>>>
>>> *) For the regular u-boot build, SPL still uses non driver-model gpio for
>>> now, but the SPL never uses axp gpios support and we were already not
>>> building
>>> axp-gpio support for the SPL.
>>>
>>> Signed-off-by: Hans de Goede 
>>> ---
>>>   arch/arm/include/asm/arch-sunxi/gpio.h |  7 ---
>>>   drivers/gpio/axp_gpio.c| 17 -
>>>   drivers/gpio/sunxi_gpio.c  | 32
>>> 
>>>   3 files changed, 8 insertions(+), 48 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
>>> b/arch/arm/include/asm/arch-sunxi/gpio.h
>>> index 2d66077..081e7d1 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
>>> @@ -225,11 +225,4 @@ int axp_gpio_init(void);
>>>   static inline int axp_gpio_init(void) { return 0; }
>>>   #endif
>>>
>>> -struct udevice;
>>> -
>>> -int axp_gpio_direction_input(struct udevice *dev, unsigned offset);
>>> -int axp_gpio_direction_output(struct udevice *dev, unsigned offset, int
>>> val);
>>> -int axp_gpio_get_value(struct udevice *dev, unsigned offset);
>>> -int axp_gpio_set_value(struct udevice *dev, unsigned offset, int val);
>>> -
>>>   #endif /* _SUNXI_GPIO_H */
>>> diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
>>> index 17358e6..956bb84 100644
>>> --- a/drivers/gpio/axp_gpio.c
>>> +++ b/drivers/gpio/axp_gpio.c
>>> @@ -25,6 +25,8 @@
>>>   #error Unknown AXP model
>>>   #endif
>>>
>>> +static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int
>>> val);
>>> +
>>>   static u8 axp_get_gpio_ctrl_reg(unsigned pin)
>>>   {
>>>  switch (pin) {
>>> @@ -40,7 +42,7 @@ static u8 axp_get_gpio_ctrl_reg(unsigned pin)
>>>  return 0;
>>>   }
>>>
>>> -int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
>>> +static int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
>>>   {
>>>  u8 reg;
>>>
>>> @@ -58,7 +60,8 @@ int axp_gpio_direction_input(struct udevice *dev,
>>> unsigned pin)
>>>  }
>>>   }
>>>
>>> -int axp_gpio_direction_output(struct udevice *dev, unsigned pin, int
>>> val)
>>> +static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
>>> +int val)
>>>   {
>>>  __maybe_unused int ret;
>>>  u8 reg;
>>> @@ -83,7 +86,7 @@ int axp_gpio_direction_output(struct udevice *dev,
>>> unsigned pin, int val)
>>>  }
>>>   }
>>>
>>> -int axp_gpio_get_value(struct udevice *dev, unsigned pin)
>>> +static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
>>>   {
>>>  u8 reg, val, mask;
>>>  int ret;
>>> @@ -115,7 +118,7 @@ int axp_gpio_get_value(struct udevice *dev, unsigned
>>> pin)
>>>  return (val & mask) ? 1 : 0;
>>>   }
>>>
>>> -int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
>>> +static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int
>>> val)
>>>   {
>>>  u8 reg;
>>>
>>> @@ -139,7 +142,6 @@ int axp_gpio_set_value(struct udevice *dev, unsigned
>>> pin, int val)
>>>  }
>>>   }
>>>
>>> -#ifdef CONFIG_DM_GPIO
>>>   static const struct dm_gpio_ops gpio_axp_ops = {
>>>  .direction_input= axp_gpio_direction_input,
>>>  .direction_output   = axp_gpio_direction_output,
>>> @@ -164,23 +166,20 @@ struct driver gpio_axp_driver = {
>>>  .ops= &gpio_axp_ops,
>>>  .probe  = gpio_axp_probe,
>>>   };
>>> -#endif
>>>
>>>   int axp_gpio_init(void)
>>>   {
>>> -   __maybe_unused struct udevice *dev;
>>> +   struct udevice *dev;
>>>  int ret;
>>>
>>>  ret = pmic_bus_init();
>>>  if (ret)
>>>  return ret;
>>>
>>> -#ifdef CONFIG_DM_GPIO
>>>  /* There is no devicetree support for the axp yet, so bind
>>> directly */
>>>  ret = device_bind(dm_root(), &gpio_axp_driver, "AXP", NULL, -1,
>>> &dev);
>>
>>
>> Is there really no compatible string you can use?
>>
>> device_bind_driver(dm_root(), "gpio_axp", "AXP", &dev)
>
>
> That seems like it is a comment on 5/6 not on this patch which only
> removes the #ifdef and #endif lines here.
>
> I did not know I could do something like the above, I'll look into that
> for 5/6 and do a v2 of 5/6 I will put a "u-boot" prefix into the compatible
> so as to not get any conflicts when we do actually get full devicetree
> support for thus in the upstream kernel and dts files.
>
> Since this is really a comment on 5/6 can I have your Reviewed-by for
> this one ?

Ah yes I see, sorry

Re: [U-Boot] [PATCH v2] x86: minnowmax: use the correct NOR in the configuration

[Simon Glass]

On 26 April 2015 at 08:08, Bin Meng  wrote:
> On Sat, Apr 25, 2015 at 11:13 PM, Gabriel Huau  
> wrote:
>> The SPI NOR on the minnowboard max is a MICRON N25Q064A
>>
>> Signed-off-by: Gabriel Huau 
>> ---
>> Changes for v2:
>> - Update the dts to put the correct flash name
>>
>>  arch/x86/dts/minnowmax.dts  | 2 +-
>>  include/configs/minnowmax.h | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>> index 3936e21..dd20b2c 100644
>> --- a/arch/x86/dts/minnowmax.dts
>> +++ b/arch/x86/dts/minnowmax.dts
>> @@ -94,7 +94,7 @@
>> compatible = "intel,ich";
>> spi-flash@0 {
>> reg = <0>;
>> -   compatible = "sst,25vf016b", "spi-flash";
>> +   compatible = "stmicro,n25q064a", "spi-flash";
>> memory-map = <0xff80 0x0080>;
>> };
>> };
>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
>> index 3c7b266..72393fa 100644
>> --- a/include/configs/minnowmax.h
>> +++ b/include/configs/minnowmax.h
>> @@ -43,7 +43,7 @@
>>
>>  #define CONFIG_SCSI_DEV_LIST\
>> {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
>> -#define CONFIG_SPI_FLASH_SST
>> +#define CONFIG_SPI_FLASH_STMICRO
>>
>>  #define CONFIG_MMC
>>  #define CONFIG_SDHCI
>> --
>
> Reviewed-by: Bin Meng 

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode

[Simon Glass]

On 27 April 2015 at 00:16, Bin Meng  wrote:
> By default the legacy segments (Ah-Bh, Eh-Fh)
> do not decode to system RAM. Turn on the decode so that we can
> write configuration tables in the F segment.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/cpu/quark/quark.c  | 12 
>  arch/x86/include/asm/arch-quark/quark.h |  7 +++
>  2 files changed, 19 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/3] x86: Check PIRQ routing table sanity in the F segment

[Simon Glass]

On 27 April 2015 at 00:16, Bin Meng  wrote:
> Previously the PIRQ routing table sanity check was performed against
> the original table provided by the platform codes. Now we switch to
> check its sanity on the final table in the F segment as this one is
> the one seen by the OS.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/lib/pirq_routing.c | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Simon Glass]

Hi Bin,

On 27 April 2015 at 00:16, Bin Meng  wrote:
> Intel Quark SoC has the same interrupt routing mechanism as the
> Queensbay platform, only the difference is that PCI devices'
> INTA/B/C/D are harcoded and cannot be changed freely.
>
> Signed-off-by: Bin Meng 
>
> ---
>
>  arch/x86/cpu/quark/Makefile  |   2 +-
>  arch/x86/cpu/quark/irq.c | 173 
> +++
>  arch/x86/cpu/quark/quark.c   |   8 ++
>  arch/x86/include/asm/arch-quark/device.h |  70 ++---
>  arch/x86/include/asm/arch-quark/irq.h|  55 ++
>  arch/x86/include/asm/arch-quark/quark.h  |  15 +++
>  configs/galileo_defconfig|   1 +
>  include/configs/galileo.h|   1 +
>  8 files changed, 309 insertions(+), 16 deletions(-)
>  create mode 100644 arch/x86/cpu/quark/irq.c
>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h

Before going too far down this path I'd like to see if we can put the
IRQ data in the device tree. What do you think?

Regards,
Simon
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Re: [U-Boot] [PATCH 2/5] x86: Kconfig: Move platform options forward

[Simon Glass]

On 27 April 2015 at 09:22, Bin Meng  wrote:
> Move platform-specific options under in arch/x86/Kconfig forward right
> after the board-specific options but before any architecture-specific
> options. When it comes to the same Kconfig option, board-specific one
> takes take the highest precedence, then platform-specific one, and
> finally architecture-specific one.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/Kconfig | 19 +--
>  1 file changed, 9 insertions(+), 10 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 4/5] x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/Kconfig

[Simon Glass]

On 27 April 2015 at 09:22, Bin Meng  wrote:
> Since all x86 boards have been converted to use DM_SPI and
> DM_SPI_FLASH, move them to arch/Kconfig x86 section.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/Kconfig | 2 ++
>  arch/x86/Kconfig | 6 --
>  2 files changed, 2 insertions(+), 6 deletions(-)
>

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/5] x86: Kconfig: Divide the target selection to vendor/model

[Simon Glass]

On 27 April 2015 at 09:22, Bin Meng  wrote:
> Let arch/x86/Kconfig prompt board vendor first, then select
> the board model under that vendor. This way arch/x86/Kconfig
> only needs concern board vendor and leave the supported target
> list to board//Kconfig.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/Kconfig| 92 
> ++---
>  board/coreboot/Kconfig  | 26 +++
>  board/google/Kconfig| 43 +
>  board/intel/Kconfig | 51 
>  configs/chromebook_link_defconfig   |  1 +
>  configs/chromebox_panther_defconfig |  1 +
>  configs/coreboot-x86_defconfig  |  1 +
>  configs/crownbay_defconfig  |  1 +
>  configs/galileo_defconfig   |  1 +
>  configs/minnowmax_defconfig |  1 +
>  10 files changed, 139 insertions(+), 79 deletions(-)
>  create mode 100644 board/coreboot/Kconfig
>  create mode 100644 board/google/Kconfig
>  create mode 100644 board/intel/Kconfig

Nice idea!

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/5] x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmetics

[Simon Glass]

On 27 April 2015 at 09:22, Bin Meng  wrote:
> Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
> fix the indention of its help text.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/Kconfig | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 5/5] x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS

[Simon Glass]

On 27 April 2015 at 09:22, Bin Meng  wrote:
> Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
> the text base address. Since it is deprecated, just remove it and use
> CONFIG_SYS_TEXT_BASE directly.
>
> Signed-off-by: Bin Meng 
> ---
>
>  Kconfig| 2 +-
>  board/coreboot/coreboot/Kconfig| 3 +++
>  board/google/chromebook_link/Kconfig   | 3 +++
>  board/google/chromebox_panther/Kconfig | 3 +++
>  board/intel/crownbay/Kconfig   | 3 +++
>  board/intel/galileo/Kconfig| 3 +++
>  board/intel/minnowmax/Kconfig  | 3 +++
>  configs/chromebook_link_defconfig  | 1 -
>  configs/chromebox_panther_defconfig| 1 -
>  configs/coreboot-x86_defconfig | 1 -
>  configs/crownbay_defconfig | 1 -
>  configs/galileo_defconfig  | 1 -
>  configs/minnowmax_defconfig| 1 -
>  13 files changed, 19 insertions(+), 7 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH] x86: Correct the typo in write_tables()

[Simon Glass]

On 28 April 2015 at 04:37, Bin Meng  wrote:
> It should be #ifdef instead of #if.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/lib/tables.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/4] mx6cuboxi: Allow HDMI and USB keyboard to be stdout/stdin

[Tom Rini]

On Mon, Apr 27, 2015 at 11:30:43PM -0300, Fabio Estevam wrote:


> From: Fabio Estevam 
> 
> There are users of Cuboxi and Hummingboard that use these boards without
> connecting them to a USB/serial adapter.
> 
> Allow such usage by allowing the HDMI port to act as stdout and USB keyboard
> as stdin.
> 
> The serial console still also works as stdin/stdout.
> 
> Signed-off-by: Rabeeh Khoury 
> Signed-off-by: Fabio Estevam 

This all looks right so:

Reviewed-by: Tom Rini 

But my keyboards (which iirc also caused problems on Allwinner) don't
work but I don't think that's a Hummingboard/mx6 problem.

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Re: [U-Boot] [PATCH 4/4] logos: Add Solidrun's logo

[Tom Rini]

On Mon, Apr 27, 2015 at 11:30:44PM -0300, Fabio Estevam wrote:

> From: Fabio Estevam 
> 
> Let Solidrun's logo appear on Cuboxi and Hummingboard by default.
> 
> Signed-off-by: Rabeeh Khoury 
> Signed-off-by: Fabio Estevam 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 1/4] mx6cuboxi: Add HDMI output support

[Tom Rini]

On Mon, Apr 27, 2015 at 11:30:41PM -0300, Fabio Estevam wrote:

> From: Fabio Estevam 
> 
> Add HDMI output using PLL5 as the source for the IPU DI clocks,
> and accurate VESA timings.
> 
> These settings are based on the patch from Soeren Moch 
> submitted for the tbs2910 mx6 based board.
> 
> It allows the display to work properly at 1024x768@60.
> 
> This should make the hdmi output signal compatible with most if not all
> modern displays.
> 
> Signed-off-by: Jon Nettleton 
> Signed-off-by: Fabio Estevam 

Reviewed-by: Tom Rini 
Tested-by: Tom Rini 

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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Tom Rini]

On Mon, Apr 27, 2015 at 11:30:42PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> Enable USB Host1 port.
> 
> Signed-off-by: Rabeeh Khoury 
> Signed-off-by: Fabio Estevam 
[snip]
> diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
> index 207a2a6..e7a18c6 100644
> --- a/include/configs/mx6cuboxi.h
> +++ b/include/configs/mx6cuboxi.h
> @@ -82,6 +82,18 @@
>  #define CONFIG_IMX_HDMI
>  #define CONFIG_IMX_VIDEO_SKIP
>  
> +/* USB */
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_ASIX
> +#define CONFIG_MXC_USB_PORTSC(PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT  2

Since we have FEC do we really need to add ASIX as well?  Also, what
devices did you test this with for USB?  I grabbed a Sandisk USB drive
and on the i2eX I have, the bottom USB port doesn't see it and on the
top I get:
scanning bus 1 for devices... failed to set default configuration len 0,
status 8000

-- 
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Re: [U-Boot] [GIT PULL] u-boot-mips/master

[Tom Rini]

On Fri, Apr 24, 2015 at 12:20:30PM +0200, Daniel Schwierzeck wrote:

> The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71:
> 
>   Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23 
> 14:56:47 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to 90b1c9fad7bde21e3f0d388d0ba0ac5ee1f2e976:
> 
>   MIPS: implement device-tree handover to Linux kernel (2015-04-24 12:15:34 
> +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Pull request: u-boot-spi/master

[Tom Rini]

On Tue, Apr 28, 2015 at 01:47:35PM +0530, Jagannadha Sutradharudu Teki wrote:

> Hi Tom,
> 
> Please pick this PR.
> 
> thanks!
> Jagan.
> 
> The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06:
> 
>   serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-spi.git master
> 
> for you to fetch changes up to c650ca7b4c160193791dc7a52381c71c6a29e871:
> 
>   sf: Fix to compute proper sector_size (2015-04-28 13:31:36 +0530)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[Tom Rini]

On Thu, Apr 23, 2015 at 07:17:51PM -0700, York Sun wrote:

> Tom,
> 
> I am having trouble cloning git repositories. I hope this pull request was
> generated correctly. I saw "fatal: read error: Connection reset by peer" when
> creating this pull request.
> 
> The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06:
> 
>   serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-fsl-qoriq.git master
> 
> for you to fetch changes up to ab10d73d2fc13bd5baf5024e54ad92641d238bdb:
> 
>   armv8/fsl-lsch3: Implement workaround for I2C erratum A009203 (2015-04-23
> 16:46:51 -0700)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-fdt

[Tom Rini]

On Fri, Apr 24, 2015 at 09:37:02AM -0600, Simon Glass wrote:

> Hi Tom,
> 
> The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71:
> 
>   Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23
> 14:56:47 -0400)
> 
> are available in the git repository at:
> 
>   http://git.denx.de/u-boot-fdt.git
> 
> for you to fetch changes up to 77d7fff8cec2652be8c2494b6b66d14a398ec860:
> 
>   fdt: Fix handling of paths with options in them (2015-04-23 22:54:32 -0600)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [PULL] Please pull u-boot-imx

[Stefano Babic]

Hi Tom,

please pull from u-boot-imx, thanks !

The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:

  Prepare v2015.04 (2015-04-13 10:53:03 -0400)

are available in the git repository at:

  git://www.denx.de/git/u-boot-imx.git master

for you to fetch changes up to 205d58699b157df75f1aa0b363ea9c21add21a0c:

  mx6cuboxi: Load the correct 'fdtfile' variable (2015-04-27 13:13:58 +0200)


Eric Nelson (1):
  nitrogen6x: allow gzipped bitmap display

Fabio Estevam (9):
  mx6: Add initial SPL support for HummingBoard-i2eX
  mx6sabresd: Fix SPL memory description
  mx6sabresd: Remove uneeded ifdef
  mx6cuboxi: Fix the defconfig name
  mx6cuboxi: Prepare for multi SoC support
  mx6cuboxi: Introduce multi-SoC support
  mx6cuboxi: Differentiate Cubox-i and Hummingboard
  mx6cuboxi: Use more standard namings for fdt variables
  mx6cuboxi: Load the correct 'fdtfile' variable

Jörg Krause (1):
  ARM: mxs: Get boot mode from OCRAM

Pushpal Sidhu (3):
  imx: ventana: add DT fixup for GW522x to change PCIE_RST# GPIO
  imx: ventana: Add new memory configuration
  imx: ventana: Update missing memory/calib handling

Stefan Roese (1):
  arm: mx6: tqma6: Extract baseboard configs into separate config file

Tim Harvey (34):
  arm: mx6: ddr: add pd_fast_exit flag to system information
  fdt: add new fdt_fixup_display function to configure display
  imx: ventana: disable 4k tftp/nfs packets
  imx: ventana: add i210 support
  imx: ventana: assign default ethprime dynamically
  imx: ventana: remove unused GPIO configuration
  imx: ventana: add usb_pcisel hwconfig support
  imx: ventana: enable precharge power-down fast-exit mode
  imx: ventana: add support for 4Gb density mem devices with IMX6DL
  imx: ventana: set LTC3676 PMIC to appropriate values per datasheet
  imx: ventana: config: add USB Mass Storage (ums) support
  imx: ventana: config: Support ramdisk
  imx: ventana: config: enable edid support
  imx: ventana: config: enable EXT4 filesystem read/write support
  imx: ventana: fix various sparse warnings
  imx: ventana: disable IMX6 watchdogs on GW51xx RevA and RevB
  imx: ventana: Add support for GW551x
  imx: ventana: add usb_pgood_delay 2sec default
  imx: ventana: add wdis config for GW5520
  imx: ventana: only pinmux FEC enet signals for boards using it
  imx: ventana: update boot scripts to support ubifs boot vol
  imx: ventana: remove GSC hwmon voltage rail min/max test
  imx: ventana: add mem_mb dynamic env var
  imx: ventana: gsc: add new hwmon rails
  imx: ventana: added DT fixup for GW551x-A video input
  imx: ventana: updated 16bit DDR calibration
  imx: ventana: remove 128x16 calibration (share with 128x32)
  imx: ventana: add DT fixup for GW54xx compatibility with older kernels
  imx: ventana: add support for DLC-700JMGT4 and DLC-800FIGT3 LCD
displays
  imx: ventana: added device-tree display configuration for LVDS
displays
  imx: ventana: add 'gsc wd' command for enabling and disabling GSC
watchdog
  imx: ventana: use hdmiinfmt env var to override HDMI capture format
  imx: ventana: set HDMI video in to yuv422bt656 for GW551x-A
  power: pfuze100: fix LDO_EN bit value

gaurav rana (1):
  iMX: Fix compilation error when enabling SECURE_BOOT

 arch/arm/Kconfig|   6 ++
 arch/arm/cpu/arm926ejs/mxs/spl_boot.c   |  29 ++
 arch/arm/cpu/armv7/mx6/ddr.c|   7 ++-
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |   1 +
 board/freescale/common/Makefile |   3 +-
 board/freescale/mx6sabresd/mx6sabresd.c |  13 ++---
 board/gateworks/gw_ventana/eeprom.c |  10 +++-
 board/gateworks/gw_ventana/gsc.c| 130
+
 board/gateworks/gw_ventana/gsc.h|  10 +++-
 board/gateworks/gw_ventana/gw_ventana.c | 367

 board/gateworks/gw_ventana/gw_ventana_spl.c | 129
-
 board/gateworks/gw_ventana/ventana_eeprom.h |   1 +
 board/solidrun/mx6cuboxi/Kconfig|  15 +
 board/solidrun/mx6cuboxi/MAINTAINERS|   6 ++
 board/solidrun/mx6cuboxi/Makefile   |   9 +++
 board/solidrun/mx6cuboxi/README |  21 +++
 board/solidrun/mx6cuboxi/mx6cuboxi.c| 510
+
 common/fdt_support.c|  29 ++
 configs/mx6cuboxi_defconfig |   6 ++
 include/configs/gw_ventana.h|  68 ++
 include/configs/mx6cuboxi.h 

Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Fabio Estevam]

Hi Tom,

On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:

> Since we have FEC do we really need to add ASIX as well?  Also, what

I can remove it if needed. Just kept the same as done in the Solidrun's U-boot.

> devices did you test this with for USB?  I grabbed a Sandisk USB drive
> and on the i2eX I have, the bottom USB port doesn't see it and on the
> top I get:
> scanning bus 1 for devices... failed to set default configuration len 0,
> status 8000

I tested with USB pen drive and USB keyboard and it could recognize them.

Only the bottom top works for me and the same is seen on Solidrun's U-boot.

Regards,

Fabio Estevam
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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Fabio Estevam]

On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam  wrote:
> Hi Tom,
>
> On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:
>
>> Since we have FEC do we really need to add ASIX as well?  Also, what
>
> I can remove it if needed. Just kept the same as done in the Solidrun's 
> U-boot.
>
>> devices did you test this with for USB?  I grabbed a Sandisk USB drive
>> and on the i2eX I have, the bottom USB port doesn't see it and on the
>> top I get:
>> scanning bus 1 for devices... failed to set default configuration len 0,
>> status 8000
>
> I tested with USB pen drive and USB keyboard and it could recognize them.
>
> Only the bottom top works for me and the same is seen on Solidrun's U-boot.

Ops, I mean "Only the bottom USB port works for me".
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Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree

[Stephen Warren]

On 04/28/2015 07:53 AM, Simon Glass wrote:

Hi Gabriel,

On 25 April 2015 at 14:17, Gabriel Huau  wrote:

Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.



diff --git a/include/dt-bindings/gpio/x86-gpio.h 
b/include/dt-bindings/gpio/x86-gpio.h



+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.


I think this comment needs updating.
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Re: [U-Boot] [PATCH 1/4 v3] x86: baytrail: fix the GPIOBASE address

[Simon Glass]

On 28 April 2015 at 07:53, Simon Glass  wrote:
> On 26 April 2015 at 07:52, Bin Meng  wrote:
>> Hi Gabriel,
>>
>> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau  
>> wrote:
>>> The correct GPIOBASE address on the baytrail is 0x48
>>>
>>> Signed-off-by: Gabriel Huau 
>>> ---
>>
>> Reviewed-by: Bin Meng 
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 2/4 v2] x86: minnowmax: add GPIO banks in the device tree

[Simon Glass]

On 28 April 2015 at 07:53, Simon Glass  wrote:
> On 26 April 2015 at 07:54, Bin Meng  wrote:
>> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau  
>> wrote:
>>> There are 6 banks:
>>> 4 banks for CORE: available in S0 mode
>>> 2 banks for SUS (Suspend): available in S0-S5 mode
>>>
>>> Signed-off-by: Gabriel Huau 
>>> ---
>>> Changes for v2:
>>> - Fix typo in the commit message
>>>
>>>  arch/x86/dts/minnowmax.dts | 42 ++
>>>  1 file changed, 42 insertions(+)

Applied to u-boot-x86, thanks!

>>>
>>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>>> index 8f34369..c73e421 100644
>>> --- a/arch/x86/dts/minnowmax.dts
>>> +++ b/arch/x86/dts/minnowmax.dts
>>> @@ -21,6 +21,48 @@
>>> silent_console = <0>;
>>> };
>>>
>>> +   gpioa {
>>> +   compatible = "intel,ich6-gpio";
>>> +   u-boot,dm-pre-reloc;
>>> +   reg = <0 0x20>;
>>> +   bank-name = "A";
>>> +   };
>>> +
>>> +   gpiob {
>>> +   compatible = "intel,ich6-gpio";
>>> +   u-boot,dm-pre-reloc;
>>> +   reg = <0x20 0x20>;
>>> +   bank-name = "B";
>>> +   };
>>> +
>>> +   gpioc {
>>> +   compatible = "intel,ich6-gpio";
>>> +   u-boot,dm-pre-reloc;
>>> +   reg = <0x40 0x20>;
>>> +   bank-name = "C";
>>> +   };
>>> +
>>> +   gpiod {
>>> +   compatible = "intel,ich6-gpio";
>>> +   u-boot,dm-pre-reloc;
>>> +   reg = <0x60 0x20>;
>>> +   bank-name = "D";
>>> +   };
>>> +
>>> +   gpioe {
>>> +   compatible = "intel,ich6-gpio";
>>> +   u-boot,dm-pre-reloc;
>>> +   reg = <0x80 0x20>;
>>> +   bank-name = "E";
>>> +   };
>>> +
>>> +   gpiof {
>>> +   compatible = "intel,ich6-gpio";
>>> +   u-boot,dm-pre-reloc;
>>> +   reg = <0xA0 0x20>;
>>> +   bank-name = "F";
>>> +   };
>>> +
>>> chosen {
>>> stdout-path = "/serial";
>>> };
>>> --
>>
>> Reviewed-by: Bin Meng 
>
> Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH v2] x86: minnowmax: use the correct NOR in the configuration

[Simon Glass]

On 28 April 2015 at 07:59, Simon Glass  wrote:
> On 26 April 2015 at 08:08, Bin Meng  wrote:
>> On Sat, Apr 25, 2015 at 11:13 PM, Gabriel Huau  
>> wrote:
>>> The SPI NOR on the minnowboard max is a MICRON N25Q064A
>>>
>>> Signed-off-by: Gabriel Huau 
>>> ---
>>> Changes for v2:
>>> - Update the dts to put the correct flash name
>>>
>>>  arch/x86/dts/minnowmax.dts  | 2 +-
>>>  include/configs/minnowmax.h | 2 +-
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>>> index 3936e21..dd20b2c 100644
>>> --- a/arch/x86/dts/minnowmax.dts
>>> +++ b/arch/x86/dts/minnowmax.dts
>>> @@ -94,7 +94,7 @@
>>> compatible = "intel,ich";
>>> spi-flash@0 {
>>> reg = <0>;
>>> -   compatible = "sst,25vf016b", "spi-flash";
>>> +   compatible = "stmicro,n25q064a", "spi-flash";
>>> memory-map = <0xff80 0x0080>;
>>> };
>>> };
>>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
>>> index 3c7b266..72393fa 100644
>>> --- a/include/configs/minnowmax.h
>>> +++ b/include/configs/minnowmax.h
>>> @@ -43,7 +43,7 @@
>>>
>>>  #define CONFIG_SCSI_DEV_LIST\
>>> {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
>>> -#define CONFIG_SPI_FLASH_SST
>>> +#define CONFIG_SPI_FLASH_STMICRO
>>>
>>>  #define CONFIG_MMC
>>>  #define CONFIG_SDHCI
>>> --
>>
>> Reviewed-by: Bin Meng 
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 2/3] x86: quark: Turn on legacy segments decode

[Simon Glass]

On 28 April 2015 at 08:05, Simon Glass  wrote:
> On 27 April 2015 at 00:16, Bin Meng  wrote:
>> By default the legacy segments (Ah-Bh, Eh-Fh)
>> do not decode to system RAM. Turn on the decode so that we can
>> write configuration tables in the F segment.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/cpu/quark/quark.c  | 12 
>>  arch/x86/include/asm/arch-quark/quark.h |  7 +++
>>  2 files changed, 19 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 1/3] x86: Check PIRQ routing table sanity in the F segment

[Simon Glass]

On 28 April 2015 at 08:04, Simon Glass  wrote:
> On 27 April 2015 at 00:16, Bin Meng  wrote:
>> Previously the PIRQ routing table sanity check was performed against
>> the original table provided by the platform codes. Now we switch to
>> check its sanity on the final table in the F segment as this one is
>> the one seen by the OS.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/lib/pirq_routing.c | 18 +-
>>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH] x86: Correct Minnowboard instructions to use the right descriptor

[Simon Glass]

On 25 April 2015 at 11:46, Simon Glass  wrote:
> The descriptor provided with the FSP does not seem to work. Update the
> instructions to use the descriptor from the original Intel firmware.
>
> Signed-off-by: Simon Glass 
> ---
>
>  doc/README.x86 | 23 ---
>  1 file changed, 20 insertions(+), 3 deletions(-)

Applied to u-boot-x86.
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Re: [U-Boot] [PATCH 1/5] x86: Kconfig: Divide the target selection to vendor/model

[Simon Glass]

On 28 April 2015 at 08:11, Simon Glass  wrote:
> On 27 April 2015 at 09:22, Bin Meng  wrote:
>> Let arch/x86/Kconfig prompt board vendor first, then select
>> the board model under that vendor. This way arch/x86/Kconfig
>> only needs concern board vendor and leave the supported target
>> list to board//Kconfig.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/Kconfig| 92 
>> ++---
>>  board/coreboot/Kconfig  | 26 +++
>>  board/google/Kconfig| 43 +
>>  board/intel/Kconfig | 51 
>>  configs/chromebook_link_defconfig   |  1 +
>>  configs/chromebox_panther_defconfig |  1 +
>>  configs/coreboot-x86_defconfig  |  1 +
>>  configs/crownbay_defconfig  |  1 +
>>  configs/galileo_defconfig   |  1 +
>>  configs/minnowmax_defconfig |  1 +
>>  10 files changed, 139 insertions(+), 79 deletions(-)
>>  create mode 100644 board/coreboot/Kconfig
>>  create mode 100644 board/google/Kconfig
>>  create mode 100644 board/intel/Kconfig
>
> Nice idea!
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 4/5] x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/Kconfig

[Simon Glass]

On 28 April 2015 at 08:12, Simon Glass  wrote:
> On 27 April 2015 at 09:22, Bin Meng  wrote:
>> Since all x86 boards have been converted to use DM_SPI and
>> DM_SPI_FLASH, move them to arch/Kconfig x86 section.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/Kconfig | 2 ++
>>  arch/x86/Kconfig | 6 --
>>  2 files changed, 2 insertions(+), 6 deletions(-)
>>
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 2/5] x86: Kconfig: Move platform options forward

[Simon Glass]

On 28 April 2015 at 08:12, Simon Glass  wrote:
> On 27 April 2015 at 09:22, Bin Meng  wrote:
>> Move platform-specific options under in arch/x86/Kconfig forward right
>> after the board-specific options but before any architecture-specific
>> options. When it comes to the same Kconfig option, board-specific one
>> takes take the highest precedence, then platform-specific one, and
>> finally architecture-specific one.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/Kconfig | 19 +--
>>  1 file changed, 9 insertions(+), 10 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH] x86: Correct the typo in write_tables()

[Simon Glass]

On 28 April 2015 at 08:13, Simon Glass  wrote:
> On 28 April 2015 at 04:37, Bin Meng  wrote:
>> It should be #ifdef instead of #if.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/lib/tables.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 5/5] x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS

[Simon Glass]

On 28 April 2015 at 08:12, Simon Glass  wrote:
> On 27 April 2015 at 09:22, Bin Meng  wrote:
>> Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
>> the text base address. Since it is deprecated, just remove it and use
>> CONFIG_SYS_TEXT_BASE directly.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  Kconfig| 2 +-
>>  board/coreboot/coreboot/Kconfig| 3 +++
>>  board/google/chromebook_link/Kconfig   | 3 +++
>>  board/google/chromebox_panther/Kconfig | 3 +++
>>  board/intel/crownbay/Kconfig   | 3 +++
>>  board/intel/galileo/Kconfig| 3 +++
>>  board/intel/minnowmax/Kconfig  | 3 +++
>>  configs/chromebook_link_defconfig  | 1 -
>>  configs/chromebox_panther_defconfig| 1 -
>>  configs/coreboot-x86_defconfig | 1 -
>>  configs/crownbay_defconfig | 1 -
>>  configs/galileo_defconfig  | 1 -
>>  configs/minnowmax_defconfig| 1 -
>>  13 files changed, 19 insertions(+), 7 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 3/5] x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmetics

[Simon Glass]

On 28 April 2015 at 08:12, Simon Glass  wrote:
> On 27 April 2015 at 09:22, Bin Meng  wrote:
>> Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
>> fix the indention of its help text.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/Kconfig | 8 
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-x86, thanks!
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[U-Boot] [PATCH 0/4]: imx: mx6: use OTP for temperature grade and freq grade

[Tim Harvey]

The MX6 has OTP bits specifying the processor speed grade as well as
temperature grade.

This series adds functions to return this information as well as adds the
details to the CPU info displayed.

Additionally we use the temperature grade to replace the hard-coded limits
in imx_thermal.c

I expect some possible discussion/debate regarding the displaying of this info,
but perhaps adding the functions to obtain the info and use it for imx_thermal
is beyond debate. Please let me know.

Tim Harvey (4):
  imx: mx6: display max cpu frequency in print_cpuinfo()
  mx6: add OTP bank1 registers
  imx: mx6: add display of temperature grade of processor in
cpu_printinfo()
  thermal: imx_thermal: use CPU temperature grade for trip points

 arch/arm/cpu/armv7/mx6/soc.c  | 58 +++
 arch/arm/imx-common/cpu.c | 37 +++-
 arch/arm/include/asm/arch-mx6/imx-regs.h  | 19 ++
 arch/arm/include/asm/arch-mx6/sys_proto.h |  2 ++
 arch/arm/include/asm/proc |  1 +
 drivers/thermal/imx_thermal.c | 29 ++--
 include/imx_thermal.h |  6 
 7 files changed, 141 insertions(+), 11 deletions(-)
 create mode 12 arch/arm/include/asm/proc

-- 
1.9.1

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[U-Boot] [PATCH 1/4] imx: mx6: display max cpu frequency in print_cpuinfo()

[Tim Harvey]

The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
(OCOTP_CFG3[17:16]).

Display this value to make it clear the difference regarding the CPU speed
currently running at vs the max speed allowed per grade. Note that the power
on CPU speed is determined by OCOTP_CFG4[18].

I see no indication in the IMX6SX reference manual that it has the same CPU
speed grades in this OTP register.

Signed-off-by: Tim Harvey 
---
 arch/arm/cpu/armv7/mx6/soc.c  | 26 ++
 arch/arm/imx-common/cpu.c | 17 +
 arch/arm/include/asm/arch-mx6/sys_proto.h |  1 +
 arch/arm/include/asm/proc |  1 +
 4 files changed, 45 insertions(+)
 create mode 12 arch/arm/include/asm/proc

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index dd34138..dc422a6 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -83,6 +83,32 @@ u32 get_cpu_rev(void)
return (type << 12) | (reg + 0x10);
 }
 
+#define OCOTP_CFG3_SPEED_SHIFT  16
+#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
+#define OCOTP_CFG3_SPEED_996MHZ 0x2
+#define OCOTP_CFG3_SPEED_852MHZ 0x1
+
+u32 get_cpu_speed_grade_hz(void)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = &ocotp->bank[0];
+   struct fuse_bank0_regs *fuse =
+   (struct fuse_bank0_regs *)bank->fuse_regs;
+   uint32_t val;
+
+   val = readl(&fuse->cfg3);
+   val >>= OCOTP_CFG3_SPEED_SHIFT;
+   val &= 0x3;
+
+   if (val == OCOTP_CFG3_SPEED_1P2GHZ)
+   return 12;
+   if (val == OCOTP_CFG3_SPEED_996MHZ)
+   return 99600;
+   if (val == OCOTP_CFG3_SPEED_852MHZ)
+   return 85200;
+   return 79200;
+}
+
 #ifdef CONFIG_REVISION_TAG
 u32 __weak get_board_rev(void)
 {
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 067d08f..ead7f08 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -151,11 +151,28 @@ int print_cpuinfo(void)
 
cpurev = get_cpu_rev();
 
+#if defined(CONFIG_MX6)
+   printf("CPU:   Freescale i.MX%s rev%d.%d",
+   get_imx_type((cpurev & 0xFF000) >> 12),
+   (cpurev & 0x000F0) >> 4,
+   (cpurev & 0xF) >> 0);
+   if (is_cpu_type(MXC_CPU_MX6SX))
+   printf(" at %d MHz", mxc_get_clock(MXC_ARM_CLK) / 100);
+   else {
+   printf(" %d MHz", get_cpu_speed_grade_hz() / 100);
+   if (get_cpu_speed_grade_hz() != mxc_get_clock(MXC_ARM_CLK)) {
+   printf(" (at %d MHz)",
+  mxc_get_clock(MXC_ARM_CLK) / 100);
+   }
+   }
+   puts("\n");
+#else
printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
(cpurev & 0xF) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 100);
+#endif
 
 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h 
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 28ba844..a2cd0a9 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -16,6 +16,7 @@
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
+u32 get_cpu_speed_grade_hz(void);
 
 /* returns MXC_CPU_ value */
 #define cpu_type(rev) (((rev) >> 12)&0xff)
diff --git a/arch/arm/include/asm/proc b/arch/arm/include/asm/proc
new file mode 12
index 000..c7f3c20
--- /dev/null
+++ b/arch/arm/include/asm/proc
@@ -0,0 +1 @@
+proc-armv
\ No newline at end of file
-- 
1.9.1

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[U-Boot] [PATCH 4/4] thermal: imx_thermal: use CPU temperature grade for trip points

[Tim Harvey]

Replace the hard-coded values for min/max/passive with values derived from
the CPU temperature grade.

Cc: Ye.Li 
Signed-off-by: Tim Harvey 
---
 drivers/thermal/imx_thermal.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 0bd9cfd..b5dab63 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -12,15 +12,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#define TEMPERATURE_MIN-40
-#define TEMPERATURE_HOT80
-#define TEMPERATURE_MAX125
 #define FACTOR01000
 #define FACTOR115976
 #define FACTOR24297157
@@ -34,14 +32,21 @@
 #define MISC0_REFTOP_SELBIASOFF(1 << 3)
 #define TEMPSENSE1_MEASURE_FREQ0x
 
+struct thermal_data {
+   unsigned int fuse;
+   int passive;
+   int minc;
+   int maxc;
+};
+
 static int read_cpu_temperature(struct udevice *dev)
 {
int temperature;
unsigned int reg, n_meas;
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
-   unsigned int *priv = dev_get_priv(dev);
-   u32 fuse = *priv;
+   struct thermal_data *priv = dev_get_priv(dev);
+   u32 fuse = priv->fuse;
int t1, n1;
u32 c1, c2;
u64 temp64;
@@ -119,11 +124,12 @@ static int read_cpu_temperature(struct udevice *dev)
 
 int imx_thermal_get_temp(struct udevice *dev, int *temp)
 {
+   struct thermal_data *priv = dev_get_priv(dev);
int cpu_tmp = 0;
 
cpu_tmp = read_cpu_temperature(dev);
-   while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) {
-   if (cpu_tmp >= TEMPERATURE_HOT) {
+   while (cpu_tmp > priv->minc && cpu_tmp < priv->maxc) {
+   if (cpu_tmp >= priv->passive) {
printf("CPU Temperature is %d C, too hot to boot, 
waiting...\n",
   cpu_tmp);
udelay(500);
@@ -147,7 +153,7 @@ static int imx_thermal_probe(struct udevice *dev)
unsigned int fuse = ~0;
 
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
-   unsigned int *priv = dev_get_priv(dev);
+   struct thermal_data *priv = dev_get_priv(dev);
 
/* Read Temperature calibration data fuse */
fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
@@ -158,7 +164,10 @@ static int imx_thermal_probe(struct udevice *dev)
return -EPERM;
}
 
-   *priv = fuse;
+   /* set passive cooling temp to max - 20C */
+   get_cpu_temp_grade(&priv->minc, &priv->maxc);
+   priv->passive = priv->maxc - 20;
+   priv->fuse = fuse;
 
enable_thermal_clk();
 
@@ -170,6 +179,6 @@ U_BOOT_DRIVER(imx_thermal) = {
.id = UCLASS_THERMAL,
.ops= &imx_thermal_ops,
.probe  = imx_thermal_probe,
-   .priv_auto_alloc_size = sizeof(unsigned int),
+   .priv_auto_alloc_size = sizeof(struct thermal_data),
.flags  = DM_FLAG_PRE_RELOC,
 };
-- 
1.9.1

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[U-Boot] [PATCH 3/4] imx: mx6: add display of temperature grade of processor in cpu_printinfo()

[Tim Harvey]

The MX6 has a temperature grade defined by OCOTP_MEM0[7:6].

While the MX6SX also has temperature grades, I see no mention in the reference
manual where that information is stored in the OTP.

Signed-off-by: Tim Harvey 
---
 arch/arm/cpu/armv7/mx6/soc.c  | 32 +++
 arch/arm/imx-common/cpu.c | 28 ++-
 arch/arm/include/asm/arch-mx6/sys_proto.h |  1 +
 include/imx_thermal.h |  6 ++
 4 files changed, 62 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index dc422a6..8d41c47 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -109,6 +109,38 @@ u32 get_cpu_speed_grade_hz(void)
return 79200;
 }
 
+#define OCOTP_MEM0_TEMP_SHIFT  6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = &ocotp->bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   uint32_t val;
+
+   val = readl(&fuse->mem0);
+   val >>= OCOTP_MEM0_TEMP_SHIFT;
+   val &= 0x3;
+
+   if (minc && maxc) {
+   if (val == TEMP_AUTOMOTIVE) {
+   *minc = -40;
+   *maxc = 125;
+   } else if (val == TEMP_INDUSTRIAL) {
+   *minc = -40;
+   *maxc = 105;
+   } else if (val == TEMP_EXTCOMMERCIAL) {
+   *minc = -20;
+   *maxc = 105;
+   } else {
+   *minc = 0;
+   *maxc = 95;
+   }
+   }
+   return val;
+}
+
 #ifdef CONFIG_REVISION_TAG
 u32 __weak get_board_rev(void)
 {
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index ead7f08..a1045db 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -146,24 +147,41 @@ int print_cpuinfo(void)
 
 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
-   int cpu_tmp, ret;
+   int cpu_tmp, minc, maxc, ret;
 #endif
 
cpurev = get_cpu_rev();
 
 #if defined(CONFIG_MX6)
printf("CPU:   Freescale i.MX%s rev%d.%d",
-   get_imx_type((cpurev & 0xFF000) >> 12),
-   (cpurev & 0x000F0) >> 4,
-   (cpurev & 0xF) >> 0);
+  get_imx_type((cpurev & 0xFF000) >> 12),
+  (cpurev & 0x000F0) >> 4,
+  (cpurev & 0xF) >> 0);
if (is_cpu_type(MXC_CPU_MX6SX))
printf(" at %d MHz", mxc_get_clock(MXC_ARM_CLK) / 100);
else {
+#if defined(CONFIG_IMX6_THERMAL)
+   switch (get_cpu_temp_grade(&minc, &maxc)) {
+   case TEMP_AUTOMOTIVE:
+   puts(" automotive");
+   break;
+   case TEMP_INDUSTRIAL:
+   puts(" industrial");
+   break;
+   case TEMP_EXTCOMMERCIAL:
+   puts(" extended commercial");
+   break;
+   default:
+   puts(" commercial");
+   break;
+   }
+   printf(" (%dC to %dC)", minc, maxc);
printf(" %d MHz", get_cpu_speed_grade_hz() / 100);
if (get_cpu_speed_grade_hz() != mxc_get_clock(MXC_ARM_CLK)) {
printf(" (at %d MHz)",
   mxc_get_clock(MXC_ARM_CLK) / 100);
}
+#endif /* #if defined(CONFIG_IMX6_THERMAL) */
}
puts("\n");
 #else
@@ -172,7 +190,7 @@ int print_cpuinfo(void)
(cpurev & 0x000F0) >> 4,
(cpurev & 0xF) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 100);
-#endif
+#endif /* #if defined(CONFIG_MX6) */
 
 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h 
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index a2cd0a9..c583291 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -17,6 +17,7 @@
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
 u32 get_cpu_speed_grade_hz(void);
+u32 get_cpu_temp_grade(int *minc, int *maxc);
 
 /* returns MXC_CPU_ value */
 #define cpu_type(rev) (((rev) >> 12)&0xff)
diff --git a/include/imx_thermal.h b/include/imx_thermal.h
index be13652..8ce333c 100644
--- a/include/imx_thermal.h
+++ b/include/imx_thermal.h
@@ -8,6 +8,12 @@
 #ifndef _IMX_THERMAL_H_
 #define _IMX_THERMAL_H_
 
+/* CPU Temperature Grades */
+#define TEMP_COMMERCIAL 0
+#define TEMP_EXTCOMMERCIAL  1
+#define TEMP_INDUSTRIAL 2
+#define TEMP_AUTOMOTIVE   

[U-Boot] [PATCH 2/4] mx6: add OTP bank1 registers

[Tim Harvey]

Signed-off-by: Tim Harvey 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 9a4ad8b..35bb005 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -640,6 +640,25 @@ struct fuse_bank0_regs {
u32 rsvd7[3];
 };
 
+struct fuse_bank1_regs {
+   u32 mem0;
+   u32 rsvd0[3];
+   u32 mem1;
+   u32 rsvd1[3];
+   u32 mem2;
+   u32 rsvd2[3];
+   u32 mem3;
+   u32 rsvd3[3];
+   u32 mem4;
+   u32 rsvd4[3];
+   u32 ana0;
+   u32 rsvd5[3];
+   u32 ana1;
+   u32 rsvd6[3];
+   u32 ana2;
+   u32 rsvd7[3];
+};
+
 #ifdef CONFIG_MX6SX
 struct fuse_bank4_regs {
u32 sjc_resp_low;
-- 
1.9.1

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Re: [U-Boot] [PATCH] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support

[York Sun]

Rijay,

On 04/28/2015 04:15 AM, Ciubotariu Codrin Constantin-B43658 wrote:
>>
>>  #ifdef CONFIG_FMAN_ENET
>>  #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
>> -#define CONFIG_SYS_SGMII1_PHY_ADDR  0x03
>> +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
>> +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
>> +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
>> +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
>> +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
>> +#endif
> 
> The PHY address for SGMII PHY connected to FM1@DTSEC3 on T1040D4RDB should be 
> 0x01, not 0x02 (CONFIG_SYS_SGMII1_PHY_ADDR).
> 

Please check the PHY address. If you send a new patch, please rebase to the
latest master. A change is needed in defconfig file.

York
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Re: [U-Boot] Hi, guys.

[Jagan Teki]

On 28 April 2015 at 14:51, Wandy Lau  wrote:
> I am new to this project. But I am so interested with it and I want to dive
> into it. Where should I start ?

What you what to start with, see this wiki[1] for all details about
u-boot project
like documentation, development process, source code and etc..

[1] http://www.denx.de/wiki/U-Boot

thanks!
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Re: [U-Boot] Fat filesystem format support in u-boot

[Jagan Teki]

On 27 April 2015 at 11:13, S Durga Prasad Paladugu
 wrote:
> Hi All,
>
> I want to know whether we have FAT file system formatting support in u-boot?
> I would like to format my SD card from u-boot.

Probably formatting does it on host machine mostly.

+ Pantelis Antoniou may give more details.

thanks!
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Re: [U-Boot] [PATCH] New QorIQ p1020 based board support from Arcturus Networks Inc.

[York Sun]

Oleks,

I suggest to change the subject to "powerpc/mpc85xx: Add board support for 
ucp1020".

On 04/15/2015 12:37 PM, Oleksandr G Zhadan wrote:
> New QorIQ p1020 based board support from Arcturus Networks Inc.
> http://www.arcturusnetworks.com/products/ucp1020/
> 
> Signed-off-by: Michael Durrant 
> Signed-off-by: Oleksandr G Zhadan 
> ---



> +int get_arc_info(void)
> +{
> + int location = 1;
> +
> + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
> + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
> +
> + if (spi_flash_read(flash, (0x200 - sizeof(smac)), sizeof(smac), smac)) {
> + location++;
> + if (spi_flash_read(flash, (0x400 - sizeof(smac)), sizeof(smac), 
> smac)) {
> + location++;
> + if (spi_flash_read(flash, (CONFIG_ENV_SECT_SIZE + 0x200 
> - sizeof(smac)), sizeof(smac), smac)) {
> + location++;
> + if (spi_flash_read(flash, (CONFIG_ENV_SECT_SIZE 
> + 0x400 - sizeof(smac)), sizeof(smac), smac)) {
> + printf("%s: ERROR: Failed to read all 
> %d factory info spi locations\n", __func__, location);

These lines are way too long. Please wrap them back at or before 80 characters.
You can keep printf string in one line, but the arguments should be in next.

There are many lines over 80 characters. Please try to fix all.

York
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Re: [U-Boot] [PATCH] mpc85xx: gpio related compiler error fix when build common/cmd_gpio.c

[York Sun]

Oleks,

Suggest to change subject to "powerpc/mpc85xx: Fix compiling error for
common/cmd_gpio.c".

It would be helpful to put the compiling error into commit message.

On 04/15/2015 12:17 PM, Oleksandr G Zhadan wrote:
> 1. Include asm/mpc85xx_gpio.h into asm/gpio.h
> 2. Fix Incompatibility in functions gpio_free() and gpio_set_value() 
> definitions between  and 

Please wrap back at about 65-70 characters.

York
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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Tom Rini]

On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam  wrote:
> > Hi Tom,
> >
> > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:
> >
> >> Since we have FEC do we really need to add ASIX as well?  Also, what
> >
> > I can remove it if needed. Just kept the same as done in the Solidrun's 
> > U-boot.
> >
> >> devices did you test this with for USB?  I grabbed a Sandisk USB drive
> >> and on the i2eX I have, the bottom USB port doesn't see it and on the
> >> top I get:
> >> scanning bus 1 for devices... failed to set default configuration len 0,
> >> status 8000
> >
> > I tested with USB pen drive and USB keyboard and it could recognize them.
> >
> > Only the bottom top works for me and the same is seen on Solidrun's U-boot.
> 
> Ops, I mean "Only the bottom USB port works for me".

How many USB pen drives do you have handy?  I confirmed that my
keyboards don't work on my Allwinner board (A20 OLinuXino Lime2) but the
pen drive does (scanned, loaded and crc32'd a file).  I'll try and do
the same test on my Sabrelite shortly.

-- 
Tom


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Re: [U-Boot] [RFC PATCH v2] arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations

[Stefano Babic]

On 22/04/2015 17:37, Nikolay Dimitrov wrote:
> This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
> frequencies as per imx6 SOC models, and for dynamically calculating valid
> clock value based on mem_speed.
> 
> Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
> calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
> doesn't take into account DDR3 memory limitations.
> 
> Signed-off-by: Nikolay Dimitrov 
> Cc: Fabio Estevam 
> Cc: Stefano Babic 
> Cc: Tim Harvey 
> Cc: Eric Nelson 
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Tom Rini]

On Tue, Apr 28, 2015 at 12:39:41PM -0400, Tom Rini wrote:
> On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam  wrote:
> > > Hi Tom,
> > >
> > > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:
> > >
> > >> Since we have FEC do we really need to add ASIX as well?  Also, what
> > >
> > > I can remove it if needed. Just kept the same as done in the Solidrun's 
> > > U-boot.
> > >
> > >> devices did you test this with for USB?  I grabbed a Sandisk USB drive
> > >> and on the i2eX I have, the bottom USB port doesn't see it and on the
> > >> top I get:
> > >> scanning bus 1 for devices... failed to set default configuration len 0,
> > >> status 8000
> > >
> > > I tested with USB pen drive and USB keyboard and it could recognize them.
> > >
> > > Only the bottom top works for me and the same is seen on Solidrun's 
> > > U-boot.
> > 
> > Ops, I mean "Only the bottom USB port works for me".
> 
> How many USB pen drives do you have handy?  I confirmed that my
> keyboards don't work on my Allwinner board (A20 OLinuXino Lime2) but the
> pen drive does (scanned, loaded and crc32'd a file).  I'll try and do
> the same test on my Sabrelite shortly.

Same drive is good in my Sabrelite btw.

-- 
Tom


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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Jon Nettleton]

On Tue, Apr 28, 2015 at 6:39 PM, Tom Rini  wrote:

> On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam 
> wrote:
> > > Hi Tom,
> > >
> > > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:
> > >
> > >> Since we have FEC do we really need to add ASIX as well?  Also, what
> > >
> > > I can remove it if needed. Just kept the same as done in the
> Solidrun's U-boot.
> > >
> > >> devices did you test this with for USB?  I grabbed a Sandisk USB drive
> > >> and on the i2eX I have, the bottom USB port doesn't see it and on the
> > >> top I get:
> > >> scanning bus 1 for devices... failed to set default configuration len
> 0,
> > >> status 8000
> > >
> > > I tested with USB pen drive and USB keyboard and it could recognize
> them.
> > >
> > > Only the bottom top works for me and the same is seen on Solidrun's
> U-boot.
> >
> > Ops, I mean "Only the bottom USB port works for me".
>
> How many USB pen drives do you have handy?  I confirmed that my
> keyboards don't work on my Allwinner board (A20 OLinuXino Lime2) but the
> pen drive does (scanned, loaded and crc32'd a file).  I'll try and do
> the same test on my Sabrelite shortly.
>

Is CONFIG_SYS_USB_EVENT_POLL defined in the config?  I found that without
that usb input was not reliable.  Even with it enabled some wireless
keyboards behaved poorly.

-Jon


>
> --
> Tom
>
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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Otavio Salvador]

On Tue, Apr 28, 2015 at 1:45 PM, Jon Nettleton  wrote:
...
> Is CONFIG_SYS_USB_EVENT_POLL defined in the config?  I found that without
> that usb input was not reliable.  Even with it enabled some wireless
> keyboards behaved poorly.

For the keyboard it may indeed help but what about the USB pendrive?


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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Tom Rini]

On Tue, Apr 28, 2015 at 06:45:43PM +0200, Jon Nettleton wrote:
> On Tue, Apr 28, 2015 at 6:39 PM, Tom Rini  wrote:
> 
> > On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> > > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam 
> > wrote:
> > > > Hi Tom,
> > > >
> > > > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:
> > > >
> > > >> Since we have FEC do we really need to add ASIX as well?  Also, what
> > > >
> > > > I can remove it if needed. Just kept the same as done in the
> > Solidrun's U-boot.
> > > >
> > > >> devices did you test this with for USB?  I grabbed a Sandisk USB drive
> > > >> and on the i2eX I have, the bottom USB port doesn't see it and on the
> > > >> top I get:
> > > >> scanning bus 1 for devices... failed to set default configuration len
> > 0,
> > > >> status 8000
> > > >
> > > > I tested with USB pen drive and USB keyboard and it could recognize
> > them.
> > > >
> > > > Only the bottom top works for me and the same is seen on Solidrun's
> > U-boot.
> > >
> > > Ops, I mean "Only the bottom USB port works for me".
> >
> > How many USB pen drives do you have handy?  I confirmed that my
> > keyboards don't work on my Allwinner board (A20 OLinuXino Lime2) but the
> > pen drive does (scanned, loaded and crc32'd a file).  I'll try and do
> > the same test on my Sabrelite shortly.
> 
> Is CONFIG_SYS_USB_EVENT_POLL defined in the config?  I found that without
> that usb input was not reliable.  Even with it enabled some wireless
> keyboards behaved poorly.

Just checked and yes it's set.  I think I also had these not working
with the Solid Run tree either so I'll just call 'em both weird.

-- 
Tom


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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Otavio Salvador]

On Tue, Apr 28, 2015 at 1:52 PM, Tom Rini  wrote:
> On Tue, Apr 28, 2015 at 06:45:43PM +0200, Jon Nettleton wrote:
>> On Tue, Apr 28, 2015 at 6:39 PM, Tom Rini  wrote:
>>
>> > On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
>> > > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam 
>> > wrote:
>> > > > Hi Tom,
>> > > >
>> > > > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini  wrote:
>> > > >
>> > > >> Since we have FEC do we really need to add ASIX as well?  Also, what
>> > > >
>> > > > I can remove it if needed. Just kept the same as done in the
>> > Solidrun's U-boot.
>> > > >
>> > > >> devices did you test this with for USB?  I grabbed a Sandisk USB drive
>> > > >> and on the i2eX I have, the bottom USB port doesn't see it and on the
>> > > >> top I get:
>> > > >> scanning bus 1 for devices... failed to set default configuration len
>> > 0,
>> > > >> status 8000
>> > > >
>> > > > I tested with USB pen drive and USB keyboard and it could recognize
>> > them.
>> > > >
>> > > > Only the bottom top works for me and the same is seen on Solidrun's
>> > U-boot.
>> > >
>> > > Ops, I mean "Only the bottom USB port works for me".
>> >
>> > How many USB pen drives do you have handy?  I confirmed that my
>> > keyboards don't work on my Allwinner board (A20 OLinuXino Lime2) but the
>> > pen drive does (scanned, loaded and crc32'd a file).  I'll try and do
>> > the same test on my Sabrelite shortly.
>>
>> Is CONFIG_SYS_USB_EVENT_POLL defined in the config?  I found that without
>> that usb input was not reliable.  Even with it enabled some wireless
>> keyboards behaved poorly.
>
> Just checked and yes it's set.  I think I also had these not working
> with the Solid Run tree either so I'll just call 'em both weird.

In this case I think there is no reason to not merge this as is and
fix/improve it later.

-- 
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Re: [U-Boot] [PATCH 0/4]: imx: mx6: use OTP for temperature grade and freq grade

[Stefan Roese]

Hi Tim,

On 28.04.2015 17:44, Tim Harvey wrote:

The MX6 has OTP bits specifying the processor speed grade as well as
temperature grade.

This series adds functions to return this information as well as adds the
details to the CPU info displayed.

Additionally we use the temperature grade to replace the hard-coded limits
in imx_thermal.c

I expect some possible discussion/debate regarding the displaying of this info,
but perhaps adding the functions to obtain the info and use it for imx_thermal
is beyond debate. Please let me know.


Could you please send (or include in the commit text) an example, how 
these infos are displayed now in the bootup log? Best in comparison to 
the "old" log. To see the output change resulting from the patchset.


Thanks,
Stefan

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Re: [U-Boot] [PATCH 0/4]: imx: mx6: use OTP for temperature grade and freq grade

[Tim Harvey]

On Tue, Apr 28, 2015 at 10:11 AM, Stefan Roese  wrote:
> Hi Tim,
>
> On 28.04.2015 17:44, Tim Harvey wrote:
>>
>> The MX6 has OTP bits specifying the processor speed grade as well as
>> temperature grade.
>>
>> This series adds functions to return this information as well as adds the
>> details to the CPU info displayed.
>>
>> Additionally we use the temperature grade to replace the hard-coded limits
>> in imx_thermal.c
>>
>> I expect some possible discussion/debate regarding the displaying of this
>> info,
>> but perhaps adding the functions to obtain the info and use it for
>> imx_thermal
>> is beyond debate. Please let me know.
>
>
> Could you please send (or include in the commit text) an example, how these
> infos are displayed now in the bootup log? Best in comparison to the "old"
> log. To see the output change resulting from the patchset.
>
> Thanks,
> Stefan
>

Stefan,

Good point - as I am guessing there will be debate about the 'amount'
of info displayed and am open to suggestions on how to word it and/or
how to enable it. In future revs of the patchset I'll be more explicit
in the commit logs, but for now with the series applied I get this:

IMX6Q automotive (1GHz capable) powering up at 800MHz:
- before:
CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
- after Patch 1/4:
CPU:   Freescale i.MX6Q rev1.2 996 MHz (at 792 MHz)
- after Patch 3/4 (if CONFIG_IMX6_THERMAL defined)
CPU:   Freescale i.MX6Q rev1.2 automotive (-40C to 125C) 996 MHz (at 792 MHz)

IMX6S industrial (800MHz capable) powering up at 800MHz:
- before:
CPU:   Freescale i.MX6SOLO rev1.2 at 792 MHz
- after Patch 1/4: (max speed == cur speed)
CPU:   Freescale i.MX6SOLO rev1.2 792 MHz
- after Patch 3/4 (if CONFIG_IMX6_THERMAL defined)
CPU:   Freescale i.MX6SOLO rev1.2 industrial (-40C to 105C) 792 MHz

When I submit the next version I will split out adding the functions
to get speed-grade and temperature-grade from using those functions in
cpu_printinfo() as well as some may not be happy with adding more info
to cpu_printinfo() but may find value in setting the thermal limits of
imx_thermal properly based on temp-grade (Patch 4/4).

Tim
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[U-Boot] [PATCH] powerpc/mpc85xx: Fix compiling error for common/cmd_gpio.c

[Oleksandr G Zhadan]

To replicate:
1. add to include/configs/p1_p2_rdb_pc.h "#define CONFIG_CMD_GPIO"
2. run `make P1020RDB-PC_defconfig`
3. run CROSS_COMPILE=powerpc-linux- make

and you will get:
common/built-in.o: In function `do_gpio':
u-boot/common/cmd_gpio.c:186: undefined reference to `gpio_request'
u-boot/common/cmd_gpio.c:194: undefined reference to `gpio_direction_input'
u-boot/common/cmd_gpio.c:195: undefined reference to `gpio_get_value'
u-boot/common/cmd_gpio.c:200: undefined reference to `gpio_get_value'
u-boot/common/cmd_gpio.c:203: undefined reference to `gpio_direction_output'
u-boot/common/cmd_gpio.c:209: undefined reference to `gpio_free

Signed-off-by: Michael Durrant 
Signed-off-by: Oleksandr G Zhadan 
---

 arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 ++
 arch/powerpc/include/asm/mpc85xx_gpio.h  | 6 --
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h 
b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 8beed30..71794a8 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -12,4 +12,6 @@
 #ifndef __ASM_ARCH_MX85XX_GPIO_H
 #define __ASM_ARCH_MX85XX_GPIO_H
 
+#include 
+
 #endif
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h 
b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 87bb4a0..1d0dad4 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -72,9 +72,10 @@ static inline int gpio_request(unsigned gpio, const char 
*label)
return 0;
 }
 
-static inline void gpio_free(unsigned gpio)
+static inline int gpio_free(unsigned gpio)
 {
/* Compatibility shim */
+   return 0;
 }
 
 static inline int gpio_direction_input(unsigned gpio)
@@ -97,12 +98,13 @@ static inline int gpio_get_value(unsigned gpio)
return !!mpc85xx_gpio_get(1U << gpio);
 }
 
-static inline void gpio_set_value(unsigned gpio, int value)
+static inline int gpio_set_value(unsigned gpio, int value)
 {
if (value)
mpc85xx_gpio_set_high(1U << gpio);
else
mpc85xx_gpio_set_low(1U << gpio);
+   return 0;
 }
 
 static inline int gpio_is_valid(int gpio)
-- 
2.1.4

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Re: [U-Boot] HUSH logical AND/OR expressions

[Joe Hershberger]

Hi Joakim,

On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
 wrote:
> Trying to get a better handle of HUSH shell expressions, this does not work 
> as I expect:
> => false && true || echo ECHO
> => false && false || echo ECHO
>
> none prints ECHO, seems like a bug?

I think it works as it should. false followed by && will terminate always.

> This the only one that prints ECHO
>>= true && false || echo ECHO

This also seems correct. Passing true into && and false into || will
always continue.

Cheers,
-Joe
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Re: [U-Boot] HUSH logical AND/OR expressions

[James Chargin]

Dear Joe Hershberger,
On 04/28/2015 11:00 AM, Joe Hershberger wrote:

Hi Joakim,

On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
 wrote:

Trying to get a better handle of HUSH shell expressions, this does not work as 
I expect:
=> false && true || echo ECHO
=> false && false || echo ECHO

none prints ECHO, seems like a bug?


I think it works as it should. false followed by && will terminate always.


This the only one that prints ECHO

= true && false || echo ECHO


This also seems correct. Passing true into && and false into || will
always continue.



I thought hush is supposed to be mostly similar to sh. On my Linux 
desktop, bash (which is supposed to be backward compatible with sh) says


$ which sh
/usr/bin/sh
$ ls -l /usr/bin/sh
lrwxrwxrwx 1 root root 4 Apr 17 14:43 /usr/bin/sh -> bash
$ sh --version
GNU bash, version 4.2.46(1)-release (x86_64-redhat-linux-gnu)
Copyright (C) 2011 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later 



This is free software; you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
$ sh
sh-4.2$ false && true || echo ECHO
ECHO
sh-4.2$ false && false || echo ECHO
ECHO
sh-4.2$ true && false || echo ECHO
ECHO
sh-4.2$ exit
exit

Is this one of the places where hush and sh are not the same?

Regards,
Jim
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Re: [U-Boot] HUSH logical AND/OR expressions

[Joe Hershberger]

Hi James,

On Tue, Apr 28, 2015 at 1:19 PM, James Chargin  wrote:
> Dear Joe Hershberger,
>
> On 04/28/2015 11:00 AM, Joe Hershberger wrote:
>>
>> Hi Joakim,
>>
>> On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
>>  wrote:
>>>
>>> Trying to get a better handle of HUSH shell expressions, this does not
>>> work as I expect:
>>> => false && true || echo ECHO
>>> => false && false || echo ECHO
>>>
>>> none prints ECHO, seems like a bug?
>>
>>
>> I think it works as it should. false followed by && will terminate always.
>>
>>> This the only one that prints ECHO

 = true && false || echo ECHO
>>
>>
>> This also seems correct. Passing true into && and false into || will
>> always continue.
>>
>
> I thought hush is supposed to be mostly similar to sh. On my Linux desktop,
> bash (which is supposed to be backward compatible with sh) says
>
> $ which sh
> /usr/bin/sh
> $ ls -l /usr/bin/sh
> lrwxrwxrwx 1 root root 4 Apr 17 14:43 /usr/bin/sh -> bash
> $ sh --version
> GNU bash, version 4.2.46(1)-release (x86_64-redhat-linux-gnu)
> Copyright (C) 2011 Free Software Foundation, Inc.
> License GPLv3+: GNU GPL version 3 or later
> 
>
> This is free software; you are free to change and redistribute it.
> There is NO WARRANTY, to the extent permitted by law.
> $ sh
> sh-4.2$ false && true || echo ECHO
> ECHO
> sh-4.2$ false && false || echo ECHO
> ECHO
> sh-4.2$ true && false || echo ECHO
> ECHO
> sh-4.2$ exit
> exit
>
> Is this one of the places where hush and sh are not the same?

The way hush seems to work is it drops out of the entire command if a
case is false.

Looking at the code in the hush parser, it seems at face value like it
should be skipping the command and then picking up the next command
(echo), but it clearly doesn't.


if ( (rcode==EXIT_SUCCESS && pi->followup==PIPE_OR) ||
 (rcode!=EXIT_SUCCESS && pi->followup==PIPE_AND) )
skip_more_in_this_rmode=rmode;


I always just assumed this was a limitation of hush, but it's now
looking like a bug instead.

I haven't debugged into it, but I tend to stay away from hush these
days. When I've submitted a bug fix to this area I've been told that
we should upgrade wholesale instead, and I've haven't been up for that
task so far.  http://lists.denx.de/pipermail/u-boot/2012-November/139841.html

Perhaps there is an easy, minor bugfix for this that would be palette-able.

-Joe
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Re: [U-Boot] [PATCH 2/4] mx6cuboxi: Add USB host support

[Fabio Estevam]

On Tue, Apr 28, 2015 at 1:52 PM, Tom Rini  wrote:

>> Is CONFIG_SYS_USB_EVENT_POLL defined in the config?  I found that without
>> that usb input was not reliable.  Even with it enabled some wireless
>> keyboards behaved poorly.
>
> Just checked and yes it's set.  I think I also had these not working
> with the Solid Run tree either so I'll just call 'em both weird.

Does it improve if you remove CONFIG_SYS_USB_EVENT_POLL and use

#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP , instead?

While at it, please also try to add:

#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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Re: [U-Boot] HUSH logical AND/OR expressions

[James Chargin]

Dear Joe,

On 04/28/2015 11:35 AM, Joe Hershberger wrote:

Hi James,

On Tue, Apr 28, 2015 at 1:19 PM, James Chargin  wrote:

Dear Joe Hershberger,

On 04/28/2015 11:00 AM, Joe Hershberger wrote:


Hi Joakim,

On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
 wrote:


Trying to get a better handle of HUSH shell expressions, this does not
work as I expect:
=> false && true || echo ECHO
=> false && false || echo ECHO


...



I always just assumed this was a limitation of hush, but it's now
looking like a bug instead.

I haven't debugged into it, but I tend to stay away from hush these
days. When I've submitted a bug fix to this area I've been told that
we should upgrade wholesale instead, and I've haven't been up for that
task so far.  http://lists.denx.de/pipermail/u-boot/2012-November/139841.html


That's a great conversation with Wolfgang, thanks for the reference.

Like you, I have tended to use hush carefully. It is similar to sh/bash, 
but different enough that I never count on an easy port of bash script 
fragments.


I noticed you asked for a reference to the original hush code that is 
the origin for U-Boot's adaptation. I couldn't find a reply to that 
question. I also haven't been able to find anything with a quick we 
search. Do you know where it did come from?




Perhaps there is an easy, minor bugfix for this that would be palette-able.


I've been "afraid" of the hush code for a while. I don't think I want to 
mess with it now. I'll just continue to work with what we've got, carefully.


Thanks again for your attention,

Jim

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