[U-Boot] [PATCH v9 40/49] rockchip: spi: Correct the bus init code

[Simon Glass]

Two of the init values are created locally so cannot be out of range.
The masking is unnecessary and in one case is incorrect. Fix it.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index aaf139d..3418f9b 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -221,7 +221,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
 
/* Data Frame Size */
-   ctrlr0 |= spi_dfs & DFS_MASK << DFS_SHIFT;
+   ctrlr0 |= spi_dfs << DFS_SHIFT;
 
/* set SPI mode 0..3 */
if (priv->mode & SPI_CPOL)
@@ -242,7 +242,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
ctrlr0 |= FBM_MSB << FBM_SHIFT;
 
/* Byte and Halfword Transform */
-   ctrlr0 |= (spi_tf & HALF_WORD_MASK) << HALF_WORD_TX_SHIFT;
+   ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
 
/* Rxd Sample Delay */
ctrlr0 |= 0 << RXDSD_SHIFT;
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH 8/9] ARM: ARMv7: PSCI: ls102xa: add psci functions implemention

[Dongsheng Wang]

Hi Scott,

Thanks for your review.

> On Tue, 2016-01-19 at 06:28 +, Dongsheng Wang wrote:
> > Hi Scott,
> >
> > > On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > > > From: Wang Dongsheng 
> > > >
> > > > Based on PSCI v1.0, implement interface for ls102xa SoC:
> > > > psci_version,
> > > > psci_features,
> > > > psci_cpu_suspend,
> > > > psci_affinity_info,
> > > > psci_system_reset,
> > > > psci_system_off.
> > > >
> > > > Tested on LS1021aQDS, LS1021aTWR.
> > > >
> > > > Signed-off-by: Wang Dongsheng 
> > > > ---
> > > >  arch/arm/cpu/armv7/ls102xa/psci.S  | 110
> > > > +++--
> > > >  arch/arm/include/asm/arch-ls102xa/config.h |   1 +
> > > >  board/freescale/ls1021aqds/Makefile|   1 +
> > > >  board/freescale/ls1021aqds/psci.S  |  36 ++
> > > >  board/freescale/ls1021atwr/Makefile|   1 +
> > > >  board/freescale/ls1021atwr/psci.S  |  28 
> > > >  include/configs/ls1021aqds.h   |   3 +
> > > >  include/configs/ls1021atwr.h   |   1 +
> > > >  8 files changed, 177 insertions(+), 4 deletions(-)  create mode
> > > > 100644 board/freescale/ls1021aqds/psci.S  create mode 100644
> > > > board/freescale/ls1021atwr/psci.S
> > > >
> > > > diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S
> > > > b/arch/arm/cpu/armv7/ls102xa/psci.S
> > > > index 3091362..bfc908e 100644
> > > > --- a/arch/arm/cpu/armv7/ls102xa/psci.S
> > > > +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> > > > @@ -12,19 +12,72 @@
> > > >  #include   #include 
> > > >
> > > > +#define RCPM_TWAITSR   0x04C
> > > > +
> > > >  #define SCFG_CORE0_SFT_RST  0x130
> > > >  #define SCFG_CORESRENCR 0x204
> > > >
> > > > -#define DCFG_CCSR_BRR   0x0E4
> > > > -#define DCFG_CCSR_SCRATCHRW10x200
> > > > +#define DCFG_CCSR_RSTCR0x0B0
> > > > +#define DCFG_CCSR_RSTCR_RESET_REQ  0x2
> > > > +#define DCFG_CCSR_BRR  0x0E4
> > > > +#define DCFG_CCSR_SCRATCHRW1   0x200
> > > > +
> > > > +#define PSCI_FN_PSCI_VERSION_FEATURE_MASK  0x0
> > > > +#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK   0x0
> > > > +#define PSCI_FN_CPU_OFF_FEATURE_MASK   0x0
> > > > +#define PSCI_FN_CPU_ON_FEATURE_MASK0x0
> > > > +#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
> > > > +#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK0x0
> > > > +#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK  0x0
> > > >
> > > > .pushsection ._secure.text, "ax"
> > > >
> > > > .arch_extension sec
> > > >
> > > > +   .align  5
> > > > +
> > > >  #defineONE_MS  (GENERIC_TIMER_CLK / 1000)
> > > >  #defineRESET_WAIT  (30 * ONE_MS)
> > > >
> > > > +.globl psci_version
> > > > +psci_version:
> > > > +   movwr0, #0
> > > > +   movtr0, #1
> > > > +
> > > > +   bx  lr
> > > > +
> > > > +_ls102x_psci_supported_table:
> > > > +   .word   PSCI_FN_PSCI_VERSION
> > > > +   .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
> > > > +   .word   PSCI_FN_CPU_SUSPEND
> > > > +   .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
> > > > +   .word   PSCI_FN_CPU_OFF
> > > > +   .word   PSCI_FN_CPU_OFF_FEATURE_MASK
> > > > +   .word   PSCI_FN_CPU_ON
> > > > +   .word   PSCI_FN_CPU_ON_FEATURE_MASK
> > > > +   .word   PSCI_FN_AFFINITY_INFO
> > > > +   .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
> > > > +   .word   PSCI_FN_SYSTEM_OFF
> > > > +   .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
> > > > +   .word   PSCI_FN_SYSTEM_RESET
> > > > +   .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
> > > > +   .word   0
> > > > +   .word   PSCI_RET_NOT_SUPPORTED
> > >
> > > Can you use the main _psci_table instead of duplicating it?
> > >
> >
> > The main table does not apply here. Because this table shows what is
> > supported in our platform.
> 
> How does that set differ from what's in the main table?
> 

The main table include all of functions about PSCI spec. If we use main table
to match the pass in parameter, it will always return SUPPORT.

This table just we supported table, if the parameter not matched in this table
it will finally return NOT_SUPPORTED.

The main table include in functions ID and function handle, not match this 
feature
return value, we not need to get the functions handler, just need to return 
sub-feature,
and this table will return sub-feature if the PSCI ID be matched.

> > And this table also contains the sub-feature mask of PSCI functions.
> 
> ...which is always zero.  As of PSCI 1.0 there's only one function that 
> supports
> subfeatures, and you could put an explicit check in for that if it ever needs 
> a
> non-zero value.
> 

Yes, for now there is only one function that supports sub-features. But this 
table is
easy to extend, even if PSCI defines some other sub-features we just need to
take care this table, and not need to modify the code logic. :)

> > > > +
> > > > +.globl psci_fe

[U-Boot] [PATCH v9 05/49] power: Add base support for the RK808 PMIC

[Simon Glass]

This Rockchip PMIC provides features suitable for battery-powered
applications. It is commonly used with Rockchip SoCs.

Add a driver which provides register access. The regulator driver will use
this.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/power/pmic/Kconfig  |  9 +
 drivers/power/pmic/Makefile |  1 +
 drivers/power/pmic/rk808.c  | 96 +
 include/power/rk808_pmic.h  | 77 
 4 files changed, 183 insertions(+)
 create mode 100644 drivers/power/pmic/rk808.c
 create mode 100644 include/power/rk808_pmic.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index fb29843..8be3c07 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -33,6 +33,15 @@ config DM_PMIC_MAX77686
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
 
+config PMIC_RK808
+   bool "Enable support for Rockchip PMIC RK808"
+   depends on DM_PMIC
+   ---help---
+   The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
+   an RTC and two low Rds (resistance (drain to source)) switches. It is
+   accessed via an I2C interface. The device is used with Rockchip SoCs.
+   This driver implements register read/write operations.
+
 config PMIC_S2MPS11
bool "Enable Driver Model for PMIC Samsung S2MPS11"
depends on DM_PMIC
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 91e78f8..c6e8d0c 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
+obj-$(CONFIG_PMIC_RK808) += rk808.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
 
diff --git a/drivers/power/pmic/rk808.c b/drivers/power/pmic/rk808.c
new file mode 100644
index 000..11d5f07
--- /dev/null
+++ b/drivers/power/pmic/rk808.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+   { .prefix = "DCDC_REG", .driver = "rk808_buck"},
+   { .prefix = "LDO_REG", .driver = "rk808_ldo"},
+   { .prefix = "SWITCH_REG", .driver = "rk808_switch"},
+   { },
+};
+
+static int rk808_reg_count(struct udevice *dev)
+{
+   return RK808_NUM_OF_REGS;
+}
+
+static int rk808_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+   if (dm_i2c_write(dev, reg, buff, len)) {
+   debug("write error to device: %p register: %#x!", dev, reg);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+static int rk808_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+   if (dm_i2c_read(dev, reg, buff, len)) {
+   debug("read error from device: %p register: %#x!", dev, reg);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+static int rk808_bind(struct udevice *dev)
+{
+   const void *blob = gd->fdt_blob;
+   int regulators_node;
+   int children;
+
+   regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+"regulators");
+   if (regulators_node <= 0) {
+   debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+   return -ENXIO;
+   }
+
+   debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+   children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+   if (!children)
+   debug("%s: %s - no child found\n", __func__, dev->name);
+
+   /* Always return success for this device */
+   return 0;
+}
+#endif
+
+static struct dm_pmic_ops rk808_ops = {
+   .reg_count = rk808_reg_count,
+   .read = rk808_read,
+   .write = rk808_write,
+};
+
+static const struct udevice_id rk808_ids[] = {
+   { .compatible = "rockchip,rk808" },
+   { }
+};
+
+U_BOOT_DRIVER(pmic_rk808) = {
+   .name = "rk808 pmic",
+   .id = UCLASS_PMIC,
+   .of_match = rk808_ids,
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+   .bind = rk808_bind,
+#endif
+   .ops = &rk808_ops,
+};
diff --git a/include/power/rk808_pmic.h b/include/power/rk808_pmic.h
new file mode 100644
index 000..fb0800b
--- /dev/null
+++ b/include/power/rk808_pmic.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _PMIC_RK808_H_
+#define _PMIC_RK808_H_
+
+e

[U-Boot] [PATCH v2 29/37] rockchip: spl: Support full-speed CPU in SPL

[Simon Glass]

Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-veyron.dtsi |  2 +
 arch/arm/include/asm/arch-rockchip/clock.h  |  5 +++
 arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 12 ++
 arch/arm/mach-rockchip/rk3288/Kconfig   |  9 
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 36 
 configs/chromebook_jerry_defconfig  |  1 +
 drivers/clk/clk_rk3288.c| 56 +
 include/configs/chromebook_jerry.h  |  3 ++
 8 files changed, 124 insertions(+)

diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index c201e85..421d212 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -332,6 +332,7 @@
clock-frequency = <40>;
i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
i2c-scl-rising-time-ns = <100>; /* 45ns measured */
+   u-boot,dm-pre-reloc;
 
rk808: pmic@1b {
compatible = "rockchip,rk808";
@@ -344,6 +345,7 @@
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
+   u-boot,dm-pre-reloc;
 
vcc1-supply = <&vcc33_sys>;
vcc2-supply = <&vcc33_sys>;
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h 
b/arch/arm/include/asm/arch-rockchip/clock.h
index a9ea268..d66b26f 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -74,4 +74,9 @@ void *rockchip_get_cru(void);
  */
 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
 
+struct rk3288_cru;
+struct rk3288_grf;
+
+void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index b0dea70..d2690c7 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -109,6 +109,18 @@ enum {
SPI0_DIV_MASK   = 0x7f,
 };
 
+/* CRU_CLKSEL37_CON */
+enum {
+   PCLK_CORE_DBG_DIV_SHIFT = 9,
+   PCLK_CORE_DBG_DIV_MASK  = 0x1f,
+
+   ATCLK_CORE_DIV_CON_SHIFT = 4,
+   ATCLK_CORE_DIV_CON_MASK = 0x1f,
+
+   CLK_L2RAM_DIV_SHIFT = 0,
+   CLK_L2RAM_DIV_MASK  = 7,
+};
+
 /* CRU_CLKSEL39_CON */
 enum {
ACLK_HEVC_PLL_SHIFT = 0xe,
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index d0a7276..ed89c3e 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,6 +16,15 @@ config TARGET_CHROMEBOOK_JERRY
  WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
  the keyboard and battery functions.
 
+config ROCKCHIP_FAST_SPL
+   bool "Change the CPU to full speed in SPL"
+   depends on TARGET_CHROMEBOOK_JERRY
+   help
+ Some boards want to boot as fast as possible. We can increase the
+ CPU frequency in SPL if the power supply is configured to the correct
+ voltage. This option is only available on boards which support it
+ and have the required PMIC code.
+
 config SYS_SOC
default "rockchip"
 
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 074cf518..e9e2211 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -22,6 +22,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -748,6 +750,32 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 }
 
 #ifdef CONFIG_SPL_BUILD
+# ifdef CONFIG_ROCKCHIP_FAST_SPL
+static int veyron_init(struct dram_info *priv)
+{
+   struct udevice *pmic;
+   int ret;
+
+   ret = uclass_first_device(UCLASS_PMIC, &pmic);
+   if (ret)
+   return ret;
+
+   /* Slowly raise to max CPU voltage to prevent overshoot */
+   ret = rk808_spl_configure_buck(pmic, 1, 120);
+   if (ret)
+   return ret;
+   udelay(175);/* Must wait for voltage to stabilize, 2mV/us */
+   ret = rk808_spl_configure_buck(pmic, 1, 140);
+   if (ret)
+   return ret;
+   udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
+
+   rkclk_configure_cpu(priv->cru, priv->grf);
+
+   return 0;
+}
+# endif
+
 static int setup_sdram(struct udevice *dev)
 {
struct dram_info *priv = dev_get_priv(dev);
@@ -791,6 +819,14 @@ static int setup_sdram(struct udevice *dev)
return -EINVAL;
}
 
+# ifdef CONFIG_ROCKCHIP_FAST_SPL
+   if (!fdt_node_check_compatible(blob, 0, "google,veyron")) {
+   ret = veyron_init(priv);
+   

[U-Boot] [PATCH v9 09/49] rockchip: Convert the PMU IOMUX registers into an array

[Simon Glass]

This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.

Adjust it, adding an enum to improve readability.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 12 
 drivers/pinctrl/rockchip/pinctrl_rk3288.c   |  4 ++--
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
index 12fa685..081675e 100644
--- a/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
@@ -46,14 +46,18 @@ struct rk3288_pmu {
u32 gpio_op;
 
u32 gpio0_sel18;/* 0x80 */
-   u32 gpio0a_iomux;
-   u32 gpio0b_iomux;
-   u32 gpio0c_iomux;
-   u32 gpio0d_iomux;
+   u32 gpio0_iomux[4]; /* a, b, c, d */
u32 sys_reg[4];
 };
 check_member(rk3288_pmu, sys_reg[3], 0x00a0);
 
+enum {
+   PMU_GPIO0_A = 0,
+   PMU_GPIO0_B,
+   PMU_GPIO0_C,
+   PMU_GPIO0_D,
+};
+
 /* PMU_GPIO0_B_IOMUX */
 enum {
GPIO0_B7_SHIFT  = 14,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index c432a00..ec3c4fe 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -56,10 +56,10 @@ static void pinctrl_rk3288_i2c_config(struct rk3288_grf 
*grf,
 {
switch (i2c_id) {
case PERIPH_ID_I2C0:
-   clrsetbits_le32(&pmu->gpio0b_iomux,
+   clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
GPIO0_B7_MASK << GPIO0_B7_SHIFT,
GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
-   clrsetbits_le32(&pmu->gpio0b_iomux,
+   clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
GPIO0_C0_MASK << GPIO0_C0_SHIFT,
GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
break;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 14/49] rockchip: Use a separate clock ID for clocks

[Simon Glass]

At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.

Update the clock drivers and the code that uses them.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2:
- Update call to clk_get_by_index()

 configs/chromebook_jerry_defconfig |  1 +
 configs/firefly-rk3288_defconfig   |  1 +
 drivers/clk/clk_rk3036.c   | 16 +-
 drivers/clk/clk_rk3288.c   | 63 +-
 drivers/mmc/rockchip_dw_mmc.c  | 13 +++-
 5 files changed, 50 insertions(+), 44 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 456b6ea..5535105 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index f41c241..5b26a3d 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index f650810..dfecc24 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -13,8 +13,8 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -233,19 +233,19 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
 }
 
 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint 
clk_general_rate,
- enum periph_id periph)
+ int periph)
 {
uint src_rate;
uint div, mux;
u32 con;
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
-   case PERIPH_ID_SDCARD:
+   case HCLK_SDIO:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
@@ -259,7 +259,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
 }
 
 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint 
clk_general_rate,
- enum periph_id periph, uint freq)
+ int periph, uint freq)
 {
int src_clk_div;
int mux;
@@ -277,14 +277,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
}
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 mux << EMMC_PLL_SHIFT |
 (src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
-   case PERIPH_ID_SDCARD:
+   case HCLK_SDIO:
rk_clrsetreg(&cru->cru_clksel_con[11],
 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -320,7 +320,7 @@ static ulong rk3036_set_periph_rate(struct udevice *dev, 
int periph, ulong rate)
ulong new_rate;
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
periph, rate);
break;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 0172ad1..e410e7d1 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -14,7 +14,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -364,24 +364,24 @@ static ulong rk3288_clk_set_rate(struct udevice *dev, 
ulong rate)
 }
 
 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint 
clk_general_rate,
- enum periph_id periph)
+ int periph)
 {
uint src_rate;
uint div, mux;
u32 con;
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
 

[U-Boot] [PATCH v9 43/49] rockchip: pinctrl: Implement the get_gpio_mux() method

[Simon Glass]

Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 68 +++
 1 file changed, 52 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 53b8cf2..8356786 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -520,18 +520,16 @@ static int rk3288_pinctrl_set_state_simple(struct udevice 
*dev,
 }
 
 #ifndef CONFIG_SPL_BUILD
-static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
-  int muxval, int flags)
+int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
+   int banknum, int ind, u32 **addrp, uint *shiftp,
+   uint *maskp)
 {
-   struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
-   uint shift, muxnum, ind = index;
+   uint muxnum;
u32 *addr;
 
-   debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
for (muxnum = 0; muxnum < 4; muxnum++) {
struct rockchip_iomux *mux = &bank->iomux[muxnum];
-   uint mask;
 
if (ind >= 8) {
ind -= 8;
@@ -543,24 +541,61 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, 
int banknum, int index,
else
addr = (u32 *)priv->grf - 4;
addr += mux->offset;
-   shift = ind & 7;
+   *shiftp = ind & 7;
if (mux->type & IOMUX_WIDTH_4BIT) {
-   mask = 0xf;
-   shift *= 4;
-   if (shift >= 16) {
-   shift -= 16;
+   *maskp = 0xf;
+   *shiftp *= 4;
+   if (*shiftp >= 16) {
+   *shiftp -= 16;
addr++;
}
} else {
-   mask = 3;
-   shift *= 2;
+   *maskp = 3;
+   *shiftp *= 2;
}
 
debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
- mask, shift);
-   rk_clrsetreg(addr, mask << shift, muxval << shift);
-   break;
+ *maskp, *shiftp);
+   *addrp = addr;
+   return 0;
}
+
+   return -EINVAL;
+}
+
+static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+  int index)
+{
+   struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+   uint shift;
+   uint mask;
+   u32 *addr;
+   int ret;
+
+   ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
+ &mask);
+   if (ret)
+   return ret;
+   return (readl(addr) & mask) >> shift;
+}
+
+static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
+  int muxval, int flags)
+{
+   struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+   uint shift, ind = index;
+   uint mask;
+   u32 *addr;
+   int ret;
+
+   debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
+   ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
+ &mask);
+   if (ret)
+   return ret;
+   rk_clrsetreg(addr, mask << shift, muxval << shift);
+
+   /* Handle pullup/pulldown */
if (flags) {
uint val = 0;
 
@@ -618,6 +653,7 @@ static int rk3288_pinctrl_set_state(struct udevice *dev, 
struct udevice *config)
 static struct pinctrl_ops rk3288_pinctrl_ops = {
 #ifndef CONFIG_SPL_BUILD
.set_state  = rk3288_pinctrl_set_state,
+   .get_gpio_mux   = rk3288_pinctrl_get_gpio_mux,
 #endif
.set_state_simple   = rk3288_pinctrl_set_state_simple,
.request= rk3288_pinctrl_request,
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 26/49] rockchip: jerry: Drop unused options

[Simon Glass]

To reduce the SPL image size, drop the LED features. Jerry does not have
an LED and we can leave out GPIO support also.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 configs/chromebook_jerry_defconfig | 5 -
 include/configs/chromebook_jerry.h | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 99f6161..ceec6f5 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -22,9 +22,6 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_LED=y
-CONFIG_SPL_LED=y
-CONFIG_LED_GPIO=y
 CONFIG_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
@@ -34,10 +31,8 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
-CONFIG_PMIC_ACT8846=y
 CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
diff --git a/include/configs/chromebook_jerry.h 
b/include/configs/chromebook_jerry.h
index e29d776..78c06af 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -15,4 +15,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPI_FLASH_GIGADEVICE
 
+#undef CONFIG_SPL_GPIO_SUPPORT
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 32/37] rockchip: firefly-rk3288: Enable HDMI output

[Simon Glass]

Enable HDMI output and a console on firefly.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 configs/firefly-rk3288_defconfig | 7 +++
 include/configs/firefly-rk3288.h | 9 -
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index d8db532..15eb4d8 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -32,9 +32,13 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
@@ -42,6 +46,9 @@ CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_ROTATION=y
+CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index 8ac6521..d6423e7 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -7,7 +7,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS \
+   "stdin=serial,cros-ec-keyb\0" \
+   "stdout=serial,vidconsole\0" \
+   "stderr=serial,vidconsole\0"
 
 #include 
 
@@ -21,4 +24,8 @@
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 
+#define CONFIG_I2C_EDID
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES10
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 08/37] dm: backlight: Add a backlight uclass

[Simon Glass]

LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/Makefile   |  1 +
 drivers/video/backlight-uclass.c | 25 +
 include/backlight.h  | 31 +++
 include/dm/uclass-id.h   |  1 +
 4 files changed, 58 insertions(+)
 create mode 100644 drivers/video/backlight-uclass.c
 create mode 100644 include/backlight.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ee04629..fa90721 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -7,6 +7,7 @@
 
 ifdef CONFIG_DM
 obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o
+obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
 obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o
 obj-$(CONFIG_DM_VIDEO) += video_bmp.o
 obj-$(CONFIG_VIDEO_ROTATION) += console_rotate.o
diff --git a/drivers/video/backlight-uclass.c b/drivers/video/backlight-uclass.c
new file mode 100644
index 000..0238289
--- /dev/null
+++ b/drivers/video/backlight-uclass.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int backlight_enable(struct udevice *dev)
+{
+   const struct backlight_ops *ops = backlight_get_ops(dev);
+
+   if (!ops->enable)
+   return -ENOSYS;
+
+   return ops->enable(dev);
+}
+
+UCLASS_DRIVER(backlight) = {
+   .id = UCLASS_PANEL_BACKLIGHT,
+   .name   = "backlight",
+};
diff --git a/include/backlight.h b/include/backlight.h
new file mode 100644
index 000..90e1d98
--- /dev/null
+++ b/include/backlight.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _BACKLIGHT_H
+#define _BACKLIGHT_H
+
+struct backlight_ops {
+   /**
+* enable() - Enable a backlight
+*
+* @dev:Backlight device to enable
+* @return 0 if OK, -ve on error
+*/
+   int (*enable)(struct udevice *dev);
+};
+
+#define backlight_get_ops(dev) ((struct backlight_ops *)(dev)->driver->ops)
+
+/**
+ * backlight_enable() - Enable a backlight
+ *
+ * @dev:   Backlight device to enable
+ * @return 0 if OK, -ve on error
+ */
+int backlight_enable(struct udevice *dev);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 8f0381d..5421981 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -45,6 +45,7 @@ enum uclass_id {
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+   UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
UCLASS_PCH, /* x86 platform controller hub */
UCLASS_PCI, /* PCI bus */
UCLASS_PCI_GENERIC, /* Generic PCI bus device */
-- 
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[U-Boot] [PATCH v2 21/37] rockchip: config: Enable the 'gpio' command

[Simon Glass]

Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 include/configs/rk3288_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index b9ff5a5..ebf1ab0 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -79,6 +79,7 @@
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_GPIO
 
 #define CONFIG_SYS_SDRAM_BASE  0
 #define CONFIG_NR_DRAM_BANKS   1
-- 
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[U-Boot] [PATCH v2 05/37] video: bridge: Allow GPIOs to be optional

[Simon Glass]

Some video bridges will not have GPIOs to control reset, etc. Allow these
to be optional.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/bridge/video-bridge-uclass.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/video/bridge/video-bridge-uclass.c 
b/drivers/video/bridge/video-bridge-uclass.c
index 6c5990f..07270ba 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -55,7 +55,8 @@ static int video_bridge_pre_probe(struct udevice *dev)
   &uc_priv->sleep, GPIOD_IS_OUT);
if (ret) {
debug("%s: Could not decode sleep-gpios (%d)\n", __func__, ret);
-   return ret;
+   if (ret != -ENOENT)
+   return ret;
}
/*
 * Drop this for now as we do not have driver model pinctrl support
@@ -70,7 +71,8 @@ static int video_bridge_pre_probe(struct udevice *dev)
   GPIOD_IS_OUT);
if (ret) {
debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret);
-   return ret;
+   if (ret != -ENOENT)
+   return ret;
}
/*
 * Drop this for now as we do not have driver model pinctrl support
@@ -83,9 +85,10 @@ static int video_bridge_pre_probe(struct udevice *dev)
 */
ret = gpio_request_by_name(dev, "hotplug-gpios", 0, &uc_priv->hotplug,
   GPIOD_IS_IN);
-   if (ret && ret != -ENOENT) {
+   if (ret) {
debug("%s: Could not decode hotplug (%d)\n", __func__, ret);
-   return ret;
+   if (ret != -ENOENT)
+   return ret;
}
 
return 0;
-- 
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Re: [U-Boot] [PATCH v2] clk: add fixed rate clock driver

[Simon Glass]

On 19 January 2016 at 21:35, Simon Glass  wrote:
> On 18 January 2016 at 21:55, Masahiro Yamada
>  wrote:
>> This commit intends to implement "fixed-clock" as in Linux.
>> (drivers/clk/clk-fixed-rate.c in Linux)
>>
>> If you need a very simple clock to just provide fixed clock rate
>> like a crystal oscillator, you do not have to write a new driver.
>> This driver can support it.
>>
>> Signed-off-by: Masahiro Yamada 
>> ---
>>
>> Changes in v2:
>>   - Change file name from clk-fixed-rate.c to clk_fixed-rate.c
>>   - Use .ofdata_to_platdata method instead of .probe
>>   - Change driver name "Fixed Rate Clock" to "fixed_rate_clock"
>>
>>  drivers/clk/Makefile |  2 +-
>>  drivers/clk/clk_fixed_rate.c | 57 
>> 
>>  2 files changed, 58 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/clk_fixed_rate.c
>
> Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig

[Simon Glass]

Hi,

On 19 January 2016 at 22:32, Bin Meng  wrote:
> Hi Wenbin,
>
> On Wed, Jan 20, 2016 at 12:29 PM, Wenbin Song  wrote:
>> Hi: Bin,
>>
>> Could you tell me which  tree your patches have been merged into ?
>>
>
> I believe it will be merged via u-boot-dm, cc Simon to confirm.
>
>> Regards
>>
>> Wenbin Song
>>
>
> [snip]
>
> Regards,
> Bin

This should be in u-boot-dm now.

Regards,
Simon
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[U-Boot] [PATCH v2 35/37] rockchip: rock2: dts: Make changes for U-Boot

[Simon Glass]

Add the required pre-relocation tags and SDRAM init information for U-Boot.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-rock2-square.dts | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/rk3288-rock2-square.dts 
b/arch/arm/dts/rk3288-rock2-square.dts
index c5453a0..8d7446f 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -96,6 +96,7 @@
 };
 
 &sdmmc {
+   u-boot,dm-pre-reloc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@@ -138,6 +139,7 @@
 };
 
 &pinctrl {
+   u-boot,dm-pre-reloc;
ir {
ir_int: ir-int {
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -169,6 +171,8 @@
 
 &uart2 {
status = "okay";
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
 };
 
 &usbphy {
@@ -178,3 +182,20 @@
 &usb_host0_ehci {
status = "okay";
 };
+
+&dmc {
+   rockchip,num-channels = <2>;
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+&gpio7 {
+   u-boot,dm-pre-reloc;
+};
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH v4 01/50] dm: clk: Add support for decoding clocks from the device tree

[Simon Glass]

On 20 January 2016 at 20:04, Masahiro Yamada
 wrote:
> 2016-01-21 11:43 GMT+09:00 Simon Glass :
>> Add a method which can locate a clock for a device, given its index. This
>> uses the normal device tree bindings to return the clock device and the
>> first argument which is normally used as a peripheral ID in U-Boot.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>> Changes in v4:
>> - Add a static inline for when OF_CONTROL is not enabled
>>
>> Changes in v3:
>> - Use CONFIG_IS_ENABLED(OF_CONTROL) in C and header file
>>
>> Changes in v2:
>> - Make the peripheral ID a return value
>> - Add an assert for clk_devp
>> - Make the function dependent on OF_CONTROL
>
>
> Reviewed-by: Masahiro Yamada 

Added errno.h header from http://patchwork.ozlabs.org/patch/571013/

Applied to u-boot-rockchip.
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[U-Boot] [PATCH v9 20/49] rockchip: spi: Avoid setting the pinctrl twice

[Simon Glass]

If full pinctrl is enabled we don't need to manually set the pinctrl in the
driver. It will happen automatically. Adjust the code to suit - we will
still use manual mode in SPL.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 62434be..2b58393 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -182,13 +182,15 @@ static int rockchip_spi_probe(struct udevice *bus)
 static int rockchip_spi_claim_bus(struct udevice *dev)
 {
struct udevice *bus = dev->parent;
-   struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
-   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u8 spi_dfs, spi_tf;
uint ctrlr0;
+#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
+   struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
int ret;
+#endif
 
/* Disable the SPI hardware */
rkspi_enable_chip(regs, 0);
@@ -249,12 +251,13 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 
writel(ctrlr0, ®s->ctrlr0);
-
+#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
if (ret) {
debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
return ret;
}
+#endif
 
return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 00/49] rockchip: Add support for cros_ec keyboard

[Simon Glass]

This series provides a number of new features and improvements leading to
enabling the keyboard (via Chrome OS EC) on jerry. This is conneected via
SPI and uses its own message protocol.

Features and fixes are needed in the rockchip code to make this work include:
- RK808 PMIC and regulator driver
- Fixes and improvements to the i2c and SPI drivers
- A full implementation of the GPIO driver
- Additional clock support
- Additional pinctrl support

The series moves a few rockchip boards to use the full pinctrl driver. I'm
not sure this is a great idea, as it slows down start-up noticeably. It is
currently needed for the display series (to come), but I intend to change
that.

Changes in v9:
- Rebase to upstream/master

Changes in v2:
- Update call to clk_get_by_index()
- Update call to clk_get_by_index()
- Update call to clk_get_by_index()
- Add an assert for clk_devp

Simon Glass (49):
  dm: core: Don't set pinctrl for pinctrl devices
  dm: pinctrl: Add a function to parse PIN_CONFIG flags
  dm: pmic: Add 'reg status' to show all regulators
  dts: Bring in pinctrl device tree binding
  power: Add base support for the RK808 PMIC
  power: Add support for RK808 regulators
  dm: Add a power sequencing uclass
  rockchip: Avoid using MMC code when not booting from MMC
  rockchip: Convert the PMU IOMUX registers into an array
  rockchip: mmc: Use a pwrseq device if available
  rockchip: Correct the defconfig order
  rockchip: Use pwrseq for MMC start-up on jerry
  rockchip: jerry: Disable pmic-int-1 setup to avoid a hang
  rockchip: Use a separate clock ID for clocks
  rockchip: clock: Rename the general clock variable to gclk_rate
  rockchip: clk: Add a function to get a peripheral clock rate
  rockchip: clock: Add a function to find a clock by ID
  rockchip: i2c: Update the driver to use the new clock ID
  rockchip: spi: Update the driver to use the new clock ID
  rockchip: spi: Avoid setting the pinctrl twice
  rockchip: mmc: Update the driver to use the new clock ID
  rockchip: pinctrl: Add a full pinctrl driver
  rockchip: Move firefly and jerry to use the full pinctrl
  rockchip: jerry: Enable the RK808 PMIC and regulator
  rockchip: Disable simple-bus in SPL for firefly-rk3288, jerry
  rockchip: jerry: Drop unused options
  gpio: Allow 's' as an abbreviation for 'status'
  cros_ec: Disable the Chrome OS EC in SPL
  dm: i2c: Allow muxes to be enabled for SPL separately
  spi: Correct device tree usage in spi_flash_decode_fdt()
  dm: power: Allow regulators to be omitted from SPL
  dm: pinctrl: Add a way for a GPIO driver to obtain a pin function
  dm: core: Export uclass_find_device_by_of_offset()
  dm: power: Tidy up debugging output and return values
  dm: power: Allow regulators to not implement all operations
  dm: clk: Add a simple version of clk_get_by_index()
  rockchip: sdram: Use the rk_clr/setreg() interface
  rockchip: reset: Use the rk_clr/setreg() interface
  rockchip: spi: Remember the last speed to avoid re-setting it
  rockchip: spi: Correct the bus init code
  rockchip: clk: Make rkclk_get_clk() SoC-specific
  rockchip: pinctrl: Reduce the size for SPL
  rockchip: pinctrl: Implement the get_gpio_mux() method
  rockchip: gpio: Read the GPIO value correctly
  rockchip: gpio: Implement the get_function() method
  rockchip: spi: Implement the delays
  rockchip: spi: Correct chip-enable code
  rockchip: spi: Remove the explicit pinctrl setting
  rockchip: jerry: Enable the Chrome OS EC

 arch/arm/dts/rk3288-veyron-chromebook.dtsi |   4 +
 arch/arm/dts/rk3288-veyron.dtsi|  20 +-
 arch/arm/include/asm/arch-rockchip/clock.h |  12 +
 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h|  12 +-
 arch/arm/mach-rockchip/Makefile|   1 -
 arch/arm/mach-rockchip/common.c|  28 --
 arch/arm/mach-rockchip/rk3288-board-spl.c  |   2 +
 arch/arm/mach-rockchip/rk3288/reset_rk3288.c   |   4 +-
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c   |   7 +-
 common/cmd_gpio.c  |   2 +-
 common/cmd_regulator.c |  66 -
 configs/chromebook_jerry_defconfig |  25 +-
 configs/firefly-rk3288_defconfig   |   7 +-
 .../pinctrl/pinctrl-bindings.txt   | 236 
 drivers/clk/clk-uclass.c   |  18 +-
 drivers/clk/clk_rk3036.c   |  33 ++-
 drivers/clk/clk_rk3288.c   | 157 ---
 drivers/core/device.c  |   6 +-
 drivers/core/uclass.c  |   4 +-
 drivers/gpio/rk_gpio.c |  42 ++-
 drivers/i2c/Makefile   |   4 +-
 drivers/i2c/muxes/Kconfig  |   9 +
 drivers/i2c/muxes/Makefile |   2 +-
 drivers/i2c/rk_i2c.c   |  38 +--
 drivers/misc/Kconfig  

[U-Boot] [PATCH v2 31/37] rockchip: jerry: Enable EDP and HDMI video output

[Simon Glass]

Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-jerry.dts  | 5 +
 arch/arm/dts/rk3288.dtsi   | 1 +
 configs/chromebook_jerry_defconfig | 6 ++
 include/configs/chromebook_jerry.h | 8 ++--
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-jerry.dts
index da37ea8..2aa3b9f 100644
--- a/arch/arm/dts/rk3288-jerry.dts
+++ b/arch/arm/dts/rk3288-jerry.dts
@@ -108,6 +108,11 @@
pinctrl-0 = <&vcc50_hdmi_en>;
 };
 
+&vopb {
+   /* Disable this so that we use vopl */
+   status = "disabled";
+};
+
 &edp {
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index ac367f8..fb1d1f7 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -692,6 +692,7 @@
iommus = <&vopl_mmu>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
+   u-boot,dm-pre-reloc;
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 526306f..27e53c1 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -42,7 +42,10 @@ CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_RK808=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
@@ -51,6 +54,9 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_ROTATION=y
+CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/chromebook_jerry.h 
b/include/configs/chromebook_jerry.h
index 2a0dad4..150e876 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -9,8 +9,8 @@
 
 #define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,cros-ec-keyb\0" \
-   "stdout=serial\0" \
-   "stderr=serial\0"
+   "stdout=serial,vidconsole\0" \
+   "stderr=serial,vidconsole\0"
 
 #include 
 
@@ -30,4 +30,8 @@
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
 
+#define CONFIG_I2C_EDID
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES10
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 06/37] dm: pwm: Add a PWM uclass

[Simon Glass]

Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/Kconfig  |  2 ++
 drivers/pwm/Kconfig  | 10 +
 drivers/pwm/Makefile |  1 +
 drivers/pwm/pwm-uclass.c | 36 
 include/dm/uclass-id.h   |  1 +
 include/pwm.h| 53 
 6 files changed, 103 insertions(+)
 create mode 100644 drivers/pwm/Kconfig
 create mode 100644 drivers/pwm/pwm-uclass.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index c481e93..70993fd 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -46,6 +46,8 @@ source "drivers/pinctrl/Kconfig"
 
 source "drivers/power/Kconfig"
 
+source "drivers/pwm/Kconfig"
+
 source "drivers/ram/Kconfig"
 
 source "drivers/remoteproc/Kconfig"
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
new file mode 100644
index 000..bd47159
--- /dev/null
+++ b/drivers/pwm/Kconfig
@@ -0,0 +1,10 @@
+config DM_PWM
+   bool "Enable support for pulse-width modulation devices (PWM)"
+   depends on DM
+   help
+ A pulse-width modulator emits a pulse of varying width and provides
+ control over the duty cycle (high and low time) of the signal. This
+ is often used to control a voltage level. The more time the PWM
+ spends in the 'high' state, the higher the voltage. The PWM's
+ frequency/period can be controlled along with the proportion of that
+ time that the signal is high.
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c0c4883..d1b15e5 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -10,4 +10,5 @@
 
 #ccflags-y += -DDEBUG
 
+obj-$(CONFIG_DM_PWM) += pwm-uclass.o
 obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
diff --git a/drivers/pwm/pwm-uclass.c b/drivers/pwm/pwm-uclass.c
new file mode 100644
index 000..c2200af
--- /dev/null
+++ b/drivers/pwm/pwm-uclass.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
+  uint duty_ns)
+{
+   struct pwm_ops *ops = pwm_get_ops(dev);
+
+   if (!ops->set_config)
+   return -ENOSYS;
+
+   return ops->set_config(dev, channel, period_ns, duty_ns);
+}
+
+int pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+   struct pwm_ops *ops = pwm_get_ops(dev);
+
+   if (!ops->set_enable)
+   return -ENOSYS;
+
+   return ops->set_enable(dev, channel, enable);
+}
+
+UCLASS_DRIVER(pwm) = {
+   .id = UCLASS_PWM,
+   .name   = "pwm",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index b5f43ae..8f0381d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -51,6 +51,7 @@ enum uclass_id {
UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
UCLASS_PINCONFIG,   /* Pin configuration node device */
UCLASS_PMIC,/* PMIC I/O device */
+   UCLASS_PWM, /* Pulse-width modulator */
UCLASS_PWRSEQ,  /* Power sequence device */
UCLASS_REGULATOR,   /* Regulator device */
UCLASS_RESET,   /* Reset device */
diff --git a/include/pwm.h b/include/pwm.h
index f24f220..851915e 100644
--- a/include/pwm.h
+++ b/include/pwm.h
@@ -1,6 +1,7 @@
 /*
  * header file for pwm driver.
  *
+ * Copyright 2016 Google Inc.
  * Copyright (c) 2011 samsung electronics
  * Donghwa Lee 
  *
@@ -10,9 +11,61 @@
 #ifndef _pwm_h_
 #define _pwm_h_
 
+/* struct pwm_ops: Operations for the PWM uclass */
+struct pwm_ops {
+   /**
+* set_config() - Set the PWM configuration
+*
+* @dev:PWM device to update
+* @channel:PWM channel to update
+* @period_ns:  PWM period in nanoseconds
+* @duty_ns:PWM duty period in nanoseconds
+* @return 0 if OK, -ve on error
+*/
+   int (*set_config)(struct udevice *dev, uint channel, uint period_ns,
+ uint duty_ns);
+
+   /**
+* set_enable() - Enable or disable the PWM
+*
+* @dev:PWM device to update
+* @channel:PWM channel to update
+* @enable: true to enable, false to disable
+* @return 0 if OK, -ve on error
+*/
+   int (*set_enable)(struct udevice *dev, uint channel, bool enable);
+};
+
+#define pwm_get_ops(dev)   ((struct pwm_ops *)(dev)->driver->ops)
+
+/**
+ * pwm_set_config() - Set the PWM configuration
+ *
+ * @dev:   PWM device to update
+ * @channel:   PWM channel to update
+ * @period_ns: PWM period in nanoseconds
+ * @duty_ns:   PWM duty period in nanoseconds
+ * @return 0 if OK, -ve on error
+ */
+int pwm_set_config(struct ud

[U-Boot] [PATCH v9 16/49] rockchip: clk: Add a function to get a peripheral clock rate

[Simon Glass]

It is useful to be able to read the rate of a peripheral clock. Add a
handler for that.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/clk/clk_rk3288.c | 37 +
 1 file changed, 37 insertions(+)

diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 49c2bdf..df5c38c 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -508,6 +508,42 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, 
uint gclk_rate,
return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
+static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
+{
+   struct rk3288_clk_priv *priv = dev_get_priv(dev);
+   struct udevice *gclk;
+   ulong new_rate, gclk_rate;
+   int ret;
+
+   ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+   if (ret)
+   return ret;
+   gclk_rate = clk_get_rate(gclk);
+   switch (periph) {
+   case HCLK_EMMC:
+   case HCLK_SDIO0:
+   case HCLK_SDIO1:
+   new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
+   break;
+   case SCLK_SPI0:
+   case SCLK_SPI1:
+   case SCLK_SPI2:
+   new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
+   break;
+   case PCLK_I2C0:
+   case PCLK_I2C1:
+   case PCLK_I2C2:
+   case PCLK_I2C3:
+   case PCLK_I2C4:
+   case PCLK_I2C5:
+   return gclk_rate;
+   default:
+   return -ENOENT;
+   }
+
+   return new_rate;
+}
+
 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong 
rate)
 {
struct rk3288_clk_priv *priv = dev_get_priv(dev);
@@ -543,6 +579,7 @@ static struct clk_ops rk3288_clk_ops = {
.get_rate   = rk3288_clk_get_rate,
.set_rate   = rk3288_clk_set_rate,
.set_periph_rate = rk3288_set_periph_rate,
+   .get_periph_rate = rk3288_get_periph_rate,
 };
 
 static int rk3288_clk_probe(struct udevice *dev)
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 25/49] rockchip: Disable simple-bus in SPL for firefly-rk3288, jerry

[Simon Glass]

This is not needed for booting, so drop it from SPL to save about 300 bytes.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 configs/chromebook_jerry_defconfig | 1 +
 configs/firefly-rk3288_defconfig   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index a0af6ec..99f6161 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -17,6 +17,7 @@ CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 7d8ca6c..d8db532 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -17,6 +17,7 @@ CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 44/49] rockchip: gpio: Read the GPIO value correctly

[Simon Glass]

This function should return 0 or 1, not a mask. Fix it.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/gpio/rk_gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index fbdf9f3..a22e219 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -53,7 +53,7 @@ static int rockchip_gpio_get_value(struct udevice *dev, 
unsigned offset)
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct rockchip_gpio_regs *regs = priv->regs;
 
-   return readl(®s->ext_port) & OFFSET_TO_BIT(offset);
+   return readl(®s->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
 }
 
 static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 48/49] rockchip: spi: Remove the explicit pinctrl setting

[Simon Glass]

The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 28 ++--
 1 file changed, 2 insertions(+), 26 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 412fa8b..9eff423 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -27,8 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG_RK_SPI   0
 
 struct rockchip_spi_platdata {
-   int periph_id;
-   struct udevice *pinctrl;
s32 frequency;  /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us;   /* Delay to wait after deactivate */
@@ -139,17 +137,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
int ret;
 
plat->base = dev_get_addr(bus);
-   ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
-   if (ret)
-   return ret;
-   ret = pinctrl_get_periph_id(plat->pinctrl, bus);
 
-   if (ret < 0) {
-   debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
- bus->name, ret);
-   return ret;
-   }
-   plat->periph_id = ret;
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
debug("%s: Could not get clock for %s: %d\n", __func__,
@@ -164,8 +152,8 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
"spi-deactivate-delay", 0);
plat->activate_delay_us = fdtdec_get_int(blob, node,
 "spi-activate-delay", 0);
-   debug("%s: base=%x, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
- __func__, (uint)plat->base, plat->periph_id, plat->frequency,
+   debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, (uint)plat->base, plat->frequency,
  plat->deactivate_delay_us);
 
return 0;
@@ -207,11 +195,6 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
struct rockchip_spi *regs = priv->regs;
u8 spi_dfs, spi_tf;
uint ctrlr0;
-#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
-   struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
-   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
-   int ret;
-#endif
 
/* Disable the SPI hardware */
rkspi_enable_chip(regs, 0);
@@ -273,13 +256,6 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 
writel(ctrlr0, ®s->ctrlr0);
-#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
-   ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
-   if (ret) {
-   debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
-   return ret;
-   }
-#endif
 
return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 15/37] rockchip: video: Add a display driver for rockchip HDMI

[Simon Glass]

Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Update for new clk_get_by_index() API

 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 +++
 drivers/video/Kconfig|  10 +
 drivers/video/Makefile   |   1 +
 drivers/video/rockchip/Makefile  |   8 +
 drivers/video/rockchip/rk_hdmi.c | 933 +++
 5 files changed, 1408 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
 create mode 100644 drivers/video/rockchip/Makefile
 create mode 100644 drivers/video/rockchip/rk_hdmi.c

diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
new file mode 100644
index 000..0b51d40
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
@@ -0,0 +1,456 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HDMI_H
+#define _ASM_ARCH_HDMI_H
+
+
+#define HDMI_EDID_BLOCK_SIZE128
+
+struct rk3288_hdmi {
+   u32 reserved0[0x100];
+   u32 ih_fc_stat0;
+   u32 ih_fc_stat1;
+   u32 ih_fc_stat2;
+   u32 ih_as_stat0;
+   u32 ih_phy_stat0;
+   u32 ih_i2cm_stat0;
+   u32 ih_cec_stat0;
+   u32 ih_vp_stat0;
+   u32 ih_i2cmphy_stat0;
+   u32 ih_ahbdmaaud_stat0;
+   u32 reserved1[0x17f-0x109];
+   u32 ih_mute_fc_stat0;
+   u32 ih_mute_fc_stat1;
+   u32 ih_mute_fc_stat2;
+   u32 ih_mute_as_stat0;
+   u32 ih_mute_phy_stat0;
+   u32 ih_mute_i2cm_stat0;
+   u32 ih_mute_cec_stat0;
+   u32 ih_mute_vp_stat0;
+   u32 ih_mute_i2cmphy_stat0;
+   u32 ih_mute_ahbdmaaud_stat0;
+   u32 reserved2[0x1fe - 0x189];
+   u32 ih_mute;
+   u32 tx_invid0;
+   u32 tx_instuffing;
+   u32 tx_gydata0;
+   u32 tx_gydata1;
+   u32 tx_rcrdata0;
+   u32 tx_rcrdata1;
+   u32 tx_bcbdata0;
+   u32 tx_bcbdata1;
+   u32 reserved3[0x7ff-0x207];
+   u32 vp_status;
+   u32 vp_pr_cd;
+   u32 vp_stuff;
+   u32 vp_remap;
+   u32 vp_conf;
+   u32 vp_stat;
+   u32 vp_int;
+   u32 vp_mask;
+   u32 vp_pol;
+   u32 reserved4[0xfff-0x808];
+   u32 fc_invidconf;
+   u32 fc_inhactv0;
+   u32 fc_inhactv1;
+   u32 fc_inhblank0;
+   u32 fc_inhblank1;
+   u32 fc_invactv0;
+   u32 fc_invactv1;
+   u32 fc_invblank;
+   u32 fc_hsyncindelay0;
+   u32 fc_hsyncindelay1;
+   u32 fc_hsyncinwidth0;
+   u32 fc_hsyncinwidth1;
+   u32 fc_vsyncindelay;
+   u32 fc_vsyncinwidth;
+   u32 fc_infreq0;
+   u32 fc_infreq1;
+   u32 fc_infreq2;
+   u32 fc_ctrldur;
+   u32 fc_exctrldur;
+   u32 fc_exctrlspac;
+   u32 fc_ch0pream;
+   u32 fc_ch1pream;
+   u32 fc_ch2pream;
+   u32 fc_aviconf3;
+   u32 fc_gcp;
+   u32 fc_aviconf0;
+   u32 fc_aviconf1;
+   u32 fc_aviconf2;
+   u32 fc_avivid;
+   u32 fc_avietb0;
+   u32 fc_avietb1;
+   u32 fc_avisbb0;
+   u32 fc_avisbb1;
+   u32 fc_avielb0;
+   u32 fc_avielb1;
+   u32 fc_avisrb0;
+   u32 fc_avisrb1;
+   u32 fc_audiconf0;
+   u32 fc_audiconf1;
+   u32 fc_audiconf2;
+   u32 fc_audiconf3;
+   u32 fc_vsdieeeid0;
+   u32 fc_vsdsize;
+   u32 reserved7[0x2fff-0x102a];
+   u32 phy_conf0;
+   u32 phy_tst0;
+   u32 phy_tst1;
+   u32 phy_tst2;
+   u32 phy_stat0;
+   u32 phy_int0;
+   u32 phy_mask0;
+   u32 phy_pol0;
+   u32 reserved8[0x301f-0x3007];
+   u32 phy_i2cm_slave_addr;
+   u32 phy_i2cm_address_addr;
+   u32 phy_i2cm_datao_1_addr;
+   u32 phy_i2cm_datao_0_addr;
+   u32 phy_i2cm_datai_1_addr;
+   u32 phy_i2cm_datai_0_addr;
+   u32 phy_i2cm_operation_addr;
+   u32 phy_i2cm_int_addr;
+   u32 phy_i2cm_ctlint_addr;
+   u32 phy_i2cm_div_addr;
+   u32 phy_i2cm_softrstz_addr;
+   u32 phy_i2cm_ss_scl_hcnt_1_addr;
+   u32 phy_i2cm_ss_scl_hcnt_0_addr;
+   u32 phy_i2cm_ss_scl_lcnt_1_addr;
+   u32 phy_i2cm_ss_scl_lcnt_0_addr;
+   u32 phy_i2cm_fs_scl_hcnt_1_addr;
+   u32 phy_i2cm_fs_scl_hcnt_0_addr;
+   u32 phy_i2cm_fs_scl_lcnt_1_addr;
+   u32 phy_i2cm_fs_scl_lcnt_0_addr;
+   u32 reserved9[0x30ff-0x3032];
+   u32 aud_conf0;
+   u32 aud_conf1;
+   u32 aud_int;
+   u32 aud_conf2;
+   u32 aud_int1;
+   u32 reserved32[0x31ff-0x3104];
+ 

[U-Boot] [PATCH v9 35/49] dm: power: Allow regulators to not implement all operations

[Simon Glass]

Some regulators will not implement any operations (e.g. fixed regulators).
This is not an error, so allow the autoset process to continue when one
of these regulators is found.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/power/regulator/regulator-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/power/regulator/regulator-uclass.c 
b/drivers/power/regulator/regulator-uclass.c
index fec2886..9fe07f2 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -334,6 +334,8 @@ int regulators_enable_boot_on(bool verbose)
}
if (verbose)
regulator_show(dev, ret);
+   if (ret == -ENOSYS)
+   ret = 0;
}
 
return ret;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 22/49] rockchip: pinctrl: Add a full pinctrl driver

[Simon Glass]

We can make use of the device tree to configure pinctrl settings. Add this
support for the driver so we can use it in U-Boot proper.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 230 +-
 1 file changed, 229 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index ec3c4fe..0e7721e 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -24,8 +24,103 @@ DECLARE_GLOBAL_DATA_PTR;
 struct rk3288_pinctrl_priv {
struct rk3288_grf *grf;
struct rk3288_pmu *pmu;
+   int num_banks;
 };
 
+/**
+ * Encode variants of iomux registers into a type variable
+ */
+#define IOMUX_GPIO_ONLYBIT(0)
+#define IOMUX_WIDTH_4BIT   BIT(1)
+#define IOMUX_SOURCE_PMU   BIT(2)
+#define IOMUX_UNROUTED BIT(3)
+
+/**
+ * @type: iomux variant using IOMUX_* constants
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ * an initial offset value the relevant source offset can be reset
+ * to a new value for autocalculating the following iomux registers.
+ */
+struct rockchip_iomux {
+   u8 type;
+   s16 offset;
+};
+
+/**
+ * @reg: register offset of the gpio bank
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @name: name of the bank
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+   u16 reg;
+   u8 nr_pins;
+   u8 bank_num;
+   char *name;
+   struct rockchip_iomux iomux[4];
+};
+
+#define PIN_BANK(id, pins, label)  \
+   {   \
+   .bank_num   = id,   \
+   .nr_pins= pins, \
+   .name   = label,\
+   .iomux  = { \
+   { .offset = -1 },   \
+   { .offset = -1 },   \
+   { .offset = -1 },   \
+   { .offset = -1 },   \
+   },  \
+   }
+
+#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)  \
+   {   \
+   .bank_num   = id,   \
+   .nr_pins= pins, \
+   .name   = label,\
+   .iomux  = { \
+   { .type = iom0, .offset = -1 }, \
+   { .type = iom1, .offset = -1 }, \
+   { .type = iom2, .offset = -1 }, \
+   { .type = iom3, .offset = -1 }, \
+   },  \
+   }
+
+#ifndef CONFIG_SPL_BUILD
+static struct rockchip_pin_bank rk3288_pin_banks[] = {
+   PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+IOMUX_SOURCE_PMU,
+IOMUX_SOURCE_PMU,
+IOMUX_UNROUTED
+   ),
+   PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
+IOMUX_UNROUTED,
+IOMUX_UNROUTED,
+0
+   ),
+   PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
+   PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
+   PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+IOMUX_WIDTH_4BIT,
+0,
+0
+   ),
+   PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
+0,
+0,
+IOMUX_UNROUTED
+   ),
+   PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
+   PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
+0,
+IOMUX_WIDTH_4BIT,
+IOMUX_UNROUTED
+   ),
+   PIN_BANK(8, 16, "gpio8"),
+};
+#endif
+
 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 {
switch (pwm_id) {
@@ -410,7 +505,106 @@ static int rk3288_pinctrl_set_state_simple(s

[U-Boot] [PATCH v9 49/49] rockchip: jerry: Enable the Chrome OS EC

[Simon Glass]

Turn on the EC and enable the keyboard.

Signed-off-by: Simon Glass 
---

Changes in v9:
- Rebase to upstream/master

Changes in v2: None

 arch/arm/dts/rk3288-veyron-chromebook.dtsi | 4 
 configs/chromebook_jerry_defconfig | 8 
 include/configs/chromebook_jerry.h | 7 +++
 include/configs/firefly-rk3288.h   | 2 ++
 include/configs/rk3288_common.h| 7 +++
 5 files changed, 28 insertions(+)

diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi 
b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
index 6d619c9..bbbc2f4 100644
--- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
@@ -91,12 +91,16 @@
 
 &spi0 {
status = "okay";
+   spi-activate-delay = <100>;
+   spi-max-frequency = <300>;
+   spi-deactivate-delay = <200>;
 
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
spi-max-frequency = <300>;
interrupt-parent = <&gpio7>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+   ec-interrupt = <&gpio7 7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_int>;
reg = <0>;
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index ceec6f5..b2672b8 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_CHROMEBOOK_JERRY=y
 CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DM_KEYBOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
@@ -21,7 +22,13 @@ CONFIG_SPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
@@ -31,6 +38,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_RK808=y
diff --git a/include/configs/chromebook_jerry.h 
b/include/configs/chromebook_jerry.h
index 78c06af..6e32f2c 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -7,6 +7,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define ROCKCHIP_DEVICE_SETTINGS \
+   "stdin=serial,cros-ec-keyb\0" \
+   "stdout=serial\0" \
+   "stderr=serial\0"
+
 #include 
 
 #define CONFIG_ENV_IS_NOWHERE
@@ -17,4 +22,6 @@
 
 #undef CONFIG_SPL_GPIO_SUPPORT
 
+#define CONFIG_KEYBOARD
+
 #endif
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index 4c5c4dd..8ac6521 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define ROCKCHIP_DEVICE_SETTINGS
+
 #include 
 
 #define CONFIG_SPL_MMC_SUPPORT
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index f47573b..ebddfb0 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -42,6 +42,12 @@
 #define CONFIG_ROCKCHIP_COMMON
 #define CONFIG_SPL_ROCKCHIP_COMMON
 
+#define CONFIG_SILENT_CONSOLE
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_SYS_CONSOLE_IS_IN_ENV
+# define CONFIG_CONSOLE_MUX
+#endif
+
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -110,6 +116,7 @@
"fdt_high=0x1fff\0" \
"initrd_high=0x1fff\0" \
ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
 #endif
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 12/37] dm: video: Repurpose the 'displayport' uclass to 'display'

[Simon Glass]

The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.

Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.

Also update nyan-big which is affected by this.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 configs/nyan-big_defconfig   |  2 +-
 drivers/video/Kconfig| 13 +
 drivers/video/Makefile   |  2 +-
 drivers/video/display-uclass.c   | 52 
 drivers/video/dp-uclass.c| 34 ---
 drivers/video/tegra124/display.c | 18 -
 drivers/video/tegra124/dp.c  |  9 ---
 include/{displayport.h => display.h} | 33 ++-
 include/dm/uclass-id.h   |  2 +-
 include/edid.h   |  1 +
 10 files changed, 95 insertions(+), 71 deletions(-)
 create mode 100644 drivers/video/display-uclass.c
 delete mode 100644 drivers/video/dp-uclass.c
 rename include/{displayport.h => display.h} (59%)

diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 7fc1bde..03348a6 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -25,7 +25,7 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_DISPLAY_PORT=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ae122da..9ecfeae 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -293,12 +293,15 @@ config VIDEO_LCD_SPI_MISO
option takes a string in the format understood by 'name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
 
-config DISPLAY_PORT
-   bool "Enable DisplayPort support"
+config DISPLAY
+   bool "Enable Display support"
+   depends on DM
+   default y
help
-  eDP (Embedded DisplayPort) is a standard widely used in laptops
-  to drive LCD panels. This framework provides support for enabling
-  these displays where supported by the video hardware.
+  This supports drivers that provide a display, such as eDP (Embedded
+  DisplayPort) and HDMI (High Definition Multimedia Interface).
+  The devices provide a simple interface to start up the display,
+  read display information and enable it.
 
 config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6658e96..c135e22 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -6,7 +6,7 @@
 #
 
 ifdef CONFIG_DM
-obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o
+obj-$(CONFIG_DISPLAY) += display-uclass.o
 obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
 obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
 obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
new file mode 100644
index 000..31522ea
--- /dev/null
+++ b/drivers/video/display-uclass.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int display_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+
+   if (!ops || !ops->read_edid)
+   return -ENOSYS;
+   return ops->read_edid(dev, buf, buf_size);
+}
+
+int display_enable(struct udevice *dev, int panel_bpp,
+   const struct display_timing *timing)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+
+   if (!ops || !ops->enable)
+   return -ENOSYS;
+   return ops->enable(dev, panel_bpp, timing);
+}
+
+int display_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+   int panel_bits_per_colour;
+   u8 buf[EDID_EXT_SIZE];
+   int ret;
+
+   if (!ops || !ops->read_edid)
+   return -ENOSYS;
+   ret = ops->read_edid(dev, buf, sizeof(buf));
+   if (ret < 0)
+   return ret;
+
+   return edid_get_timing(buf, ret, timing, &panel_bits_per_colour);
+}
+
+UCLASS_DRIVER(display) = {
+   .id = UCLASS_DISPLAY,
+   .name   = "display",
+   .per_device_platdata_auto_alloc_size= sizeof(struct display_plat),
+};
diff --git a/drivers/video/dp-uclass.c b/drivers/video/dp-uclass.c
deleted file mode 100644
index 17f5de9..000
--- a/drivers/video/dp-uclass.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2014 Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-
-int display_port_read_edid(struct udevice *dev, u8

[U-Boot] [PATCH v2 23/37] rockchip: sdram: Use syscon_get_first_range() where possible

[Simon Glass]

This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 2a43574..074cf518 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -808,20 +808,9 @@ static int rk3288_dmc_probe(struct udevice *dev)
priv->chan[1].msch = (struct rk3288_msch *)
(regmap_get_range(map, 0) + 0x80);
 
-   map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
-   if (IS_ERR(map))
-   return PTR_ERR(map);
-   priv->grf = regmap_get_range(map, 0);
-
-   map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_SGRF);
-   if (IS_ERR(map))
-   return PTR_ERR(map);
-   priv->sgrf = regmap_get_range(map, 0);
-
-   map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_PMU);
-   if (IS_ERR(map))
-   return PTR_ERR(map);
-   priv->pmu = regmap_get_range(map, 0);
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+   priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 
ret = regmap_init_mem(dev, &map);
if (ret)
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 41/49] rockchip: clk: Make rkclk_get_clk() SoC-specific

[Simon Glass]

The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.

Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/mach-rockchip/Makefile |  1 -
 arch/arm/mach-rockchip/common.c | 28 
 drivers/clk/clk_rk3036.c| 17 +
 drivers/clk/clk_rk3288.c| 13 +
 4 files changed, 30 insertions(+), 29 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/common.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1cc4a96..55567cb 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,6 +11,5 @@ else
 obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
 endif
 obj-y += rk_timer.o
-obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c
deleted file mode 100644
index fc7ac72..000
--- a/arch/arm/mach-rockchip/common.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-void *rockchip_get_cru(void)
-{
-   struct udevice *dev;
-   fdt_addr_t addr;
-   int ret;
-
-   ret = uclass_get_device(UCLASS_CLK, 0, &dev);
-   if (ret)
-   return ERR_PTR(ret);
-
-   addr = dev_get_addr(dev);
-   if (addr == FDT_ADDR_T_NONE)
-   return ERR_PTR(-EINVAL);
-
-   return (void *)addr;
-}
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index dfecc24..bd5f22a 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -57,6 +57,23 @@ static inline unsigned int log2(unsigned int value)
return fls(value) - 1;
 }
 
+void *rockchip_get_cru(void)
+{
+   struct udevice *dev;
+   fdt_addr_t addr;
+   int ret;
+
+   ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+   if (ret)
+   return ERR_PTR(ret);
+
+   addr = dev_get_addr(dev);
+   if (addr == FDT_ADDR_T_NONE)
+   return ERR_PTR(-EINVAL);
+
+   return (void *)addr;
+}
+
 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
 const struct pll_div *div)
 {
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index d294788..5a8f175 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -159,6 +159,19 @@ int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice 
**devp)
return -ENODEV;
 }
 
+void *rockchip_get_cru(void)
+{
+   struct rk3288_clk_priv *priv;
+   struct udevice *dev;
+   int ret;
+
+   ret = rkclk_get_clk(CLK_GENERAL, &dev);
+   if (ret)
+   return ERR_PTR(ret);
+   priv = dev_get_priv(dev);
+   return priv->cru;
+}
+
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 const struct pll_div *div)
 {
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 24/49] rockchip: jerry: Enable the RK808 PMIC and regulator

[Simon Glass]

Enable this PMIC and regulator, which is used on jerry.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 configs/chromebook_jerry_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 1e5edc9..a0af6ec 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -34,8 +34,10 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
+CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_ACT8846=y
+CONFIG_REGULATOR_RK808=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 37/49] rockchip: sdram: Use the rk_clr/setreg() interface

[Simon Glass]

Use this function in preference to the macro.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 09017cc..5da04b9 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -400,7 +400,7 @@ static void set_bandwidth_ratio(const struct chan_info 
*chan, u32 channel,
 
if (n == 1) {
setbits_le32(&pctl->ppcfg, 1);
-   writel(RK_SETBITS(1 << (8 + channel)), &grf->soc_con0);
+   rk_setreg(&grf->soc_con0, 1 << (8 + channel));
setbits_le32(&msch->ddrtiming, 1 << 31);
/* Data Byte disable*/
clrbits_le32(&publ->datx8[2].dxgcr, 1);
@@ -410,7 +410,7 @@ static void set_bandwidth_ratio(const struct chan_info 
*chan, u32 channel,
setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
} else {
clrbits_le32(&pctl->ppcfg, 1);
-   writel(RK_CLRBITS(1 << (8 + channel)), &grf->soc_con0);
+   rk_clrreg(&grf->soc_con0, 1 << (8 + channel));
clrbits_le32(&msch->ddrtiming, 1 << 31);
/* Data Byte enable*/
setbits_le32(&publ->datx8[2].dxgcr, 1);
@@ -571,8 +571,7 @@ static void dram_all_config(const struct dram_info *dram,
dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
}
writel(sys_reg, &dram->pmu->sys_reg[2]);
-   writel(RK_CLRSETBITS(0x1F, sdram_params->base.stride),
-  &dram->sgrf->soc_con2);
+   rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
 
 static int sdram_init(const struct dram_info *dram,
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 33/49] dm: core: Export uclass_find_device_by_of_offset()

[Simon Glass]

It is sometimes useful to be able to find a device before probing it,
perhaps to set up some platform data for it. Allow finding by of_offset
also.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/core/uclass.c|  4 ++--
 include/dm/uclass-internal.h | 16 
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index e1acefe..12095e7 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -254,8 +254,8 @@ int uclass_find_device_by_seq(enum uclass_id id, int 
seq_or_req_seq,
return -ENODEV;
 }
 
-static int uclass_find_device_by_of_offset(enum uclass_id id, int node,
-  struct udevice **devp)
+int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+   struct udevice **devp)
 {
struct uclass *uc;
struct udevice *dev;
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
index b51e1da..ad284b8 100644
--- a/include/dm/uclass-internal.h
+++ b/include/dm/uclass-internal.h
@@ -99,6 +99,22 @@ int uclass_find_device_by_seq(enum uclass_id id, int 
seq_or_req_seq,
  bool find_req_seq, struct udevice **devp);
 
 /**
+ * uclass_find_device_by_of_offset() - Find a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if -ve then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+   struct udevice **devp);
+
+/**
  * uclass_bind_device() - Associate device with a uclass
  *
  * Connect the device into uclass's list of devices.
-- 
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[U-Boot] [PATCH v9 32/49] dm: pinctrl: Add a way for a GPIO driver to obtain a pin function

[Simon Glass]

GPIO drivers want to be able to show if a pin is enabled for input, output,
or is being used by another function. Some drivers can easily find this
and the code is included in the driver. For some SoCs this is more complex.
Conceptually this should be handled by pinctrl rather than GPIO. Most
pinctrl drivers will have this feature anyway.

Add a method by which a GPIO driver can obtain the pin mux value given a
GPIO reference. This avoids repeating the code in two places.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/pinctrl/pinctrl-uclass.c | 10 ++
 include/dm/pinctrl.h | 32 
 2 files changed, 42 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 1acbfaf..ccc5d30 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -246,6 +246,16 @@ int pinctrl_get_periph_id(struct udevice *dev, struct 
udevice *periph)
return ops->get_periph_id(dev, periph);
 }
 
+int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index)
+{
+   struct pinctrl_ops *ops = pinctrl_get_ops(dev);
+
+   if (!ops->get_gpio_mux)
+   return -ENOSYS;
+
+   return ops->get_gpio_mux(dev, banknum, index);
+}
+
 /**
  * pinconfig_post-bind() - post binding for PINCTRL uclass
  * Recursively bind child nodes as pinconfig devices in case of full pinctrl.
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index 5cd4503..0eb4b92 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -114,6 +114,22 @@ struct pinctrl_ops {
* @return peripheral ID of @periph, or -ENOENT on error
*/
int (*get_periph_id)(struct udevice *dev, struct udevice *periph);
+
+   /**
+* get_gpio_mux() - get the mux value for a particular GPIO
+*
+* This allows the raw mux value for a GPIO to be obtained. It is
+* useful for displaying the function being used by that GPIO, such
+* as with the 'gpio' command. This function is internal to the GPIO
+* subsystem and should not be used by generic code. Typically it is
+* used by a GPIO driver with knowledge of the SoC pinctrl setup.
+*
+   * @dev: Pinctrl device to use
+   * @banknum: GPIO bank number
+   * @index:   GPIO index within the bank
+   * @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+*/
+   int (*get_gpio_mux)(struct udevice *dev, int banknum, int index);
 };
 
 #define pinctrl_get_ops(dev)   ((struct pinctrl_ops *)(dev)->driver->ops)
@@ -297,4 +313,20 @@ int pinctrl_get_periph_id(struct udevice *dev, struct 
udevice *periph);
  */
 int pinctrl_decode_pin_config(const void *blob, int node);
 
+/**
+ * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO
+ *
+ * This allows the raw mux value for a GPIO to be obtained. It is
+ * useful for displaying the function being used by that GPIO, such
+ * as with the 'gpio' command. This function is internal to the GPIO
+ * subsystem and should not be used by generic code. Typically it is
+ * used by a GPIO driver with knowledge of the SoC pinctrl setup.
+ *
+ * @dev:   Pinctrl device to use
+ * @banknum:   GPIO bank number
+ * @index: GPIO index within the bank
+ * @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+*/
+int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index);
+
 #endif /* __PINCTRL_H */
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 30/49] spi: Correct device tree usage in spi_flash_decode_fdt()

[Simon Glass]

This function currently searches the entire device tree for a node that
it thinks is relevant. But the node is known and is passed in. Correct the
code and enable it only with driver model, since only driver-model boards
will use it.

This avoids bringing in a large number of strings from fdtdec.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/mtd/spi/spi_flash.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index a567414..8a60c72 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -939,14 +939,10 @@ static int set_quad_mode(struct spi_flash *flash, u8 
idcode0)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {
+#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
fdt_size_t size;
-   int node;
-
-   /* If there is no node, do nothing */
-   node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
-   if (node < 0)
-   return 0;
+   int node = flash->dev->of_offset;
 
addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
@@ -959,6 +955,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash 
*flash)
return -1;
}
flash->memory_map = map_sysmem(addr, size);
+#endif
 
return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 46/49] rockchip: spi: Implement the delays

[Simon Glass]

Some devices need delays before and after activiation. Implement these
features in the SPI driver so that we will be able to enable the Chrome
OS EC.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 27 +++
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 3418f9b..35b528f 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -32,6 +32,7 @@ struct rockchip_spi_platdata {
s32 frequency;  /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us;   /* Delay to wait after deactivate */
+   uint activate_delay_us; /* Delay to wait after activate */
 };
 
 struct rockchip_spi_priv {
@@ -101,16 +102,32 @@ static int rkspi_wait_till_not_busy(struct rockchip_spi 
*regs)
return 0;
 }
 
-static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
+static void spi_cs_activate(struct udevice *dev, uint cs)
 {
+   struct udevice *bus = dev->parent;
+   struct rockchip_spi_platdata *plat = bus->platdata;
+   struct rockchip_spi_priv *priv = dev_get_priv(bus);
+   struct rockchip_spi *regs = priv->regs;
+
debug("activate cs%u\n", cs);
writel(1 << cs, ®s->ser);
+   if (plat->activate_delay_us)
+   udelay(plat->activate_delay_us);
 }
 
-static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
+static void spi_cs_deactivate(struct udevice *dev, uint cs)
 {
+   struct udevice *bus = dev->parent;
+   struct rockchip_spi_platdata *plat = bus->platdata;
+   struct rockchip_spi_priv *priv = dev_get_priv(bus);
+   struct rockchip_spi *regs = priv->regs;
+
debug("deactivate cs%u\n", cs);
writel(0, ®s->ser);
+
+   /* Remember time of this transaction so we can honour the bus delay */
+   if (plat->deactivate_delay_us)
+   priv->last_transaction_us = timer_get_us();
 }
 
 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
@@ -145,6 +162,8 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
 5000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
+   plat->activate_delay_us = fdtdec_get_int(blob, node,
+"spi-activate-delay", 0);
debug("%s: base=%x, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
  __func__, (uint)plat->base, plat->periph_id, plat->frequency,
  plat->deactivate_delay_us);
@@ -290,7 +309,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
 
/* Assert CS before transfer */
if (flags & SPI_XFER_BEGIN)
-   spi_cs_activate(regs, slave_plat->cs);
+   spi_cs_activate(dev, slave_plat->cs);
 
while (len > 0) {
int todo = min(len, 0x);
@@ -324,7 +343,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
 
/* Deassert CS after transfer */
if (flags & SPI_XFER_END)
-   spi_cs_deactivate(regs, slave_plat->cs);
+   spi_cs_deactivate(dev, slave_plat->cs);
 
rkspi_enable_chip(regs, false);
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 30/37] rockchip: jerry: Add support for timing SPI flash speed

[Simon Glass]

Add the 'time' and 'sf test' commands so that we can test SPI flash
performance.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 include/configs/chromebook_jerry.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/chromebook_jerry.h 
b/include/configs/chromebook_jerry.h
index e07d057..2a0dad4 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -20,6 +20,9 @@
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPI_FLASH_GIGADEVICE
 
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_TIME
+
 #undef CONFIG_SPL_GPIO_SUPPORT
 
 #define CONFIG_KEYBOARD
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 34/37] rockchip: rock2: Bring in device tree files from Linux

[Simon Glass]

Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-rock2-som.dtsi   | 278 +++
 arch/arm/dts/rk3288-rock2-square.dts | 180 +++
 2 files changed, 458 insertions(+)
 create mode 100644 arch/arm/dts/rk3288-rock2-som.dtsi
 create mode 100644 arch/arm/dts/rk3288-rock2-square.dts

diff --git a/arch/arm/dts/rk3288-rock2-som.dtsi 
b/arch/arm/dts/rk3288-rock2-som.dtsi
new file mode 100644
index 000..1ece66f
--- /dev/null
+++ b/arch/arm/dts/rk3288-rock2-som.dtsi
@@ -0,0 +1,278 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include "rk3288.dtsi"
+
+/ {
+   memory {
+   reg = <0x0 0x8000>;
+   device_type = "memory";
+   };
+
+   emmc_pwrseq: emmc-pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   pinctrl-0 = <&emmc_reset>;
+   pinctrl-names = "default";
+   reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+   };
+
+   ext_gmac: external-gmac-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <12500>;
+   clock-output-names = "ext_gmac";
+   };
+
+   vcc_sys: vsys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+};
+
+&cpu0 {
+   cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+   bus-width = <8>;
+   cap-mmc-highspeed;
+   disable-wp;
+   non-removable;
+   num-slots = <1>;
+   mmc-pwrseq = <&emmc_pwrseq>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+   vmmc-supply = <&vcc_io>;
+   status = "okay";
+};
+
+&gmac {
+   assigned-clocks = <&cru SCLK_MAC>;
+   assigned-clock-parents = <&ext_gmac>;
+   clock_in_out = "input";
+   phy-mode = "rgmii";
+   phy-supply = <&vccio_pmu>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&rgmii_pins &phy_rst>;
+   snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+   snps,reset-active-low;
+   snps,reset-delays-us = <0 1 3>;
+   rx_delay = <0x10>;
+   tx_delay = <0x30>;
+};
+
+&i2c0 {
+   status = "okay";
+
+   act8846: act8846@5a {
+   compatible = "active-semi,act8846";
+   reg = <0x5a>;
+   system-power-controller;
+   inl1-supply = <&vcc_io>;
+   inl2-supply = <&vcc_sys>;
+   inl3-supply = <&vcc_20>;
+   vp1-supply = <&vcc_sys>;
+   vp2-supply = <&vcc_sys>;
+   vp3-supply = <&vcc_sys>;
+   vp4-supply = <&vcc_sys>;
+
+   regulators {
+   vcc_ddr: REG1 {
+   

[U-Boot] [PATCH v9 19/49] rockchip: spi: Update the driver to use the new clock ID

[Simon Glass]

We can use the new clk_get_by_index() function to get the correct clock.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2:
- Update call to clk_get_by_index()

 drivers/spi/rk_spi.c | 32 +---
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 242a83b..62434be 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG_RK_SPI   0
 
 struct rockchip_spi_platdata {
-   enum periph_id periph_id;
+   int periph_id;
struct udevice *pinctrl;
s32 frequency;  /* Default clock frequency, -1 for none */
fdt_addr_t base;
@@ -36,10 +36,10 @@ struct rockchip_spi_platdata {
 
 struct rockchip_spi_priv {
struct rockchip_spi *regs;
-   struct udevice *clk_gpll;
+   struct udevice *clk;
+   int clk_id;
unsigned int max_freq;
unsigned int mode;
-   enum periph_id periph_id;   /* Peripheral ID for this device */
ulong last_transaction_us;  /* Time of last transaction end */
u8 bits_per_word;   /* max 16 bits per word */
u8 n_bytes;
@@ -114,6 +114,7 @@ static void spi_cs_deactivate(struct rockchip_spi *regs, 
uint cs)
 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 {
struct rockchip_spi_platdata *plat = bus->platdata;
+   struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
int ret;
@@ -127,16 +128,23 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
if (ret < 0) {
debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
  bus->name, ret);
-   return -FDT_ERR_NOTFOUND;
+   return ret;
}
plat->periph_id = ret;
+   ret = clk_get_by_index(bus, 0, &priv->clk);
+   if (ret < 0) {
+   debug("%s: Could not get clock for %s: %d\n", __func__,
+ bus->name, ret);
+   return ret;
+   }
+   priv->clk_id = ret;
 
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-   5000);
+5000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
-   debug("%s: base=%lx, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
- __func__, plat->base, plat->periph_id, plat->frequency,
+   debug("%s: base=%x, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
+ __func__, (uint)plat->base, plat->periph_id, plat->frequency,
  plat->deactivate_delay_us);
 
return 0;
@@ -153,18 +161,12 @@ static int rockchip_spi_probe(struct udevice *bus)
 
priv->last_transaction_us = timer_get_us();
priv->max_freq = plat->frequency;
-   priv->periph_id = plat->periph_id;
-   ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk_gpll);
-   if (ret) {
-   debug("%s: Failed to find CLK_GENERAL: %d\n", __func__, ret);
-   return ret;
-   }
 
/*
 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
 * is the assumed speed for CLK_GENERAL.
 */
-   ret = clk_set_periph_rate(priv->clk_gpll, plat->periph_id, 9900);
+   ret = clk_set_periph_rate(priv->clk, priv->clk_id, 9900);
if (ret < 0) {
debug("%s: Failed to set clock: %d\n", __func__, ret);
return ret;
@@ -248,7 +250,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 
writel(ctrlr0, ®s->ctrlr0);
 
-   ret = pinctrl_request(plat->pinctrl, priv->periph_id, slave_plat->cs);
+   ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
if (ret) {
debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
return ret;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 16/37] rockchip: video: Add a display driver for rockchip eDP

[Simon Glass]

Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Update for new clk_get_by_index() API

 arch/arm/include/asm/arch-rockchip/edp_rk3288.h |  636 +
 drivers/video/rockchip/Makefile |2 +-
 drivers/video/rockchip/rk_edp.c | 1085 +++
 3 files changed, 1722 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/edp_rk3288.h
 create mode 100644 drivers/video/rockchip/rk_edp.c

diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
new file mode 100644
index 000..a9e2761
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
@@ -0,0 +1,636 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_EDP_H
+#define _ASM_ARCH_EDP_H
+
+struct rk3288_edp {
+   u8  res0[0x10];
+   u32 dp_tx_version;
+   u8  res1[0x4];
+   u32 func_en_1;
+   u32 func_en_2;
+   u32 video_ctl_1;
+   u32 video_ctl_2;
+   u32 video_ctl_3;
+   u32 video_ctl_4;
+   u8  res2[0xc];
+   u32 video_ctl_8;
+   u8  res3[0x4];
+   u32 video_ctl_10;
+   u32 total_line_l;
+   u32 total_line_h;
+   u32 active_line_l;
+   u32 active_line_h;
+   u32 v_f_porch;
+   u32 vsync;
+   u32 v_b_porch;
+   u32 total_pixel_l;
+   u32 total_pixel_h;
+   u32 active_pixel_l;
+   u32 active_pixel_h;
+   u32 h_f_porch_l;
+   u32 h_f_porch_h;
+   u32 hsync_l;
+   u32 hysnc_h;
+   u32 h_b_porch_l;
+   u32 h_b_porch_h;
+   u32 vid_status;
+   u32 total_line_sta_l;
+   u32 total_line_sta_h;
+   u32 active_line_sta_l;
+   u32 active_line_sta_h;
+   u32 v_f_porch_sta;
+   u32 vsync_sta;
+   u32 v_b_porch_sta;
+   u32 total_pixel_sta_l;
+   u32 total_pixel_sta_h;
+   u32 active_pixel_sta_l;
+   u32 active_pixel_sta_h;
+   u32 h_f_porch_sta_l;
+   u32 h_f_porch_sta_h;
+   u32 hsync_sta_l;
+   u32 hsync_sta_h;
+   u32 h_b_porch_sta_l;
+   u32 h_b_porch__sta_h;
+   u8  res4[0x28];
+   u32 pll_reg_1;
+   u8  res5[4];
+   u32 ssc_reg;
+   u8  res6[0xc];
+   u32 tx_common;
+   u32 tx_common2;
+   u8  res7[0x4];
+   u32 dp_aux;
+   u32 dp_bias;
+   u32 dp_test;
+   u32 dp_pd;
+   u32 dp_reserv1;
+   u32 dp_reserv2;
+   u8  res8[0x224];
+   u32 lane_map;
+   u8  res9[0x14];
+   u32 analog_ctl_2;
+   u8  res10[0x48];
+   u32 int_state;
+   u32 common_int_sta_1;
+   u32 common_int_sta_2;
+   u32 common_int_sta_3;
+   u32 common_int_sta_4;
+   u32 spdif_biphase_int_sta;
+   u8  res11[0x4];
+   u32 dp_int_sta;
+   u32 common_int_mask_1;
+   u32 common_int_mask_2;
+   u32 common_int_mask_3;
+   u32 common_int_mask_4;
+   u8  res12[0x08];
+   u32 int_sta_mask;
+   u32 int_ctl;
+   u8  res13[0x200];
+   u32 sys_ctl_1;
+   u32 sys_ctl_2;
+   u32 sys_ctl_3;
+   u32 sys_ctl_4;
+   u32 dp_vid_ctl;
+   u8  res14[0x4];
+   u32 dp_aud_ctl;
+   u8  res15[0x24];
+   u32 pkt_send_ctl;
+   u8  res16[0x4];
+   u32 dp_hdcp_ctl;
+   u8  res17[0x34];
+   u32 link_bw_set;
+   u32 lane_count_set;
+   u32 dp_training_ptn_set;
+   u32 ln_link_trn_ctl[4];
+   u8  res18[0x4];
+   u32 dp_hw_link_training;
+   u8  res19[0x1c];
+   u32 dp_debug_ctl;
+   u32 hpd_deglitch_l;
+   u32 hpd_deglitch_h;
+   u8  res20[0x14];
+   u32 dp_link_debug_ctl;
+   u8  res21[0x1c];
+   u32 m_vid_0;
+   u32 m_vid_1;
+   u32 m_vid_2;
+   u32 n_vid_0;
+   u32 n_vid_1;
+   u32 n_vid_2;
+   u32 m_vid_mon;
+   u8  res22[0x14];
+   u32 dp_video_fifo_thrd;
+   u8  res23[0x8];
+   u32 dp_audio_margin;
+   u8  res24[0x20];
+   u32 dp_m_cal_ctl;
+   u32 m_vid_gen_filter_th;
+   u8  res25[0x10];
+   u32 m_aud_gen_filter_th;
+   u8  res26[0x4];
+   u32 aux_ch_sta;
+   u32 aux_err_num;
+   u32 aux_ch_defer_dtl;
+   u32 aux_rx_comm;
+   u32 buf_data_ctl;
+   u32 aux_ch_ctl_1;
+   u32 aux_addr_7_0;
+   u32 aux_ad

Re: [U-Boot] [PATCH v2 1/2] tpm: Fix fault in case CONFIG_DM_TPM is set without any TPM

[Simon Glass]

On 21 January 2016 at 15:19, Christophe Ricard
 wrote:
> In case CONFIG_DM_TPM was set without any TPM chipset configured a fault
> was generated (NULL pointer access).
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  common/cmd_tpm.c | 2 +-
>  lib/tpm.c| 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v2 1/3] tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific stuff in tpm_infineon.c

[Simon Glass]

On 21 January 2016 at 15:27, Christophe Ricard
 wrote:
> I2C protocol is not standardize for TPM 1.2.
> TIS prococol is define by the Trusted Computing Group and potentially
> available on several TPMs.
>
> tpm_tis_infineon.h header is not generic enough.
>
> Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific
> defines/variables to tpm_tis_infineon.c
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} | 17 +
>  drivers/tpm/tpm_tis_infineon.c| 17 -
>  2 files changed, 17 insertions(+), 17 deletions(-)
>  rename drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} (86%)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v2 2/2] tpm: tpm_tis_lpc: fix typo

[Simon Glass]

On 21 January 2016 at 15:19, Christophe Ricard
 wrote:
> TPM_TIS_LPC is connected to the LPC bus, not I2C.
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  drivers/tpm/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v2 2/3] tpm: st33zp24: Add tpm st33zp24 support with i2c

[Simon Glass]

On 21 January 2016 at 15:27, Christophe Ricard
 wrote:
> Add support for TPM ST33ZP24 family with i2c.
>
> For i2c we are relying only on DM_I2C.
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  README |   7 +
>  drivers/tpm/Kconfig|   9 +
>  drivers/tpm/Makefile   |   1 +
>  drivers/tpm/tpm_tis_st33zp24_i2c.c | 543 
> +
>  4 files changed, 560 insertions(+)
>  create mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c

Applied to u-boot-dm, thanks!

(please enable this for your board in a subsequent patch, as this is
dead code at present)
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Re: [U-Boot] [PATCH v2 3/3] tpm: st33zp24: Add tpm st33zp24 spi support

[Simon Glass]

On 21 January 2016 at 15:27, Christophe Ricard
 wrote:
> Add support for TPM ST33ZP24 spi.
>
> The ST33ZP24 does have a spi interface.
> The transport protocol is proprietary.
>
> For spi we are relying only on DM_SPI.
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  README |   4 +
>  drivers/tpm/Kconfig|   9 +
>  drivers/tpm/Makefile   |   1 +
>  drivers/tpm/tpm_tis_st33zp24_spi.c | 672 
> +
>  4 files changed, 686 insertions(+)
>  create mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c

Applied to u-boot-dm, thanks!

(please enable this for your board in a subsequent patch, as this is
dead code at present)
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[U-Boot] [PATCH v2 28/37] rockchip: rk3288: pinctrl: Fix HDMI pinctrl

[Simon Glass]

Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 8356786..7c769bd 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -503,6 +503,8 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_I2C4;
case 65:
return PERIPH_ID_I2C5;
+   case 103:
+   return PERIPH_ID_HDMI;
}
 
return -ENOENT;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 01/37] stdio: Correct a build error with driver model

[Simon Glass]

When driver model is used for video but not for the keyboard, a compiler
warnings is produced. Fix it.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 common/stdio.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/common/stdio.c b/common/stdio.c
index 7252bab..f99cfe7 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -283,6 +283,9 @@ int stdio_add_devices(void)
 #endif
 #ifdef CONFIG_DM_VIDEO
struct udevice *vdev;
+# ifndef CONFIG_DM_KEYBOARD
+   int ret;
+# endif
 
for (ret = uclass_first_device(UCLASS_VIDEO, &vdev);
 vdev;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 09/37] dm: backlight: Add a driver for a PWM backlight

[Simon Glass]

Many backlights need to use a PWM to control the brightness. Add a driver
for this. It understands the standard device tree binding.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/Makefile|   3 +
 drivers/video/pwm_backlight.c | 134 ++
 2 files changed, 137 insertions(+)
 create mode 100644 drivers/video/pwm_backlight.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index fa90721..6d89532 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -10,6 +10,9 @@ obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o
 obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
 obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o
 obj-$(CONFIG_DM_VIDEO) += video_bmp.o
+ifdef CONFIG_DM_VIDEO
+obj-$(CONFIG_DM_PWM) += pwm_backlight.o
+endif
 obj-$(CONFIG_VIDEO_ROTATION) += console_rotate.o
 endif
 
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
new file mode 100644
index 000..de6277f
--- /dev/null
+++ b/drivers/video/pwm_backlight.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pwm_backlight_priv {
+   struct udevice *reg;
+   struct gpio_desc enable;
+   struct udevice *pwm;
+   uint channel;
+   uint period_ns;
+   uint default_level;
+   uint min_level;
+   uint max_level;
+};
+
+static int pwm_backlight_enable(struct udevice *dev)
+{
+   struct pwm_backlight_priv *priv = dev_get_priv(dev);
+   uint duty_cycle;
+   int ret;
+
+   debug("%s: Enable '%s', regulator '%s'\n", __func__, dev->name,
+ priv->reg->name);
+   ret = regulator_set_enable(priv->reg, true);
+   if (ret) {
+   debug("%s: Cannot enable regulator for PWM '%s'\n", __func__,
+ dev->name);
+   return ret;
+   }
+   mdelay(120);
+
+   duty_cycle = priv->period_ns * (priv->default_level - priv->min_level) /
+   (priv->max_level - priv->min_level + 1);
+   ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
+duty_cycle);
+   if (ret)
+   return ret;
+   ret = pwm_set_enable(priv->pwm, priv->channel, true);
+   if (ret)
+   return ret;
+   mdelay(10);
+   dm_gpio_set_value(&priv->enable, 1);
+
+   return 0;
+}
+
+static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
+{
+   struct pwm_backlight_priv *priv = dev_get_priv(dev);
+   struct fdtdec_phandle_args args;
+   const void *blob = gd->fdt_blob;
+   int node = dev->of_offset;
+   int index, ret, count, len;
+   const u32 *cell;
+
+   ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+  "power-supply", &priv->reg);
+   if (ret) {
+   debug("%s: Cannot get power supply: ret=%d\n", __func__, ret);
+   return ret;
+   }
+   ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
+  GPIOD_IS_OUT);
+   if (ret) {
+   debug("%s: Warning: cannot get enable GPIO: ret=%d\n",
+ __func__, ret);
+   if (ret != -ENOENT)
+   return ret;
+   }
+   ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
+0, 0, &args);
+   if (ret) {
+   debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
+   return ret;
+   }
+
+   ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
+   if (ret) {
+   debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
+   return ret;
+   }
+   priv->channel = args.args[0];
+   priv->period_ns = args.args[1];
+
+   index = fdtdec_get_int(blob, node, "default-brightness-level", 255);
+   cell = fdt_getprop(blob, node, "brightness-levels", &len);
+   count = len / sizeof(u32);
+   if (cell && count > index) {
+   priv->default_level = fdt32_to_cpu(cell[index]);
+   priv->max_level = fdt32_to_cpu(cell[count - 1]);
+   } else {
+   priv->default_level = index;
+   priv->max_level = 255;
+   }
+
+
+   return 0;
+}
+
+static int pwm_backlight_probe(struct udevice *dev)
+{
+   return 0;
+}
+
+static const struct backlight_ops pwm_backlight_ops = {
+   .enable = pwm_backlight_enable,
+};
+
+static const struct udevice_id pwm_backlight_ids[] = {
+   { .compatible = "pwm-backlight" },
+   { }
+};
+
+U_BOOT_DRIVER(pwm_backlight) = {
+   .name   = "pwm_backlight",
+   .id = UCLASS_PANEL_BACKLIGHT,
+   .of_match = pwm_backlight_ids,
+   .ops= &pwm_backlight_

[U-Boot] [PATCH v2 02/37] gpio: Warn about invalid GPIOs used with the 'gpio' command

[Simon Glass]

At present there is no indication that an invalid GPIO is used except that
the GPIO status is not displayed. Make the error more explicit to avoid
confusion.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 common/cmd_gpio.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c
index bb0f63a..2b78b16 100644
--- a/common/cmd_gpio.c
+++ b/common/cmd_gpio.c
@@ -174,8 +174,10 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 * GPIO compatibility layer.
 */
ret = gpio_lookup_name(str_gpio, NULL, NULL, &gpio);
-   if (ret)
+   if (ret) {
+   printf("GPIO: '%s' not found\n", str_gpio);
return cmd_process_error(cmdtp, ret);
+   }
 #else
/* turn the gpio name into a gpio number */
gpio = name_to_gpio(str_gpio);
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 36/37] rockchip: Add support for Raxda Rock 2

[Simon Glass]

This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/Makefile |  1 +
 arch/arm/mach-rockchip/rk3288-board-spl.c |  2 ++
 arch/arm/mach-rockchip/rk3288/Kconfig | 10 ++
 board/radxa/rock2/Kconfig | 15 +
 board/radxa/rock2/MAINTAINERS |  6 
 board/radxa/rock2/Makefile|  7 
 board/radxa/rock2/rock2.c |  7 
 configs/rock2_defconfig   | 53 +++
 doc/README.rockchip   |  7 +---
 include/configs/rock2.h   | 31 ++
 10 files changed, 133 insertions(+), 6 deletions(-)
 create mode 100644 board/radxa/rock2/Kconfig
 create mode 100644 board/radxa/rock2/MAINTAINERS
 create mode 100644 board/radxa/rock2/Makefile
 create mode 100644 board/radxa/rock2/rock2.c
 create mode 100644 configs/rock2_defconfig
 create mode 100644 include/configs/rock2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7706b41..641510c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -22,6 +22,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
rk3288-jerry.dtb \
+   rk3288-rock2-square.dtb \
rk3036-sdk.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 9fdd37d..6a54368 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -114,6 +114,7 @@ static void configure_l2ctlr(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
+#ifndef CONFIG_TARGET_ROCK2
struct gpio_desc desc;
int ret;
 
@@ -143,6 +144,7 @@ static int configure_emmc(struct udevice *pinctrl)
debug("gpio value ret=%d\n", ret);
return ret;
}
+#endif
 
return 0;
 }
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index ed89c3e..7215624 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,6 +16,14 @@ config TARGET_CHROMEBOOK_JERRY
  WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
  the keyboard and battery functions.
 
+config TARGET_ROCK2
+   bool "Radxa Rock 2"
+   help
+ Rock 2 is a SOM and base-board combination based on RK3288. It
+ includes Ethernet, HDMI, 3 USB, micro-SD, audio, SATA, WiFi and
+ space for a real-time-clock battery. There is also an expansion
+ interface which provides access to many pins.
+
 config ROCKCHIP_FAST_SPL
bool "Change the CPU to full speed in SPL"
depends on TARGET_CHROMEBOOK_JERRY
@@ -35,4 +43,6 @@ source "board/google/chromebook_jerry/Kconfig"
 
 source "board/firefly/firefly-rk3288/Kconfig"
 
+source "board/radxa/rock2/Kconfig"
+
 endif
diff --git a/board/radxa/rock2/Kconfig b/board/radxa/rock2/Kconfig
new file mode 100644
index 000..c2ff9e9
--- /dev/null
+++ b/board/radxa/rock2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK2
+
+config SYS_BOARD
+   default "rock2"
+
+config SYS_VENDOR
+   default "radxa"
+
+config SYS_CONFIG_NAME
+   default "rock2"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/radxa/rock2/MAINTAINERS b/board/radxa/rock2/MAINTAINERS
new file mode 100644
index 000..a697e68
--- /dev/null
+++ b/board/radxa/rock2/MAINTAINERS
@@ -0,0 +1,6 @@
+FIREFLY
+M: Simon Glass 
+S: Maintained
+F: board/radxa/rock2
+F: include/configs/rock2.h
+F: configs/rock2_defconfig
diff --git a/board/radxa/rock2/Makefile b/board/radxa/rock2/Makefile
new file mode 100644
index 000..caa305b
--- /dev/null
+++ b/board/radxa/rock2/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += rock2.o
diff --git a/board/radxa/rock2/rock2.c b/board/radxa/rock2/rock2.c
new file mode 100644
index 000..5119e95
--- /dev/null
+++ b/board/radxa/rock2/rock2.c
@@ -0,0 +1,7 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
new file mode 100644
index 000..2563775
--- /dev/null
+++ b/configs/rock2_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_ROCK2=y
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
+CONFIG_SPL_STACK_R=y
+CONFIG_SP

[U-Boot] [PATCH v9 39/49] rockchip: spi: Remember the last speed to avoid re-setting it

[Simon Glass]

Rather than changing the clock to the same value on every transaction,
remember the last value and don't adjust the clock unless it is necessary.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 2b58393..aaf139d 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -44,6 +44,7 @@ struct rockchip_spi_priv {
u8 bits_per_word;   /* max 16 bits per word */
u8 n_bytes;
unsigned int speed_hz;
+   unsigned int last_speed_hz;
unsigned int tmode;
uint input_rate;
 };
@@ -82,6 +83,7 @@ static void rkspi_set_clk(struct rockchip_spi_priv *priv, 
uint speed)
debug("spi speed %u, div %u\n", speed, clk_div);
 
writel(clk_div, &priv->regs->baudr);
+   priv->last_speed_hz = speed;
 }
 
 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
@@ -212,7 +214,8 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
return -EPROTONOSUPPORT;
}
 
-   rkspi_set_clk(priv, priv->speed_hz);
+   if (priv->speed_hz != priv->last_speed_hz)
+   rkspi_set_clk(priv, priv->speed_hz);
 
/* Operation Mode */
ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 28/49] cros_ec: Disable the Chrome OS EC in SPL

[Simon Glass]

This is not used in SPL so don't allow it to be built there, even if I2C
is enabled in SPL.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/misc/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index fc8eb6f..cd4846b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -10,11 +10,13 @@ obj-$(CONFIG_ALI152X) += ali512x.o
 obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
 obj-$(CONFIG_DS4510)  += ds4510.o
 obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
 obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
 obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
+endif
 obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_GPIO_LED) += gpio_led.o
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 26/37] rockchip: jerry: Fix the SDRAM timing

[Simon Glass]

There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3288-veyron.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index a31e00e..c201e85 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -246,7 +246,7 @@
666000 120
>;
rockchip,num-channels = <2>;
-   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 36/49] dm: clk: Add a simple version of clk_get_by_index()

[Simon Glass]

This function adds quite a bit of code to SPL and we probably don't need
all the features in SPL. Add a simple version (for SPL only) to save space.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2:
- Add an assert for clk_devp

 drivers/clk/clk-uclass.c | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 8a4c568..b483c1e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -67,8 +67,23 @@ ulong clk_set_periph_rate(struct udevice *dev, int periph, 
ulong rate)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
 {
-   struct fdtdec_phandle_args args;
int ret;
+#ifdef CONFIG_SPL_BUILD
+   u32 cell[2];
+
+   if (index != 0)
+   return -ENOSYS;
+   assert(*clk_devp);
+   ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
+   if (ret)
+   return ret;
+   ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
+  cell, 2);
+   if (ret)
+   return ret;
+   return cell[1];
+#else
+   struct fdtdec_phandle_args args;
 
assert(*clk_devp);
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
@@ -87,6 +102,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct 
udevice **clk_devp)
return ret;
}
return args.args_count > 0 ? args.args[0] : 0;
+#endif
 }
 #endif
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 29/49] dm: i2c: Allow muxes to be enabled for SPL separately

[Simon Glass]

Since I2C muxes are seldom needed in SPL, and the code for this increases
the size somewhat, add a separate option to enable I2C muxes for SPL.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/i2c/Makefile   | 4 ++--
 drivers/i2c/muxes/Kconfig  | 9 +
 drivers/i2c/muxes/Makefile | 2 +-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 811ad9b..bbbc0dc 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -7,8 +7,8 @@
 obj-$(CONFIG_DM_I2C) += i2c-uclass.o
 obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o
 obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
-obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
-obj-$(CONFIG_I2C_CROS_EC_LDO) += cros_ec_ldo.o
+obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
+obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
 
 obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 913093d..f959d9d 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -7,6 +7,15 @@ config I2C_MUX
  bus select is handled automatically when that bus is accessed,
  using a suitable I2C MUX driver.
 
+config SPL_I2C_MUX
+   bool "Support I2C multiplexers on SPL"
+   depends on I2C_MUX
+   help
+ This enables I2C buses to be multiplexed, so that you can select
+ one of several buses using some sort of control mechanism. The
+ bus select is handled automatically when that bus is accessed,
+ using a suitable I2C MUX driver.
+
 config I2C_ARB_GPIO_CHALLENGE
bool "GPIO-based I2C arbitration"
depends on I2C_MUX
diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile
index 612cc27..47c1240 100644
--- a/drivers/i2c/muxes/Makefile
+++ b/drivers/i2c/muxes/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
-obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o
+obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 23/49] rockchip: Move firefly and jerry to use the full pinctrl

[Simon Glass]

Use the full pinctrl driver in U-Boot proper.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 configs/chromebook_jerry_defconfig | 1 -
 configs/firefly-rk3288_defconfig   | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 5535105..1e5edc9 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -29,7 +29,6 @@ CONFIG_RESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 5b26a3d..7d8ca6c 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -27,7 +27,6 @@ CONFIG_RESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 17/49] rockchip: clock: Add a function to find a clock by ID

[Simon Glass]

The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/include/asm/arch-rockchip/clock.h | 12 
 drivers/clk/clk_rk3288.c   | 24 ++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h 
b/arch/arm/include/asm/arch-rockchip/clock.h
index 8a0376c..a9ea268 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -62,4 +62,16 @@ static inline u32 clk_get_divisor(ulong input_rate, uint 
output_rate)
  */
 void *rockchip_get_cru(void);
 
+/**
+ * rkclk_get_clk() - get a pointer to a given clock
+ *
+ * This is an internal function - use outside the clock subsystem indicates
+ * that work is needed!
+ *
+ * @clk_id:Clock requested
+ * @devp:  Returns a pointer to that clock
+ * @return 0 if OK, -ve on error
+ */
+int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
+
 #endif
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index df5c38c..fdc5347 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -15,7 +15,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -139,6 +141,24 @@ static const struct pll_div apll_init_cfg = 
PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
+int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
+{
+   struct udevice *dev;
+
+   for (uclass_find_first_device(UCLASS_CLK, &dev);
+dev;
+uclass_find_next_device(&dev)) {
+   struct rk3288_clk_plat *plat = dev_get_platdata(dev);
+
+   if (plat->clk_id == clk_id) {
+   *devp = dev;
+   return device_probe(dev);
+   }
+   }
+
+   return -ENODEV;
+}
+
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 const struct pll_div *div)
 {
@@ -515,7 +535,7 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, 
int periph)
ulong new_rate, gclk_rate;
int ret;
 
-   ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+   ret = rkclk_get_clk(CLK_GENERAL, &gclk);
if (ret)
return ret;
gclk_rate = clk_get_rate(gclk);
@@ -551,7 +571,7 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, 
int periph, ulong rate)
ulong new_rate, gclk_rate;
int ret;
 
-   ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+   ret = rkclk_get_clk(CLK_GENERAL, &gclk);
if (ret)
return ret;
gclk_rate = clk_get_rate(gclk);
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 27/49] gpio: Allow 's' as an abbreviation for 'status'

[Simon Glass]

The 'gpio' command allows abbreviations for most subcommands. Allow them
for 'status' also.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 common/cmd_gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c
index 65d6df4..bb0f63a 100644
--- a/common/cmd_gpio.c
+++ b/common/cmd_gpio.c
@@ -141,7 +141,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #endif
if (argc > 0)
str_gpio = *argv;
-   if (!strcmp(str_cmd, "status")) {
+   if (!strncmp(str_cmd, "status", 1)) {
/* Support deprecated gpio_status() */
 #ifdef gpio_status
gpio_status();
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 38/49] rockchip: reset: Use the rk_clr/setreg() interface

[Simon Glass]

Use this function in preference to the macro.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
index 7affd11..bf7540a 100644
--- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
@@ -22,11 +22,11 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t 
type)
return PTR_ERR(cru);
switch (type) {
case RESET_WARM:
-   writel(RK_CLRBITS(0x), &cru->cru_mode_con);
+   rk_clrreg(&cru->cru_mode_con, 0x);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
case RESET_COLD:
-   writel(RK_CLRBITS(0x), &cru->cru_mode_con);
+   rk_clrreg(&cru->cru_mode_con, 0x);
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
-- 
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[U-Boot] [PATCH v9 45/49] rockchip: gpio: Implement the get_function() method

[Simon Glass]

Provide this method so that 'gpio status' works fully. It now shows
whether a pin is used for input, output or some other function.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/gpio/rk_gpio.c | 40 
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index a22e219..c62f025 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -8,11 +8,16 @@
  */
 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
+#include 
 
 enum {
ROCKCHIP_GPIOS_PER_BANK = 32,
@@ -22,6 +27,8 @@ enum {
 
 struct rockchip_gpio_priv {
struct rockchip_gpio_regs *regs;
+   struct udevice *pinctrl;
+   int bank;
char name[2];
 };
 
@@ -70,7 +77,25 @@ static int rockchip_gpio_set_value(struct udevice *dev, 
unsigned offset,
 
 static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
 {
-   return -ENOSYS;
+#ifdef CONFIG_SPL_BUILD
+   return -ENODATA;
+#else
+   struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+   struct rockchip_gpio_regs *regs = priv->regs;
+   bool is_output;
+   int ret;
+
+   ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
+   if (ret)
+   return ret;
+
+   /* If it's not 0, then it is not a GPIO */
+   if (ret)
+   return GPIOF_FUNC;
+   is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
+
+   return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
+#endif
 }
 
 static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
@@ -87,13 +112,20 @@ static int rockchip_gpio_probe(struct udevice *dev)
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
char *end;
-   int bank;
+   int ret;
 
+   /* This only supports RK3288 at present */
priv->regs = (struct rockchip_gpio_regs *)dev_get_addr(dev);
+   ret = uclass_first_device(UCLASS_PINCTRL, &priv->pinctrl);
+   if (ret)
+   return ret;
+   if (!priv->pinctrl)
+   return -ENODEV;
+
uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
end = strrchr(dev->name, '@');
-   bank = trailing_strtoln(dev->name, end);
-   priv->name[0] = 'A' + bank;
+   priv->bank = trailing_strtoln(dev->name, end);
+   priv->name[0] = 'A' + priv->bank;
uc_priv->bank_name = priv->name;
 
return 0;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 47/49] rockchip: spi: Correct chip-enable code

[Simon Glass]

At present there is an incorrect call to rkspi_enable_chip(). It should
be disabling the chip, not enabling it. Correct this and ensure that the
chip is disabled when releasing the bus.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 35b528f..412fa8b 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -286,6 +286,11 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 
 static int rockchip_spi_release_bus(struct udevice *dev)
 {
+   struct udevice *bus = dev->parent;
+   struct rockchip_spi_priv *priv = dev_get_priv(bus);
+
+   rkspi_enable_chip(priv->regs, false);
+
return 0;
 }
 
@@ -314,7 +319,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
while (len > 0) {
int todo = min(len, 0x);
 
-   rkspi_enable_chip(regs, true);
+   rkspi_enable_chip(regs, false);
writel(todo - 1, ®s->ctrlr1);
rkspi_enable_chip(regs, true);
 
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH v5 1/6] ARM: bootm: Try to use relocated ramdisk

[Simon Glass]

On 13 January 2016 at 19:19, Jeffy Chen  wrote:
> After boot_ramdisk_high(), ramdisk would be relocated to
> initrd_start & initrd_end, so use them instead of rd_start & rd_end.
>
> Signed-off-by: Jeffy Chen 
> Acked-by: Simon Glass 
> Reviewed-by: Tom Rini 
>
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> Add comments.
>
>  arch/arm/lib/bootm.c | 12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v5 6/6] rockchip: kylin: Store env in emmc

[Simon Glass]

On 14 January 2016 at 10:17, Simon Glass  wrote:
> On 13 January 2016 at 19:19, Jeffy Chen  wrote:
>> There's a 64K reserved area at the end of the first 4M.
>> Store env there, so we can use fastboot to flash it.
>>
>> Signed-off-by: Jeffy Chen 
>>
>> ---
>>
>> Changes in v5:
>> New patch.
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>>  include/configs/kylin_rk3036.h | 12 
>>  1 file changed, 12 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v5 5/6] rockchip: kylin: Check fastboot request

[Simon Glass]

On 14 January 2016 at 10:17, Simon Glass  wrote:
> On 13 January 2016 at 19:19, Jeffy Chen  wrote:
>> We will save boot mode flag in grf's os_reg[4], if fastboot
>> requested or fastboot key pressed, try to enter fastboot mode
>> at preboot stage.
>>
>> Signed-off-by: Jeffy Chen 
>>
>> ---
>>
>> Changes in v5:
>> Change "grf" to local var.
>>
>> Changes in v4:
>> Remove unused reboot mode definitions.
>>
>> Changes in v3:
>> Use rockchip's legacy reboot mode definitions.
>>
>> Changes in v2: None
>>
>>  board/kylin/kylin_rk3036/kylin_rk3036.c | 32 
>> 
>>  include/configs/kylin_rk3036.h  |  3 +++
>>  2 files changed, 35 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v5 2/6] rockchip: rk3036: Bind GPIO banks

[Simon Glass]

On 13 January 2016 at 19:19, Jeffy Chen  wrote:
> Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding.
>
> Signed-off-by: Jeffy Chen 
> Acked-by: Simon Glass 
> Reviewed-by: Tom Rini 
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  drivers/pinctrl/rockchip/pinctrl_rk3036.c | 8 
>  1 file changed, 8 insertions(+)

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v4 5/6] rockchip: kylin: Enable boot with android boot image

[Simon Glass]

Hi,

On 15 January 2016 at 18:18, Simon Glass  wrote:
> Hi,
>
> On 15 January 2016 at 08:42, Daniel Schwierzeck
>  wrote:
>> Am Freitag, den 15.01.2016, 09:42 -0500 schrieb Tom Rini:
>>> On Fri, Jan 15, 2016 at 10:20:43AM +0800, Jeffy Chen wrote:
>>> > Hi Tom,
>>> >
>>> > On 2016-1-15 8:59, Tom Rini wrote:
>>> > > On Fri, Jan 15, 2016 at 08:53:06AM +0800, Jeffy Chen wrote:
>>> > > > Hi Tom,
>>> > > >
>>> > > > On 2016-1-15 0:22, Tom Rini wrote:
>>> > > > > On Thu, Jan 14, 2016 at 10:31:34AM +0800, Jeffy Chen wrote:
>>> > > > > > Hi Tom,
>>> > > > > >
>>> > > > > > On 2016-1-13 23:28, Tom Rini wrote:
>>> > > > > > > On Wed, Jan 13, 2016 at 04:53:19PM +0800, Jeffy Chen
>>> > > > > > > wrote:
>>> > > > > > >
>>> > > > > > > > The android kernel is using appended dtb by default,
>>> > > > > > > > and store
>>> > > > > > > > ramdisk right after kernel & dtb.
>>> > > > > > > > So we needs to relocate ramdisk, and use atags to pass
>>> > > > > > > > params.
>>> > > > > > > >
>>> > > > > > > > Signed-off-by: Jeffy Chen 
>>> > > > > > > > Acked-by: Simon Glass 
>>> > > > > > > > ---
>>> > > > > > > >
>>> > > > > > > > Changes in v4: None
>>> > > > > > > > Changes in v3: None
>>> > > > > > > > Changes in v2: None
>>> > > > > > > >
>>> > > > > > > >  include/configs/kylin_rk3036.h | 23
>>> > > > > > > > +++
>>> > > > > > > >  1 file changed, 23 insertions(+)
>>> > > > > > > >
>>> > > > > > > > diff --git a/include/configs/kylin_rk3036.h
>>> > > > > > > > b/include/configs/kylin_rk3036.h
>>> > > > > > > > index b750b26..49997ec 100644
>>> > > > > > > > --- a/include/configs/kylin_rk3036.h
>>> > > > > > > > +++ b/include/configs/kylin_rk3036.h
>>> > > > > > > > @@ -35,6 +35,29 @@
>>> > > > > > > >  #undef CONFIG_EXTRA_ENV_SETTINGS
>>> > > > > > > >  #define CONFIG_EXTRA_ENV_SETTINGS \
>>> > > > > > > > "partitions=" PARTS_DEFAULT \
>>> > > > > > > > +   "mmcdev=0\0" \
>>> > > > > > > > +   "mmcpart=5\0" \
>>> > > > > > > > +   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)
>>> > > > > > > > "\0" \
>>> > > > > > > > +
>>> > > > > > > > +#define CONFIG_ANDROID_BOOT_IMAGE
>>> > > > > > > > +#define CONFIG_SYS_BOOT_RAMDISK_HIGH
>>> > > > > > > This should already be set.
>>> > > > > > Right, i'll remove it...
>>> > > > > > > > +#define CONFIG_SYS_HUSH_PARSER
>>> > > > > > > > +
>>> > > > > > > > +#undef CONFIG_BOOTCOMMAND
>>> > > > > > > > +#define CONFIG_BOOTCOMMAND \
>>> > > > > > > > +   "mmc dev ${mmcdev}; if mmc rescan; then " \
>>> > > > > > > > +   "part start mmc ${mmcdev} ${mmcpart}
>>> > > > > > > > boot_start;" \
>>> > > > > > > > +   "part size mmc ${mmcdev} ${mmcpart}
>>> > > > > > > > boot_size;" \
>>> > > > > > > > +   "mmc read ${loadaddr} ${boot_start}
>>> > > > > > > > ${boot_size};" \
>>> > > > > > > > +   "bootm start ${loadaddr}; bootm
>>> > > > > > > > ramdisk;" \
>>> > > > > > > > +   "bootm prep; bootm go;" \
>>> > > > > > > > +   "fi;" \
>>> > > > > > > > +
>>> > > > > > > > +/* Enable atags */
>>> > > > > > > > +#define CONFIG_SYS_BOOTPARAMS_LEN  (64*1024)
>>> > > > > > > > +#define CONFIG_INITRD_TAG
>>> > > > > > > > +#define CONFIG_SETUP_MEMORY_TAGS
>>> > > > > > > > +#define CONFIG_CMDLINE_TAG
>>> > > > > > > But I'm confused as to what exactly is going on here.
>>> > > > > > >  Appended dtb is
>>> > > > > > > not the same as ATAGS.  And you shouldn't need to split
>>> > > > > > > up bootm like
>>> > > > > > > that.  Can you please explain a bit more?  Thanks!
>>> > > > > > The u-boot will pass atags to kernel, and kernel will merge
>>> > > > > > those
>>> > > > > > atags into the appended dtb(fdt).
>>> > > > > >
>>> > > > > > The default bootm flow would not pass ramdisk state, but we
>>> > > > > > need it,
>>> > > > > > so we should add this state into default flow, or just use
>>> > > > > > split
>>> > > > > > bootm cmds :)
>>> > > > > That seems very strange.  Is the ramdisk concatenated with
>>> > > > > the kernel
>>> > > > > and dtb as well (and that's why bootm ramdisk somehow finds
>>> > > > > it but
>>> > > > > normal bootm doesn't as you aren't passing in a ramdisk
>>> > > > > address) ?
>>> > > > Yes, the ramdisk concatenated with the kernel and dtb as
>>> > > > well(u-boot/include/android_image.h: struct andr_img_hdr).
>>> > > >
>>> > > > And the normal bootm cmd would find it by parsing andr_img_hdr
>>> > > > struct.
>>> > > > But we still need bootm ramdisk state, because it will call
>>> > > > boot_ramdisk_high to relocate ramdisk area :)
>>> > > >
>>> > > > I found if not relocate it to somewhere else, it would be
>>> > > > corrupted
>>> > > > after kernel's decompressing(during update fdt area).
>>> > > So 'bootm $loadaddr' of an Android image sees, but does not
>>> > > relocate the
>>> > > ramdisk that is included in the image, but bootm ramdisk does?
>>> > >  That
>>> > > sounds like a bug in the regular bootm handling.
>>> > Yep, the default bootm flow would not con

Re: [U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model

[Simon Glass]

Hi,

On 12 January 2016 at 02:30, Bhuvanchandra DV
 wrote:
> Hi Bin,
>
>
> On 01/12/2016 12:21 PM, Bin Meng wrote:
>>
>> Hi Bhuvanchandra,
>>
>> On Tue, Jan 12, 2016 at 2:43 PM, Bhuvanchandra DV
>>  wrote:
>>>
>>> Hi Bin,
>>>
>>>
>>> On 01/12/2016 11:05 AM, Bin Meng wrote:


 Hi Bhuvanchandra,

 On Tue, Jan 12, 2016 at 12:28 PM, Bhuvanchandra DV
  wrote:
>
>
> - Convert lpuart driver to driver model and remove the legacy code.
> - Update Toradex Colibri VF50/VF61 serial support with driver model.
> - Update Freescale vf610twr serial support with driver model.
> - Update Freescale ls1021atwr serial support with driver model.
> - Update Phytec pcm052 serial support with driver model.
> - Tested the driver on Toradex Colibri VF50/VF61 hardware.
> - Compile checked board files for vf610twr, ls1021atwr and pcm052
> since I don't have access to such hardware at my end. Reviewers
> and testers welcome!
>
> Bhuvanchandra DV (8):
> dm: lpuart: Add driver model support for the serial driver
> colibri_vf: Update enabling lpuart support with driver model
> arm: vf610twr: Add driver model support
> vf610twr: Update enabling lpuart with driver model
> arm: ls102xa: Add driver model support
> ls1021x: Update enabling lpuart with driver model
> arm: pcm052: Enable driver model support
> pcm052: Update enabling lpuart support with driver model
>
>arch/arm/include/asm/arch-ls102xa/serial.h |  16 
>arch/arm/include/asm/arch-vf610/serial.h   |  16 
>board/freescale/ls1021atwr/ls1021atwr.c|  15 ++-
>board/freescale/vf610twr/vf610twr.c|  13 +++
>board/phytec/pcm052/pcm052.c   |  13 +++
>board/toradex/colibri_vf/colibri_vf.c  |  13 +++
>configs/ls1021atwr_nor_lpuart_defconfig|   1 +
>configs/pcm052_defconfig   |   1 +
>configs/vf610twr_defconfig |   1 +
>configs/vf610twr_nand_defconfig|   1 +
>drivers/serial/Kconfig |   6 ++
>drivers/serial/serial_lpuart.c | 148
> +++--
>include/configs/colibri_vf.h   |   6 +-
>include/configs/ls1021atwr.h   |   1 +
>include/configs/pcm052.h   |   6 +-
>include/configs/vf610twr.h |   6 +-
>16 files changed, 180 insertions(+), 83 deletions(-)
>create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h
>create mode 100644 arch/arm/include/asm/arch-vf610/serial.h
>
> --



 Please see existing patch series @
 http://patchwork.ozlabs.org/patch/561855/. You can drop the ls102xa
 changes and rebase your patch series on top of that. Thanks!
>>>
>>>
>>>
>>> We are not aware of this patch set, sorry! about that. You want me to
>>> drop
>>> only the ls102xa changes? How about the changes/updates to the lpuart
>>> driver? should i update them with your device tree support stuff and
>>> rebase
>>> the remaining patch set along with your Signed-off-by tag ?
>>> Any suggestions ?
>>>
>>
>> I believe you can:
>> - Drop the LPUART DM conversion patch in your series, which was already
>> done
>
>
> I believe that the patch set[1] is now _only_ supporting device tree enabled
> boards, there are boards using lpuart which are not yet having device trees,
> boards like vf610twr and Phytec pcm052. Even with driver model enabled i
> guess these boards canont use lpuart via platform data with this patch set.
> I think it would be nice to have the support for both platform data and
> device tree so that we can use it with platform data via board files and
> device tree too.
>
> Since only few boards are using lpuart driver we can update the driver
> completly to driver model, drop the legacy code and update the boards.
>
> Seems the legacy code in lpuart driver is broken:
> drivers/serial/serial_lpuart.c:148:9: error: too few arguments to function
> '_lpuart_serial_tstc'
>
> I will test the patch set[1] atleast on Toradex Colibri VF50/VF61 h/w and
> will provide a detailed report of my observations.
>
>
> [1] http://patchwork.ozlabs.org/patch/561855/
>
>> - Drop the ls1021atwr changes, which was already done
>> - Do the similar changes to all other boards in your series, by
>> following ls1021atwr changes in my series
>> - There is no need to add my SOB tag in your series as I was actually
>> not doing anything :)

Please go ahead and post any new patches that are required here now
that Bin's series has landed.

Regards,
Simon
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Re: [U-Boot] [PATCH v5 3/6] rockchip: kylin: Add default gpt partition table

[Simon Glass]

On 13 January 2016 at 19:19, Jeffy Chen  wrote:
> Add default android gpt partition table for kylin board.
>
> Use "gpt write mmc 0 $partitions" to apply.
>
> Signed-off-by: Jeffy Chen 
> Acked-by: Simon Glass 
> Reviewed-by: Tom Rini 
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  include/configs/kylin_rk3036.h | 29 +
>  1 file changed, 29 insertions(+)

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [Patch V5 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue

[Qianyu Gong]

> -Original Message-
> From: Scott Wood
> Sent: Friday, January 22, 2016 3:30 AM
> To: Qianyu Gong ; u-boot@lists.denx.de;
> r58...@freescale.com
> Cc: mingkai...@freescale.com; jt...@openedev.com; b48...@freescale.com;
> shaohui@freescale.com; wenbin.s...@freescale.com; Scott Wood
> ; Gong Qianyu 
> Subject: Re: [Patch V5 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue
> 
> On 01/20/2016 09:43 PM, Gong Qianyu wrote:
> > From: Gong Qianyu 
> >
> > In current driver everytime we memcpy 4 bytes to the dest memory
> > regardless of the remaining length.
> > This patch adds checking the remaining length before memcpy.
> > If the length is shorter than 4 bytes, memcpy the actual length of
> > data to the dest memory.
> >
> > Signed-off-by: Gong Qianyu 
> > ---
> > V2-V5:
> >  - No change.
> >
> >  drivers/spi/fsl_qspi.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 38e5900..f178857 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -500,7 +500,10 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, 
> > u32
> *rxbuf, u32 len)
> > if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
> > data = qspi_read32(priv->flags, ®s->rbdr[i]);
> > data = qspi_endian_xchg(data);
> > -   memcpy(rxbuf, &data, 4);
> > +   if (size < 4)
> > +   memcpy(rxbuf, &data, size);
> > +   else
> > +   memcpy(rxbuf, &data, 4);
> 
> memcpy(rxbuf, &data, min(size, 4));
> 
> > rxbuf++;
> > size -= 4;
> > i++;
> 
> size -= 4 even if size was < 4?
> 
> -Scott

Yes.. The following is complete code:

i = 0;
size = len;
while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
rbsr_reg = qspi_read32(priv->flags, ®s->rbsr);
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
data = qspi_endian_xchg(data);
memcpy(rxbuf, &data, min(size, 4));
rxbuf++;
size -= 4;
i++;
}
}


Regards,
Qianyu
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Re: [U-Boot] [PATCH 1/8] test/py: fix timeout to be absolute

[Simon Glass]

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Currently, Spawn.expect() imposes its timeout solely upon receipt of new
> data, not on its overall operation. In theory, this could cause the
> timeout not to fire if U-Boot continually generated output that did not
> match the expected patterns.
>
> Fix the code to additionally impose a timeout on overall operation, which
> is the intended mode of operation.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/u_boot_spawn.py | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 2/8] test/py: move U-Boot respawn trigger to the test core

[Simon Glass]

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Prior to this change, U-Boot was lazilly (re-)spawned if/when a test
> attempted to interact with it, and no active connection existed. This
> approach was simple, yet had the disadvantage that U-Boot might be
> spawned in the middle of a test function, e.g. after the test had already
> performed actions such as creating data files, etc. In that case, this
> could cause the log to contain the sequence (1) some test logs, (2)
> U-Boot's boot process, (3) the rest of that test's logs. This isn't
> optimally readable. This issue will affect the upcoming DFU and enhanced
> UMS tests.
>
> This change converts u_boot_console to be a function-scoped fixture, so
> that pytest attempts to re-create the object for each test invocation.
> This allows the fixture factory function to ensure that U-Boot is spawned
> prior to every test. In practice, the same object is returned each time
> so there is essentially no additional overhead due to this change.
>
> This allows us to remove:
>
> - The explicit ensure_spawned() call from test_sleep, since the core now
> ensures that the spawn happens before the test code is executed.
>
> - The laxy calls to ensure_spawned() in the u_boot_console_*
> implementations.
>
> The one downside is that test_env's "state_ttest_env" fixture must be
> converted to a function-scoped fixture too, since a module-scoped fixture
> cannot use a function-scoped fixture. To avoid overhead, we use the same
> trick of returning the same object each time.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/conftest.py| 3 ++-
>  test/py/tests/test_env.py  | 8 ++--
>  test/py/tests/test_sandbox_exit.py | 2 --
>  test/py/tests/test_sleep.py| 4 
>  test/py/u_boot_console_base.py | 2 --
>  test/py/u_boot_console_sandbox.py  | 1 -
>  6 files changed, 8 insertions(+), 12 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 5/8] test/py: optionally ignore errors from shell commands

[Simon Glass]

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Sometimes it's useful to run shell commands and ignore any errors. One
> example might be cleanup logic; if a test-case experiences an error, the
> cleanup logic might experience an error too, and we don't want that error
> to mask the original error, so we want to ignore the subsequent error.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/multiplexed_log.py | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/8] test/py: drain console log at the end of any failed test

[Simon Glass]

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Tests may fail for a number of reasons, and in particular for reasons
> other than a timeout waiting for U-Boot to print expected data. If the
> last operation that a failed test performs is not waiting for U-Boot to
> print something, then any trailing output from U-Boot during that test's
> operation will not be logged as part of that test, but rather either
> along with the next test, or even thrown away, potentiall hiding clues
> re: the test failure reason.
>
> Solve this by explicitly draining (and hence logging) the U-Boot output
> in the case of failed tests.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/conftest.py|  1 +
>  test/py/u_boot_console_base.py | 38 ++
>  2 files changed, 39 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/2] test/py: move find_ram_base() into u_boot_utils

[Simon Glass]

On 21 January 2016 at 16:05, Stephen Warren  wrote:
> From: Stephen Warren 
>
> find_ram_base() is a shared utility function, not a core part of the
> U-Boot console interaction.
>
> Signed-off-by: Stephen Warren 
> ---
> These two patches depend on my previous series starting with:
> test/py: fix timeout to be absolute
> and ending with:
> test/py: add DFU test
> ---
>  test/py/tests/test_md.py   |  5 +++--
>  test/py/u_boot_console_base.py | 37 -
>  test/py/u_boot_utils.py| 38 ++
>  3 files changed, 41 insertions(+), 39 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 4/8] test/py: log when tests send CTRL-C

[Simon Glass]

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Write a note to the log file when a test sends CTRL-C to U-Boot. This
> makes it easier to follow what's happening in the logs, especially since
> U-Boot doesn't echo the character back to its output, so there's no other
> signal of what's going on.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/u_boot_console_base.py | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 8/8] test/py: add DFU test

[Simon Glass]

On 21 January 2016 at 11:17, Stephen Warren  wrote:
> On 01/21/2016 03:50 AM, Lukasz Majewski wrote:
>>
>> Hi Stephen,
>>
>>> From: Stephen Warren 
>>>
>>> Add a test of DFU functionality to the Python test suite. The test
>>> starts DFU in U-Boot, waits for USB device enumeration on the host,
>>> executes dfu-util multiple times to test various transfer sizes, many
>>> of which trigger USB driver edge cases, and finally aborts the DFU
>>> command in U-Boot.
>>>
>>> This test mirrors the functionality previously available via the shell
>>> scripts in test/dfu, and hence those are removed too.
>
> ...
>>
>> Acked-by: Lukasz Majewski 
>>
>> Great work Stephen, Thanks !
>
>
> Thanks for the review. I'm glad you're OK with the patch, given it deletes
> your previous script.
>
> I'll hold off on posting v2 (for the comment fix) for a few days in case
> there are other comments.

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 2/2] test/py: add a networking test

[Simon Glass]

On 21 January 2016 at 16:05, Stephen Warren  wrote:
> From: Stephen Warren 
>
> This tests:
> - dhcp (if indicated by boardenv file).
> - Static IP network setup (if provided by boardenv file).
> - Ping.
> - TFTP get.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/tests/test_net.py | 153 
> ++
>  1 file changed, 153 insertions(+)
>  create mode 100644 test/py/tests/test_net.py

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 7/8] test/py: ums: add filesystem-based testing

[Simon Glass]

On 21 January 2016 at 04:26, Lukasz Majewski  wrote:
> Hi Stephen,
>
>> From: Stephen Warren 
>>
>> Enhance the UMS test to optionally mount a partition and read/write a
>> file to it, validating that the content written and read back are
>> identical.
>>
>> This enhancement is backwards-compatible; old boardenv contents that
>> don't define the new configuration data will cause the test code to
>> perform as before.
>>
>> test/ums/ is deleted since the Python test now performs the same
>> testing that it did.
>>
>> The code is also re-written to make use of the recently added utility
>> module, and split it up into nested functions so the overall logic of
>> the test process can be followed more easily without the details
>> cluttering the code.
>>
>> Cc: Lukasz Majewski 
>> Signed-off-by: Stephen Warren 
>> ---
>>  test/py/tests/test_ums.py   | 212
>> +++-
>> test/ums/README |  30 --- test/ums/ums_gadget_test.sh
>> | 183 -- 3 files changed, 169
>> insertions(+), 256 deletions(-) delete mode 100644 test/ums/README
>>  delete mode 100755 test/ums/ums_gadget_test.sh
>>

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

[Simon Glass]

Hi,

On 21 January 2016 at 18:39, Bin Meng  wrote:
> Hi Stephen,
>
> On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  wrote:
>> From: Stephen Warren 
>>
>> PCI controllers should be enumerated at startup so that PCI devices
>> such as Ethernet controllers are available at startup. Fix board_init_r()
>> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
>> an implementation of pci_init() for the DM case.
>>
>
> What exact issue are you trying to fix? I posted the same question on
> Simon's patch [1] before. Does your patch and Simon's fix the same
> issue?
>
> Note I submitted a similar patch [2] last year for x86 only, to
> explicitly trigger the PCI enueration. But it was not accepted.
>
>> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
>> for Ethernet")
>> Signed-off-by: Stephen Warren 
>> ---
>> I'm not sure if relying on the side-effects of calling
>> uclass_{first,ext}_device is the correct approach; is there a more explicit
>> way to probe all PCI controllers?
>>
>> Arguably, perhaps we should introduce a "pci start" command instead of
>> this change to be consistent with e.g. USB. However, that would be a
>> regression relative to earlier versions of U-Boot.
>> ---
>
> [1] http://patchwork.ozlabs.org/patch/569323/
> [2] http://patchwork.ozlabs.org/patch/500246/
>
> Regards,
> Bin

This does go against the driver-model philosophy of lazy init. I
wonder if we should add this patch with a Kconfig option to enable it?
Then it can be enabled only for boards that need it.

Regards
Simon
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Re: [U-Boot] [PATCH 6/8] test/py: add various utility code

[Simon Glass]

Hi Stephen,

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Add various common utility functions. These will be used by a forthcoming
> re-written UMS test, and a brand-new DFU test.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/u_boot_console_base.py |  19 +
>  test/py/u_boot_utils.py| 171 
> +
>  2 files changed, 190 insertions(+)
>  create mode 100644 test/py/u_boot_utils.py

Acked-by: Simon Glass 

>
> diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
> index 433bec6e9fdd..06f61f987180 100644
> --- a/test/py/u_boot_console_base.py
> +++ b/test/py/u_boot_console_base.py
> @@ -215,6 +215,25 @@ class ConsoleBase(object):
>  self.log.action('Sending Ctrl-C')
>  self.run_command(chr(3), wait_for_echo=False, send_nl=False)
>
> +def wait_for(self, text):
> +'''Wait for a pattern to be emitted by U-Boot.

I meant to say we should use """ for function comments to keep it
consistent with the rest of U-Boot. Maybe could adjust this in a
follow-on patch?

> +
> +This is useful when a long-running command such as "dfu" is 
> executing,
> +and it periodically emits some text that should show up at a specific
> +location in the log file.
> +
> +Args:
> +text: The text to wait for; either a string (containing raw text,
> +not a regular expression) or an re object.
> +
> +Returns:
> +Nothing.
> +'''
> +
> +if type(text) == type(''):
> +text = re.escape(text)
> +self.p.expect([text])

Does this potentially wait forever?

> +
>  def drain_console(self):
>  '''Read from and log the U-Boot console for a short time.
>
> diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
> new file mode 100644
> index ..539af618dbf2
> --- /dev/null
> +++ b/test/py/u_boot_utils.py
> @@ -0,0 +1,171 @@
> +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
> +#
> +# SPDX-License-Identifier: GPL-2.0
> +
> +# Utility code shared across multiple tests.
> +
> +import hashlib
> +import os
> +import os.path
> +import sys
> +import time
> +
> +def md5sum_data(data):
> +'''Calculate the MD5 hash of some data.
> +
> +Args:
> +data: The data to hash.
> +
> +Returns:
> +The hash of the data, as a binary string.
> +'''
> +
> +h = hashlib.md5()
> +h.update(data)
> +return h.digest()

Or just:

   return hashlib.md5().update(data).digest()

Regards,
Simon
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

[Bin Meng]

On Fri, Jan 22, 2016 at 11:36 AM, Simon Glass  wrote:
> Hi,
>
> On 21 January 2016 at 18:39, Bin Meng  wrote:
>> Hi Stephen,
>>
>> On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  
>> wrote:
>>> From: Stephen Warren 
>>>
>>> PCI controllers should be enumerated at startup so that PCI devices
>>> such as Ethernet controllers are available at startup. Fix board_init_r()
>>> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
>>> an implementation of pci_init() for the DM case.
>>>
>>
>> What exact issue are you trying to fix? I posted the same question on
>> Simon's patch [1] before. Does your patch and Simon's fix the same
>> issue?
>>
>> Note I submitted a similar patch [2] last year for x86 only, to
>> explicitly trigger the PCI enueration. But it was not accepted.
>>
>>> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
>>> for Ethernet")
>>> Signed-off-by: Stephen Warren 
>>> ---
>>> I'm not sure if relying on the side-effects of calling
>>> uclass_{first,ext}_device is the correct approach; is there a more explicit
>>> way to probe all PCI controllers?
>>>
>>> Arguably, perhaps we should introduce a "pci start" command instead of
>>> this change to be consistent with e.g. USB. However, that would be a
>>> regression relative to earlier versions of U-Boot.
>>> ---
>>
>> [1] http://patchwork.ozlabs.org/patch/569323/
>> [2] http://patchwork.ozlabs.org/patch/500246/
>>
>> Regards,
>> Bin
>
> This does go against the driver-model philosophy of lazy init. I
> wonder if we should add this patch with a Kconfig option to enable it?
> Then it can be enabled only for boards that need it.
>

I suspect the issue is somewhere else. On Intel Galileo with a PCI
ethernet, it works fine without such explicit pci init. Which PCI
ethernet driver does not work on Tegra?

Regards,
Bin
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[U-Boot] CONFIG_EXTRA_ENV_SETTINGS and Kconfig

[Oleg K Dzhimiev]

Hello,

A couple years ago we developed Ezynq  to
build the bootloader for our camera board (w/o using Vivado's SDK).
The config files are *.h and now we would like update the project to
Kconfig.

There is the CONFIG_EXTRA_ENV_SETTINGS parameter:
include/configs/.h:

> #define CONFIG_EXTRA_ENV_SETTINGS = /*many lines*/

used in:
include/env_default.h

Are there any tips on how to deal with it?

U-boot revision, git log:

> commit fa85e826c16b9ce1ad302a57e9c4b24db0d8b930
> Author: Tom Rini 
> Date:   Tue Jan 12 09:06:54 2016 -0500
> Prepare v2016.01
>
> Signed-off-by: Tom Rini 


Thanks

Best regards,
Oleg Dzhimiev
Electronics Engineer
phone: +1 801 783  x124
Elphel, Inc.
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

[Simon Glass]

Hi Bin,

On 21 January 2016 at 20:53, Bin Meng  wrote:
> On Fri, Jan 22, 2016 at 11:36 AM, Simon Glass  wrote:
>> Hi,
>>
>> On 21 January 2016 at 18:39, Bin Meng  wrote:
>>> Hi Stephen,
>>>
>>> On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  
>>> wrote:
 From: Stephen Warren 

 PCI controllers should be enumerated at startup so that PCI devices
 such as Ethernet controllers are available at startup. Fix board_init_r()
 not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
 an implementation of pci_init() for the DM case.

>>>
>>> What exact issue are you trying to fix? I posted the same question on
>>> Simon's patch [1] before. Does your patch and Simon's fix the same
>>> issue?
>>>
>>> Note I submitted a similar patch [2] last year for x86 only, to
>>> explicitly trigger the PCI enueration. But it was not accepted.
>>>
 Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
 for Ethernet")
 Signed-off-by: Stephen Warren 
 ---
 I'm not sure if relying on the side-effects of calling
 uclass_{first,ext}_device is the correct approach; is there a more explicit
 way to probe all PCI controllers?

 Arguably, perhaps we should introduce a "pci start" command instead of
 this change to be consistent with e.g. USB. However, that would be a
 regression relative to earlier versions of U-Boot.
 ---
>>>
>>> [1] http://patchwork.ozlabs.org/patch/569323/
>>> [2] http://patchwork.ozlabs.org/patch/500246/
>>>
>>> Regards,
>>> Bin
>>
>> This does go against the driver-model philosophy of lazy init. I
>> wonder if we should add this patch with a Kconfig option to enable it?
>> Then it can be enabled only for boards that need it.
>>
>
> I suspect the issue is somewhere else. On Intel Galileo with a PCI
> ethernet, it works fine without such explicit pci init. Which PCI
> ethernet driver does not work on Tegra?

It could be because that board probes PCI to get its serial to work.

This could be fixed on Tegra by adding an Ethernet node to the device
tree to cause it to be probed. But I don't think that should be a
requirement.

Regards,
Simon
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[U-Boot] [PATCH 2/2] QE: assgin pins to QE-HDLC

[Zhao Qiang]

QE-HDLC and USB multi-use the pins, when set "hwconfig=qe-hdlc",
assign the pins to QE-HDLC, if not, assgin to USB

Signed-off-by: Zhao Qiang 
---
 board/freescale/ls1043ardb/ls1043ardb.c | 54 -
 1 file changed, 39 insertions(+), 15 deletions(-)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index 834fdff..042a59f 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -75,23 +75,8 @@ int dram_init(void)
 
 int board_early_init_f(void)
 {
-   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-   u32 usb_pwrfault;
-
fsl_lsch2_early_init_f();
 
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-   out_be32(&scfg->rcwpmuxcr0, 0x);
-   out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
-   usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
-   SCFG_USBPWRFAULT_USB3_SHIFT) |
-   (SCFG_USBPWRFAULT_DEDICATED <<
-   SCFG_USBPWRFAULT_USB2_SHIFT) |
-   (SCFG_USBPWRFAULT_SHARED <<
-SCFG_USBPWRFAULT_USB1_SHIFT);
-   out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
-#endif
-
return 0;
 }
 
@@ -126,6 +111,27 @@ int board_init(void)
 
 int config_board_mux(void)
 {
+   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+   u32 usb_pwrfault;
+
+   if (hwconfig("qe-hdlc")) {
+   out_be32(&scfg->rcwpmuxcr0,
+(in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
+   printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
+  in_be32(&scfg->rcwpmuxcr0));
+   } else {
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+   out_be32(&scfg->rcwpmuxcr0, 0x);
+   out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+   usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+   SCFG_USBPWRFAULT_USB3_SHIFT) |
+   (SCFG_USBPWRFAULT_DEDICATED <<
+   SCFG_USBPWRFAULT_USB2_SHIFT) |
+   (SCFG_USBPWRFAULT_SHARED <<
+SCFG_USBPWRFAULT_USB1_SHIFT);
+   out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+   }
return 0;
 }
 
@@ -152,6 +158,16 @@ int misc_init_r(void)
 }
 #endif
 
+void fdt_del_qe(void *blob)
+{
+   int nodeoff = 0;
+
+   while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+   "fsl,qe")) >= 0) {
+   fdt_del_node(blob, nodeoff);
+   }
+}
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
u64 base[CONFIG_NR_DRAM_BANKS];
@@ -169,6 +185,14 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
 #endif
+
+   if (hwconfig("qe-hdlc"))
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+   fdt_del_node_and_alias(blob, "usb1");
+#endif
+   else if (!hwconfig("qe-uart"))
+   fdt_del_qe(blob);
+
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] QE: add QE support on ls1043ardb

[Zhao Qiang]

Upload QE microcode on ls1043ardb

Signed-off-by: Zhao Qiang 
---
 board/freescale/ls1043ardb/ls1043ardb.c | 8 
 include/configs/ls1043ardb.h| 7 +++
 2 files changed, 15 insertions(+)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index c8f723a..834fdff 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -21,6 +21,10 @@
 #include 
 #include 
 #include "cpld.h"
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -113,6 +117,10 @@ int board_init(void)
enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_U_QE
+   u_qe_init();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 585114f..6494507 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -278,6 +278,13 @@
 #define CONFIG_ETHPRIME"FM1@DTSEC3"
 #endif
 
+/* QE */
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+   !defined(CONFIG_QSPI_BOOT)
+#define CONFIG_U_QE
+#endif
+#define CONFIG_SYS_QE_FW_ADDR 0x6060
+
 /* USB */
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

[Bin Meng]

Hi Simon,

On Fri, Jan 22, 2016 at 12:03 PM, Simon Glass  wrote:
> Hi Bin,
>
> On 21 January 2016 at 20:53, Bin Meng  wrote:
>> On Fri, Jan 22, 2016 at 11:36 AM, Simon Glass  wrote:
>>> Hi,
>>>
>>> On 21 January 2016 at 18:39, Bin Meng  wrote:
 Hi Stephen,

 On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  
 wrote:
> From: Stephen Warren 
>
> PCI controllers should be enumerated at startup so that PCI devices
> such as Ethernet controllers are available at startup. Fix board_init_r()
> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
> an implementation of pci_init() for the DM case.
>

 What exact issue are you trying to fix? I posted the same question on
 Simon's patch [1] before. Does your patch and Simon's fix the same
 issue?

 Note I submitted a similar patch [2] last year for x86 only, to
 explicitly trigger the PCI enueration. But it was not accepted.

> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
> for Ethernet")
> Signed-off-by: Stephen Warren 
> ---
> I'm not sure if relying on the side-effects of calling
> uclass_{first,ext}_device is the correct approach; is there a more 
> explicit
> way to probe all PCI controllers?
>
> Arguably, perhaps we should introduce a "pci start" command instead of
> this change to be consistent with e.g. USB. However, that would be a
> regression relative to earlier versions of U-Boot.
> ---

 [1] http://patchwork.ozlabs.org/patch/569323/
 [2] http://patchwork.ozlabs.org/patch/500246/

 Regards,
 Bin
>>>
>>> This does go against the driver-model philosophy of lazy init. I
>>> wonder if we should add this patch with a Kconfig option to enable it?
>>> Then it can be enabled only for boards that need it.
>>>
>>
>> I suspect the issue is somewhere else. On Intel Galileo with a PCI
>> ethernet, it works fine without such explicit pci init. Which PCI
>> ethernet driver does not work on Tegra?
>
> It could be because that board probes PCI to get its serial to work.

Even if it does not have a PCI serial, the PCI ethernet driver should
still have a chance to get PCI bus probe by calling one of these DM
PCI APIs. See an example in eth_designware.c. That's why I'd like to
know which PCI ethernet driver is this?

>
> This could be fixed on Tegra by adding an Ethernet node to the device
> tree to cause it to be probed. But I don't think that should be a
> requirement.
>

Regards,
Bin
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

[Simon Glass]

Hi Bin,

On 21 January 2016 at 21:06, Bin Meng  wrote:
> Hi Simon,
>
> On Fri, Jan 22, 2016 at 12:03 PM, Simon Glass  wrote:
>> Hi Bin,
>>
>> On 21 January 2016 at 20:53, Bin Meng  wrote:
>>> On Fri, Jan 22, 2016 at 11:36 AM, Simon Glass  wrote:
 Hi,

 On 21 January 2016 at 18:39, Bin Meng  wrote:
> Hi Stephen,
>
> On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  
> wrote:
>> From: Stephen Warren 
>>
>> PCI controllers should be enumerated at startup so that PCI devices
>> such as Ethernet controllers are available at startup. Fix board_init_r()
>> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
>> an implementation of pci_init() for the DM case.
>>
>
> What exact issue are you trying to fix? I posted the same question on
> Simon's patch [1] before. Does your patch and Simon's fix the same
> issue?
>
> Note I submitted a similar patch [2] last year for x86 only, to
> explicitly trigger the PCI enueration. But it was not accepted.
>
>> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver 
>> model
>> for Ethernet")
>> Signed-off-by: Stephen Warren 
>> ---
>> I'm not sure if relying on the side-effects of calling
>> uclass_{first,ext}_device is the correct approach; is there a more 
>> explicit
>> way to probe all PCI controllers?
>>
>> Arguably, perhaps we should introduce a "pci start" command instead of
>> this change to be consistent with e.g. USB. However, that would be a
>> regression relative to earlier versions of U-Boot.
>> ---
>
> [1] http://patchwork.ozlabs.org/patch/569323/
> [2] http://patchwork.ozlabs.org/patch/500246/
>
> Regards,
> Bin

 This does go against the driver-model philosophy of lazy init. I
 wonder if we should add this patch with a Kconfig option to enable it?
 Then it can be enabled only for boards that need it.

>>>
>>> I suspect the issue is somewhere else. On Intel Galileo with a PCI
>>> ethernet, it works fine without such explicit pci init. Which PCI
>>> ethernet driver does not work on Tegra?
>>
>> It could be because that board probes PCI to get its serial to work.
>
> Even if it does not have a PCI serial, the PCI ethernet driver should
> still have a chance to get PCI bus probe by calling one of these DM
> PCI APIs. See an example in eth_designware.c. That's why I'd like to
> know which PCI ethernet driver is this?

Well beaver uses RTL8169. But unless the driver is bound, it won't be
visible to the Ethernet stack.

>
>>
>> This could be fixed on Tegra by adding an Ethernet node to the device
>> tree to cause it to be probed. But I don't think that should be a
>> requirement.
>>
>
> Regards,
> Bin
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Re: [U-Boot] [Patch V5 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform

[Qianyu Gong]

> -Original Message-
> From: Scott Wood
> Sent: Friday, January 22, 2016 3:28 AM
> To: Qianyu Gong ; u-boot@lists.denx.de;
> r58...@freescale.com
> Cc: mingkai...@freescale.com; jt...@openedev.com; b48...@freescale.com;
> shaohui@freescale.com; wenbin.s...@freescale.com; Scott Wood
> ; Gong Qianyu 
> Subject: Re: [Patch V5 1/4] spi: fsl_qspi: fix compile warning for 64-bit 
> platform
> 
> On 01/20/2016 09:42 PM, Gong Qianyu wrote:
> > From: Gong Qianyu 
> >
> > This patch fixes the following compile warning:
> > drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
> > drivers/spi/fsl_qspi.c:937:15:
> >   warning: cast to pointer from integer of different size
> >  [-Wint-to-pointer-cast]
> >   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
> >^
> > Just make the cast explicit.
> >
> > Signed-off-by: Gong Qianyu 
> > ---
> > V5:
> >  - Use uintptr_t instead of unsigned long.
> > V4:
> >  - Revise the commit message.
> > V2-V3:
> >  - No change.
> >
> >  drivers/spi/fsl_qspi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 542b6cf..38e5900 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus)
> >
> > dm_spi_bus->max_hz = plat->speed_hz;
> >
> > -   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
> > +   priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
> > priv->flags = plat->flags;
> >
> > priv->speed_hz = plat->speed_hz;
> >
> 
> Use phys_to_virt().
> 
> -Scott

The function seems to be dropped in U-Boot? 
I just find it in arch/arm/include/asm/memory.h with ''#if 0''.

Regards,
Qianyu
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Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support

[Qianyu Gong]

Hi Scott,

> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Friday, January 22, 2016 6:50 AM
> To: Qianyu Gong ; u-boot@lists.denx.de
> Cc: b48...@freescale.com; wenbin.s...@freescale.com; Mingkai Hu
> 
> Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support
> 
> On Thu, 2016-01-14 at 04:26 +, Qianyu Gong wrote:
> > > -Original Message-
> > > From: Scott Wood [mailto:o...@buserror.net]
> > > Sent: Thursday, January 14, 2016 8:21 AM
> > > To: Qianyu Gong ; u-boot@lists.denx.de
> > > Cc: b07...@freescale.com; b48...@freescale.com;
> > > wenbin.s...@freescale.com; Mingkai Hu 
> > > Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot
> > > support
> > >
> > > On Tue, 2016-01-12 at 03:14 +, Qianyu Gong wrote:
> > > > > -Original Message-
> > > > > From: Scott Wood [mailto:o...@buserror.net]
> > > > > Sent: Tuesday, January 12, 2016 1:47 AM
> > > > > To: Qianyu Gong ; u-boot@lists.denx.de
> > > > > Cc: b07...@freescale.com; b48...@freescale.com;
> > > > > wenbin.s...@freescale.com; Mingkai Hu 
> > > > > Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI
> > > > > boot support
> > > > >
> > > > > On Mon, 2016-01-11 at 10:17 +0800, Gong Qianyu wrote:
> > > > > > diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > > b/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > > index d6696ca..770b79f 100644
> > > > > > --- a/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > > +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > > @@ -43,15 +43,19 @@ enum {
> > > > > >
> > > > > >  int checkboard(void)
> > > > > >  {
> > > > > > +#ifndef CONFIG_QSPI_BOOT
> > > > > > char buf[64];
> > > > > >  #ifndef CONFIG_SD_BOOT
> > > > > > u8 sw;
> > > > > >  #endif
> > > > > > +#endif
> > > > > >
> > > > > > puts("Board: LS1043AQDS, boot from ");
> > > > > >
> > > > > >  #ifdef CONFIG_SD_BOOT
> > > > > > puts("SD\n");
> > > > > > +#elif defined(CONFIG_QSPI_BOOT)
> > > > > > +   puts("QSPI\n");
> > > > > >  #else
> > > > > > sw = QIXIS_READ(brdcfg[0]);
> > > > > > sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@
> > > > > > -68,12
> > > > > +72,15
> > > > > > @@ int checkboard(void)
> > > > > > printf("invalid setting of SW%u\n",
> QIXIS_LBMAP_SWITCH);
> > > > > #endif
> > > > > >
> > > > > > +#ifndef CONFIG_QSPI_BOOT
> > > > > > +   /* For QSPI boot, here I2C is not ready yet. */
> > > > > > printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
> > > > > >QIXIS_READ(id), QIXIS_READ(arch));
> > > > > >
> > > > > > printf("FPGA:  v%d (%s), build %d\n",
> > > > > >(int)QIXIS_READ(scver), qixis_read_tag(buf),
> > > > > >(int)qixis_read_minor());
> > > > > > +#endif
> > > > >
> > > > > Why isn't i2c ready?  How is DDR inited without it?
> > > > >
> > > > > -Scott
> > > >
> > > > Hi Scott,
> > > >
> > > > The calling sequence in U-Boot is :
> > > > checkboard() -> init_func_i2c() -> dram_init()
> > > >
> > > > So I2C is not ready in checkboard() but is ready for DDR initialization.
> > >
> > > Can you move the prints later in the boot sequence?
> > >
> > > In any case, the relevant variable is whether qixis uses i2c, not
> > > whether you're booting from qspi (even if they are correlated).
> > >
> > > -Scott
> >
> > Yes. Only with QSPI it needs I2C to access QIXIS.
> > But if defining CONFIG_DISPLAY_BOARDINFO_LATE, the print layout will
> > look really uncomfortable.. So we just comment out the FPGA prints for QSPI
> boot.
> 
> Can this info be dumped from a command instead of just removed?
> 
> -Scott

We could only dump the registers using ''qixis_reset dump''. 
Another way is to just make QSPI boot print this info later.
The following is the boot log:

U-Boot 2016.01-00289-g946e8fe-dirty (Jan 22 2016 - 12:40:21 +0800)

SoC:  unknown (0x87920010)
Clock Configuration:
   CPU0(A53):1500 MHz  CPU1(A53):1500 MHz  CPU2(A53):1500 MHz
   CPU3(A53):1500 MHz
   Bus:  400  MHz  DDR:  1600 MT/s  FMAN: 500  MHz
Reset Configuration Word (RCW):
   : 081f 0c00  
   0010: 14550002 80004012 40025000 61002000
   0020:    00038800
   0030: 20124000 1100 0096 0001
I2C:   ready
DRAM:  Initializing DDRusing SPD
Detected UDIMM 9ASF51272AZ-2G1A1
2 GiB (DDR4, 32-bit, CL=11, ECC on)
Waking secondary cores to start from ffd42000
All (4) cores are up.
Using SERDES1 Protocol: 5205 (0x1455)
MMC:   FSL_SDHC: 0
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 
16 MiB
PCIe1: disabled
PCIe2: Root Complex no link, regs @ 0x350
PCIe3: Root Complex no link, regs @ 0x360
In:serial
Out:   serial
Err:   serial
Model: LS1043A QDS Board
Board: LS1043AQDS, boot from QSPI
Sys ID: 0x36, Sys Ver: 0x11
FPGA:  v5 (LS1043QDS_2015_0427_1339), build 5
SATA link 0 timeout.
AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
fla

Re: [U-Boot] [PATCH] ls2085a: Correct the model & board name of RDB and QDS

[Calvin Johnson]

Hi Ashish,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Ashish,
> Kumar
> Sent: Wednesday, January 20, 2016 12:33 PM
> To: prabhakar.khusw...@nxp.com; u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH] ls2085a: Correct the model & board name of RDB
> and QDS
> 
>  * LS2085ARDB and LS2085AQDS host LS2080A and LS2085A,
> So update model and board name.
> 
> Signed-off-by: Ashish Kumar 
> ---
>  arch/arm/dts/fsl-ls2080a-qds.dts|2 +-
>  arch/arm/dts/fsl-ls2080a-rdb.dts|2 +-
>  board/freescale/ls2080aqds/ls2080aqds.c |3 +--
>  board/freescale/ls2080ardb/ls2080ardb.c |4 +---
>  4 files changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts 
> b/arch/arm/dts/fsl-ls2080a-qds.dts
> index 547ec27..7b1dae8 100644
> --- a/arch/arm/dts/fsl-ls2080a-qds.dts
> +++ b/arch/arm/dts/fsl-ls2080a-qds.dts
> @@ -11,7 +11,7 @@
>  #include "fsl-ls2080a.dtsi"
> 
>  / {
> - model = "Freescale Layerscape 2080a QDS Board";
> + model = "Freescale Layerscape 2085a QDS Board";
>   compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
> 
>   aliases {
> diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts 
> b/arch/arm/dts/fsl-ls2080a-rdb.dts
> index 1a1813b..71d1969 100644
> --- a/arch/arm/dts/fsl-ls2080a-rdb.dts
> +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts
> @@ -11,7 +11,7 @@
>  #include "fsl-ls2080a.dtsi"
> 
>  / {
> - model = "Freescale Layerscape 2080a RDB Board";
> + model = "Freescale Layerscape 2085a RDB Board";
>   compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
> 
>   aliases {
> diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
> b/board/freescale/ls2080aqds/ls2080aqds.c
> index aa256a2..fe20f3a 100644
> --- a/board/freescale/ls2080aqds/ls2080aqds.c
> +++ b/board/freescale/ls2080aqds/ls2080aqds.c
> @@ -61,8 +61,7 @@ int checkboard(void)
>   "100 separate SSCG"};
>   int clock;
> 
> - cpu_name(buf);
> - printf("Board: %s-QDS, ", buf);
> + printf("Board: LS2085A-QDS, ");

Isn't it good to change the file name to ls2085aqds.c?

> 
>   sw = QIXIS_READ(arch);
>   printf("Board Arch: V%d, ", sw >> 4);
> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
> b/board/freescale/ls2080ardb/ls2080ardb.c
> index c63b639..ccf98c9 100644
> --- a/board/freescale/ls2080ardb/ls2080ardb.c
> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
> @@ -54,10 +54,8 @@ unsigned long long get_qixis_addr(void)  int
> checkboard(void)  {
>   u8 sw;
> - char buf[15];
> 
> - cpu_name(buf);
> - printf("Board: %s-RDB, ", buf);
> + printf("Board: LS2085A-RDB, ");

And here file name change to ls1085rdb.c?

> 
>   sw = QIXIS_READ(arch);
>   printf("Board Arch: V%d, ", sw >> 4);
> --
> 1.7.6.GIT
> 
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Regards
Calvin
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Re: [U-Boot] [PATCH v9 18/49] rockchip: i2c: Update the driver to use the new clock ID

[Heiko Schocher]

Hello Simon,

Am 22.01.2016 um 03:43 schrieb Simon Glass:

We can use the new clk_get_by_index() function to get the correct clock.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2:
- Update call to clk_get_by_index()

  drivers/i2c/rk_i2c.c | 38 ++
  1 file changed, 22 insertions(+), 16 deletions(-)


Thanks!

Reviewed-by: Heiko Schocher 

bye,
Heiko

diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index ebdba35..3fceade 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -30,10 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;

  struct rk_i2c {
struct udevice *clk;
-   struct udevice *pinctrl;
struct i2c_regs *regs;
unsigned int speed;
-   enum periph_id id;
+   int clk_id;
  };

  static inline void rk_i2c_get_div(int div, int *divh, int *divl)
@@ -56,7 +55,7 @@ static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t 
scl_rate)
int div, divl, divh;

/* First get i2c rate from pclk */
-   i2c_rate = clk_get_periph_rate(i2c->clk, i2c->id);
+   i2c_rate = clk_get_periph_rate(i2c->clk, i2c->clk_id);

div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
divh = 0;
@@ -352,23 +351,29 @@ int rockchip_i2c_set_bus_speed(struct udevice *bus, 
unsigned int speed)
return 0;
  }

-static int rockchip_i2c_probe(struct udevice *bus)
+static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
  {
-   struct rk_i2c *i2c = dev_get_priv(bus);
+   struct rk_i2c *priv = dev_get_priv(bus);
int ret;

-   ret = uclass_get_device(UCLASS_PINCTRL, 0, &i2c->pinctrl);
-   if (ret)
-   return ret;
-   ret = uclass_get_device(UCLASS_CLK, 0, &i2c->clk);
-   if (ret)
-   return ret;
-   ret = pinctrl_get_periph_id(i2c->pinctrl, bus);
-   if (ret < 0)
+   ret = clk_get_by_index(bus, 0, &priv->clk);
+   if (ret < 0) {
+   debug("%s: Could not get clock for %s: %d\n", __func__,
+ bus->name, ret);
return ret;
-   i2c->id = ret;
-   i2c->regs = (void *)dev_get_addr(bus);
-   return pinctrl_request(i2c->pinctrl, i2c->id, 0);
+   }
+   priv->clk_id = ret;
+
+   return 0;
+}
+
+static int rockchip_i2c_probe(struct udevice *bus)
+{
+   struct rk_i2c *priv = dev_get_priv(bus);
+
+   priv->regs = (void *)dev_get_addr(bus);
+
+   return 0;
  }

  static const struct dm_i2c_ops rockchip_i2c_ops = {
@@ -385,6 +390,7 @@ U_BOOT_DRIVER(i2c_rockchip) = {
.name   = "i2c_rockchip",
.id = UCLASS_I2C,
.of_match = rockchip_i2c_ids,
+   .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
.probe  = rockchip_i2c_probe,
.priv_auto_alloc_size = sizeof(struct rk_i2c),
.ops= &rockchip_i2c_ops,



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Re: [U-Boot] [PATCH v9 29/49] dm: i2c: Allow muxes to be enabled for SPL separately

[Heiko Schocher]

Hello Simon,

Am 22.01.2016 um 03:43 schrieb Simon Glass:

Since I2C muxes are seldom needed in SPL, and the code for this increases
the size somewhat, add a separate option to enable I2C muxes for SPL.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

  drivers/i2c/Makefile   | 4 ++--
  drivers/i2c/muxes/Kconfig  | 9 +
  drivers/i2c/muxes/Makefile | 2 +-
  3 files changed, 12 insertions(+), 3 deletions(-)


Thanks!

Reviewed-by: Heiko Schocher 

bye,
Heiko


diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 811ad9b..bbbc0dc 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -7,8 +7,8 @@
  obj-$(CONFIG_DM_I2C) += i2c-uclass.o
  obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o
  obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
-obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
-obj-$(CONFIG_I2C_CROS_EC_LDO) += cros_ec_ldo.o
+obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
+obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o

  obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
  obj-$(CONFIG_I2C_MV) += mv_i2c.o
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 913093d..f959d9d 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -7,6 +7,15 @@ config I2C_MUX
  bus select is handled automatically when that bus is accessed,
  using a suitable I2C MUX driver.

+config SPL_I2C_MUX
+   bool "Support I2C multiplexers on SPL"
+   depends on I2C_MUX
+   help
+ This enables I2C buses to be multiplexed, so that you can select
+ one of several buses using some sort of control mechanism. The
+ bus select is handled automatically when that bus is accessed,
+ using a suitable I2C MUX driver.
+
  config I2C_ARB_GPIO_CHALLENGE
bool "GPIO-based I2C arbitration"
depends on I2C_MUX
diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile
index 612cc27..47c1240 100644
--- a/drivers/i2c/muxes/Makefile
+++ b/drivers/i2c/muxes/Makefile
@@ -4,4 +4,4 @@
  # SPDX-License-Identifier:GPL-2.0+
  #
  obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
-obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o
+obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o



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[U-Boot] [Patch V6 4/4] dm: env_sf: fix saveenv() to use driver model

[Gong Qianyu]

From: Gong Qianyu 

It might be missed when converting spi_flash_probe() in cmd_sf.c.

This patch refers to commit fbb099183e3a ("dm: Convert
spi_flash_probe() and 'sf probe' to use driver model").

Signed-off-by: Gong Qianyu 
---
V6:
 - No change.
V5:
 - Revise commit message.
V4:
 - Use CONFIG_ENV_* instead of CONFIG_SF_*.
 - Remove the variables and call the macros directly.
 - Use set_default_env instead of print info.
V3:
 - Remove redundant operations for saveenv()
V2:
 - New patch.

 common/env_sf.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/common/env_sf.c b/common/env_sf.c
index 9409831..892e6cb 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifndef CONFIG_ENV_SPI_BUS
 # define CONFIG_ENV_SPI_BUS0
@@ -51,6 +52,19 @@ int saveenv(void)
char*saved_buffer = NULL, flag = OBSOLETE_FLAG;
u32 saved_size, saved_offset, sector = 1;
int ret;
+#ifdef CONFIG_DM_SPI_FLASH
+   struct udevice *new;
+
+   ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+CONFIG_ENV_SPI_MAX_HZ,
+CONFIG_ENV_SPI_MODE, &new);
+   if (ret) {
+   set_default_env("!spi_flash_probe_bus_cs() failed");
+   return 1;
+   }
+
+   env_flash = dev_get_uclass_priv(new);
+#else
 
if (!env_flash) {
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
@@ -61,6 +75,7 @@ int saveenv(void)
return 1;
}
}
+#endif
 
ret = env_export(&env_new);
if (ret)
@@ -227,6 +242,19 @@ int saveenv(void)
char*saved_buffer = NULL;
int ret = 1;
env_t   env_new;
+#ifdef CONFIG_DM_SPI_FLASH
+   struct udevice *new;
+
+   ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+CONFIG_ENV_SPI_MAX_HZ,
+CONFIG_ENV_SPI_MODE, &new);
+   if (ret) {
+   set_default_env("!spi_flash_probe_bus_cs() failed");
+   return 1;
+   }
+
+   env_flash = dev_get_uclass_priv(new);
+#else
 
if (!env_flash) {
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
@@ -237,6 +265,7 @@ int saveenv(void)
return 1;
}
}
+#endif
 
/* Is the sector larger than the env (i.e. embedded) */
if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V6 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue

[Gong Qianyu]

From: Gong Qianyu 

In current driver everytime we memcpy 4 bytes to the dest memory
regardless of the remaining length.
This patch adds checking the remaining length before memcpy.
If the length is shorter than 4 bytes, memcpy the actual length of data
to the dest memory.

Signed-off-by: Gong Qianyu 
---
V6:
 - Use min() to simplify code.
V2-V5:
 - No change.
 
 drivers/spi/fsl_qspi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 38e5900..3fe80d3 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -500,7 +500,7 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 
*rxbuf, u32 len)
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
data = qspi_endian_xchg(data);
-   memcpy(rxbuf, &data, 4);
+   memcpy(rxbuf, &data, min(size, 4));
rxbuf++;
size -= 4;
i++;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V6 0/4] QSPI bug fixing patches

[Gong Qianyu]

This patchset is mainly related with Freescale QSPI and tested
on LS1043AQDS board.

The version 6 patchset has fixes to:
 - Use min() to simplify the code in QSPI driver.

[Patch V6 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform
[Patch V6 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue
[Patch V6 3/4] spi: fsl_qspi: Fix qspi_op_rdsr memcpy issue
[Patch V6 4/4] dm: env_sf: fix saveenv() to use driver model



Regards,
Qianyu
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[U-Boot] [Patch V6 3/4] spi: fsl_qspi: Fix qspi_op_rdsr memcpy issue

[Gong Qianyu]

From: Gong Qianyu 

In current driver, we always copy 4 bytes to the dest memory.
Actually the dest memory may be shorter than 4 bytes.
Add an argument to indicate the dest memory length.
Avoid writing memory outside of the bounds.

Signed-off-by: Gong Qianyu 
---
V3-V6:
 - No change.
V2:
 - New patch. 

 drivers/spi/fsl_qspi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 3fe80d3..1cee1d7 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -639,7 +639,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 
*txbuf, u32 len)
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
 }
 
-static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf)
+static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 {
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg, reg, data;
@@ -662,7 +662,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 
*rxbuf)
if (reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[0]);
data = qspi_endian_xchg(data);
-   memcpy(rxbuf, &data, 4);
+   memcpy(rxbuf, &data, len);
qspi_write32(priv->flags, ®s->mcr,
 qspi_read32(priv->flags, ®s->mcr) |
 QSPI_MCR_CLR_RXF_MASK);
@@ -751,7 +751,7 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int 
bitlen,
} else if (priv->cur_seqid == QSPI_CMD_RDID)
qspi_op_rdid(priv, din, bytes);
else if (priv->cur_seqid == QSPI_CMD_RDSR)
-   qspi_op_rdsr(priv, din);
+   qspi_op_rdsr(priv, din, bytes);
 #ifdef CONFIG_SPI_FLASH_BAR
else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
-- 
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[U-Boot] [Patch V6 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform

[Gong Qianyu]

From: Gong Qianyu 

This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
  warning: cast to pointer from integer of different size
 [-Wint-to-pointer-cast]
  priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
   ^
Just make the cast explicit.

Signed-off-by: Gong Qianyu 
---
V6:
 - No change.
V5:
 - Use uintptr_t instead of unsigned long.
V4:
 - Revise the commit message.
V2-V3:
 - No change.

 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 542b6cf..38e5900 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
dm_spi_bus->max_hz = plat->speed_hz;
 
-   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
+   priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
priv->flags = plat->flags;
 
priv->speed_hz = plat->speed_hz;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2 v3] board/t4240rdb: VID support

[ying.zhang]

From: Ying Zhang 

The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

Signed-off-by: Ying Zhang 
---
Changed from v2:
- Split the Intel mode support patch
Changed from v1:
- Not support IR chip is used in AMD mode
---
 board/freescale/common/vid.c |  2 +-
 board/freescale/t4rdb/t4240rdb.c |  7 +++
 include/configs/T4240RDB.h   | 10 ++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 1ea1b88..1bd65a8 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -42,7 +42,7 @@ int __weak board_vdd_drop_compensation(void)
  * The IR chip can show up under the following addresses:
  * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
  * 0x09 (Verified on T1040RDB-PA)
- * 0x38 (Verified on T2080QDS, T2081QDS)
+ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
  */
 static int find_ir_chip_on_i2c(void)
 {
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index fac442b..99a8730 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -21,6 +21,7 @@
 
 #include "t4rdb.h"
 #include "cpld.h"
+#include "../common/vid.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -79,6 +80,12 @@ int board_early_init_r(void)
 #ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
 #endif
+   /*
+* Adjust core voltage according to voltage ID
+* This function changes I2C mux to channel 2.
+   */
+   if (adjust_vdd(0))
+   printf("Warning: Adjusting core voltage failed.\n");
 
return 0;
 }
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 73279c8..4a17f41 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -606,6 +606,16 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_VOL_MONITOR_BUS_V_OVF  0x1
 #define I2C_VOL_MONITOR_BUS_V_SHIFT3
 
+#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T4240RDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
 /*
  * eSPI - Enhanced SPI
  */
-- 
1.8.4.1

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[U-Boot] [PATCH 1/2 v3] VID: support IR chip is used in Intel mode

[ying.zhang]

From: Ying Zhang 

IR chip on all the boards support VID are required to be
used in Intel mode.
the VDD will not be adjusted while IR chip is not used in
Intel mode.

Signed-off-by: Ying Zhang 
---
Changed from v2:
- Separate this patch from T4RDB VID support patch
Changed from v1:
- Not support IR chip is used in AMD mode
---
 board/freescale/common/vid.c | 17 -
 board/freescale/common/vid.h |  4 
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index f1bed51..1ea1b88 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override)
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
u32 fusesr;
-   u8 vid;
+   u8 vid, buf;
int vdd_target, vdd_current, vdd_last;
int ret, i2caddress;
unsigned long vdd_string_override;
@@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override)
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
 
+   /* check IR chip work on Intel mode*/
+   ret = i2c_read(i2caddress,
+  IR36021_INTEL_MODE_OOFSET,
+  1, (void *)&buf, 1);
+   if (ret) {
+   printf("VID: failed to read IR chip mode.\n");
+   ret = -1;
+   goto exit;
+   }
+   if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+   printf("VID: IR Chip is not used in Intel mode.\n");
+   ret = -1;
+   goto exit;
+   }
+
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
/*
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
index a9c7bb4..9182c20 100644
--- a/board/freescale/common/vid.h
+++ b/board/freescale/common/vid.h
@@ -11,6 +11,10 @@
 #define IR36021_LOOP1_VOUT_OFFSET  0x9A
 #define IR36021_MFR_ID_OFFSET  0x92
 #define IR36021_MFR_ID 0x43
+#define IR36021_INTEL_MODE_OOFSET  0x14
+#define IR36021_MODE_MASK  0x20
+#define IR36021_INTEL_MODE 0x00
+#define IR36021_AMD_MODE   0x20
 
 /* step the IR regulator in 5mV increments */
 #define IR_VDD_STEP_DOWN   5
-- 
1.8.4.1

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