date:20160305

Re: [U-Boot] [U-BOOT.V2] usb: xhci: Fix vendor command error if the request

2016-03-05 Thread Marek Vasut

On 03/05/2016 06:53 PM, Anand Moon wrote:
> Hi Marek,

Hi!

> On 5 March 2016 at 18:00, Marek Vasut  wrote:
>> On 03/05/2016 09:43 AM, Anand Moon wrote:
>>> From: Ted Chen 
>>>
>>> From: Ted Chen 
>>>
>>> type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION.
>>> To: ma...@denx.de, swar...@nvidia.com, u-boot@lists.denx.de
>>> Cc: linux.am...@gmail.com, Ted Chen 
>>>
>>> Add a condition of set_address and set_configuration to check
>>> if the request is standardized.
>>
>> Can you please rephrase the commit message ? It's really hard to
>> understand. I believe such a patch will be needed for ehci as well,
>> can you prepare one ?
> 
> I could not find any need for such check in ehci-hcd driver.

Please explain why this is not needed.

> Sorry for this mess in commit message, I completely missed formatting
> the statement
> because of it got warped up in the message
> Will send this message again with proper commit message.

Yes, the message is complete chaos.

>>
>>> Signed-off-by: Ted Chen 
>>> ---
>>> Resend this patch it some how got missed
>>> Changes since v1: None.
>>>
>>> Tested on Odroid XU4: with Ethernet USB3.0 RT8153-VB
>>> ---
>>>  drivers/usb/host/xhci.c | 6 --
>>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>>> index ca598aa..cb8a04b 100644
>>> --- a/drivers/usb/host/xhci.c
>>> +++ b/drivers/usb/host/xhci.c
>>> @@ -941,10 +941,12 @@ static int _xhci_submit_control_msg(struct usb_device 
>>> *udev, unsigned long pipe,
>>>   if (usb_pipedevice(pipe) == ctrl->rootdev)
>>>   return xhci_submit_root(udev, pipe, buffer, setup);
>>>
>>> - if (setup->request == USB_REQ_SET_ADDRESS)
>>> + if (setup->request == USB_REQ_SET_ADDRESS &&
>>> +(setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
>>>   return xhci_address_device(udev, root_portnr);
>>>
>>> - if (setup->request == USB_REQ_SET_CONFIGURATION) {
>>> + if (setup->request == USB_REQ_SET_CONFIGURATION &&
>>> +(setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
>>>   ret = xhci_set_configuration(udev);
>>>   if (ret) {
>>>   puts("Failed to configure xHCI endpoint\n");
>>>
>>
>> What happens to the non-standard requests ?
>>
> Device will not able to detect leaving message
> "scanning usb for ethernet devices... Non standard request in USB
> vendor command"

Let me re-phrase, how are the non-standard requests handled ?

>> --
>> Best regards,
>> Marek Vasut
> 
> Here is the modified commit message
> 
> "Add a condition of set_address and set_configuration to check
> if the requesttype is of standardized in the USB vendor request
> so that usb device is detected"

Add test into xhci_submit_control_message for usb requesttype in USB
vendor request being of standardized type. This fixes detection of
certain USB fixes, for example .

> Do you agree with this modified commit statement.
> 
> Best regards,
> -Anand Moon
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] serial: pl01x: Add support for devices with the rate pre-configured.

2016-03-05 Thread Stephen Warren


On 02/05/2016 09:19 PM, Stephen Warren wrote:

On 02/05/2016 02:43 PM, Eric Anholt wrote:

For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt.  Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.


Tested-by: Stephen Warren 
(With a 6MHz init_uart_clock and with/without init_uart_baud=9600)


Simon/Tom, did this slip through the cracks, or are you deferring it 
until the next release?

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Re: [U-Boot] [PATCH v2 00/18] Add support for 96boards Dragonboard410C board

2016-03-05 Thread Mateusz Kulikowski

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256

Hi Tom,

I finally was able to do some coding and so:

On 25.02.2016 00:42, Tom Rini wrote:
> On Sun, Feb 07, 2016 at 09:57:20PM +0100, Mateusz Kulikowski wrote:
[...]
>> - Rebased to recent master
> 
> Please note that I see a lot of warnings when building this both with
> gcc-5 and gcc-4.9, please fix.  Thanks!
> 
For v3 I've created 3 patches that fix asix and ULPI warnings.

It was easier than I was afraid :)

I will post it soon (tm).

Regards,
Mateusz
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[U-Boot] [PATCH 1/2] OMAP3: am3517_evm: Use BCH8 ECC for NAND

2016-03-05 Thread Derald D. Woods

Select 8-bit BCH ecc-scheme with s/w based error correction
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW

Signed-off-by: Derald D. Woods 
---
 include/configs/am3517_evm.h | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 4d662ad..98a59c5 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -328,8 +328,8 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE   0x40200800
-#define CONFIG_SPL_MAX_SIZE(54 * 1024) /* 8 KB for stack */
+#define CONFIG_SPL_TEXT_BASE   0x4020
+#define CONFIG_SPL_MAX_SIZE(64 * 1024)
 
 #define CONFIG_SPL_BSS_START_ADDR  0x8000
 #define CONFIG_SPL_BSS_MAX_SIZE0x8 /* 512 KB */
@@ -354,17 +354,26 @@
 #define CONFIG_SPL_LDSCRIPT"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 /* NAND boot config */
+#define CONFIG_BCH
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT 64
 #define CONFIG_SYS_NAND_PAGE_SIZE  2048
 #define CONFIG_SYS_NAND_OOBSIZE64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
-   10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCPOS { 2,  3,  4,  5,  6,  7,  8,  9, 10, \
+11, 12, 13, 14, 16, 17, 18, 19, 20, \
+21, 22, 23, 24, 25, 26, 27, 28, 30, \
+31, 32, 33, 34, 35, 36, 37, 38, 39, \
+40, 41, 42, 44, 45, 46, 47, 48, 49, \
+50, 51, 52, 53, 54, 55, 56 }
+
 #define CONFIG_SYS_NAND_ECCSIZE512
-#define CONFIG_SYS_NAND_ECCBYTES   3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_ECCBYTES   13
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_MAX_OOBFREE2
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS0x8
 
-- 
2.7.2

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[U-Boot] [PATCH 2/2] OMAP3: am3517_evm: Add NAND MTD partitions with UBI/UBIFS support

2016-03-05 Thread Derald D. Woods

- Add required UBI/UBIFS config definitions
- Add reasonable MTD partition layout
- Remove JFFS2 config definitions
- Drop some CFI verbage and definitions
- Make comment 'one-liners' truly one line
- Improve readability and content arrangement

Signed-off-by: Derald D. Woods 
---
 configs/am3517_evm_defconfig |   2 +
 include/configs/am3517_evm.h | 309 +--
 2 files changed, 153 insertions(+), 158 deletions(-)

diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index cde84fe..c7699e0 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -4,9 +4,11 @@ CONFIG_TARGET_AM3517_EVM=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_PROMPT="AM3517_EVM # "
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 98a59c5..5b689a8 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -13,14 +13,17 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE  64
+/* High Level Configuration Options */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP1   /* in a TI OMAP core */
-#define CONFIG_OMAP3_AM3517EVM 1   /* working with AM3517EVM */
+#define CONFIG_OMAP
 #define CONFIG_OMAP_COMMON
+
+#define CONFIG_SYS_CACHELINE_SIZE  64
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_NR_DRAM_BANKS   2   /* CS1 may or may not be populated */
+
 /* Common ARM Erratas */
 #define CONFIG_ARM_ERRATA_454179
 #define CONFIG_ARM_ERRATA_430973
@@ -28,59 +31,48 @@
 
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x8010 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE   0x8010
+#define CONFIG_SYS_SPL_MALLOC_START0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
+
 #include   /* get chip and board defs */
 #include 
 
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO   1
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_OF_LIBFDT
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 /* Clock Defines */
 #define V_OSCK 2600/* Clock output from T2 */
 #define V_SCLK (V_OSCK >> 1)
 
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_CMDLINE_TAG 1   /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS   1
-#define CONFIG_INITRD_TAG  1
-#define CONFIG_REVISION_TAG1
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN  (16 << 20)
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE(128 << 10) /* 128 KiB 
sector */
-#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (128 << 10))
-/*
- * DDR related
- */
-#define CONFIG_SYS_CS0_SIZE(256 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
+/* Hardware drivers */
 
-/*
- * OMAP GPIO configuration
- */
+/* OMAP GPIO configuration */
 #define CONFIG_OMAP_GPIO
 
-/*
- * NS16550 Configuration
- */
+/* NS16550 Configuration */
 #define V_NS16550_CLK  4800/* 48MHz (APLL96/2) */
-
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE(-4)
 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
 
-/*
- * select serial console configuration
- */
+/* select serial console configuration */
 #define CONFIG_CONS_INDEX  3
 #define CONFIG_SYS_NS16550_COM3OMAP34XX_UART3
 #define CONFIG_SERIAL3 3   /* UART3 on AM3517 EVM */
@@ -90,10 +82,12 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_OMAP_HSMMC  1
-#define CONFIG_DOS_PARTITION   1
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
 
 /*
  * USB configuration
@@ -111,7 +105,6 @@
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
 
 #ifdef CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
@@ -129,30 +122,29 @@
 #endif /* CONFIG_USB_MUSB_AM35X */

[U-Boot] [PATCH V2 0/2] OMAP3: am3517_evm: Add BCH8 ECC and UBIFS NAND support

2016-03-05 Thread Derald D. Woods

This patch series updates NAND support for the LogicPD AM3517 EVM/EXP
development boards and their corresponding System On Modules.

OMAP3: am3517_evm: Use BCH8 ECC for NAND
 include/configs/am3517_evm.h | 23 ---
 1 file changed, 16 insertions(+), 7 deletions(-)

OMAP3: am3517_evm: Add NAND MTD partitions with UBI/UBIFS support
 configs/am3517_evm_defconfig |   2 +
 include/configs/am3517_evm.h | 309 +--
 2 files changed, 153 insertions(+), 158 deletions(-)

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[U-Boot] [PATCH] sandbox: Fix building with LLVM

2016-03-05 Thread Tom Rini

- The macro __BIGGEST_ALIGNMENT__ is gcc-specific.  If it is not defined
  we'll just assume 16.  This is correct for at least the common cases
  and LLVM does not provide an equivalent macro.
- When linking U-Boot we're passing -T to the linker, and while gcc will
  just pass this along with LLVM we need to be specific.

Cc: Simon Glass 
Signed-off-by: Tom Rini 

---
I've tested this with both test/fs/fs-test.sh (and a quick kludge to
force it to use LLVM) and test/pytest/test.py with a pre-built sandbox
and both pass as much as with gcc does for me.
---
 arch/sandbox/config.mk   |2 +-
 arch/sandbox/include/asm/cache.h |6 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index b05a90f..16fd6d5 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -16,7 +16,7 @@ PLATFORM_CPPFLAGS += $(shell sdl-config --cflags)
 endif
 endif
 
-cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
+cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds \
-Wl,--start-group $(u-boot-main) -Wl,--end-group \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
 
diff --git a/arch/sandbox/include/asm/cache.h b/arch/sandbox/include/asm/cache.h
index d28c385..ffbb984 100644
--- a/arch/sandbox/include/asm/cache.h
+++ b/arch/sandbox/include/asm/cache.h
@@ -12,7 +12,13 @@
  * the contents of stack buffers to something reasonable.  The
  * GCC macro __BIGGEST_ALIGNMENT__ is defined to be the maximum
  * required alignment for any basic type.  This seems reasonable.
+ * This is however GCC specific so if we don't have that available
+ * assume that 16 is large enough.
  */
+#ifdef __BIGGEST_ALIGNMENT__
 #define ARCH_DMA_MINALIGN  __BIGGEST_ALIGNMENT__
+#else
+#define ARCH_DMA_MINALIGN  16
+#endif
 
 #endif /* __SANDBOX_CACHE_H__ */
-- 
1.7.9.5

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Re: [U-Boot] [PATCH V2 1/2] malloc: use hidden visibility

2016-03-05 Thread Tom Rini

On Sat, Mar 05, 2016 at 11:31:46AM -0700, Stephen Warren wrote:
> On 03/05/2016 10:44 AM, Tom Rini wrote:
> >On Sat, Mar 05, 2016 at 10:30:52AM -0700, Stephen Warren wrote:
> >
> >>When running sandbox, the following phases occur, each with different
> >>malloc implementations or behaviors:
> >>
> >>1) Dynamic linker execution, using the dynamic linker's own malloc()
> >>implementation. This is fully functional.
> >>
> >>2) After U-Boot's malloc symbol has been hooked into the GOT, but before
> >>any U-Boot code has run. This phase is entirely non-functional, since
> >>U-Boot's gd symbol is NULL and U-Boot's initf_malloc() and
> >>mem_malloc_init() have not been called.
> >>
> >>At least on Ubuntu Xenial, the dynamic linker does make both malloc() and
> >>free() calls during this phase. Currently these free() calls crash since
> >>they dereference gd, which is NULL.
> >>
> >>U-Boot itself makes no use of malloc() during this phase.
> >>
> >>3) U-Boot execution after gd is set and initf_malloc() has been called.
> >>This is fully functional, albeit via a very simple malloc()
> >>implementation.
> >>
> >>4) U-Boot execution after mem_malloc_init() has been called. This is fully
> >>functional with a complete malloc() implementation.
> >>
> >>Furthermore, if code that called malloc() during phase 1 calls free() in
> >>phase 3 or later, it is likely that heap corruption will occur, since
> >>U-Boot's malloc implementation will assume the pointer is part of its own
> >>heap, although it isn't. I have not actively observed this happening.
> >>
> >>To prevent phase 2 from happening, this patch makes all of U-Boot's malloc
> >>library public symbols have hidden visibility. This prevents them from
> >>being hooked into the GOT, so only code in the U-Boot binary itself
> >>actually calls them; any other code will call into the standard C library
> >>malloc(). This also avoids the "furthermore" issue mentioned above.
> >>
> >>I have seen references to this GCC pragma in blog posts from 2008, and
> >>RHEL5's ancient gcc appears to accept it fine, so I believe it's quite
> >>safe to use it without checking gcc version.
> >>
> >>Cc: Rabin Vincent 
> >>Signed-off-by: Stephen Warren 
> >
> >Reviewed-by: Tom Rini 
> >
> >But have you tried with clang instead of gcc?  I suspect it's got code
> >to pretend to be gcc and do the right thing here but it's worth
> >confirming.
> 
> Well, clang for sandbox doesn't compile for reasons other than these
> patches on either Ubuntu 14.04 or 16.04 pre-release, nor using the
> instructions in doc/README.clang for rpi on 16.04. However, it did
> work for rpi on Ubuntu 14.04.
> 
> So in summary, I think there's no issue using this pragma with
> clang, but I can't test that clang actually implements it and hence
> solves the problem these patches fix.

OK, I did a quick local check after fixing the __BIGGEST_ALIGNMENT__
problem (but not the linking problem) and see llvm 3.5 at least is OK
with this, so we're good enough then, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH V2 1/2] malloc: use hidden visibility

2016-03-05 Thread Stephen Warren


On 03/05/2016 10:44 AM, Tom Rini wrote:

On Sat, Mar 05, 2016 at 10:30:52AM -0700, Stephen Warren wrote:


When running sandbox, the following phases occur, each with different
malloc implementations or behaviors:

1) Dynamic linker execution, using the dynamic linker's own malloc()
implementation. This is fully functional.

2) After U-Boot's malloc symbol has been hooked into the GOT, but before
any U-Boot code has run. This phase is entirely non-functional, since
U-Boot's gd symbol is NULL and U-Boot's initf_malloc() and
mem_malloc_init() have not been called.

At least on Ubuntu Xenial, the dynamic linker does make both malloc() and
free() calls during this phase. Currently these free() calls crash since
they dereference gd, which is NULL.

U-Boot itself makes no use of malloc() during this phase.

3) U-Boot execution after gd is set and initf_malloc() has been called.
This is fully functional, albeit via a very simple malloc()
implementation.

4) U-Boot execution after mem_malloc_init() has been called. This is fully
functional with a complete malloc() implementation.

Furthermore, if code that called malloc() during phase 1 calls free() in
phase 3 or later, it is likely that heap corruption will occur, since
U-Boot's malloc implementation will assume the pointer is part of its own
heap, although it isn't. I have not actively observed this happening.

To prevent phase 2 from happening, this patch makes all of U-Boot's malloc
library public symbols have hidden visibility. This prevents them from
being hooked into the GOT, so only code in the U-Boot binary itself
actually calls them; any other code will call into the standard C library
malloc(). This also avoids the "furthermore" issue mentioned above.

I have seen references to this GCC pragma in blog posts from 2008, and
RHEL5's ancient gcc appears to accept it fine, so I believe it's quite
safe to use it without checking gcc version.

Cc: Rabin Vincent 
Signed-off-by: Stephen Warren 


Reviewed-by: Tom Rini 

But have you tried with clang instead of gcc?  I suspect it's got code
to pretend to be gcc and do the right thing here but it's worth
confirming.


Well, clang for sandbox doesn't compile for reasons other than these 
patches on either Ubuntu 14.04 or 16.04 pre-release, nor using the 
instructions in doc/README.clang for rpi on 16.04. However, it did work 
for rpi on Ubuntu 14.04.


So in summary, I think there's no issue using this pragma with clang, 
but I can't test that clang actually implements it and hence solves the 
problem these patches fix.

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Re: [U-Boot] [U-BOOT.V2] usb: xhci: Fix vendor command error if the request

2016-03-05 Thread Anand Moon

Hi Marek,

On 5 March 2016 at 18:00, Marek Vasut  wrote:
> On 03/05/2016 09:43 AM, Anand Moon wrote:
>> From: Ted Chen 
>>
>> From: Ted Chen 
>>
>> type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION.
>> To: ma...@denx.de, swar...@nvidia.com, u-boot@lists.denx.de
>> Cc: linux.am...@gmail.com, Ted Chen 
>>
>> Add a condition of set_address and set_configuration to check
>> if the request is standardized.
>
> Can you please rephrase the commit message ? It's really hard to
> understand. I believe such a patch will be needed for ehci as well,
> can you prepare one ?

I could not find any need for such check in ehci-hcd driver.

Sorry for this mess in commit message, I completely missed formatting
the statement
because of it got warped up in the message
Will send this message again with proper commit message.

>
>> Signed-off-by: Ted Chen 
>> ---
>> Resend this patch it some how got missed
>> Changes since v1: None.
>>
>> Tested on Odroid XU4: with Ethernet USB3.0 RT8153-VB
>> ---
>>  drivers/usb/host/xhci.c | 6 --
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>> index ca598aa..cb8a04b 100644
>> --- a/drivers/usb/host/xhci.c
>> +++ b/drivers/usb/host/xhci.c
>> @@ -941,10 +941,12 @@ static int _xhci_submit_control_msg(struct usb_device 
>> *udev, unsigned long pipe,
>>   if (usb_pipedevice(pipe) == ctrl->rootdev)
>>   return xhci_submit_root(udev, pipe, buffer, setup);
>>
>> - if (setup->request == USB_REQ_SET_ADDRESS)
>> + if (setup->request == USB_REQ_SET_ADDRESS &&
>> +(setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
>>   return xhci_address_device(udev, root_portnr);
>>
>> - if (setup->request == USB_REQ_SET_CONFIGURATION) {
>> + if (setup->request == USB_REQ_SET_CONFIGURATION &&
>> +(setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
>>   ret = xhci_set_configuration(udev);
>>   if (ret) {
>>   puts("Failed to configure xHCI endpoint\n");
>>
>
> What happens to the non-standard requests ?
>
Device will not able to detect leaving message
"scanning usb for ethernet devices... Non standard request in USB
vendor command"
> --
> Best regards,
> Marek Vasut

Here is the modified commit message

"Add a condition of set_address and set_configuration to check
if the requesttype is of standardized in the USB vendor request
so that usb device is detected"

Do you agree with this modified commit statement.

Best regards,
-Anand Moon
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Re: [U-Boot] [PATCH 3/3] OMAP3: am3517_evm: Misc. comment and option cleanup

2016-03-05 Thread Derald D. Woods

On Sat, Mar 05, 2016 at 12:44:51PM -0500, Tom Rini wrote:
> On Thu, Mar 03, 2016 at 10:14:16PM -0600, Derald D. Woods wrote:
> 
> > - Make comment 'one-liners' truly one line
> > - Drop some CFI verbage and definitions
> >   * NOR Support needs to be added with current conventions
> > 
> > Signed-off-by: Derald D. Woods 
> 
> Reviewed-by: Tom Rini 
> 
> ... and you could move most of 2/3 into here, aside from the parts
> strictly about UBI/UBIFS.

Okay. I will submit a version 2 with only two commits.

- Derald

> 
> -- 
> Tom


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Re: [U-Boot] [PATCH 1/3] OMAP3: am3517_evm: Use BCH8 ECC for NAND

2016-03-05 Thread Tom Rini

On Thu, Mar 03, 2016 at 10:14:14PM -0600, Derald D. Woods wrote:

> Select 8-bit BCH ecc-scheme with s/w based error correction
> - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
> 
> Signed-off-by: Derald D. Woods 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH V2 1/2] malloc: use hidden visibility

2016-03-05 Thread Tom Rini

On Sat, Mar 05, 2016 at 10:30:52AM -0700, Stephen Warren wrote:

> When running sandbox, the following phases occur, each with different
> malloc implementations or behaviors:
> 
> 1) Dynamic linker execution, using the dynamic linker's own malloc()
> implementation. This is fully functional.
> 
> 2) After U-Boot's malloc symbol has been hooked into the GOT, but before
> any U-Boot code has run. This phase is entirely non-functional, since
> U-Boot's gd symbol is NULL and U-Boot's initf_malloc() and
> mem_malloc_init() have not been called.
> 
> At least on Ubuntu Xenial, the dynamic linker does make both malloc() and
> free() calls during this phase. Currently these free() calls crash since
> they dereference gd, which is NULL.
> 
> U-Boot itself makes no use of malloc() during this phase.
> 
> 3) U-Boot execution after gd is set and initf_malloc() has been called.
> This is fully functional, albeit via a very simple malloc()
> implementation.
> 
> 4) U-Boot execution after mem_malloc_init() has been called. This is fully
> functional with a complete malloc() implementation.
> 
> Furthermore, if code that called malloc() during phase 1 calls free() in
> phase 3 or later, it is likely that heap corruption will occur, since
> U-Boot's malloc implementation will assume the pointer is part of its own
> heap, although it isn't. I have not actively observed this happening.
> 
> To prevent phase 2 from happening, this patch makes all of U-Boot's malloc
> library public symbols have hidden visibility. This prevents them from
> being hooked into the GOT, so only code in the U-Boot binary itself
> actually calls them; any other code will call into the standard C library
> malloc(). This also avoids the "furthermore" issue mentioned above.
> 
> I have seen references to this GCC pragma in blog posts from 2008, and
> RHEL5's ancient gcc appears to accept it fine, so I believe it's quite
> safe to use it without checking gcc version.
> 
> Cc: Rabin Vincent 
> Signed-off-by: Stephen Warren 

Reviewed-by: Tom Rini 

But have you tried with clang instead of gcc?  I suspect it's got code
to pretend to be gcc and do the right thing here but it's worth
confirming.

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Re: [U-Boot] [PULL] u-boot-usb/master

2016-03-05 Thread Tom Rini

On Sat, Mar 05, 2016 at 02:23:00AM +0100, Marek Vasut wrote:

> Hi,
> 
> two minor fixes for 2016.03 . Thanks!
> 
> The following changes since commit 50dc8677d769be6e2b34f49b6c43ad1e977bdc51:
> 
>   Merge git://git.denx.de/u-boot-usb (2016-02-26 18:08:43 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to b5ab663a6956e47180706b897bc9567335257d58:
> 
>   usb: dwc2: disable erroneous overcurrent condition (2016-03-05
> 02:21:36 +0100)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 3/3] OMAP3: am3517_evm: Misc. comment and option cleanup

2016-03-05 Thread Tom Rini

On Thu, Mar 03, 2016 at 10:14:16PM -0600, Derald D. Woods wrote:

> - Make comment 'one-liners' truly one line
> - Drop some CFI verbage and definitions
>   * NOR Support needs to be added with current conventions
> 
> Signed-off-by: Derald D. Woods 

Reviewed-by: Tom Rini 

... and you could move most of 2/3 into here, aside from the parts
strictly about UBI/UBIFS.

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Re: [U-Boot] [PATCH 2/3] OMAP3: am3517_evm: Replace JFFS2 with UBI/UBIFS on NAND

2016-03-05 Thread Tom Rini

On Thu, Mar 03, 2016 at 10:14:15PM -0600, Derald D. Woods wrote:

> Signed-off-by: Derald D. Woods 
> ---
>  configs/am3517_evm_defconfig |   2 +
>  include/configs/am3517_evm.h | 102 
> +++
>  2 files changed, 66 insertions(+), 38 deletions(-)
> 
> diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
> index cde84fe..c7699e0 100644
> --- a/configs/am3517_evm_defconfig
> +++ b/configs/am3517_evm_defconfig
> @@ -4,9 +4,11 @@ CONFIG_TARGET_AM3517_EVM=y
>  CONFIG_SPL=y
>  CONFIG_FIT=y
>  CONFIG_SYS_PROMPT="AM3517_EVM # "
> +CONFIG_SYS_EXTRA_OPTIONS="NAND"
>  # CONFIG_CMD_IMI is not set
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
>  # CONFIG_CMD_FPGA is not set
>  # CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_GPIO=y
>  CONFIG_SYS_NS16550=y
> diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
> index 98a59c5..734b8ba 100644
> --- a/include/configs/am3517_evm.h
> +++ b/include/configs/am3517_evm.h
> @@ -34,8 +34,8 @@
>  /*
>   * Display CPU and Board information
>   */
> -#define CONFIG_DISPLAY_CPUINFO   1
> -#define CONFIG_DISPLAY_BOARDINFO 1
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
>  
>  /* Clock Defines */
>  #define V_OSCK   2600/* Clock output from T2 
> */

There's lots of clean up here and stuff too.  Which is fine, but needs a
better commit log / subject.  Thanks!

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Re: [U-Boot] [PATCH V2 2/2] malloc: remove !gd handling

2016-03-05 Thread Tom Rini

On Sat, Mar 05, 2016 at 10:30:53AM -0700, Stephen Warren wrote:

> Following the previous patch, malloc() is never called before gd is set,
> so we can remove the special-case check for this condition.
> 
> This reverts commit 854d2b9753e4 "dlmalloc: ensure gd is set for early
> alloc".
> 
> Cc: Rabin Vincent 
> Signed-off-by: Stephen Warren 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH V5] ARM: Various: Future-proof serial platdata

2016-03-05 Thread Tom Rini

On Wed, Mar 02, 2016 at 05:38:18AM -0600, Adam Ford wrote:

> A few boards still use ns16550_platdata structures, but assume the structure
> is going to be in a specific order. By explicitly naming each entry,
> this should also help 'future-proof' in the event the structure changes.
> 
> Tested on the Logic PD Torpedo + Wireless.
> 
> I only changed a handful of devices that used the same syntax as the Logic
> board.  Appologies if I missed one or stepped on toes.  Thanks to Derald Woods
> and Alexander Graf.
> 
> Signed-off-by: Adam Ford 
> 
> V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c
> 
> V4: Fix subject heading
> 
> V3: Remove  reg_offset out in all the structs. It was reverted out, and and if
> it did exist, it would get initialized to 0 by default.
> 
> V2: I hastily copy-pasted the boards without looking at the UART number.
> This addresses 3 boards that use UART3 and not UART1.

Reviewed-by: Tom Rini 

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[U-Boot] [PATCH V2 2/2] malloc: remove !gd handling

2016-03-05 Thread Stephen Warren

Following the previous patch, malloc() is never called before gd is set,
so we can remove the special-case check for this condition.

This reverts commit 854d2b9753e4 "dlmalloc: ensure gd is set for early
alloc".

Cc: Rabin Vincent 
Signed-off-by: Stephen Warren 
---
 common/dlmalloc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 5ea37dfb6e4c..d66e80c647ce 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -2184,7 +2184,7 @@ Void_t* mALLOc(bytes) size_t bytes;
   INTERNAL_SIZE_T nb;
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
-   if (gd && !(gd->flags & GD_FLG_FULL_MALLOC_INIT))
+   if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return malloc_simple(bytes);
 #endif
 
-- 
2.7.0

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[U-Boot] [PATCH V2 1/2] malloc: use hidden visibility

2016-03-05 Thread Stephen Warren

When running sandbox, the following phases occur, each with different
malloc implementations or behaviors:

1) Dynamic linker execution, using the dynamic linker's own malloc()
implementation. This is fully functional.

2) After U-Boot's malloc symbol has been hooked into the GOT, but before
any U-Boot code has run. This phase is entirely non-functional, since
U-Boot's gd symbol is NULL and U-Boot's initf_malloc() and
mem_malloc_init() have not been called.

At least on Ubuntu Xenial, the dynamic linker does make both malloc() and
free() calls during this phase. Currently these free() calls crash since
they dereference gd, which is NULL.

U-Boot itself makes no use of malloc() during this phase.

3) U-Boot execution after gd is set and initf_malloc() has been called.
This is fully functional, albeit via a very simple malloc()
implementation.

4) U-Boot execution after mem_malloc_init() has been called. This is fully
functional with a complete malloc() implementation.

Furthermore, if code that called malloc() during phase 1 calls free() in
phase 3 or later, it is likely that heap corruption will occur, since
U-Boot's malloc implementation will assume the pointer is part of its own
heap, although it isn't. I have not actively observed this happening.

To prevent phase 2 from happening, this patch makes all of U-Boot's malloc
library public symbols have hidden visibility. This prevents them from
being hooked into the GOT, so only code in the U-Boot binary itself
actually calls them; any other code will call into the standard C library
malloc(). This also avoids the "furthermore" issue mentioned above.

I have seen references to this GCC pragma in blog posts from 2008, and
RHEL5's ancient gcc appears to accept it fine, so I believe it's quite
safe to use it without checking gcc version.

Cc: Rabin Vincent 
Signed-off-by: Stephen Warren 
---
v2: A whole different approach.
---
 include/malloc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/malloc.h b/include/malloc.h
index f20e4d3d2a6b..8175c75920cf 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -914,6 +914,7 @@ int initf_malloc(void);
 /* Simple versions which can be used when space is tight */
 void *malloc_simple(size_t size);
 
+#pragma GCC visibility push(hidden)
 # if __STD_C
 
 Void_t* mALLOc(size_t);
@@ -945,6 +946,7 @@ int mALLOPt();
 struct mallinfo mALLINFo();
 # endif
 #endif
+#pragma GCC visibility pop
 
 /*
  * Begin and End of memory area for malloc(), and current "brk"
-- 
2.7.0

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[U-Boot] [PATCH] rockchip: make configure_emmc() empty for Firefly-RK3288

2016-03-05 Thread FUKAUMI Naoki

on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for
Firefly-RK3288. (it's fine for Rock2)

$ gcc --version
gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

$ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin u-boot-spl-dtb.img
Warning: SPL image is too large (size 0x80d0) and will not boot

to reduce size of SPL image, this patch makes configure_emmc() empty for
Firefly-RK3288 as same as Rock2.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 6a54368..e133cca 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -114,7 +114,7 @@ static void configure_l2ctlr(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
-#ifndef CONFIG_TARGET_ROCK2
+#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288)
struct gpio_desc desc;
int ret;
 
-- 
2.7.2

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Re: [U-Boot] [U-BOOT.V2] usb: xhci: Fix vendor command error if the request

2016-03-05 Thread Marek Vasut

On 03/05/2016 09:43 AM, Anand Moon wrote:
> From: Ted Chen 
> 
> From: Ted Chen 
> 
> type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION.
> To: ma...@denx.de, swar...@nvidia.com, u-boot@lists.denx.de
> Cc: linux.am...@gmail.com, Ted Chen 
> 
> Add a condition of set_address and set_configuration to check
> if the request is standardized.

Can you please rephrase the commit message ? It's really hard to
understand. I believe such a patch will be needed for ehci as well,
can you prepare one ?

> Signed-off-by: Ted Chen 
> ---
> Resend this patch it some how got missed
> Changes since v1: None.
> 
> Tested on Odroid XU4: with Ethernet USB3.0 RT8153-VB
> ---
>  drivers/usb/host/xhci.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> index ca598aa..cb8a04b 100644
> --- a/drivers/usb/host/xhci.c
> +++ b/drivers/usb/host/xhci.c
> @@ -941,10 +941,12 @@ static int _xhci_submit_control_msg(struct usb_device 
> *udev, unsigned long pipe,
>   if (usb_pipedevice(pipe) == ctrl->rootdev)
>   return xhci_submit_root(udev, pipe, buffer, setup);
>  
> - if (setup->request == USB_REQ_SET_ADDRESS)
> + if (setup->request == USB_REQ_SET_ADDRESS &&
> +(setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
>   return xhci_address_device(udev, root_portnr);
>  
> - if (setup->request == USB_REQ_SET_CONFIGURATION) {
> + if (setup->request == USB_REQ_SET_CONFIGURATION &&
> +(setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
>   ret = xhci_set_configuration(udev);
>   if (ret) {
>   puts("Failed to configure xHCI endpoint\n");
> 

What happens to the non-standard requests ?

-- 
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Re: [U-Boot] Ethernet not found on Arria 5.

2016-03-05 Thread Marek Vasut

On 03/04/2016 01:53 PM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,

Hi,

>> It seems like your PHY is not recongnised. Could there be some
>> reset line which is left asserted ?
> 
> I'm afraid I don't know how to check that.
> 
> But I have previous version of U-Boot (2013) where Ethernet is
> working. Maybe I can check it there? I already tried to go that path,
> but code is quite different there.
> 
> With U-Boot 2013 it is enough to config fpga and set env variables to
> have ping in both directions.

What do you mean by this ? Is your ethernet controller synthesised in
the FPGA ? The arriaV socdk u-boot uses the top-side ethernet port,
which is connected to the ethernet controller in the HPS.

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[U-Boot] [PATCH 5/6] ARM: DRA7: configs: Prepare for detecting memory > 2GB

2016-03-05 Thread Lokesh Vutla

Enable configs that are required for detecting memory > 2GB.

Signed-off-by: Lokesh Vutla 
---
 include/configs/dra7xx_evm.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index e79250b..45bda4f 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -19,6 +19,11 @@
 #define CONFIG_IODELAY_RECALIBRATION
 #endif
 
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_PHYS_64BIT
+#define CONFIG_NR_DRAM_BANKS   2
+#define CONFIG_MAX_MEM_MAPPED  0x8000
+
 #ifndef CONFIG_QSPI_BOOT
 /* MMC ENV related defines */
 #define CONFIG_ENV_IS_IN_MMC
-- 
2.1.4

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[U-Boot] [PATCH 6/6] ARM: DRA7-evm: Update memory info in banks

2016-03-05 Thread Lokesh Vutla

Updating the memory banks properly so that DT is populated accordingly.
And updating this only after DDR is properly detected by eeprom, so that
git bisect is still maintained.

Acked-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
---
 board/ti/dra7xx/evm.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index d142ccc..4c6dfa0 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -268,6 +268,20 @@ int board_init(void)
return 0;
 }
 
+void dram_init_banksize(void)
+{
+   u64 ram_size;
+
+   ram_size = board_ti_get_emif_size();
+
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = get_effective_memsize();
+   if (ram_size > CONFIG_MAX_MEM_MAPPED) {
+   gd->bd->bi_dram[1].start = 0x2;
+   gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
+   }
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-- 
2.1.4

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[U-Boot] [PATCH 4/6] ARM: DRA7: EMIF: Add 4GB DDR settings

2016-03-05 Thread Lokesh Vutla

The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory
chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the
same.

Acked-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
---
 board/ti/dra7xx/evm.c | 83 +--
 1 file changed, 80 insertions(+), 3 deletions(-)

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index c493c64..d142ccc 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -34,6 +34,8 @@
 #define board_is_dra74x_evm()  board_ti_is("5777xCPU")
 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&   \
(strncmp("H", board_ti_get_rev(), 1) <= 0)
+#define board_ti_get_emif_size()   board_ti_get_emif1_size() + \
+   board_ti_get_emif2_size()
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include 
@@ -125,18 +127,78 @@ static const struct emif_regs 
emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.emif_rd_wr_exec_thresh = 0x0305
 };
 
+const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
+   .sdram_config_init  = 0x61851ab2,
+   .sdram_config   = 0x61851ab2,
+   .sdram_config2  = 0x0800,
+   .ref_ctrl   = 0x40F1,
+   .ref_ctrl_final = 0x1035,
+   .sdram_tim1 = 0xCCCF36B3,
+   .sdram_tim2 = 0x30BF7FDA,
+   .sdram_tim3 = 0x427F8BA8,
+   .read_idle_ctrl = 0x0005,
+   .zq_config  = 0x0007190B,
+   .temp_alert_config  = 0x,
+   .emif_ddr_phy_ctlr_1_init   = 0x0024400B,
+   .emif_ddr_phy_ctlr_1= 0x0E24400B,
+   .emif_ddr_ext_phy_ctrl_1= 0x10040100,
+   .emif_ddr_ext_phy_ctrl_2= 0x00910091,
+   .emif_ddr_ext_phy_ctrl_3= 0x00950095,
+   .emif_ddr_ext_phy_ctrl_4= 0x009B009B,
+   .emif_ddr_ext_phy_ctrl_5= 0x009E009E,
+   .emif_rd_wr_lvl_rmp_win = 0x,
+   .emif_rd_wr_lvl_rmp_ctl = 0x8000,
+   .emif_rd_wr_lvl_ctl = 0x,
+   .emif_rd_wr_exec_thresh = 0x0305
+};
+
+const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
+   .sdram_config_init  = 0x61851B32,
+   .sdram_config   = 0x61851B32,
+   .sdram_config2  = 0x0800,
+   .ref_ctrl   = 0x40F1,
+   .ref_ctrl_final = 0x1035,
+   .sdram_tim1 = 0xCCCF36B3,
+   .sdram_tim2 = 0x308F7FDA,
+   .sdram_tim3 = 0x427F88A8,
+   .read_idle_ctrl = 0x0005,
+   .zq_config  = 0x0007190B,
+   .temp_alert_config  = 0x,
+   .emif_ddr_phy_ctlr_1_init   = 0x0024400B,
+   .emif_ddr_phy_ctlr_1= 0x0E24400B,
+   .emif_ddr_ext_phy_ctrl_1= 0x10040100,
+   .emif_ddr_ext_phy_ctrl_2= 0x00910091,
+   .emif_ddr_ext_phy_ctrl_3= 0x00950095,
+   .emif_ddr_ext_phy_ctrl_4= 0x009B009B,
+   .emif_ddr_ext_phy_ctrl_5= 0x009E009E,
+   .emif_rd_wr_lvl_rmp_win = 0x,
+   .emif_rd_wr_lvl_rmp_ctl = 0x8000,
+   .emif_rd_wr_lvl_ctl = 0x,
+   .emif_rd_wr_exec_thresh = 0x0305
+};
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
+   u64 ram_size;
+
+   ram_size = board_ti_get_emif_size();
+
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
switch (emif_nr) {
case 1:
-   *regs = _ddr3_532_mhz_1cs;
+   if (ram_size > CONFIG_MAX_MEM_MAPPED)
+   *regs = _ddr3_532_mhz_1cs_2G;
+   else
+   *regs = _ddr3_532_mhz_1cs;
break;
case 2:
-   *regs = _ddr3_532_mhz_1cs;
+   if (ram_size > CONFIG_MAX_MEM_MAPPED)
+   *regs = _ddr3_532_mhz_1cs_2G;
+   else
+   *regs = _ddr3_532_mhz_1cs;
break;
}
break;
@@ -164,13 +226,28 @@ static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
.is_ma_present  = 0x1
 };
 
+const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
+   .dmm_lisa_map_0 = 0x0,
+   .dmm_lisa_map_1 = 0x0,
+   .dmm_lisa_map_2 = 0x80740300,
+   .dmm_lisa_map_3 = 0xFF020100,
+   .is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 {
+   u64

[U-Boot] [PATCH 3/6] ARM: DRA7: Move emif settings to board specific files

2016-03-05 Thread Lokesh Vutla

The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.

Acked-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/omap5/sdram.c | 149 +--
 board/ti/dra7xx/evm.c| 129 +
 2 files changed, 131 insertions(+), 147 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index c386e64..7dc5bb7 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -137,81 +137,6 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.emif_rd_wr_exec_thresh = 0x4305
 };
 
-const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
-   .sdram_config_init  = 0x61851ab2,
-   .sdram_config   = 0x61851ab2,
-   .sdram_config2  = 0x0800,
-   .ref_ctrl   = 0x40F1,
-   .ref_ctrl_final = 0x1035,
-   .sdram_tim1 = 0xCCCF36B3,
-   .sdram_tim2 = 0x308F7FDA,
-   .sdram_tim3 = 0x027F88A8,
-   .read_idle_ctrl = 0x0005,
-   .zq_config  = 0x0007190B,
-   .temp_alert_config  = 0x,
-   .emif_ddr_phy_ctlr_1_init   = 0x0024400B,
-   .emif_ddr_phy_ctlr_1= 0x0E24400B,
-   .emif_ddr_ext_phy_ctrl_1= 0x10040100,
-   .emif_ddr_ext_phy_ctrl_2= 0x00910091,
-   .emif_ddr_ext_phy_ctrl_3= 0x00950095,
-   .emif_ddr_ext_phy_ctrl_4= 0x009B009B,
-   .emif_ddr_ext_phy_ctrl_5= 0x009E009E,
-   .emif_rd_wr_lvl_rmp_win = 0x,
-   .emif_rd_wr_lvl_rmp_ctl = 0x8000,
-   .emif_rd_wr_lvl_ctl = 0x,
-   .emif_rd_wr_exec_thresh = 0x0305
-};
-
-const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
-   .sdram_config_init  = 0x61851B32,
-   .sdram_config   = 0x61851B32,
-   .sdram_config2  = 0x0800,
-   .ref_ctrl   = 0x40F1,
-   .ref_ctrl_final = 0x1035,
-   .sdram_tim1 = 0xCCCF36B3,
-   .sdram_tim2 = 0x308F7FDA,
-   .sdram_tim3 = 0x027F88A8,
-   .read_idle_ctrl = 0x0005,
-   .zq_config  = 0x0007190B,
-   .temp_alert_config  = 0x,
-   .emif_ddr_phy_ctlr_1_init   = 0x0024400B,
-   .emif_ddr_phy_ctlr_1= 0x0E24400B,
-   .emif_ddr_ext_phy_ctrl_1= 0x10040100,
-   .emif_ddr_ext_phy_ctrl_2= 0x00910091,
-   .emif_ddr_ext_phy_ctrl_3= 0x00950095,
-   .emif_ddr_ext_phy_ctrl_4= 0x009B009B,
-   .emif_ddr_ext_phy_ctrl_5= 0x009E009E,
-   .emif_rd_wr_lvl_rmp_win = 0x,
-   .emif_rd_wr_lvl_rmp_ctl = 0x8000,
-   .emif_rd_wr_lvl_ctl = 0x,
-   .emif_rd_wr_exec_thresh = 0x0305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
-   .sdram_config_init  = 0x61862B32,
-   .sdram_config   = 0x61862B32,
-   .sdram_config2  = 0x0800,
-   .ref_ctrl   = 0x514C,
-   .ref_ctrl_final = 0x144A,
-   .sdram_tim1 = 0xD113781C,
-   .sdram_tim2 = 0x305A7FDA,
-   .sdram_tim3 = 0x409F86A8,
-   .read_idle_ctrl = 0x0005,
-   .zq_config  = 0x5007190B,
-   .temp_alert_config  = 0x,
-   .emif_ddr_phy_ctlr_1_init   = 0x0024400D,
-   .emif_ddr_phy_ctlr_1= 0x0E24400D,
-   .emif_ddr_ext_phy_ctrl_1= 0x10040100,
-   .emif_ddr_ext_phy_ctrl_2= 0x00A400A4,
-   .emif_ddr_ext_phy_ctrl_3= 0x00A900A9,
-   .emif_ddr_ext_phy_ctrl_4= 0x00B000B0,
-   .emif_ddr_ext_phy_ctrl_5= 0x00B000B0,
-   .emif_rd_wr_lvl_rmp_win = 0x,
-   .emif_rd_wr_lvl_rmp_ctl = 0x8000,
-   .emif_rd_wr_lvl_ctl = 0x,
-   .emif_rd_wr_exec_thresh = 0x0305
-};
-
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
@@ -220,53 +145,6 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.is_ma_present  = 0x1
 };
 
-/*
- * DRA752 EVM board has 1.5 GB of memory
- * EMIF1 --> 2Gb * 2 =  512MB
- * EMIF2 --> 2Gb * 4 =  1GB
- * so mapping 1GB interleaved and 512MB non-interleaved
-

[U-Boot] [PATCH 2/6] ARM: DRA7: Enable EEPROM support

2016-03-05 Thread Lokesh Vutla

Enable EEPROM support for DRA74-evm.

Acked-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/omap5/Kconfig |  1 +
 board/ti/dra7xx/Kconfig  |  3 ++
 board/ti/dra7xx/evm.c| 59 +---
 include/configs/dra7xx_evm.h |  4 +++
 4 files changed, 63 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index f265b34..026bf24 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -12,6 +12,7 @@ config TARGET_OMAP5_UEVM
 
 config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
+   select TI_I2C_BOARD_DETECT
 
 config TARGET_BEAGLE_X15
bool "BeagleBoard X15"
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
index 80341d9..b642113 100644
--- a/board/ti/dra7xx/Kconfig
+++ b/board/ti/dra7xx/Kconfig
@@ -17,4 +17,7 @@ config CONS_INDEX
  The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it.
  Depending on your specific board you may want something other than 
UART1
  here.
+
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index eebec88..a47122b 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,6 +28,11 @@
 #include 
 
 #include "mux_data.h"
+#include "../common/board_detect.h"
+
+#define board_is_dra74x_evm()  board_ti_is("5777xCPU")
+#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&   \
+   (strncmp("H", board_ti_get_rev(), 1) <= 0)
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include 
@@ -37,8 +43,10 @@ DECLARE_GLOBAL_DATA_PTR;
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
+#define SYSINFO_BOARD_NAME_MAX_LEN 37
+
 const struct omap_sysinfo sysinfo = {
-   "Board: DRA7xx\n"
+   "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
 };
 
 /**
@@ -57,16 +65,59 @@ int board_init(void)
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-   if (omap_revision() == DRA722_ES1_0)
-   setenv("board_name", "dra72x");
+   char *name = "unknown";
+
+   if (is_dra72x())
+   name = "dra72x";
else
-   setenv("board_name", "dra7xx");
+   name = "dra7xx";
+
+   set_board_info_env(name);
 
omap_die_id_serial();
 #endif
return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void do_board_detect(void)
+{
+   int rc;
+
+   rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
+   CONFIG_EEPROM_CHIP_ADDRESS);
+   if (rc)
+   printf("ti_i2c_eeprom_init failed %d\n", rc);
+}
+
+#else
+
+void do_board_detect(void)
+{
+   char *bname = NULL;
+   int rc;
+
+   rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
+   CONFIG_EEPROM_CHIP_ADDRESS);
+   if (rc)
+   printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+   if (board_is_dra74x_evm()) {
+   bname = "DRA74x EVM";
+   /* If EEPROM is not populated */
+   } else {
+   if (is_dra72x())
+   bname = "DRA72x EVM";
+   else
+   bname = "DRA74x EVM";
+   }
+
+   if (bname)
+   snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
+"Board: %s REV %s\n", bname, board_ti_get_rev());
+}
+#endif /* CONFIG_SPL_BUILD */
+
 void set_muxconf_regs_essential(void)
 {
do_set_mux32((*ctrl)->control_padconf_core_base,
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0196280..e79250b 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -341,4 +341,8 @@
 #endif
 #endif  /* NOR support */
 
+/* EEPROM */
+#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
+#define CONFIG_EEPROM_BUS_ADDRESS 0
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
-- 
2.1.4

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[U-Boot] [PATCH 1/6] ti: common: dra7: Add standard access for board description EEPROM

2016-03-05 Thread Lokesh Vutla

DRA7 EVM revH and later EVMs have EEPROM populated that can contain board
description information such as name, revision, DDR definition, etc. Adding
support for this EEPROM format.

Acked-by: Nishanth Menon 
Signed-off-by: Lokesh Vutla 
---
 board/ti/common/board_detect.c | 64 ++
 board/ti/common/board_detect.h | 56 
 2 files changed, 120 insertions(+)

diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 6cf4859..e0ae1a5 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -160,6 +160,50 @@ already_read:
return 0;
 }
 
+int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
+{
+   int rc, offset = 0;
+   struct dra7_eeprom dra7_ep;
+   struct ti_common_eeprom *ep;
+
+   ep = TI_EEPROM_DATA;
+   if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
+   goto already_read;
+
+   /* Initialize with a known bad marker for i2c fails.. */
+   ep->header = 0xADEAD12C;
+   ep->name[0] = 0x0;
+   ep->version[0] = 0x0;
+   ep->serial[0] = 0x0;
+   ep->emif1_size = 0;
+   ep->emif2_size = 0;
+
+   rc = ti_i2c_eeprom_get(bus_addr, dev_addr, DRA7_EEPROM_HEADER_MAGIC,
+  sizeof(dra7_ep), (uint8_t *)_ep);
+   if (rc)
+   return rc;
+
+   ep->header = dra7_ep.header;
+   strlcpy(ep->name, dra7_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
+   ti_eeprom_string_cleanup(ep->name);
+
+   offset = dra7_ep.version_major - 1;
+
+   /* Rev F is skipped */
+   if (offset >= 5)
+   offset = offset + 1;
+   snprintf(ep->version, TI_EEPROM_HDR_REV_LEN + 1, "%c.%d",
+'A' + offset, dra7_ep.version_minor);
+   ti_eeprom_string_cleanup(ep->version);
+   ep->emif1_size = (u64)dra7_ep.emif1_size;
+   ep->emif2_size = (u64)dra7_ep.emif2_size;
+   strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
+   ti_eeprom_string_cleanup(ep->config);
+
+already_read:
+   return 0;
+}
+
 bool __maybe_unused board_ti_is(char *name_tag)
 {
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
@@ -230,6 +274,26 @@ fail:
memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN);
 }
 
+u64 __maybe_unused board_ti_get_emif1_size(void)
+{
+   struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+   if (ep->header != DRA7_EEPROM_HEADER_MAGIC)
+   return 0;
+
+   return ep->emif1_size;
+}
+
+u64 __maybe_unused board_ti_get_emif2_size(void)
+{
+   struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+   if (ep->header != DRA7_EEPROM_HEADER_MAGIC)
+   return 0;
+
+   return ep->emif2_size;
+}
+
 void __maybe_unused set_board_info_env(char *name)
 {
char *unknown = "unknown";
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index c17ab34..eb17f6f 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -44,6 +44,37 @@ struct ti_am_eeprom {
char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
 } __attribute__ ((__packed__));
 
+/* DRA7 EEPROM MAGIC Header identifier */
+#define DRA7_EEPROM_HEADER_MAGIC   0xAA5533EE
+#define DRA7_EEPROM_HDR_NAME_LEN   16
+#define DRA7_EEPROM_HDR_CONFIG_LEN 4
+
+/**
+ * struct dra7_eeprom - This structure holds data read in from the DRA7 EVM
+ * EEPROMs.
+ * @header: This holds the magic number
+ * @name: The name of the board
+ * @version_major: Board major version
+ * @version_minor: Board minor version
+ * @config: Board specific config options
+ * @emif1_size: Size of DDR attached to EMIF1
+ * @emif2_size: Size of DDR attached to EMIF2
+ *
+ * The data is this structure is read from the EEPROM on the board.
+ * It is used for board detection which is based on name. It is used
+ * to configure specific DRA7 boards. This allows booting of multiple
+ * DRA7 boards with a single MLO and u-boot.
+ */
+struct dra7_eeprom {
+   u32 header;
+   char name[DRA7_EEPROM_HDR_NAME_LEN];
+   u16 version_major;
+   u16 version_minor;
+   char config[DRA7_EEPROM_HDR_CONFIG_LEN];
+   u32 emif1_size;
+   u32 emif2_size;
+} __attribute__ ((__packed__));
+
 /**
  * struct ti_common_eeprom - Null terminated, usable EEPROM contents.
  * header: Magic number
@@ -52,6 +83,8 @@ struct ti_am_eeprom {
  * @serial:NULL terminated serial number
  * @config:NULL terminated Board specific config options
  * @mac_addr:  MAC addresses
+ * @emif1_size:Size of the ddr available on emif1
+ * @emif2_size:Size of the ddr available on emif2
  */
 struct ti_common_eeprom {
u32 header;
@@ -60,6 +93,8 @@ struct ti_common_eeprom {
char serial[TI_EEPROM_HDR_SERIAL_LEN + 1];
char config[TI_EEPROM_HDR_CONFIG_LEN + 1];
char

[U-Boot] [PATCH 0/6] ARM: DRA7: Add support for RevH evm

2016-03-05 Thread Lokesh Vutla

DRA74-evm RevH and later versions uses 4GB DDR and populates this info
in EEPROM. This series reads EEPROM and populates emif settings for 4GB ddr.
If eeprom is not available or evm revision is < H, then it fall backs to
default emif settings.

This series depends on the ti common eeprom driver series posted recently.
https://www.mail-archive.com/u-boot%40lists.denx.de/msg204549.html

Tested on
DRA7 RevH: http://pastebin.ubuntu.com/15291175/
DRA7 RevG: http://pastebin.ubuntu.com/15291197/

Lokesh Vutla (6):
  ti: common: dra7: Add standard access for board description EEPROM
  ARM: DRA7: Enable EEPROM support
  ARM: DRA7: Move emif settings to board specific files
  ARM: DRA7: EMIF: Add 4GB DDR settings
  ARM: DRA7: configs: Prepare for detecting memory > 2GB
  ARM: DRA7-evm: Update memory info in banks

 arch/arm/cpu/armv7/omap5/Kconfig |   1 +
 arch/arm/cpu/armv7/omap5/sdram.c | 149 +
 board/ti/common/board_detect.c   |  64 +
 board/ti/common/board_detect.h   |  56 
 board/ti/dra7xx/Kconfig  |   3 +
 board/ti/dra7xx/evm.c| 279 ++-
 include/configs/dra7xx_evm.h |   9 ++
 7 files changed, 410 insertions(+), 151 deletions(-)

-- 
2.1.4

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[U-Boot] [PATCH 4/4] ARM: DRA7: emif: Enable interleaving for higher address space

2016-03-05 Thread Lokesh Vutla

Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.

Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 2 ++
 arch/arm/include/asm/emif.h  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c 
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 3673884..697d6e0 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1329,6 +1329,8 @@ void dmm_init(u32 base)
_lisa_map_regs->dmm_lisa_map_1);
writel(lisa_map_regs->dmm_lisa_map_0,
_lisa_map_regs->dmm_lisa_map_0);
+
+   setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
}
 
/*
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index b03cf5a..3183130 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -545,6 +545,9 @@
 
 /* Memory Adapter */
 #define MA_BASE0x482AF040
+#define MA_PRIORITY0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT   8
+#define MA_HIMEM_INTERLEAVE_UN_MASK(1 << 8)
 
 /* DMM_LISA_MAP */
 #define EMIF_SYS_ADDR_SHIFT24
-- 
2.1.4

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[U-Boot] [PATCH] ARM: AM57xx: Update EMIF registers

2016-03-05 Thread Lokesh Vutla

There are certain EMIF timing failures seen on the some x15 boards. Updating
the EMIF settings to get rid of these timing failures.

Signed-off-by: Lokesh Vutla 
---
 board/ti/am57xx/board.c | 136 +++-
 1 file changed, 65 insertions(+), 71 deletions(-)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index d712ab0..9a8ee00 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -64,22 +64,22 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs 
**dmm_lisa_regs)
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init  = 0x61851b32,
.sdram_config   = 0x61851b32,
-   .sdram_config2  = 0x,
+   .sdram_config2  = 0x800,
.ref_ctrl   = 0x40F1,
.ref_ctrl_final = 0x1035,
-   .sdram_tim1 = 0xceef266b,
-   .sdram_tim2 = 0x328f7fda,
-   .sdram_tim3 = 0x027f88a8,
+   .sdram_tim1 = 0xcccf36ab,
+   .sdram_tim2 = 0x308f7fda,
+   .sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x0005,
-   .zq_config  = 0x0007190b,
+   .zq_config  = 0x5007190b,
.temp_alert_config  = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1= 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-   .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
-   .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
-   .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
-   .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+   .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+   .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+   .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+   .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x,
.emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
@@ -89,39 +89,35 @@ static const struct emif_regs 
beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 /* Ext phy ctrl regs 1-35 */
 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
-   0x00740074,
-   0x00780078,
-   0x007c007c,
-   0x007b007b,
-   0x00800080,
-   0x00360036,
+   0x00910091,
+   0x00950095,
+   0x009B009B,
+   0x009E009E,
+   0x00980098,
0x00340034,
-   0x00360036,
0x00350035,
-   0x00350035,
-
-   0x01ff01ff,
-   0x01ff01ff,
-   0x01ff01ff,
-   0x01ff01ff,
-   0x01ff01ff,
-
-   0x00430043,
-   0x003e003e,
-   0x004a004a,
-   0x00470047,
-   0x00400040,
-
+   0x00340034,
+   0x00310031,
+   0x00340034,
+   0x007F007F,
+   0x007F007F,
+   0x007F007F,
+   0x007F007F,
+   0x007F007F,
+   0x00480048,
+   0x004A004A,
+   0x00520052,
+   0x00550055,
+   0x00500050,
0x,
0x00600020,
0x40011080,
0x08102040,
-
-   0x00400040,
-   0x00400040,
-   0x00400040,
-   0x00400040,
-   0x00400040,
+   0x0,
+   0x0,
+   0x0,
+   0x0,
+   0x0,
0x0,
0x0,
0x0,
@@ -132,22 +128,22 @@ static const u32 
beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init  = 0x61851b32,
.sdram_config   = 0x61851b32,
-   .sdram_config2  = 0x,
+   .sdram_config2  = 0x800,
.ref_ctrl   = 0x40F1,
.ref_ctrl_final = 0x1035,
-   .sdram_tim1 = 0xceef266b,
-   .sdram_tim2 = 0x328f7fda,
-   .sdram_tim3 = 0x027f88a8,
+   .sdram_tim1 = 0xcccf36ab,
+   .sdram_tim2 = 0x308f7fda,
+   .sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x0005,
-   .zq_config  = 0x0007190b,
+   .zq_config  = 0x5007190b,
.temp_alert_config  = 0x,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1= 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-   .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
-   .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
-   .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
-   .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+   .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+   .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+   .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+   .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x,
.emif_rd_wr_lvl_rmp_ctl = 0x8000,
.emif_rd_wr_lvl_ctl = 0x,
@@ -156,37 +152,35 @@ static const struct emif_regs 
beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 
 static const u32

[U-Boot] [PATCH 3/4] ARM: DRA7: emif: Check for enable bits before updating leveling output

2016-03-05 Thread Lokesh Vutla

Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 38 
 arch/arm/cpu/armv7/omap5/sdram.c | 34 +++--
 arch/arm/include/asm/emif.h  |  6 +
 3 files changed, 54 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c 
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 6b33b45..3673884 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -250,33 +250,39 @@ static void update_hwleveling_output(u32 base, const 
struct emif_regs *regs)
 {
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
-   u32 reg, i;
+   u32 reg, i, phy;
 
emif_phy_status = (u32 *)>emif_ddr_phy_status[7];
+   phy = readl(>emif_ddr_phy_ctrl_1);
 
/* Update PHY_REG_RDDQS_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)>emif_ddr_ext_phy_ctrl_7;
-   for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
-   reg = readl(emif_phy_status++);
-   writel(reg, emif_ext_phy_ctrl_reg++);
-   writel(reg, emif_ext_phy_ctrl_reg++);
-   }
+   if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
+   for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+   reg = readl(emif_phy_status++);
+   writel(reg, emif_ext_phy_ctrl_reg++);
+   writel(reg, emif_ext_phy_ctrl_reg++);
+   }
 
/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)>emif_ddr_ext_phy_ctrl_2;
-   for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
-   reg = readl(emif_phy_status++);
-   writel(reg, emif_ext_phy_ctrl_reg++);
-   writel(reg, emif_ext_phy_ctrl_reg++);
-   }
+   emif_phy_status = (u32 *)>emif_ddr_phy_status[12];
+   if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
+   for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+   reg = readl(emif_phy_status++);
+   writel(reg, emif_ext_phy_ctrl_reg++);
+   writel(reg, emif_ext_phy_ctrl_reg++);
+   }
 
/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
emif_ext_phy_ctrl_reg = (u32 *)>emif_ddr_ext_phy_ctrl_12;
-   for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
-   reg = readl(emif_phy_status++);
-   writel(reg, emif_ext_phy_ctrl_reg++);
-   writel(reg, emif_ext_phy_ctrl_reg++);
-   }
+   emif_phy_status = (u32 *)>emif_ddr_phy_status[17];
+   if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
+   for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+   reg = readl(emif_phy_status++);
+   writel(reg, emif_ext_phy_ctrl_reg++);
+   writel(reg, emif_ext_phy_ctrl_reg++);
+   }
 
/* Disable Leveling */
writel(regs->emif_ddr_phy_ctlr_1, >emif_ddr_phy_ctrl_1);
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index a8d63c2..c386e64 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -643,11 +643,12 @@ static void do_ext_phy_settings_dra7(u32 base, const 
struct emif_regs *regs)
u32 *emif_ext_phy_ctrl_base = 0;
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
-   u32 i, hw_leveling, size;
+   u32 i, hw_leveling, size, phy;
 
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+   phy = regs->emif_ddr_phy_ctlr_1_init;
 
emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
 
@@ -657,18 +658,35 @@ static void do_ext_phy_settings_dra7(u32 base, const 
struct emif_regs *regs)
writel(ext_phy_ctrl_const_regs[0], _ext_phy_ctrl_base[0]);
writel(ext_phy_ctrl_const_regs[0], _ext_phy_ctrl_base[1]);
 
-   if (!hw_leveling) {
-   /*
-* Copy the predefined PHY register values
-* in case of sw leveling
-*/
-   for (i = 1; i < 25; i++) {
+   /*
+* Copy the predefined PHY register values
+* if leveling is disabled.
+*/
+   if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
+   for (i = 1; i < 6; i++) {
writel(ext_phy_ctrl_const_regs[i],
   _ext_phy_ctrl_base[i * 2]);
writel(ext_phy_ctrl_const_regs[i],
   _ext_phy_ctrl_base[i * 2 + 1]);
}

[U-Boot] [PATCH 2/4] ARM: DRA7: emif: Fix DDR init sequence during warm reset

2016-03-05 Thread Lokesh Vutla

Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.

Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c 
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 90c241a..6b33b45 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -327,8 +327,10 @@ static void dra7_ddr3_init(u32 base, const struct 
emif_regs *regs)
 {
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-   if (warm_reset())
+   if (warm_reset()) {
emif_reset_phy(base);
+   writel(0x0, >emif_pwr_mgmt_ctrl);
+   }
do_ext_phy_settings(base, regs);
 
writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
-- 
2.1.4

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[U-Boot] [PATCH 0/4] ARM: DRA7: emif: Miscellaneous bug fixes

2016-03-05 Thread Lokesh Vutla

This series fixes miscellaneous bugs for the emif driver. 

Lokesh Vutla (4):
  ARM: DRA7: emif: Fix updating of refresh ctrl shadow
  ARM: DRA7: emif: Fix DDR init sequence during warm reset
  ARM: DRA7: emif: Check for enable bits before updating leveling output
  ARM: DRA7: emif: Enable interleaving for higher address space

 arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++--
 arch/arm/cpu/armv7/omap5/sdram.c | 34 ++-
 arch/arm/include/asm/emif.h  |  9 +
 3 files changed, 67 insertions(+), 26 deletions(-)

-- 
2.1.4

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[U-Boot] [PATCH 1/4] ARM: DRA7: emif: Fix updating of refresh ctrl shadow

2016-03-05 Thread Lokesh Vutla

On DRA7, refresh ctrl shadow should be updated with
the final value.

Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c 
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index bf7bf26..90c241a 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -163,7 +163,11 @@ void emif_update_timings(u32 base, const struct emif_regs 
*regs)
 {
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-   writel(regs->ref_ctrl, >emif_sdram_ref_ctrl_shdw);
+   if (!is_dra7xx())
+   writel(regs->ref_ctrl, >emif_sdram_ref_ctrl_shdw);
+   else
+   writel(regs->ref_ctrl_final, >emif_sdram_ref_ctrl_shdw);
+
writel(regs->sdram_tim1, >emif_sdram_tim_1_shdw);
writel(regs->sdram_tim2, >emif_sdram_tim_2_shdw);
writel(regs->sdram_tim3, >emif_sdram_tim_3_shdw);
-- 
2.1.4

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Re: [U-Boot] [PATCH] dm: ti_qspi: Fix conversion of address to a pointer

2016-03-05 Thread Jagan Teki


On Saturday 05 March 2016 04:43 PM, Lokesh Vutla wrote:

TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is
not strictly correct, as it gives a build warning when fdt_addr_t is u64.
So, use map_physmem for a proper typecasts.

This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address
instead of a pointer for the uart base")

Signed-off-by: Lokesh Vutla 


Reviewed-by: Jagan Teki 

thanks!
--
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[U-Boot] [PATCH] dm: ti_qspi: Fix conversion of address to a pointer

2016-03-05 Thread Lokesh Vutla

TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is
not strictly correct, as it gives a build warning when fdt_addr_t is u64.
So, use map_physmem for a proper typecasts.

This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address
instead of a pointer for the uart base")

Signed-off-by: Lokesh Vutla 
---
 drivers/spi/ti_qspi.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 409a5c4..e69ec0d 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -534,11 +534,15 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
fdt_addr_t addr;
+   void *mmap;
 
-   priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
-   priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+   priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
+MAP_NOCACHE);
+   priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
+  MAP_NOCACHE);
addr = dev_get_addr_index(bus, 2);
-   priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+   mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
+   priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
-- 
2.1.4

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[U-Boot] [PATCH] dm: omap_timer: Fix conversion of address to a pointer

2016-03-05 Thread Lokesh Vutla

OMAP timer driver directly typecasts fdt_addr_t to a pointer. This is
not strictly correct, as it gives a build warning when fdt_addr_t is u64.
So, use map_physmem for a proper typecasts.

This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address
instead of a pointer for the uart base")

Signed-off-by: Lokesh Vutla 
---
 drivers/timer/omap-timer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index 3bb38c5..7422e0a 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -79,7 +79,8 @@ static int omap_timer_ofdata_to_platdata(struct udevice *dev)
 {
struct omap_timer_priv *priv = dev_get_priv(dev);
 
-   priv->regs = (struct omap_gptimer_regs *)dev_get_addr(dev);
+   priv->regs = map_physmem(dev_get_addr(dev),
+sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
 
return 0;
 }
-- 
2.1.4

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[U-Boot] exynos5: common: Enable CONFIG_USB_ETHER_RTL8152 ethernet support

2016-03-05 Thread Anand Moon

Enable CONFIG_USB_ETHER_RTL8152 support for Odroid XU4 which
has support for RTL8153-CG gigabit Ethernet adapter,
connected over USB 3.0.

commit 9dc8ba19c50fc0b1623c654bcfe6caa903a4c36c added support
for Realtek 8152/8153 driver.

Signed-off-by: Anand Moon 
---
Depends on:
https://patchwork.ozlabs.org/patch/548453/
---
 include/configs/exynos5-common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 834a22f..5a7915c 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -170,6 +170,7 @@
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RTL8152
 
 /* USB boot mode */
 #define CONFIG_USB_BOOTING
-- 
1.9.1

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[U-Boot] [U-BOOT.V2] usb: xhci: Fix vendor command error if the request

2016-03-05 Thread Anand Moon

From: Ted Chen 

From: Ted Chen 

type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION.
To: ma...@denx.de, swar...@nvidia.com, u-boot@lists.denx.de
Cc: linux.am...@gmail.com, Ted Chen 

Add a condition of set_address and set_configuration to check
if the request is standardized.

Signed-off-by: Ted Chen 
---
Resend this patch it some how got missed
Changes since v1: None.

Tested on Odroid XU4: with Ethernet USB3.0 RT8153-VB
---
 drivers/usb/host/xhci.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index ca598aa..cb8a04b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -941,10 +941,12 @@ static int _xhci_submit_control_msg(struct usb_device 
*udev, unsigned long pipe,
if (usb_pipedevice(pipe) == ctrl->rootdev)
return xhci_submit_root(udev, pipe, buffer, setup);
 
-   if (setup->request == USB_REQ_SET_ADDRESS)
+   if (setup->request == USB_REQ_SET_ADDRESS &&
+  (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
return xhci_address_device(udev, root_portnr);
 
-   if (setup->request == USB_REQ_SET_CONFIGURATION) {
+   if (setup->request == USB_REQ_SET_CONFIGURATION &&
+  (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
ret = xhci_set_configuration(udev);
if (ret) {
puts("Failed to configure xHCI endpoint\n");
-- 
1.9.1

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[U-Boot] [PATCH] MIPS: fix mips_cache fallback without __builtin_mips_cache

2016-03-05 Thread Matthias Schiffer

The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer 
Cc: Paul Burton 
Cc: Daniel Schwierzeck 
---

Hi,
I've noticed this when reading the code to understand how the cache
instruction is used. I'm not sure if this bug had any practical
consequences, or if nowadays all relevant compilers have
__builtin_mips_cache anyways.

Please keep me in Cc in follow-up mails, I'm not subscribed to the u-boot
ML.

Matthias

 arch/mips/include/asm/cacheops.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index a3b07c6..002b839 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -16,7 +16,7 @@ static inline void mips_cache(int op, const volatile void 
*addr)
 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
__builtin_mips_cache(op, addr);
 #else
-   __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
+   __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
 #endif
 }

-- 
2.7.2

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