Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Pali Rohár]

Hello! See few comments below.

On Wednesday 08 March 2023 13:48:31 Minda Chen wrote:
> From: Mason Huo 
> 
> Add pcie driver for StarFive JH7110, the driver depends on
> starfive gpio, pinctrl, clk and reset driver to do init.
> 
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
> 
> Signed-off-by: Mason Huo 
> Signed-off-by: Minda Chen 
> ---
>  drivers/pci/Kconfig|  11 +
>  drivers/pci/Makefile   |   1 +
>  drivers/pci/pcie_starfive_jh7110.c | 478 +
>  3 files changed, 490 insertions(+)
>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
> 
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index ef328d2652..e7b0ff5bc3 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
> Say Y here if you want to enable PCIe controller support on
> UniPhier SoCs.
>  
> +config PCIE_STARFIVE_JH7110
> + bool "Enable Starfive JH7110 PCIe driver"
> + depends on STARFIVE_JH7110
> + depends on PINCTRL_STARFIVE_JH7110
> + depends on CLK_JH7110
> + depends on RESET_JH7110
> + default y
> + help
> +   Say Y here if you want to enable PCIe controller support on
> +   StarFive JH7110 SoC.
> +
>  endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 49506e7ba5..bbe3323bb5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
> b/drivers/pci/pcie_starfive_jh7110.c
> new file mode 100644
> index 00..5ccef1ef02
> --- /dev/null
> +++ b/drivers/pci/pcie_starfive_jh7110.c
> @@ -0,0 +1,478 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * StarFive PLDA PCIe host controller driver
> + *
> + * Copyright (c) 2023 Starfive, Inc.
> + * Author: Mason Huo 
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GEN_SETTINGS 0x80
> +#define PCIE_PCI_IDS 0x9C
> +#define PCIE_WINROM  0xFC
> +#define PMSG_SUPPORT_RX  0x3F0
> +#define PCI_MISC 0xB4
> +
> +#define PLDA_EP_ENABLE   0
> +#define PLDA_RP_ENABLE   1
> +
> +#define IDS_REVISION_ID  0x02
> +#define IDS_PCI_TO_PCI_BRIDGE0x060400
> +#define IDS_CLASS_CODE_SHIFT 8

Please do not duplicate standard PCI macros and constants. In U-Boot
they are already available in include/pci_ids.h header file.

> +#define PREF_MEM_WIN_64_SUPPORT  BIT(3)
> +#define PMSG_LTR_SUPPORT BIT(2)
> +#define PLDA_FUNCTION_DISBIT(15)
> +#define PLDA_FUNC_NUM4
> +#define PLDA_PHY_FUNC_SHIFT  9
> +
> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> +#define XR3PCI_ATR_SRC_ADDR_LOW  0x0
> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> +#define XR3PCI_ATR_TRSL_ADDR_HIGH0xc
> +#define XR3PCI_ATR_TRSL_PARAM0x10
> +#define XR3PCI_ATR_TABLE_OFFSET  0x20
> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> +
> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT1
> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> +#define XR3PCI_ATR_TRSL_ADDR_MASKGENMASK(31, 12)
> +#define XR3_PCI_ECAM_SIZE28
> +#define XR3PCI_ATR_TRSL_DIR  BIT(22)
> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY0x0
> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG0x1
> +
> +#define ECAM_BUS_SHIFT   20
> +#define ECAM_DEV_SHIFT   15
> +#define ECAM_FUNC_SHIFT  12

Please do not implement duplicate PCIe ECAM code. U-Boot and also Linux
kernel already provides PCIE_ECAM_OFFSET() macro.

> +/* Secondary bus number offset in config space */
> +#define PCI_SECONDARY_BUS0x19

Unused.

> +
> +/* system control */
> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT8
> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> +#define STG_SYSCON_CLKREQ_MASK   BIT(22)
> +#define STG_SYSCON_CKREF_SRC_SHIFT   18
> +#define STG_SYSCON_CKREF_SRC_MASKGENMASK(19, 18)
> +
> +struct starfive_pcie {
> + struct udevice *dev;
> +
> + void __iomem *reg_base;
> + void __iomem

[PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 drivers/pci/Kconfig|  11 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_starfive_jh7110.c | 478 +
 3 files changed, 490 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..e7b0ff5bc3 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,15 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   depends on STARFIVE_JH7110
+   depends on PINCTRL_STARFIVE_JH7110
+   depends on CLK_JH7110
+   depends on RESET_JH7110
+   default y
+   help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c 
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..5ccef1ef02
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS   0x80
+#define PCIE_PCI_IDS   0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC   0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_REVISION_ID0x02
+#define IDS_PCI_TO_PCI_BRIDGE  0x060400
+#define IDS_CLASS_CODE_SHIFT   8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT   BIT(2)
+#define PLDA_FUNCTION_DIS  BIT(15)
+#define PLDA_FUNC_NUM  4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM   8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT  1
+#define XR3PCI_ATR_SRC_ADDR_MASK   GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK  GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE  28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG  0x1
+
+#define ECAM_BUS_SHIFT 20
+#define ECAM_DEV_SHIFT 15
+#define ECAM_FUNC_SHIFT12
+/* Secondary bus number offset in config space */
+#define PCI_SECONDARY_BUS  0x19
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK   BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK   GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT  8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK   GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK  GENMASK(19, 18)
+
+struct starfive_pcie {
+   struct udevice *dev;
+
+   void __iomem *reg_base;
+   void __iomem *cfg_base;
+
+   struct regmap *regmap;
+   u32 stg_arfun;
+   u32 stg_awfun;
+   u32 stg_rp_nep;
+
+   struct clk_bulk clks;
+   struct reset_ctl_bulk   rsts;
+
+   int atr_table_num;
+   int first_busno;
+};
+
+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+   if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+   return 0;
+   if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
+   return 0;
+
+   return 1;
+}
+
+static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
+{
+   unsi

[PATCH v2 2/3] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 550d0ff3ab..98d23d9461 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -50,8 +51,11 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,11 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v2 0/3] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.

[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230303032432.7837-1-yanhong.w...@starfivetech.com/

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/

changes
v1->v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 

---

The JH7110 minimal system patchset upstream is in progress.
PCIe driver patches is based on this patchset.

The JH7110 minimal system patchset details are listed in [1].

For more JH7110 and visionFive v2 information and support,
you can visit RVspace wiki[2].

[2] https://wiki.rvspace.org/

Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

 .../dts/jh7110-starfive-visionfive-2.dtsi |  99 
 arch/riscv/dts/jh7110.dtsi|  75 +++
 configs/starfive_visionfive2_defconfig|   9 +
 drivers/pci/Kconfig   |  11 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie_starfive_jh7110.c| 478 ++
 6 files changed, 673 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: b0eda49bc9b00503366f2ec431be0178caf9e9b5
prerequisite-patch-id: a84452ba131408ff842b65ae19a3a05f64b3ff60
prerequisite-patch-id: bb320a2102f46d2b2d08b4467cbcdb92050767b8
prerequisite-patch-id: ef5e9d61f7392c7d2e5321aa8a10996ca8eae5fc
prerequisite-patch-id: 26dfdb401d680ecd9449acf09131cf4790e987b7
prerequisite-patch-id: a0cfa5d8cdb49bbe9d4739afa90991f882950881
prerequisite-patch-id: a0509f01172e24b3d163f4701496b0349435bdc0
prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b
prerequisite-patch-id: aa95c1c047d0b7dae469586873a42932d613411d
prerequisite-patch-id: ebc26ed3f97f7babc0fc805152acb578f5eff922
prerequisite-patch-id: 81a83d6fc1e71ce190f9151577deb0c5cd382a20
prerequisite-patch-id: ff5bd799e4cb905fef6cf1cd0ce757980e1d34b7
prerequisite-patch-id: a341d4e8a8e25cb711309123939235fcb3c10c1a
prerequisite-patch-id: 749e4eafb431857ee2bec4ac8e78a682f6a57588
prerequisite-patch-id: 04cd7779c7464c7be683cd2718baee8c6554791d
prerequisite-patch-id: 25cb7c602018ec89abce43d8835926ac3356f5db
prerequisite-patch-id: cf1af96990b01e1025ec50d0b49c79f92f64f352
prerequisite-patch-id: cc5878da5f03e7e1d2c15e88537fd2a93bf47e53
-- 
2.17.1

[PATCH v2 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 99 +++
 arch/riscv/dts/jh7110.dtsi| 75 ++
 2 files changed, 174 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e669c2a26a..995f842a6b 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -178,6 +178,87 @@
slew-rate = <0>;
};
};
+
+   pcie0_perst_default: pcie0_perst_default {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie0_perst_active: pcie0_perst_active {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie0_wake_default: pcie0_wake_default {
+   wake-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie0_clkreq_default: pcie0_clkreq_default {
+   clkreq-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_perst_default: pcie1_perst_default {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_perst_active: pcie1_perst_active {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_wake_default: pcie1_wake_default {
+   wake-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_clkreq_default: pcie1_clkreq_default {
+   clkreq-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
 };
 
 &mmc0 {
@@ -234,6 +315,24 @@
};
 };
 
+&pcie0 {
+   pinctrl-names = "perst-default", "perst-active", "wake-default", 
"clkreq-default";
+   pinctrl-0 = <&pcie0_perst_default>;
+   pinctrl-1 = <&pcie0_perst_active>;
+   pinctrl-2 = <&pcie0_wake_default>;
+   pinctrl-3 = <&pcie0_clkreq_default>;
+   status = "disabled";
+};
+
+&pcie1 {
+   pinctrl-names = "perst-default", "perst-active", "wake-default", 
"clkreq-default";
+   pinctrl-0 = <&pcie1_perst_default>;
+   pinctrl-1 = <&pcie1_perst_active>;
+   pinctrl-2 = <&pcie1_wake_default>;
+   pinctrl-3 = <&pcie1_clkreq_default>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index d3e9f92987..e43296c9d5 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -578,5 +578,80 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2B00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2B00 0x0 0x100>,
+ <0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 

Re: [PATCH 2/3] phy: rockchip-inno-usb2: add initial support for rk3588 PHY

[Vasily Khoruzhick]

On Thu, Mar 2, 2023 at 11:32 PM Eugen Hristev
 wrote:
>
> Add initial support for the rk3588 PHY variant.
> The driver now looks for phy-supply and enables/disables the vbus
> accordingly.
> The lookup for the host-port reg inside the struct now does a do {} while()
> instead of a while() {} in order to allow a first check for reg == 0.
>
> Co-developed-by: Frank Wang 
> Signed-off-by: Frank Wang 
> Signed-off-by: Eugen Hristev 

Tested-by: Vasily Khoruzhick  # rk3568-based board

> ---
>  drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 109 +-
>  1 file changed, 104 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
> b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> index 55e1dbcfef7e..0551876436d5 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -13,6 +13,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -61,6 +62,7 @@ struct rockchip_usb2phy_cfg {
>  struct rockchip_usb2phy {
> void *reg_base;
> struct clk phyclk;
> +   struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
> const struct rockchip_usb2phy_cfg *phy_cfg;
>  };
>
> @@ -86,11 +88,34 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct 
> phy *phy)
> return &phy_cfg->port_cfgs[phy->id];
>  }
>
> +static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
> +{
> +   struct udevice *parent = phy->dev->parent;
> +   struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +   struct udevice *vbus = NULL;
> +
> +   if (phy->id == USB2PHY_PORT_HOST)
> +   vbus = priv->vbus_supply[USB2PHY_PORT_HOST];
> +
> +   return vbus;
> +}
> +
>  static int rockchip_usb2phy_power_on(struct phy *phy)
>  {
> struct udevice *parent = dev_get_parent(phy->dev);
> struct rockchip_usb2phy *priv = dev_get_priv(parent);
> const struct rockchip_usb2phy_port_cfg *port_cfg = 
> us2phy_get_port(phy);
> +   struct udevice *vbus = NULL;
> +   int ret;
> +
> +   vbus = rockchip_usb2phy_check_vbus(phy);
> +   if (vbus) {
> +   ret = regulator_set_enable(vbus, true);
> +   if (ret) {
> +   dev_err(phy->dev, "vbus enable failed: %d\n", ret);
> +   return ret;
> +   }
> +   }
>
> property_enable(priv->reg_base, &port_cfg->phy_sus, false);
>
> @@ -105,6 +130,17 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
> struct udevice *parent = dev_get_parent(phy->dev);
> struct rockchip_usb2phy *priv = dev_get_priv(parent);
> const struct rockchip_usb2phy_port_cfg *port_cfg = 
> us2phy_get_port(phy);
> +   struct udevice *vbus = NULL;
> +   int ret;
> +
> +   vbus = rockchip_usb2phy_check_vbus(phy);
> +   if (vbus) {
> +   ret = regulator_set_enable(vbus, false);
> +   if (ret) {
> +   dev_err(phy->dev, "vbus disable failed: %d\n", ret);
> +   return ret;
> +   }
> +   }
>
> property_enable(priv->reg_base, &port_cfg->phy_sus, true);
>
> @@ -149,13 +185,20 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy,
>  struct ofnode_phandle_args *args)
>  {
> const char *name = phy->dev->name;
> +   struct udevice *parent = phy->dev->parent;
> +   struct rockchip_usb2phy *priv = dev_get_priv(parent);
>
> -   if (!strcasecmp(name, "host-port"))
> +   if (!strcasecmp(name, "host-port")) {
> phy->id = USB2PHY_PORT_HOST;
> -   else if (!strcasecmp(name, "otg-port"))
> +   device_get_supply_regulator(phy->dev, "phy-supply",
> +   
> &priv->vbus_supply[USB2PHY_PORT_HOST]);
> +   } else if (!strcasecmp(name, "otg-port")) {
> phy->id = USB2PHY_PORT_OTG;
> -   else
> +   device_get_supply_regulator(phy->dev, "phy-supply",
> +   
> &priv->vbus_supply[USB2PHY_PORT_OTG]);
> +   } else {
> dev_err(phy->dev, "improper %s device\n", name);
> +   }
>
> return 0;
>  }
> @@ -201,14 +244,14 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
>
> /* find out a proper config which can be matched with dt. */
> index = 0;
> -   while (phy_cfgs[index].reg) {
> +   do {
> if (phy_cfgs[index].reg == reg) {
> priv->phy_cfg = &phy_cfgs[index];
> break;
> }
>
> ++index;
> -   }
> +   } while (phy_cfgs[index].reg);
>
> if (!priv->phy_cfg) {
> dev_err(dev, "failed find proper phy-cfg\n");
> @@ -348,6 +391,58 @@ static const struct rockchip_usb2phy_cfg 
> rk3568_phy_cfgs[] = {
> { /* sentinel */ }
>  };
>
> +stati

Re: [PATCH v2 3/3] Revert "arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates"

[Vasily Khoruzhick]

On Tue, Mar 7, 2023 at 4:48 PM Kever Yang  wrote:
>
> Hi Vasily,

Hi Kever,

>  Please use a new patch instead of a revert, I think I merge the
> patch twice by mistake, so there is another one need to remove.

Sure, I changed the patch subject and description in v3.

Regards,
Vasily

[PATCH v3 2/2] arm64:dts: rk356x-u-boot: do not drop combphy1 assigned-clocks/rates

[Vasily Khoruzhick]

We have stubs for CLK_PCIEPHY_REF now, so there is no reason to
modify the dtsi.

This essentialy reverts commit 5bec4b0de785
("arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates").

Signed-off-by: Vasily Khoruzhick 
---
v3: change patch subject and description from default revert commit to a
bit more verbose
v2: revert dropping assigned-clock properties because we have stubs for
CLK_PCIEPHY_REF clocks now

 arch/arm/dts/rk356x-u-boot.dtsi | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 2331641049..1709604b22 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -34,11 +34,6 @@
};
 };
 
-&combphy1 {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-rates;
-};
-
 &cru {
u-boot,dm-pre-reloc;
status = "okay";
-- 
2.39.2

[PATCH v3 1/2] clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks

[Vasily Khoruzhick]

Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Reviewed-by: Kever Yang 
Signed-off-by: Vasily Khoruzhick 
---
v3: add r-b tag from Kever
v2: implement stubs for CLK_PCIEPHY_REF instead of dropping
assigned-clock properties

 drivers/clk/rockchip/clk_rk3568.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 253b69504f..1c6adc56f9 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong 
rate)
case PCLK_PMU:
ret = rk3568_pmu_set_pmuclk(priv, rate);
break;
+   case CLK_PCIEPHY0_REF:
+   case CLK_PCIEPHY1_REF:
+   return 0;
default:
return -ENOENT;
}
-- 
2.39.2

[PATCH] dma: ti: k3-udma: Fix channel hang on teardown

[Vignesh Raghavendra]

Setting RX flow error handling will stall the channel until descriptors
are available to move RX data. Setting this bit causes issues when
tearing down ethernet DMA channel at the end of TFTP transfer as
unrelated network packets can cause teardown to stall indefinitely waiting
for driver to queue add more desc leading to channel hang with error
logs:
udma_stop_dev2mem TIMEOUT !
udma_stop_dev2mem: peer not stopped TIMEOUT !
udma_stop_dev2mem TIMEOUT !

Fix this by clearing rx_error_handling similar to how its done for UDMA
as part of udma_alloc_rchan_sci_req()

This fixes occasional TFTP Failures seen when downloading multiple files
one after the other on AM64/AM62 SoCs.

Fixes: 9a92851c33e8 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support")
Reported-by: Nishanth Menon 
Signed-off-by: Vignesh Raghavendra 
---
 drivers/dma/ti/k3-udma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index d92b96443694..05c3a4311ced 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -2150,7 +2150,7 @@ static int pktdma_tisci_rx_channel_config(struct 
udma_chan *uc)
flow_req.rx_psinfo_present = 1;
else
flow_req.rx_psinfo_present = 0;
-   flow_req.rx_error_handling = 1;
+   flow_req.rx_error_handling = 0;
 
ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
 
-- 
2.39.2

qemu_arm_defconfig with LTO fails due to unaligned access

[Heinrich Schuchardt]

Hello Ilias, hello Tom,

Tom tried to run qemu_arm_defconfig with CONFIG_LTO=y in gitlab. This
failed as shown in protocol
https://source.denx.de/u-boot/u-boot/-/jobs/589913/raw

Executing 'HII database protocols'
test_hii_database_new_package_list:
data abort
pc : [<7ff39b98>]  lr : [<7ff87328>]
reloc pc : [<0b98>]lr : [<0004e328>]
sp : 7edf8cc0  ip : 000c fp : 7ffe60ec
r10:   r9 : 7eef8eb0 r8 : 7ffe0d02
r7 :   r6 : 7ef0f8c8 r5 : 7ffe0cf0  r4 : 7ffe0cb4
r3 : 7ffe0cef  r2 :  r1 :   r0 : 
Flags: nzcv  IRQs off  FIQs off  Mode SVC_32
Code: e2403002 e3a0 e151 012fff1e (e1f320b2)
UEFI image [0x:0x] '/\selftest'
Resetting CPU ..

Debugging shows:

efi_hii_sibt_string_ucs2_block_next() calls u16_strnlen() for an
unaligned u16 string. Here "ldrh r2, [r3, #2]!" is executed for
unaligned r3. This should be allowable for SCTLR.A = 0.

When the crash occurs SCRLR has value 0xc5187f. SCTLR.A is bit 1 with
value 1.

The implementation of allow_unaligned() in
arch/arm/cpu/armv7 /sctlr.S should have set the flag to 0.
arch/arm/cpu/armv7/sctlr.S is compiled (as demonstrated by adding #error
to the code).

If I remove the weak implementation of allow_unaligned() in
lib/efi_loader/efi_setup.c, the error does not occur.

Shouldn't building with LTO ignore the weak implementation?

If I add a printf() statement to the weak implemenation, the printf()
command is not executed but

SCTLR 0xc5187d, SCTLR.A=0

The test passes as unaligned access is allowable.

I was building inside the Docker image with the GCC downloaded by
buildman (gcc-12.2.0-nolibc/arm-linux-gnueabi).

To me this looks like a compiler issue.

Best regards

Heinrich

Re: [PATCH v1] clk: nuvoton: add read only feature for clk driver

[Jim Liu]

Hi Sean

Thanks for your review.
This is a software flag not hardware reg.
It just protects the clock source and can't modify it in uboot.

Best regards,
Jim

On Tue, Mar 7, 2023 at 9:57 PM Sean Anderson  wrote:
>
> On 3/7/23 03:13, Jim Liu wrote:
> > Set ahb/apb/fiu clock divider as read-only
>
> Are these read-only in hardware, or is there some other reason?
>
> --Sean
>
> > Signed-off-by: Jim Liu 
> > ---
> >   drivers/clk/nuvoton/clk_npcm.c| 15 ---
> >   drivers/clk/nuvoton/clk_npcm.h|  1 +
> >   drivers/clk/nuvoton/clk_npcm8xx.c | 12 ++--
> >   3 files changed, 19 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c
> > index 8d71f2a24b..18cb9cddbf 100644
> > --- a/drivers/clk/nuvoton/clk_npcm.c
> > +++ b/drivers/clk/nuvoton/clk_npcm.c
> > @@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk)
> >   return div;
> >   }
> >
> > -static u32 npcm_clk_set_div(struct clk *clk, u32 div)
> > +static int npcm_clk_set_div(struct clk *clk, u32 div)
> >   {
> >   struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
> >   struct npcm_clk_div *divider;
> > @@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
> >   if (!divider)
> >   return -EINVAL;
> >
> > + if (divider->flags & DIV_RO)
> > + return 0;
> > +
> >   if (divider->flags & PRE_DIV2)
> >   div = div >> 1;
> >
> > @@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
> >   else
> >   clkdiv = ilog2(div);
> >
> > + if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) {
> > + printf("clkdiv(%d) for clk(%ld) is over limit\n",
> > +clkdiv, clk->id);
> > + return -EINVAL;
> > + }
> > +
> >   val = readl(priv->base + divider->reg);
> >   val &= ~divider->mask;
> >   val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
> > @@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong 
> > rate)
> >   if (ret)
> >   return ret;
> >
> > - debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, 
> > parent_rate, div);
> > - return (parent_rate / div);
> > + debug("%s: rate %lu, new rate %lu\n", __func__, rate, 
> > npcm_clk_get_rate(clk));
> > + return npcm_clk_get_rate(clk);
> >   }
> >
> >   static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)
> > diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h
> > index 06b60dc8b8..b4726d8381 100644
> > --- a/drivers/clk/nuvoton/clk_npcm.h
> > +++ b/drivers/clk/nuvoton/clk_npcm.h
> > @@ -50,6 +50,7 @@
> >   #define PRE_DIV2BIT(2)  /* Pre divisor = 2 */
> >   #define POST_DIV2   BIT(3)  /* Post divisor = 2 */
> >   #define FIXED_PARENTBIT(4)  /* clock source is fixed */
> > +#define DIV_RO   BIT(5)  /* divider is read-only */
> >
> >   /* Parameters of PLL configuration */
> >   struct npcm_clk_pll {
> > diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c 
> > b/drivers/clk/nuvoton/clk_npcm8xx.c
> > index 27e3cfcf55..d1b32e3237 100644
> > --- a/drivers/clk/nuvoton/clk_npcm8xx.c
> > +++ b/drivers/clk/nuvoton/clk_npcm8xx.c
> > @@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = 
> > {
> >   };
> >
> >   static struct npcm_clk_div npcm8xx_clk_dividers[] = {
> > - {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2},
> > - {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2},
> > - {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2},
> > - {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1},
> > - {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1},
> > - {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1},
> > + {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO},
> > + {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO},
> > + {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO},
> > + {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO},
> > + {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO},
> > + {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO},
> >   {NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
> >   {NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
> >   {NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1},
>

Re: [PATCH v2 1/3] phy: rockchip-inno-usb2: add support for phy-supply

[Vasily Khoruzhick]

On Tue, Mar 7, 2023 at 4:52 PM Kever Yang  wrote:
>
> Hi Vasily,

Hi Keven,

>  This patch is cover by patch[1] from Eugen, right?

Yeah, I didn't notice Eugen's patch. Anyway, he sent his patch
earlier, so please discard mine.

Regards,
Vasily

Re: [RFC PATCH v3 5/9] ram: cadence: add driver for Cadence EDAC

[Ralph Siemsen]

On Fri, Feb 24, 2023 at 10:19:53AM -0500, Ralph Siemsen wrote:

Hi Bryan,

On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof  wrote:


Hi Ralph!
Love seeing more boards here, though I know of a few chips that use some
type of cadence controller. I'm just curious if it would it make sense
to name this with some type of Renesas specific branding?


Indeed the this IP from Cadence likely is used in quite a few places.
However it is usually quite difficult to figure out exactly which
version of the IP is present, what bugs/workarounds are needed, etc.

I am fine with renaming this in a more renesas-specific manner
(suggestions welcomed!). On the other hand, it would good to try and
encourage having one driver for this, rather than a bunch of
similar-but-not-quite-equivalent ones scattered about. Perhaps a
non-specific name might help?


Can anyone offer guidance on the naming of the DDR controller? Other 
than this issue, I have v4 of this patch series ready to post.


Thanks!
Ralph

Re: [PATCH v2 1/3] phy: rockchip-inno-usb2: add support for phy-supply

[Kever Yang]

Hi Vasily,

    This patch is cover by patch[1] from Eugen, right?

Thanks,

- Kever

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20230303073134.282462-2-eugen.hris...@collabora.com/


On 2023/3/8 06:08, Vasily Khoruzhick wrote:

PHY driver needs to enable PHY supply, otherwise port will
remain unpowered.

Signed-off-by: Vasily Khoruzhick 
---
v2: address check_patch.pl issues

  drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 64 ++-
  1 file changed, 61 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 55e1dbcfef..a859cd6f18 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -19,6 +19,7 @@
  #include 
  #include 
  #include 
+#include 
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@ -62,6 +63,10 @@ struct rockchip_usb2phy {

void *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   struct udevice *host_supply;
+   struct udevice *otg_supply;
+#endif
  };
  
  static inline int property_enable(void *reg_base,

@@ -86,12 +91,42 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct 
phy *phy)
return &phy_cfg->port_cfgs[phy->id];
  }
  
+#if IS_ENABLED(CONFIG_DM_REGULATOR)

+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+   struct udevice *supply;
+   int ret = 0;
+
+   if (phy->id == USB2PHY_PORT_HOST)
+   supply = priv->host_supply;
+   else
+   supply = priv->otg_supply;
+
+   if (supply)
+   ret = regulator_set_enable(supply, enable);
+
+   return ret;
+}
+#else
+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   return 0;
+}
+#endif
+
  static int rockchip_usb2phy_power_on(struct phy *phy)
  {
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
  
+	int ret = rockchip_usb2phy_regulator_set_enable(phy, true);

+
+   if (ret)
+   return ret;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
  
  	/* waiting for the utmi_clk to become stable */

@@ -108,6 +143,11 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
  
  	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
  
+	int ret = rockchip_usb2phy_regulator_set_enable(phy, false);

+
+   if (ret)
+   return ret;
+
return 0;
  }
  
@@ -149,13 +189,31 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy,

 struct ofnode_phandle_args *args)
  {
const char *name = phy->dev->name;
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   struct udevice *supply;
+   int ret = device_get_supply_regulator(phy->dev, "phy-supply", &supply);
+
+   if (ret && ret != -ENOENT) {
+   pr_err("Failed to get PHY regulator\n");
+   return ret;
+   }
+#endif
  
-	if (!strcasecmp(name, "host-port"))

+   if (!strcasecmp(name, "host-port")) {
phy->id = USB2PHY_PORT_HOST;
-   else if (!strcasecmp(name, "otg-port"))
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   priv->host_supply = supply;
+#endif
+   } else if (!strcasecmp(name, "otg-port")) {
phy->id = USB2PHY_PORT_OTG;
-   else
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   priv->otg_supply = supply;
+#endif
+   } else {
dev_err(phy->dev, "improper %s device\n", name);
+   }
  
  	return 0;

  }

Re: [PATCH 3/3] configs: rockchip: rock5b-rk3588: enable USB and regulators

[Kever Yang]

On 2023/3/3 15:31, Eugen Hristev wrote:

Enable USB command, USB drivers, PHY and regulators, for USB host
operations.

Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
  configs/rock5b-rk3588_defconfig | 18 +-
  1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 66199387195a..ed63db1e297b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -41,12 +41,13 @@ CONFIG_SPL_STACK_R=y
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPT=y
  CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
  # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
  # CONFIG_SPL_DOS_PARTITION is not set
  CONFIG_SPL_OF_CONTROL=y
  CONFIG_OF_LIVE=y
  CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent 
assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_NET_RANDOM_ETHADDR=y
  CONFIG_SPL_REGMAP=y
  CONFIG_SPL_SYSCON=y
  CONFIG_SPL_CLK=y
@@ -61,11 +62,26 @@ CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
  CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
  CONFIG_PWM_ROCKCHIP=y
  CONFIG_SPL_RAM=y
  CONFIG_BAUDRATE=150
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_DEBUG_UART_ANNOUNCE=y
  CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
  CONFIG_ERRNO_STR=y

Re: [PATCH 2/3] phy: rockchip-inno-usb2: add initial support for rk3588 PHY

[Kever Yang]

On 2023/3/3 15:31, Eugen Hristev wrote:

Add initial support for the rk3588 PHY variant.
The driver now looks for phy-supply and enables/disables the vbus
accordingly.
The lookup for the host-port reg inside the struct now does a do {} while()
instead of a while() {} in order to allow a first check for reg == 0.

Co-developed-by: Frank Wang 
Signed-off-by: Frank Wang 
Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
  drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 109 +-
  1 file changed, 104 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 55e1dbcfef7e..0551876436d5 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -13,6 +13,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -61,6 +62,7 @@ struct rockchip_usb2phy_cfg {
  struct rockchip_usb2phy {
void *reg_base;
struct clk phyclk;
+   struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
const struct rockchip_usb2phy_cfg *phy_cfg;
  };
  
@@ -86,11 +88,34 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)

return &phy_cfg->port_cfgs[phy->id];
  }
  
+static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)

+{
+   struct udevice *parent = phy->dev->parent;
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+   struct udevice *vbus = NULL;
+
+   if (phy->id == USB2PHY_PORT_HOST)
+   vbus = priv->vbus_supply[USB2PHY_PORT_HOST];
+
+   return vbus;
+}
+
  static int rockchip_usb2phy_power_on(struct phy *phy)
  {
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+   struct udevice *vbus = NULL;
+   int ret;
+
+   vbus = rockchip_usb2phy_check_vbus(phy);
+   if (vbus) {
+   ret = regulator_set_enable(vbus, true);
+   if (ret) {
+   dev_err(phy->dev, "vbus enable failed: %d\n", ret);
+   return ret;
+   }
+   }
  
  	property_enable(priv->reg_base, &port_cfg->phy_sus, false);
  
@@ -105,6 +130,17 @@ static int rockchip_usb2phy_power_off(struct phy *phy)

struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+   struct udevice *vbus = NULL;
+   int ret;
+
+   vbus = rockchip_usb2phy_check_vbus(phy);
+   if (vbus) {
+   ret = regulator_set_enable(vbus, false);
+   if (ret) {
+   dev_err(phy->dev, "vbus disable failed: %d\n", ret);
+   return ret;
+   }
+   }
  
  	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
  
@@ -149,13 +185,20 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy,

 struct ofnode_phandle_args *args)
  {
const char *name = phy->dev->name;
+   struct udevice *parent = phy->dev->parent;
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
  
-	if (!strcasecmp(name, "host-port"))

+   if (!strcasecmp(name, "host-port")) {
phy->id = USB2PHY_PORT_HOST;
-   else if (!strcasecmp(name, "otg-port"))
+   device_get_supply_regulator(phy->dev, "phy-supply",
+   
&priv->vbus_supply[USB2PHY_PORT_HOST]);
+   } else if (!strcasecmp(name, "otg-port")) {
phy->id = USB2PHY_PORT_OTG;
-   else
+   device_get_supply_regulator(phy->dev, "phy-supply",
+   
&priv->vbus_supply[USB2PHY_PORT_OTG]);
+   } else {
dev_err(phy->dev, "improper %s device\n", name);
+   }
  
  	return 0;

  }
@@ -201,14 +244,14 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
  
  	/* find out a proper config which can be matched with dt. */

index = 0;
-   while (phy_cfgs[index].reg) {
+   do {
if (phy_cfgs[index].reg == reg) {
priv->phy_cfg = &phy_cfgs[index];
break;
}
  
  		++index;

-   }
+   } while (phy_cfgs[index].reg);
  
  	if (!priv->phy_cfg) {

dev_err(dev, "failed find proper phy-cfg\n");
@@ -348,6 +391,58 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] 
= {
{ /* sentinel */ }
  };
  
+static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {

+   {
+   .reg= 0x,
+   .port_cfgs  = {
+   [USB2PHY_PORT_OTG] = {
+   .phy_sus= { 0x000c, 11, 11, 0, 1 },
+  

Re: [PATCH 1/3] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host

[Kever Yang]

On 2023/3/3 15:31, Eugen Hristev wrote:

Add USB 2.0 host nodes and PHYs.

Co-developed-by: William Wu 
Signed-off-by: William Wu 
Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169 
  1 file changed, 169 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 2386edf90deb..e1d240baf35d 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -4,6 +4,9 @@
   */
  
  #include "rk3588-u-boot.dtsi"

+#include 
+#include 
+#include 
  
  / {

aliases {
@@ -13,6 +16,105 @@
chosen {
u-boot,spl-boot-order = &sdmmc;
};
+
+   vcc5v0_host: vcc5v0-host-regulator {
+   u-boot,dm-pre-reloc;
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_host";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   enable-active-high;
+   gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&vcc5v0_host_en>;
+   vin-supply = <&vcc5v0_sys>;
+   };
+
+   usb_host0_ehci: usb@fc80 {
+   compatible = "generic-ehci";
+   reg = <0x0 0xfc80 0x0 0x4>;
+   interrupts = ;
+   clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
+   clock-names = "usbhost", "arbiter";
+   power-domains = <&power RK3588_PD_USB>;
+   status = "disabled";
+   };
+
+   usb_host0_ohci: usb@fc84 {
+   compatible = "generic-ohci";
+   reg = <0x0 0xfc84 0x0 0x4>;
+   interrupts = ;
+   clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
+   clock-names = "usbhost", "arbiter";
+   power-domains = <&power RK3588_PD_USB>;
+   status = "disabled";
+   };
+
+   usb_host1_ehci: usb@fc88 {
+   compatible = "generic-ehci";
+   reg = <0x0 0xfc88 0x0 0x4>;
+   interrupts = ;
+   clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
+   clock-names = "usbhost", "arbiter";
+   power-domains = <&power RK3588_PD_USB>;
+   status = "disabled";
+   };
+
+   usb_host1_ohci: usb@fc8c {
+   compatible = "generic-ohci";
+   reg = <0x0 0xfc8c 0x0 0x4>;
+   interrupts = ;
+   clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
+   clock-names = "usbhost", "arbiter";
+   power-domains = <&power RK3588_PD_USB>;
+   status = "disabled";
+   };
+
+   usb2phy2_grf: syscon@fd5d8000 {
+   compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+"simple-mfd";
+   reg = <0x0 0xfd5d8000 0x0 0x4000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   u2phy2: usb2-phy@8000 {
+   compatible = "rockchip,rk3588-usb2phy";
+   reg = <0x8000 0x10>;
+   interrupts = ;
+   clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+   clock-names = "phyclk";
+   #clock-cells = <0>;
+   status = "disabled";
+
+   u2phy2_host: host-port {
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+   };
+   };
+
+   usb2phy3_grf: syscon@fd5dc000 {
+   compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+"simple-mfd";
+   reg = <0x0 0xfd5dc000 0x0 0x4000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   u2phy3: usb2-phy@c000 {
+   compatible = "rockchip,rk3588-usb2phy";
+   reg = <0xc000 0x10>;
+   interrupts = ;
+   clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+   clock-names = "phyclk";
+   #clock-cells = <0>;
+   status = "disabled";
+
+   u2phy3_host: host-port {
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+   };
+   };
  };
  
  &sdmmc {

@@ -20,3 +122,70 @@
u-boot,dm-spl;
status = "okay";
  };
+
+&pinctrl {
+   usb {
+   vcc5v0_host_en: vcc5v0-host-en {
+   rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+   };
+};
+
+&usb_host0_ehci {
+   companion = <&usb_host0_ohci>;
+   phys = <&u2phy2_ho

Re: [PATCH v2 3/3] Revert "arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates"

[Kever Yang]

Hi Vasily,

    Please use a new patch instead of a revert, I think I merge the 
patch twice by mistake, so there is another one need to remove.



Thanks,

- Kever

On 2023/3/8 06:08, Vasily Khoruzhick wrote:

This reverts commit 5bec4b0de7851a254fb4447b3599a60f95550141.

Signed-off-by: Vasily Khoruzhick 
---
v2: revert dropping assigned-clock properties because we have stubs for
CLK_PCIEPHY_REF clocks now

  arch/arm/dts/rk356x-u-boot.dtsi | 5 -
  1 file changed, 5 deletions(-)

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 2331641049..1709604b22 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -34,11 +34,6 @@
};
  };
  
-&combphy1 {

-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-rates;
-};
-
  &cru {
u-boot,dm-pre-reloc;
status = "okay";

Re: [PATCH v2 2/3] clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks

[Kever Yang]

On 2023/3/8 06:08, Vasily Khoruzhick wrote:

Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Signed-off-by: Vasily Khoruzhick 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
v2: implement stubs for CLK_PCIEPHY_REF instead of dropping
assigned-clock properties

  drivers/clk/rockchip/clk_rk3568.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 253b69504f..1c6adc56f9 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong 
rate)
case PCLK_PMU:
ret = rk3568_pmu_set_pmuclk(priv, rate);
break;
+   case CLK_PCIEPHY0_REF:
+   case CLK_PCIEPHY1_REF:
+   return 0;
default:
return -ENOENT;
}

Re: [PATCH v2 1/3] phy: rockchip-inno-usb2: add support for phy-supply

[Kever Yang]

On 2023/3/8 06:08, Vasily Khoruzhick wrote:

PHY driver needs to enable PHY supply, otherwise port will
remain unpowered.

Signed-off-by: Vasily Khoruzhick 



Reviewed-by: Kever Yang 


Thanks,
- Kever

---
v2: address check_patch.pl issues

  drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 64 ++-
  1 file changed, 61 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 55e1dbcfef..a859cd6f18 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -19,6 +19,7 @@
  #include 
  #include 
  #include 
+#include 
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@ -62,6 +63,10 @@ struct rockchip_usb2phy {

void *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   struct udevice *host_supply;
+   struct udevice *otg_supply;
+#endif
  };
  
  static inline int property_enable(void *reg_base,

@@ -86,12 +91,42 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct 
phy *phy)
return &phy_cfg->port_cfgs[phy->id];
  }
  
+#if IS_ENABLED(CONFIG_DM_REGULATOR)

+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+   struct udevice *supply;
+   int ret = 0;
+
+   if (phy->id == USB2PHY_PORT_HOST)
+   supply = priv->host_supply;
+   else
+   supply = priv->otg_supply;
+
+   if (supply)
+   ret = regulator_set_enable(supply, enable);
+
+   return ret;
+}
+#else
+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   return 0;
+}
+#endif
+
  static int rockchip_usb2phy_power_on(struct phy *phy)
  {
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
  
+	int ret = rockchip_usb2phy_regulator_set_enable(phy, true);

+
+   if (ret)
+   return ret;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
  
  	/* waiting for the utmi_clk to become stable */

@@ -108,6 +143,11 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
  
  	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
  
+	int ret = rockchip_usb2phy_regulator_set_enable(phy, false);

+
+   if (ret)
+   return ret;
+
return 0;
  }
  
@@ -149,13 +189,31 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy,

 struct ofnode_phandle_args *args)
  {
const char *name = phy->dev->name;
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   struct udevice *supply;
+   int ret = device_get_supply_regulator(phy->dev, "phy-supply", &supply);
+
+   if (ret && ret != -ENOENT) {
+   pr_err("Failed to get PHY regulator\n");
+   return ret;
+   }
+#endif
  
-	if (!strcasecmp(name, "host-port"))

+   if (!strcasecmp(name, "host-port")) {
phy->id = USB2PHY_PORT_HOST;
-   else if (!strcasecmp(name, "otg-port"))
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   priv->host_supply = supply;
+#endif
+   } else if (!strcasecmp(name, "otg-port")) {
phy->id = USB2PHY_PORT_OTG;
-   else
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   priv->otg_supply = supply;
+#endif
+   } else {
dev_err(phy->dev, "improper %s device\n", name);
+   }
  
  	return 0;

  }

Re: [PATCH 2/2] arm64: dts: rk3568-u-boot: Drop combphy0 assigned-clocks/rates

[Kever Yang]

Hi Vasily,

On 2023/3/8 05:34, Vasily Khoruzhick wrote:

On Tue, Mar 7, 2023 at 1:04 PM Mark Kettenis  wrote:


And implement support for the CLK_PCIEPHYn_REF clocks in
drivers/clk/rockchip/clk_rk3568.c:rk3568_pmuclk_set_rate()?

Yes, I'd say so.

If U-Boot doesn't actually need these clocks to run at the frequency
provided by assigned-clock-rates, that could be as simple as returning
0 for these clocks.

Sounds good. I'll send v2 that reverts 5bec4b0de785 and implements
stubs for CLK_PCIEPHYn_REF clocks.

FWIW, I tried booting linux-6.2.2 with u-boot dtb and these clocks
dropped, and USB works just fine.


The assigned-clock is a software set default value, the hardware can 
works fine because


these clocks have a correct default hardware value.

So for the PHY,  it works in U-Boot without assigned clock in most case.

Returing 0 for those clocks is also OK.


Thanks,

- Kever




commit 5bec4b0de785 ("arm64: dts: rk356x-u-boot: Drop combphy1 
assigned-clocks/rates")
dropped these properties for combphy1, so let's drop them for combphy0 as well.

Signed-off-by: Vasily Khoruzhick 
---
  arch/arm/dts/rk3568-evb-u-boot.dtsi |  1 +
  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  1 +
  arch/arm/dts/rk3568-u-boot.dtsi | 11 +++
  3 files changed, 13 insertions(+)
  create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi

diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi 
b/arch/arm/dts/rk3568-evb-u-boot.dtsi
index 17503d3d27..77430da3ba 100644
--- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
@@ -4,6 +4,7 @@
   */

  #include "rk356x-u-boot.dtsi"
+#include "rk3568-u-boot.dtsi"

  / {
   chosen {
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index ed47efa44b..44cf33ed4b 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -5,6 +5,7 @@
   */

  #include "rk356x-u-boot.dtsi"
+#include "rk3568-u-boot.dtsi"

  / {
   chosen {
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
new file mode 100644
index 00..c677df
--- /dev/null
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Vasily Khoruzhick 
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+&combphy0 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+};
--
2.39.2

[PATCH 3/3] test: Add test for new command pci_mps

[stcarlso]

From: Stephen Carlson 

Adds a test for the new pci_mps command to ensure that it can set the
Maximum Payload Size (MPS) of all devices to 256 bytes in the sandbox
environment. Enables the pci_mps command in the sandbox environment so
that this test can be run.

Signed-off-by: Stephen Carlson 
---
 MAINTAINERS   |  6 ++
 configs/sandbox_defconfig |  1 +
 test/py/tests/test_pci_mps.py | 13 +
 3 files changed, 20 insertions(+)
 create mode 100644 test/py/tests/test_pci_mps.py

diff --git a/MAINTAINERS b/MAINTAINERS
index 3e8e193ecc..83948b6aa7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1242,6 +1242,12 @@ M:   Heiko Schocher 
 S: Maintained
 F: drivers/pci/pci_mpc85xx.c
 
+PCI MPS
+M: Stephen Carlson 
+S: Maintained
+F: cmd/pci_mps.c
+F: test/py/tests/test_pci_mps.py
+
 POWER
 M: Jaehoon Chung 
 S: Maintained
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 34c342b6f5..cd6bb8e2c4 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -77,6 +77,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_MUX=y
 CONFIG_CMD_OSD=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_PCI_MPS=y
 CONFIG_CMD_READ=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_SPI=y
diff --git a/test/py/tests/test_pci_mps.py b/test/py/tests/test_pci_mps.py
new file mode 100644
index 00..8d33490f9f
--- /dev/null
+++ b/test/py/tests/test_pci_mps.py
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+import pytest
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_pci')
+@pytest.mark.buildconfigspec('cmd_pci_mps')
+def test_pci_mps_safe(u_boot_console):
+"""Tests that PCI MPS can be set to safe mode and uses 256 bytes."""
+
+response = u_boot_console.run_command('pci e; pci_mps s')
+expected_response = 'to 256B'
+assert(expected_response in response)
-- 
2.25.1

[PATCH 1/3] cmd: pci: Add command to set MPS of all PCIe devices

[stcarlso]

From: Stephen Carlson 

Enable tuning of the PCI Express MPS (Maximum Payload Size) of
each device. The Maximum Read Request Size is not altered.

The SAFE method uses the largest MPS value supported by all devices in the
system for each device. This method is the same algorithm as used by Linux
pci=pcie_bus_safe.

The PEER2PEER method sets all devices to the minimal (128 byte) MPS, which
allows hot plug of devices later that might only support the minimum size,
and ensures compatibility of DMA between two devices on the bus.

Signed-off-by: Stephen Carlson 
---
 cmd/Kconfig   |  10 +++
 cmd/Makefile  |   1 +
 cmd/pci_mps.c | 167 ++
 include/pci.h |   7 +++
 4 files changed, 185 insertions(+)
 create mode 100644 cmd/pci_mps.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index dc0446e02e..632c5c45db 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1390,6 +1390,16 @@ config CMD_PCI
  peripherals. Sub-commands allow bus enumeration, displaying and
  changing configuration space and a few other features.
 
+config CMD_PCI_MPS
+   bool "pci_mps - Configure PCI device MPS"
+   depends on PCI
+   help
+ Enables PCI Express Maximum Packet Size (MPS) tuning. This
+ command configures the PCI Express MPS of each endpoint to the
+ largest value supported by all devices below the root complex.
+ The Maximum Read Request Size will not be altered. This method is
+ the same algorithm as used by Linux pci=pcie_bus_safe.
+
 config CMD_PINMUX
bool "pinmux - show pins muxing"
depends on PINCTRL
diff --git a/cmd/Makefile b/cmd/Makefile
index 7b6ff73186..3365634843 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -133,6 +133,7 @@ obj-$(CONFIG_CMD_PART) += part.o
 obj-$(CONFIG_CMD_PCAP) += pcap.o
 ifdef CONFIG_PCI
 obj-$(CONFIG_CMD_PCI) += pci.o
+obj-$(CONFIG_CMD_PCI_MPS) += pci_mps.o
 endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
 obj-$(CONFIG_CMD_PMC) += pmc.o
diff --git a/cmd/pci_mps.c b/cmd/pci_mps.c
new file mode 100644
index 00..c67d007838
--- /dev/null
+++ b/cmd/pci_mps.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Microsoft Corporation 
+ * Stephen Carlson 
+ *
+ * PCI Express Maximum Packet Size (MPS) configuration
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCI_MPS_SAFE 0
+#define PCI_MPS_PEER2PEER 1
+
+static int pci_mps_find_safe(struct udevice *bus, unsigned int *min_mps,
+unsigned int *n)
+{
+   struct udevice *dev;
+   int res = 0, addr;
+   unsigned int mpss;
+   u32 regval;
+
+   if (!min_mps || !n)
+   return -EINVAL;
+
+   for (device_find_first_child(bus, &dev);
+dev;
+device_find_next_child(&dev)) {
+   addr = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
+   if (addr <= 0)
+   continue;
+
+   res = dm_pci_read_config32(dev, addr + PCI_EXP_DEVCAP,
+  ®val);
+   if (res != 0)
+   return res;
+   mpss = (unsigned int)(regval & PCI_EXP_DEVCAP_PAYLOAD);
+   *n += 1;
+   if (mpss < *min_mps)
+   *min_mps = mpss;
+   }
+
+   return res;
+}
+
+static int pci_mps_set_bus(struct udevice *bus, unsigned int target)
+{
+   struct udevice *dev;
+   u32 mpss, target_mps = (u32)(target << 5);
+   u16 mps;
+   int res = 0, addr;
+   int busnum = dev_seq(bus);
+
+   for (device_find_first_child(bus, &dev);
+dev && res == 0;
+device_find_next_child(&dev)) {
+   struct pci_child_plat *pplat;
+
+   addr = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
+   if (addr <= 0)
+   continue;
+
+   res = dm_pci_read_config32(dev, addr + PCI_EXP_DEVCAP,
+  &mpss);
+   if (res != 0)
+   return res;
+
+   /* Do not set device above its maximum MPSS */
+   mpss = (mpss & PCI_EXP_DEVCAP_PAYLOAD) << 5;
+   if (target_mps < mpss)
+   mps = (u16)target_mps;
+   else
+   mps = (u16)mpss;
+   res = dm_pci_clrset_config16(dev, addr + PCI_EXP_DEVCTL,
+PCI_EXP_DEVCTL_PAYLOAD, mps);
+   }
+
+   return res;
+}
+
+/*
+ * Sets the MPS of each PCI Express device to the specified policy.
+ */
+static int pci_mps_set(int policy)
+{
+   struct udevice *bus;
+   int i, res = 0;
+   /* 0 = 128B, min value for hotplug */
+   unsigned int mps = 0;
+
+   if (policy == PCI_MPS_SAFE) {
+   unsigned int min_mps = PCI_EXP_DEVCAP_PAYLOAD_4096B, n = 0;
+
+   /* Find maxi

[PATCH 0/3] Add command to set MPS of all PCI Express devices

[stcarlso]

From: Stephen Carlson 

This patch set adds support for configuring the Maximum Payload Size
(MPS) for attached PCI Express devices. Modifying the MPS can increase
PCI Express performance or ensure compatibility with hot-plugged
devices.

New config CONFIG_CMD_PCI_MPS. If enabled, a new "pci_mps" command will
be added that accepts an argument describing a strategy to configure the
PCI Express payload size for devices that are currently attached. Two
strategies are currently supported:

"safe" emulates the Linux kernel's pci=pcie_bus_safe and sets all devices
to the minimum MPS supported by all devices.

"peer2peer" sets all devices to an MPS of 128 bytes, the only size which
must be supported by all compliant PCI Express devices, to ensure that
all devices can directly communicate with each other and with devices that
are hotplugged later.

A test for the sandbox environment is also added by advertising a
larger supported Maximum Payload Size in the swapcase device and
verifying that the pci_mps command can read and configure the MPS.

Stephen Carlson (3):
  cmd: pci: Add command to set MPS of all PCIe devices
  drivers: pci: sandbox: Add stub sandbox PCI MPS support
  test: Add test for new command pci_mps

 MAINTAINERS   |   6 ++
 cmd/Kconfig   |  10 ++
 cmd/Makefile  |   1 +
 cmd/pci_mps.c | 167 ++
 configs/sandbox_defconfig |   1 +
 drivers/misc/swap_case.c  |   3 +
 include/pci.h |   7 ++
 test/py/tests/test_pci_mps.py |  13 +++
 8 files changed, 208 insertions(+)
 create mode 100644 cmd/pci_mps.c
 create mode 100644 test/py/tests/test_pci_mps.py

-- 
2.25.1

[PATCH 2/3] drivers: pci: sandbox: Add stub sandbox PCI MPS support

[stcarlso]

From: Stephen Carlson 

Reports the sandbox swapcase PCI Express device to support a 256 byte
Maximum Payload Size for MPS tuning tests.

Signed-off-by: Stephen Carlson 
---
 drivers/misc/swap_case.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c
index 7093ad1cd4..ee5c12bd0a 100644
--- a/drivers/misc/swap_case.c
+++ b/drivers/misc/swap_case.c
@@ -165,6 +165,9 @@ static int sandbox_swap_case_read_config(const struct 
udevice *emul,
case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
*valuep = PCI_CAP_ID_MSIX_OFFSET;
break;
+   case PCI_CAP_ID_EXP_OFFSET + PCI_EXP_DEVCAP:
+   *valuep = PCI_EXP_DEVCAP_PAYLOAD_256B;
+   break;
case PCI_CAP_ID_MSIX_OFFSET:
if (sandbox_swap_case_use_ea(emul))
*valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
-- 
2.25.1

Re: [PATCH v1 2/2] arm: dts: rockchip: rk3188-radxarock-u-boot: remove timer compatible replacement

[Kever Yang]

On 2023/3/7 23:32, Johan Jonker wrote:

The Rockchip timer driver has been renamed after the fall back compatible.
There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi
anymore, so remove.

Signed-off-by: Johan Jonker 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
  arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 1 -
  1 file changed, 1 deletion(-)

diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi 
b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
index 9c9016de..de299598 100644
--- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -52,7 +52,6 @@
  };

  &timer3 {
-   compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
clock-frequency = <2400>;
u-boot,dm-spl;
  };
--
2.20.1

Re: [PATCH v1 1/2] rockchip: timer: rockchip_timer: fix compatible and driver name

[Kever Yang]

On 2023/3/7 23:30, Johan Jonker wrote:

In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
  drivers/timer/rockchip_timer.c | 8 +++-
  1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 62eacb98..e66c49aa 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;

  #if CONFIG_IS_ENABLED(OF_PLATDATA)
  struct rockchip_timer_plat {
-   struct dtd_rockchip_rk3368_timer dtd;
+   struct dtd_rockchip_rk3288_timer dtd;
  };
  #endif

@@ -152,14 +152,12 @@ static const struct timer_ops rockchip_timer_ops = {
  };

  static const struct udevice_id rockchip_timer_ids[] = {
-   { .compatible = "rockchip,rk3188-timer" },
{ .compatible = "rockchip,rk3288-timer" },
-   { .compatible = "rockchip,rk3368-timer" },
{}
  };

-U_BOOT_DRIVER(rockchip_rk3368_timer) = {
-   .name   = "rockchip_rk3368_timer",
+U_BOOT_DRIVER(rockchip_rk3288_timer) = {
+   .name   = "rockchip_rk3288_timer",
.id = UCLASS_TIMER,
.of_match = rockchip_timer_ids,
.probe = rockchip_timer_probe,
--
2.20.1

Re: [PATCH v3] pinctrl: rockchip: support rk3588 pinctrl

[Kever Yang]

On 2023/3/7 19:56, Eugen Hristev wrote:

From: Jianqun Xu 

Add support for Rockchip rk3588 variant of pinctrl.

The driver is adapted from the Linux driver.

Signed-off-by: Jianqun Xu 
[eugen.hris...@collabora.com:
port to latest U-boot, bring more changes from Linux]
Signed-off-by: Eugen Hristev 

Reviewed-by: Kever Yang 


Thanks,
- Kever

---
Changes in v3:
- change assert(i) to assert (i >= 0) because i==0 is a valid number it's
the first entry in the array. Otherwise it would assert wrongly when setting
gpio 0 A2 e.g.

Changes in v2:
- change the way the reg is computed to align with Linux
- For the gpio4 bank D0-8, as the downstream uboot uses VCCIO6 instead of
VCCIO2, change accordingly, otherwise D0-D5 pins won't work to set PUP/PDOWN,
DS, etc. It appears gpio4D has the registers just after gpio4A,gpio4B,gpio4C
in the same VCCIO6, and not in VCCIO2.

  drivers/pinctrl/rockchip/Makefile   |   1 +
  drivers/pinctrl/rockchip/pinctrl-rk3588.c   | 347 
  drivers/pinctrl/rockchip/pinctrl-rockchip.h | 187 +++
  3 files changed, 535 insertions(+)
  create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3588.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 90461ae8819a..c91f650b0434 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
  obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
  obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
  obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
  obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
  obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
new file mode 100644
index ..fc373989a20c
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-rockchip.h"
+#include 
+
+static int rk3588_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+   struct rockchip_pinctrl_priv *priv = bank->priv;
+   struct regmap *regmap;
+   int iomux_num = (pin / 8);
+   int reg, ret, mask;
+   u8 bit;
+   u32 data;
+
+   debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+   regmap = priv->regmap_base;
+   reg = bank->iomux[iomux_num].offset;
+   if ((pin % 8) >= 4)
+   reg += 0x4;
+   bit = (pin % 4) * 4;
+   mask = 0xf;
+
+   if (bank->bank_num == 0) {
+   if (pin >= RK_PB4 && pin <= RK_PD7) {
+   if (mux < 8) {
+   reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
+   data = (mask << (bit + 16));
+   data |= (mux & mask) << bit;
+   ret = regmap_write(regmap, reg, data);
+   } else {
+   u32 reg0 = 0;
+
+   reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+   data = (mask << (bit + 16));
+   data |= 8 << bit;
+   ret = regmap_write(regmap, reg0, data);
+
+   reg0 = reg + 0x8000; /* BUS_IOC_BASE */
+   data = (mask << (bit + 16));
+   data |= mux << bit;
+   regmap = priv->regmap_base;
+   regmap_write(regmap, reg0, data);
+   }
+   } else {
+   data = (mask << (bit + 16));
+   data |= (mux & mask) << bit;
+   ret = regmap_write(regmap, reg, data);
+   }
+   return ret;
+   } else if (bank->bank_num > 0) {
+   reg += 0x8000; /* BUS_IOC_BASE */
+   }
+
+   data = (mask << (bit + 16));
+   data |= (mux & mask) << bit;
+
+   return regmap_write(regmap, reg, data);
+}
+
+#define RK3588_PMU1_IOC_REG(0x)
+#define RK3588_PMU2_IOC_REG(0x4000)
+#define RK3588_BUS_IOC_REG (0x8000)
+#define RK3588_VCCIO1_4_IOC_REG(0x9000)
+#define RK3588_VCCIO3_5_IOC_REG(0xA000)
+#define RK3588_VCCIO2_IOC_REG  (0xB000)
+#define RK3588_VCCIO6_IOC_REG  (0xC000)
+#define RK3588_EMMC_IOC_REG(0xD000)
+
+static const u32 rk3588_ds_regs[][2] = {
+   {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
+   {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
+   {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
+   {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
+   {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
+   {RK_G

Re: [PATCH] mtd: rawnand: nand_base: Handle algorithm selection

[Linus Walleij]

On Sun, Jan 22, 2023 at 12:43 AM Linus Walleij  wrote:

> For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
> D-Link DIR-885L and DIR-890L routers, we need to explicitly
> select the ECC like this in the device tree:
>
>   nand-ecc-algo = "bch";
>   nand-ecc-strength = <1>;
>   nand-ecc-step-size = <512>;
>
> This is handled by the Linux kernel but U-Boot core does
> not respect this. Fix it up by parsing the algorithm and
> preserve the behaviour using this property to select
> software BCH as far as possible.
>
> Signed-off-by: Linus Walleij 

It's been 1 1/2 month, could we apply this patch?

Yours,
Linus Walleij

Re: [PATCH] nand: brcmnand: add iproc support

[Linus Walleij]

On Sun, Jan 22, 2023 at 12:45 AM Linus Walleij  wrote:

> Add support for the iproc Broadcom NAND controller,
> used in Northstar SoCs for example. Based on the Linux
> driver.
>
> Cc: Philippe Reynes 
> Signed-off-by: Linus Walleij 

It's been 1 1/2 month, could we apply this patch?

Yours,
Linus Walleij

[PATCH v2 3/3] Revert "arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates"

[Vasily Khoruzhick]

This reverts commit 5bec4b0de7851a254fb4447b3599a60f95550141.

Signed-off-by: Vasily Khoruzhick 
---
v2: revert dropping assigned-clock properties because we have stubs for
CLK_PCIEPHY_REF clocks now

 arch/arm/dts/rk356x-u-boot.dtsi | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 2331641049..1709604b22 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -34,11 +34,6 @@
};
 };
 
-&combphy1 {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-rates;
-};
-
 &cru {
u-boot,dm-pre-reloc;
status = "okay";
-- 
2.39.2

[PATCH v2 2/3] clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks

[Vasily Khoruzhick]

Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Signed-off-by: Vasily Khoruzhick 
---
v2: implement stubs for CLK_PCIEPHY_REF instead of dropping
assigned-clock properties

 drivers/clk/rockchip/clk_rk3568.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 253b69504f..1c6adc56f9 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong 
rate)
case PCLK_PMU:
ret = rk3568_pmu_set_pmuclk(priv, rate);
break;
+   case CLK_PCIEPHY0_REF:
+   case CLK_PCIEPHY1_REF:
+   return 0;
default:
return -ENOENT;
}
-- 
2.39.2

[PATCH v2 1/3] phy: rockchip-inno-usb2: add support for phy-supply

[Vasily Khoruzhick]

PHY driver needs to enable PHY supply, otherwise port will
remain unpowered.

Signed-off-by: Vasily Khoruzhick 
---
v2: address check_patch.pl issues

 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 64 ++-
 1 file changed, 61 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 55e1dbcfef..a859cd6f18 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -62,6 +63,10 @@ struct rockchip_usb2phy {
void *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   struct udevice *host_supply;
+   struct udevice *otg_supply;
+#endif
 };
 
 static inline int property_enable(void *reg_base,
@@ -86,12 +91,42 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct 
phy *phy)
return &phy_cfg->port_cfgs[phy->id];
 }
 
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+   struct udevice *supply;
+   int ret = 0;
+
+   if (phy->id == USB2PHY_PORT_HOST)
+   supply = priv->host_supply;
+   else
+   supply = priv->otg_supply;
+
+   if (supply)
+   ret = regulator_set_enable(supply, enable);
+
+   return ret;
+}
+#else
+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   return 0;
+}
+#endif
+
 static int rockchip_usb2phy_power_on(struct phy *phy)
 {
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
 
+   int ret = rockchip_usb2phy_regulator_set_enable(phy, true);
+
+   if (ret)
+   return ret;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
 
/* waiting for the utmi_clk to become stable */
@@ -108,6 +143,11 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
 
property_enable(priv->reg_base, &port_cfg->phy_sus, true);
 
+   int ret = rockchip_usb2phy_regulator_set_enable(phy, false);
+
+   if (ret)
+   return ret;
+
return 0;
 }
 
@@ -149,13 +189,31 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy,
 struct ofnode_phandle_args *args)
 {
const char *name = phy->dev->name;
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   struct udevice *supply;
+   int ret = device_get_supply_regulator(phy->dev, "phy-supply", &supply);
+
+   if (ret && ret != -ENOENT) {
+   pr_err("Failed to get PHY regulator\n");
+   return ret;
+   }
+#endif
 
-   if (!strcasecmp(name, "host-port"))
+   if (!strcasecmp(name, "host-port")) {
phy->id = USB2PHY_PORT_HOST;
-   else if (!strcasecmp(name, "otg-port"))
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   priv->host_supply = supply;
+#endif
+   } else if (!strcasecmp(name, "otg-port")) {
phy->id = USB2PHY_PORT_OTG;
-   else
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+   priv->otg_supply = supply;
+#endif
+   } else {
dev_err(phy->dev, "improper %s device\n", name);
+   }
 
return 0;
 }
-- 
2.39.2

Re: [PATCH 2/2] arm64: dts: rk3568-u-boot: Drop combphy0 assigned-clocks/rates

[Vasily Khoruzhick]

On Tue, Mar 7, 2023 at 1:04 PM Mark Kettenis  wrote:

> And implement support for the CLK_PCIEPHYn_REF clocks in
> drivers/clk/rockchip/clk_rk3568.c:rk3568_pmuclk_set_rate()?
>
> Yes, I'd say so.
>
> If U-Boot doesn't actually need these clocks to run at the frequency
> provided by assigned-clock-rates, that could be as simple as returning
> 0 for these clocks.

Sounds good. I'll send v2 that reverts 5bec4b0de785 and implements
stubs for CLK_PCIEPHYn_REF clocks.

FWIW, I tried booting linux-6.2.2 with u-boot dtb and these clocks
dropped, and USB works just fine.

> > > > commit 5bec4b0de785 ("arm64: dts: rk356x-u-boot: Drop combphy1 
> > > > assigned-clocks/rates")
> > > > dropped these properties for combphy1, so let's drop them for combphy0 
> > > > as well.
> > > >
> > > > Signed-off-by: Vasily Khoruzhick 
> > > > ---
> > > >  arch/arm/dts/rk3568-evb-u-boot.dtsi |  1 +
> > > >  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  1 +
> > > >  arch/arm/dts/rk3568-u-boot.dtsi | 11 +++
> > > >  3 files changed, 13 insertions(+)
> > > >  create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi
> > > >
> > > > diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi 
> > > > b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > > > index 17503d3d27..77430da3ba 100644
> > > > --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > > > +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > > > @@ -4,6 +4,7 @@
> > > >   */
> > > >
> > > >  #include "rk356x-u-boot.dtsi"
> > > > +#include "rk3568-u-boot.dtsi"
> > > >
> > > >  / {
> > > >   chosen {
> > > > diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
> > > > b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > > > index ed47efa44b..44cf33ed4b 100644
> > > > --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > > > +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > > > @@ -5,6 +5,7 @@
> > > >   */
> > > >
> > > >  #include "rk356x-u-boot.dtsi"
> > > > +#include "rk3568-u-boot.dtsi"
> > > >
> > > >  / {
> > > >   chosen {
> > > > diff --git a/arch/arm/dts/rk3568-u-boot.dtsi 
> > > > b/arch/arm/dts/rk3568-u-boot.dtsi
> > > > new file mode 100644
> > > > index 00..c677df
> > > > --- /dev/null
> > > > +++ b/arch/arm/dts/rk3568-u-boot.dtsi
> > > > @@ -0,0 +1,11 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + * Copyright (c) 2023 Vasily Khoruzhick 
> > > > + */
> > > > +
> > > > +#include "rockchip-u-boot.dtsi"
> > > > +
> > > > +&combphy0 {
> > > > + /delete-property/ assigned-clocks;
> > > > + /delete-property/ assigned-clock-rates;
> > > > +};
> > > > --
> > > > 2.39.2
> > > >
> > > >
> >

[PATCH] rockchip: sdhci: rk3568: fix clock setting logic

[Vasily Khoruzhick]

mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.

Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.

Fix it by using MAX(mmc->tran_speed, mmc->clock)

Signed-off-by: Vasily Khoruzhick 
---
 drivers/mmc/rockchip_sdhci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 9608770d4e..1ac95f32b3 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -394,11 +394,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct 
sdhci_host *host)
 static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 {
struct mmc *mmc = host->mmc;
-   uint clock = mmc->tran_speed;
+   uint clock = mmc->clock;
u32 reg, vendor_reg;
 
-   if (!clock)
-   clock = mmc->clock;
+   if (mmc->tran_speed && mmc->clock > mmc->tran_speed)
+   clock = mmc->tran_speed;
 
rk3568_sdhci_emmc_set_clock(host, clock);
 
-- 
2.39.2

Re: [PATCH 2/2] arm64: dts: rk3568-u-boot: Drop combphy0 assigned-clocks/rates

[Mark Kettenis]

> From: Vasily Khoruzhick 
> Date: Tue, 7 Mar 2023 12:34:48 -0800
> 
> On Tue, Mar 7, 2023 at 11:53 AM Mark Kettenis  wrote:
> 
> > That is probably the wrong approach.  It should be possible to boot an
> > OS with the device tree provided by U-Boot.  Removing these properties
> > means the OS doesn't see them either.  But if the assigned-clocks
> > property isn't needed it wouldn't be there would it?
> 
> Well, should we revert 5bec4b0de785 in this case?

And implement support for the CLK_PCIEPHYn_REF clocks in
drivers/clk/rockchip/clk_rk3568.c:rk3568_pmuclk_set_rate()?

Yes, I'd say so.

If U-Boot doesn't actually need these clocks to run at the frequency
provided by assigned-clock-rates, that could be as simple as returning
0 for these clocks.

> > > commit 5bec4b0de785 ("arm64: dts: rk356x-u-boot: Drop combphy1 
> > > assigned-clocks/rates")
> > > dropped these properties for combphy1, so let's drop them for combphy0 as 
> > > well.
> > >
> > > Signed-off-by: Vasily Khoruzhick 
> > > ---
> > >  arch/arm/dts/rk3568-evb-u-boot.dtsi |  1 +
> > >  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  1 +
> > >  arch/arm/dts/rk3568-u-boot.dtsi | 11 +++
> > >  3 files changed, 13 insertions(+)
> > >  create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi
> > >
> > > diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi 
> > > b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > > index 17503d3d27..77430da3ba 100644
> > > --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > > +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > > @@ -4,6 +4,7 @@
> > >   */
> > >
> > >  #include "rk356x-u-boot.dtsi"
> > > +#include "rk3568-u-boot.dtsi"
> > >
> > >  / {
> > >   chosen {
> > > diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
> > > b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > > index ed47efa44b..44cf33ed4b 100644
> > > --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > > +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > > @@ -5,6 +5,7 @@
> > >   */
> > >
> > >  #include "rk356x-u-boot.dtsi"
> > > +#include "rk3568-u-boot.dtsi"
> > >
> > >  / {
> > >   chosen {
> > > diff --git a/arch/arm/dts/rk3568-u-boot.dtsi 
> > > b/arch/arm/dts/rk3568-u-boot.dtsi
> > > new file mode 100644
> > > index 00..c677df
> > > --- /dev/null
> > > +++ b/arch/arm/dts/rk3568-u-boot.dtsi
> > > @@ -0,0 +1,11 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright (c) 2023 Vasily Khoruzhick 
> > > + */
> > > +
> > > +#include "rockchip-u-boot.dtsi"
> > > +
> > > +&combphy0 {
> > > + /delete-property/ assigned-clocks;
> > > + /delete-property/ assigned-clock-rates;
> > > +};
> > > --
> > > 2.39.2
> > >
> > >
> 

Re: [PATCH RFC u-boot-mvebu 0/6] arm: mvebu: Fix boot mode detection

[Pali Rohár]

On Tuesday 07 March 2023 12:53:45 Tony Dinh wrote:
> Hi Pali,
> 
> On Mon, Mar 6, 2023 at 11:56 PM Pali Rohár  wrote:
> >
> > On Monday 06 March 2023 20:15:07 Tony Dinh wrote:
> > > Hi Pali,
> > >
> > > On Mon, Mar 6, 2023 at 4:11 PM Pali Rohár  wrote:
> > > >
> > > > On Monday 06 March 2023 16:01:58 Tony Dinh wrote:
> > > > > Hi Pali,
> > > > >
> > > > > On Sun, Mar 5, 2023 at 4:41 PM Tony Dinh  wrote:
> > > > > >
> > > > > > Hi Pali,
> > > > > >
> > > > > > On Sun, Mar 5, 2023 at 2:54 PM Pali Rohár  wrote:
> > > > > > >
> > > > > > > On Sunday 05 March 2023 14:46:55 Tony Dinh wrote:
> > > > > > > > On Sun, Mar 5, 2023 at 2:44 PM Tony Dinh  
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > Hi Pali,
> > > > > > > > >
> > > > > > > > > On Sun, Mar 5, 2023 at 3:55 AM Pali Rohár  
> > > > > > > > > wrote:
> > > > > > > > > >
> > > > > > > > > > On Sunday 05 March 2023 04:21:42 Martin Rowe wrote:
> > > > > > > > > > > On Sat, 4 Mar 2023 at 10:51, Pali Rohár  
> > > > > > > > > > > wrote:
> > > > > > > > > > >
> > > > > > > > > > > > Improve code for checking strapping pins which 
> > > > > > > > > > > > specifies boot mode source.
> > > > > > > > > > > >
> > > > > > > > > > > > Martin, could you test if Clearfog can be still 
> > > > > > > > > > > > configured into UART
> > > > > > > > > > > > booting mode via HW switches and if it still works 
> > > > > > > > > > > > correctly? First
> > > > > > > > > > > > patch is reverting UART related commit for Clearfog 
> > > > > > > > > > > > which I think it not
> > > > > > > > > > > > needed anymore.
> > > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > On Clearfog the logic in the CONFIG_ARMADA_38X ifdef 
> > > > > > > > > > > before the switch that
> > > > > > > > > > > you refactored in cpu.c/get_boot_device is all that gets 
> > > > > > > > > > > processed. It
> > > > > > > > > > > decides there is an error and returns BOOT_DEVICE_UART, 
> > > > > > > > > > > probably because of
> > > > > > > > > > > the invalid boot workaround for broken UART selection 
> > > > > > > > > > > that you identified.
> > > > > > > > > >
> > > > > > > > > > Ok, so I figured out correctly how this invalid mode works.
> > > > > > > > > >
> > > > > > > > > > > UART only works if I use the clearfog_spi_defconfig or if 
> > > > > > > > > > > I select
> > > > > > > > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_UART=y. It does not work 
> > > > > > > > > > > with the MMC or SATA
> > > > > > > > > > > defconfigs. I get the same result without this patch 
> > > > > > > > > > > series applied, though.
> > > > > > > > > > >
> > > > > > > > > > > The failed cases have the same output (other than kwboot 
> > > > > > > > > > > header patching
> > > > > > > > > > > output) until after sending boot image data is complete. 
> > > > > > > > > > > The output stops
> > > > > > > > > > > after:
> > > > > > > > > > > 
> > > > > > > > > > >  98 % 
> > > > > > > > > > > [.
> > > > > > > > > > >   ]
> > > > > > > > > > > Done
> > > > > > > > > > > Finishing transfer
> > > > > > > > > > > [Type Ctrl-\ + c to quit]
> > > > > > > > > > > 
> > > > > > > > > >
> > > > > > > > > > This is very strange because 
> > > > > > > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_UART just
> > > > > > > > > > instruct mkimage what to put into kwbimage header.
> > > > > > > > > >
> > > > > > > > > > If I'm looking at the output correctly then SPL was booted, 
> > > > > > > > > > it correctly
> > > > > > > > > > trained DDR RAM, returned back to bootrom, kwboot continued 
> > > > > > > > > > sending main
> > > > > > > > > > u-boot and bootrom confirmed that transfer of both SPL and 
> > > > > > > > > > main u-boot
> > > > > > > > > > is complete. But then there is no output from main u-boot.
> > > > > > > > > >
> > > > > > > > > > > It looks like an unrelated issue with kwboot.c, which I 
> > > > > > > > > > > was sure was
> > > > > > > > > > > working after the last patches but I can no longer 
> > > > > > > > > > > reproduce a successful
> > > > > > > > > > > boot.
> > > > > > > > > >
> > > > > > > > > > Can you check that you are using _both_ mkimage and kwboot 
> > > > > > > > > > from version
> > > > > > > > > > with applying _all_ my patches recently sent to ML? Because 
> > > > > > > > > > both mkimage
> > > > > > > > > > and kwboot have fixes for SATA and SDIO images.
> > > > > > > > > >
> > > > > > > > > > For me it looks like that either mkimage generated 
> > > > > > > > > > incorrect image size
> > > > > > > > > > for SATA or SDIO image. Or kwboot incorrectly parsed that 
> > > > > > > > > > image size
> > > > > > > > > > from kwbimage header and sent smaller image.
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > > Also could you check if SATA booting is still working 
> > > > > > > > > > > > correctly?
> > > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > 

Re: [PATCH RFC u-boot-mvebu 0/6] arm: mvebu: Fix boot mode detection

[Tony Dinh]

Hi Pali,

On Mon, Mar 6, 2023 at 11:56 PM Pali Rohár  wrote:
>
> On Monday 06 March 2023 20:15:07 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Mon, Mar 6, 2023 at 4:11 PM Pali Rohár  wrote:
> > >
> > > On Monday 06 March 2023 16:01:58 Tony Dinh wrote:
> > > > Hi Pali,
> > > >
> > > > On Sun, Mar 5, 2023 at 4:41 PM Tony Dinh  wrote:
> > > > >
> > > > > Hi Pali,
> > > > >
> > > > > On Sun, Mar 5, 2023 at 2:54 PM Pali Rohár  wrote:
> > > > > >
> > > > > > On Sunday 05 March 2023 14:46:55 Tony Dinh wrote:
> > > > > > > On Sun, Mar 5, 2023 at 2:44 PM Tony Dinh  
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > Hi Pali,
> > > > > > > >
> > > > > > > > On Sun, Mar 5, 2023 at 3:55 AM Pali Rohár  
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > On Sunday 05 March 2023 04:21:42 Martin Rowe wrote:
> > > > > > > > > > On Sat, 4 Mar 2023 at 10:51, Pali Rohár  
> > > > > > > > > > wrote:
> > > > > > > > > >
> > > > > > > > > > > Improve code for checking strapping pins which specifies 
> > > > > > > > > > > boot mode source.
> > > > > > > > > > >
> > > > > > > > > > > Martin, could you test if Clearfog can be still 
> > > > > > > > > > > configured into UART
> > > > > > > > > > > booting mode via HW switches and if it still works 
> > > > > > > > > > > correctly? First
> > > > > > > > > > > patch is reverting UART related commit for Clearfog which 
> > > > > > > > > > > I think it not
> > > > > > > > > > > needed anymore.
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > On Clearfog the logic in the CONFIG_ARMADA_38X ifdef before 
> > > > > > > > > > the switch that
> > > > > > > > > > you refactored in cpu.c/get_boot_device is all that gets 
> > > > > > > > > > processed. It
> > > > > > > > > > decides there is an error and returns BOOT_DEVICE_UART, 
> > > > > > > > > > probably because of
> > > > > > > > > > the invalid boot workaround for broken UART selection that 
> > > > > > > > > > you identified.
> > > > > > > > >
> > > > > > > > > Ok, so I figured out correctly how this invalid mode works.
> > > > > > > > >
> > > > > > > > > > UART only works if I use the clearfog_spi_defconfig or if I 
> > > > > > > > > > select
> > > > > > > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_UART=y. It does not work with 
> > > > > > > > > > the MMC or SATA
> > > > > > > > > > defconfigs. I get the same result without this patch series 
> > > > > > > > > > applied, though.
> > > > > > > > > >
> > > > > > > > > > The failed cases have the same output (other than kwboot 
> > > > > > > > > > header patching
> > > > > > > > > > output) until after sending boot image data is complete. 
> > > > > > > > > > The output stops
> > > > > > > > > > after:
> > > > > > > > > > 
> > > > > > > > > >  98 % 
> > > > > > > > > > [.
> > > > > > > > > >   ]
> > > > > > > > > > Done
> > > > > > > > > > Finishing transfer
> > > > > > > > > > [Type Ctrl-\ + c to quit]
> > > > > > > > > > 
> > > > > > > > >
> > > > > > > > > This is very strange because 
> > > > > > > > > CONFIG_MVEBU_SPL_BOOT_DEVICE_UART just
> > > > > > > > > instruct mkimage what to put into kwbimage header.
> > > > > > > > >
> > > > > > > > > If I'm looking at the output correctly then SPL was booted, 
> > > > > > > > > it correctly
> > > > > > > > > trained DDR RAM, returned back to bootrom, kwboot continued 
> > > > > > > > > sending main
> > > > > > > > > u-boot and bootrom confirmed that transfer of both SPL and 
> > > > > > > > > main u-boot
> > > > > > > > > is complete. But then there is no output from main u-boot.
> > > > > > > > >
> > > > > > > > > > It looks like an unrelated issue with kwboot.c, which I was 
> > > > > > > > > > sure was
> > > > > > > > > > working after the last patches but I can no longer 
> > > > > > > > > > reproduce a successful
> > > > > > > > > > boot.
> > > > > > > > >
> > > > > > > > > Can you check that you are using _both_ mkimage and kwboot 
> > > > > > > > > from version
> > > > > > > > > with applying _all_ my patches recently sent to ML? Because 
> > > > > > > > > both mkimage
> > > > > > > > > and kwboot have fixes for SATA and SDIO images.
> > > > > > > > >
> > > > > > > > > For me it looks like that either mkimage generated incorrect 
> > > > > > > > > image size
> > > > > > > > > for SATA or SDIO image. Or kwboot incorrectly parsed that 
> > > > > > > > > image size
> > > > > > > > > from kwbimage header and sent smaller image.
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > > Also could you check if SATA booting is still working 
> > > > > > > > > > > correctly?
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > SATA works correctly.
> > > > > > > > >
> > > > > > > > > Perfect!
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > > Tony, should address problems with SPI booting when it is 
> > > > > > > > > > > configured to
> > > > > > > > > > > different configuration. In f

Re: [PATCH 2/2] arm64: dts: rk3568-u-boot: Drop combphy0 assigned-clocks/rates

[Vasily Khoruzhick]

On Tue, Mar 7, 2023 at 11:53 AM Mark Kettenis  wrote:

> That is probably the wrong approach.  It should be possible to boot an
> OS with the device tree provided by U-Boot.  Removing these properties
> means the OS doesn't see them either.  But if the assigned-clocks
> property isn't needed it wouldn't be there would it?

Well, should we revert 5bec4b0de785 in this case?

> > commit 5bec4b0de785 ("arm64: dts: rk356x-u-boot: Drop combphy1 
> > assigned-clocks/rates")
> > dropped these properties for combphy1, so let's drop them for combphy0 as 
> > well.
> >
> > Signed-off-by: Vasily Khoruzhick 
> > ---
> >  arch/arm/dts/rk3568-evb-u-boot.dtsi |  1 +
> >  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  1 +
> >  arch/arm/dts/rk3568-u-boot.dtsi | 11 +++
> >  3 files changed, 13 insertions(+)
> >  create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi
> >
> > diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi 
> > b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > index 17503d3d27..77430da3ba 100644
> > --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> > @@ -4,6 +4,7 @@
> >   */
> >
> >  #include "rk356x-u-boot.dtsi"
> > +#include "rk3568-u-boot.dtsi"
> >
> >  / {
> >   chosen {
> > diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
> > b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > index ed47efa44b..44cf33ed4b 100644
> > --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> > @@ -5,6 +5,7 @@
> >   */
> >
> >  #include "rk356x-u-boot.dtsi"
> > +#include "rk3568-u-boot.dtsi"
> >
> >  / {
> >   chosen {
> > diff --git a/arch/arm/dts/rk3568-u-boot.dtsi 
> > b/arch/arm/dts/rk3568-u-boot.dtsi
> > new file mode 100644
> > index 00..c677df
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3568-u-boot.dtsi
> > @@ -0,0 +1,11 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2023 Vasily Khoruzhick 
> > + */
> > +
> > +#include "rockchip-u-boot.dtsi"
> > +
> > +&combphy0 {
> > + /delete-property/ assigned-clocks;
> > + /delete-property/ assigned-clock-rates;
> > +};
> > --
> > 2.39.2
> >
> >

Re: Please pull u-boot-video/next

[Tom Rini]

On Tue, Mar 07, 2023 at 05:16:49PM +0100, Anatolij Gustschin wrote:

> Hi Tom,
> 
> please pull video patches for next.
> 
> CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/15482
> 
> Thanks,
> Anatolij
> 
> The following changes since commit d1653548d29959a6ea6b4037a00b48a28257e6e6:
> 
>   Merge branch '2023-03-02-kconfig-and-CONFIG-cleanups' into next (2023-03-03 
> 12:48:23 -0500)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-video.git tags/next-20230307
> 
> for you to fetch changes up to 72471620e82758b6cbdb9f70d775c0c18b043794:
> 
>   video console: add 12x22 console simple font test (2023-03-07 16:00:18 
> +0100)
> 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] arm64: dts: rk3568-u-boot: Drop combphy0 assigned-clocks/rates

[Mark Kettenis]

> From: Vasily Khoruzhick 
> Date: Tue,  7 Mar 2023 11:37:48 -0800
> 
> combphy0 is failing to probe due to unhandled assigned-clocks and
> assigned-clocks-rates.

That is probably the wrong approach.  It should be possible to boot an
OS with the device tree provided by U-Boot.  Removing these properties
means the OS doesn't see them either.  But if the assigned-clocks
property isn't needed it wouldn't be there would it?

> commit 5bec4b0de785 ("arm64: dts: rk356x-u-boot: Drop combphy1 
> assigned-clocks/rates")
> dropped these properties for combphy1, so let's drop them for combphy0 as 
> well.
> 
> Signed-off-by: Vasily Khoruzhick 
> ---
>  arch/arm/dts/rk3568-evb-u-boot.dtsi |  1 +
>  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  1 +
>  arch/arm/dts/rk3568-u-boot.dtsi | 11 +++
>  3 files changed, 13 insertions(+)
>  create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi 
> b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> index 17503d3d27..77430da3ba 100644
> --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
> @@ -4,6 +4,7 @@
>   */
>  
>  #include "rk356x-u-boot.dtsi"
> +#include "rk3568-u-boot.dtsi"
>  
>  / {
>   chosen {
> diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
> b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> index ed47efa44b..44cf33ed4b 100644
> --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> @@ -5,6 +5,7 @@
>   */
>  
>  #include "rk356x-u-boot.dtsi"
> +#include "rk3568-u-boot.dtsi"
>  
>  / {
>   chosen {
> diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
> new file mode 100644
> index 00..c677df
> --- /dev/null
> +++ b/arch/arm/dts/rk3568-u-boot.dtsi
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2023 Vasily Khoruzhick 
> + */
> +
> +#include "rockchip-u-boot.dtsi"
> +
> +&combphy0 {
> + /delete-property/ assigned-clocks;
> + /delete-property/ assigned-clock-rates;
> +};
> -- 
> 2.39.2
> 
> 

[PATCH 2/2] arm64: dts: rk3568-u-boot: Drop combphy0 assigned-clocks/rates

[Vasily Khoruzhick]

combphy0 is failing to probe due to unhandled assigned-clocks and
assigned-clocks-rates.

commit 5bec4b0de785 ("arm64: dts: rk356x-u-boot: Drop combphy1 
assigned-clocks/rates")
dropped these properties for combphy1, so let's drop them for combphy0 as well.

Signed-off-by: Vasily Khoruzhick 
---
 arch/arm/dts/rk3568-evb-u-boot.dtsi |  1 +
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi |  1 +
 arch/arm/dts/rk3568-u-boot.dtsi | 11 +++
 3 files changed, 13 insertions(+)
 create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi

diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi 
b/arch/arm/dts/rk3568-evb-u-boot.dtsi
index 17503d3d27..77430da3ba 100644
--- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "rk356x-u-boot.dtsi"
+#include "rk3568-u-boot.dtsi"
 
 / {
chosen {
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index ed47efa44b..44cf33ed4b 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include "rk356x-u-boot.dtsi"
+#include "rk3568-u-boot.dtsi"
 
 / {
chosen {
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
new file mode 100644
index 00..c677df
--- /dev/null
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Vasily Khoruzhick 
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+&combphy0 {
+   /delete-property/ assigned-clocks;
+   /delete-property/ assigned-clock-rates;
+};
-- 
2.39.2

[PATCH 1/2] phy: rockchip-inno-usb2: add support for phy-supply

[Vasily Khoruzhick]

PHY driver needs to enable PHY supply, otherwise port will
remain unpowered.

Signed-off-by: Vasily Khoruzhick 
---
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 59 ++-
 1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c 
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 55e1dbcfef..1ef40b448e 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -62,6 +63,10 @@ struct rockchip_usb2phy {
void *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+   struct udevice *host_supply;
+   struct udevice *otg_supply;
+#endif
 };
 
 static inline int property_enable(void *reg_base,
@@ -86,12 +91,40 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct 
phy *phy)
return &phy_cfg->port_cfgs[phy->id];
 }
 
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+   struct udevice *supply;
+   int ret = 0;
+   if (phy->id == USB2PHY_PORT_HOST)
+   supply = priv->host_supply;
+   else
+   supply = priv->otg_supply;
+
+   if (supply)
+   ret = regulator_set_enable(supply, enable);
+
+   return ret;
+}
+#else
+static int rockchip_usb2phy_regulator_set_enable(struct phy *phy, bool enable)
+{
+   return 0;
+}
+#endif
+
 static int rockchip_usb2phy_power_on(struct phy *phy)
 {
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
 
+   int ret = rockchip_usb2phy_regulator_set_enable(phy, true);
+   if (ret)
+   return ret;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
 
/* waiting for the utmi_clk to become stable */
@@ -108,6 +141,10 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
 
property_enable(priv->reg_base, &port_cfg->phy_sus, true);
 
+   int ret = rockchip_usb2phy_regulator_set_enable(phy, false);
+   if (ret)
+   return ret;
+
return 0;
 }
 
@@ -149,11 +186,29 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy,
 struct ofnode_phandle_args *args)
 {
const char *name = phy->dev->name;
+   struct udevice *parent = dev_get_parent(phy->dev);
+   struct rockchip_usb2phy *priv = dev_get_priv(parent);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+   struct udevice *supply;
+   int ret = device_get_supply_regulator(phy->dev, "phy-supply", &supply);
+   if (ret && ret != -ENOENT) {
+   pr_err("Failed to get PHY regulator\n");
+   return ret;
+   }
+#endif
 
-   if (!strcasecmp(name, "host-port"))
+   if (!strcasecmp(name, "host-port")) {
phy->id = USB2PHY_PORT_HOST;
-   else if (!strcasecmp(name, "otg-port"))
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+   priv->host_supply = supply;
+#endif
+   }
+   else if (!strcasecmp(name, "otg-port")) {
phy->id = USB2PHY_PORT_OTG;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+   priv->otg_supply = supply;
+#endif
+   }
else
dev_err(phy->dev, "improper %s device\n", name);
 
-- 
2.39.2

Re: [PATCH V2 8/9] arm64: dts: rockchip: add gpio-ranges property to gpio nodes

[Vasily Khoruzhick]

On Wed, Mar 1, 2023 at 6:49 PM Kever Yang  wrote:

Hi Kever,

> So I have take this patch set, and we can improve later when kernel have
> a version and we have a better solution for U-Boot.

My concern is that dts will be overwritten during the next dts sync
with the kernel. U-boot specific properties should be moved into an
appropriate -u-boot.dtsi file.

Regards,
Vasily

Re: [PATCH v3 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree

[Conor Dooley]

On Tue, Mar 07, 2023 at 06:30:19AM +, Conor Dooley wrote:
> 
> 
> On 7 March 2023 01:59:31 GMT, yanhong wang  
> wrote:
> >
> >
> >On 2023/3/4 5:16, Conor Dooley wrote:
> >> On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
> >>> Add initial device tree for the JH7110 RISC-V SoC.
> >>> 
> >>> Signed-off-by: Yanhong Wang 
> >>> ---
> >>>  arch/riscv/dts/jh7110.dtsi | 582 +
> >>>  1 file changed, 582 insertions(+)
> >>>  create mode 100644 arch/riscv/dts/jh7110.dtsi
> >>> 
> >>> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> >>> new file mode 100644
> >>> index 00..d3e9f92987
> >>> --- /dev/null
> >>> +++ b/arch/riscv/dts/jh7110.dtsi
> >>> @@ -0,0 +1,582 @@
> >>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >>> +/*
> >>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >>> + */
> >>> +
> >>> +/dts-v1/;
> >>> +#include 
> >>> +#include 
> >>> +
> >>> +/ {
> >>> + compatible = "starfive,jh7110";
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> +
> >>> + cpus {
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> +
> >>> + S7_0: cpu@0 {
> >>> + compatible = "sifive,s7", "riscv";
> >>> + reg = <0>;
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <8192>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <40>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <16384>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <40>;
> >>> + mmu-type = "riscv,sv39";
> >>> + next-level-cache = <&ccache>;
> >>> + riscv,isa = "rv64imac_zba_zbb";
> >> 
> >> Hmm, based on what Sean said on the previous version, "We use strchr on
> >> it; so something like Zicsr is parsed as 5 extensions", are you sure that
> >> adding this here behaves correctly?
> >> 
> >
> > As you said, u-boot does not parse the content after '_', zba/zbb has
> > no practical meaning in u-boot. 
> 
> That's not what Sean's comment on the previous version said.
> If it is actually ignored, this is fine, but Sean's comment read like
> it would be misinterpreted by U-Boot.
> I'll have to go read the code.

Having gone and found the code in question, it does indeed look like it
stops at an _, supports_extension() in arch/riscv/cpu/cpu.c, so having
Zba and Zbb in the riscv,isa string is fine.
Apologies for the noise here, I must've misunderstood the comments on
the previous version.

Cheers,
Conor.


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Re: [PATCH] timer: fttmr010: return a previously deleted driver now ported to DM

[Tom Rini]

On Mon, Feb 13, 2023 at 08:34:36PM +0300, Sergei Antonov wrote:

> The fttmr010 timer driver was deleted by
> commit 29fc6f24926e ("ARM: remove a320evb board support")
> The original source file was: arch/arm/cpu/arm920t/a320/timer.c
> 
> Return the driver to the codebase in a DM compatible form.
> A platform using fttmr010 will be submitted later.
> 
> This hardware is described in the datasheet [1], starting from page 348.
> According to the datasheet, there is a Revision Register at offset 0x3C,
> which is not present in 'struct fttmr010'. Add it and debug() print
> revision in probe function.
> 
> [1]
> https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
> 
> Signed-off-by: Sergei Antonov 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] am62a7: dts: Enable full 4GB LPDDR4

[Tom Rini]

On Mon, Feb 06, 2023 at 05:04:51PM +0530, Devarsh Thakkar wrote:

> AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
> but only 2GB was enabled early.
> 
> Enable full 4GB memory by updating the latter 2GB memory region
> which gets mapped to 0x088000 i.e. DDR16SS0_SDRAM as referred in
> Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].
> 
> [1] : https://www.ti.com/lit/zip/spruj16
> Logs: https://gist.github.com/devarsht/e85b6af89c01ddadb3a62f3e5f196af8
> 
> Signed-off-by: Devarsh Thakkar 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] ARM: dts: uniphier: Sync DT with Linux v6.2

[Tom Rini]

On Tue, Feb 28, 2023 at 11:37:09AM +0900, Kunihiko Hayashi wrote:

> Synchronize devicetree sources with Linux v6.2.
> 
> - Use GIC interrupt definitions
> - Add reg properties in USB-glue and SoC-glue node
> - Fix node names to follow the generic names list in DT specification
> - Add L2 cache and AHCI nodes
> - Update nand and pcie nodes
> - And some trivial fixes
> 
> Signed-off-by: Kunihiko Hayashi 
> Acked-by: Marek Vasut 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] ARM: dts: uniphier: Switch USB node to the original

[Tom Rini]

On Tue, Feb 28, 2023 at 11:37:08AM +0900, Kunihiko Hayashi wrote:

> UniPhier DT applies its own USB node for U-Boot due to the USB driver
> constrains. After solving this issue, u-boot allows the original USB node.
> 
> After switching USB node, synchronization of USB node with Linux becomes
> possible.
> 
> Signed-off-by: Kunihiko Hayashi 
> Acked-by: Marek Vasut 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] powerpc, mpc83xx: Remove CONFIG_ELBC_BRx_ORx

[Tom Rini]

On Sun, Feb 26, 2023 at 10:44:09AM +0100, Christophe Leroy wrote:

> Commit fe7d654d04 ("mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to
> Kconfig") converted CONFIG_SYS_{BRx/ORx}_PRELIM to Kconfig by
> implementing a fine-grained selection of every bit in Kconfig.
> 
> But commit c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to
> Kconfig") reworked it so that you now just have to provide the raw
> value of each register in Kconfig. However, all fine-grained
> Kconfig items remained allthough they are not used anymore.
> 
> Remove them all.
> 
> Fixes: c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig")
> Signed-off-by: Christophe Leroy 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 2/2] configs: j7200: Merge HS and non-HS defconfigs

[Tom Rini]

On Fri, Feb 24, 2023 at 10:37:49AM +0530, Manorit Chawdhry wrote:

> K3 devices have runtime type board detection. Make the default defconfig
> include the secure configuration. Then remove the HS specific config.
> 
> Non-HS devices will continue to boot due to runtime device type detection.
> If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
> devices these can be ignored.
> 
> Signed-off-by: Manorit Chawdhry 
> Acked-by: Andrew Davis 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 1/2] configs: j721s2: merge HS and non-HS defconfigs

[Tom Rini]

On Fri, Feb 24, 2023 at 10:37:48AM +0530, Manorit Chawdhry wrote:

> K3 devices have runtime type board detection. Make the default defconfig
> include the secure configuration. Then remove the HS specific config.
> 
> Non-HS devices will continue to boot due to runtime device type detection.
> If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
> devices these can be ignored.
> 
> Signed-off-by: Manorit Chawdhry 
> Acked-by: Andrew Davis 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] mmc: remove SDHCI SPEAR

[Tom Rini]

On Wed, Feb 22, 2023 at 08:19:59PM +0100, Patrick Delaunay wrote:

> As the file spear_sdhci.c file is already removed, delete the associated
> configuration CONFIG_MMC_SDHCI_SPEAR.
> 
> Fixes: c942fc925e7dab ("mmc: spear: remove the entire spear_sdhci.c file")
> Signed-off-by: Patrick Delaunay 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] ARM: remove SPEAR entry in makefile

[Tom Rini]

On Wed, Feb 22, 2023 at 08:19:58PM +0100, Patrick Delaunay wrote:

> As the lastest spear directories are removed, delete the associated entry
> in Makefile.
> 
> Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr 
> support")
> Signed-off-by: Patrick Delaunay 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] clk: ast2600: Keep PLL power on

[Tom Rini]

On Tue, Feb 21, 2023 at 09:01:10PM +0800, Dylan Hung wrote:

> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
> 
> Signed-off-by: Dylan Hung 
> Reviewed-by: Joel Stanley 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] ram: ast2600: Keep MPLL power on

[Tom Rini]

On Tue, Feb 21, 2023 at 09:01:09PM +0800, Dylan Hung wrote:

> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
> 
> Signed-off-by: Dylan Hung 
> Reviewed-by: Joel Stanley 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] configs: evb-ast2600: Enable configs to store env in SPI

[Tom Rini]

On Fri, Feb 10, 2023 at 03:41:53PM +0800, Ryan Chen wrote:

> Enable defconfigs relevant for storing env on SPI flash.
> 
> Signed-off-by: Ryan Chen 
> Reviewed-by: Chia-Wei Wang 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] arm64: Reduce PT size estimation complexity

[Tom Rini]

On Tue, Feb 14, 2023 at 09:38:14PM +0800, Ying-Chun Liu (PaulLiu) wrote:

> From: Marc Zyngier 
> 
> count_required_pts()'s complexity is high if mappings are not using the
> largest possible block size (due to some other requirement such as tracking
> dirty pages, for example).
> 
> Let's switch to a method that follows the pattern established with
> the add_map() helper, and make it almost instantaneous instead of
> taking a large amount of time if 2MB mappings are in use instead of
> 1GB.
> 
> Signed-off-by: Marc Zyngier 
> Signed-off-by: Pierre-Clément Tosi 
> [ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
>   upstream ]
> Signed-off-by: Ying-Chun Liu (PaulLiu) 
> Cc: Tom Rini 
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/5d756d147e31a1cdaaa261a50e526404ca5968f5
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/6be9330601d81545c7c941e3609f35bf68a09059

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] arm64: Reduce add_map() complexity

[Tom Rini]

On Tue, Feb 14, 2023 at 09:38:13PM +0800, Ying-Chun Liu (PaulLiu) wrote:

> From: Marc Zyngier 
> 
> In the add_map() function, for each level it populates, it iterates from
> the root of the PT tree, making it ineficient if a mapping needs to occur
> past level 1.
> 
> Instead, replace it with a recursive (and much simpler) algorithm
> that keeps the complexity as low as possible. With this, mapping
> 512GB at level 2 goes from several seconds down to not measurable
> on an A55 machine.
> 
> We keep the block mappings at level 1 for now though.
> 
> Signed-off-by: Marc Zyngier 
> Signed-off-by: Pierre-Clément Tosi 
> [ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
>   upstream ]
> Signed-off-by: Ying-Chun Liu (PaulLiu) 
> Cc: Tom Rini 
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/96ad729cf4cab53bdff8222bb3eb256f38b5c3a6
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/6be9330601d81545c7c941e3609f35bf68a09059

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 2/2] arm64: Initialize TLB memory if CMO_BY_VA_ONLY

[Tom Rini]

On Thu, Feb 09, 2023 at 04:54:28AM +0800, Ying-Chun Liu (PaulLiu) wrote:

> From: Pierre-Clément Tosi 
> 
> Memory used to hold the page tables is allocated from the top of RAM
> with no prior initialization and could therefore hold invalid data. As
> invalidate_dcache_all() will be called before the MMU has been
> initialized and as that function relies indirectly on the page tables
> when using CMO_BY_VA_ONLY, these must be in a valid state from their
> allocation.
> 
> Signed-off-by: Pierre-Clément Tosi 
> [ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased
>   to the upstream. ]
> Signed-off-by: Ying-Chun Liu (PaulLiu) 
> Cc: Tom Rini 
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/e3ceef4230b772186c6853cace4a676a407e6ab7

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2 1/2] arm: cpu: Add optional CMOs by VA

[Tom Rini]

On Thu, Feb 09, 2023 at 04:54:27AM +0800, Ying-Chun Liu (PaulLiu) wrote:

> From: Marc Zyngier 
> 
> Exposing set/way cache maintenance to a virtual machine is unsafe, not
> least because the instructions are not permission-checked but also
> because they are not broadcast between CPUs. Consequently, KVM traps and
> emulates such maintenance in the host kernel using by-VA operations and
> looping over the stage-2 page-tables. However, when running under
> protected KVM, these instructions are not able to be emulated and will
> instead result in an exception being delivered to the guest.
> 
> Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select
> this option and perform by-VA cache maintenance instead of using the
> set/way instructions.
> 
> Signed-off-by: Marc Zyngier 
> Signed-off-by: Will Deacon 
> Signed-off-by: Pierre-Clément Tosi 
> [ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some
>   checkpatch warnings. Rebased to upstream. ]
> Signed-off-by: Ying-Chun Liu (PaulLiu) 
> Cc: Tom Rini 
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/db5507f47f4f57f766d52f753ff2cc761afc213b
> Link: 
> https://android.googlesource.com/platform/external/u-boot/+/2baf54e743380a1e4a6bc2dbdde020a2e783ff67

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] riscv: semihosting: replace inline assembly with assembly file

[Tom Rini]

On Tue, Feb 07, 2023 at 03:21:05PM +, Andre Przywara wrote:

> So far we used inline assembly to inject the actual instruction that
> triggers the semihosting service. While this sounds elegant, as it's
> really only about a few instructions, it has some serious downsides:
> - We need some barriers in place to force the compiler to issue writes
>   to a data structure before issuing the trap instruction.
> - We need to convince the compiler to actually fill the structures that
>   we use pointers to.
> - We need a memory clobber to avoid the compiler caching the data in
>   those structures, when semihosting writes data back.
> - We need register arguments to make sure the function ID and the
>   pointer land in the right registers.
> 
> This is all doable, but fragile and somewhat cumbersome. Since we now
> have a separate function in an extra file anyway, we can do away with
> all the magic and just write that in an actual assembler.
> This is much more readable and robust.
> 
> Signed-off-by: Andre Przywara 
> Reviewed-by: Sean Anderson 

After correcting the style on the SPDX header of the new .S file,
applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] arm: semihosting: replace inline assembly with assembly file

[Tom Rini]

On Tue, Feb 07, 2023 at 03:21:04PM +, Andre Przywara wrote:

> So far we used inline assembly to inject the actual instruction that
> triggers the semihosting service. While this sounds elegant, as it's
> really only about one instruction, it has some serious downsides:
> - We need some barriers in place to force the compiler to issue writes
>   to a data structure before issuing the trap instruction.
> - We need to convince the compiler to actually fill the structures that
>   we use pointers to.
> - We need a memory clobber to avoid the compiler caching the data in
>   those structures, when semihosting writes data back.
> - We need register arguments to make sure the function ID and the
>   pointer land in the right registers.
> 
> This is all doable, but fragile and somewhat cumbersome. Since we now
> have a separate function in an extra file anyway, we can do away with
> all the magic and just write that in an actual assembly file.
> This is much more readable and robust.
> 
> Signed-off-by: Andre Przywara 
> Reviewed-by: Sean Anderson 

Applied to u-boot/next, thanks!

-- 
Tom


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Please pull u-boot-video/next

[Anatolij Gustschin]

Hi Tom,

please pull video patches for next.

CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/15482

Thanks,
Anatolij

The following changes since commit d1653548d29959a6ea6b4037a00b48a28257e6e6:

  Merge branch '2023-03-02-kconfig-and-CONFIG-cleanups' into next (2023-03-03 
12:48:23 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-video.git tags/next-20230307

for you to fetch changes up to 72471620e82758b6cbdb9f70d775c0c18b043794:

  video console: add 12x22 console simple font test (2023-03-07 16:00:18 +0100)


 - video console refactoring and optimization
 - support for fonts wider than 1 byte
 - use named header for 8x16 font data
 - support multiple fonts configuration
 - move get_font_size() to truetype driver ops
 - support font size configuration at runtime
 - add 16x32 Terminus font from linux
 - add 12x22 Sun font from linux
 - add 12x22 console simple font test


Dzmitry Sankouski (10):
  video console: refactoring and optimization
  video console: add support for fonts wider than 1 byte
  video console: move 8x16 font data in named header
  video console: implement multiple fonts configuration
  video console: move vidconsole_get_font_size() logic to driver ops
  video console: allow font size configuration at runtime
  video console: add 12x22 Sun font from linux
  video console: add 16x32 Terminus font from linux
  video console: sandbox: add 12x22 font defconfigs
  video console: add 12x22 console simple font test

 cmd/Kconfig |8 +
 cmd/Makefile|2 +-
 cmd/font.c  |6 +-
 common/splash.c |8 +-
 configs/sandbox_defconfig   |1 +
 configs/sandbox_flattree_defconfig  |1 +
 drivers/video/Kconfig   |   30 +
 drivers/video/Makefile  |6 +
 drivers/video/console_core.c|  212 ++
 drivers/video/console_normal.c  |  177 +-
 drivers/video/console_rotate.c  |  371 +--
 drivers/video/console_truetype.c|3 +-
 drivers/video/vidconsole-uclass.c   |   11 +
 drivers/video/vidconsole_internal.h |  120 +
 include/video_console.h |   17 +-
 include/video_font.h|   31 +-
 include/video_font_4x6.h|   11 +-
 include/video_font_8x16.h   | 4624 ++
 include/video_font_data.h   | 4644 +-
 include/video_font_sun12x22.h   | 6158 +++
 include/video_font_ter16x32.h   | 2062 
 test/cmd/font.c |   13 +-
 test/dm/video.c |   41 +
 23 files changed, 13513 insertions(+), 5044 deletions(-)
 create mode 100644 drivers/video/console_core.c
 create mode 100644 drivers/video/vidconsole_internal.h
 create mode 100644 include/video_font_8x16.h
 create mode 100644 include/video_font_sun12x22.h
 create mode 100644 include/video_font_ter16x32.h

[PATCH v1 2/2] arm: dts: rockchip: rk3188-radxarock-u-boot: remove timer compatible replacement

[Johan Jonker]

The Rockchip timer driver has been renamed after the fall back compatible.
There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi
anymore, so remove.

Signed-off-by: Johan Jonker 
---
 arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi 
b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
index 9c9016de..de299598 100644
--- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -52,7 +52,6 @@
 };

 &timer3 {
-   compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
clock-frequency = <2400>;
u-boot,dm-spl;
 };
--
2.20.1

[PATCH v1 1/2] rockchip: timer: rockchip_timer: fix compatible and driver name

[Johan Jonker]

In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker 
---
 drivers/timer/rockchip_timer.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 62eacb98..e66c49aa 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;

 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 struct rockchip_timer_plat {
-   struct dtd_rockchip_rk3368_timer dtd;
+   struct dtd_rockchip_rk3288_timer dtd;
 };
 #endif

@@ -152,14 +152,12 @@ static const struct timer_ops rockchip_timer_ops = {
 };

 static const struct udevice_id rockchip_timer_ids[] = {
-   { .compatible = "rockchip,rk3188-timer" },
{ .compatible = "rockchip,rk3288-timer" },
-   { .compatible = "rockchip,rk3368-timer" },
{}
 };

-U_BOOT_DRIVER(rockchip_rk3368_timer) = {
-   .name   = "rockchip_rk3368_timer",
+U_BOOT_DRIVER(rockchip_rk3288_timer) = {
+   .name   = "rockchip_rk3288_timer",
.id = UCLASS_TIMER,
.of_match = rockchip_timer_ids,
.probe = rockchip_timer_probe,
--
2.20.1

Re: [PATCH v8 04/10] video console: implement multiple fonts configuration

[Anatolij Gustschin]

On Tue,  7 Mar 2023 13:21:14 +0300
Dzmitry Sankouski dsankou...@gmail.com wrote:
...
> @@ -138,13 +139,15 @@ void splash_display_banner(void)
>   if (ret)
>   return;
>  
> -#ifdef CONFIG_VIDEO_LOGO
> - col = BMP_LOGO_WIDTH / VIDEO_FONT_WIDTH + 1;
> - row = BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT + 1;
> -#else
> - col = 0;
> - row = 0;
> -#endif
> + if (IS_ENABLED(CONFIG_VIDEO_LOGO)) {
> + struct video_fontdata *fontdata = fonts;
> +
> + col = BMP_LOGO_WIDTH / fontdata->width + 1;
> + row = BMP_LOGO_HEIGHT / fontdata->height + 1;
> + } else {
> + col = 0;
> + row = 0;
> + }

there was another build error for boards with CONFIG_VIDEO_LOGO
disabled:

 https://source.denx.de/u-boot/custodians/u-boot-video/-/jobs/589501#L1430

I changed this to

 void splash_display_banner(void)
 {
+   struct video_fontdata __maybe_unused *fontdata = fonts;
struct udevice *dev;
char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
int col, row, ret;
@@ -138,9 +140,9 @@ void splash_display_banner(void)
if (ret)
return;
 
-#ifdef CONFIG_VIDEO_LOGO
-   col = BMP_LOGO_WIDTH / VIDEO_FONT_WIDTH + 1;
-   row = BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT + 1;
+#if IS_ENABLED(CONFIG_VIDEO_LOGO)
+   col = BMP_LOGO_WIDTH / fontdata->width + 1;
+   row = BMP_LOGO_HEIGHT / fontdata->height + 1;
 #else
col = 0;
row = 0;

--
Anatolij

Re: [PATCH 0/4] Fix arasan nand driver issues

[Michal Simek]

Hi,

On 3/7/23 15:02, Michael Nazzareno Trimarchi wrote:

Hi


On Tue, Mar 7, 2023 at 2:35 PM Michal Simek > wrote:




On 2/24/23 06:07, Ashok Reddy Soma wrote:
 > In this patch series
 >   - Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options
 >   - Find and update nand ofnode.
 >   - Fix nand node in zynqmp-zc1751-xm017-dc3.dts file
 >   - Enable nand-on-flash-bbt flag in zynqmp DT's by default
 >


If we are not fast to pick our part, please ping us

Thank you to pick them anyway
I am normally taking patches related to Xilinx/AMD SOCs and these 2 were quite 
simply.
Anyway Ashok told me that nand core is kind of our sync from upstream kernel. Do 
you have any plan to sync changes from the kernel back to U-Boot?


Thanks,
Michal

Re: [PATCH 0/4] Fix arasan nand driver issues

[Michael Nazzareno Trimarchi]

Hi


On Tue, Mar 7, 2023 at 2:35 PM Michal Simek  wrote:

>
>
> On 2/24/23 06:07, Ashok Reddy Soma wrote:
> > In this patch series
> >   - Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options
> >   - Find and update nand ofnode.
> >   - Fix nand node in zynqmp-zc1751-xm017-dc3.dts file
> >   - Enable nand-on-flash-bbt flag in zynqmp DT's by default
> >
>

If we are not fast to pick our part, please ping us

Thank you to pick them anyway

Michael


> >
> > Ashok Reddy Soma (4):
> >mtd: nand: arasan: Remove hardcoded bbt option
> >mtd: nand: arasan: Set ofnode value
> >arm64: dts: zynqmp: Fix nand dt node
> >arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default
> >
> >   arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts |   2 +
> >   arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 119 ++-
> >   drivers/mtd/nand/raw/arasan_nfc.c|   5 +-
> >   3 files changed, 78 insertions(+), 48 deletions(-)
> >
>
> Applied,
> M
>


-- 
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__

Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com

Re: [PATCH v1] clk: nuvoton: add read only feature for clk driver

[Sean Anderson]

On 3/7/23 03:13, Jim Liu wrote:

Set ahb/apb/fiu clock divider as read-only


Are these read-only in hardware, or is there some other reason?

--Sean


Signed-off-by: Jim Liu 
---
  drivers/clk/nuvoton/clk_npcm.c| 15 ---
  drivers/clk/nuvoton/clk_npcm.h|  1 +
  drivers/clk/nuvoton/clk_npcm8xx.c | 12 ++--
  3 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c
index 8d71f2a24b..18cb9cddbf 100644
--- a/drivers/clk/nuvoton/clk_npcm.c
+++ b/drivers/clk/nuvoton/clk_npcm.c
@@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk)
return div;
  }
  
-static u32 npcm_clk_set_div(struct clk *clk, u32 div)

+static int npcm_clk_set_div(struct clk *clk, u32 div)
  {
struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
struct npcm_clk_div *divider;
@@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
if (!divider)
return -EINVAL;
  
+	if (divider->flags & DIV_RO)

+   return 0;
+
if (divider->flags & PRE_DIV2)
div = div >> 1;
  
@@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)

else
clkdiv = ilog2(div);
  
+	if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) {

+   printf("clkdiv(%d) for clk(%ld) is over limit\n",
+  clkdiv, clk->id);
+   return -EINVAL;
+   }
+
val = readl(priv->base + divider->reg);
val &= ~divider->mask;
val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
@@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
if (ret)
return ret;
  
-	debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div);

-   return (parent_rate / div);
+   debug("%s: rate %lu, new rate %lu\n", __func__, rate, 
npcm_clk_get_rate(clk));
+   return npcm_clk_get_rate(clk);
  }
  
  static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)

diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h
index 06b60dc8b8..b4726d8381 100644
--- a/drivers/clk/nuvoton/clk_npcm.h
+++ b/drivers/clk/nuvoton/clk_npcm.h
@@ -50,6 +50,7 @@
  #define PRE_DIV2  BIT(2)  /* Pre divisor = 2 */
  #define POST_DIV2 BIT(3)  /* Post divisor = 2 */
  #define FIXED_PARENT  BIT(4)  /* clock source is fixed */
+#define DIV_RO BIT(5)  /* divider is read-only */
  
  /* Parameters of PLL configuration */

  struct npcm_clk_pll {
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c 
b/drivers/clk/nuvoton/clk_npcm8xx.c
index 27e3cfcf55..d1b32e3237 100644
--- a/drivers/clk/nuvoton/clk_npcm8xx.c
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = {
  };
  
  static struct npcm_clk_div npcm8xx_clk_dividers[] = {

-   {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2},
-   {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2},
-   {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2},
-   {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1},
-   {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1},
-   {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1},
+   {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO},
+   {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO},
+   {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO},
+   {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO},
+   {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO},
+   {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO},
{NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
{NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
{NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1},

[PATCH v8 08/10] video console: add 16x32 Terminus font from linux

[Dzmitry Sankouski]

Modern mobile phones typically have high pixel density.
Bootmenu is hardly readable on those with 8x16 font.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 
---

Changes in v8:
none

Changes in v7:
none

Changes in v6:
rebase only

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
none

Changes in v2:
- edit for runtime configuration

 drivers/video/Kconfig |7 +
 include/video_font.h  |6 +
 include/video_font_ter16x32.h | 2062 +
 3 files changed, 2075 insertions(+)
 create mode 100644 include/video_font_ter16x32.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index a928ae498a..60f4a4bf9c 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -38,6 +38,13 @@ config VIDEO_FONT_SUN12X22
  Provides character bitmap data in header file.
  When selecting multiple fonts, you may want to enable CMD_SELECT_FONT 
too.
 
+config VIDEO_FONT_16X32
+   bool "16 x 32 font size"
+   help
+ Font for video console driver, 16 x 32 pixels
+ Provides character bitmap data in header file.
+ When selecting multiple fonts, you may want to enable CMD_SELECT_FONT 
too.
+
 config VIDEO_LOGO
bool "Show the U-Boot logo on the display"
default y if !SPLASH_SCREEN
diff --git a/include/video_font.h b/include/video_font.h
index f354d0cc4d..05d3f989a7 100644
--- a/include/video_font.h
+++ b/include/video_font.h
@@ -18,6 +18,9 @@
 #if defined(CONFIG_VIDEO_FONT_SUN12X22)
 #include 
 #endif
+#if defined(CONFIG_VIDEO_FONT_16X32)
+#include 
+#endif
 
 static struct video_fontdata __maybe_unused fonts[] = {
 #if defined(CONFIG_VIDEO_FONT_8X16)
@@ -28,6 +31,9 @@ static struct video_fontdata __maybe_unused fonts[] = {
 #endif
 #if defined(CONFIG_VIDEO_FONT_SUN12X22)
FONT_ENTRY(12, 22, 12x22),
+#endif
+#if defined(CONFIG_VIDEO_FONT_16X32)
+   FONT_ENTRY(16, 32, 16x32),
 #endif
{/* list terminator */}
 };
diff --git a/include/video_font_ter16x32.h b/include/video_font_ter16x32.h
new file mode 100644
index 00..bcf3d4b123
--- /dev/null
+++ b/include/video_font_ter16x32.h
@@ -0,0 +1,2062 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copied from linux.
+ */
+
+#ifndef _VIDEO_FONT_TER_16X32_
+#define _VIDEO_FONT_TER_16X32_
+
+#include 
+
+static unsigned char video_fontdata_16x32[VIDEO_FONT_SIZE(256, 16, 32)] = {
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 0x7f, 0xfc,
+   0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
+   0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
+   0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
+   0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
+   0x7f, 0xfc, 0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x7f, 0xfc,
+   0xf0, 0x1e, 0xe0, 0x0e, 0xe0, 0x0e, 0xe0, 0x0e,
+   0xee, 0xee, 0xee, 0xee, 0xe0, 0x0e, 0xe0, 0x0e,
+   0xe0, 0x0e, 0xe0, 0x0e, 0xef, 0xee, 0xe7, 0xce,
+   0xe0, 0x0e, 0xe0, 0x0e, 0xe0, 0x0e, 0xf0, 0x1e,
+   0x7f, 0xfc, 0x3f, 0xf8, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 1 */
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x7f, 0xfc,
+   0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe,
+   0xe3, 0x8e, 0xe3, 0x8e, 0xff, 0xfe, 0xff, 0xfe,
+   0xff, 0xfe, 0xff, 0xfe, 0xe0, 0x0e, 0xf0, 0x1e,
+   0xf8, 0x3e, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe,
+   0x7f, 0xfc, 0x3f, 0xf8, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 */
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x78, 0x3c, 0xfc, 0x7e, 0xfe, 0xfe, 0xff, 0xfe,
+   0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe,
+   0x7f, 0xfc, 0x7f, 0xfc, 0x3f, 0xf8, 0x1f, 0xf0,
+   0x0f, 0xe0, 0x07, 0xc0, 0x03, 0x80, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 3 */
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x03, 0x80, 0x07, 0xc0, 0x0f, 0xe0,
+   0x1f, 0xf0, 0x3f, 0xf8, 0x7f, 0xfc, 0xff, 0xfe,
+   0xff, 0xfe, 0x7f, 0xfc, 0x3f, 0xf8, 0x1f, 0xf0,
+   0x0f, 0xe0, 0x07, 0xc0, 0x03, 0x80, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 4 */
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x07, 0xc0, 0x0f, 0xe0,
+   0x0f, 0xe0, 0x0f, 0xe0, 0x0f, 0xe0, 0x0f, 0xe0,
+   0x07, 0xc0, 0x03, 0x80, 0x3b, 0xb8, 0x7f, 0xfc,
+   0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe,
+   0x7f, 0xfc, 0x3b, 0xb8, 0x03, 0

Re: [PATCH 0/4] Fix arasan nand driver issues

[Michal Simek]

On 2/24/23 06:07, Ashok Reddy Soma wrote:

In this patch series
  - Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options
  - Find and update nand ofnode.
  - Fix nand node in zynqmp-zc1751-xm017-dc3.dts file
  - Enable nand-on-flash-bbt flag in zynqmp DT's by default


Ashok Reddy Soma (4):
   mtd: nand: arasan: Remove hardcoded bbt option
   mtd: nand: arasan: Set ofnode value
   arm64: dts: zynqmp: Fix nand dt node
   arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default

  arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts |   2 +
  arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 119 ++-
  drivers/mtd/nand/raw/arasan_nfc.c|   5 +-
  3 files changed, 78 insertions(+), 48 deletions(-)



Applied,
M

Re: [PATCH v2] spi: xilinx_spi: Fix spi reset

[Michal Simek]

po 27. 2. 2023 v 18:17 odesílatel Jiajie Chen  napsal:
>
> It was incorrectly using an old priv->regs pointer, which was
> initialized to zero. SPI resets won't happen on first call.
>
> Signed-off-by: Jiajie Chen 
> ---
>  drivers/spi/xilinx_spi.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
> index 4e9115dafe..9e6255a172 100644
> --- a/drivers/spi/xilinx_spi.c
> +++ b/drivers/spi/xilinx_spi.c
> @@ -112,10 +112,9 @@ struct xilinx_spi_priv {
>  static int xilinx_spi_probe(struct udevice *bus)
>  {
> struct xilinx_spi_priv *priv = dev_get_priv(bus);
> -   struct xilinx_spi_regs *regs = priv->regs;
> -
> -   priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
> +   struct xilinx_spi_regs *regs;
>
> +   regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
> priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
>
> writel(SPISSR_RESET_VALUE, ®s->srr);
> --
> 2.30.2
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

[PATCH v3] pinctrl: rockchip: support rk3588 pinctrl

[Eugen Hristev]

From: Jianqun Xu 

Add support for Rockchip rk3588 variant of pinctrl.

The driver is adapted from the Linux driver.

Signed-off-by: Jianqun Xu 
[eugen.hris...@collabora.com:
port to latest U-boot, bring more changes from Linux]
Signed-off-by: Eugen Hristev 
---
Changes in v3:
- change assert(i) to assert (i >= 0) because i==0 is a valid number it's
the first entry in the array. Otherwise it would assert wrongly when setting
gpio 0 A2 e.g.

Changes in v2:
- change the way the reg is computed to align with Linux
- For the gpio4 bank D0-8, as the downstream uboot uses VCCIO6 instead of
VCCIO2, change accordingly, otherwise D0-D5 pins won't work to set PUP/PDOWN,
DS, etc. It appears gpio4D has the registers just after gpio4A,gpio4B,gpio4C
in the same VCCIO6, and not in VCCIO2.

 drivers/pinctrl/rockchip/Makefile   |   1 +
 drivers/pinctrl/rockchip/pinctrl-rk3588.c   | 347 
 drivers/pinctrl/rockchip/pinctrl-rockchip.h | 187 +++
 3 files changed, 535 insertions(+)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3588.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 90461ae8819a..c91f650b0434 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
 obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
new file mode 100644
index ..fc373989a20c
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-rockchip.h"
+#include 
+
+static int rk3588_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+   struct rockchip_pinctrl_priv *priv = bank->priv;
+   struct regmap *regmap;
+   int iomux_num = (pin / 8);
+   int reg, ret, mask;
+   u8 bit;
+   u32 data;
+
+   debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+   regmap = priv->regmap_base;
+   reg = bank->iomux[iomux_num].offset;
+   if ((pin % 8) >= 4)
+   reg += 0x4;
+   bit = (pin % 4) * 4;
+   mask = 0xf;
+
+   if (bank->bank_num == 0) {
+   if (pin >= RK_PB4 && pin <= RK_PD7) {
+   if (mux < 8) {
+   reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
+   data = (mask << (bit + 16));
+   data |= (mux & mask) << bit;
+   ret = regmap_write(regmap, reg, data);
+   } else {
+   u32 reg0 = 0;
+
+   reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+   data = (mask << (bit + 16));
+   data |= 8 << bit;
+   ret = regmap_write(regmap, reg0, data);
+
+   reg0 = reg + 0x8000; /* BUS_IOC_BASE */
+   data = (mask << (bit + 16));
+   data |= mux << bit;
+   regmap = priv->regmap_base;
+   regmap_write(regmap, reg0, data);
+   }
+   } else {
+   data = (mask << (bit + 16));
+   data |= (mux & mask) << bit;
+   ret = regmap_write(regmap, reg, data);
+   }
+   return ret;
+   } else if (bank->bank_num > 0) {
+   reg += 0x8000; /* BUS_IOC_BASE */
+   }
+
+   data = (mask << (bit + 16));
+   data |= (mux & mask) << bit;
+
+   return regmap_write(regmap, reg, data);
+}
+
+#define RK3588_PMU1_IOC_REG(0x)
+#define RK3588_PMU2_IOC_REG(0x4000)
+#define RK3588_BUS_IOC_REG (0x8000)
+#define RK3588_VCCIO1_4_IOC_REG(0x9000)
+#define RK3588_VCCIO3_5_IOC_REG(0xA000)
+#define RK3588_VCCIO2_IOC_REG  (0xB000)
+#define RK3588_VCCIO6_IOC_REG  (0xC000)
+#define RK3588_EMMC_IOC_REG(0xD000)
+
+static const u32 rk3588_ds_regs[][2] = {
+   {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
+   {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
+   {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
+   {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
+   {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
+   {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
+   {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
+ 

[PATCH v8 09/10] video console: sandbox: add 12x22 font defconfigs

[Dzmitry Sankouski]

Add 12x22 font in order to write a test for it.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 
---

Changes in v8:
- add 12X22 font in sandbox_flattree_defconfig for tests

Changes in v7:
none

Changes in v6:
N/A

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
N/A

Changes in v2:
N/A

 configs/sandbox_defconfig  | 1 +
 configs/sandbox_flattree_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 77ade1f1d8..a0fbdad20a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -298,6 +298,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_FONT_SUN12X22=y
 CONFIG_VIDEO_COPY=y
 CONFIG_CONSOLE_ROTATION=y
 CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/sandbox_flattree_defconfig 
b/configs/sandbox_flattree_defconfig
index 5366b1ff1d..84d9da8184 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -206,6 +206,7 @@ CONFIG_USB=y
 CONFIG_USB_EMUL=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_FONT_SUN12X22=y
 CONFIG_CONSOLE_ROTATION=y
 CONFIG_CONSOLE_TRUETYPE=y
 CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
-- 
2.30.2

[PATCH v8 10/10] video console: add 12x22 console simple font test

[Dzmitry Sankouski]

Tests fonts wider than a byte.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 
---

Changes in v8:
none

Changes in v7:
none

Changes in v6:
- rebase
- move sandbox defconfig change to separate patch
- run savedefconfig

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v2:
N/A
none

 test/dm/video.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/test/dm/video.c b/test/dm/video.c
index 17a33cc7af..30778157d9 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -151,6 +151,8 @@ static int dm_test_video_text(struct unit_test_state *uts)
 
ut_assertok(select_vidconsole(uts, "vidconsole0"));
ut_assertok(video_get_nologo(uts, &dev));
+   ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+   ut_assertok(vidconsole_select_font(con, "8x16", 0));
ut_asserteq(46, compress_frame_buffer(uts, dev));
 
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
@@ -175,6 +177,42 @@ static int dm_test_video_text(struct unit_test_state *uts)
 }
 DM_TEST(dm_test_video_text, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
 
+static int dm_test_video_text_12x22(struct unit_test_state *uts)
+{
+   struct udevice *dev, *con;
+   int i;
+
+#define WHITE  0x
+#define SCROLL_LINES   100
+
+   ut_assertok(select_vidconsole(uts, "vidconsole0"));
+   ut_assertok(video_get_nologo(uts, &dev));
+   ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+   ut_assertok(vidconsole_select_font(con, "12x22", 0));
+   ut_asserteq(46, compress_frame_buffer(uts, dev));
+
+   ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+   vidconsole_putc_xy(con, 0, 0, 'a');
+   ut_asserteq(89, compress_frame_buffer(uts, dev));
+
+   vidconsole_putc_xy(con, 0, 0, ' ');
+   ut_asserteq(46, compress_frame_buffer(uts, dev));
+
+   for (i = 0; i < 20; i++)
+   vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
+   ut_asserteq(363, compress_frame_buffer(uts, dev));
+
+   vidconsole_set_row(con, 0, WHITE);
+   ut_asserteq(46, compress_frame_buffer(uts, dev));
+
+   for (i = 0; i < 20; i++)
+   vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
+   ut_asserteq(363, compress_frame_buffer(uts, dev));
+
+   return 0;
+}
+DM_TEST(dm_test_video_text_12x22, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
 /* Test handling of special characters in the console */
 static int dm_test_video_chars(struct unit_test_state *uts)
 {
@@ -184,6 +222,7 @@ static int dm_test_video_chars(struct unit_test_state *uts)
ut_assertok(select_vidconsole(uts, "vidconsole0"));
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+   ut_assertok(vidconsole_select_font(con, "8x16", 0));
vidconsole_put_string(con, test_string);
ut_asserteq(466, compress_frame_buffer(uts, dev));
 
@@ -201,6 +240,7 @@ static int dm_test_video_ansi(struct unit_test_state *uts)
ut_assertok(select_vidconsole(uts, "vidconsole0"));
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+   ut_assertok(vidconsole_select_font(con, "8x16", 0));
 
/* reference clear: */
video_clear(con->parent);
@@ -249,6 +289,7 @@ static int check_vidconsole_output(struct unit_test_state 
*uts, int rot,
 
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+   ut_assertok(vidconsole_select_font(con, "8x16", 0));
ut_asserteq(46, compress_frame_buffer(uts, dev));
 
/* Check display wrap */
-- 
2.30.2

[PATCH v8 05/10] video console: move vidconsole_get_font_size() logic to driver ops

[Dzmitry Sankouski]

Since multiple vidconsole drivers exists, vidconsole_get_font_size()
implementation cannot longer live in vidconsole_uclass.c file.

Move current vidconsole_get_font_size logic to truetype driver ops.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 
---

Changes in v8:
none

Changes in v7:
N/A

Changes in v6:
N/A

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
N/A

Changes in v2:
N/A

 cmd/font.c|  6 +-
 drivers/video/console_truetype.c  |  3 ++-
 drivers/video/vidconsole-uclass.c | 11 +++
 include/video_console.h   | 14 --
 test/cmd/font.c   | 13 +++--
 5 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/cmd/font.c b/cmd/font.c
index 7b4347f32b..fe2d65caaf 100644
--- a/cmd/font.c
+++ b/cmd/font.c
@@ -61,7 +61,11 @@ static int do_font_size(struct cmd_tbl *cmdtp, int flag, int 
argc,
 
if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev))
return CMD_RET_FAILURE;
-   font_name = vidconsole_get_font_size(dev, &size);
+   ret = vidconsole_get_font_size(dev, &font_name, &size);
+   if (ret) {
+   printf("Failed (error %d)\n", ret);
+   return CMD_RET_FAILURE;
+   }
 
size = dectoul(argv[1], NULL);
 
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 9cac9a6de4..6b5390136a 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -724,7 +724,7 @@ static int truetype_select_font(struct udevice *dev, const 
char *name,
return 0;
 }
 
-const char *vidconsole_get_font_size(struct udevice *dev, uint *sizep)
+const char *console_truetype_get_font_size(struct udevice *dev, uint *sizep)
 {
struct console_tt_priv *priv = dev_get_priv(dev);
struct console_tt_metrics *met = priv->cur_met;
@@ -773,6 +773,7 @@ struct vidconsole_ops console_truetype_ops = {
.backspace  = console_truetype_backspace,
.entry_start= console_truetype_entry_start,
.get_font   = console_truetype_get_font,
+   .get_font_size  = console_truetype_get_font_size,
.select_font= truetype_select_font,
 };
 
diff --git a/drivers/video/vidconsole-uclass.c 
b/drivers/video/vidconsole-uclass.c
index 72a13d3052..a5f2350ca1 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -575,6 +575,17 @@ int vidconsole_get_font(struct udevice *dev, int seq,
return ops->get_font(dev, seq, info);
 }
 
+int vidconsole_get_font_size(struct udevice *dev, const char **name, uint 
*sizep)
+{
+   struct vidconsole_ops *ops = vidconsole_get_ops(dev);
+
+   if (!ops->get_font_size)
+   return -ENOSYS;
+
+   *name = ops->get_font_size(dev, sizep);
+   return 0;
+}
+
 int vidconsole_select_font(struct udevice *dev, const char *name, uint size)
 {
struct vidconsole_ops *ops = vidconsole_get_ops(dev);
diff --git a/include/video_console.h b/include/video_console.h
index 3e1e00c23f..770103284b 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -160,6 +160,15 @@ struct vidconsole_ops {
int (*get_font)(struct udevice *dev, int seq,
struct vidfont_info *info);
 
+   /**
+* get_font_size() - get the current font name and size
+*
+* @dev: vidconsole device
+* @sizep: Place to put the font size (nominal height in pixels)
+* Returns: Current font name
+*/
+   const char *(*get_font_size)(struct udevice *dev, uint *sizep);
+
/**
 * select_font() - Select a particular font by name / size
 *
@@ -303,9 +312,10 @@ void vidconsole_list_fonts(struct udevice *dev);
  *
  * @dev: vidconsole device
  * @sizep: Place to put the font size (nominal height in pixels)
- * Returns: Current font name
+ * @name: pointer to font name, a placeholder for result
+ * Return: 0 if OK, -ENOSYS if not implemented in driver
  */
-const char *vidconsole_get_font_size(struct udevice *dev, uint *sizep);
+int vidconsole_get_font_size(struct udevice *dev, const char **name, uint 
*sizep);
 
 #ifdef CONFIG_VIDEO_COPY
 /**
diff --git a/test/cmd/font.c b/test/cmd/font.c
index adb353965a..40682e5ce4 100644
--- a/test/cmd/font.c
+++ b/test/cmd/font.c
@@ -19,6 +19,7 @@
 static int font_test_base(struct unit_test_state *uts)
 {
struct udevice *dev;
+   const char *name;
int max_metrics;
uint size;
int ret;
@@ -32,8 +33,8 @@ static int font_test_base(struct unit_test_state *uts)
ut_assert_nextline("cantoraone_regular");
ut_assertok(ut_check_console_end(uts));
 
-   ut_asserteq_str("nimbus_sans_l_regular",
-   vidconsole_get_font_size(dev, &size));
+   ut_assertok(vidconsole_get_font_size(dev, &name, &size));
+   ut_asserteq_str("nimbus_sans_l_regular", name);
ut_asserteq(18, size);
 
max_metrics = 1;
@@ -5

[PATCH v8 04/10] video console: implement multiple fonts configuration

[Dzmitry Sankouski]

This needed for unit testing different fonts.

Configured fonts are placed in an array of fonts.
First font is selected by default upon console probe.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 

---

Changes in v8:
none

Changes in v7:
- place 8x16 font first in list as default
- &fonts[0] - fonts

Changes in v6:
rebase only

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
N/A

Changes in v2:
N/A

 common/splash.c | 17 +++---
 drivers/video/Kconfig   | 15 ++
 drivers/video/console_core.c| 81 +
 drivers/video/console_normal.c  | 32 +++-
 drivers/video/console_rotate.c  | 72 -
 drivers/video/vidconsole_internal.h | 20 ---
 include/video_font.h| 17 +-
 include/video_font_4x6.h| 11 ++--
 include/video_font_8x16.h   |  8 +--
 include/video_font_data.h   | 31 +++
 10 files changed, 207 insertions(+), 97 deletions(-)
 create mode 100644 include/video_font_data.h

diff --git a/common/splash.c b/common/splash.c
index 245ff680eb..c8f7ad98b3 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -127,6 +127,7 @@ void splash_get_pos(int *x, int *y)
 #include 
 #include 
 #include 
+#include 
 
 void splash_display_banner(void)
 {
@@ -138,13 +139,15 @@ void splash_display_banner(void)
if (ret)
return;
 
-#ifdef CONFIG_VIDEO_LOGO
-   col = BMP_LOGO_WIDTH / VIDEO_FONT_WIDTH + 1;
-   row = BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT + 1;
-#else
-   col = 0;
-   row = 0;
-#endif
+   if (IS_ENABLED(CONFIG_VIDEO_LOGO)) {
+   struct video_fontdata *fontdata = fonts;
+
+   col = BMP_LOGO_WIDTH / fontdata->width + 1;
+   row = BMP_LOGO_HEIGHT / fontdata->height + 1;
+   } else {
+   col = 0;
+   row = 0;
+   }
 
display_options_get_banner(false, buf, sizeof(buf));
vidconsole_position_cursor(dev, col, 1);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2a76d19cc8..ce97eb4727 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -16,6 +16,21 @@ config VIDEO
 
 if VIDEO
 
+config VIDEO_FONT_4X6
+   bool "4 x 6 font size"
+   help
+ Font for video console driver, 4 x 6 pixels.
+ Provides character bitmap data in header file.
+ When selecting multiple fonts, you may want to enable CMD_SELECT_FONT 
too.
+
+config VIDEO_FONT_8X16
+   bool "8 x 16 font size"
+   default y
+   help
+ Font for video console driver, 8 x 16 pixels
+ Provides character bitmap data in header file.
+ When selecting multiple fonts, you may want to enable CMD_SELECT_FONT 
too.
+
 config VIDEO_LOGO
bool "Show the U-Boot logo on the display"
default y if !SPLASH_SCREEN
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index de004f585c..d019b985b4 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -9,8 +9,41 @@
 #include 
 #include 
 #include 
+#include 
 #include "vidconsole_internal.h"
 
+/**
+ * console_set_font() - prepare vidconsole for chosen font.
+ *
+ * @devvidconsole device
+ * @fontdata   pointer to font data struct
+ */
+static int console_set_font(struct udevice *dev, struct video_fontdata 
*fontdata)
+{
+   struct console_simple_priv *priv = dev_get_priv(dev);
+   struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
+   struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+
+   debug("console_simple: setting %s font\n", fontdata->name);
+   debug("width: %d\n", fontdata->width);
+   debug("byte width: %d\n", fontdata->byte_width);
+   debug("height: %d\n", fontdata->height);
+
+   priv->fontdata = fontdata;
+   vc_priv->x_charsize = fontdata->width;
+   vc_priv->y_charsize = fontdata->height;
+   if (vid_priv->rot % 2) {
+   vc_priv->cols = vid_priv->ysize / fontdata->width;
+   vc_priv->rows = vid_priv->xsize / fontdata->height;
+   vc_priv->xsize_frac = VID_TO_POS(vid_priv->ysize);
+   } else {
+   vc_priv->cols = vid_priv->xsize / fontdata->width;
+   vc_priv->rows = vid_priv->ysize / fontdata->height;
+   }
+
+   return 0;
+}
+
 int check_bpix_support(int bpix)
 {
if (bpix == VIDEO_BPP8 && IS_ENABLED(CONFIG_VIDEO_BPP8))
@@ -43,7 +76,7 @@ inline void fill_pixel_and_goto_next(void **dstp, u32 value, 
int pbytes, int ste
 }
 
 int fill_char_vertically(uchar *pfont, void **line, struct video_priv 
*vid_priv,
-bool direction)
+struct video_fontdata *fontdata, bool direction)
 {
int step, line_step, pbytes, bitcount, width_remainder, ret;
void *dst;
@@ -61,17 +94,17 @@ int fill_char_vertically(uchar *pfont, void **line, struct 
video_priv *vid_priv,
 

[PATCH v8 06/10] video console: allow font size configuration at runtime

[Dzmitry Sankouski]

Allow font size configuration at runtime for console_simple.c
driver. This needed for unit testing different fonts.

Configuring is done by `font` command, also used for font
selection in true type console.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 
---

Changes in v8:
none

Changes in v7:
- (&fonts[seq])->name
- fonts[seq].name

Changes in v6:
rebase only

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
- move 8x16 font patch extracted
- implement multiple fonts patch extracted
- add static modifiers, where needed
- remove list fonts operation
- put fontdata in local var

Changes in v2:
N/A

 cmd/Kconfig |  8 
 cmd/Makefile|  2 +-
 drivers/video/Kconfig   |  1 +
 drivers/video/console_core.c| 30 +
 drivers/video/console_normal.c  |  3 +++
 drivers/video/console_rotate.c  |  9 +
 drivers/video/vidconsole_internal.h | 18 +
 7 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2caa4af71c..a3512836c1 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2226,6 +2226,14 @@ config CMD_VIDCONSOLE
  The name 'lcdputs' is a bit of a misnomer, but so named because the
  video device is often an LCD.
 
+config CMD_SELECT_FONT
+   bool "select font size"
+   depends on VIDEO
+   default n
+   help
+ Enabling this will provide 'font' command.
+ Allows font selection at runtime.
+
 endmenu
 
 source "cmd/ti/Kconfig"
diff --git a/cmd/Makefile b/cmd/Makefile
index 36d2daf22a..2d8bb4fc05 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -78,7 +78,7 @@ obj-$(CONFIG_CMD_EXT2) += ext2.o
 obj-$(CONFIG_CMD_FAT) += fat.o
 obj-$(CONFIG_CMD_FDT) += fdt.o
 obj-$(CONFIG_CMD_SQUASHFS) += sqfs.o
-obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o
+obj-$(CONFIG_CMD_SELECT_FONT) += font.o
 obj-$(CONFIG_CMD_FLASH) += flash.o
 obj-$(CONFIG_CMD_FPGA) += fpga.o
 obj-$(CONFIG_CMD_FPGAD) += fpgad.o
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ce97eb4727..e1bcc89b30 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -165,6 +165,7 @@ config CONSOLE_ROTATION
 
 config CONSOLE_TRUETYPE
bool "Support a console that uses TrueType fonts"
+   select CMD_SELECT_FONT
help
  TrueTrype fonts can provide outline-drawing capability rather than
  needing to provide a bitmap for each font and size that is needed.
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index d019b985b4..d4f79c656a 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -180,3 +180,33 @@ int console_probe(struct udevice *dev)
 {
return console_set_font(dev, fonts);
 }
+
+const char *console_simple_get_font_size(struct udevice *dev, uint *sizep)
+{
+   struct console_simple_priv *priv = dev_get_priv(dev);
+
+   *sizep = priv->fontdata->width;
+
+   return priv->fontdata->name;
+}
+
+int console_simple_get_font(struct udevice *dev, int seq, struct vidfont_info 
*info)
+{
+   info->name = fonts[seq].name;
+
+   return 0;
+}
+
+int console_simple_select_font(struct udevice *dev, const char *name, uint 
size)
+{
+   struct video_fontdata *font;
+
+   for (font = fonts; font->name; font++) {
+   if (!strcmp(name, font->name)) {
+   console_set_font(dev, font);
+   return 0;
+   }
+   };
+   printf("no such font: %s, make sure it's name has x 
format\n", name);
+   return -ENOENT;
+}
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 03e859898c..413c7abee9 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -101,6 +101,9 @@ struct vidconsole_ops console_ops = {
.putc_xy= console_putc_xy,
.move_rows  = console_move_rows,
.set_row= console_set_row,
+   .get_font_size  = console_simple_get_font_size,
+   .get_font   = console_simple_get_font,
+   .select_font= console_simple_select_font,
 };
 
 U_BOOT_DRIVER(vidconsole_normal) = {
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index b924bc3459..65358a1c6e 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -262,18 +262,27 @@ struct vidconsole_ops console_ops_1 = {
.putc_xy= console_putc_xy_1,
.move_rows  = console_move_rows_1,
.set_row= console_set_row_1,
+   .get_font_size  = console_simple_get_font_size,
+   .get_font   = console_simple_get_font,
+   .select_font= console_simple_select_font,
 };
 
 struct vidconsole_ops console_ops_2 = {
.putc_xy= console_putc_xy_2,
.move_rows  = console_move_rows_2,
.set_row= console_set_row_2,
+   .get_font_size  = console_simple_get_font_size,
+   .g

[PATCH v8 01/10] video console: refactoring and optimization

[Dzmitry Sankouski]

- move common code to vidconsole_internal.h and console_core.c
- unite probe functions
- get rid of code duplications in switch across bpp values
- extract common pixel fill logic in two functions one per
horizontal and vertical filling
- rearrange statements in put_xy* methods in unified way
- replace types - uint*_t to u*

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 

---

Changes in v8:
- fix build with disabled CONFIG_VIDEO_COPY
- add 12X22 font to sandox defconfig
- fix build with disabled CONFIG_VIDEO_COPY

Changes in v7:
none

Changes in v6:
none

Changes in v5:
- move common functions to console-core.c file
- remove static keyword from shared functions

Changes in v4:
- move common code to vidconsole_internal.h
- unite probe functions

Changes in v3:
none

Changes in v2:
none

 drivers/video/Makefile  |   6 +
 drivers/video/console_core.c| 141 +
 drivers/video/console_normal.c  | 150 --
 drivers/video/console_rotate.c  | 308 
 drivers/video/vidconsole_internal.h |  95 +
 include/video_console.h |   3 +
 6 files changed, 327 insertions(+), 376 deletions(-)
 create mode 100644 drivers/video/console_core.c
 create mode 100644 drivers/video/vidconsole_internal.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index cdb7d9a54d..cb3f373645 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -9,6 +9,12 @@ obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o
 obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o
 obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o
 obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
+ifdef CONFIG_CONSOLE_NORMAL
+obj-y += console_core.o
+else ifdef CONFIG_CONSOLE_ROTATION
+obj-y += console_core.o
+endif
+obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
 obj-$(CONFIG_DISPLAY) += display-uclass.o
 obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
new file mode 100644
index 00..9c2e4cb4ea
--- /dev/null
+++ b/drivers/video/console_core.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Google, Inc
+ * (C) Copyright 2015
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ * (C) Copyright 2023 Dzmitry Sankouski 
+ */
+
+#include 
+#include 
+#include 
+#include "vidconsole_internal.h"
+
+int check_bpix_support(int bpix)
+{
+   if (bpix == VIDEO_BPP8 && IS_ENABLED(CONFIG_VIDEO_BPP8))
+   return 0;
+   else if (bpix == VIDEO_BPP16 && IS_ENABLED(CONFIG_VIDEO_BPP16))
+   return 0;
+   else if (bpix == VIDEO_BPP32 && IS_ENABLED(CONFIG_VIDEO_BPP32))
+   return 0;
+   else
+   return -ENOSYS;
+}
+
+inline void fill_pixel_and_goto_next(void **dstp, u32 value, int pbytes, int 
step)
+{
+   u8 *dst_byte = *dstp;
+
+   if (pbytes == 4) {
+   u32 *dst = *dstp;
+   *dst = value;
+   }
+   if (pbytes == 2) {
+   u16 *dst = *dstp;
+   *dst = value;
+   }
+   if (pbytes == 1) {
+   u8 *dst = *dstp;
+   *dst = value;
+   }
+   *dstp = dst_byte + step;
+}
+
+int fill_char_vertically(uchar *pfont, void **line, struct video_priv 
*vid_priv,
+bool direction)
+{
+   int step, line_step, pbytes, ret;
+   void *dst;
+
+   ret = check_bpix_support(vid_priv->bpix);
+   if (ret)
+   return ret;
+
+   pbytes = VNBYTES(vid_priv->bpix);
+   if (direction) {
+   step = -pbytes;
+   line_step = -vid_priv->line_length;
+   } else {
+   step = pbytes;
+   line_step = vid_priv->line_length;
+   }
+
+   for (int row = 0; row < VIDEO_FONT_HEIGHT; row++) {
+   dst = *line;
+   uchar bits = pfont[row];
+
+   for (int i = 0; i < VIDEO_FONT_WIDTH; i++) {
+   u32 value = (bits & 0x80) ?
+   vid_priv->colour_fg :
+   vid_priv->colour_bg;
+
+   fill_pixel_and_goto_next(&dst,
+value,
+pbytes,
+step
+   );
+   bits <<= 1;
+   }
+   *line += line_step;
+   }
+   return ret;
+}
+
+int fill_char_horizontally(uchar *pfont, void **line, struct video_priv 
*vid_priv,
+  bool direction)
+{
+   int step, line_step, pbytes, ret;
+   void *dst;
+   u8 mask = 0x80;
+
+   ret = check_bpix_support(vid_priv->bpix);
+   if (ret)
+   return ret;
+
+   pbytes = VNBYTES(vid_priv->bpix);
+   if (direction) {
+   step

[PATCH v8 02/10] video console: add support for fonts wider than 1 byte

[Dzmitry Sankouski]

Devices with high ppi may benefit from wider fonts.

Current width implementation is limited by 1 byte, i.e. 8 bits.
New version iterates VIDEO_FONT_BYTE_WIDTH times, to process all
width bytes, thus allowing fonts wider than 1 byte.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 

---

Changes in v8:
none

Changes in v7:
none

Changes in v6:
rebase only

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
none

Changes in v2:
- replace TAIL_BIT_COUNT macro with c code
- rename refactoring

 drivers/video/console_core.c| 84 ++---
 drivers/video/console_normal.c  |  2 +-
 drivers/video/console_rotate.c  |  6 +--
 drivers/video/vidconsole_internal.h |  1 +
 4 files changed, 59 insertions(+), 34 deletions(-)

diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index 9c2e4cb4ea..de004f585c 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -45,7 +45,7 @@ inline void fill_pixel_and_goto_next(void **dstp, u32 value, 
int pbytes, int ste
 int fill_char_vertically(uchar *pfont, void **line, struct video_priv 
*vid_priv,
 bool direction)
 {
-   int step, line_step, pbytes, ret;
+   int step, line_step, pbytes, bitcount, width_remainder, ret;
void *dst;
 
ret = check_bpix_support(vid_priv->bpix);
@@ -61,23 +61,36 @@ int fill_char_vertically(uchar *pfont, void **line, struct 
video_priv *vid_priv,
line_step = vid_priv->line_length;
}
 
+   width_remainder = VIDEO_FONT_WIDTH % 8;
for (int row = 0; row < VIDEO_FONT_HEIGHT; row++) {
+   uchar bits;
+
+   bitcount = 8;
dst = *line;
-   uchar bits = pfont[row];
-
-   for (int i = 0; i < VIDEO_FONT_WIDTH; i++) {
-   u32 value = (bits & 0x80) ?
-   vid_priv->colour_fg :
-   vid_priv->colour_bg;
-
-   fill_pixel_and_goto_next(&dst,
-value,
-pbytes,
-step
-   );
-   bits <<= 1;
+   for (int col = 0; col < VIDEO_FONT_BYTE_WIDTH; col++) {
+   if (width_remainder) {
+   bool is_last_iteration = (VIDEO_FONT_BYTE_WIDTH 
- col == 1);
+
+   if (is_last_iteration)
+   bitcount = width_remainder;
+   }
+   bits = pfont[col];
+
+   for (int bit = 0; bit < bitcount; bit++) {
+   u32 value = (bits & 0x80) ?
+   vid_priv->colour_fg :
+   vid_priv->colour_bg;
+
+   fill_pixel_and_goto_next(&dst,
+value,
+pbytes,
+step
+   );
+   bits <<= 1;
+   }
}
*line += line_step;
+   pfont += VIDEO_FONT_BYTE_WIDTH;
}
return ret;
 }
@@ -85,9 +98,9 @@ int fill_char_vertically(uchar *pfont, void **line, struct 
video_priv *vid_priv,
 int fill_char_horizontally(uchar *pfont, void **line, struct video_priv 
*vid_priv,
   bool direction)
 {
-   int step, line_step, pbytes, ret;
+   int step, line_step, pbytes, bitcount = 8, width_remainder, ret;
void *dst;
-   u8 mask = 0x80;
+   u8 mask;
 
ret = check_bpix_support(vid_priv->bpix);
if (ret)
@@ -101,21 +114,32 @@ int fill_char_horizontally(uchar *pfont, void **line, 
struct video_priv *vid_pri
step = pbytes;
line_step = -vid_priv->line_length;
}
-   for (int col = 0; col < VIDEO_FONT_WIDTH; col++) {
-   dst = *line;
-   for (int row = 0; row < VIDEO_FONT_HEIGHT; row++) {
-   u32 value = (pfont[row * VIDEO_FONT_BYTE_WIDTH] & mask) 
?
-   vid_priv->colour_fg :
-   vid_priv->colour_bg;
-
-   fill_pixel_and_goto_next(&dst,
-value,
-pbytes,
-step
-   );
+
+   width_remainder = VIDEO_FONT_WIDTH % 8;
+   for (int col = 0; col < VIDEO_FONT_BYTE_WIDTH; col++) {
+   mask = 0x80;
+   if (width_remainder) {
+   bool is_last_iteration = (VIDEO_FONT_BYTE_WIDTH - col 
== 1);
+
+

[PATCH v8 03/10] video console: move 8x16 font data in named header

[Dzmitry Sankouski]

Consistent font data header names needed to add new
fonts.

Signed-off-by: Dzmitry Sankouski 
Reviewed-by: Simon Glass 
---

Changes in v8:
none

Changes in v7:
none

Changes in v6:
rebase only

Changes in v5:
N/A

Changes in v4:
N/A

Changes in v3:
N/A

Changes in v2:
N/A

 include/video_font.h | 2 +-
 include/{video_font_data.h => video_font_8x16.h} | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)
 rename include/{video_font_data.h => video_font_8x16.h} (99%)

diff --git a/include/video_font.h b/include/video_font.h
index 5e23f70f85..b07c07662c 100644
--- a/include/video_font.h
+++ b/include/video_font.h
@@ -10,7 +10,7 @@
 #ifdef CONFIG_VIDEO_FONT_4X6
 #include 
 #else
-#include 
+#include 
 #endif
 
 #endif /* _VIDEO_FONT_ */
diff --git a/include/video_font_data.h b/include/video_font_8x16.h
similarity index 99%
rename from include/video_font_data.h
rename to include/video_font_8x16.h
index 6e64198d1a..d3d4295032 100644
--- a/include/video_font_data.h
+++ b/include/video_font_8x16.h
@@ -6,8 +6,8 @@
  * This file contains an 8x16 bitmap font for code page 437.
  */
 
-#ifndef _VIDEO_FONT_DATA_
-#define _VIDEO_FONT_DATA_
+#ifndef _VIDEO_FONT_8X16
+#define _VIDEO_FONT_8X16
 
 #define VIDEO_FONT_CHARS   256
 #define VIDEO_FONT_WIDTH   8
@@ -4623,7 +4623,6 @@ static unsigned char __maybe_unused 
video_fontdata[VIDEO_FONT_SIZE] = {
0x00, /*  */
0x00, /*  */
0x00, /*  */
-
 };
 
 #endif
-- 
2.30.2

[PATCH v8 00/10] vidconsole: refactoring and support for wider fonts

[Dzmitry Sankouski]

Version 7 has vidconsole_get_font_size() function reworked to use
driver ops.

Version 6 contains entire rebased patch series.
New patch 'move vidconsole_get_font_size() to test.h' added.

Version 5 contain minor changes:
- move common functions to console-core.c file
- remove static keyword from shared functions

In version 4, only first patch sent, because review fixes to this would add
large rebase & patch formatting overhead. When it'll receive reviewed tag,
I'll resent entire rebased series.

Modern mobile phones typically have high pixel density.
Bootmenu is hardly readable on those with 8x16 font.

This patch series aims to add wider fonts for devices with high ppi.

Add 16x32, 12x22 fonts from linux, and allow font size configuration.

There was significant changes in version 2:
- fix video tests failures
- add runtime font size configuration
- add test for 12x22 font

In version 3,
'video console: add select font logic to vidconsole uclass driver'
patch was removed in favor of already merged patch
'video: Add font functions to the vidconsole API'

Changes in v8:
- fix build with disabled CONFIG_VIDEO_COPY
- add 12X22 font to sandox defconfig

Dzmitry Sankouski (10):
  video console: refactoring and optimization
  video console: add support for fonts wider than 1 byte
  video console: move 8x16 font data in named header
  video console: implement multiple fonts configuration
  video console: move vidconsole_get_font_size() logic to driver ops
  video console: allow font size configuration at runtime
  video console: add 12x22 Sun font from linux
  video console: add 16x32 Terminus font from linux
  video console: sandbox: add 12x22 font defconfigs
  video console: add 12x22 console simple font test

 cmd/Kconfig |8 +
 cmd/Makefile|2 +-
 cmd/font.c  |6 +-
 common/splash.c |   17 +-
 configs/sandbox_defconfig   |1 +
 configs/sandbox_flattree_defconfig  |1 +
 drivers/video/Kconfig   |   30 +
 drivers/video/Makefile  |6 +
 drivers/video/console_core.c|  212 +
 drivers/video/console_normal.c  |  177 +-
 drivers/video/console_rotate.c  |  371 +-
 drivers/video/console_truetype.c|3 +-
 drivers/video/vidconsole-uclass.c   |   11 +
 drivers/video/vidconsole_internal.h |  120 +
 include/video_console.h |   17 +-
 include/video_font.h|   31 +-
 include/video_font_4x6.h|   11 +-
 include/video_font_8x16.h   | 4624 
 include/video_font_data.h   | 4644 +---
 include/video_font_sun12x22.h   | 6158 +++
 include/video_font_ter16x32.h   | 2062 +
 test/cmd/font.c |   13 +-
 test/dm/video.c |   41 +
 23 files changed, 13518 insertions(+), 5048 deletions(-)
 create mode 100644 drivers/video/console_core.c
 create mode 100644 drivers/video/vidconsole_internal.h
 create mode 100644 include/video_font_8x16.h
 create mode 100644 include/video_font_sun12x22.h
 create mode 100644 include/video_font_ter16x32.h

-- 
2.30.2

Re: [PATCH 1/1] efi_loader: describe term_get_char()

[Ilias Apalodimas]

On Fri, 3 Mar 2023 at 23:06, Heinrich Schuchardt
 wrote:
>
> Add a function description.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  lib/efi_loader/efi_console.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
> index 4317630907..d970b667a6 100644
> --- a/lib/efi_loader/efi_console.c
> +++ b/lib/efi_loader/efi_console.c
> @@ -77,6 +77,14 @@ static struct simple_text_output_mode efi_con_mode = {
> .cursor_visible = 1,
>  };
>
> +/**
> + * term_get_char() - read a character from the console
> + *
> + * Wait for up to 100 ms to read a character from the console.
> + *
> + * @c: pointer to the buffer to receive the character
> + * Return: 0 on success, 1 otherwise
> + */
>  static int term_get_char(s32 *c)
>  {
> u64 timeout;
> --
> 2.39.2
>

Reviewed-by: Ilias Apalodimas 

[PATCH 2/2] ARM: meson: Add initial support for BPI-CM4 module with BPI-CM4IO baseboard

[Neil Armstrong]

Add support for both the BananaPi BPI-CM4 module and the BananaPi
baseboard which is compatible with the RaspberryPi CM4IO baseboard.

The BananaPi BPI-CM4 module follows the CM4 specifications at [1],
but with a single HDMI port and a single DSI output.

The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.

[1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf

Signed-off-by: Neil Armstrong 
---
 .../dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi  |  6 ++
 board/amlogic/u200/MAINTAINERS |  1 +
 configs/bananapi-cm4-cm4io_defconfig   | 84 ++
 doc/board/amlogic/index.rst|  1 +
 4 files changed, 92 insertions(+)

diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi 
b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi
new file mode 100644
index 00..a60ba27806
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong 
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS
index 47cec234a1..7535e489d1 100644
--- a/board/amlogic/u200/MAINTAINERS
+++ b/board/amlogic/u200/MAINTAINERS
@@ -4,6 +4,7 @@ S:  Maintained
 L: u-boot-amlo...@groups.io
 F: board/amlogic/u200/
 F: configs/u200_defconfig
+F: configs/bananapi-cm4-cm4io_defconfig
 F: configs/bananapi-m5_defconfig
 F: configs/radxa-zero_defconfig
 F: doc/board/amlogic/u200.rst
diff --git a/configs/bananapi-cm4-cm4io_defconfig 
b/configs/bananapi-cm4-cm4io_defconfig
new file mode 100644
index 00..0801b9d06f
--- /dev/null
+++ b/configs/bananapi-cm4-cm4io_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x0100
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_IDENT_STRING="bpi-cm4io"
+CONFIG_SYS_LOAD_ADDR=0x100
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst
index f945f672dd..e51b904582 100644
--- a/doc/board/amlogic/index.rst
+++ b/doc/board/amlogic/index.rst
@@ -22,6 +22,7 @@ This matrix concerns the actual source code version.
 |   |   | JetHub J80  |  | 
|| Odroid-Go-  | BananaPi-M5  |
 |   |   | |  | 
|| Ultra   |  |
 |   |   | |  | 
|| Odroid-N2L  |  |
+|   |   | |  | 
|| BPI-M4  |  |
 
+---+---+-+--+-++

[PATCH 1/2] ARM: dts: import initial DT for BPI-CM4 module with BPI-CM4IO baseboard

[Neil Armstrong]

Import initial support for BPI-CM4 module with BPI-CM4IO baseboard
from the Linux submission applied at [1].

The BananaPi BPI-CM4 module follows the CM4 specifications at [2],
but with a single HDMI port and a single DSI output.

The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.

[1] https://git.kernel.org/amlogic/c/0262f2736978b1763363224698f47112a148dab0
[2] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf

Signed-off-by: Neil Armstrong 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 +++
 arch/arm/dts/meson-g12b-bananapi-cm4.dtsi  | 388 +
 3 files changed, 554 insertions(+)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c160e884bf..0c149b636a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -212,6 +212,7 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-g12b-odroid-n2.dtb \
meson-g12b-odroid-n2l.dtb \
meson-g12b-odroid-n2-plus.dtb \
+   meson-g12b-bananapi-cm4-cm4io.dtb \
meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts 
b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts
new file mode 100644
index 00..1b0c3881c6
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong 
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-bananapi-cm4.dtsi"
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", 
"amlogic,g12b";
+   model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module";
+
+   aliases {
+   ethernet0 = ðmac;
+   i2c0 = &i2c1;
+   i2c1 = &i2c3;
+   };
+
+   adc-keys {
+   compatible = "adc-keys";
+   io-channels = <&saradc 2>;
+   io-channel-names = "buttons";
+   keyup-threshold-microvolt = <171>;
+
+   button-function {
+   label = "Function";
+   linux,code = ;
+   press-threshold-microvolt = <1>;
+   };
+   };
+
+   hdmi_connector: hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_connector_in: endpoint {
+   remote-endpoint = <&hdmi_tx_tmds_out>;
+   };
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   led-blue {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   sound {
+   compatible = "amlogic,axg-sound-card";
+   model = "BPI-CM4IO";
+   audio-aux-devs = <&tdmout_b>;
+   audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+   "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+   "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+   "TDM_B Playback", "TDMOUT_B OUT";
+
+   assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+   assigned-clock-parents = <0>, <0>, <0>;
+   assigned-clock-rates = <294912000>,
+  <270950400>,
+  <393216000>;
+
+   dai-link-0 {
+   sound-dai = <&frddr_a>;
+   };
+
+   dai-link-1 {
+   sound-dai = <&frddr_b>;
+   };
+
+   dai-link-2 {
+   sound-dai = <&frddr_c>;
+   };
+
+   /* 8ch hdmi interface */
+   dai-link-3 {
+   sound-dai = <&tdmif_b>;
+   dai-format = "i2s";
+   dai-tdm-slot-tx-mask-0 = <1 1>;
+   dai-tdm-slot-tx-mask-1 = <1 1>;
+   dai-tdm-slot-tx-mask-2 = <1 1>;
+   dai-tdm-slot-tx-mask-3 = <1 1>;
+   mclk-fs = <256>;
+
+   codec {
+   sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+   };
+   };
+
+   /* hdmi g

[PATCH 0/2] ARM: meson: Add initial support for BPI-CM4 module with BPI-CM4IO baseboard

[Neil Armstrong]

Add support for both the BananaPi BPI-CM4 module and the BananaPi
baseboard which is compatible with the RaspberryPi CM4IO baseboard.


The BananaPi BPI-CM4 module follows the CM4 specifications at [1],
but with a single HDMI port and a single DSI output.

The current CM4IO baseboard DT should work fine on the Raspberry CM4
baseboard and other derivatives baseboards, but proper DT should
be written for other baseboards.

The DT is imported from the submission done at [2] and applied
at [3].

[1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
[2] 
https://lore.kernel.org/all/20230303-topic-amlogic-upstream-bpi-cm4-v2-0-2ecfde76f...@linaro.org/
[3] https://git.kernel.org/amlogic/c/0262f2736978b1763363224698f47112a148dab0

Signed-off-by: Neil Armstrong 
---
Neil Armstrong (2):
  ARM: dts: import initial DT for BPI-CM4 module with BPI-CM4IO baseboard
  ARM: meson: Add initial support for BPI-CM4 module with BPI-CM4IO 
baseboard

 arch/arm/dts/Makefile  |   1 +
 .../dts/meson-g12b-bananapi-cm4-cm4io-u-boot.dtsi  |   6 +
 arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts | 165 +
 arch/arm/dts/meson-g12b-bananapi-cm4.dtsi  | 388 +
 board/amlogic/u200/MAINTAINERS |   1 +
 configs/bananapi-cm4-cm4io_defconfig   |  84 +
 doc/board/amlogic/index.rst|   1 +
 7 files changed, 646 insertions(+)
---
base-commit: b08ffdffdce95e267e782366f4a77bf6b5537b28
change-id: 20230307-u-boot-cm4-1311815d8371

Best regards,
-- 
Neil Armstrong 

[PATCH v1] clk: nuvoton: add read only feature for clk driver

[Jim Liu]

Set ahb/apb/fiu clock divider as read-only

Signed-off-by: Jim Liu 
---
 drivers/clk/nuvoton/clk_npcm.c| 15 ---
 drivers/clk/nuvoton/clk_npcm.h|  1 +
 drivers/clk/nuvoton/clk_npcm8xx.c | 12 ++--
 3 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c
index 8d71f2a24b..18cb9cddbf 100644
--- a/drivers/clk/nuvoton/clk_npcm.c
+++ b/drivers/clk/nuvoton/clk_npcm.c
@@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk)
return div;
 }
 
-static u32 npcm_clk_set_div(struct clk *clk, u32 div)
+static int npcm_clk_set_div(struct clk *clk, u32 div)
 {
struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
struct npcm_clk_div *divider;
@@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
if (!divider)
return -EINVAL;
 
+   if (divider->flags & DIV_RO)
+   return 0;
+
if (divider->flags & PRE_DIV2)
div = div >> 1;
 
@@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
else
clkdiv = ilog2(div);
 
+   if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) {
+   printf("clkdiv(%d) for clk(%ld) is over limit\n",
+  clkdiv, clk->id);
+   return -EINVAL;
+   }
+
val = readl(priv->base + divider->reg);
val &= ~divider->mask;
val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
@@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
if (ret)
return ret;
 
-   debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, 
parent_rate, div);
-   return (parent_rate / div);
+   debug("%s: rate %lu, new rate %lu\n", __func__, rate, 
npcm_clk_get_rate(clk));
+   return npcm_clk_get_rate(clk);
 }
 
 static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)
diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h
index 06b60dc8b8..b4726d8381 100644
--- a/drivers/clk/nuvoton/clk_npcm.h
+++ b/drivers/clk/nuvoton/clk_npcm.h
@@ -50,6 +50,7 @@
 #define PRE_DIV2   BIT(2)  /* Pre divisor = 2 */
 #define POST_DIV2  BIT(3)  /* Post divisor = 2 */
 #define FIXED_PARENT   BIT(4)  /* clock source is fixed */
+#define DIV_RO BIT(5)  /* divider is read-only */
 
 /* Parameters of PLL configuration */
 struct npcm_clk_pll {
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c 
b/drivers/clk/nuvoton/clk_npcm8xx.c
index 27e3cfcf55..d1b32e3237 100644
--- a/drivers/clk/nuvoton/clk_npcm8xx.c
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = {
 };
 
 static struct npcm_clk_div npcm8xx_clk_dividers[] = {
-   {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2},
-   {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2},
-   {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2},
-   {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1},
-   {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1},
-   {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1},
+   {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO},
+   {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO},
+   {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO},
+   {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO},
+   {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO},
+   {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO},
{NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
{NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
{NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1},
-- 
2.17.1

[PATCH v1] spi: npcm-fiu: add regulator feature and remove set clock

[Jim Liu]

NPCM7xx/NPCM8xx default is boot from flash.
removed set clock feature due to reliability and security.
the clock will set by bootblock or tip.

Signed-off-by: Jim Liu 
---
 drivers/spi/npcm_fiu_spi.c | 72 +++---
 1 file changed, 59 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c
index 7000fe5860..73c506442a 100644
--- a/drivers/spi/npcm_fiu_spi.c
+++ b/drivers/spi/npcm_fiu_spi.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DW_SIZE4
 #define CHUNK_SIZE 16
@@ -34,6 +35,34 @@
 #define UMA_CTS_RDYST  BIT(24)
 #define UMA_CTS_DEV_NUM_MASK   GENMASK(9, 8)
 
+/* Direct Write Configuration Register */
+#define DWR_CFG_WBURST_MASKGENMASK(25, 24)
+#define DWR_CFG_ADDSIZ_MASKGENMASK(17, 16)
+#define DWR_CFG_ABPCK_MASK GENMASK(11, 10)
+#define DRW_CFG_DBPCK_MASK GENMASK(9, 8)
+#define DRW_CFG_WRCMD  2
+enum {
+   DWR_WBURST_1_BYTE,
+   DWR_WBURST_16_BYTE = 3,
+};
+
+enum {
+   DWR_ADDSIZ_24_BIT,
+   DWR_ADDSIZ_32_BIT,
+};
+
+enum {
+   DWR_ABPCK_BIT_PER_CLK,
+   DWR_ABPCK_2_BIT_PER_CLK,
+   DWR_ABPCK_4_BIT_PER_CLK,
+};
+
+enum {
+   DWR_DBPCK_BIT_PER_CLK,
+   DWR_DBPCK_2_BIT_PER_CLK,
+   DWR_DBPCK_4_BIT_PER_CLK,
+};
+
 struct npcm_fiu_regs {
unsigned intdrd_cfg;
unsigned intdwr_cfg;
@@ -67,19 +96,10 @@ struct npcm_fiu_regs {
 
 struct npcm_fiu_priv {
struct npcm_fiu_regs *regs;
-   struct clk clk;
 };
 
 static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
 {
-   struct npcm_fiu_priv *priv = dev_get_priv(bus);
-   int ret;
-
-   debug("%s: set speed %u\n", bus->name, speed);
-   ret = clk_set_rate(&priv->clk, speed);
-   if (ret < 0)
-   return ret;
-
return 0;
 }
 
@@ -349,13 +369,38 @@ static int npcm_fiu_exec_op(struct spi_slave *slave,
 static int npcm_fiu_spi_probe(struct udevice *bus)
 {
struct npcm_fiu_priv *priv = dev_get_priv(bus);
-   int ret;
+   struct udevice *vqspi_supply;
+   int vqspi_uv;
 
priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus);
 
-   ret = clk_get_by_index(bus, 0, &priv->clk);
-   if (ret < 0)
-   return ret;
+   if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+   device_get_supply_regulator(bus, "vqspi-supply", &vqspi_supply);
+   vqspi_uv = dev_read_u32_default(bus, "vqspi-microvolt", 0);
+   /* Set IO voltage */
+   if (vqspi_supply && vqspi_uv)
+   regulator_set_value(vqspi_supply, vqspi_uv);
+   }
+
+   return 0;
+}
+
+static int npcm_fiu_spi_bind(struct udevice *bus)
+{
+   struct npcm_fiu_regs *regs;
+
+   if (dev_read_bool(bus, "nuvoton,spix-mode")) {
+   regs = dev_read_addr_ptr(bus);
+   if (!regs)
+   return -EINVAL;
+
+   /* Setup direct write cfg for SPIX */
+   writel(FIELD_PREP(DWR_CFG_WBURST_MASK, DWR_WBURST_16_BYTE) |
+  FIELD_PREP(DWR_CFG_ADDSIZ_MASK, DWR_ADDSIZ_24_BIT) |
+  FIELD_PREP(DWR_CFG_ABPCK_MASK, DWR_ABPCK_4_BIT_PER_CLK) |
+  FIELD_PREP(DRW_CFG_DBPCK_MASK, DWR_DBPCK_4_BIT_PER_CLK) |
+  DRW_CFG_WRCMD, ®s->dwr_cfg);
+   }
 
return 0;
 }
@@ -384,4 +429,5 @@ U_BOOT_DRIVER(npcm_fiu_spi) = {
.ops= &npcm_fiu_spi_ops,
.priv_auto = sizeof(struct npcm_fiu_priv),
.probe  = npcm_fiu_spi_probe,
+   .bind = npcm_fiu_spi_bind,
 };
-- 
2.17.1