Re: [PATCH u-boot 4/4] board: purism: Use U-Boot mmc function for converting boot part to part access
On 2023-04-13 14:10, Pali Rohár wrote: eMMC Boot Partition Enable bits in mmc->part_config (EXT_CSD[179]) has different coding than eMMC Partition Access bits. Use spl_mmc_emmc_boot_partition() function which does this conversion properly (hopefully). Signed-off-by: Pali Rohár Reviewed-by: Angus Ainslie
Re: [PATCH v8] board: purism: add the Purism Librem5 phone
On 2022-09-18 13:41, sba...@denx.de wrote: Initial commit of Librem5 u-boot and SPL Signed-off-by: Angus Ainslie Co-developed-by: Sebastian Krzyszkowiak Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Thanks Stefano ! Cheers Angus Best regards, Stefano Babic
Re: imx8mq allocation issue
Hi Heiko, On 2022-09-09 07:45, Heiko Thiery wrote: Hi Angus, Am Fr., 9. Sept. 2022 um 16:43 Uhr schrieb Angus Ainslie : Hi Heiko, The librem5 (imx8mq) is able to boot using these [1] patches on top of u-boot-imx-20220729. I believe the change that fixed the allocation issue for me was CONFIG_SPL_MAX_SIZE=0x25000 The imx8mq_evk board boots also but when enabling the DEBUG_UART the output shown in my previous mail is seen. Could you also try to enable the DEBUG UART please? -- Heiko Yeah it still boots CUK**SH022.10-rc1-00013-g1b8b4362ac-dirty (Sep 09 2022 - 09:24:49 -0700) Initializing pinmux Initializing ECSPI Initializing DRAM SDRAM val 2 SDRAM val 3 SDRAM val 3 spl_dram_init: LPDDR4 3 GiB USB Boot Trying to boot from USB SDP board_usb_init : index 0 type 1 SDP: initialize... SDP: handle requests... Downloading file of size 946628 to 0x4040... done Jumping to header at 0x4040 Header Tag is not an IMX image Found header at 0x40410c00 board_usb_cleanup : 0 ?2~3 U-Boot 2022.10-rc1-00013-g1b8b4362ac-dirty (Sep 09 2022 - 09:24:49 -0700) CPU: Freescale i.MX8MQ rev2.1 1500 MHz (running at 1000 MHz) CPU: Commercial temperature grade (0C to 95C) at 32C Reset cause: POR Model: Purism Librem 5r4 DRAM: 3 GiB clk_register: failed to get device (parent of ckil) clk_register: failed to get device (parent of clock-osc-27m) clk_register: failed to get device (parent of sys1_pll) clk_register: failed to get device (parent of sys2_pll) clk_register: failed to get device (parent of sys3_pll) Enabling regulator-hub tps65982 boot successful Core: 193 devices, 25 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Board name: librem5 Board rev: 4 USB Boot vol_down_key_pressed : 1 Net: No ethernet found. Hit any key to stop autoboot: 0 Cheers, Angus [1] https://lore.kernel.org/u-boot/20220825134602.382775-1-an...@akkea.ca/ On 2022-09-09 02:12, Heiko Thiery wrote: > HI, > > I think on the imx8mq platform we have a problem with the introduction > of the clock driver. I tried to debug the problem that the pitx-imx8m > board was not able to start for some time. I was wondering why the > pitx-im8m doesn't work anymore although the imx8mq_evk is running. > > So I switched to the imx8mq_evk for counter testing. As I already > figured out in [1] also the imx8mq_evk is not able to start properly. > > On the EVK I enabled the DEBUG_UART and see the outputs below. I > suspect all imx8mq boards have this problem. > > CONFIG_DEBUG_UART_BASE=0x3086 # for uart1 > CONFIG_DEBUG_UART_CLOCK=2400 > > --- 8< > U-Boot SPL 2022.10-rc4-00038-ge3fce5e560-dirty (Sep 09 2022 - 10:51:29 > +0200) > PMIC: PFUZE100 ID=0x10 > SEC0: RNG instantiated > Normal Boot > Trying to boot from MMC2 > clk_register: failed to get device (parent of ckil) > clk_register: failed to get device (parent of clock-osc-27m) > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > : > : > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhaustedÿ > > U-Boot 2022.10-rc4-00038-ge3fce5e560-dirty (Sep 09 2022 - 10:51:29 > +0200) > > CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz > Reset cause: POR > Model: NXP i.MX8MQ EVK > DRAM: 3 GiB > clk_register: failed to get device (parent of ckil) > clk_register: failed to get device (parent of clock-osc-27m) > clk_register: failed to get device (parent of sys1_pll) > clk_register: failed to get device (parent of sys2_pll) > clk_register: failed to get device (parent of sys3_pll) > Core: 147 devices, 21 uclasses, devicetree: separate > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > Loading Environment from MMC... OK > In:serial@3086 > Out: serial@3086 > Err: serial@3086 > SEC0: RNG instantiated > Net: eth0: ethernet@30be > Hit any key to stop autoboot: 0 > u-boot=> > --- 8< > > Could the maintainers of the other imx8mq boards please check if they > can confirm this? > > [1] > https://lore.kernel.org/u-boot/caeymn7bcac8y8b0moai72yjthmkdjt_oe_ebznrwhh4jxxo...@mail.gmail.com/#t > > Thanks, > Heiko
Re: imx8mq allocation issue
Hi Heiko, The librem5 (imx8mq) is able to boot using these [1] patches on top of u-boot-imx-20220729. I believe the change that fixed the allocation issue for me was CONFIG_SPL_MAX_SIZE=0x25000 Cheers, Angus [1] https://lore.kernel.org/u-boot/20220825134602.382775-1-an...@akkea.ca/ On 2022-09-09 02:12, Heiko Thiery wrote: HI, I think on the imx8mq platform we have a problem with the introduction of the clock driver. I tried to debug the problem that the pitx-imx8m board was not able to start for some time. I was wondering why the pitx-im8m doesn't work anymore although the imx8mq_evk is running. So I switched to the imx8mq_evk for counter testing. As I already figured out in [1] also the imx8mq_evk is not able to start properly. On the EVK I enabled the DEBUG_UART and see the outputs below. I suspect all imx8mq boards have this problem. CONFIG_DEBUG_UART_BASE=0x3086 # for uart1 CONFIG_DEBUG_UART_CLOCK=2400 --- 8< U-Boot SPL 2022.10-rc4-00038-ge3fce5e560-dirty (Sep 09 2022 - 10:51:29 +0200) PMIC: PFUZE100 ID=0x10 SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 clk_register: failed to get device (parent of ckil) clk_register: failed to get device (parent of clock-osc-27m) alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted : : alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhaustedÿ U-Boot 2022.10-rc4-00038-ge3fce5e560-dirty (Sep 09 2022 - 10:51:29 +0200) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: NXP i.MX8MQ EVK DRAM: 3 GiB clk_register: failed to get device (parent of ckil) clk_register: failed to get device (parent of clock-osc-27m) clk_register: failed to get device (parent of sys1_pll) clk_register: failed to get device (parent of sys2_pll) clk_register: failed to get device (parent of sys3_pll) Core: 147 devices, 21 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In:serial@3086 Out: serial@3086 Err: serial@3086 SEC0: RNG instantiated Net: eth0: ethernet@30be Hit any key to stop autoboot: 0 u-boot=> --- 8< Could the maintainers of the other imx8mq boards please check if they can confirm this? [1] https://lore.kernel.org/u-boot/caeymn7bcac8y8b0moai72yjthmkdjt_oe_ebznrwhh4jxxo...@mail.gmail.com/#t Thanks, Heiko
[PATCH v8] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
Reviewed-by: Fabio Estevam
---
Changes since v7:
Added Reviewed-by
Move patch comments
Changes since v6:
Move migrated symbols
Rebase onto latest u-boot-imx
Changes since v5:
Proper handling of the Display Port firmware for CI builds
Update the DP section of the docs
Changes since v4:
Include imx8mq-u-boot.dtsi instead of adding a new copy
Changes since v3:
Dropped unused MMCROOT
Rebased on u-boot-imx
Changes since v2:
Cleanup Kconfig symbols used in librem5.h
Cleanup various checkpatch issues
Drop some un-used functions
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 24 +
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |9 +
board/purism/librem5/librem5.c | 425 ++
board/purism/librem5/librem5.h | 181 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 593
configs/librem5_defconfig| 152 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 95 ++
19 files changed, 5401 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 48cb1f52b7..5e9e4c0d09 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -971,7 +971,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-venice-gw74xx.dtb \
imx8mp-verdin-wifi-dev.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 00..9d0a54a32f
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
+ { /* console */
+ u-boot,dm-spl;
+};
+
+ {
+ /delete-node/ signed-hdmi;
+
+ signed-hdmi {
+ filename = "signed_hdmi.bin";
+
+ signed-dp-imx8m {
+ filename = "signed_dp_imx8m.bin";
+ type = "blob-ext";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts
b/arch/arm/dts/imx8mq-librem5-r4.dts
new file mode 100644
index 00..cbfb49aa25
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Purism SPC
+
+/dts-v1/;
+
+#include "imx8mq-librem5.dtsi"
+
+/ {
+ model = "Purism Librem 5r4";
+ compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
+};
+
+_gyro {
+ mount-matrix = "1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+};
+
+ {
+ maxim,rsns-microohm = <1667>;
+};
+
+ {
+ ti,battery-regulation-voltage = <420>; /* uV */
+ ti,charge-current = <15000
Re: [PATCH v7] board: purism: add the Purism Librem5 phone
On 2022-08-13 07:53, Fabio Estevam wrote: Hi Angus, On Sun, Aug 7, 2022 at 1:02 PM Angus Ainslie wrote: Initial commit of Librem5 u-boot and SPL All of the pre-requisite patches for this board are now upstream. Changes since v6: Move migrated symbols Rebase onto latest u-boot-imx Changes since v5: Proper handling of the Display Port firmware for CI builds Update the DP section of the docs Changes since v4: Include imx8mq-u-boot.dtsi instead of adding a new copy Changes since v3: Dropped unused MMCROOT Rebased on u-boot-imx Changes since v2: Cleanup Kconfig symbols used in librem5.h Cleanup various checkpatch issues Drop some un-used functions Changes since v1: Merged patches into a monolithic board patch Using DM drivers for devices in u-boot Added USB storage support for uSD rootfs Dropped many SPL_BUILD guarded define's Fixed documentation index Signed-off-by: Angus Ainslie Co-developed-by: Sebastian Krzyszkowiak Signed-off-by: Sebastian Krzyszkowiak Patch looks good: Reviewed-by: Fabio Estevam I would suggest removing the changes history from the commit log and put this information below the --- line. Thanks for the review Fabio. I'll try and resend it early next week with that fixed. Does anyone know if the CI is passing with this patch ?
[PATCH v7] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL
All of the pre-requisite patches for this board are now upstream.
Changes since v6:
Move migrated symbols
Rebase onto latest u-boot-imx
Changes since v5:
Proper handling of the Display Port firmware for CI builds
Update the DP section of the docs
Changes since v4:
Include imx8mq-u-boot.dtsi instead of adding a new copy
Changes since v3:
Dropped unused MMCROOT
Rebased on u-boot-imx
Changes since v2:
Cleanup Kconfig symbols used in librem5.h
Cleanup various checkpatch issues
Drop some un-used functions
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 24 +
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |9 +
board/purism/librem5/librem5.c | 425 ++
board/purism/librem5/librem5.h | 181 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 593
configs/librem5_defconfig| 152 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 95 ++
19 files changed, 5401 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 48cb1f52b7..5e9e4c0d09 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -971,7 +971,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-venice-gw74xx.dtb \
imx8mp-verdin-wifi-dev.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 00..9d0a54a32f
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
+ { /* console */
+ u-boot,dm-spl;
+};
+
+ {
+ /delete-node/ signed-hdmi;
+
+ signed-hdmi {
+ filename = "signed_hdmi.bin";
+
+ signed-dp-imx8m {
+ filename = "signed_dp_imx8m.bin";
+ type = "blob-ext";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts
b/arch/arm/dts/imx8mq-librem5-r4.dts
new file mode 100644
index 00..cbfb49aa25
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Purism SPC
+
+/dts-v1/;
+
+#include "imx8mq-librem5.dtsi"
+
+/ {
+ model = "Purism Librem 5r4";
+ compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
+};
+
+_gyro {
+ mount-matrix = "1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+};
+
+ {
+ maxim,rsns-microohm = <1667>;
+};
+
+ {
+ ti,battery-regulation-voltage = <420>; /* uV */
+ ti,charge-current = <150>; /* uA */
+
Re: [PATCH v6] board: purism: add the Purism Librem5 phone
On 2022-07-26 00:35, Stefano Babic wrote: On 30.06.22 21:29, Angus Ainslie wrote: Hi Stefano, On 2022-06-30 12:09, Stefano Babic wrote: Hi Angus, On 30.06.22 19:30, Angus Ainslie wrote: Hi All, Are there any remaining issues with this patch ? Rather yes, it was supposed that issues with dwc3 was already fixed, maybe another patch is missing - can you check this ? https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/457089 It needs the patch mentioned down below in the description. Next attempt... There are several CONFIG_ in include/configs/librem5.h that should be really set in the config file, causing build error, see: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/472302 Can you fix them ? Thanks ! Unfortunately rebasing on the latest u-boot-imx the board doesn't boot anymore so I'll need to bisect that first Regards Angus Best regards, Stefano
Re: DWC3 host support
On 2022-07-18 23:47, Michal Simek wrote:
Hi,
On 7/18/22 18:23, Angus Ainslie wrote:
Hi,
On 2022-07-18 01:13, Michal Simek wrote:
On 7/17/22 17:23, Marek Vasut wrote:
On 7/17/22 05:00, Angus Ainslie wrote:
On 2022-07-16 11:37, Marek Vasut wrote:
On 7/16/22 15:02, Angus Ainslie wrote:
Hi Michal,
I recently rebased my librem5 tree onto the latest u-boot-imx
branch
and the dwc3 host mode stopped working.
I bisected it down to this commit:
142d50fbce7c364a74f5e8204dba491b9f066e6c usb: dwc3: Add support
for
usb3-phy PHY configuration
Reverting that commit allows usb host mode to work on the librem5
again.
Should this initialization go into an SOC specific glue_configure
function ?
Is the imx8mq.dtsi missing something that will keep usb host
working
with this patch ?
Does this break usb host on other imx8mq devices ?
Wasn't this fixed by:
868d58f69c ("usb: dwc3: Fix non-usb3 configurations")
?
I've got that in my tree and it still fails to probe the USB2 hub
and
USB 2 storage.
I assume you do have CONFIG_PHY_IMX8MQ_USB enabled ?
What does generic_phy_get_by_name() return for you in
drivers/usb/dwc3/dwc3-generic.c ?
As Marek said there was one patch which fixes origin patch which
didn't handle all the error cases properly. We need to know return
value from generic_phy_get_by_name(), also if you still have usb3-phy
in DT (as is in imx8mq.dtsi) with phy DT status enabled and enabled
phy driver (CONFIG_PHY_IMX8MQ_USB).
Removing the usb3 phy definition also "fixes" it
--- a/arch/arm/dts/imx8mq-librem5-r4.dts
+++ b/arch/arm/dts/imx8mq-librem5-r4.dts
@@ -33,3 +33,8 @@
{
proximity-near-level = <10>;
};
+
+_dwc3_1 {
+ phys = <_phy1>;
+ phy-names = "usb2-phy";
+};
Log shows that phy initialization is called properly but it looks like
that initialization itself has issue which should be the issue with
phy driver.
DWC3 driver is calling just phy_init and phy_power_on which are quite
small 2 functions in phy-imx8mq-usb.c.
Did usb3 work before 142d50fbce7c364a74f5e8204dba491b9f066e6c?
I have no idea how imx is working but I have added to CC author of
this phy driver.
We don't use USB3 on that port so no idea. The only thing connected to
that port is a USB 2 hub and then downstream devices from the hub. The
USB 2 hub did work without 142d50fbce7c364a74f5e8204dba491b9f066e6c.
I see small differences between Linux and U-Boot drivers.
99 value &= ~PHY_CTRL0_SSC_RANGE_MASK;
100 value |= PHY_CTRL0_SSC_RANGE_4003PPM;
And in power_on I see this in u-boot
129 /* Disable rx term override */
130 value = readl(imx_phy->base + PHY_CTRL6);
131 value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL;
132 writel(value, imx_phy->base + PHY_CTRL6);
And Linux driver is handling regulators. Do you use any regulator?
There isn't a regulator specifically for the PHY. There is one for the
hub and it gets enabled before the phy_init functions.
If usb3.0 works in Linux I think it should be easier for you to track
this down but there are some small differences in the U-Boot driver
which can be the reason why it is failing on your board.
Thanks
Angus
Thanks,
Michal
Re: DWC3 host support
Hi,
On 2022-07-18 01:13, Michal Simek wrote:
On 7/17/22 17:23, Marek Vasut wrote:
On 7/17/22 05:00, Angus Ainslie wrote:
On 2022-07-16 11:37, Marek Vasut wrote:
On 7/16/22 15:02, Angus Ainslie wrote:
Hi Michal,
I recently rebased my librem5 tree onto the latest u-boot-imx
branch
and the dwc3 host mode stopped working.
I bisected it down to this commit:
142d50fbce7c364a74f5e8204dba491b9f066e6c usb: dwc3: Add support for
usb3-phy PHY configuration
Reverting that commit allows usb host mode to work on the librem5
again.
Should this initialization go into an SOC specific glue_configure
function ?
Is the imx8mq.dtsi missing something that will keep usb host
working
with this patch ?
Does this break usb host on other imx8mq devices ?
Wasn't this fixed by:
868d58f69c ("usb: dwc3: Fix non-usb3 configurations")
?
I've got that in my tree and it still fails to probe the USB2 hub and
USB 2 storage.
I assume you do have CONFIG_PHY_IMX8MQ_USB enabled ?
What does generic_phy_get_by_name() return for you in
drivers/usb/dwc3/dwc3-generic.c ?
As Marek said there was one patch which fixes origin patch which
didn't handle all the error cases properly. We need to know return
value from generic_phy_get_by_name(), also if you still have usb3-phy
in DT (as is in imx8mq.dtsi) with phy DT status enabled and enabled
phy driver (CONFIG_PHY_IMX8MQ_USB).
Removing the usb3 phy definition also "fixes" it
--- a/arch/arm/dts/imx8mq-librem5-r4.dts
+++ b/arch/arm/dts/imx8mq-librem5-r4.dts
@@ -33,3 +33,8 @@
{
proximity-near-level = <10>;
};
+
+_dwc3_1 {
+ phys = <_phy1>;
+ phy-names = "usb2-phy";
+};
Thanks
Angus
Thanks,
Michal
Re: DWC3 host support
Hi Marek/Michal,
On 2022-07-18 01:13, Michal Simek wrote:
On 7/17/22 17:23, Marek Vasut wrote:
On 7/17/22 05:00, Angus Ainslie wrote:
On 2022-07-16 11:37, Marek Vasut wrote:
On 7/16/22 15:02, Angus Ainslie wrote:
Hi Michal,
I recently rebased my librem5 tree onto the latest u-boot-imx
branch
and the dwc3 host mode stopped working.
I bisected it down to this commit:
142d50fbce7c364a74f5e8204dba491b9f066e6c usb: dwc3: Add support for
usb3-phy PHY configuration
Reverting that commit allows usb host mode to work on the librem5
again.
Should this initialization go into an SOC specific glue_configure
function ?
Is the imx8mq.dtsi missing something that will keep usb host
working
with this patch ?
Does this break usb host on other imx8mq devices ?
Wasn't this fixed by:
868d58f69c ("usb: dwc3: Fix non-usb3 configurations")
?
I've got that in my tree and it still fails to probe the USB2 hub and
USB 2 storage.
I assume you do have CONFIG_PHY_IMX8MQ_USB enabled ?
What does generic_phy_get_by_name() return for you in
drivers/usb/dwc3/dwc3-generic.c ?
As Marek said there was one patch which fixes origin patch which
didn't handle all the error cases properly. We need to know return
value from generic_phy_get_by_name(), also if you still have usb3-phy
in DT (as is in imx8mq.dtsi) with phy DT status enabled and enabled
phy driver (CONFIG_PHY_IMX8MQ_USB).
I use the imx8mq.dtsi from the u-boot-imx tree that includes the
usb3-phy
https://source.denx.de/u-boot/custodians/u-boot-imx/-/blob/master/arch/arm/dts/imx8mq.dtsi#L1421
CONFIG_PHY_IMX8MQ_USB is defined in my defconfig
https://source.puri.sm/angus.ainslie/uboot-imx/-/blob/upstream/librem5-uart2/configs/librem5_defconfig#L114
Here is the error path I think you're talking about
https://source.puri.sm/angus.ainslie/uboot-imx/-/blob/upstream/librem5-uart2/drivers/usb/dwc3/dwc3-generic.c#L474
I modified dwc3-generic.c to print the return value
@@ -475,6 +477,8 @@ static int dwc3_glue_probe(struct udevice *dev)
phy.dev = NULL;
}
+ debug("phy3 initialized %d %s\n", ret, phy.dev ? phy.dev->name :
"null");
+
glue->regs = dev_read_addr(dev);
Here's the output from the boot
U-Boot 2022.07-rc5-00014-g329f8a8ae05-dirty (Jul 18 2022 - 06:59:45
-0700)
CPU: Freescale i.MX8MQ rev2.0 1500 MHz (running at 1000 MHz)
CPU: Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Purism Librem 5r4
DRAM: 3 GiB
dwc3_glue_bind: subnode name: port@0
dwc3_glue_bind: dr_mode: OTG or Peripheral
dwc3_glue_bind: subnode name: port@1
dwc3_glue_bind: dr_mode: OTG or Peripheral
dwc3_glue_bind: subnode name: hub@1
dwc3_glue_bind: dr_mode: HOST
clk_register: failed to get device (parent of ckil)
clk_register: failed to get device (parent of clock-osc-27m)
clk_register: failed to get device (parent of sys1_pll)
clk_register: failed to get device (parent of sys2_pll)
clk_register: failed to get device (parent of sys3_pll)
Enabling regulator-hub
tps65982 boot successful
Core: 192 devices, 25 uclasses, devicetree: separate
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In:serial
Out: serial
Err: serial
Board name: librem5
Board rev: 4
vol_down_key_pressed : 1
Net: No ethernet found.
Hit any key to stop autoboot: 0
u-boot=> usb start
starting USB...
Bus hub@1: generic_phy_get_by_name(dev=ffb19830, name=usb3-phy,
phy=ffb08460)
generic_phy_get_by_index_nodev(node=usb@3820, index=1,
phy=ffb08460)
generic_phy_xlate_offs_flags(phy=ffb08460)
phy3 initialized 0 usb-phy@382f0040
phy3 powered on
dwc3_glue_probe finished
generic_phy_get_by_index_nodev(node=usb@3820, index=0,
phy=ffb2b1e0)
generic_phy_xlate_offs_flags(phy=ffb2b1e0)
generic_phy_get_by_index_nodev(node=usb@3820, index=1,
phy=ffb2b1f0)
generic_phy_xlate_offs_flags(phy=ffb2b1f0)
dwc3-generic-host hub@1: Event buf ffb2b340 dma ffb2b340 length
256
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus hub@1 for devices... cannot reset port 1!?
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
u-boot=> usb info
1: Hub, USB Revision 3.0
- U-Boot XHCI Host Controller
- Class: Hub
- PacketSize: 512 Configurations: 1
- Vendor: 0x Product 0x Version 1.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms
Thanks
Angus
Thanks,
Michal
Re: DWC3 host support
On 2022-07-16 11:37, Marek Vasut wrote:
On 7/16/22 15:02, Angus Ainslie wrote:
Hi Michal,
I recently rebased my librem5 tree onto the latest u-boot-imx branch
and the dwc3 host mode stopped working.
I bisected it down to this commit:
142d50fbce7c364a74f5e8204dba491b9f066e6c usb: dwc3: Add support for
usb3-phy PHY configuration
Reverting that commit allows usb host mode to work on the librem5
again.
Should this initialization go into an SOC specific glue_configure
function ?
Is the imx8mq.dtsi missing something that will keep usb host working
with this patch ?
Does this break usb host on other imx8mq devices ?
Wasn't this fixed by:
868d58f69c ("usb: dwc3: Fix non-usb3 configurations")
?
I've got that in my tree and it still fails to probe the USB2 hub and
USB 2 storage.
Angus
Re: DWC3 host support
On 2022-07-16 06:02, Angus Ainslie wrote: Hi Michal, I recently rebased my librem5 tree onto the latest u-boot-imx branch and the dwc3 host mode stopped working. Further debugging indicates that the "U-Boot XHCI Host Controller" is detected but downstream USB 2 hubs and storage devices are not. I bisected it down to this commit: 142d50fbce7c364a74f5e8204dba491b9f066e6c usb: dwc3: Add support for usb3-phy PHY configuration Reverting that commit allows usb host mode to work on the librem5 again. Should this initialization go into an SOC specific glue_configure function ? Is the imx8mq.dtsi missing something that will keep usb host working with this patch ? Does this break usb host on other imx8mq devices ? Thanks Angus
DWC3 host support
Hi Michal, I recently rebased my librem5 tree onto the latest u-boot-imx branch and the dwc3 host mode stopped working. I bisected it down to this commit: 142d50fbce7c364a74f5e8204dba491b9f066e6c usb: dwc3: Add support for usb3-phy PHY configuration Reverting that commit allows usb host mode to work on the librem5 again. Should this initialization go into an SOC specific glue_configure function ? Is the imx8mq.dtsi missing something that will keep usb host working with this patch ? Does this break usb host on other imx8mq devices ? Thanks Angus
Re: [PATCH v4 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
On 2022-07-14 10:24, Marek Vasut wrote: On 7/14/22 17:11, Angus Ainslie wrote: Thanks, the patches will go in via next USB PR. Great, Thanks Also, thanks for reminding me of the missed patches.
[PATCH v4 2/2] configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC
Adding the SPL_USB_DWC3_GENERIC symbol broke some ti builds. This should fix the builds but untested on HW. Signed-off-by: Angus Ainslie --- configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ 9 files changed, 18 insertions(+) diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 35b1cdb4016..8503aa47b2d 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -69,6 +69,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_MISC=y +CONFIG_SPL_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -103,6 +104,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 0a4b9a99cee..8acf06d8ad8 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -8,6 +8,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_AM43XX=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 @@ -104,6 +105,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index c401d5619a9..6613177e0f4 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 @@ -102,6 +103,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 1c37b635406..2ac7028ab09 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -14,6 +14,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x28 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -121,6 +122,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 65e41e5b6af..fabb116ba44 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_SIZE=0x2 CONFIG_ENV_OFFSET=0x68 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y +CONFIG_SPL_MISC=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" CONFIG_SPL_TEXT_BASE=0x8008 CONFIG_SPL_MMC=y @@ -173,6 +174,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 7507128c11e..edfd9a74627 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y +CONFIG_SPL_MISC=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -128,6 +129,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index bd3ce11b79f..935e3531006 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_ev
[PATCH v4 1/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Suppress warnings when building the SPL without USB_DWC3_GENERIC Signed-off-by: Angus Ainslie --- drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0cd..f010291d022 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -30,6 +30,13 @@ config USB_DWC3_GENERIC Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. +config SPL_USB_DWC3_GENERIC + bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue) for the SPL" + depends on SPL_DM_USB && USB_DWC3 && SPL_MISC + help + Select this for Xilinx ZynqMP and similar Platforms. + This wrapper supports Host and Peripheral operation modes. + config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 0dd1ba87cd9..97b4f7191ca 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o -obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o +obj-$(CONFIG_$(SPL_)USB_DWC3_GENERIC) += dwc3-generic.o obj-$(CONFIG_USB_DWC3_UNIPHIER)+= dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP)+= ti_usb_phy.o -- 2.34.1
[PATCH v4 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Changes since v3: Rebased onto usb/master. Changes since v2: Add a second patch to deal with CI failures due to the new options. Changes since v1: Updated Kconfig depends Angus Ainslie (2): usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 11 files changed, 26 insertions(+), 1 deletion(-) -- 2.34.1
Re: [PATCH v3 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
On 2022-07-14 07:54, Marek Vasut wrote: On 7/14/22 16:52, Angus Ainslie wrote: On 2022-07-14 07:31, Marek Vasut wrote: On 7/14/22 16:21, Angus Ainslie wrote: Hi, Hi, Are there any problems with these patches ? I missed them, sigh ... sorry. Can you rebase them on usb/master and resend, so I can pick them up? Sure, could you remind me how to run the CI tests again. I don't think you can do that yourself unless you have a repo at source.denx.de/u-boot , but I might be wrong. Ah I found it in the gitlab ci script ./tools/buildman/buildman -o /tmp -P -E -W arm Really just run git rebase -i on git://source.denx.de/u-boot-usb.git / master and then git send-email --annontate , that's all. Ok I'll send ASAP
Re: [PATCH v3 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
On 2022-07-14 07:31, Marek Vasut wrote: On 7/14/22 16:21, Angus Ainslie wrote: Hi, Hi, Are there any problems with these patches ? I missed them, sigh ... sorry. Can you rebase them on usb/master and resend, so I can pick them up? Sure, could you remind me how to run the CI tests again.
Re: [PATCH v3 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Hi, Are there any problems with these patches ? Thanks Angus On 2022-05-30 10:15, Angus Ainslie wrote: Changes since v2: Add a second patch to deal with CI failures due to the new options. Changes since v1: Updated Kconfig depends Angus Ainslie (2): usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 11 files changed, 26 insertions(+), 1 deletion(-)
Re: [PATCH v6] board: purism: add the Purism Librem5 phone
Hi Stefano, On 2022-06-30 12:09, Stefano Babic wrote: Hi Angus, On 30.06.22 19:30, Angus Ainslie wrote: Hi All, Are there any remaining issues with this patch ? Rather yes, it was supposed that issues with dwc3 was already fixed, maybe another patch is missing - can you check this ? https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/457089 It needs the patch mentioned down below in the description. Regards, Stefano Thanks Angus On 2022-05-30 13:58, Angus Ainslie wrote: Initial commit of Librem5 u-boot and SPL All of the pre-requisite patches for this board are now upstream or in review. Changes since v5: Proper handling of the Display Port firmware for CI builds Update the DP section of the docs Changes since v4: Include imx8mq-u-boot.dtsi instead of adding a new copy Changes since v3: Dropped unused MMCROOT Rebased on u-boot-imx Needs this patch set to supress SPL warnings https://lists.denx.de/pipermail/u-boot/2022-May/485298.html Here :) Does that fix it ? Thanks Angus Changes since v2: Cleanup Kconfig symbols used in librem5.h Cleanup various checkpatch issues Drop some un-used functions Changes since v1: Merged patches into a monolithic board patch Using DM drivers for devices in u-boot Added USB storage support for uSD rootfs Dropped many SPL_BUILD guarded define's Fixed documentation index [snip]
Re: [PATCH v2 0/2] usb: dwc3: Add support for standalone DWC3 nodes
Hi Alban, On 2022-06-16 01:47, Alban Bedel wrote: Hi all, Sometimes ago I submitted a patch to fix the support for the DWC3 controller on the imx8mq which, unlike most DWC3 implementation, doesn't use a top glue node with child DWC3 nodes. Instead it has the DWC3 node directly on the main bus. Angus Ainslie then asked why this patch was needed as he had submitted the original support for the imx8mq. Looking into the issue it turned out that Angus patch basically let the driver use the `port` subnodes, which are there to define the connection to a type C connector, as DWC3 nodes. As the board I'm working on has no type C connecor, hence no `port` subnodes the driver just did nothing in my case. This new series replace my previous patch (usb: dwc3-generic: Fix the iMX8MQ support). It starts by reverting Angus patch as it was not following the DT binding and then add support for generic DWC3 without glue node. This fix the imx8mq case and might add support for a few other SoC at the same time. I tested this on my imx8mq target and it works for SDP and the USB works in Linux. If I try and use host mode in u-boot that no longer works. nop 1 [ ] dwc3-wrapper | |-- usb@3810 usb 0 [ ] dwc3-generic-periphe | | `-- usb@3810 phy 0 [ ] nxp_imx8mq_usb_phy| |-- usb-phy@381f0040 nop 2 [ + ] dwc3-wrapper | |-- usb@3820 usb 0 [ ] dwc3-generic-host | | `-- usb@3820 phy 1 [ + ] nxp_imx8mq_usb_phy| `-- usb-phy@382f0040 This is a snip from running "dm tree" and the dwc3-generic-host gets identified but the driver isn't bound. The host controller also doesn't get found when using "usb start" u-boot=> usb start starting USB... Bus usb@3820: dwc3-generic-host usb@3820: this is not a DesignWare USB3 DRD Core dwc3-generic-host usb@3820: failed to initialize core Port not available. Thanks Angus Alban -- v2: - Rebased onto current master - Fixed a typo the log message Alban Bedel (2): Revert "usb: dwc3: dwc3-generic: check the parent nodes" usb: dwc3: Add support for standalone DWC3 nodes drivers/usb/dwc3/dwc3-generic.c | 124 +--- 1 file changed, 68 insertions(+), 56 deletions(-)
Re: [PATCH v3 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Did this fix the CI issues now ? On 2022-05-30 10:15, Angus Ainslie wrote: Changes since v2: Add a second patch to deal with CI failures due to the new options. Changes since v1: Updated Kconfig depends Angus Ainslie (2): usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 11 files changed, 26 insertions(+), 1 deletion(-)
[PATCH v6] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL
All of the pre-requisite patches for this board are now upstream or in review.
Changes since v5:
Proper handling of the Display Port firmware for CI builds
Update the DP section of the docs
Changes since v4:
Include imx8mq-u-boot.dtsi instead of adding a new copy
Changes since v3:
Dropped unused MMCROOT
Rebased on u-boot-imx
Needs this patch set to supress SPL warnings
https://lists.denx.de/pipermail/u-boot/2022-May/485298.html
Changes since v2:
Cleanup Kconfig symbols used in librem5.h
Cleanup various checkpatch issues
Drop some un-used functions
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 24 +
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |9 +
board/purism/librem5/librem5.c | 425 ++
board/purism/librem5/librem5.h | 181 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 593
configs/librem5_defconfig| 142 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 113 ++
19 files changed, 5409 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8187e6d72c..30f0a3ed44 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -945,7 +945,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-venice-gw74xx.dtb \
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 00..9d0a54a32f
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
+ { /* console */
+ u-boot,dm-spl;
+};
+
+ {
+ /delete-node/ signed-hdmi;
+
+ signed-hdmi {
+ filename = "signed_hdmi.bin";
+
+ signed-dp-imx8m {
+ filename = "signed_dp_imx8m.bin";
+ type = "blob-ext";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts
b/arch/arm/dts/imx8mq-librem5-r4.dts
new file mode 100644
index 00..cbfb49aa25
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Purism SPC
+
+/dts-v1/;
+
+#include "imx8mq-librem5.dtsi"
+
+/ {
+ model = "Purism Librem 5r4";
+ compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
+};
+
+_gyro {
+ mount-matrix = "1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+};
+
+ {
+ maxim,rsns-microohm = <1667>;
+};
+
+ {
+ ti,battery-regulation-voltage = <420>; /* uV
[PATCH v3 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Changes since v2: Add a second patch to deal with CI failures due to the new options. Changes since v1: Updated Kconfig depends Angus Ainslie (2): usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 11 files changed, 26 insertions(+), 1 deletion(-) -- 2.34.1
[PATCH v3 2/2] configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC
Adding the SPL_USB_DWC3_GENERIC symbol broke some ti builds. This should fix the builds but untested on HW. Signed-off-by: Angus Ainslie --- configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ 9 files changed, 18 insertions(+) diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 7a736b6fe1..13a305a53c 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -59,6 +59,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_MISC=y +CONFIG_SPL_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -93,6 +94,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index e844106243..b1f17c6a9e 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -8,6 +8,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_AM43XX=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -94,6 +95,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index d436b41a0c..206e5cf7bc 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -97,6 +98,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 194103a7e6..9cfc31cb9f 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -14,6 +14,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x28 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -114,6 +115,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 9f41b397c3..8cf24dd25f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_SIZE=0x2 CONFIG_ENV_OFFSET=0x68 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y +CONFIG_SPL_MISC=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" CONFIG_SPL_TEXT_BASE=0x8008 CONFIG_SPL_MMC=y @@ -163,6 +164,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 57cd0f35a5..0430a94a7c 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y +CONFIG_SPL_MISC=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -111,6 +112,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index e972d3b117..f118c172fe 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x403000
[PATCH v3 1/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Suppress warnings when building the SPL without USB_DWC3_GENERIC Signed-off-by: Angus Ainslie --- drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0c..f010291d02 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -30,6 +30,13 @@ config USB_DWC3_GENERIC Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. +config SPL_USB_DWC3_GENERIC + bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue) for the SPL" + depends on SPL_DM_USB && USB_DWC3 && SPL_MISC + help + Select this for Xilinx ZynqMP and similar Platforms. + This wrapper supports Host and Peripheral operation modes. + config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 0dd1ba87cd..97b4f7191c 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o -obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o +obj-$(CONFIG_$(SPL_)USB_DWC3_GENERIC) += dwc3-generic.o obj-$(CONFIG_USB_DWC3_UNIPHIER)+= dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP)+= ti_usb_phy.o -- 2.34.1
Re: [PATCH v5] board: purism: add the Purism Librem5 phone
On 2022-05-24 08:10, Tom Rini wrote:
On Tue, May 24, 2022 at 07:15:01AM -0700, Angus Ainslie wrote:
Hi Stefano,
On 2022-05-23 02:36, Stefano Babic wrote:
> On 06.05.22 14:44, Angus Ainslie wrote:
> > Initial commit of Librem5 u-boot and SPL
> >
> > Signed-off-by: Angus Ainslie
> > Co-developed-by: Sebastian Krzyszkowiak
> >
> > Signed-off-by: Sebastian Krzyszkowiak
> > ---
>
> Hi Angus,
>
> with "configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC"
> most issues are solved, but a TI board is still broken.
>
I'll resend the patch that includes a fix for the aarch64 board.
> A second issue is for the blob signed_dp_imx8m.bin, it should be done
> like for signed_hdmi.bin to avoid CI breakages.
>
> Here the result of pipeline:
>
> https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/437965
>
I see that the imx8mq_evk does not fail CI build but I'm not seeing
how the
missing signed_hdmi.bin file is handled. Any hints ?
You need to use binman to handle it, does
arch/arm/dts/imx8mq-u-boot.dtsi provide some clues?
Currently the librem5-r4-u-boot.dtsi ( text below ) includes
imx8mq-u-boot.dtsi and I tried deleting the signed-hdmi and including a
signed-dp in it's place. Now instead of an error about a missing
"signed_hdmi_imx8m.bin" I get an error about a missing
"signed_dp_imx8m.bin" so I know I'm having an effect but not enough of
one.
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mq-u-boot.dtsi"
_uart1 {
u-boot,dm-spl;
};
{ /* console */
u-boot,dm-spl;
};
{
/delete-node/ signed-hdmi;
signed-dp {
filename = "signed_dp_imx8m.bin";
signed-dp-imx8m {
filename = "signed_dp_imx8m.bin";
type = "blob-ext";
};
};
};
Re: [PATCH v5] board: purism: add the Purism Librem5 phone
Hi Stefano, On 2022-05-23 02:36, Stefano Babic wrote: On 06.05.22 14:44, Angus Ainslie wrote: Initial commit of Librem5 u-boot and SPL Signed-off-by: Angus Ainslie Co-developed-by: Sebastian Krzyszkowiak Signed-off-by: Sebastian Krzyszkowiak --- Hi Angus, with "configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC" most issues are solved, but a TI board is still broken. I'll resend the patch that includes a fix for the aarch64 board. A second issue is for the blob signed_dp_imx8m.bin, it should be done like for signed_hdmi.bin to avoid CI breakages. Here the result of pipeline: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/437965 I see that the imx8mq_evk does not fail CI build but I'm not seeing how the missing signed_hdmi.bin file is handled. Any hints ? Thanks Angus Best regards, Stefano
[PATCH] configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC
Adding the SPL_USB_DWC3_GENERIC symbol broke some ti builds. This should fix the builds but untested on HW. Signed-off-by: Angus Ainslie --- configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ 8 files changed, 16 insertions(+) diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 7a736b6fe1..13a305a53c 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -59,6 +59,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_MISC=y +CONFIG_SPL_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -93,6 +94,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index e844106243..b1f17c6a9e 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -8,6 +8,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_AM43XX=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -94,6 +95,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index d436b41a0c..206e5cf7bc 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -97,6 +98,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 6514a4f20c..dee35839c4 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -14,6 +14,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x28 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -115,6 +116,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 57cd0f35a5..0430a94a7c 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y +CONFIG_SPL_MISC=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -111,6 +112,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 1aee9d742c..db7eb8efe9 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x4030 CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x28 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -137,6 +138,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 728515d433..7796419f6b 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -13,6 +13,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0
Re: [PATCH v2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
On 2022-05-20 05:31, Stefano Babic wrote: On 20.05.22 12:21, Marek Vasut wrote: On 5/20/22 11:08, Stefano Babic wrote: Hi Marek, don't you mind if I apply to my u-booz-imx this (that really belongs to your competence area) ? It fixes warnings for the librem5, and it is a pity if I cannot merge it. Just pick it via imx, that's fine, I don't expect conflict. Rather it breaks some TI boards - Angus, can you take a look and possibly run buildman for ARM32 boards ? This a link for the failure : https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/437210 I put Libre5 in standby, but I will still merge for the release if the problem is solved. The fix is probably as simple as adding SPL_USB_DWC3_GENERIC to all configs where USB_DWC3_GENERIC was already defined. I'll try and verify that today. Thanks Angus Regards, Stefano
[PATCH v5] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
All of the pre-requisite patches for this board are now upstream or in review.
Changes since v4:
Include imx8mq-u-boot.dtsi instead of adding a new copy
Changes since v3:
Dropped unused MMCROOT
Rebased on u-boot-imx
Needs this patch to supress SPL warnings
https://lists.denx.de/pipermail/u-boot/2022-April/482369.html
Changes since v2:
Cleanup Kconfig symbols used in librem5.h
Cleanup various checkpatch issues
Drop some un-used functions
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi |3 +
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |8 +
board/purism/librem5/librem5.c | 425 ++
board/purism/librem5/librem5.h | 181 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 593
configs/librem5_defconfig| 142 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 113 ++
19 files changed, 5387 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 90f86e3fca..719fd7db8d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -937,7 +937,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-venice-gw74xx.dtb \
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 00..8a68f53ace
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts
b/arch/arm/dts/imx8mq-librem5-r4.dts
new file mode 100644
index 00..cbfb49aa25
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Purism SPC
+
+/dts-v1/;
+
+#include "imx8mq-librem5.dtsi"
+
+/ {
+ model = "Purism Librem 5r4";
+ compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
+};
+
+_gyro {
+ mount-matrix = "1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+};
+
+ {
+ maxim,rsns-microohm = <1667>;
+};
+
+ {
+ ti,battery-regulation-voltage = <420>; /* uV */
+ ti,charge-current = <150>; /* uA */
+ ti,termination-current = <144000>; /* uA */
+};
+
+_backlight {
+ led-max-microamp = <25000>;
+};
+
+ {
+ proximity-near-level = <10>;
+};
diff --git a/arch/arm/dts/imx8mq-librem5.dtsi b/arch/arm/dts/imx8mq-librem5.dtsi
new file mode 100644
index 00..60d47c7149
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5.dtsi
@@ -0,0 +1,1255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2020 Purism SPC
+ */
[PATCH v4] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
All of the pre-requisite patches for this board are now upstream or in review.
Changes since v3:
Dropped unused MMCROOT
Rebased on u-boot-imx
Needs this patch to supress SPL warnings
https://lists.denx.de/pipermail/u-boot/2022-April/482369.html
Changes since v2:
Cleanup Kconfig symbols used in librem5.h
Cleanup various checkpatch issues
Drop some un-used functions
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 134 ++
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |8 +
board/purism/librem5/librem5.c | 425 ++
board/purism/librem5/librem5.h | 181 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 593
configs/librem5_defconfig| 142 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 113 ++
19 files changed, 5518 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 90f86e3fca..719fd7db8d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -937,7 +937,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-venice-gw74xx.dtb \
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 00..e3f780ca75
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+
[PATCH v2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Suppress warnings when building the SPL without USB_DWC3_GENERIC Signed-off-by: Angus Ainslie --- Changes since v1: Updated Kconfig depends drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0c..f010291d02 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -30,6 +30,13 @@ config USB_DWC3_GENERIC Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. +config SPL_USB_DWC3_GENERIC + bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue) for the SPL" + depends on SPL_DM_USB && USB_DWC3 && SPL_MISC + help + Select this for Xilinx ZynqMP and similar Platforms. + This wrapper supports Host and Peripheral operation modes. + config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 0dd1ba87cd..97b4f7191c 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o -obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o +obj-$(CONFIG_$(SPL_)USB_DWC3_GENERIC) += dwc3-generic.o obj-$(CONFIG_USB_DWC3_UNIPHIER)+= dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP)+= ti_usb_phy.o -- 2.34.1
Re: [PATCH v3] board: purism: add the Purism Librem5 phone
On 2022-04-22 02:15, Stefano Babic wrote: Hi Angus, On 20.04.22 20:13, Angus Ainslie wrote: Initial commit of Librem5 u-boot and SPL [snip] After merging a patch on dwc3, build reports some warnings (functions defined and not used). Could you fix them ? This patch should silence the warnings https://lists.denx.de/pipermail/u-boot/2022-April/482313.html [snip] + +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ You do not use this in your code, and this variable was drop in another series and it is not more in the whitelist. Simply drop the line. I'll fix that up in v4 Thanks Angus + +#define CONFIG_SYS_SDRAM_BASE 0x4000 +#define PHYS_SDRAM 0x4000 +#define PHYS_SDRAM_SIZE0xc000 /* 3GB LPDDR4 one Rank */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#endif Best regards, Stefano
[PATCH] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
Suppress warnings when building the SPL without USB_DWC3_GENERIC Signed-off-by: Angus Ainslie --- drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0c..93dffeb1f9 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -30,6 +30,13 @@ config USB_DWC3_GENERIC Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. +config SPL_USB_DWC3_GENERIC + bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue) for the SPL" + depends on DM_USB && USB_DWC3 && MISC + help + Select this for Xilinx ZynqMP and similar Platforms. + This wrapper supports Host and Peripheral operation modes. + config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 0dd1ba87cd..97b4f7191c 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o -obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o +obj-$(CONFIG_$(SPL_)USB_DWC3_GENERIC) += dwc3-generic.o obj-$(CONFIG_USB_DWC3_UNIPHIER)+= dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP)+= ti_usb_phy.o -- 2.34.1
Re: [PATCH] spl: spl_sdp: don't call board_usb_init twice
Hi On 2022-01-17 06:11, Angus Ainslie wrote: When CONFIG_DM_USB is not defined then usb_gadget_initialize is just a call to board_usb_init. Calling board_usb_init twice causes the USB to fail so make sure the second invocation is not compiled in when CONFIG_DM_USB is not defined. Signed-off-by: Angus Ainslie --- common/spl/spl_sdp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index ae9c09883a..2a2bc8475d 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -17,7 +17,8 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image, int ret; const int controller_index = CONFIG_SPL_SDP_USB_DEV; - usb_gadget_initialize(controller_index); + if (IS_ENABLED(CONFIG_DM_USB)) + usb_gadget_initialize(controller_index); board_usb_init(0, USB_INIT_DEVICE); Any comments on this patch ? Thanks Angus
Re: [PATCH v3] drivers: spi-nor: Add JEDEC id for W25Q16JV
Hi Jagan, [snip] On 2022-01-20 06:39, Jagan Teki wrote: Okay, I'm merging v3. let me know if you have any questions? I didn't see this go in yet. Should it be in u-boot master ? Thanks Angus Thanks, Jagan.
Re: [PATCH v2] board: purism: add the Purism Librem5 phone
Hi Stefano, On 2022-04-11 09:21, Stefano Babic wrote: Hi Angus, build is not started after merging your board. It is checked that symbols (CONFIG_) defined in Kbuild are not sert in header file, that is include/configs/librem5.h. I can recognize several of them, like CONFIG_SYS_MALLOC_F_LEN, CONFIG_SYS_TEXT_BASE, CONFIG_SYS_PROMPT,... See the broken pipeline here: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/420970 Please fix and repost, thanks ! Just sent a v3. Thanks Angus Best regards, Stefano Babic
[PATCH v3] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
All of the pre-requisite patches for this board are now upstream or in review.
Changes since v2:
Cleanup Kconfig symbols used in librem5.h
Cleanup various checkpatch issues
Drop some un-used functions
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 134 ++
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |8 +
board/purism/librem5/librem5.c | 425 ++
board/purism/librem5/librem5.h | 181 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 593
configs/librem5_defconfig| 142 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 115 ++
19 files changed, 5520 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a0efd8eda..df1081b403 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -936,7 +936,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 00..e3f780ca75
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF
Re: [PATCH] usb: dwc3-generic: Fix the iMX8MQ support
Hi Alban,
On 2022-04-19 01:07, Alban Bedel wrote:
The binding of iMX8MQ USB controller doesn't use child nodes like the
other devices supported in this driver. To support it split the child
nodes parsing to its own function and add a field to the platform data
to indicate that we should just use the top node.
I'm not clear on what this is fixing. Doesn't the original code deal
with a devicetree stanza that has the information in either the node or
the parent.
Which case does this fix ?
Thanks
Angus
Signed-off-by: Alban Bedel
---
drivers/usb/dwc3/dwc3-generic.c | 95 +++--
1 file changed, 56 insertions(+), 39 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c
b/drivers/usb/dwc3/dwc3-generic.c
index 01bd0ca190e3..defef43ff503 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -221,6 +221,7 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
struct dwc3_glue_ops {
void (*select_dr_mode)(struct udevice *dev, int index,
enum usb_dr_mode mode);
+ int single_node;
};
void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
@@ -307,54 +308,66 @@ struct dwc3_glue_ops ti_ops = {
.select_dr_mode = dwc3_ti_select_dr_mode,
};
+static int dwc3_glue_bind_node(struct udevice *parent, ofnode node,
+ enum usb_dr_mode dr_mode)
+{
+ const char *name = ofnode_get_name(node);
+ const char *driver = NULL;
+ struct udevice *dev;
+ int ret;
+
+ debug("%s: subnode name: %s\n", __func__, name);
+
+ /* if the parent node doesn't have a mode check the leaf */
+ if (!dr_mode)
+ dr_mode = usb_get_dr_mode(node);
+
+ switch (dr_mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ case USB_DR_MODE_OTG:
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+ debug("%s: dr_mode: OTG or Peripheral\n", __func__);
+ driver = "dwc3-generic-peripheral";
+#endif
+ break;
+#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
+ case USB_DR_MODE_HOST:
+ debug("%s: dr_mode: HOST\n", __func__);
+ driver = "dwc3-generic-host";
+ break;
+#endif
+ default:
+ debug("%s: unsupported dr_mode\n", __func__);
+ return -ENODEV;
+ };
+
+ if (!driver)
+ return 0;
+
+ ret = device_bind_driver_to_node(parent, driver, name,
+node, );
+ if (ret)
+ debug("%s: not able to bind usb device mode\n",
+ __func__);
+ return ret;
+}
+
static int dwc3_glue_bind(struct udevice *parent)
{
+ struct dwc3_glue_ops *ops = (struct dwc3_glue_ops
*)dev_get_driver_data(parent);
ofnode node;
int ret;
enum usb_dr_mode dr_mode;
+ if (ops->single_node)
+ return dwc3_glue_bind_node(parent, dev_ofnode(parent), 0);
+
dr_mode = usb_get_dr_mode(dev_ofnode(parent));
ofnode_for_each_subnode(node, dev_ofnode(parent)) {
- const char *name = ofnode_get_name(node);
- struct udevice *dev;
- const char *driver = NULL;
-
- debug("%s: subnode name: %s\n", __func__, name);
-
- /* if the parent node doesn't have a mode check the leaf */
- if (!dr_mode)
- dr_mode = usb_get_dr_mode(node);
-
- switch (dr_mode) {
- case USB_DR_MODE_PERIPHERAL:
- case USB_DR_MODE_OTG:
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
- debug("%s: dr_mode: OTG or Peripheral\n", __func__);
- driver = "dwc3-generic-peripheral";
-#endif
- break;
-#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
- case USB_DR_MODE_HOST:
- debug("%s: dr_mode: HOST\n", __func__);
- driver = "dwc3-generic-host";
- break;
-#endif
- default:
- debug("%s: unsupported dr_mode\n", __func__);
- return -ENODEV;
- };
-
- if (!driver)
- continue;
-
- ret = device_bind_driver_to_node(parent, driver, name,
-node, );
- if (ret) {
- debug("%s: not able to bind usb device mode\n",
- __func__);
+ ret = dwc3_glue_bind_node(parent, node, dr_mode);
+ if (ret)
return ret;
- }
}
return 0;
@@ -454,6 +467,10 @@ static int dwc3_glue_remove(struct udevice *dev)
return 0;
}
+struct dwc3_glue_ops single_node_ops = {
+ .single_node = 1,
+};
+
static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "xlnx,zynqmp-dwc3" },
Re: [PATCH 07/10] dm: core: Allow devres to be disabled in SPL
On 2022-03-27 13:26, Simon Glass wrote:
At present if devres is enabled in U-Boot proper it is enabled in SPL.
We don't normally want it there, so disable it.
Signed-off-by: Simon Glass
Tested-by: Angus Ainslie
---
drivers/core/Makefile| 2 +-
drivers/core/device.c| 2 +-
include/dm/device-internal.h | 6 +++---
include/dm/device.h | 2 +-
include/dm/devres.h | 4 ++--
test/dm/Makefile | 2 +-
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index 5edd4e41357..0cbc3ab217e 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -4,7 +4,7 @@
obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o
obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi.o
-obj-$(CONFIG_DEVRES) += devres.o
+obj-$(CONFIG_$(SPL_TPL_)DEVRES) += devres.o
obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o
obj-$(CONFIG_$(SPL_)SIMPLE_BUS)+= simple-bus.o
obj-$(CONFIG_SIMPLE_PM_BUS)+= simple-pm-bus.o
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 1b356f12dd8..b7ce8544140 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -68,7 +68,7 @@ static int device_bind_common(struct udevice
*parent, const struct driver *drv,
INIT_LIST_HEAD(>sibling_node);
INIT_LIST_HEAD(>child_head);
INIT_LIST_HEAD(>uclass_node);
-#ifdef CONFIG_DEVRES
+#if CONFIG_IS_ENABLED(DEVRES)
INIT_LIST_HEAD(>devres_head);
#endif
dev_set_plat(dev, plat);
diff --git a/include/dm/device-internal.h
b/include/dm/device-internal.h
index c420726287e..2fc41f31f5a 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -396,7 +396,7 @@ fdt_addr_t simple_bus_translate(struct udevice
*dev, fdt_addr_t addr);
#define DM_UCLASS_ROOT_S_NON_CONST (((gd_t *)gd)->uclass_root_s)
/* device resource management */
-#ifdef CONFIG_DEVRES
+#if CONFIG_IS_ENABLED(DEVRES)
/**
* devres_release_probe - Release managed resources allocated after
probing
@@ -416,7 +416,7 @@ void devres_release_probe(struct udevice *dev);
*/
void devres_release_all(struct udevice *dev);
-#else /* ! CONFIG_DEVRES */
+#else /* ! DEVRES */
static inline void devres_release_probe(struct udevice *dev)
{
@@ -426,7 +426,7 @@ static inline void devres_release_all(struct
udevice *dev)
{
}
-#endif /* ! CONFIG_DEVRES */
+#endif /* DEVRES */
static inline int device_notify(const struct udevice *dev, enum
event_t type)
{
diff --git a/include/dm/device.h b/include/dm/device.h
index cb52a0997c8..3d8961f9ac6 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -184,7 +184,7 @@ struct udevice {
#if CONFIG_IS_ENABLED(OF_REAL)
ofnode node_;
#endif
-#ifdef CONFIG_DEVRES
+#if CONFIG_IS_ENABLED(DEVRES)
struct list_head devres_head;
#endif
#if CONFIG_IS_ENABLED(DM_DMA)
diff --git a/include/dm/devres.h b/include/dm/devres.h
index 0ab277ec38e..697534aa5be 100644
--- a/include/dm/devres.h
+++ b/include/dm/devres.h
@@ -30,7 +30,7 @@ struct devres_stats {
int total_size;
};
-#ifdef CONFIG_DEVRES
+#if CONFIG_IS_ENABLED(DEVRES)
#ifdef CONFIG_DEBUG_DEVRES
void *__devres_alloc(dr_release_t release, size_t size, gfp_t gfp,
@@ -207,7 +207,7 @@ void devm_kfree(struct udevice *dev, void *ptr);
/* Get basic stats on allocations */
void devres_get_stats(const struct udevice *dev, struct devres_stats
*stats);
-#else /* ! CONFIG_DEVRES */
+#else /* ! DEVRES */
static inline void *devres_alloc(dr_release_t release, size_t size,
gfp_t gfp)
{
diff --git a/test/dm/Makefile b/test/dm/Makefile
index d46552fbf32..9a1a904d906 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_CLK) += clk.o clk_ccf.o
obj-$(CONFIG_CPU) += cpu.o
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
-obj-$(CONFIG_DEVRES) += devres.o
+obj-$(CONFIG_$(SPL_TPL_)DEVRES) += devres.o
obj-$(CONFIG_DMA) += dma.o
obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o
obj-$(CONFIG_DM_DSA) += dsa.o
Re: [PATCH v6 0/3] Add a clock driver for the imx8mq
Please ignore. I introduced some unused variables. v7 sent. Angus On 2022-03-29 06:52, Angus Ainslie wrote: This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v5 Added UART clocks Added video clocks Added DRAM clocks Changes since v4 Rebased onto [1] so patch 4 of 4 was dropped. Added CLK_COMPOSITE_CCF Fixed const* clock definitions Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel [1]https://patchwork.ozlabs.org/project/uboot/patch/20220320203446.740178-2-sean...@gmail.com/
[PATCH v7 3/3] clk: imx8m: reduce rate table duplication
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
place")
Signed-off-by: Angus Ainslie
Tested-by: Adam Ford #imx8mm-beacon
---
drivers/clk/imx/clk-imx8mm.c | 60 +++-
drivers/clk/imx/clk-imx8mn.c | 60 +++-
drivers/clk/imx/clk-imx8mp.c | 65 ++-
drivers/clk/imx/clk-imx8mq.c | 59 ---
drivers/clk/imx/clk-pll14xx.c | 61
drivers/clk/imx/clk.h | 4 +++
6 files changed, 91 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 443bbdae332..11213212620 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
- PLL_1416X_RATE(18U, 225, 3, 0),
- PLL_1416X_RATE(16U, 200, 3, 0),
- PLL_1416X_RATE(12U, 300, 3, 1),
- PLL_1416X_RATE(10U, 250, 3, 1),
- PLL_1416X_RATE(8U, 200, 3, 1),
- PLL_1416X_RATE(75000U, 250, 2, 2),
- PLL_1416X_RATE(7U, 350, 3, 2),
- PLL_1416X_RATE(6U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
- PLL_1443X_RATE(65000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mm_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
@@ -164,19 +114,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, _dram_pll));
+ base + 0x50, _1443x_dram_pll));
clk_dm(IMX8MM_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, _arm_pll));
+ base + 0x84, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, _sys_pll));
+ base + 0x94, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, _sys_pll));
+ base + 0x104, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, _sys_pll));
+ base + 0x114, _1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index bb62138f8ca..15d7599cfb7 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv
[PATCH v7 2/3] clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie
Acked-by: Sean Anderson
---
drivers/clk/imx/Kconfig | 18 ++
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 550 +++
3 files changed, 570 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..04d252a1e03 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,24 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ select CLK_COMPOSITE_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..c5766901f2b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000..1aa7c2c86e2
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mq_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
+};
+
+static const char *const pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *const arm_pll_bypass_sels[] = {"arm_pll",
"arm_pll_ref_sel", };
+static const char *const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char *const vpu_pll_byp
[PATCH v7 1/3] dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie
Reviewed-by: Marek Vasut
---
include/dt-bindings/clock/imx8mq-clock.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h
b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8..82e907ce7bd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
#define IMX8MQ_CLK_A53_CORE289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
+#define IMX8MQ_CLK_MON_SEL 301
+#define IMX8MQ_CLK_MON_CLK2_OUT302
+
+#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.25.1
[PATCH v7 0/3] Add a clock driver for the imx8mq
This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v6 Fixed unused variable warning Changes since v5 Added UART clocks Added video clocks Added DRAM clocks Changes since v4 Rebased onto [1] so patch 4 of 4 was dropped. Added CLK_COMPOSITE_CCF Fixed const* clock definitions Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel [1] https://patchwork.ozlabs.org/project/uboot/patch/20220320203446.740178-2-sean...@gmail.com/ Angus Ainslie (3): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication drivers/clk/imx/Kconfig | 18 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx8mm.c | 60 +-- drivers/clk/imx/clk-imx8mn.c | 60 +-- drivers/clk/imx/clk-imx8mp.c | 65 +-- drivers/clk/imx/clk-imx8mq.c | 503 +++ drivers/clk/imx/clk-pll14xx.c| 61 +++ drivers/clk/imx/clk.h| 4 + include/dt-bindings/clock/imx8mq-clock.h | 16 +- 9 files changed, 623 insertions(+), 166 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1
[PATCH v6 3/3] clk: imx8m: reduce rate table duplication
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
place")
Signed-off-by: Angus Ainslie
Tested-by: Adam Ford #imx8mm-beacon
---
drivers/clk/imx/clk-imx8mm.c | 60 +++-
drivers/clk/imx/clk-imx8mn.c | 60 +++-
drivers/clk/imx/clk-imx8mp.c | 65 ++-
drivers/clk/imx/clk-imx8mq.c | 59 ---
drivers/clk/imx/clk-pll14xx.c | 61
drivers/clk/imx/clk.h | 4 +++
6 files changed, 91 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 443bbdae332..11213212620 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
- PLL_1416X_RATE(18U, 225, 3, 0),
- PLL_1416X_RATE(16U, 200, 3, 0),
- PLL_1416X_RATE(12U, 300, 3, 1),
- PLL_1416X_RATE(10U, 250, 3, 1),
- PLL_1416X_RATE(8U, 200, 3, 1),
- PLL_1416X_RATE(75000U, 250, 2, 2),
- PLL_1416X_RATE(7U, 350, 3, 2),
- PLL_1416X_RATE(6U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
- PLL_1443X_RATE(65000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mm_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
@@ -164,19 +114,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, _dram_pll));
+ base + 0x50, _1443x_dram_pll));
clk_dm(IMX8MM_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, _arm_pll));
+ base + 0x84, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, _sys_pll));
+ base + 0x94, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, _sys_pll));
+ base + 0x104, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, _sys_pll));
+ base + 0x114, _1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index bb62138f8ca..15d7599cfb7 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv
[PATCH v6 2/3] clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie
Acked-by: Sean Anderson
---
drivers/clk/imx/Kconfig | 18 ++
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 552 +++
3 files changed, 572 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..04d252a1e03 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,24 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ select CLK_COMPOSITE_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..c5766901f2b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000..4b925265255
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,552 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mq_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
+};
+
+static const char *const pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *const arm_pll_bypass_sels[] = {"arm_pll",
"arm_pll_ref_sel", };
+static const char *const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char *const vpu_pll_byp
[PATCH v6 1/3] dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie
Reviewed-by: Marek Vasut
---
include/dt-bindings/clock/imx8mq-clock.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h
b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8..82e907ce7bd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
#define IMX8MQ_CLK_A53_CORE289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
+#define IMX8MQ_CLK_MON_SEL 301
+#define IMX8MQ_CLK_MON_CLK2_OUT302
+
+#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.25.1
[PATCH v6 0/3] Add a clock driver for the imx8mq
This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v5 Added UART clocks Added video clocks Added DRAM clocks Changes since v4 Rebased onto [1] so patch 4 of 4 was dropped. Added CLK_COMPOSITE_CCF Fixed const* clock definitions Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel [1] https://patchwork.ozlabs.org/project/uboot/patch/20220320203446.740178-2-sean...@gmail.com/ Angus Ainslie (3): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication drivers/clk/imx/Kconfig | 18 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx8mm.c | 60 +-- drivers/clk/imx/clk-imx8mn.c | 60 +-- drivers/clk/imx/clk-imx8mp.c | 65 +-- drivers/clk/imx/clk-imx8mq.c | 505 +++ drivers/clk/imx/clk-pll14xx.c| 61 +++ drivers/clk/imx/clk.h| 4 + include/dt-bindings/clock/imx8mq-clock.h | 16 +- 9 files changed, 625 insertions(+), 166 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1
Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
Hi Heiko, On 2022-03-24 01:28, Heiko Thiery wrote: Hi Angus, could you include the UART clocks? Sure I can add the UART clocks. We've also found an issue with devfreq using the current setup so it might be a few days before I send an update. Angus
Re: [PATCH v5 3/3] clk: imx8m: reduce rate table duplication
On 2022-03-22 06:49, Adam Ford wrote:
On Tue, Mar 22, 2022 at 8:02 AM Angus Ainslie wrote:
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to
common place")
I did a clk dump before this series and after this series then
compared the outputs to look for changes on an imx8mm. None were
identified.
Tested-by: Adam Ford #imx8mm-beacon
Thanks Adam
[PATCH v5 3/3] clk: imx8m: reduce rate table duplication
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
place")
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/clk-imx8mm.c | 60 +++-
drivers/clk/imx/clk-imx8mn.c | 60 +++-
drivers/clk/imx/clk-imx8mp.c | 65 ++-
drivers/clk/imx/clk-imx8mq.c | 59 ---
drivers/clk/imx/clk-pll14xx.c | 61
drivers/clk/imx/clk.h | 4 +++
6 files changed, 91 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 443bbdae332..11213212620 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
- PLL_1416X_RATE(18U, 225, 3, 0),
- PLL_1416X_RATE(16U, 200, 3, 0),
- PLL_1416X_RATE(12U, 300, 3, 1),
- PLL_1416X_RATE(10U, 250, 3, 1),
- PLL_1416X_RATE(8U, 200, 3, 1),
- PLL_1416X_RATE(75000U, 250, 2, 2),
- PLL_1416X_RATE(7U, 350, 3, 2),
- PLL_1416X_RATE(6U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
- PLL_1443X_RATE(65000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mm_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
@@ -164,19 +114,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, _dram_pll));
+ base + 0x50, _1443x_dram_pll));
clk_dm(IMX8MM_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, _arm_pll));
+ base + 0x84, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, _sys_pll));
+ base + 0x94, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, _sys_pll));
+ base + 0x104, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, _sys_pll));
+ base + 0x114, _1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index bb62138f8ca..15d7599cfb7 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv
[PATCH v5 2/3] clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie
Acked-by: Sean Anderson
---
drivers/clk/imx/Kconfig | 18 ++
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 487 +++
3 files changed, 507 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..04d252a1e03 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,24 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ select CLK_COMPOSITE_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..c5766901f2b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000..2a861c3edb9
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mq_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
+};
+
+static const char *const pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *const arm_pll_bypass_sels[] = {"arm_pll",
"arm_pll_ref_sel", };
+static const char *const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char *const vpu_pll_byp
[PATCH v5 1/3] dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie
Reviewed-by: Marek Vasut
---
include/dt-bindings/clock/imx8mq-clock.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h
b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8..82e907ce7bd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
#define IMX8MQ_CLK_A53_CORE289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
+#define IMX8MQ_CLK_MON_SEL 301
+#define IMX8MQ_CLK_MON_CLK2_OUT302
+
+#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.25.1
[PATCH v5 0/3] Add a clock driver for the imx8mq
This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since V4 Rebased onto [1] so patch 4 of 4 was dropped. Added CLK_COMPOSITE_CCF Fixed const* clock definitions Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel [1] https://patchwork.ozlabs.org/project/uboot/patch/20220320203446.740178-2-sean...@gmail.com/ Angus Ainslie (3): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication drivers/clk/imx/Kconfig | 18 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx8mm.c | 60 +--- drivers/clk/imx/clk-imx8mn.c | 60 +--- drivers/clk/imx/clk-imx8mp.c | 65 +--- drivers/clk/imx/clk-imx8mq.c | 440 +++ drivers/clk/imx/clk-pll14xx.c| 61 drivers/clk/imx/clk.h| 4 + include/dt-bindings/clock/imx8mq-clock.h | 16 +- 9 files changed, 560 insertions(+), 166 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1
Re: [RFC] serial: mxc: get the clock frequency from the used clock for the device
On 2022-03-21 06:50, Heiko Thiery wrote: Hi Angus, [snip] > So I'm not sure if the ipg clock is the right one for the boards that > has different clock for ipg and per. So I only looked at imx6qdl.dtsi where the clocks are different clocks = < IMX6QDL_CLK_UART_IPG>, < IMX6QDL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; And from that file it looks like the per clock would be the correct one. Yes, 'per' seems to be the right one. Should the clock be looked up by id instead of by name and then have a different code path for each imx board type ? But how to get the right clk id? The id's for all the implementations are different. Or not? Yeah you're correct that won't work. > >> > + } >> > + >> > + /* as fallback we try to get the clk rate that way */ >> > + if (rate == 0) >> > + rate = imx_get_uartclk(); >> >> Would it be better to re-write imx_get_uartclk so that both the >> getting >> and setting of clocks was correct ? > > I do not understand what you mean with that. > There are other places in the code that imx_get_uartclk gets called. If an index was added to imx_get_uartclk(int index) then you wouldn't need the code above in the mxc_serial_setbrg function. That would also make all of the places where imx_get_uartclk gets called return the correct value. By index do you mean the clk id? No I was thinking number of the device uart[0-3]. Thinking about it some more it's probably not useful as you already have the udevice pointer. I was just trying to think of ways to reduce the amount of code change for the older SOCs. Using the 'per' clock is a better solution. It might make sense to create a new function imx7_get_uartclk that gets called on newer SOCs so that the imx6 and earlier code doesn't need to get changed. At what point should this be called instead of the imx_get_uartclk() function? I was thinking a CONFIG_IS_ENBLED switch between the old version and the new one based on SOC. Angus
Re: [PATCH v2] core: devres: optionally build devres into the SPL
On 2022-03-19 07:15, Angus Ainslie wrote: Hi Simon, On 2022-03-18 15:41, Simon Glass wrote: Hi Angus, On Tue, 1 Mar 2022 at 07:58, Simon Glass wrote: On Mon, 28 Feb 2022 at 13:33, Angus Ainslie wrote: > > Add a CONFIG_SPL_DEVRES option > > Signed-off-by: Angus Ainslie > --- > > Changes since v1: > > Instead of gaurding the source add an SPL_DEVRES option > > drivers/core/Kconfig | 13 + > drivers/core/Makefile | 2 +- > 2 files changed, 14 insertions(+), 1 deletion(-) Unfortunately this break the tests, e.g. building sandbox_spl - can you please take a look? sandbox_spl: +make O=build-sandbox_spl -s sandbox_spl_defconfig +make O=build-sandbox_spl -s -j4 /usr/bin/ld: /tmp/ccsYY64W.ltrans0.ltrans.o: in function `device_unbind': build-sandbox_spl/spl/../../drivers/core/device-remove.c:120: undefined reference to `devres_release_all' /usr/bin/ld: /tmp/ccsYY64W.ltrans0.ltrans.o: in function `device_free': build-sandbox_spl/spl/../../drivers/core/device-remove.c:157: undefined reference to `devres_release_probe' collect2: error: ld returned 1 exit status make[3]: *** [../scripts/Makefile.spl:509: spl/u-boot-spl] Error 1 make[2]: *** [Makefile:2094: spl/u-boot-spl] Error 2 make[1]: *** [Makefile:177: sub-make] Error 2 Exit code: 2 So the problem here is that CONFIG_DM_DEVICE_REMOVE can be defined without CONFIG_DEVRES being defined. Is there a way to make DM_DEVICE_REMOVE dependant on DEVRES or do I need to add "&& CONFIG_IS_ENABLED(DEVRES)" everywhere that I find "CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)" ? The test failure can be "fixed" using this diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index ec912cf0ec8..69c97921744 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -105,6 +105,7 @@ CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y +CONFIG_SPL_DEVRES=y # CONFIG_SPL_SIMPLE_BUS is not set CONFIG_ADC=y CONFIG_ADC_SANDBOX=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 1687ccf4530..2fcda46dfd1 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -107,6 +107,7 @@ CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y +CONFIG_SPL_DEVRES=y # CONFIG_SPL_SIMPLE_BUS is not set CONFIG_ADC=y CONFIG_ADC_SANDBOX=y But is that the right way based on the questions above ? Thanks Angus Regards, Simon
Re: [RFC] serial: mxc: get the clock frequency from the used clock for the device
On 2022-03-18 12:06, Heiko Thiery wrote:
Hi Angus,
Am Do., 17. März 2022 um 14:19 Uhr schrieb Angus Ainslie
:
Hi Heiko,
On 2022-03-17 05:41, Heiko Thiery wrote:
> With the clock driver enabled for the imx8mq, it was noticed that the
> frequency used to calculate the baud rate is always taken from the root
> clock of UART1. This can cause problems if UART1 is not used as console
> and the settings are different from UART1. The result is that the
> console
> output is garbage. To do this correctly the UART frequency is taken
> from
> the used device. For the implementations that don't have the igp clock
> frequency written or can't return it the old way is tried.
>
> Signed-off-by: Heiko Thiery
> ---
> drivers/serial/serial_mxc.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> index e4970a169b..6fdb2b2397 100644
> --- a/drivers/serial/serial_mxc.c
> +++ b/drivers/serial/serial_mxc.c
> @@ -3,6 +3,7 @@
> * (c) 2007 Sascha Hauer
> */
>
> +#include
> #include
> #include
> #include
> @@ -266,9 +267,19 @@ __weak struct serial_device
> *default_serial_console(void)
> int mxc_serial_setbrg(struct udevice *dev, int baudrate)
> {
> struct mxc_serial_plat *plat = dev_get_plat(dev);
> - u32 clk = imx_get_uartclk();
> + u32 rate = 0;
> +
> + if (IS_ENABLED(CONFIG_CLK)) {
> + struct clk clk;
> + if(!clk_get_by_name(dev, "ipg", ))
> + rate = clk_get_rate();
Is the "ipg" clock the correct name for all of the imx DM boards ?
I checked the dtsi files for all the boards that use the compatible
strings from the serial_mxc and see that there are always 2 clocks:
'ipg' and 'per'.
The imx8 dtsi files describe ipg and per always the same clock.
The imx7 dtsi files descibe ipg and per always the same clock.
The imx6 dtsi files describe ipg and per are 2 different clocks
The imx51 dtsi files describeipg and per are 2 different clocks
So I'm not sure if the ipg clock is the right one for the boards that
has different clock for ipg and per.
So I only looked at imx6qdl.dtsi where the clocks are different
clocks = < IMX6QDL_CLK_UART_IPG>,
< IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
And from that file it looks like the per clock would be the correct one.
Should the clock be looked up by id instead of by name and then have a
different code path for each imx board type ?
> + }
> +
> + /* as fallback we try to get the clk rate that way */
> + if (rate == 0)
> + rate = imx_get_uartclk();
Would it be better to re-write imx_get_uartclk so that both the
getting
and setting of clocks was correct ?
I do not understand what you mean with that.
There are other places in the code that imx_get_uartclk gets called. If
an index was added to imx_get_uartclk(int index) then you wouldn't need
the code above in the mxc_serial_setbrg function. That would also make
all of the places where imx_get_uartclk gets called return the correct
value.
It might make sense to create a new function imx7_get_uartclk that gets
called on newer SOCs so that the imx6 and earlier code doesn't need to
get changed.
With DM clocks enabled I don't even think it makes sense to call those
older functions.
You mean when DM clocks are available the "new" method should be used
and no fallback to the old mechanism?
For older boards it makes sense to fallback to the single clock. On
newer boards if it returned an error instead it would have been easier
for you to figure out where the serial console failed.
Angus
Angus
>
> - _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
> + _mxc_serial_setbrg(plat->reg, rate, baudrate, plat->use_dte);
>
> return 0;
> }
Re: [PATCH v2] core: devres: optionally build devres into the SPL
Hi Simon, On 2022-03-18 15:41, Simon Glass wrote: Hi Angus, On Tue, 1 Mar 2022 at 07:58, Simon Glass wrote: On Mon, 28 Feb 2022 at 13:33, Angus Ainslie wrote: > > Add a CONFIG_SPL_DEVRES option > > Signed-off-by: Angus Ainslie > --- > > Changes since v1: > > Instead of gaurding the source add an SPL_DEVRES option > > drivers/core/Kconfig | 13 + > drivers/core/Makefile | 2 +- > 2 files changed, 14 insertions(+), 1 deletion(-) Unfortunately this break the tests, e.g. building sandbox_spl - can you please take a look? sandbox_spl: +make O=build-sandbox_spl -s sandbox_spl_defconfig +make O=build-sandbox_spl -s -j4 /usr/bin/ld: /tmp/ccsYY64W.ltrans0.ltrans.o: in function `device_unbind': build-sandbox_spl/spl/../../drivers/core/device-remove.c:120: undefined reference to `devres_release_all' /usr/bin/ld: /tmp/ccsYY64W.ltrans0.ltrans.o: in function `device_free': build-sandbox_spl/spl/../../drivers/core/device-remove.c:157: undefined reference to `devres_release_probe' collect2: error: ld returned 1 exit status make[3]: *** [../scripts/Makefile.spl:509: spl/u-boot-spl] Error 1 make[2]: *** [Makefile:2094: spl/u-boot-spl] Error 2 make[1]: *** [Makefile:177: sub-make] Error 2 Exit code: 2 So the problem here is that CONFIG_DM_DEVICE_REMOVE can be defined without CONFIG_DEVRES being defined. Is there a way to make DM_DEVICE_REMOVE dependant on DEVRES or do I need to add "&& CONFIG_IS_ENABLED(DEVRES)" everywhere that I find "CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)" ? Thanks Angus Regards, Simon
Re: [RFC] serial: mxc: get the clock frequency from the used clock for the device
Hi Heiko,
On 2022-03-17 05:41, Heiko Thiery wrote:
With the clock driver enabled for the imx8mq, it was noticed that the
frequency used to calculate the baud rate is always taken from the root
clock of UART1. This can cause problems if UART1 is not used as console
and the settings are different from UART1. The result is that the
console
output is garbage. To do this correctly the UART frequency is taken
from
the used device. For the implementations that don't have the igp clock
frequency written or can't return it the old way is tried.
Signed-off-by: Heiko Thiery
---
drivers/serial/serial_mxc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index e4970a169b..6fdb2b2397 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,6 +3,7 @@
* (c) 2007 Sascha Hauer
*/
+#include
#include
#include
#include
@@ -266,9 +267,19 @@ __weak struct serial_device
*default_serial_console(void)
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
struct mxc_serial_plat *plat = dev_get_plat(dev);
- u32 clk = imx_get_uartclk();
+ u32 rate = 0;
+
+ if (IS_ENABLED(CONFIG_CLK)) {
+ struct clk clk;
+ if(!clk_get_by_name(dev, "ipg", ))
+ rate = clk_get_rate();
Is the "ipg" clock the correct name for all of the imx DM boards ?
+ }
+
+ /* as fallback we try to get the clk rate that way */
+ if (rate == 0)
+ rate = imx_get_uartclk();
Would it be better to re-write imx_get_uartclk so that both the getting
and setting of clocks was correct ?
With DM clocks enabled I don't even think it makes sense to call those
older functions.
Angus
- _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
+ _mxc_serial_setbrg(plat->reg, rate, baudrate, plat->use_dte);
return 0;
}
Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
Hi Heiko, On 2022-03-16 08:55, Heiko Thiery wrote: Hi Angus, [snip] > > But then something went wrong when probing uart3 ... the baudrate > > switched for the uart2 (console) and the serial output became broken. > > Later when the kernel starts the output becomes correct again. So the > > kernel seems to configure it correctly. > > > > see here: https://pastebin.com/raw/qXVShb3Q > > > > When I remove the "assigned-clock-parents = < > > IMX8MQ_SYS1_PLL_80M>;" for uart3 the output of uart2 (console) keeps > > ok. > > If that "fixes" it then it means that the parent IMX8MQ_SYS1_PLL_80M > clock rate is getting changed by the uart3 stanza. > > Are you using the mainline devicetree file for your board ? If not could > you provide a link ? I use the mainline u-boot/linux one. We (thanks to Michael) found the issue. For the imx8mq the imx_get_uartclk() returns always the values for UART1_CLK_ROOT [1]. This is wrong. Here we have to get the value dependent on the used UART. [1] https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-imx/imx8m/clock_imx8mq.c#L381 Yeah that driver could do with an overhaul as it also does that for the ECSPI clocks which can also break things. Angus
Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-16 07:02, Heiko Thiery wrote: Hi Angus, [snip] > > Meanwhile I figured out what the problem is with the 'No serial driver > found'. In the used dtb there are 'assigned-clocks' and > 'assigned-clock-parents' set in the uart nodes. When removing this the > serial will work. I have to admit that I do not know why this is set > that way. I can only imagine that this was taken from the uboot-imx > tree. > > --- > assigned-clocks = < IMX8MQ_CLK_UART1>; > assigned-clock-parents = < IMX8MQ_SYS1_PLL_80M>; > --- > Does that solve the reboot ? Yes, when I remove these assigned-clocks from my dtb the issue is solved and the board finds the serial driver and starts correctly. > see also here: > https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts#L315 If that works for Linux it should also work for u-boot. It may be that the SYS1_PLL_80M isn't set correctly or that the CLK_UART1 mux isn't correctly setup. If you enable DEBUG in clk-uclass I might be able to figure out were the problem is. The problem is that the IMX8MQ_CLK_UART1 is not found and that is the reason that the probe fails. I tried to add the missing clocks to how it is done in the kernel. see here: https://pastebin.com/raw/iYYMHEdy Looking at that you shouldn't need + clk_dm(IMX8MQ_CLK_25M, clk_register_fixed_rate(NULL, "clock-osc-25m", 2500)); + clk_dm(IMX8MQ_CLK_25M, clk_register_fixed_rate(NULL, "clock-osc-27m", 2700)); Those get correctly probed by the clock-controller. The rest of it looks OK and could be a follow on patch to the clock driver, But then something went wrong when probing uart3 ... the baudrate switched for the uart2 (console) and the serial output became broken. Later when the kernel starts the output becomes correct again. So the kernel seems to configure it correctly. see here: https://pastebin.com/raw/qXVShb3Q When I remove the "assigned-clock-parents = < IMX8MQ_SYS1_PLL_80M>;" for uart3 the output of uart2 (console) keeps ok. If that "fixes" it then it means that the parent IMX8MQ_SYS1_PLL_80M clock rate is getting changed by the uart3 stanza. Are you using the mainline devicetree file for your board ? If not could you provide a link ?
Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-16 05:26, Heiko Thiery wrote: Hi, Am Mi., 16. März 2022 um 08:14 Uhr schrieb Heiko Thiery : Hi Angus, Am Di., 15. März 2022 um 16:46 Uhr schrieb Angus Ainslie : > > Hi Heiko, > > On 2022-03-15 08:35, Heiko Thiery wrote: > > Hi Angus and all, > > > > > Am Di., 15. März 2022 um 14:09 Uhr schrieb Angus Ainslie : >> >> This is a DM clock driver based off the imx8mm u-boot driver and the linux >> kernel driver. >> >> All of the PLLs and clocks are initialized so the subsystems below are >> functional and tested. >> >> 1) USB host and peripheral >> 2) ECSPI >> 3) UART >> 4) I2C all busses >> 5) USDHC for eMMC support >> 6) USB storage >> 7) GPIO >> 8) DRAM >> >> > Snip > > > when adding this patch and enabling CLK_IMX8MQ I see the following on my board .. Any idea what I missed here? > > --- >8 --- > U-Boot SPL 2022.04-rc4-8-g390d9bf9a1 (Mar 15 2022 - 16:26:59 +0100) > Trying to boot from SD card > > > U-Boot 2022.04-rc4-8-g390d9bf9a1 (Mar 15 2022 - 16:26:59 +0100) > > CPU: Freescale i.MX8MQ rev2.1 at 800 MHz > Reset cause: POR > Model: Kontron pITX-imx8m > DRAM: alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > alloc space exhausted > 4 GiB > > My guess is that there was static code that was setting up the DRAM pll that isn't get executed now that there's a DM clock driver. > > I'd try enabling DEBUG in the clk-uclass and clk-composite drivers. > > Also look at what DRAM initialization code is not being run now. Our board doesn't have an DRAM specific initialization so there could be a bug in the DRAM setup. The problem was the MALLOC_F_LEN value. Increasing that the "alloc space exhausted" is gone. But with the enabled DM_SERIAL the problem of "No serial driver found" is still there and the board reboots. You said you have DM_SERIAL enabled and it works? Meanwhile I figured out what the problem is with the 'No serial driver found'. In the used dtb there are 'assigned-clocks' and 'assigned-clock-parents' set in the uart nodes. When removing this the serial will work. I have to admit that I do not know why this is set that way. I can only imagine that this was taken from the uboot-imx tree. --- assigned-clocks = < IMX8MQ_CLK_UART1>; assigned-clock-parents = < IMX8MQ_SYS1_PLL_80M>; --- Does that solve the reboot ? see also here: https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts#L315 If that works for Linux it should also work for u-boot. It may be that the SYS1_PLL_80M isn't set correctly or that the CLK_UART1 mux isn't correctly setup. If you enable DEBUG in clk-uclass I might be able to figure out were the problem is.
Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-15 08:46, Angus Ainslie wrote: Hi Heiko, On 2022-03-15 08:35, Heiko Thiery wrote: Hi Angus and all, Am Di., 15. März 2022 um 14:09 Uhr schrieb Angus Ainslie : This is a DM clock driver based off the imx8mm u-boot driver and the linux kernel driver. All of the PLLs and clocks are initialized so the subsystems below are functional and tested. 1) USB host and peripheral 2) ECSPI 3) UART 4) I2C all busses 5) USDHC for eMMC support 6) USB storage 7) GPIO 8) DRAM Snip when adding this patch and enabling CLK_IMX8MQ I see the following on my board .. Any idea what I missed here? --- >8 --- U-Boot SPL 2022.04-rc4-8-g390d9bf9a1 (Mar 15 2022 - 16:26:59 +0100) Trying to boot from SD card U-Boot 2022.04-rc4-8-g390d9bf9a1 (Mar 15 2022 - 16:26:59 +0100) CPU: Freescale i.MX8MQ rev2.1 at 800 MHz Reset cause: POR Model: Kontron pITX-imx8m DRAM: alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted 4 GiB My guess is that there was static code that was setting up the DRAM pll that isn't get executed now that there's a DM clock driver. I'd try enabling DEBUG in the clk-uclass and clk-composite drivers. Also look at what DRAM initialization code is not being run now. Our board doesn't have an DRAM specific initialization so there could be a bug in the DRAM setup. clk_register: failed to get device (parent of ckil) clk_register: failed to get device (parent of sys1_pll) clk_register: failed to get device (parent of sys2_pll) clk_register: failed to get device (parent of sys3_pll) These are warnings and shouldn't affect the functioning of the driver. No serial driver found Are you using the DM serial driver ? Again this is not something that is running on our board. But I can try enabling it. With DM_SERIAL enabled and SPL_DM_SERIAL disabled U-Boot SPL 2022.04-rc3-00076-gb363332dc70-dirty (Mar 15 2022 - 09:09:24 -0700) [0/1906] Initializing pinmux Initializing ECSPI Initializing DRAM USB Boot Trying to boot from USB SDP board_usb_init : index 0 type 1 SDP: initialize... SDP: handle requests... Downloading file of size 868420 to 0x4040... done Jumping to header at 0x4040 Header Tag is not an IMX image Found header at 0x40406e00 board_usb_cleanup : 0 Status: -108 U-Boot 2022.04-rc3-00076-gb363332dc70-dirty (Mar 15 2022 - 09:09:24 -0700) CPU: Freescale i.MX8MQ rev2.1 1500 MHz (running at 1000 MHz) CPU: Commercial temperature grade (0C to 95C) at 60C Reset cause: POR Model: Purism Librem 5r4 DRAM: 3 GiB Enabling regulator-hub clk_register: failed to get device (parent of ckil) clk_register: failed to get device (parent of sys1_pll) clk_register: failed to get device (parent of sys2_pll) clk_register: failed to get device (parent of sys3_pll) tps65982 boot successful Core: 178 devices, 23 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial BuildInfo: - ATF 1fd3ff8 Board name: librem5 Board rev: 4 USB Boot vol_down_key_pressed : 1 Net: No ethernet found. Hit any key to stop autoboot: 0 Thanks Angus resetting ... --- >8 --- -- Heiko
Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
Hi Heiko, On 2022-03-15 08:35, Heiko Thiery wrote: Hi Angus and all, Am Di., 15. März 2022 um 14:09 Uhr schrieb Angus Ainslie : This is a DM clock driver based off the imx8mm u-boot driver and the linux kernel driver. All of the PLLs and clocks are initialized so the subsystems below are functional and tested. 1) USB host and peripheral 2) ECSPI 3) UART 4) I2C all busses 5) USDHC for eMMC support 6) USB storage 7) GPIO 8) DRAM Snip when adding this patch and enabling CLK_IMX8MQ I see the following on my board .. Any idea what I missed here? --- >8 --- U-Boot SPL 2022.04-rc4-8-g390d9bf9a1 (Mar 15 2022 - 16:26:59 +0100) Trying to boot from SD card U-Boot 2022.04-rc4-8-g390d9bf9a1 (Mar 15 2022 - 16:26:59 +0100) CPU: Freescale i.MX8MQ rev2.1 at 800 MHz Reset cause: POR Model: Kontron pITX-imx8m DRAM: alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted alloc space exhausted 4 GiB My guess is that there was static code that was setting up the DRAM pll that isn't get executed now that there's a DM clock driver. I'd try enabling DEBUG in the clk-uclass and clk-composite drivers. Also look at what DRAM initialization code is not being run now. Our board doesn't have an DRAM specific initialization so there could be a bug in the DRAM setup. clk_register: failed to get device (parent of ckil) clk_register: failed to get device (parent of sys1_pll) clk_register: failed to get device (parent of sys2_pll) clk_register: failed to get device (parent of sys3_pll) These are warnings and shouldn't affect the functioning of the driver. No serial driver found Are you using the DM serial driver ? Again this is not something that is running on our board. But I can try enabling it. Thanks Angus resetting ... --- >8 --- -- Heiko
[PATCH v4 4/4] clk: imx8m: remove code duplication
All of the imx8m[nmpq] use the same clk_ops functions so move them
to a common file.
Signed-off-by: Angus Ainslie
Reviewed-by: Marek Vasut
---
drivers/clk/imx/Makefile | 8 +--
drivers/clk/imx/clk-imx8m.c | 108 +++
drivers/clk/imx/clk-imx8m.h | 12
drivers/clk/imx/clk-imx8mm.c | 89 +
drivers/clk/imx/clk-imx8mn.c | 89 +
drivers/clk/imx/clk-imx8mp.c | 91 +
drivers/clk/imx/clk-imx8mq.c | 91 +
7 files changed, 132 insertions(+), 356 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8m.c
create mode 100644 drivers/clk/imx/clk-imx8m.h
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c5766901f2b..09030f1ded2 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -11,13 +11,13 @@ obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8m.c b/drivers/clk/imx/clk-imx8m.c
new file mode 100644
index 000..d3e9f8aaee0
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8m.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Copyright 2022 Purism SPC
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-imx8m.h"
+
+ulong imx8m_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_get_rate);
+
+ulong imx8m_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_set_rate);
+
+static int __imx8m_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+int imx8m_clk_disable(struct clk *clk)
+{
+ return __imx8m_clk_enable(clk, 0);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_disable);
+
+int imx8m_clk_enable(struct clk *clk)
+{
+ return __imx8m_clk_enable(clk, 1);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_enable);
+
+int imx8m_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_set_parent(c, cp);
+ c->dev->parent = cp->dev;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_set_parent);
+
+struct clk_ops imx8m_clk_ops = {
+ .set_rate = imx8m_clk_set_rate,
+ .get_rate = imx8m_clk_get_rate,
+ .enable = imx8m_clk_enable,
+ .disable = imx8m_clk_disable,
+ .set_parent = imx8m_clk_set_parent,
+};
+EXPORT_SYMBOL_GPL(imx8m_clk_ops);
diff --git a/drivers/clk/imx/clk-imx8m.h b/drivers/clk/imx/clk-imx8m.h
new file mode 100644
index 000..7c0892e148d
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8m.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Purism SPC
+ */
+
+extern ulong imx8m_clk_get_rate(struct clk *clk);
+extern ulong imx8m_clk_set_rate(struct clk *clk, unsigned long rate);
+extern int imx8m_clk_disable(struct clk *clk);
+extern int imx8m_clk_enable(struct clk *clk);
+extern int imx8m_clk_set_parent(struct clk *clk, struct clk *parent);
+
+extern struct clk_ops imx8
[PATCH v4 3/4] clk: imx8m: reduce rate table duplication
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
place")
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/clk-imx8mm.c | 60 +++-
drivers/clk/imx/clk-imx8mn.c | 60 +++-
drivers/clk/imx/clk-imx8mp.c | 65 ++-
drivers/clk/imx/clk-imx8mq.c | 59 ---
drivers/clk/imx/clk-pll14xx.c | 61
drivers/clk/imx/clk.h | 4 +++
6 files changed, 91 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 3aa8c641f9a..ab8f9b4d6b9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
- PLL_1416X_RATE(18U, 225, 3, 0),
- PLL_1416X_RATE(16U, 200, 3, 0),
- PLL_1416X_RATE(12U, 300, 3, 1),
- PLL_1416X_RATE(10U, 250, 3, 1),
- PLL_1416X_RATE(8U, 200, 3, 1),
- PLL_1416X_RATE(75000U, 250, 2, 2),
- PLL_1416X_RATE(7U, 350, 3, 2),
- PLL_1416X_RATE(6U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
- PLL_1443X_RATE(65000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mm_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
@@ -250,19 +200,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, _dram_pll));
+ base + 0x50, _1443x_dram_pll));
clk_dm(IMX8MM_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, _arm_pll));
+ base + 0x84, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, _sys_pll));
+ base + 0x94, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, _sys_pll));
+ base + 0x104, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, _sys_pll));
+ base + 0x114, _1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index e398d7de02a..c3d60ad057c 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv
[PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/Kconfig | 16 +
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 575 +++
3 files changed, 593 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..06d8c1a5dd3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,22 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..c5766901f2b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000..0aea417a29b
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mq_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *audio_pll1_bypass_
[PATCH v4 1/4] dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie
Reviewed-by: Marek Vasut
---
include/dt-bindings/clock/imx8mq-clock.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h
b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8..82e907ce7bd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
#define IMX8MQ_CLK_A53_CORE289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
+#define IMX8MQ_CLK_MON_SEL 301
+#define IMX8MQ_CLK_MON_CLK2_OUT302
+
+#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.25.1
[PATCH v4 0/4] Add a clock driver for the imx8mq
This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel Angus Ainslie (4): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication clk: imx8m: remove code duplication drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 8 +- drivers/clk/imx/clk-imx8m.c | 108 ++ drivers/clk/imx/clk-imx8m.h | 12 + drivers/clk/imx/clk-imx8mm.c | 149 +--- drivers/clk/imx/clk-imx8mn.c | 149 +--- drivers/clk/imx/clk-imx8mp.c | 156 +--- drivers/clk/imx/clk-imx8mq.c | 441 +++ drivers/clk/imx/clk-pll14xx.c| 61 drivers/clk/imx/clk.h| 4 + include/dt-bindings/clock/imx8mq-clock.h | 16 +- 11 files changed, 688 insertions(+), 432 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8m.c create mode 100644 drivers/clk/imx/clk-imx8m.h create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1
Re: [PATCH v3 3/4] clk: imx8m: reduce rate table duplication
On 2022-03-14 11:57, Marek Vasut wrote:
On 3/14/22 19:22, Angus Ainslie wrote:
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to
common place")
Signed-off-by: Angus Ainslie
Thanks
[...]
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, _sys_pll));
+ base + 0x114, _1416x_pll));
imx8m_pll1416x , since those samsung PLL14xxx are new on MX8M I think.
For the kernel driver it uses the generic ones ?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/imx/clk-imx8mm.c#n346
[...]
diff --git a/drivers/clk/imx/clk-pll14xx.c
b/drivers/clk/imx/clk-pll14xx.c
index b0ccb6c8eda..a60cf9bdcb0 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -52,6 +52,50 @@ struct clk_pll14xx {
#define to_clk_pll14xx(_clk) container_of(_clk, struct
clk_pll14xx, clk)
+static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(15U, 375, 3, 1),
+ PLL_1416X_RATE(14U, 350, 3, 1),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
+ PLL_1443X_RATE(103950U, 173, 2, 1, 16384),
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(51975U, 173, 2, 2, 16384),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+struct imx_pll14xx_clk imx_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
+};
+EXPORT_SYMBOL_GPL(imx_1443x_pll);
+
+struct imx_pll14xx_clk imx_1443x_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
+ .flags = CLK_GET_RATE_NOCACHE,
+};
+EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
+
+struct imx_pll14xx_clk imx_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
+};
+EXPORT_SYMBOL_GPL(imx_1416x_pll);
+
static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
struct clk_pll14xx *pll, unsigned long rate)
{
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 60f287046b9..ac7e50fbe97 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -41,6 +41,27 @@ struct imx_pll14xx_clk {
int flags;
};
+extern struct imx_pll14xx_clk imx_1416x_pll;
+extern struct imx_pll14xx_clk imx_1443x_pll;
+extern struct imx_pll14xx_clk imx_1443x_dram_pll;
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
Should these macros be in drivers/clk/imx/clk-pll14xx.c ?
Yeah I guess they aren't used anywhere else.
[PATCH v3 4/4] clk: imx8m: remove code duplication
All of the imx8m[nmpq] use the same clk_ops functions so move them
to a common file.
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/Makefile | 8 +--
drivers/clk/imx/clk-imx8m.c | 108 +++
drivers/clk/imx/clk-imx8m.h | 12
drivers/clk/imx/clk-imx8mm.c | 89 +
drivers/clk/imx/clk-imx8mn.c | 89 +
drivers/clk/imx/clk-imx8mp.c | 91 +
drivers/clk/imx/clk-imx8mq.c | 91 +
7 files changed, 132 insertions(+), 356 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8m.c
create mode 100644 drivers/clk/imx/clk-imx8m.h
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c5766901f2b..09030f1ded2 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -11,13 +11,13 @@ obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
- clk-composite-8m.o
+ clk-composite-8m.o clk-imx8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8m.c b/drivers/clk/imx/clk-imx8m.c
new file mode 100644
index 000..d3e9f8aaee0
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8m.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Copyright 2022 Purism SPC
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk-imx8m.h"
+
+ulong imx8m_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_get_rate);
+
+ulong imx8m_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_set_rate);
+
+static int __imx8m_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+int imx8m_clk_disable(struct clk *clk)
+{
+ return __imx8m_clk_enable(clk, 0);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_disable);
+
+int imx8m_clk_enable(struct clk *clk)
+{
+ return __imx8m_clk_enable(clk, 1);
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_enable);
+
+int imx8m_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_set_parent(c, cp);
+ c->dev->parent = cp->dev;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(imx8m_clk_set_parent);
+
+struct clk_ops imx8m_clk_ops = {
+ .set_rate = imx8m_clk_set_rate,
+ .get_rate = imx8m_clk_get_rate,
+ .enable = imx8m_clk_enable,
+ .disable = imx8m_clk_disable,
+ .set_parent = imx8m_clk_set_parent,
+};
+EXPORT_SYMBOL_GPL(imx8m_clk_ops);
diff --git a/drivers/clk/imx/clk-imx8m.h b/drivers/clk/imx/clk-imx8m.h
new file mode 100644
index 000..7c0892e148d
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8m.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Purism SPC
+ */
+
+extern ulong imx8m_clk_get_rate(struct clk *clk);
+extern ulong imx8m_clk_set_rate(struct clk *clk, unsigned long rate);
+extern int imx8m_clk_disable(struct clk *clk);
+extern int imx8m_clk_enable(struct clk *clk);
+extern int imx8m_clk_set_parent(struct clk *clk, struct clk *parent);
+
+extern struct clk_ops imx8m_clk_ops;
diff --git a/d
[PATCH v3 2/4] clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock drvier based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/Kconfig | 16 +
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 575 +++
3 files changed, 593 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..06d8c1a5dd3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,22 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..c5766901f2b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000..0aea417a29b
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mq_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *audio_pll1_bypass_
[PATCH v3 3/4] clk: imx8m: reduce rate table duplication
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
place")
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/clk-imx8mm.c | 60 +++-
drivers/clk/imx/clk-imx8mn.c | 60 +++-
drivers/clk/imx/clk-imx8mp.c | 65 ++-
drivers/clk/imx/clk-imx8mq.c | 59 ---
drivers/clk/imx/clk-pll14xx.c | 44
drivers/clk/imx/clk.h | 21 +++
6 files changed, 91 insertions(+), 218 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 3aa8c641f9a..ab8f9b4d6b9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
-static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
- PLL_1416X_RATE(18U, 225, 3, 0),
- PLL_1416X_RATE(16U, 200, 3, 0),
- PLL_1416X_RATE(12U, 300, 3, 1),
- PLL_1416X_RATE(10U, 250, 3, 1),
- PLL_1416X_RATE(8U, 200, 3, 1),
- PLL_1416X_RATE(75000U, 250, 2, 2),
- PLL_1416X_RATE(7U, 350, 3, 2),
- PLL_1416X_RATE(6U, 300, 3, 2),
-};
-
-static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
- PLL_1443X_RATE(65000U, 325, 3, 2, 0),
-};
-
-static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
- .type = PLL_1443X,
- .rate_table = imx8mm_drampll_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
-static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
- .type = PLL_1416X,
- .rate_table = imx8mm_pll1416x_tbl,
- .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
-};
-
static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
@@ -250,19 +200,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_DRAM_PLL,
imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
- base + 0x50, _dram_pll));
+ base + 0x50, _1443x_dram_pll));
clk_dm(IMX8MM_ARM_PLL,
imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
- base + 0x84, _arm_pll));
+ base + 0x84, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL1,
imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
- base + 0x94, _sys_pll));
+ base + 0x94, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL2,
imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
- base + 0x104, _sys_pll));
+ base + 0x104, _1416x_pll));
clk_dm(IMX8MM_SYS_PLL3,
imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
- base + 0x114, _sys_pll));
+ base + 0x114, _1416x_pll));
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index e398d7de02a..c3d60ad057c 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -15,56 +15,6 @@
#include "clk.h"
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv
[PATCH v3 1/4] dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie
---
include/dt-bindings/clock/imx8mq-clock.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h
b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8..82e907ce7bd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
#define IMX8MQ_CLK_A53_CORE289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
+#define IMX8MQ_CLK_MON_SEL 301
+#define IMX8MQ_CLK_MON_CLK2_OUT302
+
+#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.25.1
[PATCH v3 0/4] Add a clock driver for the imx8mq
This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel Angus Ainslie (4): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication clk: imx8m: remove code duplication drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 8 +- drivers/clk/imx/clk-imx8m.c | 108 ++ drivers/clk/imx/clk-imx8m.h | 12 + drivers/clk/imx/clk-imx8mm.c | 149 +--- drivers/clk/imx/clk-imx8mn.c | 149 +--- drivers/clk/imx/clk-imx8mp.c | 156 +--- drivers/clk/imx/clk-imx8mq.c | 441 +++ drivers/clk/imx/clk-pll14xx.c| 44 +++ drivers/clk/imx/clk.h| 21 ++ include/dt-bindings/clock/imx8mq-clock.h | 16 +- 11 files changed, 688 insertions(+), 432 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8m.c create mode 100644 drivers/clk/imx/clk-imx8m.h create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1
Re: [PATCH v2 2/2] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-11 11:19, Marek Vasut wrote:
On 3/11/22 19:41, Angus Ainslie wrote:
On 2022-03-11 10:05, Marek Vasut wrote:
On 3/11/22 18:02, Angus Ainslie wrote:
On 2022-03-11 08:57, Marek Vasut wrote:
On 3/11/22 17:35, Angus Ainslie wrote:
All of the PLLs and clocks are initialized so the subsystems below
are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
The PLL rate tables are from the kernel
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=43cdaa1567ad3931fbde438853947d45238cc040
That patch is three years old.
That patch is for MX8M Mini clock, not for MX8M(Q).
You can use the abbreviated commit ID instead:
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure
to common place")
But that seems to be the wrong commit.
That's the commit where the imx8m PLL frequency table is moved to a
common file for use by all of the imx8m variants. The imx8mq linux
driver does not even use the frequency tables so there is not a
specific commit for it.
Isn't large part of this driver coming from these tables ?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/log/drivers/clk/imx/clk-imx8mq.c
When I said tables I was referring to the PLL frequency tables.
Ahh, hmmm, I see that we now have three copies of those PLL tables in
each MX8M{M,N,P} driver and Linux instead has this in common code. Can
you deduplicate the PLL tables before we add fourth copy ?
Ok I can do that for the imx8m* clock drivers.
The driver is modelled after the u-boot imx8mm u-boot driver with
register and mux updates from the imx8mq reference manual. Very little
comes from the imx8mq kernel driver. Mainly I just verified mux naming
and register offsets against that driver.
Would it make sense to pick the Linux kernel tables instead then,
instead of hand-writing them from scratch ? That seems error prone.
It's a good thing I didn't just copy the kernel drivers because I found
an error there. After this driver accepted there will very few if any
updates to the mux tables as I think most if not all of the clocks
you'll need in u-boot are defined. If there are any future updates those
could be cut and pasted.
Re: [PATCH v2 2/2] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-11 10:05, Marek Vasut wrote:
On 3/11/22 18:02, Angus Ainslie wrote:
On 2022-03-11 08:57, Marek Vasut wrote:
On 3/11/22 17:35, Angus Ainslie wrote:
All of the PLLs and clocks are initialized so the subsystems below
are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
The PLL rate tables are from the kernel
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=43cdaa1567ad3931fbde438853947d45238cc040
That patch is three years old.
That patch is for MX8M Mini clock, not for MX8M(Q).
You can use the abbreviated commit ID instead:
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to
common place")
But that seems to be the wrong commit.
That's the commit where the imx8m PLL frequency table is moved to a
common file for use by all of the imx8m variants. The imx8mq linux
driver does not even use the frequency tables so there is not a
specific commit for it.
Isn't large part of this driver coming from these tables ?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/log/drivers/clk/imx/clk-imx8mq.c
When I said tables I was referring to the PLL frequency tables.
The driver is modelled after the u-boot imx8mm u-boot driver with
register and mux updates from the imx8mq reference manual. Very little
comes from the imx8mq kernel driver. Mainly I just verified mux naming
and register offsets against that driver.
That reminds me that I need to send a kernel patch for the monitor
muxes.
[PATCH v2] board: purism: add the Purism Librem5 phone
Initial commit of Librem5 phone u-boot and SPL
Using this u-boot the phone can boot from eMMC or USB via SDP.
USB host is also active so the kernel can be loaded from USB storage
or one of the boot methods above.
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
All of the pre-requisite patches for this board are now upstream or in review.
Changes since v1:
Merged patches into a monolithic board patch
Using DM drivers for devices in u-boot
Added USB storage support for uSD rootfs
Dropped many SPL_BUILD guarded define's
Fixed documentation index
arch/arm/dts/Makefile|3 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 134 ++
arch/arm/dts/imx8mq-librem5-r4.dts | 35 +
arch/arm/dts/imx8mq-librem5.dtsi | 1255 +
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/purism/librem5/Kconfig | 15 +
board/purism/librem5/MAINTAINERS |8 +
board/purism/librem5/Makefile| 13 +
board/purism/librem5/imximage-8mq-lpddr4.cfg |8 +
board/purism/librem5/librem5.c | 483 +++
board/purism/librem5/librem5.h | 182 +++
board/purism/librem5/lpddr4_timing.c | 1324 ++
board/purism/librem5/lpddr4_timing_b0.c | 1191
board/purism/librem5/spl.c | 597
configs/librem5_defconfig| 139 ++
doc/board/index.rst |1 +
doc/board/purism/index.rst |9 +
doc/board/purism/librem5.rst | 60 +
include/configs/librem5.h| 151 ++
19 files changed, 5616 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts
create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi
create mode 100644 board/purism/librem5/Kconfig
create mode 100644 board/purism/librem5/MAINTAINERS
create mode 100644 board/purism/librem5/Makefile
create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg
create mode 100644 board/purism/librem5/librem5.c
create mode 100644 board/purism/librem5/librem5.h
create mode 100644 board/purism/librem5/lpddr4_timing.c
create mode 100644 board/purism/librem5/lpddr4_timing_b0.c
create mode 100644 board/purism/librem5/spl.c
create mode 100644 configs/librem5_defconfig
create mode 100644 doc/board/purism/index.rst
create mode 100644 doc/board/purism/librem5.rst
create mode 100644 include/configs/librem5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 960f1a9fd4d..c8d5b541109 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -926,7 +926,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
- imx8mq-kontron-pitx-imx8m.dtb
+ imx8mq-kontron-pitx-imx8m.dtb \
+ imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
new file mode 100644
index 000..e3f780ca75b
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ descript
Re: [PATCH v2 2/2] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-11 08:57, Marek Vasut wrote:
On 3/11/22 17:35, Angus Ainslie wrote:
This is a DM clock drvier based off the imx8mm u-boot driver and the
linux
kernel driver.
s@drvier@driver@
Thanks
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
The PLL rate tables are from the kernel
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=43cdaa1567ad3931fbde438853947d45238cc040
That patch is three years old.
That patch is for MX8M Mini clock, not for MX8M(Q).
You can use the abbreviated commit ID instead:
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to
common place")
But that seems to be the wrong commit.
That's the commit where the imx8m PLL frequency table is moved to a
common file for use by all of the imx8m variants. The imx8mq linux
driver does not even use the frequency tables so there is not a specific
commit for it.
[PATCH v2 2/2] clk: imx8mq: Add a clock driver for the imx8mq
This is a DM clock drvier based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
The PLL rate tables are from the kernel
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=43cdaa1567ad3931fbde438853947d45238cc040
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/Kconfig | 16 +
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 575 +++
3 files changed, 593 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..06d8c1a5dd3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,22 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..c5766901f2b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000..0aea417a29b
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+ PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+ PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+};
+
+static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mq_pll1443x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_re
[PATCH v2 0/2] Add a clock driver for the imx8mq
This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel Angus Ainslie (2): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx8mq.c | 575 +++ include/dt-bindings/clock/imx8mq-clock.h | 16 +- 4 files changed, 608 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1
[PATCH v2 1/2] dt-bindings: imx8mq-clock: add mainline definitions
Sync the clock ids with the mainline kernel Signed-off-by: Angus Ainslie --- include/dt-bindings/clock/imx8mq-clock.h | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 9b8045d75b8..82e907ce7bd 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -431,6 +431,20 @@ #define IMX8MQ_CLK_A53_CORE289 -#define IMX8MQ_CLK_END 290 +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 +#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 +#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 +#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV296 +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV297 +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV298 +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV299 +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 +#define IMX8MQ_CLK_MON_SEL 301 +#define IMX8MQ_CLK_MON_CLK2_OUT302 + +#define IMX8MQ_CLK_END 303 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- 2.25.1
Re: [PATCH] clk: imx8mq: Add a clock driver for the imx8mq
On 2022-03-11 02:18, Marek Vasut wrote:
On 3/11/22 01:53, Angus Ainslie wrote:
Based off the imx8mm u-boot driver and the linux kernel driver
What does this patch do again ? (it is impossible to tell from the
one-line commit message above unless you have it back-to-back with
Subject).
Also, if these tables come from Linux, please include the upstream
linux kernel commit ID from which these tables come from, so next time
the tables need to be synchronized from Linux to U-Boot, we could only
pick the new commits from Linux since the base commit.
Ok I'll update the description.
[...]
+static const char *imx8mq_a53_core_sels[] = {"arm_a53_div",
"arm_pll_out", };
+static const char *imx8mq_a53_sels[] = {"clock-osc-25m",
"arm_pll_out", "sys_pll2_500m",
+ "sys_pll2_1000m", "sys_pll1_800m",
"sys_pll1_400m",
+ "audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mq_ahb_sels[] = {"clock-osc-25m",
"sys_pll1_133m", "sys_pll1_800m",
+ "sys_pll1_400m", "sys_pll2_125m",
"sys_pll3_out",
+ "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_enet_axi_sels[] = {"clock-osc-25m",
"sys_pll1_266m", "sys_pll1_800m",
+"sys_pll2_250m", "sys_pll2_200m",
"audio_pll1_out",
+"video_pll1_out", "sys_pll3_out",
};
+
+#ifndef CONFIG_SPL_BUILD
You might want to invert the logic -- ifdef CONFIG_SPL_BUILD -- and
then NOT include a lot of these clock in SPL to reduce the size of the
SPL.
I don't use it in the SPL so just mirrored what was in the imx8mm
driver.
I think I prefer to just drop them and then if there is an SPL user they
can figure out where to disable SPL clocks based on the subsystems
enabled rather than the SPL_BUILD flag.
[...]
The rest looks good to me, thanks.
Thanks can I add a Reviewed-by ?
[PATCH] clk: imx8mq: Add a clock driver for the imx8mq
Based off the imx8mm u-boot driver and the linux kernel driver
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/Kconfig | 16 +
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mq.c | 593 +++
3 files changed, 611 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b..06d8c1a5dd 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -71,6 +71,22 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
+config SPL_CLK_IMX8MQ
+ bool "SPL clock support for i.MX8MQ"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MQ
+
+config CLK_IMX8MQ
+ bool "Clock support for i.MX8MQ"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MX8MQ platforms.
+
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3ae..c5766901f2 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \
+ clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 00..052af53d7b
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Purism
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static struct imx_pll14xx_clk imx8mq_arm_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mq_sys_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mq_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m",
"clock-phy-27m", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *audio_pll1_bypass_sels[] = {"audio_pll1",
"audio_pll1_ref_sel", };
+static const char *audio_pll2_bypass_sels[] = {"audio_pll2",
"audio_pll2_ref_sel", };
+static const char *video_pll1_bypass_sels[] = {"video_pll1",
"video_pll1_ref_sel", };
+
+static const char *sys1_pll_bypass_sels[] = {"sys1_pll", "sys1_pll_ref_sel", };
+static const char *sys2_pll_bypass_sels[] = {"sys2_pll", "sys2_pll_ref_sel", };
+static const char *sys3_pll_bypass_sels[] = {"
[PATCH v2] core: devres: optionally build devres into the SPL
Add a CONFIG_SPL_DEVRES option Signed-off-by: Angus Ainslie --- Changes since v1: Instead of gaurding the source add an SPL_DEVRES option drivers/core/Kconfig | 13 + drivers/core/Makefile | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 8f7703c8b5..7e666708fe 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -206,6 +206,19 @@ config DEVRES non-managed variants. For example, devres_alloc() to kzalloc(), devm_kmalloc() to kmalloc(), etc. +config SPL_DEVRES + bool "Managed device resources in the SPL" + depends on DM + help + This option enables the Managed device resources core support. + Device resources managed by the devres framework are automatically + released whether initialization fails half-way or the device gets + detached. + + If this option is disabled, devres functions fall back to + non-managed variants. For example, devres_alloc() to kzalloc(), + devm_kmalloc() to kmalloc(), etc. + config DEBUG_DEVRES bool "Managed device resources debugging functions" depends on DEVRES diff --git a/drivers/core/Makefile b/drivers/core/Makefile index 5edd4e4135..0cbc3ab217 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -4,7 +4,7 @@ obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi.o -obj-$(CONFIG_DEVRES) += devres.o +obj-$(CONFIG_$(SPL_TPL_)DEVRES) += devres.o obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS)+= simple-bus.o obj-$(CONFIG_SIMPLE_PM_BUS)+= simple-pm-bus.o -- 2.25.1
Re: [PATCH] core: devres: don't use devres code when CONFIG_DEVRES is not defined
Hi Simon, On 2022-02-19 14:12, Simon Glass wrote: On Wed, 2 Feb 2022 at 16:16, Angus Ainslie wrote: Put guards around the devres code so that it isn't compiled during the SPL. Signed-off-by: Angus Ainslie --- drivers/core/devres.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) I think the correct fix here is to change the Makefile rule for this file to use CONFIG_$(SPL_)DEVRES instead of CONFIG_DEVRES Can you try it? I think it will work that way and I did think about doing the patch that way. My concern was that it might break some boards because they are expecting DEVRES in the SPL. I can rework the patch that way but not sure how I'd test which boards needed the CONFIG_SPL_DEVRES defined. Thanks Angus Regards, Simon [..]
Re: [PATCH v2] imx8m: clock_imx8mq: Add the ecspi clocks
On 2022-02-15 08:45, Marek Vasut wrote: On 2/15/22 15:55, Angus Ainslie wrote: On 2022-02-15 00:01, Marek Vasut wrote: On 2/15/22 01:51, Angus Ainslie wrote: On 2022-02-14 16:25, Marek Vasut wrote: On 2/14/22 21:51, Angus Ainslie wrote: Enable the clocks for spi buses 1 through 3 Signed-off-by: Angus Ainslie --- Changes since v1: added MXC_CSPI_CLK to ECSPI1_CLK_ROOT mapping arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 40 ++ 2 files changed, 49 insertions(+) Shouldn't all this come from DT ? This is used in the SPL. The imx8mq also doesn't have a DM clock driver. Hmm, would it be possible to take one of the other Ms clock drivers, fork it into MQ one, and fill in the tables from Linux, thus creating the missing MQ clock driver? I've begun working on that as well. I'll send the patches once I get Linux to boot. Thanks Does it make sense to wait with this patch for after 2022.04 , when it might not be needed ? I'll let Stefano decide ... Ok, I'm not sure why it should get held back as it fixes ECSPI initialization and use in the SPL.
Re: [PATCH v2] imx8m: clock_imx8mq: Add the ecspi clocks
On 2022-02-15 00:01, Marek Vasut wrote: On 2/15/22 01:51, Angus Ainslie wrote: On 2022-02-14 16:25, Marek Vasut wrote: On 2/14/22 21:51, Angus Ainslie wrote: Enable the clocks for spi buses 1 through 3 Signed-off-by: Angus Ainslie --- Changes since v1: added MXC_CSPI_CLK to ECSPI1_CLK_ROOT mapping arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 40 ++ 2 files changed, 49 insertions(+) Shouldn't all this come from DT ? This is used in the SPL. The imx8mq also doesn't have a DM clock driver. Hmm, would it be possible to take one of the other Ms clock drivers, fork it into MQ one, and fill in the tables from Linux, thus creating the missing MQ clock driver? I've begun working on that as well. I'll send the patches once I get Linux to boot.
Re: [PATCH v2] imx8m: clock_imx8mq: Add the ecspi clocks
Hi Marek, On 2022-02-14 16:25, Marek Vasut wrote: On 2/14/22 21:51, Angus Ainslie wrote: Enable the clocks for spi buses 1 through 3 Signed-off-by: Angus Ainslie --- Changes since v1: added MXC_CSPI_CLK to ECSPI1_CLK_ROOT mapping arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 40 ++ 2 files changed, 49 insertions(+) Shouldn't all this come from DT ? This is used in the SPL. The imx8mq also doesn't have a DM clock driver. Thanks Angus
[PATCH v2] imx8m: clock_imx8mq: Add the ecspi clocks
Enable the clocks for spi buses 1 through 3
Signed-off-by: Angus Ainslie
---
Changes since v1:
added MXC_CSPI_CLK to ECSPI1_CLK_ROOT mapping
arch/arm/include/asm/arch-imx8m/imx-regs.h | 9 +
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 40 ++
2 files changed, 49 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1..8cb499d3a3 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -94,6 +94,15 @@
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
+#define IMX_CSPI1_BASE 0x3082
+#define IMX_CSPI2_BASE 0x3083
+#define IMX_CSPI3_BASE 0x3084
+
+#define MXC_SPI_BASE_ADDRESSES \
+ IMX_CSPI1_BASE, \
+ IMX_CSPI2_BASE, \
+ IMX_CSPI3_BASE
+
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 60e2218a3c..ef0249cd58 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -359,6 +359,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
clock_get_target_val(IPG_CLK_ROOT, );
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
case MXC_ESDHC_CLK:
return get_root_clk(USDHC1_CLK_ROOT);
case MXC_ESDHC2_CLK:
@@ -505,6 +507,31 @@ int set_clk_qspi(void)
return 0;
}
+int set_clk_ecspi(int sel)
+{
+ int clk = ECSPI1_CLK_ROOT;
+
+ switch (sel) {
+ case 1:
+ clk = ECSPI1_CLK_ROOT;
+ break;
+ case 2:
+ clk = ECSPI2_CLK_ROOT;
+ break;
+ case 3:
+ clk = ECSPI3_CLK_ROOT;
+ break;
+ }
+
+ clock_enable(clk, 0);
+ /*
+* TODO: configure clock
+*/
+ clock_enable(clk, 1);
+
+ return 0;
+}
+
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type)
{
@@ -772,6 +799,19 @@ int clock_init(void)
clock_enable(CCGR_TSENSOR, 1);
clock_enable(CCGR_OCOTP, 1);
+ /*
+* set ecspi roots
+*/
+ clock_enable(CCGR_ECSPI1, 0);
+ clock_enable(CCGR_ECSPI2, 0);
+ clock_enable(CCGR_ECSPI3, 0);
+ clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_ECSPI1, 1);
+ clock_enable(CCGR_ECSPI2, 1);
+ clock_enable(CCGR_ECSPI3, 1);
+
/* config GIC ROOT to sys_pll2_200m */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT,
--
2.25.1
[PATCH] phy: phy-uclass: check the parents for phys
The port/hub leaf nodes don't contain the phy definitions in some dts
files so check the parents.
Signed-off-by: Angus Ainslie
---
drivers/phy/phy-uclass.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index 49e2ec25c2..8b84da3ce0 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -354,23 +354,31 @@ int generic_phy_configure(struct phy *phy, void *params)
int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk)
{
int i, ret, count;
+ struct udevice *phydev = dev;
bulk->count = 0;
/* Return if no phy declared */
- if (!dev_read_prop(dev, "phys", NULL))
- return 0;
+ if (!dev_read_prop(dev, "phys", NULL)) {
+ phydev = dev->parent;
+ if (!dev_read_prop(phydev, "phys", NULL)) {
+ pr_err("%s : no phys property\n", __func__);
+ return 0;
+ }
+ }
- count = dev_count_phandle_with_args(dev, "phys", "#phy-cells", 0);
- if (count < 1)
+ count = dev_count_phandle_with_args(phydev, "phys", "#phy-cells", 0);
+ if (count < 1) {
+ pr_err("%s : no phys found %d\n", __func__, count);
return count;
+ }
- bulk->phys = devm_kcalloc(dev, count, sizeof(struct phy), GFP_KERNEL);
+ bulk->phys = devm_kcalloc(phydev, count, sizeof(struct phy),
GFP_KERNEL);
if (!bulk->phys)
return -ENOMEM;
for (i = 0; i < count; i++) {
- ret = generic_phy_get_by_index(dev, i, >phys[i]);
+ ret = generic_phy_get_by_index(phydev, i, >phys[i]);
if (ret) {
pr_err("Failed to get PHY%d for %s\n", i, dev->name);
return ret;
--
2.25.1
[PATCH] core: devres: don't use devres code when CONFIG_DEVRES is not defined
Put guards around the devres code so that it isn't compiled during the SPL.
Signed-off-by: Angus Ainslie
---
drivers/core/devres.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/core/devres.c b/drivers/core/devres.c
index 313ddc7089..92a237c64c 100644
--- a/drivers/core/devres.c
+++ b/drivers/core/devres.c
@@ -91,6 +91,7 @@ void *_devres_alloc(dr_release_t release, size_t size, gfp_t
gfp)
return dr->data;
}
+#if CONFIG_DEVRES
void devres_free(void *res)
{
if (res) {
@@ -257,7 +258,7 @@ void devres_get_stats(const struct udevice *dev, struct
devres_stats *stats)
}
}
-#endif
+#endif /* CONFIG_DEBUG_DEVRES */
/*
* Managed kmalloc/kfree
@@ -292,3 +293,4 @@ void devm_kfree(struct udevice *dev, void *p)
rc = devres_destroy(dev, devm_kmalloc_release, devm_kmalloc_match, p);
assert_noisy(!rc);
}
+#endif /* CONFIG_DEVRES */
--
2.25.1
[PATCH 1/2] usb: dwc3: dwc3-generic: check the parent nodes
The kernel devicetree has definitions for port and hub nodes as subnodes
to the USB devices. These subnodes don't contain all of the data required
to properly configure the dwc3. Check the parent nodes if the data is not
in the port/hub node.
Here's an example from the librem5 kernel dts file
_dwc3_0 {
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
status = "okay";
port@0 {
reg = <0>;
typec_hs: endpoint {
remote-endpoint = <_con_hs>;
};
};
port@1 {
reg = <1>;
typec_ss: endpoint {
remote-endpoint = <_con_ss>;
};
};
};
_dwc3_1 {
dr_mode = "host";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* Microchip USB2642 */
hub@1 {
compatible = "usb424,2640";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mass-storage@1 {
compatible = "usb424,4041";
reg = <1>;
};
};
};
Signed-off-by: Angus Ainslie
---
drivers/usb/dwc3/dwc3-generic.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 8d53ba7790..01bd0ca190 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -110,7 +110,12 @@ static int dwc3_generic_of_to_plat(struct udevice *dev)
struct dwc3_generic_plat *plat = dev_get_plat(dev);
ofnode node = dev_ofnode(dev);
- plat->base = dev_read_addr(dev);
+ if (!strncmp(dev->name, "port", 4) || !strncmp(dev->name, "hub", 3)) {
+ /* This is a leaf so check the parent */
+ plat->base = dev_read_addr(dev->parent);
+ } else {
+ plat->base = dev_read_addr(dev);
+ }
plat->maximum_speed = usb_get_maximum_speed(node);
if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
@@ -120,8 +125,13 @@ static int dwc3_generic_of_to_plat(struct udevice *dev)
plat->dr_mode = usb_get_dr_mode(node);
if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
- pr_err("Invalid usb mode setup\n");
- return -ENODEV;
+ /* might be a leaf so check the parent for mode */
+ node = dev_ofnode(dev->parent);
+ plat->dr_mode = usb_get_dr_mode(node);
+ if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
+ pr_err("Invalid usb mode setup\n");
+ return -ENODEV;
+ }
}
return 0;
@@ -301,16 +311,20 @@ static int dwc3_glue_bind(struct udevice *parent)
{
ofnode node;
int ret;
+ enum usb_dr_mode dr_mode;
+
+ dr_mode = usb_get_dr_mode(dev_ofnode(parent));
ofnode_for_each_subnode(node, dev_ofnode(parent)) {
const char *name = ofnode_get_name(node);
- enum usb_dr_mode dr_mode;
struct udevice *dev;
const char *driver = NULL;
debug("%s: subnode name: %s\n", __func__, name);
- dr_mode = usb_get_dr_mode(node);
+ /* if the parent node doesn't have a mode check the leaf */
+ if (!dr_mode)
+ dr_mode = usb_get_dr_mode(node);
switch (dr_mode) {
case USB_DR_MODE_PERIPHERAL:
@@ -450,6 +464,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "qcom,dwc3" },
+ { .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }
};
--
2.25.1
[PATCH 2/2] usb: dwc3: core: stop the core when it's removed
If u-boot doesn't stop the core when it's finished with it then
linux can't find it.
Signed-off-by: Angus Ainslie
---
drivers/usb/dwc3/core.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ce1c0e88c2..b592a487e0 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -706,6 +706,14 @@ static void dwc3_gadget_run(struct dwc3 *dwc)
mdelay(100);
}
+static void dwc3_core_stop(struct dwc3 *dwc)
+{
+ u32 reg;
+
+ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+ dwc3_writel(dwc->regs, DWC3_DCTL, reg & ~(DWC3_DCTL_RUN_STOP));
+}
+
static void dwc3_core_exit_mode(struct dwc3 *dwc)
{
switch (dwc->dr_mode) {
@@ -1128,6 +1136,7 @@ void dwc3_remove(struct dwc3 *dwc)
dwc3_core_exit_mode(dwc);
dwc3_event_buffers_cleanup(dwc);
dwc3_free_event_buffers(dwc);
+ dwc3_core_stop(dwc);
dwc3_core_exit(dwc);
kfree(dwc->mem);
}
--
2.25.1
[PATCH 0/2] Fixes for the dwc3 driver
dwc3 driver fixes to work better with the linux kernel. Angus Ainslie (2): usb: dwc3: dwc3-generic: check the parent nodes usb: dwc3: core: stop the core when it's removed drivers/usb/dwc3/core.c | 9 + drivers/usb/dwc3/dwc3-generic.c | 25 - 2 files changed, 29 insertions(+), 5 deletions(-) -- 2.25.1
[PATCH] mach-imx: iomux-v3: add a define for the SION bit
SION (Software Input On Field) - force the select mode input path Signed-off-by: Angus Ainslie --- arch/arm/include/asm/mach-imx/iomux-v3.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 9330a32fe9..231b9c027c 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -243,6 +243,7 @@ typedef u64 iomux_v3_cfg_t; #endif +#define IMX_PAD_SION 0x4000 #define IOMUX_CONFIG_SION 0x10 #define GPIO_PIN_MASK 0x1f -- 2.25.1
