RE: [PATCH 071/149] board: hoperun: Remove and add needed includes

[Biju Das]

Hi Tom,

> Subject: [PATCH 071/149] board: hoperun: Remove  and add needed 
> includes
> 
> Remove  from this board vendor directory and when needed add 
> missing include files
> directly.
> 
> Signed-off-by: Tom Rini 

Reviewed-by: Biju Das 

> ---
> Cc: Biju Das 
> ---
>  board/hoperun/hihope-rzg2/hihope-rzg2.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c 
> b/board/hoperun/hihope-rzg2/hihope-rzg2.c
> index 68d3d300dc40..0966e257464a 100644
> --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
> +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2021 Renesas Electronics Corporation
>   */
> 
> -#include 
>  #include 
>  #include 
>  #include 
> --
> 2.34.1

RE: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Biju Das]

> -Original Message-
> From: U-Boot  On Behalf Of Paul Barker
> Sent: Monday, February 26, 2024 3:06 PM
> To: Marek Vasut ; Nobuhiro Iwamatsu
> 
> Cc: Paul Barker ; u-boot@lists.denx.de
> Subject: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
> 
> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC,
> also known as the RIIC module.
> 
> This patch is based on both the u-boot driver in the Renesas RZ BSP
> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit
> 0dd3ee311255).
> 
> Support for deblocking the I2C bus is included as this may be needed after
> triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC
> asserts the reset line before the SoC completes the I2C write transaction
> with obvious bus locking effects). If the SDA line is observed to be low
> during initialisation, we automatically attempt to deblock.
> 
> [1]:
> 
> Signed-off-by: Paul Barker 
> eviewed-by: Marek Vasut 

Typo. R is missing in the Rb tag.

Also change log is missing.

> ---
>  arch/arm/mach-rmobile/Kconfig |   1 +
>  configs/renesas_rzg2l_smarc_defconfig |   2 +
>  drivers/i2c/Kconfig   |   7 +
>  drivers/i2c/Makefile  |   1 +
>  drivers/i2c/rz_riic.c | 624 ++
>  5 files changed, 635 insertions(+)
>  create mode 100644 drivers/i2c/rz_riic.c
> 
> diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
> index 2bb96749fc0d..38ede6e0b5b5 100644
> --- a/arch/arm/mach-rmobile/Kconfig
> +++ b/arch/arm/mach-rmobile/Kconfig
> @@ -78,6 +78,7 @@ config RZG2L
>   imply RENESAS_SDHI
>   imply RZG2L_GPIO
>   imply SCIF_CONSOLE
> + imply SYS_I2C_RZ_RIIC
>   imply SYS_MALLOC_F
>   help
> Enable support for the Renesas RZ/G2L family of SoCs. Currently
> diff --git a/configs/renesas_rzg2l_smarc_defconfig
> b/configs/renesas_rzg2l_smarc_defconfig
> index e45579ae6b98..ad46297c6619 100644
> --- a/configs/renesas_rzg2l_smarc_defconfig
> +++ b/configs/renesas_rzg2l_smarc_defconfig
> @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y
>  CONFIG_SYS_MAXARGS=64
>  CONFIG_CMD_CLK=y
>  CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
>  CONFIG_CMD_MMC=y
>  CONFIG_CMD_PART=y
>  CONFIG_CMD_EXT2=y
> @@ -44,6 +45,7 @@ CONFIG_CLK=y
>  CONFIG_CLK_RENESAS=y
>  # CONFIG_CLK_RCAR_GEN3 is not set
>  CONFIG_GPIO_HOG=y
> +CONFIG_DM_I2C=y
>  CONFIG_MMC_IO_VOLTAGE=y
>  CONFIG_MMC_UHS_SUPPORT=y
>  CONFIG_MMC_HS400_SUPPORT=y
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index
> 4f42200f3923..d2a3a13493aa 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP
> have several I2C ports and all are provided, controlled by the
> device tree.
> 
> +config SYS_I2C_RZ_RIIC
> + bool "Renesas RZ/G2L RIIC driver"
> + depends on RZG2L && DM_I2C
> + help
> +   Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
> +   family.
> +
>  config SYS_I2C_SANDBOX
>   bool "Sandbox I2C driver"
>   depends on SANDBOX && DM_I2C
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index
> a96a8c7e955e..692f63bafd02 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o
>  obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
>  obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
>  obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
> +obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o
>  obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
>  obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
>  obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
> diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c new file mode
> 100644 index ..5f3f8d1b24b7
> --- /dev/null
> +++ b/drivers/i2c/rz_riic.c
> @@ -0,0 +1,624 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * RZ/G2L I2C (RIIC) driver
> + *
> + * Copyright (C) 2021-2023 Renesas Electronics Corp.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define RIIC_ICCR1   0x00
> +#define RIIC_ICCR2   0x04
> +#define RIIC_ICMR1   0x08
> +#define RIIC_ICMR2   0x0c
> +#define RIIC_ICMR3   0x10
> +#define RIIC_ICFER   0x14
> +#define RIIC_ICSER   0x18
> +#define RIIC_ICIER   0x1c
> +#define RIIC_ICSR1   0x20
> +#define RIIC_ICSR2   0x24
> +#define RIIC_ICSAR0  0x28
> +#define RIIC_ICBRL   0x34
> +#define RIIC_ICBRH   0x38
> +#define RIIC_ICDRT   0x3c
> +#define RIIC_ICDRR   0x40
> +
> +/* ICCR1 */
> +#define ICCR1_ICEBIT(7)
> +#define ICCR1_IICRST BIT(6)
> +#define ICCR1_CLOBIT(5)
> +#define ICCR1_SOWP   BIT(4)
> +#define ICCR1_SCLO   BIT(3)
> +#define ICCR1_SDAO   BIT(2)
> +#define ICCR1_SCLI   BIT(1)
> +#define ICCR1_SDAI   BIT(0)
> +
> +/* ICCR2 */
> +#define ICCR2_BBSY   BIT(7)
> +#define ICCR2_MSTBIT(6)
> +#define ICCR2_TRSBIT(5)
> +#define ICCR2_SP 

RE: [PATCH 2/8] arm: mach-rmobile: Drop

[Biju Das]

Hi Paul,

Thanks for the patch.

> Subject: [PATCH 2/8] arm: mach-rmobile: Drop 
> 
> For most source files we can just drop . We need to add an
> include for  in a couple of places. Also sort the include
> list in memmap-gen3.c while we're here.

Why only sorting memmap-gen3.c? why not sorting all the files touching here?

Cheers,
Biju

> 
> Signed-off-by: Paul Barker 
> ---
>  arch/arm/mach-rmobile/board.c| 2 +-
>  arch/arm/mach-rmobile/cpu_info-r8a7740.c | 2 +-
>  arch/arm/mach-rmobile/cpu_info-rcar.c| 2 +-
>  arch/arm/mach-rmobile/cpu_info-rzg.c | 2 +-
>  arch/arm/mach-rmobile/cpu_info-rzg2l.c   | 1 -
>  arch/arm/mach-rmobile/cpu_info.c | 2 +-
>  arch/arm/mach-rmobile/emac.c | 1 -
>  arch/arm/mach-rmobile/memmap-gen3.c  | 4 ++--
>  arch/arm/mach-rmobile/memmap-rzg2l.c | 2 +-
>  arch/arm/mach-rmobile/pfc-r8a7740.c  | 2 +-
>  arch/arm/mach-rmobile/psci-r8a779a0.c| 1 -
>  11 files changed, 9 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c
> index a10371f74e0c..79c7e02671f2 100644
> --- a/arch/arm/mach-rmobile/board.c
> +++ b/arch/arm/mach-rmobile/board.c
> @@ -3,7 +3,7 @@
>   * (C) Copyright 2012 Nobuhiro Iwamatsu 
>   * (C) Copyright 2012 Renesas Solutions Corp.
>   */
> -#include 
> +
>  #include 
>  #include 
> 
> diff --git a/arch/arm/mach-rmobile/cpu_info-r8a7740.c b/arch/arm/mach-
> rmobile/cpu_info-r8a7740.c
> index dcbe25f37ab9..5a94235c4b9e 100644
> --- a/arch/arm/mach-rmobile/cpu_info-r8a7740.c
> +++ b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
> @@ -3,7 +3,7 @@
>   * (C) Copyright 2012 Nobuhiro Iwamatsu 
>   * (C) Copyright 2012 Renesas Solutions Corp.
>   */
> -#include 
> +
>  #include 
> 
>  u32 rmobile_get_cpu_type(void)
> diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-
> rmobile/cpu_info-rcar.c
> index 8fc4cd7f9de8..b9d8b5e57b5a 100644
> --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> @@ -4,7 +4,7 @@
>   *
>   * Copyright (C) 2013,2014 Renesas Electronics Corporation
>   */
> -#include 
> +
>  #include 
> 
>  #define PRR_MASK 0x7fff
> diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c b/arch/arm/mach-
> rmobile/cpu_info-rzg.c
> index 1c18fd06f0b6..4ade4bc02198 100644
> --- a/arch/arm/mach-rmobile/cpu_info-rzg.c
> +++ b/arch/arm/mach-rmobile/cpu_info-rzg.c
> @@ -3,7 +3,7 @@
>   * Copyright (C) 2021 Renesas Electronics Corporation
>   *
>   */
> -#include 
> +
>  #include 
> 
>  /* If the firmware passed a device tree, use it for soc identification. */
> diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-
> rmobile/cpu_info-rzg2l.c
> index de4892ee901e..f69649dc7eaf 100644
> --- a/arch/arm/mach-rmobile/cpu_info-rzg2l.c
> +++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
> @@ -4,7 +4,6 @@
>   *
>   */
> 
> -#include 
>  #include 
>  #include 
> 
> diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-
> rmobile/cpu_info.c
> index 6804b1da2cda..895c0f5336b6 100644
> --- a/arch/arm/mach-rmobile/cpu_info.c
> +++ b/arch/arm/mach-rmobile/cpu_info.c
> @@ -3,7 +3,7 @@
>   * (C) Copyright 2012 Nobuhiro Iwamatsu 
>   * (C) Copyright 2012-2021 Renesas Solutions Corp.
>   */
> -#include 
> +
>  #include 
>  #include 
>  #include 
> diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c
> index cb9bce0cf23b..95651626da4a 100644
> --- a/arch/arm/mach-rmobile/emac.c
> +++ b/arch/arm/mach-rmobile/emac.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2012  Nobuhiro Iwamatsu
> 
>   */
> 
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-
> rmobile/memmap-gen3.c
> index a68eb806b353..4dff9e07629d 100644
> --- a/arch/arm/mach-rmobile/memmap-gen3.c
> +++ b/arch/arm/mach-rmobile/memmap-gen3.c
> @@ -5,10 +5,10 @@
>   * Copyright (C) 2017 Marek Vasut 
>   */
> 
> -#include 
> -#include 
>  #include 
>  #include 
> +#include 
> +#include 
> 
>  #define GEN3_NR_REGIONS 16
> 
> diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-
> rmobile/memmap-rzg2l.c
> index a08d0ea08fc0..9934a775220b 100644
> --- a/arch/arm/mach-rmobile/memmap-rzg2l.c
> +++ b/arch/arm/mach-rmobile/memmap-rzg2l.c
> @@ -6,9 +6,9 @@
>   * Copyright (C) 2023 Renesas Electronics Corp.
>   */
> 
> -#include 
>  #include 
>  #include 
> +#include 
>  #include 
> 
>  #define RZG2L_NR_REGIONS 16
> diff --git a/arch/arm/mach-rmobile/pfc-r8a7740.c b/arch/arm/mach-
> rmobile/pfc-r8a7740.c
> index 5d42a68266b1..4f4847699b07 100644
> --- a/arch/arm/mach-rmobile/pfc-r8a7740.c
> +++ b/arch/arm/mach-rmobile/pfc-r8a7740.c
> @@ -18,7 +18,7 @@
>   * along with this program; if not, write to the Free Software
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301
> USA
>   */
> -#include 
> +
>  #include 
>  #include 
>  #include 
> diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-
> rmobile/psci-r8a779a0.c
> index 

RE: [PATCH v2 11/19] serial: sh: Fix error handling

[Biju Das]

Hi Paul,

Thanks for the patch.

> Subject: [PATCH v2 11/19] serial: sh: Fix error handling
> 
> The current SCIF error handling is broken for the RZ/G2L. After a break
> condition has been triggered, the current code is unable to clear the error
> and serial port output never resumes.
> 
> The RZ/G2L datasheet says that most error conditions are cleared by
> resetting the relevant error bits in the FSR & LSR registers to zero.
> To clear framing errors, the invalid data also needs to be read out of the
> receive FIFO.
> 
> After reviewing datasheets for RZ/G2{H,M,N,E}, R-Car Gen4, R-Car Gen3 and
> even SH7751 SoCs, it's clear that this is the way to clear errors for all
> of these SoCs.
> 
> While we're here, annotate the handle_error() function with a couple of
> comments as the reads and writes themselves don't immediately make it clear
> what we're doing.
> 
> Signed-off-by: Paul Barker 
> ---
> v1->v2:
>   * New patch after discussion with Marek & further investigation.
> 
> I'm not going to put a `Fixes` tag on this, the error handling has been
> writing ones to clear errors since at least 2007 so maybe it was originally
> right for some board. It doesn't seem to apply to any of the current users
> of the SCIF driver though.
> 
>  drivers/serial/serial_sh.c | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index
> 5e543dbf3d58..2b650d458e71 100644
> --- a/drivers/serial/serial_sh.c
> +++ b/drivers/serial/serial_sh.c
> @@ -79,10 +79,22 @@ sh_serial_setbrg_generic(struct uart_port *port, int
> clk, int baudrate)
> 
>  static void handle_error(struct uart_port *port)  {
> - sci_in(port, SCxSR);
> - sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
> + /*
> +  * Most errors are cleared by resetting the relevant error bits to
> zero
> +  * in the FSR & LSR registers. For each register, a read followed by
> a
> +  * write is needed according to the relevant datasheets.
> +  */
> + unsigned short status = sci_in(port, SCxSR);
> + sci_out(port, SCxSR, status & ~SCIF_ERRORS);
>   sci_in(port, SCLSR);
>   sci_out(port, SCLSR, 0x00);
> +
> + /*
> +  * To clear framing errors, we also need to read and discard a
> +  * character.
> +  */
> + if (status & SCIF_FER)
> + sci_in(port, SCxRDR);

Do we need to read status again to make sure framing error
is cleared?

Cheers,
Biju

>  }
> 
>  static int serial_raw_putc(struct uart_port *port, const char c)
> --
> 2.39.2

RE: [PATCH 16/16] board: rzg2l: Add RZ/G2L SMARC EVK board

[Biju Das]

Hi Paul,

> Subject: Re: [PATCH 16/16] board: rzg2l: Add RZ/G2L SMARC EVK board
> 
> On 03/10/2023 14:36, Marek Vasut wrote:
> > On 9/20/23 14:42, Paul Barker wrote:
> >> The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
> >> System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common
> >> SMARC carrier board.
> >>
> >> The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes
> >> a devicetree blob to the bootloader as an argument in the same was
> >> previous R-Car gen3/gen4 SoCs. This blob contains a compatible string
> >> which can be used to identify the particular SoC we are running on
> >> and this is used to select the appropriate device tree to load.
> >>
> >> The configuration renesas_rzg2l_smarc_defconfig is added to support
> >> building for this target. In the future this defconfig will be
> >> extended to support other SoCs and evaluation boards from the RZ/G2L
> family.
> >>
> >> Signed-off-by: Paul Barker 
> >> Reviewed-by: Biju Das 
> >> Reviewed-by: Lad Prabhakar 
> >> ---
> >>   arch/arm/mach-rmobile/Kconfig.rzg2l   | 14 +
> >>   board/renesas/rzg2l/Kconfig   | 18 +++
> >>   board/renesas/rzg2l/MAINTAINERS   |  6 +++
> >>   board/renesas/rzg2l/Makefile  |  4 ++
> >>   board/renesas/rzg2l/rzg2l.c   | 76 +++
> >>   configs/renesas_rzg2l_smarc_defconfig | 52 ++
> >>   include/configs/rzg2l-smarc.h | 14 +
> >>   7 files changed, 184 insertions(+)
> >>   create mode 100644 board/renesas/rzg2l/Kconfig
> >>   create mode 100644 board/renesas/rzg2l/MAINTAINERS
> >>   create mode 100644 board/renesas/rzg2l/Makefile
> >>   create mode 100644 board/renesas/rzg2l/rzg2l.c
> >>   create mode 100644 configs/renesas_rzg2l_smarc_defconfig
> >>   create mode 100644 include/configs/rzg2l-smarc.h
> >>
> >> diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l
> >> b/arch/arm/mach-rmobile/Kconfig.rzg2l
> >> index 7d268e8c366a..1fe49e323300 100644
> >> --- a/arch/arm/mach-rmobile/Kconfig.rzg2l
> >> +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
> >> @@ -9,6 +9,20 @@ config R9A07G044L
> >>help
> >>  Enable support for the R9A07G044L SoC used in the RZ/G2L.
> >>
> >> +choice
> >> +  prompt "Renesas RZ/G2L Family Board selection"
> >> +  default TARGET_RZG2L_SMARC_EVK
> >> +
> >> +config TARGET_RZG2L_SMARC_EVK
> >> +  bool "Renesas RZ/G2L SMARC EVK"
> >> +  imply R9A07G044L
> >> +  help
> >> +Enable support for the RZ/G2L SMARC evaluation board.
> >> +
> >> +source "board/renesas/rzg2l/Kconfig"
> >> +
> >> +endchoice
> >> +
> >>   config MULTI_DTB_FIT_UNCOMPRESS_SZ
> >>default 0x8 if TARGET_RZG2L_SMARC_EVK
> >>
> >> diff --git a/board/renesas/rzg2l/Kconfig
> >> b/board/renesas/rzg2l/Kconfig new file mode 100644 index
> >> ..1335fc7ae806
> >> --- /dev/null
> >> +++ b/board/renesas/rzg2l/Kconfig
> >> @@ -0,0 +1,18 @@
> >> +# Copyright (C) 2023 Renesas Electronics Corporation #
> >> +SPDX-License-Identifier: GPL-2.0+
> >> +
> >> +if TARGET_RZG2L_SMARC_EVK
> >> +
> >> +config SYS_SOC
> >> +  default "rmobile"
> >> +
> >> +config SYS_BOARD
> >> +  default "rzg2l"
> >> +
> >> +config SYS_VENDOR
> >> +  default "renesas"
> >> +
> >> +config SYS_CONFIG_NAME
> >> +  default "rzg2l-smarc"
> >> +
> >> +endif
> >> diff --git a/board/renesas/rzg2l/MAINTAINERS
> >> b/board/renesas/rzg2l/MAINTAINERS new file mode 100644 index
> >> ..0a51391c1fc9
> >> --- /dev/null
> >> +++ b/board/renesas/rzg2l/MAINTAINERS
> >> @@ -0,0 +1,6 @@
> >> +RENESAS RZG2L BOARD FAMILY
> >> +M:Paul Barker 
> >> +S:Supported
> >> +F:arch/arm/dts/rz-smarc-common.dtsi
> >
> > I suspect there should be more files here, right ?
> > You likely want to be CCed on things like rzg2l clock, scif, and so on.
> >
> >> +N:rzg2l
> >> +N:r9a07g044
> >> diff --git a/board/renesas/rzg2l/Makefile
> >> b/board/renesas/rzg2l/Makefile new file mode 100644 index
> >> ..466935fc8158
> >&

RE: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver

[Biju Das]

Hi Paul Barker,

> Subject: Re: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver
> 
> On Wed, Oct 04, 2023 at 12:56:14PM +0000, Biju Das wrote:
> > Hi Marek and Paul,
> >
> > > Subject: Re: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver
> > >
> > > On 10/4/23 10:40, Paul Barker wrote:
> > > > On 03/10/2023 14:20, Marek Vasut wrote:
> > > >> On 9/20/23 14:42, Paul Barker wrote:
> > > >>> This driver provides pinctrl and gpio control for the Renesas
> > > >>> RZ/G2L
> > > >>> (R9A07G044) SoC.
> > > >>>
> > > >>> This patch is based on the corresponding Linux v6.5 driver.
> > > >>>
> > > >>> Signed-off-by: Paul Barker 
> > > >>> Reviewed-by: Biju Das 
> > > >>> Reviewed-by: Lad Prabhakar
> > > >>> 
> > > >>> ---
> > > >>>arch/arm/mach-rmobile/Kconfig   |   1 +
> > > >>>drivers/pinctrl/renesas/Kconfig |   9 +
> > > >>>drivers/pinctrl/renesas/Makefile|   1 +
> > > >>>drivers/pinctrl/renesas/rzg2l-pfc.c | 906
> > > 
> > > >>>4 files changed, 917 insertions(+)
> > > >>>create mode 100644 drivers/pinctrl/renesas/rzg2l-pfc.c
> > > >>>
> > > >>> diff --git a/arch/arm/mach-rmobile/Kconfig
> > > >>> b/arch/arm/mach-rmobile/Kconfig index 91f544c78337..973e84fcf7ba
> > > >>> 100644
> > > >>> --- a/arch/arm/mach-rmobile/Kconfig
> > > >>> +++ b/arch/arm/mach-rmobile/Kconfig
> > > >>> @@ -76,6 +76,7 @@ config RZG2L
> > > >>>   imply SYS_MALLOC_F
> > > >>>   imply RENESAS_SDHI
> > > >>>   imply CLK_RZG2L
> > > >>> + imply PINCTRL_RZG2L
> > > >>
> > > >> Keep the list sorted
> > > >>
> > > >> [...]
> > > >>
> > > >> Drop the parenthesis around values please, fix globally and in
> > > >> other patches too.
> > > >>
> > > >>> +#define PWPR (0x3014)
> > > >>> +#define SD_CH(n) (0x3000 + (n) * 4)
> > > >>> +#define QSPI (0x3008)
> > > >>> +
> > > >>> +#define PVDD_18001   /* I/O domain voltage <= 1.8V */
> > > >>> +#define PVDD_33000   /* I/O domain voltage >= 3.3V */
> > > >>> +
> > > >>> +#define PWPR_B0WIBIT(7)  /* Bit Write Disable */
> > > >>> +#define PWPR_PFCWE   BIT(6)  /* PFC Register Write Enable */
> > > >>> +
> > > >>> +#define PM_MASK  0x03
> > > >>> +#define PVDD_MASK0x01
> > > >>> +#define PFC_MASK 0x07
> > > >>> +#define IEN_MASK 0x01
> > > >>> +#define IOLH_MASK0x03
> > > >>> +
> > > >>> +#define PM_HIGH_Z0x0
> > > >>> +#define PM_INPUT 0x1
> > > >>> +#define PM_OUTPUT0x2
> > > >>> +#define PM_OUTPUT_IEN0x3
> > > >>> +
> > > >>> +struct rzg2l_pfc_driver_data {
> > > >>> + uint num_dedicated_pins;
> > > >>> + uint num_ports;
> > > >>> + const u32 *gpio_configs;
> > > >>> +};
> > > >>> +
> > > >>> +struct rzg2l_pfc_data {
> > > >>> + void __iomem *base;
> > > >>> + uint num_dedicated_pins;
> > > >>> + uint num_ports;
> > > >>> + uint num_pins;
> > > >>> + const u32 *gpio_configs;
> > > >>> + bool pfc_enabled;
> > > >>> +};
> > > >>> +
> > > >>> +struct rzg2l_dedicated_configs {
> > > >>> + const char *name;
> > > >>> + u32 config;
> > > >>> +};
> > > >>> +
> > > >>> +/*
> > > >>> + * We need to ensure that the module clock is enabled and all
> > > >>> +resets are
> > > >>> + * de-asserted before using either the gpio or pinctrl
> > > >>> +f

RE: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver

[Biju Das]

Hi Marek,
> Subject: Re: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver
> 
> On 10/4/23 14:56, Biju Das wrote:
> 
> [...]
> 
> >>>>> +   return -EINVAL;
> >>>>> +   }
> >>>>> +
> >>>>> +   uc_priv->gpio_count = args.args[2];
> >>>>> +   return rzg2l_pfc_enable(dev);
> >>>>> +}
> >>>>> +
> >>>>> +U_BOOT_DRIVER(rzg2l_pfc_gpio) = {
> >>>>> +   .name   = "rzg2l-pfc-gpio",
> >>>>> +   .id = UCLASS_GPIO,
> >>>>> +   .ops= _gpio_ops,
> >>>>> +   .probe  = rzg2l_gpio_probe,
> >>>>> +};
> >>>>
> >>>> Can you please split the GPIO and PFC drivers into separate files ?
> >>>
> >>> I assume you mean gpio and pinctrl here - the PFC handles both. I
> >>> can move the gpio driver out to drivers/gpio.
> >>
> >> Thanks. R-Car already does it that way.
> >
> > RCar has separate GPIO block and Pin control block So we have separate
> > drivers.
> >
> > On RZ/G2L we have only pinctrl block, ie, the reason it is integrated
> > driver in linux.
> >
> > If you make separate driver, how do you plan to share resources in u-
> boot. For eg: register/clock/reset??
> 
> Clock and reset are easy, just grab them twice, once in each driver.
> 
> Registers, well ... have a look at gen3_cpg_bind() in
> drivers/clk/renesas/clk-rcar-gen3.c . Specifically, see
> device_bind_with_driver_data() and how one common "superdriver" can get
> bound to an IP, and then instantiate and bind two "subdrivers" which each
> obtain resources claimed by the "superdriver" via (in this case) the 'info'
> parameter. That should work, right ?

Yes, it should work.

Thanks for the explanation.

Cheers,
Biju

RE: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver

[Biju Das]

Hi Marek and Paul,

> Subject: Re: [PATCH 09/16] pinctrl: renesas: Add RZ/G2L PFC driver
> 
> On 10/4/23 10:40, Paul Barker wrote:
> > On 03/10/2023 14:20, Marek Vasut wrote:
> >> On 9/20/23 14:42, Paul Barker wrote:
> >>> This driver provides pinctrl and gpio control for the Renesas RZ/G2L
> >>> (R9A07G044) SoC.
> >>>
> >>> This patch is based on the corresponding Linux v6.5 driver.
> >>>
> >>> Signed-off-by: Paul Barker 
> >>> Reviewed-by: Biju Das 
> >>> Reviewed-by: Lad Prabhakar 
> >>> ---
> >>>arch/arm/mach-rmobile/Kconfig   |   1 +
> >>>drivers/pinctrl/renesas/Kconfig |   9 +
> >>>drivers/pinctrl/renesas/Makefile|   1 +
> >>>drivers/pinctrl/renesas/rzg2l-pfc.c | 906
> 
> >>>4 files changed, 917 insertions(+)
> >>>create mode 100644 drivers/pinctrl/renesas/rzg2l-pfc.c
> >>>
> >>> diff --git a/arch/arm/mach-rmobile/Kconfig
> >>> b/arch/arm/mach-rmobile/Kconfig index 91f544c78337..973e84fcf7ba
> >>> 100644
> >>> --- a/arch/arm/mach-rmobile/Kconfig
> >>> +++ b/arch/arm/mach-rmobile/Kconfig
> >>> @@ -76,6 +76,7 @@ config RZG2L
> >>>   imply SYS_MALLOC_F
> >>>   imply RENESAS_SDHI
> >>>   imply CLK_RZG2L
> >>> + imply PINCTRL_RZG2L
> >>
> >> Keep the list sorted
> >>
> >> [...]
> >>
> >> Drop the parenthesis around values please, fix globally and in other
> >> patches too.
> >>
> >>> +#define PWPR (0x3014)
> >>> +#define SD_CH(n) (0x3000 + (n) * 4)
> >>> +#define QSPI (0x3008)
> >>> +
> >>> +#define PVDD_18001   /* I/O domain voltage <= 1.8V */
> >>> +#define PVDD_33000   /* I/O domain voltage >= 3.3V */
> >>> +
> >>> +#define PWPR_B0WIBIT(7)  /* Bit Write Disable */
> >>> +#define PWPR_PFCWE   BIT(6)  /* PFC Register Write Enable */
> >>> +
> >>> +#define PM_MASK  0x03
> >>> +#define PVDD_MASK0x01
> >>> +#define PFC_MASK 0x07
> >>> +#define IEN_MASK 0x01
> >>> +#define IOLH_MASK0x03
> >>> +
> >>> +#define PM_HIGH_Z0x0
> >>> +#define PM_INPUT 0x1
> >>> +#define PM_OUTPUT0x2
> >>> +#define PM_OUTPUT_IEN0x3
> >>> +
> >>> +struct rzg2l_pfc_driver_data {
> >>> + uint num_dedicated_pins;
> >>> + uint num_ports;
> >>> + const u32 *gpio_configs;
> >>> +};
> >>> +
> >>> +struct rzg2l_pfc_data {
> >>> + void __iomem *base;
> >>> + uint num_dedicated_pins;
> >>> + uint num_ports;
> >>> + uint num_pins;
> >>> + const u32 *gpio_configs;
> >>> + bool pfc_enabled;
> >>> +};
> >>> +
> >>> +struct rzg2l_dedicated_configs {
> >>> + const char *name;
> >>> + u32 config;
> >>> +};
> >>> +
> >>> +/*
> >>> + * We need to ensure that the module clock is enabled and all
> >>> +resets are
> >>> + * de-asserted before using either the gpio or pinctrl
> >>> +functionality. Error
> >>> + * handling can be quite simple here as if the PFC cannot be
> >>> +enabled then we
> >>> + * will not be able to progress with the boot anyway.
> >>> + */
> >>> +static int rzg2l_pfc_enable(struct udevice *dev) {
> >>> + struct rzg2l_pfc_data *data =
> >>> + (struct rzg2l_pfc_data *)dev_get_driver_data(dev);
> >>> + struct reset_ctl_bulk rsts;
> >>> + struct clk clk;
> >>> + int ret;
> >>> +
> >>> + if (data->pfc_enabled)
> >>
> >> When does this get triggered ?
> >
> > This is initialised to false in rzg2l_pfc_bind(), then this function
> > rzg2l_pfc_enable() sets it to true before a successful return. The
> > effect is that the PFC is enabled just once, regardless of whether the
> > pinctrl or gpio driver is probed first.
> 
> Why would be call to rzg2l_pfc_enable() a problem in the first place ?
> It just grabs and enables clock and ungates reset, the second time this is
&

RE: Applying DTB Overlays from ATF on RZ/G2

[Biju Das]

Hi Adam,

> Subject: Re: Applying DTB Overlays from ATF on RZ/G2
> 
> On Mon, Jan 9, 2023 at 2:46 AM Biju Das  wrote:
> >
> > Hi Adam,
> >
> > > Subject: Re: Applying DTB Overlays from ATF on RZ/G2
> > >
> > > On Sat, Jan 7, 2023 at 6:01 AM Adam Ford  wrote:
> > > >
> > > > On Wed, Jan 4, 2023 at 5:55 PM Marek Vasut  wrote:
> > > > >
> > > > > On 1/5/23 00:48, Heinrich Schuchardt wrote:
> > > > > > Am 5. Januar 2023 00:19:36 MEZ schrieb Adam Ford
> :
> > > > > >> On Wed, Jan 4, 2023 at 5:15 PM Heinrich Schuchardt
> > >  wrote:
> > > > > >>>
> > > > > >>> On 1/4/23 22:35, Adam Ford wrote:
> > > > > >>>> ATF generates a couple memory nodes based on how it's
> > > > > >>>> compiled and generates a reserved-memory node, and I want
> > > > > >>>> to overlay it with the device tree so Linux knows about this
> reserved memory.
> > > > > >>>>
> > > > > >>>> When I boot U-Boot, I can read the reserved-memory node:
> > > > > >>>>
> > > > > >>>> => fdt addr 0xe631e588
> > > > > >>>> Working FDT set to e631e588 => fdt print /reserved-memory
> > > > > >>>> reserved-memory {
> > > > > >>>> lossy-decompression@5400 { renesas,formats =
> > > > > >>>> <0x>; no-map; reg = <0x
> > > > > >>>> 0x5400 0x 0x0300>; compatible =
> > > > > >>>> "renesas,lossy-decompression", "shared-dma-pool"; }; }; =>
> > > > > >>>>
> > >
> > > + CC Biju Das
> >
> > > > > >>>> I attempt to overlay it with the following:
> > > > > >>>>
> > > > > >>>> => run loadfdt
> > > > > >>>> 65932 bytes read in 6 ms (10.5 MiB/s) => fdt addr
> > > > > >>>> $load_addr
> > > > > >>>
> > > > > >>> When actually setting the address you will see a message
> > > > > >>> "Working FDT set to %lx\n". So I assume $load_addr is empty.
> > > > > >>>
> > > > > >>> Did you mean $loadaddr or $fileaddr?
> > > > > >>
> > > > > >> Opps, that was a copy-paste error.  Even with that, I still
> > > > > >> get the failure to overlay:
> > > > > >>
> > > > > >
> > > > > > Did you load a .dtbo file to apply? You cannot apply a devicetree.
> > > > > >
> > > > > > Is the fdt that you want to apply the overlay to built with
> > > > > > symbols
> > > (dtc parameter -@)?
> > > > >
> > > > > Note that the fragment passed to U-Boot by upstream ATF is
> > > > > already automatically merged into the U-Boot control DT (see
> > > > > board/renesas/rcar-common/common.c ) . U-Boot should pass that
> > > > > on to Linux automatically.
> > > >
> > > > I ran some tests, and it appears the function fdtdec_board_setup
> > > > is never getting called.
> >
> > Without that board detection and proper memory detection in u-boot/kernel
> won't happen.
> > [1]
> > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felix
> > ir.bootlin.com%2Fu-boot%2Flatest%2Fsource%2Fboard%2Fhoperun%2Fhihope-r
> > zg2%2Fhihope-rzg2.c%23L83=05%7C01%7Cbiju.das.jz%40bp.renesas.com%
> > 7C0852ecec21cd4a3c09a908daf260323d%7C53d82571da1947e49cb4625a166a4a2a%
> > 7C0%7C0%7C638088792215848419%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwM
> > DAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C
> > a=RWHfDYQgV7duNwRByGAoqv%2BekIxYMEfUzQLJFME9sQY%3D=0
> >
> 
> Right now, my device trees have the memory node(s), but not the reserved-
> memory node which I'm trying to insert dymanically based on how ATF is
> built.
> 
> >
> > > > That looks like the code that grabs the blob from ATF.  I
> > > > intentionally removed the memory nodes from the kernel device tree
> > > > expecting the memory nodes to get added from ATF, but when I
> > > > booted it, it promptly hung.  That implied to me that the memory
> > > > nodes didn't get adde

RE: Applying DTB Overlays from ATF on RZ/G2

[Biju Das]

Hi Adam,

> Subject: Re: Applying DTB Overlays from ATF on RZ/G2
> 
> On Sat, Jan 7, 2023 at 6:01 AM Adam Ford  wrote:
> >
> > On Wed, Jan 4, 2023 at 5:55 PM Marek Vasut  wrote:
> > >
> > > On 1/5/23 00:48, Heinrich Schuchardt wrote:
> > > > Am 5. Januar 2023 00:19:36 MEZ schrieb Adam Ford :
> > > >> On Wed, Jan 4, 2023 at 5:15 PM Heinrich Schuchardt
>  wrote:
> > > >>>
> > > >>> On 1/4/23 22:35, Adam Ford wrote:
> > > >>>> ATF generates a couple memory nodes based on how it's compiled
> > > >>>> and generates a reserved-memory node, and I want to overlay it
> > > >>>> with the device tree so Linux knows about this reserved memory.
> > > >>>>
> > > >>>> When I boot U-Boot, I can read the reserved-memory node:
> > > >>>>
> > > >>>> => fdt addr 0xe631e588
> > > >>>> Working FDT set to e631e588
> > > >>>> => fdt print /reserved-memory
> > > >>>> reserved-memory {
> > > >>>> lossy-decompression@5400 {
> > > >>>> renesas,formats = <0x>; no-map; reg = <0x
> > > >>>> 0x5400 0x 0x0300>; compatible =
> > > >>>> "renesas,lossy-decompression", "shared-dma-pool"; }; }; =>
> > > >>>>
> 
> + CC Biju Das

> > > >>>> I attempt to overlay it with the following:
> > > >>>>
> > > >>>> => run loadfdt
> > > >>>> 65932 bytes read in 6 ms (10.5 MiB/s) => fdt addr $load_addr
> > > >>>
> > > >>> When actually setting the address you will see a message
> > > >>> "Working FDT set to %lx\n". So I assume $load_addr is empty.
> > > >>>
> > > >>> Did you mean $loadaddr or $fileaddr?
> > > >>
> > > >> Opps, that was a copy-paste error.  Even with that, I still get
> > > >> the failure to overlay:
> > > >>
> > > >
> > > > Did you load a .dtbo file to apply? You cannot apply a devicetree.
> > > >
> > > > Is the fdt that you want to apply the overlay to built with symbols
> (dtc parameter -@)?
> > >
> > > Note that the fragment passed to U-Boot by upstream ATF is already
> > > automatically merged into the U-Boot control DT (see
> > > board/renesas/rcar-common/common.c ) . U-Boot should pass that on to
> > > Linux automatically.
> >
> > I ran some tests, and it appears the function fdtdec_board_setup is
> > never getting called.  

Without that board detection and proper memory detection in u-boot/kernel won't 
happen.
[1] 
https://elixir.bootlin.com/u-boot/latest/source/board/hoperun/hihope-rzg2/hihope-rzg2.c#L83


> > That looks like the code that grabs the blob
> > from ATF.  I intentionally removed the memory nodes from the kernel
> > device tree expecting the memory nodes to get added from ATF, but when
> > I booted it, it promptly hung.  That implied to me that the memory
> > nodes didn't get added from ATF.
> >
> > I added some debug code and noticed that ft_board_setup did not get
> > executed, so I created a call to fdtdec_board_setup from
> > ft_board_setup and my board booted just fine.  I am curious to know if
> > other rcar/rzg2 boards are seeing something similar?  Is calling
> > fdtdec_board_setup from ft_board_setup appropriate?

It should be working as we are using lossy compression for media playback for 
VLP release
and VLP release[1] is using Mainline ATF and U-boot. Similar case for R-Car.
I remember correctly for lossy compression case, we explicitly add a node in 
kernel [2].

[1] 
https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip17/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts#L27

[2] 
https://github.com/renesas-rcar/linux-bsp/blob/v5.10.41/rcar-5.1.3.rc10/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts#L32


Cheers,
Biju

RE: [PATCH] ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash

[Biju Das]

Hi Adam,

Thanks for the patch.

> -Original Message-
> From: Adam Ford 
> Sent: 28 May 2021 01:31
> To: u-boot@lists.denx.de
> Cc: Biju Das ; Adam Ford 
> Subject: [PATCH] ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash
> 
> There is a QSPI NOR flash part on the board.  Because this chip isn't yet
> supported in Linux, but it is supported in U-Boot, and the face that the
> RPC_SPI compatible names are different in U-Boot and Linux, the device
> tree updates are confined to -u-boot.dtsi files.
> 

If RPC is configured for secure access in TF-A, u-boot fails. This patch works 
only 
if RPC configured for normal access(by compiling TF-A with 
RZG_RPC_HYPERFLASH_LOCKED=0).

May be you need to update this in the commit message.

> Signed-off-by: Adam Ford 

Reviewed-by: Biju Bas 

> 
> diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> index a0c0a7f35c..06271537b7 100644
> --- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> +++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> @@ -4,11 +4,19 @@
>   */
> 
>  / {
> + aliases {
> + spi0 = 
> + };
> +
>   soc {
>   u-boot,dm-pre-reloc;
>   };
>  };
> 
> + {
> + phy-mode = "rgmii-txid";
> +};
> +
>   {
>   u-boot,dm-pre-reloc;
>  };
> @@ -25,6 +33,25 @@
>   u-boot,dm-pre-reloc;
>  };
> 
> + {
> + compatible = "renesas,rcar-gen3-rpc";
> + num-cs = <1>;
> + spi-max-frequency = <4000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash0: spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> +};
> +
>   {
>   /delete-property/ cd-gpios;
>  };
> diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> index a0c0a7f35c..be0ce54e55 100644
> --- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> +++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> @@ -4,6 +4,10 @@
>   */
> 
>  / {
> + aliases {
> + spi0 = 
> + };
> +
>   soc {
>   u-boot,dm-pre-reloc;
>   };
> @@ -25,6 +29,25 @@
>   u-boot,dm-pre-reloc;
>  };
> 
> + {
> + compatible = "renesas,rcar-gen3-rpc";
> + num-cs = <1>;
> + spi-max-frequency = <4000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash0: spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> +};
> +
>   {
>   /delete-property/ cd-gpios;
>  };
> diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> index eef200af2d..228391e0df 100644
> --- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> +++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> @@ -4,6 +4,10 @@
>   */
> 
>  / {
> + aliases {
> + spi0 = 
> + };
> +
>   soc {
>   u-boot,dm-pre-reloc;
>   };
> @@ -25,6 +29,25 @@
>   u-boot,dm-pre-reloc;
>  };
> 
> + {
> + compatible = "renesas,rcar-gen3-rpc";
> + num-cs = <1>;
> + spi-max-frequency = <4000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash0: spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> +};
> +
>   {
>   /delete-property/ cd-gpios;
>   sd-uhs-sdr12;
> diff --git a/configs/r8a774a1_beacon_defconfig
> b/configs/r8a774a1_beacon_d

[PATCH v2] arm: mach-rmobile: Add CPU info support for RZ/G2

[Biju Das]

Add CPU info support for RZ/G2 SoC's.

Signed-off-by: Biju Das 
---
V1-->V2
 * Added support to make CPU info based on tfa is available only
   when CONFIG_RZ_G2 is enabled.
---
 arch/arm/mach-rmobile/Kconfig.64 |  5 +++
 arch/arm/mach-rmobile/Makefile   |  1 +
 arch/arm/mach-rmobile/cpu_info-rzg.c | 41 
 arch/arm/mach-rmobile/cpu_info.c | 21 --
 arch/arm/mach-rmobile/include/mach/rmobile.h |  1 +
 5 files changed, 65 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/cpu_info-rzg.c

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 8127d33f2d..3f7ec05379 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -57,6 +57,9 @@ config R8A77995
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
 
+config RZ_G2
+   bool "Renesas ARM SoCs RZ/G2 (64bit)"
+
 endmenu
 
 choice
@@ -107,6 +110,7 @@ config TARGET_HIHOPE_RZG2
imply R8A774A1
imply R8A774B1
imply R8A774E1
+   imply RZ_G2
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
@@ -116,6 +120,7 @@ config TARGET_HIHOPE_RZG2
 config TARGET_SILINUX_EK874
bool "Silicon Linux EK874 board"
imply R8A774C0
+   imply RZ_G2
help
   Support for Silicon Linux EK874 platform
 
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 9f56af465e..81a0dedb41 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o 
pfc-sh73a0.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
 
 OBJCOPYFLAGS_u-boot-spl.srec := -O srec
 quiet_cmd_objcopy = OBJCOPY $@
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c 
b/arch/arm/mach-rmobile/cpu_info-rzg.c
new file mode 100644
index 00..1c18fd06f0
--- /dev/null
+++ b/arch/arm/mach-rmobile/cpu_info-rzg.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ *
+ */
+#include 
+#include 
+
+/* If the firmware passed a device tree, use it for soc identification. */
+extern u64 rcar_atf_boot_args[];
+
+/* CPU information table */
+static const struct {
+   char *soc_name;
+   u8 cpu_name[10];
+} tfa_info[] = {
+   { "renesas,r8a774a1", "R8A774A1" },
+   { "renesas,r8a774b1", "R8A774B1" },
+   { "renesas,r8a774c0", "R8A774C0" },
+   { "renesas,r8a774e1", "R8A774E1" }
+};
+
+const u8 *rzg_get_cpu_name(void)
+{
+   void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+   bool ret = false;
+   int i;
+
+   if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+   return NULL;
+
+   for (i = 0; i < ARRAY_SIZE(tfa_info); i++) {
+   if (fdt_node_check_compatible(atf_fdt_blob, 0,
+ tfa_info[i].soc_name) == 0) {
+   ret = true;
+   break;
+   }
+   }
+
+   return ret ? tfa_info[i].cpu_name : NULL;
+}
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..9ec622bdb5 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012 Nobuhiro Iwamatsu 
- * (C) Copyright 2012 Renesas Solutions Corp.
+ * (C) Copyright 2012-2021 Renesas Solutions Corp.
  */
 #include 
 #include 
@@ -31,6 +31,11 @@ void enable_caches(void)
 
 #ifdef CONFIG_DISPLAY_CPUINFO
 #ifndef CONFIG_RZA1
+__weak const u8 *rzg_get_cpu_name(void)
+{
+   return 0;
+}
+
 static u32 __rmobile_get_cpu_type(void)
 {
return 0x0;
@@ -52,7 +57,7 @@ static u32 __rmobile_get_cpu_rev_fraction(void)
 u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
 
-/* CPU infomation table */
+/* CPU information table */
 static const struct {
u16 cpu_type;
u8 cpu_name[10];
@@ -86,14 +91,22 @@ static int rmobile_cpuinfo_idx(void)
return i;
 }
 
+static const u8 *get_cpu_name(int idx)
+{
+   const  u8 *cpu_name = rzg_get_cpu_name();
+
+   return cpu_name ? cpu_name : rmobile_cpuinfo[idx].cpu_name;
+}
+
 #ifdef CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
int i, idx = rmobile_cpuinfo_idx();
+   const u8 *cpu_name = get_cpu_name(idx);
char cpu[10] = { 0 };
 
for (i = 0; i < sizeof(cpu); i++)
-   cpu[i] = tolower(rmobile_cpuinfo[idx].cpu_name[i]);
+   cpu[i] 

[PATCH] arm: mach-rmobile: Add CPU info support for RZ/G2

[Biju Das]

Add CPU info support for RZ/G2 SoC's.

Signed-off-by: Biju Das 
---
RZ/G2M Logs:-

U-Boot 2021.04-rc2-00245-g9bfc7862e4 (Mar 02 2021 - 09:56:38 +)

CPU: Renesas Electronics R8A774A1 rev 1.3
Model: HopeRun HiHope RZ/G2M with sub board
DRAM:  3.9 GiB
MMC:   mmc@ee10: 0, mmc@ee16: 1
Loading Environment from MMC... OK
In:serial@e6e88000
Out:   serial@e6e88000
Err:   serial@e6e88000
Net:   eth0: ethernet@e680
Hit any key to stop autoboot:  0

RZ/G2N Logs:-

U-Boot 2021.04-rc2-00245-g9bfc7862e4 (Mar 02 2021 - 09:56:38 +)

CPU: Renesas Electronics R8A774B1 rev 1.1
Model: HopeRun HiHope RZ/G2N with sub board
DRAM:  3.9 GiB
MMC:   mmc@ee10: 0, mmc@ee16: 1
Loading Environment from MMC... OK
In:serial@e6e88000
Out:   serial@e6e88000
Err:   serial@e6e88000
Net:   eth0: ethernet@e680
Hit any key to stop autoboot:  0

RZ/G2H logs:-

U-Boot 2021.04-rc2-00245-g9bfc7862e4 (Mar 02 2021 - 09:56:38 +)

CPU: Renesas Electronics R8A774E1 rev 3.0
Model: HopeRun HiHope RZ/G2H with sub board
DRAM:  3.9 GiB
MMC:   mmc@ee10: 0, mmc@ee16: 1
Loading Environment from MMC... OK
In:serial@e6e88000
Out:   serial@e6e88000
Err:   serial@e6e88000
Net:   eth0: ethernet@e680
Hit any key to stop autoboot:  0
---
 arch/arm/mach-rmobile/Makefile   |  1 +
 arch/arm/mach-rmobile/cpu_info-rzg.c | 41 
 arch/arm/mach-rmobile/cpu_info.c | 21 --
 arch/arm/mach-rmobile/include/mach/rmobile.h |  1 +
 4 files changed, 60 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/cpu_info-rzg.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 3206bce722..da425afddd 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o 
pfc-sh73a0.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN3) += cpu_info-rzg.o
 
 OBJCOPYFLAGS_u-boot-spl.srec := -O srec
 quiet_cmd_objcopy = OBJCOPY $@
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c 
b/arch/arm/mach-rmobile/cpu_info-rzg.c
new file mode 100644
index 00..1c18fd06f0
--- /dev/null
+++ b/arch/arm/mach-rmobile/cpu_info-rzg.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ *
+ */
+#include 
+#include 
+
+/* If the firmware passed a device tree, use it for soc identification. */
+extern u64 rcar_atf_boot_args[];
+
+/* CPU information table */
+static const struct {
+   char *soc_name;
+   u8 cpu_name[10];
+} tfa_info[] = {
+   { "renesas,r8a774a1", "R8A774A1" },
+   { "renesas,r8a774b1", "R8A774B1" },
+   { "renesas,r8a774c0", "R8A774C0" },
+   { "renesas,r8a774e1", "R8A774E1" }
+};
+
+const u8 *rzg_get_cpu_name(void)
+{
+   void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+   bool ret = false;
+   int i;
+
+   if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+   return NULL;
+
+   for (i = 0; i < ARRAY_SIZE(tfa_info); i++) {
+   if (fdt_node_check_compatible(atf_fdt_blob, 0,
+ tfa_info[i].soc_name) == 0) {
+   ret = true;
+   break;
+   }
+   }
+
+   return ret ? tfa_info[i].cpu_name : NULL;
+}
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..9ec622bdb5 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012 Nobuhiro Iwamatsu 
- * (C) Copyright 2012 Renesas Solutions Corp.
+ * (C) Copyright 2012-2021 Renesas Solutions Corp.
  */
 #include 
 #include 
@@ -31,6 +31,11 @@ void enable_caches(void)
 
 #ifdef CONFIG_DISPLAY_CPUINFO
 #ifndef CONFIG_RZA1
+__weak const u8 *rzg_get_cpu_name(void)
+{
+   return 0;
+}
+
 static u32 __rmobile_get_cpu_type(void)
 {
return 0x0;
@@ -52,7 +57,7 @@ static u32 __rmobile_get_cpu_rev_fraction(void)
 u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
 
-/* CPU infomation table */
+/* CPU information table */
 static const struct {
u16 cpu_type;
u8 cpu_name[10];
@@ -86,14 +91,22 @@ static int rmobile_cpuinfo_idx(void)
return i;
 }
 
+static const u8 *get_cpu_name(int idx)
+{
+   const  u8 *cpu_name = rzg_get_cpu_name();
+
+   return cpu_name ? cpu_name : rmobile_cpuinfo[idx].cpu_name;
+}
+
 #ifdef CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
int i, idx = rmobile_cpuinfo_idx();
+   const u8 *cpu_name = get_cpu_name(idx);
  

[PATCH v9 4/5] arm: rmobile: Add HopeRun HiHope RZ/G2N board support

[Biju Das]

The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v4-v9:
 * Board identity for multidtb support derived from TF-A blob.
v3:
 * Seperated DT patches
v1->v2:
 * No Change. rebased on u-boot-sh/next
v1:
 * New patch
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++
 arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  6 ++-
 configs/hihope_rzg2_defconfig |  2 +-
 6 files changed, 88 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 26633fad57..2e16adcc76 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -812,6 +812,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774b1-beacon-rzg2n-kit.dtb \
r8a774e1-beacon-rzg2h-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
+   r8a774b1-hihope-rzg2n-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 00..0bdc6909bf
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi 
b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 00..6fab78e776
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ _sound;
+/delete-node/ 
+/delete-node/ _card;
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+
+/ {
+   /delete-node/ hdmi0-out;
+};
+
+/ {
+   soc {
+   /delete-node/ fdp1@fe94;
+   };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 2c2c60385d..03b99864ee 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -104,6 +104,7 @@ config TARGET_EBISU
 config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
+   imply R8A774B1
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c 
b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index a60529f780..2a61268c69 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * board/hoperun/hihope-rzg2/hihope-rzg2.c
- * This file is HiHope RZ/G2M board support.
+ * This file is HiHope RZ/G2[MN] board support.
  *
  * Copyright (C) 2021 Renesas Electronics Corporation
  */
@@ -100,6 +100,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
return 0;
 
+   if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
+   !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
+   return 0;
+
return -1;
 }
 #endif
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index bc40445b5e..73245d9cfc 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/c

[PATCH v9 3/5] arm: rmobile: Add HopeRun HiHope RZ/G2M board support

[Biju Das]

The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v8->v9
 * Board idenitty for multidtb is derived from TF-A blob.
v7->v8
 * Seperated DT patches
V6->V7
 * Seperated driver patches from board support patches.

v5->v6
  * Rebased to U-boot-sh/master
  * Changed the logic for USB0 channel0 Host support.
  * Enabled CONFIG_SOC_DEVICE_RENESAS option

V4->V5
  * Rebased to U-boot-sh/next

V3->V4
  * Added USB0 channel0 Host support

V2->V3  
   * Reworked as per Marek's suggestion
   * Added rzg2_get_cpu_type function to get cpu_type by matching TFA 
compatible string
   * Removed SoC family type Enum

V1->V2
 * Fixed indentation for R8A774A1 config
 * Used GPIO hog for setting WLAN/BT REG ON
 * Removed USB related initialization

V1:-
 * New Patch

---
 arch/arm/dts/Makefile   |   1 +
 arch/arm/mach-rmobile/Kconfig.64|  14 
 board/hoperun/hihope-rzg2/Kconfig   |  15 
 board/hoperun/hihope-rzg2/MAINTAINERS   |   6 ++
 board/hoperun/hihope-rzg2/Makefile  |   9 ++
 board/hoperun/hihope-rzg2/hihope-rzg2.c | 105 
 configs/hihope_rzg2_defconfig   |  82 ++
 include/configs/hihope-rzg2.h   |  20 +
 8 files changed, 252 insertions(+)
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 33e483f4fb..26633fad57 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -811,6 +811,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774b1-beacon-rzg2n-kit.dtb \
r8a774e1-beacon-rzg2h-kit.dtb \
+   r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index b95c8e8d29..2c2c60385d 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -4,6 +4,8 @@ menu "Select Target SoC"
 
 config R8A774A1
bool "Renesas SoC R8A774A1"
+   imply CLK_R8A774A1
+   imply PINCTRL_PFC_R8A774A1
 
 config R8A774B1
bool "Renesas SoC R8A774B1"
@@ -99,6 +101,15 @@ config TARGET_EBISU
help
   Support for Renesas R-Car Gen3 Ebisu platform
 
+config TARGET_HIHOPE_RZG2
+   bool "HiHope RZ/G2 board"
+   imply R8A774A1
+   imply SYS_MALLOC_F
+   imply MULTI_DTB_FIT
+   imply MULTI_DTB_FIT_USER_DEFINED_AREA
+   help
+  Support for RZG2 HiHope platform
+
 config TARGET_SALVATOR_X
bool "Salvator-X board"
imply R8A7795
@@ -133,12 +144,15 @@ source "board/renesas/ebisu/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/beacon/beacon-rzg2m/Kconfig"
+source "board/hoperun/hihope-rzg2/Kconfig"
 
 config MULTI_DTB_FIT_UNCOMPRESS_SZ
+   default 0x8 if TARGET_HIHOPE_RZG2
default 0x8 if TARGET_SALVATOR_X
default 0x8 if TARGET_ULCB
 
 config MULTI_DTB_FIT_USER_DEF_ADDR
+   default 0x4900 if TARGET_HIHOPE_RZG2
default 0x4900 if TARGET_SALVATOR_X
default 0x4900 if TARGET_ULCB
 
diff --git a/board/hoperun/hihope-rzg2/Kconfig 
b/board/hoperun/hihope-rzg2/Kconfig
new file mode 100644
index 00..ee422ba6c8
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIHOPE_RZG2
+
+config SYS_SOC
+   default "rmobile"
+
+config SYS_BOARD
+   default "hihope-rzg2"
+
+config SYS_VENDOR
+   default "hoperun"
+
+config SYS_CONFIG_NAME
+   default "hihope-rzg2"
+
+endif
diff --git a/board/hoperun/hihope-rzg2/MAINTAINERS 
b/board/hoperun/hihope-rzg2/MAINTAINERS
new file mode 100644
index 00..e3702fd12e
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/MAINTAINERS
@@ -0,0 +1,6 @@
+HIHOPE_RZG2 BOARD
+M: Biju Das 
+S: Maintained
+F: board/hoperun/hihope-rzg2/
+F: include/configs/hihope-rzg2.h
+F: configs/hihope_rzg2_defconfig
diff --git a/board/hoperun/hihope-rzg2/Makefile 
b/board/hoperun/hihope-rzg2/Makefile
new file mode 100644
index 00..e989e7aacc
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/Makefile
@@ -0,0 +1,9 @@
+#
+# board/hoperun/hihope-rzg2/Makefile
+#
+# Co

[PATCH v9 5/5] arm: rmobile: Add HopeRun HiHope RZ/G2H board support

[Biju Das]

The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v4-v9:
 * Board identity for multidtb support derived from TF-A blob.
v3:
 * Seperated DT patches
v1->v2:
 * No Change. rebased on u-boot-sh/next
v1:
 * New patch
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 +
 arch/arm/dts/r8a774e1-u-boot.dtsi | 59 +++
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  6 +-
 configs/hihope_rzg2_defconfig |  2 +-
 6 files changed, 94 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2e16adcc76..6cdd4a9c48 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -813,6 +813,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774e1-beacon-rzg2h-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
+   r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
new file mode 100644
index 00..03a17bac7e
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "r8a774e1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi 
b/arch/arm/dts/r8a774e1-u-boot.dtsi
new file mode 100644
index 00..74758dfedf
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ _sound;
+/delete-node/ 
+/delete-node/ _card;
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+
+/ {
+   /delete-node/ hdmi0-out;
+};
+
+/ {
+   soc {
+   /delete-node/ fdp1@fe94;
+   /delete-node/ fdp1@fe944000;
+   };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 03b99864ee..7eec65d8ea 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -105,6 +105,7 @@ config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
imply R8A774B1
+   imply R8A774E1
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c 
b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index 2a61268c69..c1bfdcbc1d 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * board/hoperun/hihope-rzg2/hihope-rzg2.c
- * This file is HiHope RZ/G2[MN] board support.
+ * This file is HiHope RZ/G2[HMN] board support.
  *
  * Copyright (C) 2021 Renesas Electronics Corporation
  */
@@ -104,6 +104,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
return 0;
 
+   if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
+   !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
+   return 0;
+
return -1;
 }
 #endif
diff --git a/configs/hihope_rzg2_

[PATCH v9 2/5] arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.11

[Biju Das]

Synchronize r8a774e1 device trees with Linux 5.11,
commit f40ddce88593482919 ("Linux 5.11").

Signed-off-by: Biju Das 
---
 * New patch
---
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 20 +++
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts| 41 +++
 2 files changed, 61 insertions(+)
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts

diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 00..8129959398
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+"renesas,r8a774e1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 00..9525d5ed6f
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+   compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@5 {
+   device_type = "memory";
+   reg = <0x5 0x 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
-- 
2.17.1

[PATCH v9 1/5] arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.11

[Biju Das]

Synchronize r8a774b1 device trees with Linux 5.11,
commit f40ddce88593482919 ("Linux 5.11")

Signed-off-by: Biju Das 
---
 * New patch
---
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 21 
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts| 41 +++
 2 files changed, 62 insertions(+)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts

diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 00..60d7c8adea
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+"renesas,r8a774b1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 00..f1883cbd1a
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+   compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
-- 
2.17.1

[PATCH v9 0/5] Add RZ/G2[HMN] board support

[Biju Das]

This patch series adds the required SoC/Board support to boot HopeRun
HiHope RZ/G2[HMN] boards. Board identification support for supporting
multidtb is derived from TF-A blob.

V8-->v9
 * Use tf-a blob for identifying board type.

Biju Das (5):
  arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.11
  arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.11
  arm: rmobile: Add HopeRun HiHope RZ/G2M board support
  arm: rmobile: Add HopeRun HiHope RZ/G2N board support
  arm: rmobile: Add HopeRun HiHope RZ/G2H board support

 arch/arm/dts/Makefile |   3 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts |  21 
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts |  27 +
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts|  41 +++
 arch/arm/dts/r8a774b1-u-boot.dtsi |  53 
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts |  20 
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts |  27 +
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts|  41 +++
 arch/arm/dts/r8a774e1-u-boot.dtsi |  59 +
 arch/arm/mach-rmobile/Kconfig.64  |  16 +++
 board/hoperun/hihope-rzg2/Kconfig |  15 +++
 board/hoperun/hihope-rzg2/MAINTAINERS |   6 +
 board/hoperun/hihope-rzg2/Makefile|   9 ++
 board/hoperun/hihope-rzg2/hihope-rzg2.c   | 113 ++
 configs/hihope_rzg2_defconfig |  82 +
 include/configs/hihope-rzg2.h |  20 
 16 files changed, 553 insertions(+)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

-- 
2.17.1

RE: [PATCH v5] dm: core: Add of_match_node helper function

[Biju Das]

Hi Simon,

I have a discussion with Marek and as per him this patch is wrongly assigned to 
him in patchwork. This patch supposed to be picked up by you.

I will rebase this patch to latest master and send it you.

Regards,
Biju

> -Original Message-
> From: Biju Das
> Sent: 15 February 2021 08:19
> To: Simon Glass ; Marek Vasut
> ; Tom Rini 
> Cc: u-boot@lists.denx.de; Adam Ford ; Marek Vasut
> ; Nobuhiro Iwamatsu ;
> Chris Paterson ; Prabhakar Mahadev Lad
> 
> Subject: RE: [PATCH v5] dm: core: Add of_match_node helper function
> 
> Hi All,
> 
> Gentle remainder. Are we happy with this patch[1]?
> 
> Not sure who needs to merge  this patch. Currently this patch has been
> delegated to Marek and is reviewed by Simon.
> 
> [1] https://patchwork.ozlabs.org/project/uboot/patch/20210116124042.24007-
> 1-biju.das...@bp.renesas.com/
> 
> Regards,
> Biju
> 
> > -Original Message-
> > From: Biju Das 
> > Sent: 16 January 2021 12:41
> > To: Simon Glass 
> > Cc: Biju Das ; u-boot@lists.denx.de; Tom
> > Rini ; Adam Ford ; Marek Vasut
> > ; Nobuhiro Iwamatsu
> > ; Chris Paterson ;
> > Prabhakar Mahadev Lad 
> > Subject: [PATCH v5] dm: core: Add of_match_node helper function
> >
> > Add of_match_node() helper function to iterate over the device tree
> > and tell if a device_node has a matching of_match structure.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar 
> > Reviewed-by: Simon Glass 
> > ---
> > v4->v5:
> >  * Rebased to latest master
> > v3->v4: No change
> >  * Added Simon's Rb tag.
> > v2->v3:
> >  * Added a test case for of_match_node helper function.
> >  (Ref:
> > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> > hwor
> > k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201102150959.4793-2-
> > biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.re
> > nesa
> > s.com%7C9a457b5b5cef4377a0a608d8ba1bf25f%7C53d82571da1947e49cb4625a166
> > a4a2
> > a%7C0%7C0%7C63746397665584%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
> > wMDA
> > iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=0DB8m
> > 2aLk
> > J0YqTFtjqXBpOmYpQAZO7eh7omBDGzrNR4%3Dreserved=0)
> > v1->v2:
> >  * No Change
> > v1:
> >  * New Patch
> > ---
> >  drivers/core/device.c | 21 +
> >  include/dm/device.h   | 13 +
> >  test/dm/core.c| 31 +++
> >  3 files changed, 65 insertions(+)
> >
> > diff --git a/drivers/core/device.c b/drivers/core/device.c index
> > aeab3836ed..4ff708fd38 100644
> > --- a/drivers/core/device.c
> > +++ b/drivers/core/device.c
> > @@ -1022,6 +1022,27 @@ bool of_machine_is_compatible(const char *compat)
> > return !fdt_node_check_compatible(fdt, 0, compat);  }
> >
> > +static
> > +const struct udevice_id *__of_match_node(const struct udevice_id
> > *matches,
> > +const ofnode node)
> > +{
> > +   if (!matches)
> > +   return NULL;
> > +
> > +   for (; matches->compatible; matches++) {
> > +   if (ofnode_device_is_compatible(node, matches->compatible))
> > +   return matches;
> > +   }
> > +
> > +   return NULL;
> > +}
> > +
> > +const struct udevice_id *of_match_node(const struct udevice_id
> *matches,
> > +  const ofnode node)
> > +{
> > +   return __of_match_node(matches, node); }
> > +
> >  int dev_disable_by_path(const char *path)  {
> > struct uclass *uc;
> > diff --git a/include/dm/device.h b/include/dm/device.h index
> > f5b4cd6876..950fc78184 100644
> > --- a/include/dm/device.h
> > +++ b/include/dm/device.h
> > @@ -802,6 +802,19 @@ bool device_is_compatible(const struct udevice
> > *dev, const char *compat);
> >   */
> >  bool of_machine_is_compatible(const char *compat);
> >
> > +/**
> > + * of_match_node() - Tell if a device_node has a matching of_match
> > +structure
> > + *
> > + *
> > + * Low level utility function used by device matching.
> > + *
> > + * @matches:   array of of device match structures to search in
> > + * @node:  the of device structure to match against
> > + * @return matching structure on success, NULL if the match is not
> > +found  */ const struct udevice_id *of_match_node(const struct
> > +udevice_id *matches,
> > +  const ofnode node)

RE: [PATCH v5] dm: core: Add of_match_node helper function

[Biju Das]

Hi All,

Gentle remainder. Are we happy with this patch[1]?

Not sure who needs to merge  this patch. Currently this patch has been 
delegated to Marek and is reviewed by Simon.

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20210116124042.24007-1-biju.das...@bp.renesas.com/

Regards,
Biju

> -Original Message-
> From: Biju Das 
> Sent: 16 January 2021 12:41
> To: Simon Glass 
> Cc: Biju Das ; u-boot@lists.denx.de; Tom Rini
> ; Adam Ford ; Marek Vasut
> ; Nobuhiro Iwamatsu ;
> Chris Paterson ; Prabhakar Mahadev Lad
> 
> Subject: [PATCH v5] dm: core: Add of_match_node helper function
> 
> Add of_match_node() helper function to iterate over the device tree and
> tell if a device_node has a matching of_match structure.
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Lad Prabhakar 
> Reviewed-by: Simon Glass 
> ---
> v4->v5:
>  * Rebased to latest master
> v3->v4: No change
>  * Added Simon's Rb tag.
> v2->v3:
>  * Added a test case for of_match_node helper function.
>  (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201102150959.4793-2-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C9a457b5b5cef4377a0a608d8ba1bf25f%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C63746397665584%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=0DB8m2aLk
> J0YqTFtjqXBpOmYpQAZO7eh7omBDGzrNR4%3Dreserved=0)
> v1->v2:
>  * No Change
> v1:
>  * New Patch
> ---
>  drivers/core/device.c | 21 +
>  include/dm/device.h   | 13 +
>  test/dm/core.c| 31 +++
>  3 files changed, 65 insertions(+)
> 
> diff --git a/drivers/core/device.c b/drivers/core/device.c index
> aeab3836ed..4ff708fd38 100644
> --- a/drivers/core/device.c
> +++ b/drivers/core/device.c
> @@ -1022,6 +1022,27 @@ bool of_machine_is_compatible(const char *compat)
>   return !fdt_node_check_compatible(fdt, 0, compat);  }
> 
> +static
> +const struct udevice_id *__of_match_node(const struct udevice_id
> *matches,
> +  const ofnode node)
> +{
> + if (!matches)
> + return NULL;
> +
> + for (; matches->compatible; matches++) {
> + if (ofnode_device_is_compatible(node, matches->compatible))
> + return matches;
> + }
> +
> + return NULL;
> +}
> +
> +const struct udevice_id *of_match_node(const struct udevice_id *matches,
> +const ofnode node)
> +{
> + return __of_match_node(matches, node); }
> +
>  int dev_disable_by_path(const char *path)  {
>   struct uclass *uc;
> diff --git a/include/dm/device.h b/include/dm/device.h index
> f5b4cd6876..950fc78184 100644
> --- a/include/dm/device.h
> +++ b/include/dm/device.h
> @@ -802,6 +802,19 @@ bool device_is_compatible(const struct udevice *dev,
> const char *compat);
>   */
>  bool of_machine_is_compatible(const char *compat);
> 
> +/**
> + * of_match_node() - Tell if a device_node has a matching of_match
> +structure
> + *
> + *
> + * Low level utility function used by device matching.
> + *
> + * @matches: array of of device match structures to search in
> + * @node:the of device structure to match against
> + * @return matching structure on success, NULL if the match is not
> +found  */ const struct udevice_id *of_match_node(const struct
> +udevice_id *matches,
> +const ofnode node);
> +
>  /**
>   * dev_disable_by_path() - Disable a device given its device tree path
>   *
> diff --git a/test/dm/core.c b/test/dm/core.c index 1f5ca570dc..aae4d8427d
> 100644
> --- a/test/dm/core.c
> +++ b/test/dm/core.c
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1067,6 +1068,36 @@ static int dm_test_inactive_child(struct
> unit_test_state *uts)  }  DM_TEST(dm_test_inactive_child,
> UT_TESTF_SCAN_PDATA);
> 
> +static int dm_test_of_match_node(struct unit_test_state *uts) {
> + const ulong test_data_expected = 0x1234;
> + ofnode root_node = ofnode_path("/");
> + const struct udevice_id *match;
> + unsigned long match_data;
> +
> + const struct udevice_id soc_device_ids[] = {
> + { .compatible = "sandbox", .data = test_data_expected, },
> + { /* sentinel */ }
> + };
> +
> + const struct udevice_id soc_device_nomatch_ids[] = {
> + { .compatible = "sandbox123&q

RE: [PATCH 1/5] arm: dts: r8a774a1: Import DTS queued for Linux 5.12-rc1

[Biju Das]

Hi Marek and Adam,

> Subject: Re: [PATCH 1/5] arm: dts: r8a774a1: Import DTS queued for Linux
> 5.12-rc1
> 
> On 2/1/21 4:19 PM, Adam Ford wrote:
> > On Mon, Jan 25, 2021 at 6:40 AM Marek Vasut  wrote:
> >>
> >> On 1/25/21 12:22 AM, Adam Ford wrote:
> >>> On Sun, Jan 24, 2021 at 11:10 AM Marek Vasut  wrote:
> 
>  On 1/13/21 12:52 AM, Adam Ford wrote:
> > Update the RZ/G2M dtsi and r8a774a1-beacon-rzg2m-kit kit from
> > Renesas repo destined to become 5.12-rc1.
> 
>  I picked a DT sync for Linux 5.10 from Biju (on CC), does your
>  board need something from 5.12-rc1 or can it be based on 5.10 too ?
> >>>
> >>> I honestly don't remember.  I had to unexpectedly leave town for
> >>> this week due to a funeral, and I won't be near a Linux development
> >>> computer to run tests until Feb 1, so I don't know if the board will
> >>> build using 5.10 or not.  Sorry I don't have a better answer.
> >>
> >> Lets revisit this later then.
> >
> > I tested the Beacon boards, but they have a dependency on usb2_clksel
> > that is not present in the 5.10 device tree.
> > I also noticed that I forgot to include versaclock.h dt-binding file
> > from the kernel, so the Beacon boards don't build for that too.
> >

Do we have usb2_clksel support in u-boot? If yes, it make sense to import from 
5.12-rc1.
Similarly for other bits importing from kernel 5.12-rc1.

May be rpc-spcif support available in u-boot. So we could import from 5.12-rc1.
For  others like PCIe, ethernet the changes corresponding to dts is not present 
in driver.

Do we have any plans to update the driver or plan to delete the properties/nodes
from U-boot specific dtsi, so that we can save image size?

> > I can submit a V2 with the binding file included, or I can submit the
> > dt-binding file now and wait on the Beacon boards until that file has
> > been merged, or I can redo the device tree in a custom way to work the
> > 5.10 and not use the veraclock dt-bindings since there is no
> > versaclock driver in U-Boot anyway.  You may have an alternative as
> > well.
> 
> Can you try to figure out the best option with Biju , who is in charge of
> all the RZG stuff ? Either way works for me.
> 
> You also likely want to roll V2 out soon, since the RC1 is out. I would
> still like to pick it for 2021.04 .

As Marek, suggested please send V2.

Regards,
Biju

[PATCH v3] arm: rmobile: Add HopeRun HiHope RZ/G2H board support

[Biju Das]

The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
This patch series depend on [1] and [2]
[1]https://patchwork.ozlabs.org/project/uboot/list/?series=224837
[2]https://patchwork.ozlabs.org/project/uboot/patch/20210117163013.6702-3-biju.das...@bp.renesas.com/
v3:
 * Separated DT patches
v1->v2:
 * No Change. rebased on u-boot-sh/next
v1:
 * New patch
---
 arch/arm/dts/Makefile   | 1 +
 arch/arm/mach-rmobile/Kconfig.64| 1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c | 6 +-
 configs/hihope_rzg2_defconfig   | 2 +-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 12943776a7..41e067b373 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -804,6 +804,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
+   r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 18153a809e..56c522596a 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -95,6 +95,7 @@ config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
imply R8A774B1
+   imply R8A774E1
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c 
b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index 66854bcadc..cb3dcf8db2 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * board/hoperun/hihope-rzg2/hihope-rzg2.c
- * This file is HiHope RZ/G2[MN] board support.
+ * This file is HiHope RZ/G2[HMN] board support.
  *
  * Copyright (C) 2020 Renesas Electronics Corporation
  */
@@ -90,6 +90,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
return 0;
 
+   if (soc_id == SOC_ID_R8A774E1 &&
+   !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
+   return 0;
+
return -1;
 }
 #endif
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index 3c37a80405..57eab4519e 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot"
+CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot 
r8a774e1-hihope-rzg2h-u-boot"
 CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
 CONFIG_ENV_OVERWRITE=y
-- 
2.17.1

[PATCH v3] arm: rmobile: Add HopeRun HiHope RZ/G2N board support

[Biju Das]

The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
This patch series depend on [1] and [2]
[1]https://patchwork.ozlabs.org/project/uboot/list/?series=224837
[2]https://patchwork.ozlabs.org/project/uboot/patch/20210117163013.6702-2-biju.das...@bp.renesas.com/

v3:
 * Seperated DT patches
v1->v2:
 * No Change. rebased on u-boot-sh/next
v1:
 * New patch
---
 arch/arm/dts/Makefile   | 1 +
 arch/arm/mach-rmobile/Kconfig.64| 1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c | 6 +-
 configs/hihope_rzg2_defconfig   | 2 +-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dc4bc90019..12943776a7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -803,6 +803,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
+   r8a774b1-hihope-rzg2n-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 47ca4bfb2e..18153a809e 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -94,6 +94,7 @@ config TARGET_EBISU
 config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
+   imply R8A774B1
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c 
b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index d49ad78871..66854bcadc 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * board/hoperun/hihope-rzg2/hihope-rzg2.c
- * This file is HiHope RZ/G2M board support.
+ * This file is HiHope RZ/G2[MN] board support.
  *
  * Copyright (C) 2020 Renesas Electronics Corporation
  */
@@ -86,6 +86,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
return 0;
 
+   if (soc_id == SOC_ID_R8A774B1 &&
+   !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
+   return 0;
+
return -1;
 }
 #endif
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index 5e568ab8ed..3c37a80405 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot"
+CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot"
 CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
 CONFIG_ENV_OVERWRITE=y
-- 
2.17.1

[PATCH v8] arm: rmobile: Add HopeRun HiHope RZ/G2M board support

[Biju Das]

The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
This patch depend on [1] and [2]
[1]https://patchwork.ozlabs.org/project/uboot/patch/20210117163013.6702-1-biju.das...@bp.renesas.com/
[2]https://patchwork.ozlabs.org/project/uboot/list/?series=224837

v7->v8
 * Seperated DT patches
V6->V7
 * Seperated driver patches from board support patches.
v5->v6
  * Rebased to U-boot-sh/master
  * Changed the logic for USB0 channel0 Host support.
  * Enabled CONFIG_SOC_DEVICE_RENESAS option

V4->V5
  * Rebased to U-boot-sh/next
  (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201012151616.5384-4-biju.das.jz@.../)

V3->V4
  * Added USB0 channel0 Host support
(Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-2-biju.das.jz@.../)
V2->V3  
   * Reworked as per Marek's suggestion
   * Added rzg2_get_cpu_type function to get cpu_type by matching TFA 
compatible string
   * Removed SoC family type Enum
   Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-3-biju.das.jz@.../

V1->V2
 * Fixed indentation for R8A774A1 config
 * Used GPIO hog for setting WLAN/BT REG ON
 * Removed USB related initialization
  Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-2-biju.das.jz@.../

V1:-
 * New Patch
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-5-biju.das.jz@.../
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/mach-rmobile/Kconfig.64| 14 
 board/hoperun/hihope-rzg2/Kconfig   | 15 
 board/hoperun/hihope-rzg2/MAINTAINERS   |  6 ++
 board/hoperun/hihope-rzg2/Makefile  |  9 +++
 board/hoperun/hihope-rzg2/hihope-rzg2.c | 91 +
 configs/hihope_rzg2_defconfig   | 79 +
 include/configs/hihope-rzg2.h   | 20 ++
 8 files changed, 235 insertions(+)
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a9d36e0e9c..dc4bc90019 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -802,6 +802,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
 
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
+   r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 0ef6cf619b..47ca4bfb2e 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -4,6 +4,8 @@ menu "Select Target SoC"
 
 config R8A774A1
bool "Renesas SoC R8A774A1"
+   imply CLK_R8A774A1
+   imply PINCTRL_PFC_R8A774A1
 
 config R8A774B1
bool "Renesas SoC R8A774B1"
@@ -89,6 +91,15 @@ config TARGET_EBISU
help
   Support for Renesas R-Car Gen3 Ebisu platform
 
+config TARGET_HIHOPE_RZG2
+   bool "HiHope RZ/G2 board"
+   imply R8A774A1
+   imply SYS_MALLOC_F
+   imply MULTI_DTB_FIT
+   imply MULTI_DTB_FIT_USER_DEFINED_AREA
+   help
+  Support for RZG2 HiHope platform
+
 config TARGET_SALVATOR_X
bool "Salvator-X board"
imply R8A7795
@@ -123,12 +134,15 @@ source "board/renesas/ebisu/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 source "board/beacon/beacon-rzg2m/Kconfig"
+source "board/hoperun/hihope-rzg2/Kconfig"
 
 config MULTI_DTB_FIT_UNCOMPRESS_SZ
+   default 0x8 if TARGET_HIHOPE_RZG2
default 0x8 if TARGET_SALVATOR_X
default 0x8 if TARGET_ULCB
 
 config MULTI_DTB_FIT_USER_DEF_ADDR
+   default 0x4900 if TARGET_HIHOPE_RZG2
default 0x4900 if TARGET_SALVATOR_X
default 0x4900 if TARGET_ULCB
 
diff --git a/board/hoperun/hihope-rzg2/Kconfig 
b/board/hoperun/hihope-rzg2/Kconfig
new file mode 100644
index 00..ee422ba6c8
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIHOPE_RZG2
+
+config SYS_SOC
+   default "rmobile"
+
+config SYS_BOARD
+   default "hihope-rzg2"
+
+config SYS_VENDOR
+   default "hoperun"
+
+config SYS_CONFIG_NAME
+   default "hihope-rzg2"
+
+endif
diff --git a/board/hoperun/hihope-rzg2/MAINTAINERS 
b/board/hoperun

[PATCH] arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.10

[Biju Das]

DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and
r8a774e1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817b6 ("Linux 5.10").

Signed-off-by: Biju Das 
---
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts |   20 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts |   27 +
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts|   41 +
 arch/arm/dts/r8a774e1-u-boot.dtsi |   59 +
 arch/arm/dts/r8a774e1.dtsi| 1342 -
 5 files changed, 1461 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi

diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 00..a0f98fd62c
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+"renesas,r8a774e1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
new file mode 100644
index 00..d7afb55d8b
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "r8a774e1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 00..e3a78c9c58
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+   compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@5 {
+   device_type = "memory";
+   reg = <0x5 0x 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi 
b/arch/arm/dts/r8a774e1-u-boot.dtsi
new file mode 100644
index 00..5fe432c3f7
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ _sound;
+/delete-node/ 
+/delete-node/ _card;
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+
+/ {
+   /delete-node/ hdmi

[PATCH] arm: dts: rmobile: r8a774a1: Synchronize DTs with Linux 5.10

[Biju Das]

DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817 ("Linux 5.10").

Signed-off-by: Biju Das 
---
 arch/arm/dts/hihope-common.dtsi   | 377 ++
 arch/arm/dts/hihope-rev4.dtsi | 124 ++
 arch/arm/dts/hihope-rzg2-ex.dtsi  |  92 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts |  21 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts |  27 ++
 arch/arm/dts/r8a774a1-hihope-rzg2m.dts|  37 ++
 arch/arm/dts/r8a774a1-u-boot.dtsi |  55 +++
 7 files changed, 733 insertions(+)
 create mode 100644 arch/arm/dts/hihope-common.dtsi
 create mode 100644 arch/arm/dts/hihope-rev4.dtsi
 create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
 create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi

diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
new file mode 100644
index 00..b1eb6a0802
--- /dev/null
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include 
+
+/ {
+   aliases {
+   serial0 = 
+   serial1 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel";
+   stdout-path = "serial0:115200n8";
+   };
+
+   hdmi0-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi0_con: endpoint {
+   remote-endpoint = <_dw_hdmi0_out>;
+   };
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   led1 {
+   gpios = < 12 GPIO_ACTIVE_HIGH>;
+   };
+
+   led2 {
+   gpios = < 13 GPIO_ACTIVE_HIGH>;
+   };
+
+   led3 {
+   gpios = <  0 GPIO_ACTIVE_HIGH>;
+   };
+
+   led4 {
+   gpios = < 11 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   reg_1p8v: regulator0 {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   reg_3p3v: regulator1 {
+   compatible = "regulator-fixed";
+   regulator-name = "fixed-3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   sound_card: sound {
+   compatible = "audio-graph-card";
+
+   label = "rcar-sound";
+
+   dais = <_port>;
+   };
+
+   vbus0_usb2: regulator-vbus0-usb2 {
+   compatible = "regulator-fixed";
+
+   regulator-name = "USB20_VBUS0";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+
+   gpio = < 16 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   vccq_sdhi0: regulator-vccq-sdhi0 {
+   compatible = "regulator-gpio";
+
+   regulator-name = "SDHI0 VccQ";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+
+   gpios = < 30 GPIO_ACTIVE_HIGH>;
+   gpios-states = <1>;
+   states = <330 1>, <180 0>;
+   };
+
+   x302_clk: x302-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <3300>;
+   };
+
+   x304_clk: x304-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2500>;
+   };
+};
+
+_clk_a {
+   clock-frequency = <22579200>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+_clk {
+   clock-frequency = <1666>;
+};
+
+_clk {
+   clock-frequency = <32768>;
+};
+
+ {
+   usb1-reset {
+

[PATCH] arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.10

[Biju Das]

DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have been imported from linux 5.10
commit 2c85ebc57b3e1817b6c ("Linux 5.10").

Signed-off-by: Biju Das 
---
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 21 
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts| 41 ++
 arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++
 4 files changed, 142 insertions(+)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi

diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 00..58812b41ac
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+"renesas,r8a774b1";
+};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 00..0bdc6909bf
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 00..b90790a95b
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+   compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi 
b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 00..6fab78e776
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ _sound;
+/delete-node/ 
+/delete-node/ _card;
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+
+/ {
+   /delete-node/ hdmi0-out;
+};
+
+/ {
+   soc {
+   /delete-node/ fdp1@fe94;
+   };
+};
-- 
2.17.1

[PATCH v9 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Biju Das]

Add SDHI quirks for R-Car H3 and RZ/G2H SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Jaehoon chung 
---
v9:
  * No Change.
v8:
  * Added Jaehoon chung's Rb tag.
v7:
  * No Change.
v6:
  * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 055fdbbc99..6b3cb02a3e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7795_calib_table,
+};
+
 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[]  = {
{ .soc_id = "r8a774b1",
  .data = _quirks_r8a77965
},
+   { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = _quirks_4tap
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
if (quirks == _quirks_r8a7796_es12 ||
quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
-   else if (quirks == _quirks_r8a7796_es13)
+   else if (quirks == _quirks_r8a7796_es13 ||
+quirks == _quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
 }
-- 
2.17.1

[PATCH v9 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N

[Biju Das]

Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Jaehoon chung 
---
v9:
 * No Change
v7->v8:
 * Added Jaehoon chung's Rb tag
v6->v7:
 * No Change. rebased on u-boot-sh/next
v6: 
 * New patch
---
 drivers/mmc/renesas-sdhi.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d17134d27b..055fdbbc99 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a77965_calib_table,
+};
+
 /*
  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
  * So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a774b1",
+ .data = _quirks_r8a77965
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a77965",
+ .data = _quirks_r8a77965
+   },
{ /* Sentinel. */ },
 };
 
@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
-   if (quirks == _quirks_r8a7796_es12)
+   if (quirks == _quirks_r8a7796_es12 ||
+   quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == _quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
-- 
2.17.1

[PATCH v9 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Jaehoon chung 
---
v9:
 * No Change.
v8:
 * Added Jaehoon Chung's Rb tag
v7:
 * Incorporated Jaehoon Chung's review comments.
 * Fixed the build error on Renesas ARM32 platforms.
v6:
 * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 117 +
 1 file changed, 117 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 24130e620b..d17134d27b 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "tmio-common.h"
 
@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct 
tmio_sd_priv *priv)
return clk_get_rate(>clk);
 }
 
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+   bool hs400_disabled;
+   bool hs400_4taps;
+   u32 hs400_bad_taps;
+   const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+   .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+   .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[]  = {
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+   struct tmio_sd_priv *priv,
+   const struct renesas_sdhi_quirks *quirks)
+{
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+   priv->nrtaps = 8;
+
+   if (!quirks)
+   return;
+
+   if (quirks->hs400_disabled) {
+   plat->cfg.host_caps &= ~MMC_MODE_HS400;
+   if (quirks == _quirks_4tap_nohs400_b17_dtrend)
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+   }
+
+   if (quirks->hs400_4taps)
+   priv->nrtaps = 4;
+
+   if (quirks->hs400_bad_taps)
+   priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+   if (quirks->hs400_calib_table) {
+   priv->adjust_hs400_enable = true;
+   priv->adjust_hs400_calib_table =
+   quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+   if (quirks == _quirks_r8a7796_es12)
+   priv->adjust_hs400_offset = 3;
+   else if (quirks == _quirks_r8a7796_es13)
+   priv->adjust_hs400_offset = 0;
+   }
+}
+#endif
+
 static void renesas_sdhi_filter_caps(struct udevice *dev)
 {
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_plat(dev);
+   const struct soc_attr *attr;
+
+   attr =

[PATCH v9 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.

RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).

As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v8-->v9
 * Fixed make file to use default family type function for SPL builds
   for both R-Car Gen{2,3} family's.
v7->v8
 * Optimized the cpu detection image size, when Renesas SoC identification
   driver is disabled for R-Car Gen2 SPL builds

with v8:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
330   0   0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
120   0   0 120  78 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

with v7:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
462   0   0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
154   0   0 154  9a 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

v6->v7
 * Seperated driver patch series from board support patches.
v5->v6
 * Optimized the unique CPU identification method by using Renesas SoC 
identification driver.
v4->v5
 * Add support for unique identification of RZ/G2 CPU types
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das...@bp.renesas.com/)
v3->v4
 * Dropped CPU info reporting logic for RZ/G2. Will address this later.
 * Added PRRID's for RZG2[HMNE]
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das...@bp.renesas.com/)

v2->v3  
 * Reworked as per Marek's suggestion
 * Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible 
string
 * Removed SoC family type Enum
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das...@bp.renesas.com/)

v1->v2:
 * Add comment's related to loop logic
   (ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das...@bp.renesas.com/)

v1:
 * New patch
  
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das...@bp.renesas.com/
---
 arch/arm/mach-rmobile/Makefile   |  5 ++
 arch/arm/mach-rmobile/cpu_info-rcar.c| 20 ++-
 arch/arm/mach-rmobile/cpu_info.c | 12 +++-
 arch/arm/mach-rmobile/include/mach/rmobile.h | 63 +++-
 arch/arm/mach-rmobile/soc_family-info.c  | 21 +++
 5 files changed, 100 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/soc_family-info.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 3206bce722..25636699f4 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -14,6 +14,11 @@ obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o 
pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
 
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_RCAR_GEN2) += soc_family-info.o
+obj-$(CONFIG_RCAR_GEN3) += soc_family-info.o
+endif
+
 OBJCOPYFLAGS_u-boot-spl.srec := -O srec
 quiet_cmd_objcopy = OBJCOPY $@
 cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c 
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..4483363f6b 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ * arch/arm/mach-rmobile/cpu_info-rcar.c
  *
- * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2021 Renesas Electronics Corporation
  */
 #include 
 #include 
@@ -12,6 +12,15 @@
 #define R8A7796_REV_1_10x5210
 #define R8A7796_REV_1_30x5211
 
+#if defined(CONFIG_SPL_BUILD)
+static bool __is_rzg_family(void)
+{
+ 

[PATCH v9 0/4] Add CPU identification support for RZ/G2 SoC's

[Biju Das]

This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.

This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=224764

v9:
 * Fixed make file to use default family type function for SPL builds
   for both R-Car Gen{2,3} family's.

v8:
 * Added Jaehoon Chung's Rb tag
 * Optimized the cpu detection image size, when Renesas SoC identification
   driver is disabled for R-Car Gen2 SPL builds

with v8:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
330   0   0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
120   0   0 120  78 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o


with v7:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
462   0   0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
154   0   0 154  9a 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

v7:
 * Incorporated Jaehoon Chung's review comments.
 * Fixed the build error on Renesas ARM32 platforms.
 * Seperated driver patch series from board support patches.
v6:
 * Optimized the unique CPU identification method by using Renesas SoC 
identification driver.
 * quirks using soc_device_match.

Biju Das (4):
  arm: rmobile: Add RZ/G2[HMNE] SoC support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
  mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

 arch/arm/mach-rmobile/Makefile   |   5 +
 arch/arm/mach-rmobile/cpu_info-rcar.c|  20 ++-
 arch/arm/mach-rmobile/cpu_info.c |  12 +-
 arch/arm/mach-rmobile/include/mach/rmobile.h |  63 ++--
 arch/arm/mach-rmobile/soc_family-info.c  |  21 +++
 drivers/mmc/renesas-sdhi.c   | 160 +++
 6 files changed, 260 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/soc_family-info.c

-- 
2.17.1

RE: [PATCH v8 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi All,

There is a typo in comments in original commit message. The correct values are 
as follows.

with v8:


$ size spl/arch/arm/mach-rmobile/cpu_info.o
text   data bss dec hex filename
330   0   0 330 14a 
spl/arch/arm/mach-rmobile/cpu_info.o
 
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 
spl/arch/arm/mach-rmobile/cpu_info.o
 
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text   data bss dec hex filename
120   0   0 120  78 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

with v7:

$ size spl/arch/arm/mach-rmobile/cpu_info.o
text   data bss dec hex filename
462   0   0 462 1ce 
spl/arch/arm/mach-rmobile/cpu_info.o

$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 
spl/arch/arm/mach-rmobile/cpu_info.o

$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text   data bss dec hex filename
154   0   0 154  9a 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

Regards,
Biju

> Subject: [PATCH v8 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some automotive
> peripherals.
> 
> RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
> RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
> RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
> RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
> 
> As the devices are the same they also have the same SoC PRR register
> values. SoC driver is used to distinguish the cpu type based on the
> family.
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Lad Prabhakar 
> ---
> v7->v8
>  * Optimized the cpu detection image size, when Renesas SoC identification
>driver is disabled for R-Car Gen2 SPL builds
> 
> with v8:
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info.o
>text  data bss dec hex filename
> 462 0   0 462 1ce
>   spl/arch/arm/mach-rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
>   -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-
> rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>   -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-
> rmobile/cpu_info-rcar.o
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>text  data bss dec hex filename
> 154 0   0 154  9a
>   spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> 
> with v7:
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info.o
>text  data bss dec hex filename
> 330 0   0 330 14a
>   spl/arch/arm/mach-rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
>   -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-
> rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>   -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-
> rmobile/cpu_info-rcar.o
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>text  data bss dec hex filename
> 120 0   0 120  78
>   spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> 
> v6->v7
>  * Seperated driver patch series from board support patches.
> v5->v6
>  * Optimized the unique CPU identification method by using Renesas SoC
> identification driver.
> v4->v5
>  * Add support for unique identification of RZ/G2 CPU types
>(Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201008085941.3600-1-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7Cf359d4ea30294c1866b008d8ba5e79d4%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637464262268730689%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=s2xAHTFxU
> JuB%2FQwRRMVoQ37EDOgqvZqceenB6v3RFp8%3Dreserved=0)
> v3->v4
>  * Dropped CPU info reporting logic for RZ/G2. Will address this later.
>  * Added PRRID's for RZG2[HMNE]
>(Ref:
> https://jpn01.safelinks.protection.outlook.

RE: [PATCH v8 0/4] Add CPU identification support for RZ/G2 SoC's

[Biju Das]

Hi All,

There is a typo in comments in original commit message. The correct values are 
as follows.

with v8:


$ size spl/arch/arm/mach-rmobile/cpu_info.o
text   data bss dec hex filename
330   0   0 330 14a 
spl/arch/arm/mach-rmobile/cpu_info.o
 
$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 
spl/arch/arm/mach-rmobile/cpu_info.o
 
$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text   data bss dec hex filename
120   0   0 120  78 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

with v7:

$ size spl/arch/arm/mach-rmobile/cpu_info.o
text   data bss dec hex filename
462   0   0 462 1ce 
spl/arch/arm/mach-rmobile/cpu_info.o

$ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 
spl/arch/arm/mach-rmobile/cpu_info.o

$ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

$ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
text   data bss dec hex filename
154   0   0 154  9a 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

Regards,
Biju

> -Original Message-
> From: Biju Das 
> Sent: 16 January 2021 20:37
> To: Nobuhiro Iwamatsu ; Marek Vasut
> 
> Cc: Biju Das ; Prabhakar Mahadev Lad
> ; Adam Ford ;
> Tom Rini ; Peng Fan ; u-
> b...@lists.denx.de; Chris Paterson 
> Subject: [PATCH v8 0/4] Add CPU identification support for RZ/G2 SoC's
> 
> This patch series aims to add CPU identification support for RZ/G2 SoC's
> and adding SDHI quirks using SoC identification driver.
> 
> This patch series depend on SoC identification driver[1] [1]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D224764data=04%7C0
> 1%7Cbiju.das.jz%40bp.renesas.com%7C1af7124c5afd4820c86a08d8ba5e786d%7C53d8
> 2571da1947e49cb4625a166a4a2a%7C0%7C0%7C637464262217814550%7CUnknown%7CTWFp
> bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> %7C1000sdata=bnuDAT37%2FWPaTtu226Z3NCTInny%2B3CIormHcdAwYWMo%3Dr
> eserved=0
> 
> v8:
>  * Added Jaehoon Chung's Rb tag
>  * Optimized the cpu detection image size, when Renesas SoC identification
>driver is disabled for R-Car Gen2 SPL builds
> 
> with v8:
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info.o
>text  data bss dec hex filename
> 462 0   0 462 1ce
>   spl/arch/arm/mach-rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
>   -rw-r--r-- 1 biju biju 9308 Jan 16 17:28 spl/arch/arm/mach-
> rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>   -rw-r--r-- 1 biju biju 6864 Jan 16 18:28 spl/arch/arm/mach-
> rmobile/cpu_info-rcar.o
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>text  data bss dec hex filename
> 154 0   0 154  9a
>   spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> 
> with v7:
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info.o
>text  data bss dec hex filename
> 330 0   0 330 14a
>   spl/arch/arm/mach-rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
>   -rw-r--r-- 1 biju biju 9176 Jan 16 18:10 spl/arch/arm/mach-
> rmobile/cpu_info.o
> 
>   $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>   -rw-r--r-- 1 biju biju 6244 Jan 16 18:30 spl/arch/arm/mach-
> rmobile/cpu_info-rcar.o
> 
>   $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o
>text  data bss dec hex filename
> 120 0   0 120  78
>   spl/arch/arm/mach-rmobile/cpu_info-rcar.o
> 
> v7:
>  * Incorporated Jaehoon Chung's review comments.
>  * Fixed the build error on Renesas ARM32 platforms.
>  * Seperated driver patch series from board support patches.
> v6:
>  * Optimized the unique CPU identification method by using Renesas SoC
> identification driver.
>  * quirks using soc_device_match.
> 
> Biju Das (4):
>   arm: rmobile: Add RZ/G2[HMNE] SoC support
>   mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
>   mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N a

[PATCH v8 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Biju Das]

Add SDHI quirks for R-Car H3 and RZ/G2H SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Jaehoon chung 
---
v8:
  * Added Jaehoon chung's Rb tag.
v7:
  * No Change.
v6:
  * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 055fdbbc99..6b3cb02a3e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7795_calib_table,
+};
+
 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[]  = {
{ .soc_id = "r8a774b1",
  .data = _quirks_r8a77965
},
+   { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = _quirks_4tap
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
if (quirks == _quirks_r8a7796_es12 ||
quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
-   else if (quirks == _quirks_r8a7796_es13)
+   else if (quirks == _quirks_r8a7796_es13 ||
+quirks == _quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
 }
-- 
2.17.1

[PATCH v8 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N

[Biju Das]

Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Jaehoon chung 
---
v7->v8:
 * Added Jaehoon chung's Rb tag
v6->v7:
 * No Change. rebased on u-boot-sh/next
v6: 
 * New patch
---
 drivers/mmc/renesas-sdhi.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d17134d27b..055fdbbc99 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a77965_calib_table,
+};
+
 /*
  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
  * So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a774b1",
+ .data = _quirks_r8a77965
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a77965",
+ .data = _quirks_r8a77965
+   },
{ /* Sentinel. */ },
 };
 
@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
-   if (quirks == _quirks_r8a7796_es12)
+   if (quirks == _quirks_r8a7796_es12 ||
+   quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == _quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
-- 
2.17.1

[PATCH v8 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Jaehoon chung 
---
v8:
 * Added Jaehoon Chung's Rb tag
v7:
 * Incorporated Jaehoon Chung's review comments.
 * Fixed the build error on Renesas ARM32 platforms.
v6:
 * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 117 +
 1 file changed, 117 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 24130e620b..d17134d27b 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "tmio-common.h"
 
@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct 
tmio_sd_priv *priv)
return clk_get_rate(>clk);
 }
 
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+   bool hs400_disabled;
+   bool hs400_4taps;
+   u32 hs400_bad_taps;
+   const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+   .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+   .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[]  = {
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+   struct tmio_sd_priv *priv,
+   const struct renesas_sdhi_quirks *quirks)
+{
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+   priv->nrtaps = 8;
+
+   if (!quirks)
+   return;
+
+   if (quirks->hs400_disabled) {
+   plat->cfg.host_caps &= ~MMC_MODE_HS400;
+   if (quirks == _quirks_4tap_nohs400_b17_dtrend)
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+   }
+
+   if (quirks->hs400_4taps)
+   priv->nrtaps = 4;
+
+   if (quirks->hs400_bad_taps)
+   priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+   if (quirks->hs400_calib_table) {
+   priv->adjust_hs400_enable = true;
+   priv->adjust_hs400_calib_table =
+   quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+   if (quirks == _quirks_r8a7796_es12)
+   priv->adjust_hs400_offset = 3;
+   else if (quirks == _quirks_r8a7796_es13)
+   priv->adjust_hs400_offset = 0;
+   }
+}
+#endif
+
 static void renesas_sdhi_filter_caps(struct udevice *dev)
 {
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_plat(dev);
+   const struct soc_attr *attr;
+
+   attr = soc_device_match(sdhi_quirks_match);

[PATCH v8 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.

RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).

As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v7->v8
 * Optimized the cpu detection image size, when Renesas SoC identification
   driver is disabled for R-Car Gen2 SPL builds

with v8:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
462   0   0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
154   0   0 154  9a 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

with v7:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
330   0   0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
120   0   0 120  78 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

v6->v7
 * Seperated driver patch series from board support patches.
v5->v6
 * Optimized the unique CPU identification method by using Renesas SoC 
identification driver.
v4->v5
 * Add support for unique identification of RZ/G2 CPU types
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das...@bp.renesas.com/)
v3->v4
 * Dropped CPU info reporting logic for RZ/G2. Will address this later.
 * Added PRRID's for RZG2[HMNE]
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das...@bp.renesas.com/)

v2->v3  
 * Reworked as per Marek's suggestion
 * Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible 
string
 * Removed SoC family type Enum
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das...@bp.renesas.com/)

v1->v2:
 * Add comment's related to loop logic
   (ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das...@bp.renesas.com/)

v1:
 * New patch
  
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das...@bp.renesas.com/
---
 arch/arm/mach-rmobile/Makefile   |  7 +++
 arch/arm/mach-rmobile/cpu_info-rcar.c| 20 ++-
 arch/arm/mach-rmobile/cpu_info.c | 12 +++-
 arch/arm/mach-rmobile/include/mach/rmobile.h | 63 +++-
 arch/arm/mach-rmobile/soc_family-info.c  | 21 +++
 5 files changed, 102 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/soc_family-info.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 3206bce722..305dee87e2 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,6 +13,13 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o 
pfc-sh73a0.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN3) += soc_family-info.o
+
+ifeq ($(CONFIG_RCAR_GEN2),y)
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += soc_family-info.o
+endif
+endif
 
 OBJCOPYFLAGS_u-boot-spl.srec := -O srec
 quiet_cmd_objcopy = OBJCOPY $@
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c 
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..7d162235d2 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ * arch/arm/mach-rmobile/cpu_info-rcar.c
  *
- * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2021 Renesas Electronics Corporation
  */
 #include 
 #include 
@@ -12,6 +12,15 @@
 #define R8A7796_REV_1_10x5210
 #define R8A7796_REV_1_30x5211
 
+#if defined(CONFIG_RCAR_GEN2) && defined(CONFIG_SPL_BUILD)
+static bool __is_rzg_family(void)
+{
+   return false;
+}
+bool is_rzg_family(void)
+ 

[PATCH v8 0/4] Add CPU identification support for RZ/G2 SoC's

[Biju Das]

This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.

This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=224764

v8:
 * Added Jaehoon Chung's Rb tag
 * Optimized the cpu detection image size, when Renesas SoC identification
   driver is disabled for R-Car Gen2 SPL builds

with v8:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
462   0   0 462 1ce spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9308 Jan 16 17:28 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6864 Jan 16 18:28 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
154   0   0 154  9a 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

with v7:

  $ size spl/arch/arm/mach-rmobile/cpu_info.o
   textdata bss dec hex filename
330   0   0 330 14a spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info.o
-rw-r--r-- 1 biju biju 9176 Jan 16 18:10 
spl/arch/arm/mach-rmobile/cpu_info.o

  $ ls -al spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
-rw-r--r-- 1 biju biju 6244 Jan 16 18:30 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

  $ size spl/arch/arm/mach-rmobile/cpu_info-rcar.o 
   textdata bss dec hex filename
120   0   0 120  78 
spl/arch/arm/mach-rmobile/cpu_info-rcar.o

v7:
 * Incorporated Jaehoon Chung's review comments.
 * Fixed the build error on Renesas ARM32 platforms.
 * Seperated driver patch series from board support patches.
v6:
 * Optimized the unique CPU identification method by using Renesas SoC 
identification driver.
 * quirks using soc_device_match.

Biju Das (4):
  arm: rmobile: Add RZ/G2[HMNE] SoC support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
  mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

 arch/arm/mach-rmobile/Makefile   |   7 +
 arch/arm/mach-rmobile/cpu_info-rcar.c|  20 ++-
 arch/arm/mach-rmobile/cpu_info.c |  12 +-
 arch/arm/mach-rmobile/include/mach/rmobile.h |  63 ++--
 arch/arm/mach-rmobile/soc_family-info.c  |  21 +++
 drivers/mmc/renesas-sdhi.c   | 160 +++
 6 files changed, 262 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/soc_family-info.c

-- 
2.17.1

[PATCH v5 3/3] dm: soc: SoC identification driver for Renesas SoC's

[Biju Das]

Add SoC identification driver for Renesas SoC's. This allows
to identify the SoC type and revision based on Product Register.

This can be checked where needed using soc_device_match().

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
This patch depend on [1]
 [1] 
http://u-boot.10912.n7.nabble.com/PATCH-v5-dm-core-Add-of-match-node-helper-function-tt437600.html

v4->v5
  * Rebased to master and changed "priv_auto_alloc_size" to "priv_auto"
  * Improved the spl image size, when Renesas SoC identification driver is 
disabled
  with v5 on Koelsch board:-
$ ls -al spl/u-boot-spl.bin 
  -rwxr-xr-x 1 biju biju 13916 Jan 16 14:19 spl/u-boot-spl.bin
$ size spl/u-boot-spl
 text  data bss dec hex filename
13785   1281100   150133aa5 spl/u-boot-spl
  with v4 on Koelsch board:
   $ ls -al spl/u-boot-spl.bin 
-rwxr-xr-x 1 biju biju 13996 Jan 16 14:16 spl/u-boot-spl.bin
   $ size spl/u-boot-spl
   textdata bss dec hex filename
  13789 2041100   150933af5 spl/u-boot-spl 

v3->v4:
 * Updated Copy right information from Linux.
 * Updated probe function, use the prr address from DT.
v2->v3: No Change.
v2: New patch
---
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   7 ++
 drivers/soc/soc_renesas.c | 244 ++
 3 files changed, 258 insertions(+)
 create mode 100644 drivers/soc/soc_renesas.c

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 864d00a885..475e94cd77 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -16,6 +16,13 @@ config SOC_DEVICE_TI_K3
  This allows Texas Instruments Keystone 3 SoCs to identify
  specifics about the SoC in use.
 
+config SOC_DEVICE_RENESAS
+   depends on SOC_DEVICE
+   bool "Enable SoC driver for Renesas SoCs"
+   help
+ This allows Renesas SoCs to identify specifics about the
+ SoC in use.
+
 source "drivers/soc/ti/Kconfig"
 
 endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 9ef20ca506..eea37a8d84 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -3,6 +3,13 @@
 # Makefile for the U-Boot SOC specific device drivers.
 
 obj-$(CONFIG_SOC_TI) += ti/
+ifeq ($(CONFIG_SOC_DEVICE_RENESAS),y)
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
+obj-$(CONFIG_SOC_DEVICE_RENESAS) += soc_renesas.o
+endif
+else
+obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
+endif
 obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
 obj-$(CONFIG_SANDBOX) += soc_sandbox.o
diff --git a/drivers/soc/soc_renesas.c b/drivers/soc/soc_renesas.c
new file mode 100644
index 00..f6813fc2fc
--- /dev/null
+++ b/drivers/soc/soc_renesas.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2016 Glider bvba
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct soc_renesas_priv {
+   const char *family;
+   const char *soc_id;
+   char revision[6];
+};
+
+struct renesas_family {
+   const char name[16];
+   u32 reg;/* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rcar_gen3 __maybe_unused = {
+   .name   = "R-Car Gen3",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rzg2 __maybe_unused = {
+   .name   = "RZ/G2",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+struct renesas_soc {
+   const struct renesas_family *family;
+   u8 id;
+};
+
+#ifdef CONFIG_R8A774A1
+static const struct renesas_soc soc_rz_g2m = {
+   .family = _rzg2,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A774B1
+static const struct renesas_soc soc_rz_g2n = {
+   .family = _rzg2,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A774C0
+static const struct renesas_soc soc_rz_g2e = {
+   .family = _rzg2,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A774E1
+static const struct renesas_soc soc_rz_g2h = {
+   .family = _rzg2,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7795
+static const struct renesas_soc soc_rcar_h3 = {
+   .family = _rcar_gen3,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7796
+static const struct renesas_soc soc_rcar_m3_w = {
+   .family = _rcar_gen3,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A77965
+static const struct renesas_soc soc_rcar_m3_n = {
+   .family = _rcar_gen3,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A77970
+static const struct renesas_soc soc_rcar_v3m = {
+   .family = _rcar_gen3,
+   .id = 0x54,
+};
+#endif
+
+#ifdef CONFIG_R8A77980
+static const struct renesas_soc soc_rcar_v3h = {
+   .family = _rcar_gen3,
+   .id = 0x56,
+};
+#endif
+
+#ifdef CONFIG_R8A77990
+static const struct 

[PATCH v5 2/3] dm: soc: Add SoC id for attribute matching

[Biju Das]

Mainline kernel uses the "soc_id" attribute to identify the SoC for some
of the h/w platforms. On such platforms adding this attribute in u-boot
will make SoC identification similar to the mainline kernel, so that it
can be easily maintained.

Add a new attribute named "soc_id" to SOC uclass, in order to allow device
drivers for identifying the SoC using SoC identification string and also
for matching this attribute for selecting SoC specific data.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Simon Glass 
---
v4->v5:
 * No change.

v3->v4:
 * Updated patch description
 * Added Simon's Rb tag.

v2->v3:
 * split the comments patch seperate.
 
Ref:https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-3-biju.das.jz@.../

v1->v2: Changed the comments from "a SoC" to "an SoC"
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201030140724.12773-1-biju.das.jz@.../
---
 drivers/soc/soc-uclass.c  | 19 ++-
 drivers/soc/soc_sandbox.c |  8 
 include/soc.h | 27 +++
 test/dm/soc.c |  8 
 4 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index c32d647864..a3f8be841b 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size)
return ops->get_revision(dev, buf, size);
 }
 
+int soc_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_ops *ops = soc_get_ops(dev);
+
+   if (!ops->get_soc_id)
+   return -ENOSYS;
+
+   return ops->get_soc_id(dev, buf, size);
+}
+
 const struct soc_attr *
 soc_device_match(const struct soc_attr *matches)
 {
@@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
 
while (1) {
if (!(matches->machine || matches->family ||
- matches->revision))
+ matches->revision || matches->soc_id))
break;
 
match = true;
@@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
}
}
 
+   if (matches->soc_id) {
+   if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
+   if (strcmp(matches->soc_id, str))
+   match = false;
+   }
+   }
+
if (match)
return matches;
 
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad84fc..1a81d3562a 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev, char 
*buf, int size)
return 0;
 }
 
+int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   snprintf(buf, size, "r8a774a1");
+
+   return 0;
+}
+
 static const struct soc_ops soc_sandbox_ops = {
.get_family = soc_sandbox_get_family,
.get_revision = soc_sandbox_get_revision,
.get_machine = soc_sandbox_get_machine,
+   .get_soc_id = soc_sandbox_get_soc_id,
 };
 
 int soc_sandbox_probe(struct udevice *dev)
diff --git a/include/soc.h b/include/soc.h
index 05058f9331..db0e8880d1 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -20,12 +20,14 @@
  *variants. Example: am33
  * @machine  - Name of a specific SoC. Example: am3352
  * @revision - Name of a specific SoC revision. Example: SR1.1
+ * @soc_id   - SoC identification string. Example: r8a774a1
  * @data - A pointer to user data for the SoC variant
  */
 struct soc_attr {
const char *family;
const char *machine;
const char *revision;
+   const char *soc_id;
const void *data;
 };
 
@@ -59,6 +61,16 @@ struct soc_ops {
 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
 */
int (*get_family)(struct udevice *dev, char *buf, int size);
+
+   /**
+* get_soc_id() - Get SoC identification name of an SoC
+*
+* @dev:Device to check (UCLASS_SOC)
+* @buf:Buffer to place string
+* @size:   Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+*/
+   int (*get_soc_id)(struct udevice *dev, char *buf, int size);
 };
 
 #define soc_get_ops(dev)((struct soc_ops *)(dev)->driver->ops)
@@ -105,6 +117,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size);
  */
 int soc_get_family(struct udevice *dev, char *buf, int size);
 
+/**
+ * soc_get_soc_id() - Get SoC identification name of an SoC
+ * @dev:   Device to check (UCLASS_SOC)
+ * @buf:   Buffer to place string
+ * @size:  Size of string space
+ *
+ * Return: 0 if OK, -ENOSPC 

[PATCH v5 1/3] soc: Fix comments from SOC to SoC

[Biju Das]

Fix the comments from "an SOC" to "an SoC".

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Simon Glass 
---
 v4->v5: No Change.

 v3->v4: No Change
 * Added Simon's Rb tag.

 v3:
 * New patch
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-3-biju.das.jz@.../)
---
 include/soc.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/soc.h b/include/soc.h
index a55eb1b572..05058f9331 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -31,7 +31,7 @@ struct soc_attr {
 
 struct soc_ops {
/**
-* get_machine() - Get machine name of an SOC
+* get_machine() - Get machine name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -41,7 +41,7 @@ struct soc_ops {
int (*get_machine)(struct udevice *dev, char *buf, int size);
 
/**
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -51,7 +51,7 @@ struct soc_ops {
int (*get_revision)(struct udevice *dev, char *buf, int size);
 
/**
-* get_family() - Get family name of an SOC
+* get_family() - Get family name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -76,7 +76,7 @@ struct soc_ops {
 int soc_get(struct udevice **devp);
 
 /**
- * soc_get_machine() - Get machine name of an SOC
+ * soc_get_machine() - Get machine name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
@@ -86,7 +86,7 @@ int soc_get(struct udevice **devp);
 int soc_get_machine(struct udevice *dev, char *buf, int size);
 
 /**
- * soc_get_revision() - Get revision name of an SOC
+ * soc_get_revision() - Get revision name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
@@ -96,7 +96,7 @@ int soc_get_machine(struct udevice *dev, char *buf, int size);
 int soc_get_revision(struct udevice *dev, char *buf, int size);
 
 /**
- * soc_get_family() - Get family name of an SOC
+ * soc_get_family() - Get family name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
-- 
2.17.1

[PATCH v5 0/3] Add Renesas SoC identification driver support

[Biju Das]

This patch series aims to support Renesas SoC identification driver.
Also added soc_id attribute support in UCLASS_SOC which is required for Renesas 
SoC
identification driver similar to mainline linux.

Patch 3 in this series depend on [1]

[1] 
http://u-boot.10912.n7.nabble.com/PATCH-v5-dm-core-Add-of-match-node-helper-function-tt437600.html

v4->v5
  * Rebased to master and changed "priv_auto_alloc_size" to "priv_auto"
  * Improved the spl image size, when Renesas SoC identification driver is 
disabled

  with v5 on Koelsch board:-
$ ls -al spl/u-boot-spl.bin 
  -rwxr-xr-x 1 biju biju 13916 Jan 16 14:19 spl/u-boot-spl.bin

$ size spl/u-boot-spl
 text  data bss dec hex filename
13785   1281100   150133aa5 spl/u-boot-spl

  with v4 on Koelsch board:

   $ ls -al spl/u-boot-spl.bin 
-rwxr-xr-x 1 biju biju 13996 Jan 16 14:16 spl/u-boot-spl.bin

   $ size spl/u-boot-spl
   textdata bss dec hex filename
  13789 2041100   150933af5 spl/u-boot-spl

v3->v4
  * Added Simon's Rb tag
  * Updated patch description for SoC identification using soc_id
  * Updated probe function of Renesas SoC identification driver.

Biju Das (3):
  soc: Fix comments from SOC to SoC
  dm: soc: Add SoC id for attribute matching
  dm: soc: SoC identification driver for Renesas SoC's

 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   7 ++
 drivers/soc/soc-uclass.c  |  19 ++-
 drivers/soc/soc_renesas.c | 244 ++
 drivers/soc/soc_sandbox.c |   8 ++
 include/soc.h |  39 +-
 test/dm/soc.c |   8 ++
 7 files changed, 325 insertions(+), 7 deletions(-)
 create mode 100644 drivers/soc/soc_renesas.c

-- 
2.17.1

RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

> -Original Message-
> From: Biju Das
> Sent: 15 January 2021 10:02
> To: Marek Vasut ; Nobuhiro Iwamatsu
> 
> Cc: Prabhakar Mahadev Lad ; u-
> b...@lists.denx.de; Chris Paterson ; Simon
> Glass ; Tom Rini 
> Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> Hi,
> 
> > Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> >
> > >
> > > > diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > index 5bde24ae0e..08345503a2 100644
> > > > --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > @@ -6,6 +6,7 @@
> > > >*/
> > > >   #include 
> > > >   #include 
> > > > +#include 
> > > >
> > > >   #define PRR_MASK  0x7fff
> > > >   #define R8A7796_REV_1_0   0x5200
> > > > @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
> > > >   #endif
> > > >   }
> > > >
> > > > +static bool is_rzg_family(void)
> > > > +{
> > > > +   bool rzg_family_type = false;
> > > > +   struct udevice *soc;
> > > > +   char name[16];
> > > > +
> > > > +   if (!(soc_get() || soc_get_family(soc, name, 16))) {
> > >
> > > This depends on some other patchset, right ?
> > > I will wait for that to land and then apply this one.
> >
> > Yes, Simon have reviewed this patches and not sure who needs to pick
> > this up. So I have sent a gentle remainder for picking this patches
> > [1] [1]
> > http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-
> > identification-driver-support-tt432936.html
> >
> > >
> > > Did you check that this is still OK on RCar Gen2 with its
> > > size-limited SPL?

Good catch. I have built spl image for koelsch and I see there is a change in 
Size of SPL with and without soc identification driver + SoC uclass driver 
included

With SoC identification driver +  SoC uclass driver included
---

$ ls -al spl/u-boot-spl.bin 
-rwxr-xr-x 1 biju biju 13996 Jan 16 14:16 spl/u-boot-spl.bin
$ size spl/u-boot-spl
   textdata bss dec hex filename
  13789 2041100   150933af5 spl/u-boot-spl

Without SoC identification driver + SoC uclass driver
-
$ ls -al spl/u-boot-spl.bin 
  -rwxr-xr-x 1 biju biju 13916 Jan 16 14:19 spl/u-boot-spl.bin
size spl/u-boot-spl
 text  data bss dec hex filename
13785   1281100   150133aa5 spl/u-boot-spl

I will post V5 with Renesas soc identification driver disabled for SPL builds 
along with SoC uclass driver.

Regards,
Biju

[PATCH v5] dm: core: Add of_match_node helper function

[Biju Das]

Add of_match_node() helper function to iterate over the device tree
and tell if a device_node has a matching of_match structure.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Simon Glass 
---
v4->v5:
 * Rebased to latest master
v3->v4: No change
 * Added Simon's Rb tag.
v2->v3:
 * Added a test case for of_match_node helper function.
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-2-biju.das...@bp.renesas.com/)
v1->v2:
 * No Change
v1:
 * New Patch
---
 drivers/core/device.c | 21 +
 include/dm/device.h   | 13 +
 test/dm/core.c| 31 +++
 3 files changed, 65 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index aeab3836ed..4ff708fd38 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -1022,6 +1022,27 @@ bool of_machine_is_compatible(const char *compat)
return !fdt_node_check_compatible(fdt, 0, compat);
 }
 
+static
+const struct udevice_id *__of_match_node(const struct udevice_id *matches,
+const ofnode node)
+{
+   if (!matches)
+   return NULL;
+
+   for (; matches->compatible; matches++) {
+   if (ofnode_device_is_compatible(node, matches->compatible))
+   return matches;
+   }
+
+   return NULL;
+}
+
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node)
+{
+   return __of_match_node(matches, node);
+}
+
 int dev_disable_by_path(const char *path)
 {
struct uclass *uc;
diff --git a/include/dm/device.h b/include/dm/device.h
index f5b4cd6876..950fc78184 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -802,6 +802,19 @@ bool device_is_compatible(const struct udevice *dev, const 
char *compat);
  */
 bool of_machine_is_compatible(const char *compat);
 
+/**
+ * of_match_node() - Tell if a device_node has a matching of_match structure
+ *
+ *
+ * Low level utility function used by device matching.
+ *
+ * @matches:   array of of device match structures to search in
+ * @node:  the of device structure to match against
+ * @return matching structure on success, NULL if the match is not found
+ */
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node);
+
 /**
  * dev_disable_by_path() - Disable a device given its device tree path
  *
diff --git a/test/dm/core.c b/test/dm/core.c
index 1f5ca570dc..aae4d8427d 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1067,6 +1068,36 @@ static int dm_test_inactive_child(struct unit_test_state 
*uts)
 }
 DM_TEST(dm_test_inactive_child, UT_TESTF_SCAN_PDATA);
 
+static int dm_test_of_match_node(struct unit_test_state *uts)
+{
+   const ulong test_data_expected = 0x1234;
+   ofnode root_node = ofnode_path("/");
+   const struct udevice_id *match;
+   unsigned long match_data;
+
+   const struct udevice_id soc_device_ids[] = {
+   { .compatible = "sandbox", .data = test_data_expected, },
+   { /* sentinel */ }
+   };
+
+   const struct udevice_id soc_device_nomatch_ids[] = {
+   { .compatible = "sandbox123", .data = test_data_expected, },
+   { /* sentinel */ }
+   };
+
+   match = of_match_node(soc_device_ids, root_node);
+   ut_assert(match);
+
+   match_data = match->data;
+   ut_asserteq(match_data, test_data_expected);
+
+   match = of_match_node(soc_device_nomatch_ids, root_node);
+   ut_asserteq_ptr(match, NULL);
+
+   return 0;
+}
+DM_TEST(dm_test_of_match_node, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
 /* Make sure all bound devices have a sequence number */
 static int dm_test_all_have_seq(struct unit_test_state *uts)
 {
-- 
2.17.1

RE: [PATCH v4 0/4] Add Renesas SoC identification driver support

[Biju Das]

Hi All,

Just found that some of the patches in this series doesn't apply cleanly on 
mainline.
Will rebase and post new patch series.

Regards,
Biju

> -Original Message-
> From: Biju Das
> Sent: 15 January 2021 09:54
> To: Adam Ford ; Simon Glass ; Marek
> Vasut ; Tom Rini 
> Cc: Dave Gerlach ; Prabhakar Mahadev Lad
> ; u-boot@lists.denx.de; Nobuhiro
> Iwamatsu ; Chris Paterson
> 
> Subject: RE: [PATCH v4 0/4] Add Renesas SoC identification driver support
> 
> Hi All,
> 
> Gentle ping.
> 
> Can we merge this patch? If you are happy, otherwise please let meknow.
> 
> Thanks and regards,
> Biju
> 
> > -Original Message-----
> > From: Adam Ford 
> > Sent: 11 December 2020 20:25
> > To: Biju Das 
> > Cc: Simon Glass ; Marek Vasut
> > ; Tom Rini ; Dave
> > Gerlach ; Prabhakar Mahadev Lad  > lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu
> > ; Chris Paterson 
> > Subject: Re: [PATCH v4 0/4] Add Renesas SoC identification driver
> > support
> >
> > On Mon, Nov 30, 2020 at 3:18 AM Biju Das 
> > wrote:
> > >
> > > Hi All,
> > >
> > > Gentle Ping. Please let me know, are we happy with this patch series?
> > >
> >
> > I have a series pending this as well.
> >
> > thank you,
> >
> > adam
> > > The patch series[1] is blocked by this.
> > > [1]
> > > https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fu-b
> > > oo
> > > t.10912.n7.nabble.com%2FPATCH-v7-0-4-Add-CPU-identification-support-
> > > fo
> > > r-RZ-G2-SoC-s-tt433694.html%23a433807data=04%7C01%7Cbiju.das.jz
> > > %4
> > > 0bp.renesas.com%7Cd041fb395d834b5281f208d89e12e15f%7C53d82571da1947e
> > > 49
> > > cb4625a166a4a2a%7C0%7C1%7C637433151226342691%7CUnknown%7CTWFpbGZsb3d
> > > 8e
> > > yJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> > > 30
> > > 00sdata=kXysig8DF8cNkoHn7kRC2Zphcgj3RyOCcWYstRavbSA%3Drese
> > > rv
> > > ed=0
> > >
> > > Cheers,
> > > Biju
> > >
> > > > -Original Message-
> > > > From: Biju Das 
> > > > Sent: 16 November 2020 13:04
> > > > To: Simon Glass ; Marek Vasut
> > > > 
> > > > Cc: Biju Das ; Dave Gerlach  > > > gerl...@ti.com>; Prabhakar Mahadev Lad  > > > lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu
> > > > ; Chris Paterson
> > > > 
> > > > Subject: [PATCH v4 0/4] Add Renesas SoC identification driver
> > > > support
> > > >
> > > > This patch series aims to support Renesas SoC identification driver.
> > > >
> > > > Added a helper function of_match_node to find the matching
> > > > of_match structure. This helper function can be used to replace
> > > > the following code in u-boot [1] and [2]
> > > >
> > > > [1]
> > > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > > el
> > > > ixir.b
> > > > ootlin.com%2Fu-
> > > > boot%2Flatest%2Fsource%2Fdrivers%2Fserial%2Fserial_uniphier.c%23L1
> > > > 29
> > > > d
> > > > ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c40
> > > > 8d
> > > > 88a306
> > > > 996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63741128782099926
> > > > 4%
> > > > 7CUnkn
> > > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1h
> > > > aW
> > > > wiLCJX
> > > > VCI6Mn0%3D%7C1000sdata=YmZ52jZrOQqXhvbflvy5XWnXsfb7FIRgxpY1Xh
> > > > BI
> > > > 6YE%3D
> > > > reserved=0
> > > > [2]
> > > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > > el
> > > > ixir.b
> > > > ootlin.com%2Fu-
> > > > boot%2Flatest%2Fsource%2Fdrivers%2Fusb%2Fphy%2Frockchip_usb2_phy.c
> > > > %2
> > > > 3L77
> > > > mp;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb
> > > > 3c
> > > > 408d88
> > > > a306996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6374112878209
> > > > 99
> > > > 264%7C
> > > > Unknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> > > > Ik
> > > > 1haWwi
> > > > LCJXVCI6Mn0%3D%7C1000sdata=N2wF3aZNCkN7TQlA%2FbhV3ggDjZdYVjjS
> > > &

RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi,

> Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> >
> > > diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > index 5bde24ae0e..08345503a2 100644
> > > --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > @@ -6,6 +6,7 @@
> > >*/
> > >   #include 
> > >   #include 
> > > +#include 
> > >
> > >   #define PRR_MASK0x7fff
> > >   #define R8A7796_REV_1_0 0x5200
> > > @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
> > >   #endif
> > >   }
> > >
> > > +static bool is_rzg_family(void)
> > > +{
> > > + bool rzg_family_type = false;
> > > + struct udevice *soc;
> > > + char name[16];
> > > +
> > > + if (!(soc_get() || soc_get_family(soc, name, 16))) {
> >
> > This depends on some other patchset, right ?
> > I will wait for that to land and then apply this one.
> 
> Yes, Simon have reviewed this patches and not sure who needs to pick this
> up. So I have sent a gentle remainder for picking this patches [1] [1]
> http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-
> identification-driver-support-tt432936.html
> 
> >
> > Did you check that this is still OK on RCar Gen2 with its size-limited
> > SPL?
> 
> Unfortunately I do not have access currently to RCar Gen2 boards.
> 

Because of lock down, Still I don't have access to R-Car Gen2 boards.

As you said, R-Car Gen2 SPL has constraint on image size,
Can we make a decision, we won't enable SoC identification driver on R-Car Gen2 
SPL?

Regards,
Biju

RE: [PATCH v4 0/4] Add Renesas SoC identification driver support

[Biju Das]

Hi All,

Gentle ping. 

Can we merge this patch? If you are happy, otherwise please let meknow.

Thanks and regards,
Biju

> -Original Message-
> From: Adam Ford 
> Sent: 11 December 2020 20:25
> To: Biju Das 
> Cc: Simon Glass ; Marek Vasut
> ; Tom Rini ; Dave
> Gerlach ; Prabhakar Mahadev Lad  lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu
> ; Chris Paterson 
> Subject: Re: [PATCH v4 0/4] Add Renesas SoC identification driver support
> 
> On Mon, Nov 30, 2020 at 3:18 AM Biju Das 
> wrote:
> >
> > Hi All,
> >
> > Gentle Ping. Please let me know, are we happy with this patch series?
> >
> 
> I have a series pending this as well.
> 
> thank you,
> 
> adam
> > The patch series[1] is blocked by this.
> > [1]
> > https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fu-boo
> > t.10912.n7.nabble.com%2FPATCH-v7-0-4-Add-CPU-identification-support-fo
> > r-RZ-G2-SoC-s-tt433694.html%23a433807data=04%7C01%7Cbiju.das.jz%4
> > 0bp.renesas.com%7Cd041fb395d834b5281f208d89e12e15f%7C53d82571da1947e49
> > cb4625a166a4a2a%7C0%7C1%7C637433151226342691%7CUnknown%7CTWFpbGZsb3d8e
> > yJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C30
> > 00sdata=kXysig8DF8cNkoHn7kRC2Zphcgj3RyOCcWYstRavbSA%3Dreserv
> > ed=0
> >
> > Cheers,
> > Biju
> >
> > > -Original Message-
> > > From: Biju Das 
> > > Sent: 16 November 2020 13:04
> > > To: Simon Glass ; Marek Vasut
> > > 
> > > Cc: Biju Das ; Dave Gerlach  > > gerl...@ti.com>; Prabhakar Mahadev Lad  > > lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu
> > > ; Chris Paterson 
> > > Subject: [PATCH v4 0/4] Add Renesas SoC identification driver
> > > support
> > >
> > > This patch series aims to support Renesas SoC identification driver.
> > >
> > > Added a helper function of_match_node to find the matching of_match
> > > structure. This helper function can be used to replace the following
> > > code in u-boot [1] and [2]
> > >
> > > [1]
> > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fel
> > > ixir.b
> > > ootlin.com%2Fu-
> > > boot%2Flatest%2Fsource%2Fdrivers%2Fserial%2Fserial_uniphier.c%23L129
> > > d
> > > ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c408d
> > > 88a306
> > > 996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637411287820999264%
> > > 7CUnkn
> > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > > wiLCJX
> > > VCI6Mn0%3D%7C1000sdata=YmZ52jZrOQqXhvbflvy5XWnXsfb7FIRgxpY1XhBI
> > > 6YE%3D
> > > reserved=0
> > > [2]
> > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fel
> > > ixir.b
> > > ootlin.com%2Fu-
> > > boot%2Flatest%2Fsource%2Fdrivers%2Fusb%2Fphy%2Frockchip_usb2_phy.c%2
> > > 3L77
> > > mp;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c
> > > 408d88
> > > a306996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637411287820999
> > > 264%7C
> > > Unknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > 1haWwi
> > > LCJXVCI6Mn0%3D%7C1000sdata=N2wF3aZNCkN7TQlA%2FbhV3ggDjZdYVjjS%2
> > > F0tOFf
> > > j%2BkOE%3Dreserved=0
> > >
> > > Also added soc_id attribute support in UCLASS_SOC which is required
> > > for Renesas SoC identification driver similar to mainline linux.
> > >
> > > v3->v4
> > >   * Added Simon's Rb tag
> > >   * Updated patch description for SoC identification using soc_id
> > >   * Updated probe function of Renesas SoC identification driver.
> > >
> > > Biju Das (4):
> > >   dm: core: Add of_match_node helper function
> > >   soc: Fix comments from SOC to SoC
> > >   dm: soc: Add SoC id for attribute matching
> > >   dm: soc: SoC identification driver for Renesas SoC's
> > >
> > >  drivers/core/device.c |  21 
> > >  drivers/soc/Kconfig   |   7 ++
> > >  drivers/soc/Makefile  |   1 +
> > >  drivers/soc/soc-uclass.c  |  19 ++-  drivers/soc/soc_renesas.c |
> > > 244 ++
> > >  drivers/soc/soc_sandbox.c |   8 ++
> > >  include/dm/device.h   |  13 ++
> > >  include/soc.h |  39 +-
> > >  test/dm/core.c|  31 +
> > >  test/dm/soc.c |   8 ++
> > >  10 files changed, 384 insertions(+), 7 deletions(-)  create mode
> > > 100644 drivers/soc/soc_renesas.c
> > >
> > > --
> > > 2.17.1
> >

RE: [PATCH] spi: renesas_rpc_spi: Fix fallback compatibility string

[Biju Das]

Hi Adam,

Thanks for the reply.

> -Original Message-
> Subject: Re: [PATCH] spi: renesas_rpc_spi: Fix fallback compatibility
> string
> 
> On Tue, Jan 5, 2021 at 6:08 AM Biju Das 
> wrote:
> >
> > Hi Adam,
> >
> > Thanks for the patch.
> >
> > > -Original Message-
> > > From: Adam Ford 
> > > Sent: 04 January 2021 17:38
> > > To: u-boot@lists.denx.de
> > > Cc: ja...@amarulasolutions.com; Biju Das
> > > ; Adam Ford 
> > > Subject: [PATCH] spi: renesas_rpc_spi: Fix fallback compatibility
> > > string
> > >
> > > A generic compatibility string was added, but it doesn't match the
> > > name used by Linux or the device tree bindings from any of the SoC's.
> > > Fix it to read "renesas,rcar-gen3-rpc-if"
> >
> > The framework used in Linux and u-boot are different. On Linux there is
> Core RPC-IF driver which has the above compatible string, with support for
> both spi flash and hyperflash support.
> 
> Does the hyperflash have a separate .compatible entry?

Core driver [1] and documentation[2] is  here
[1]https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/memory/renesas-rpc-if.c?h=next-20210113
[2]https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml?h=next-20210113

As per [2], hyperflash uses same compatible string and there is no compatible 
stuff defined in hyperflash driver[3]
[3] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/mtd/hyperbus/rpc-if.c?h=next-20210113

> 
> > Where as in u-boot, it is supporting only rpc spi flash. Since the
> driver is not supporting hyperflash in u-boot, may be we could reuse
> "renesas,rcar-gen3-rpc-if" just for rpc spi flash.

Sorry , just found that U-boot have hyperflash support[4] and it uses 
compatible string "renesas,rpc".
[4] 
https://elixir.bootlin.com/u-boot/v2021.01-rc5/source/drivers/mtd/renesas_rpc_hf.c

Thanks,
Biju


> >
> > >
> > > Fixes: 2f220c639a2a ("spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2
> > > fallback compatibility string")
> > > Signed-off-by: Adam Ford 
> > >
> > > diff --git a/drivers/spi/renesas_rpc_spi.c
> > > b/drivers/spi/renesas_rpc_spi.c index d0ff918af8..0724a03a34 100644
> > > --- a/drivers/spi/renesas_rpc_spi.c
> > > +++ b/drivers/spi/renesas_rpc_spi.c
> > > @@ -454,7 +454,7 @@ static const struct udevice_id rpc_spi_ids[] = {
> > >   { .compatible = "renesas,rpc-r8a77965" },
> > >   { .compatible = "renesas,rpc-r8a77970" },
> > >   { .compatible = "renesas,rpc-r8a77995" },
> > > - { .compatible = "renesas,rcar-gen3-rpc" },
> > > + { .compatible = "renesas,rcar-gen3-rpc-if" },
> > >   { }
> > >  };
> > >
> > > --
> > > 2.25.1
> >

RE: [PATCH] spi: renesas_rpc_spi: Fix fallback compatibility string

[Biju Das]

Hi Adam,

Thanks for the patch.

> -Original Message-
> From: Adam Ford 
> Sent: 04 January 2021 17:38
> To: u-boot@lists.denx.de
> Cc: ja...@amarulasolutions.com; Biju Das ;
> Adam Ford 
> Subject: [PATCH] spi: renesas_rpc_spi: Fix fallback compatibility string
> 
> A generic compatibility string was added, but it doesn't match the name
> used by Linux or the device tree bindings from any of the SoC's.
> Fix it to read "renesas,rcar-gen3-rpc-if"

The framework used in Linux and u-boot are different. On Linux there is Core 
RPC-IF driver which has the above compatible string, with support for both spi 
flash and hyperflash support.

Where as in u-boot, it is supporting only rpc spi flash. Since the driver is 
not supporting hyperflash in u-boot, may be we could reuse 
"renesas,rcar-gen3-rpc-if" just for rpc spi flash.

Marek, What do you think?

Cheers,
Biju

> 
> Fixes: 2f220c639a2a ("spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2
> fallback compatibility string")
> Signed-off-by: Adam Ford 
> 
> diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
> index d0ff918af8..0724a03a34 100644
> --- a/drivers/spi/renesas_rpc_spi.c
> +++ b/drivers/spi/renesas_rpc_spi.c
> @@ -454,7 +454,7 @@ static const struct udevice_id rpc_spi_ids[] = {
>   { .compatible = "renesas,rpc-r8a77965" },
>   { .compatible = "renesas,rpc-r8a77970" },
>   { .compatible = "renesas,rpc-r8a77995" },
> - { .compatible = "renesas,rcar-gen3-rpc" },
> + { .compatible = "renesas,rcar-gen3-rpc-if" },
>   { }
>  };
> 
> --
> 2.25.1

RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

Thanks for the reply.

> Subject: Re: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> On 11/27/20 3:52 PM, Biju Das wrote:
> 
> Sorry for the late reply.
> 
> [...]
> 
> > diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > index 5bde24ae0e..08345503a2 100644
> > --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > @@ -6,6 +6,7 @@
> >*/
> >   #include 
> >   #include 
> > +#include 
> >
> >   #define PRR_MASK  0x7fff
> >   #define R8A7796_REV_1_0   0x5200
> > @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
> >   #endif
> >   }
> >
> > +static bool is_rzg_family(void)
> > +{
> > +   bool rzg_family_type = false;
> > +   struct udevice *soc;
> > +   char name[16];
> > +
> > +   if (!(soc_get() || soc_get_family(soc, name, 16))) {
> 
> This depends on some other patchset, right ?
> I will wait for that to land and then apply this one.

Yes, Simon have reviewed this patches and not sure who needs to pick this up. 
So I have sent a gentle remainder for picking this patches [1]
[1] 
http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-identification-driver-support-tt432936.html

> 
> Did you check that this is still OK on RCar Gen2 with its size-limited
> SPL?

Unfortunately I do not have access currently to RCar Gen2 boards. 

Shall we enable "is_rzg_family" as a weekfunction and override it for RCar 
Gen3? or it will be grateful, please could you test this on RCar Gen2 boards, 
if you have any?

Please let us know.


> Also, do you have a git tree with all the remaining patches applied on
> top? It would be useful to get an overview what's still pending for
> mainline.

We have an internal private u-boot repository, where we run mainline u-boot CI 
job as part of patch submission.

Regarding status wise, all the patches required for boot RZ/G2[HMN] boards are 
submitted to mainline and is in review state.

For RZ/G2E, some patches are pending because of the dependency with RZ/G2[HMN]. 
We created a public repo[1] to get an overview what is still pending for  
mainline.

[1] https://github.com/prabhakarlad/u-boot-rzg2

Regards,
Biju

> 
> Thanks
> 
> > +   if (!strcmp(name, "RZ/G2"))
> > +   rzg_family_type = true;
> > +   }
> 
> [...]

RE: [PATCH v4 0/4] Add Renesas SoC identification driver support

[Biju Das]

Hi All,

Gentle Ping. Please let me know, are we happy with this patch series?

The patch series[1] is blocked by this.
[1] 
http://u-boot.10912.n7.nabble.com/PATCH-v7-0-4-Add-CPU-identification-support-for-RZ-G2-SoC-s-tt433694.html#a433807

Cheers,
Biju

> -Original Message-
> From: Biju Das 
> Sent: 16 November 2020 13:04
> To: Simon Glass ; Marek Vasut
> 
> Cc: Biju Das ; Dave Gerlach  gerl...@ti.com>; Prabhakar Mahadev Lad  lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu
> ; Chris Paterson 
> Subject: [PATCH v4 0/4] Add Renesas SoC identification driver support
> 
> This patch series aims to support Renesas SoC identification driver.
> 
> Added a helper function of_match_node to find the matching of_match
> structure. This helper function can be used to replace the following code
> in u-boot [1] and [2]
> 
> [1]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.b
> ootlin.com%2Fu-
> boot%2Flatest%2Fsource%2Fdrivers%2Fserial%2Fserial_uniphier.c%23L129d
> ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c408d88a306
> 996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637411287820999264%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> VCI6Mn0%3D%7C1000sdata=YmZ52jZrOQqXhvbflvy5XWnXsfb7FIRgxpY1XhBI6YE%3D
> reserved=0
> [2]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.b
> ootlin.com%2Fu-
> boot%2Flatest%2Fsource%2Fdrivers%2Fusb%2Fphy%2Frockchip_usb2_phy.c%23L77
> mp;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c408d88
> a306996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637411287820999264%7C
> Unknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> LCJXVCI6Mn0%3D%7C1000sdata=N2wF3aZNCkN7TQlA%2FbhV3ggDjZdYVjjS%2F0tOFf
> j%2BkOE%3Dreserved=0
> 
> Also added soc_id attribute support in UCLASS_SOC which is required for
> Renesas SoC identification driver similar to mainline linux.
> 
> v3->v4
>   * Added Simon's Rb tag
>   * Updated patch description for SoC identification using soc_id
>   * Updated probe function of Renesas SoC identification driver.
> 
> Biju Das (4):
>   dm: core: Add of_match_node helper function
>   soc: Fix comments from SOC to SoC
>   dm: soc: Add SoC id for attribute matching
>   dm: soc: SoC identification driver for Renesas SoC's
> 
>  drivers/core/device.c |  21 
>  drivers/soc/Kconfig   |   7 ++
>  drivers/soc/Makefile  |   1 +
>  drivers/soc/soc-uclass.c  |  19 ++-
>  drivers/soc/soc_renesas.c | 244 ++
>  drivers/soc/soc_sandbox.c |   8 ++
>  include/dm/device.h   |  13 ++
>  include/soc.h |  39 +-
>  test/dm/core.c|  31 +
>  test/dm/soc.c |   8 ++
>  10 files changed, 384 insertions(+), 7 deletions(-)  create mode 100644
> drivers/soc/soc_renesas.c
> 
> --
> 2.17.1

RE: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

> -Original Message-
> From: Marek Vasut 
> Sent: 04 November 2020 19:24
> To: Biju Das ; Nobuhiro Iwamatsu
> 
> Cc: u-boot@lists.denx.de; Chris Paterson ;
> Prabhakar Mahadev Lad 
> Subject: Re: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> On 11/3/20 11:06 AM, Biju Das wrote:
> > Hi Marek,
> 
> Hi,
> 
> [...]
> 
> >>> On the next version, I will send Renesas SoC identification driver,
> >>> which supports caching family type which can be used to provide
> >>> unique
> >> identification for CPU type.
> >>
> >> Please make sure to check it on RCar2 as well, those use SPL and the
> >> SPL size is quite limited.
> >
> > Currently SoC identification driver is enabled only for RZ/G2 boards and
> support is added to both R-Car Gen3 and RZ/G2 devices.
> >
> > For the disabled case, the UCLASS-SOC class functions are inlined to
> "NULL"  for soc_device_match and rest of the api's it is "-ENOSYS".
> >
> > I agree, in future we need to add support for RCar2 as well, since we
> are going to add u-boot support for RZ/G1 devices.
> > Please find the size details related to R-Car Gen2(by adding support for
> R-Car M2-W and RZ/G1M SoC).
> >
> > There is increase of 944 bytes, for R-Car Gen2 device, if we enable
> Renesas SoC identification driver for Gen2 devices.
> >
> > Current u-boot-sh/master
> > ---
> > $ ls -al u-boot.bin
> > -rw-r--r-- 1 biju biju 523001 Nov  3 09:16 u-boot.bin
> >
> > Current u-boot-sh/master + SoC renesas driver (R-Car M2-W enabled only
> > case)
> > --
> > --
> > $ ls -al u-boot.bin
> > -rw-r--r-- 1 biju biju 523945 Nov  3 09:47 u-boot.bin
> >
> > If you agree, we will add support for Gen2 to SoC identification driver
> later. Currently there is no users for using it.
> > Please let me know.
> 
> The problem on Gen2 isn't the size of u-boot.bin , but of spl/u-boot-
> spl.bin . That one is severely limited and I don't think it's realistic to
> add any sort of SoC identification driver into it. In fact, I think even
> the DM is somehow reduced in there.

If you see the make file , soc identification driver is disabled for spl/u-boot.

obj-$(CONFIG_$(SPL_)SOC_DEVICE_RENESAS) += soc_renesas.o

So I think we are having same understanding not to add soc identification 
driver for spl/uboot.
Please let me know, if you think other wise.

Regards,
Biju

[PATCH v7 4/4] arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.10.rc5

[Biju Das]

Synchronize RZ/G2H SoC DTs and HiHope board DTs files with mainline
Linux 5.10-rc5 commit 418baf2c28f34 ("Linux 5.10-rc5")

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v7:
 * New patch
---
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts |5 +
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts|   15 +
 arch/arm/dts/r8a774e1-u-boot.dtsi |   34 +
 arch/arm/dts/r8a774e1.dtsi| 1340 -
 4 files changed, 1367 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
index 265355e0de..8129959398 100644
--- a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -13,3 +13,8 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
 "renesas,r8a774e1";
 };
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
index cdbe527e93..9525d5ed6f 100644
--- a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -24,3 +24,18 @@
reg = <0x5 0x 0x0 0x8000>;
};
 };
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi 
b/arch/arm/dts/r8a774e1-u-boot.dtsi
index 30c38dcfba..74758dfedf 100644
--- a/arch/arm/dts/r8a774e1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -11,15 +11,49 @@
u-boot,dm-pre-reloc;
 };
 
+/delete-node/ 
+/delete-node/ 
 /delete-node/ 
 /delete-node/ 
 /delete-node/ 
+/delete-node/ 
+/delete-node/ 
 /delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
 /delete-node/ 
+/delete-node/ 
 /delete-node/ _sound;
 /delete-node/ 
 /delete-node/ _card;
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
 
 / {
/delete-node/ hdmi0-out;
 };
+
+/ {
+   soc {
+   /delete-node/ fdp1@fe94;
+   /delete-node/ fdp1@fe944000;
+   };
+};
diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi
index 0f86cfd524..c29643442e 100644
--- a/arch/arm/dts/r8a774e1.dtsi
+++ b/arch/arm/dts/r8a774e1.dtsi
@@ -28,6 +28,12 @@
clock-frequency = <0>;
};
 
+   audio_clk_b: audio_clk_b {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -127,6 +133,7 @@
power-domains = < R8A774E1_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = < CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <_opp>;
@@ -141,6 +148,7 @@
power-domains = < R8A774E1_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -154,6 +162,7 @@
power-domains = < R8A774E1_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -167,6 +176,7 @@
power-domains = < R8A774E1_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_C

[PATCH v7 3/4] arm: rmobile: Add HopeRun HiHope RZ/G2H board support

[Biju Das]

The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.

DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and
r8a774e1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9").

This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v6->v7:
 * No Change. rebased on u-boot-sh/next
v6: 
 * New patch
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 15 +++
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 +++
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts| 26 ++
 arch/arm/dts/r8a774e1-u-boot.dtsi | 25 +
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  6 -
 configs/hihope_rzg2_defconfig |  2 +-
 8 files changed, 101 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d509f00dc6..1f0d55a982 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -800,6 +800,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
+   r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 00..265355e0de
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+"renesas,r8a774e1";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
new file mode 100644
index 00..03a17bac7e
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "r8a774e1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 00..cdbe527e93
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+   compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@5 {
+   device_type = "memory";
+   reg = <0x5 0x 0x0 0x8000>;
+   };
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi 
b/arch/arm/dts/r8a774e1-u-boot.dtsi
new file mode 100644
index 00..30c38dcfba
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/de

[PATCH v7 1/4] arm: rmobile: Add HopeRun HiHope RZ/G2M board support

[Biju Das]

The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.

DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9").

This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
V6->V7
 * Seperated driver patches from board support patches.
v5->v6
  * Rebased to U-boot-sh/master
  * Changed the logic for USB0 channel0 Host support.
  * Enabled CONFIG_SOC_DEVICE_RENESAS option

V4->V5
  * Rebased to U-boot-sh/next
  (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201012151616.5384-4-biju.das...@bp.renesas.com/)

V3->V4
  * Added USB0 channel0 Host support
(Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-2-biju.das...@bp.renesas.com/)
V2->V3  
   * Reworked as per Marek's suggestion
   * Added rzg2_get_cpu_type function to get cpu_type by matching TFA 
compatible string
   * Removed SoC family type Enum
   Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-3-biju.das...@bp.renesas.com/

V1->V2
 * Fixed indentation for R8A774A1 config
 * Used GPIO hog for setting WLAN/BT REG ON
 * Removed USB related initialization
  Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-2-biju.das...@bp.renesas.com/

V1:-
 * New Patch
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-5-biju.das...@bp.renesas.com/
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/hihope-common.dtsi   | 377 ++
 arch/arm/dts/hihope-rev4.dtsi | 124 ++
 arch/arm/dts/hihope-rzg2-ex.dtsi  |  92 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts |  21 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts |  27 ++
 arch/arm/dts/r8a774a1-hihope-rzg2m.dts|  37 ++
 arch/arm/dts/r8a774a1-u-boot.dtsi |  55 +++
 arch/arm/mach-rmobile/Kconfig.64  |  14 +
 board/hoperun/hihope-rzg2/Kconfig |  15 +
 board/hoperun/hihope-rzg2/MAINTAINERS |   6 +
 board/hoperun/hihope-rzg2/Makefile|   9 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  91 +
 configs/hihope_rzg2_defconfig |  77 
 include/configs/hihope-rzg2.h |  20 +
 15 files changed, 966 insertions(+)
 create mode 100644 arch/arm/dts/hihope-common.dtsi
 create mode 100644 arch/arm/dts/hihope-rev4.dtsi
 create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
 create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7d1a369845..17e19ad362 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -798,6 +798,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
 
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
+   r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
new file mode 100644
index 00..51eb74fbe9
--- /dev/null
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include 
+
+/ {
+   aliases {
+   serial0 = 
+   serial1 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel";
+   stdout-path = "serial0:115200n8";
+   };
+
+   hdmi0-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi0_con: endpoint {
+   remote-endpoint = <_dw_hdmi0_out>;
+   };
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   led1 {
+   gpios = < 12 GPIO_ACTIVE_HIGH>;
+   };
+
+   led2 {
+   gpios = < 13 GPIO_ACTIVE_HIGH>;
+

[PATCH v7 2/4] arm: rmobile: Add HopeRun HiHope RZ/G2N board support

[Biju Das]

The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.

DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9")

This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v6->v7:
 * No Change. rebased on u-boot-sh/next
v6: 
 * New patch
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 16 ++
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts| 41 ++
 arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  6 ++-
 configs/hihope_rzg2_defconfig |  2 +-
 8 files changed, 145 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 17e19ad362..d509f00dc6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -799,6 +799,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
+   r8a774b1-hihope-rzg2n-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 00..a3edd55113
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+"renesas,r8a774b1";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 00..09378a70a2
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 00..f1883cbd1a
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+   compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi 
b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 00

[PATCH v7 0/4] Add RZ/G2[HMN] board support

[Biju Das]

This patch series adds the required SoC/Board support to boot HopeRun
HiHope RZ/G2[HMN] boards. This patch series depend on [1]

[1] 
http://u-boot.10912.n7.nabble.com/PATCH-v7-0-4-Add-CPU-identification-support-for-RZ-G2-SoC-s-td433694.html

v6->v7
 * 
http://u-boot.10912.n7.nabble.com/PATCH-v6-0-7-Add-HiHope-RZ-G2-HMN-board-support-td431651.html
Biju Das (4):
  arm: rmobile: Add HopeRun HiHope RZ/G2M board support
  arm: rmobile: Add HopeRun HiHope RZ/G2N board support
  arm: rmobile: Add HopeRun HiHope RZ/G2H board support
  arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.10.rc5

 arch/arm/dts/Makefile |3 +
 arch/arm/dts/hihope-common.dtsi   |  377 +
 arch/arm/dts/hihope-rev4.dtsi |  124 ++
 arch/arm/dts/hihope-rzg2-ex.dtsi  |   92 ++
 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts |   21 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts |   27 +
 arch/arm/dts/r8a774a1-hihope-rzg2m.dts|   37 +
 arch/arm/dts/r8a774a1-u-boot.dtsi |   55 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts |   16 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts |   27 +
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts|   41 +
 arch/arm/dts/r8a774b1-u-boot.dtsi |   53 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts |   20 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts |   27 +
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts|   41 +
 arch/arm/dts/r8a774e1-u-boot.dtsi |   59 +
 arch/arm/dts/r8a774e1.dtsi| 1340 -
 arch/arm/mach-rmobile/Kconfig.64  |   16 +
 board/hoperun/hihope-rzg2/Kconfig |   15 +
 board/hoperun/hihope-rzg2/MAINTAINERS |6 +
 board/hoperun/hihope-rzg2/Makefile|9 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |   99 ++
 configs/hihope_rzg2_defconfig |   77 +
 include/configs/hihope-rzg2.h |   20 +
 24 files changed, 2575 insertions(+), 27 deletions(-)
 create mode 100644 arch/arm/dts/hihope-common.dtsi
 create mode 100644 arch/arm/dts/hihope-rev4.dtsi
 create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
 create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

-- 
2.17.1

[PATCH v7 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N

[Biju Das]

Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v7:
 * No Change.
v6: 
 * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 7e3ea92cbf..b84cfaa9a3 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a77965_calib_table,
+};
+
 /*
  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
  * So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a774b1",
+ .data = _quirks_r8a77965
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a77965",
+ .data = _quirks_r8a77965
+   },
{ /* Sentinel. */ },
 };
 
@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
-   if (quirks == _quirks_r8a7796_es12)
+   if (quirks == _quirks_r8a7796_es12 ||
+   quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == _quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
-- 
2.17.1

[PATCH v7 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Biju Das]

Add SDHI quirks for R-Car H3 and RZ/G2H SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v7:
  * No Change.
v6:
  * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index b84cfaa9a3..09d8a2aa0a 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7795_calib_table,
+};
+
 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[]  = {
{ .soc_id = "r8a774b1",
  .data = _quirks_r8a77965
},
+   { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = _quirks_4tap
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
if (quirks == _quirks_r8a7796_es12 ||
quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
-   else if (quirks == _quirks_r8a7796_es13)
+   else if (quirks == _quirks_r8a7796_es13 ||
+quirks == _quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
 }
-- 
2.17.1

[PATCH v7 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v7:
 * Incorporated Jaehoon Chung's review comments.
 * Fixed the build error on Renesas ARM32 platforms.
v6:
 * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 117 +
 1 file changed, 117 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d80b3fc28f..7e3ea92cbf 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "tmio-common.h"
 
@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct 
tmio_sd_priv *priv)
return clk_get_rate(>clk);
 }
 
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+   bool hs400_disabled;
+   bool hs400_4taps;
+   u32 hs400_bad_taps;
+   const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+   .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+   .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[]  = {
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+   struct tmio_sd_priv *priv,
+   const struct renesas_sdhi_quirks *quirks)
+{
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+   priv->nrtaps = 8;
+
+   if (!quirks)
+   return;
+
+   if (quirks->hs400_disabled) {
+   plat->cfg.host_caps &= ~MMC_MODE_HS400;
+   if (quirks == _quirks_4tap_nohs400_b17_dtrend)
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+   }
+
+   if (quirks->hs400_4taps)
+   priv->nrtaps = 4;
+
+   if (quirks->hs400_bad_taps)
+   priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+   if (quirks->hs400_calib_table) {
+   priv->adjust_hs400_enable = true;
+   priv->adjust_hs400_calib_table =
+   quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+   if (quirks == _quirks_r8a7796_es12)
+   priv->adjust_hs400_offset = 3;
+   else if (quirks == _quirks_r8a7796_es13)
+   priv->adjust_hs400_offset = 0;
+   }
+}
+#endif
+
 static void renesas_sdhi_filter_caps(struct udevice *dev)
 {
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_platdata(dev);
+   const struct soc_attr *attr;
+
+   attr = soc_device_match(sdhi_quirks_match);
+   if (attr) {
+   renesas_sdhi_add_quirks(plat, priv, attr->data);
+   return;
+   }
 
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
-- 
2.17.1

[PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.

RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).

As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v6->v7
 * Seperated driver patch series from board support patches.
v5->v6
 * Optimized the unique CPU identification method by using Renesas SoC 
identification driver.
v4->v5
 * Add support for unique identification of RZ/G2 CPU types
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das...@bp.renesas.com/)
v3->v4
 * Dropped CPU info reporting logic for RZ/G2. Will address this later.
 * Added PRRID's for RZG2[HMNE]
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das...@bp.renesas.com/)

v2->v3  
 * Reworked as per Marek's suggestion
 * Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible 
string
 * Removed SoC family type Enum
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das...@bp.renesas.com/)

v1->v2:
 * Add comment's related to loop logic
   (ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das...@bp.renesas.com/)

v1:
 * New patch
  
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das...@bp.renesas.com/
---
 arch/arm/mach-rmobile/cpu_info-rcar.c| 22 ++-
 arch/arm/mach-rmobile/cpu_info.c | 10 +++-
 arch/arm/mach-rmobile/include/mach/rmobile.h | 60 +++-
 3 files changed, 73 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c 
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..08345503a2 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -6,6 +6,7 @@
  */
 #include 
 #include 
+#include 
 
 #define PRR_MASK   0x7fff
 #define R8A7796_REV_1_00x5200
@@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
 #endif
 }
 
+static bool is_rzg_family(void)
+{
+   bool rzg_family_type = false;
+   struct udevice *soc;
+   char name[16];
+
+   if (!(soc_get() || soc_get_family(soc, name, 16))) {
+   if (!strcmp(name, "RZ/G2"))
+   rzg_family_type = true;
+   }
+
+   return rzg_family_type;
+}
+
 u32 rmobile_get_cpu_type(void)
 {
-   return (rmobile_get_prr() & 0x7F00) >> 8;
+   u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
+
+   if (is_rzg_family())
+   soc_id |= RZG_CPU_MASK;
+
+   return soc_id;
 }
 
 u32 rmobile_get_cpu_rev_integer(void)
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..b19b7e3044 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,12 +3,12 @@
  * (C) Copyright 2012 Nobuhiro Iwamatsu 
  * (C) Copyright 2012 Renesas Solutions Corp.
  */
-#include 
-#include 
 #include 
-#include 
 #include 
+#include 
+#include 
 #include 
+#include 
 #include 
 
 #ifdef CONFIG_ARCH_CPU_INIT
@@ -59,6 +59,10 @@ static const struct {
 } rmobile_cpuinfo[] = {
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
+   { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
+   { RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
+   { RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
+   { RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..da099fa4c3 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -24,21 +24,51 @@
 #endif
 #endif /* CONFIG_ARCH_RMOBILE */
 
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_SH73A00x37
-#define RMOBILE_CPU_TYPE_R8A7740   0x40
-#define RMOBILE_CPU_TYPE_R8A7790   0x45
-#define RMOBILE_CPU_TYPE_R8A7791   0x47
-#define RMOBILE_CPU_TYPE_R8A7792   0x4A
-#define RMOBILE_CPU_TYPE_R8A7793   0x4B
-#define RMOBILE_CPU_TYPE_R8A7794   0x4C
-#define RMOBILE_CPU_TYPE_R8A7795   0x4F
-#define RMOBILE_CPU_TYPE_R8A7796   0x52
-#define RMOBILE_CPU_TYPE_R8A77965  0x55
-#define RMOBILE_CPU_TYPE_R8A77970  0x54
-#define RMOBILE_CPU_TYPE_R8A77980  0x56
-#define RMOBILE_CPU_TYPE_R8A77990  0x57
-#define RMOBILE_CPU_TYPE_R8A77995  0x58
+/* PRR IDs */
+#define SOC_ID_SH73A0  0x

[PATCH v7 0/4] Add CPU identification support for RZ/G2 SoC's

[Biju Das]

This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.

This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=214706

Biju Das (4):
  arm: rmobile: Add RZ/G2[HMNE] SoC support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
  mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

 arch/arm/mach-rmobile/cpu_info-rcar.c|  22 ++-
 arch/arm/mach-rmobile/cpu_info.c |  10 +-
 arch/arm/mach-rmobile/include/mach/rmobile.h |  60 +--
 drivers/mmc/renesas-sdhi.c   | 160 +++
 4 files changed, 233 insertions(+), 19 deletions(-)

-- 
2.17.1

[PATCH v4 1/4] dm: core: Add of_match_node helper function

[Biju Das]

Add of_match_node() helper function to iterate over the device tree
and tell if a device_node has a matching of_match structure.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Simon Glass 
---
v3->v4: No change
 * Added Simon's Rb tag.
v2->v3:
 * Added a test case for of_match_node helper function.
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-2-biju.das...@bp.renesas.com/)
v1->v2:
  * No Change.
---
 drivers/core/device.c | 21 +
 include/dm/device.h   | 13 +
 test/dm/core.c| 31 +++
 3 files changed, 65 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 4b3dcb3b37..5db4c5e78b 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -1010,6 +1010,27 @@ bool of_machine_is_compatible(const char *compat)
return !fdt_node_check_compatible(fdt, 0, compat);
 }
 
+static
+const struct udevice_id *__of_match_node(const struct udevice_id *matches,
+const ofnode node)
+{
+   if (!matches)
+   return NULL;
+
+   for (; matches->compatible; matches++) {
+   if (ofnode_device_is_compatible(node, matches->compatible))
+   return matches;
+   }
+
+   return NULL;
+}
+
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node)
+{
+   return __of_match_node(matches, node);
+}
+
 int dev_disable_by_path(const char *path)
 {
struct uclass *uc;
diff --git a/include/dm/device.h b/include/dm/device.h
index 5bef484247..4c357d46ec 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -754,6 +754,19 @@ bool device_is_compatible(const struct udevice *dev, const 
char *compat);
  */
 bool of_machine_is_compatible(const char *compat);
 
+/**
+ * of_match_node() - Tell if a device_node has a matching of_match structure
+ *
+ *
+ * Low level utility function used by device matching.
+ *
+ * @matches:   array of of device match structures to search in
+ * @node:  the of device structure to match against
+ * @return matching structure on success, NULL if the match is not found
+ */
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node);
+
 /**
  * dev_disable_by_path() - Disable a device given its device tree path
  *
diff --git a/test/dm/core.c b/test/dm/core.c
index 6f380a574c..b94b78d9ba 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1066,3 +1067,33 @@ static int dm_test_inactive_child(struct unit_test_state 
*uts)
return 0;
 }
 DM_TEST(dm_test_inactive_child, UT_TESTF_SCAN_PDATA);
+
+static int dm_test_of_match_node(struct unit_test_state *uts)
+{
+   const ulong test_data_expected = 0x1234;
+   ofnode root_node = ofnode_path("/");
+   const struct udevice_id *match;
+   unsigned long match_data;
+
+   const struct udevice_id soc_device_ids[] = {
+   { .compatible = "sandbox", .data = test_data_expected, },
+   { /* sentinel */ }
+   };
+
+   const struct udevice_id soc_device_nomatch_ids[] = {
+   { .compatible = "sandbox123", .data = test_data_expected, },
+   { /* sentinel */ }
+   };
+
+   match = of_match_node(soc_device_ids, root_node);
+   ut_assert(match);
+
+   match_data = match->data;
+   ut_asserteq(match_data, test_data_expected);
+
+   match = of_match_node(soc_device_nomatch_ids, root_node);
+   ut_asserteq_ptr(match, NULL);
+
+   return 0;
+}
+DM_TEST(dm_test_of_match_node, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-- 
2.17.1

[PATCH v4 4/4] dm: soc: SoC identification driver for Renesas SoC's

[Biju Das]

Add SoC identification driver for Renesas SoC's. This allows
to identify the SoC type and revision based on Product Register.

This can be checked where needed using soc_device_match().

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v3->v4: 
 * Updated Copy right information from Linux.
 * Updated probe function, use the prr address from DT.
v2->v3: No Change.
v2: New patch
---
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   1 +
 drivers/soc/soc_renesas.c | 244 ++
 3 files changed, 252 insertions(+)
 create mode 100644 drivers/soc/soc_renesas.c

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 864d00a885..475e94cd77 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -16,6 +16,13 @@ config SOC_DEVICE_TI_K3
  This allows Texas Instruments Keystone 3 SoCs to identify
  specifics about the SoC in use.
 
+config SOC_DEVICE_RENESAS
+   depends on SOC_DEVICE
+   bool "Enable SoC driver for Renesas SoCs"
+   help
+ This allows Renesas SoCs to identify specifics about the
+ SoC in use.
+
 source "drivers/soc/ti/Kconfig"
 
 endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 9ef20ca506..b143eac5fd 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,5 +4,6 @@
 
 obj-$(CONFIG_SOC_TI) += ti/
 obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
+obj-$(CONFIG_$(SPL_)SOC_DEVICE_RENESAS) += soc_renesas.o
 obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
 obj-$(CONFIG_SANDBOX) += soc_sandbox.o
diff --git a/drivers/soc/soc_renesas.c b/drivers/soc/soc_renesas.c
new file mode 100644
index 00..a42c6342fa
--- /dev/null
+++ b/drivers/soc/soc_renesas.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2016 Glider bvba
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct soc_renesas_priv {
+   const char *family;
+   const char *soc_id;
+   char revision[6];
+};
+
+struct renesas_family {
+   const char name[16];
+   u32 reg;/* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rcar_gen3 __maybe_unused = {
+   .name   = "R-Car Gen3",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rzg2 __maybe_unused = {
+   .name   = "RZ/G2",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+struct renesas_soc {
+   const struct renesas_family *family;
+   u8 id;
+};
+
+#ifdef CONFIG_R8A774A1
+static const struct renesas_soc soc_rz_g2m = {
+   .family = _rzg2,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A774B1
+static const struct renesas_soc soc_rz_g2n = {
+   .family = _rzg2,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A774C0
+static const struct renesas_soc soc_rz_g2e = {
+   .family = _rzg2,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A774E1
+static const struct renesas_soc soc_rz_g2h = {
+   .family = _rzg2,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7795
+static const struct renesas_soc soc_rcar_h3 = {
+   .family = _rcar_gen3,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7796
+static const struct renesas_soc soc_rcar_m3_w = {
+   .family = _rcar_gen3,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A77965
+static const struct renesas_soc soc_rcar_m3_n = {
+   .family = _rcar_gen3,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A77970
+static const struct renesas_soc soc_rcar_v3m = {
+   .family = _rcar_gen3,
+   .id = 0x54,
+};
+#endif
+
+#ifdef CONFIG_R8A77980
+static const struct renesas_soc soc_rcar_v3h = {
+   .family = _rcar_gen3,
+   .id = 0x56,
+};
+#endif
+
+#ifdef CONFIG_R8A77990
+static const struct renesas_soc soc_rcar_e3 = {
+   .family = _rcar_gen3,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A77995
+static const struct renesas_soc soc_rcar_d3 = {
+   .family = _rcar_gen3,
+   .id = 0x58,
+};
+#endif
+
+static int soc_renesas_get_family(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->family);
+
+   return 0;
+}
+
+static int soc_renesas_get_revision(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->revision);
+
+   return 0;
+}
+
+static int soc_renesas_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->soc_id);
+
+   return 0;
+}
+
+static const struct udevice_id renesas_socs[] = {
+#ifdef CONFIG_R8A774A1
+   { .compatible = "renesas,r8a77

[PATCH v4 3/4] dm: soc: Add SoC id for attribute matching

[Biju Das]

Mainline kernel uses the "soc_id" attribute to identify the SoC for some
of the h/w platforms. Adding this attribute in u-boot will make SoC
identification similar to the mainline kernel, so that it can be easily
maintained.

Add a new attribute named "soc_id" to SOC uclass, in order to allow device
drivers for identifying the SoC using SoC identification string and also
for matching this attribute for selecting SoC specific data.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Simon Glass 
---
v3->v4:
 * Updated patch description
 * Added Simon's Rb tag.

v2->v3:
 * split the comments patch seperate.
 
Ref:https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-3-biju.das...@bp.renesas.com/

v1->v2: Changed the comments from "a SoC" to "an SoC"
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201030140724.12773-1-biju.das...@bp.renesas.com/
---
 drivers/soc/soc-uclass.c  | 19 ++-
 drivers/soc/soc_sandbox.c |  8 
 include/soc.h | 27 +++
 test/dm/soc.c |  8 
 4 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index c32d647864..a3f8be841b 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size)
return ops->get_revision(dev, buf, size);
 }
 
+int soc_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_ops *ops = soc_get_ops(dev);
+
+   if (!ops->get_soc_id)
+   return -ENOSYS;
+
+   return ops->get_soc_id(dev, buf, size);
+}
+
 const struct soc_attr *
 soc_device_match(const struct soc_attr *matches)
 {
@@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
 
while (1) {
if (!(matches->machine || matches->family ||
- matches->revision))
+ matches->revision || matches->soc_id))
break;
 
match = true;
@@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
}
}
 
+   if (matches->soc_id) {
+   if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
+   if (strcmp(matches->soc_id, str))
+   match = false;
+   }
+   }
+
if (match)
return matches;
 
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad84fc..1a81d3562a 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev, char 
*buf, int size)
return 0;
 }
 
+int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   snprintf(buf, size, "r8a774a1");
+
+   return 0;
+}
+
 static const struct soc_ops soc_sandbox_ops = {
.get_family = soc_sandbox_get_family,
.get_revision = soc_sandbox_get_revision,
.get_machine = soc_sandbox_get_machine,
+   .get_soc_id = soc_sandbox_get_soc_id,
 };
 
 int soc_sandbox_probe(struct udevice *dev)
diff --git a/include/soc.h b/include/soc.h
index 05058f9331..db0e8880d1 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -20,12 +20,14 @@
  *variants. Example: am33
  * @machine  - Name of a specific SoC. Example: am3352
  * @revision - Name of a specific SoC revision. Example: SR1.1
+ * @soc_id   - SoC identification string. Example: r8a774a1
  * @data - A pointer to user data for the SoC variant
  */
 struct soc_attr {
const char *family;
const char *machine;
const char *revision;
+   const char *soc_id;
const void *data;
 };
 
@@ -59,6 +61,16 @@ struct soc_ops {
 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
 */
int (*get_family)(struct udevice *dev, char *buf, int size);
+
+   /**
+* get_soc_id() - Get SoC identification name of an SoC
+*
+* @dev:Device to check (UCLASS_SOC)
+* @buf:Buffer to place string
+* @size:   Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+*/
+   int (*get_soc_id)(struct udevice *dev, char *buf, int size);
 };
 
 #define soc_get_ops(dev)((struct soc_ops *)(dev)->driver->ops)
@@ -105,6 +117,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size);
  */
 int soc_get_family(struct udevice *dev, char *buf, int size);
 
+/**
+ * soc_get_soc_id() - Get SoC identification name of an SoC
+ * @dev:   Device to check (UCLASS_SOC)
+ * @buf:   Buffer to place string
+ * @size:  Size of string space
+ *
+ * Return: 0 if OK, -ENOSPC if buffer is 

[PATCH v4 2/4] soc: Fix comments from SOC to SoC

[Biju Das]

Fix the comments from "an SOC" to "an SoC".

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
Reviewed-by: Simon Glass 
---
 v3->v4: No Change
 * Added Simon's Rb tag.
 v3: 
 * New patch
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-3-biju.das...@bp.renesas.com/)
---
 include/soc.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/soc.h b/include/soc.h
index a55eb1b572..05058f9331 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -31,7 +31,7 @@ struct soc_attr {
 
 struct soc_ops {
/**
-* get_machine() - Get machine name of an SOC
+* get_machine() - Get machine name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -41,7 +41,7 @@ struct soc_ops {
int (*get_machine)(struct udevice *dev, char *buf, int size);
 
/**
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -51,7 +51,7 @@ struct soc_ops {
int (*get_revision)(struct udevice *dev, char *buf, int size);
 
/**
-* get_family() - Get family name of an SOC
+* get_family() - Get family name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -76,7 +76,7 @@ struct soc_ops {
 int soc_get(struct udevice **devp);
 
 /**
- * soc_get_machine() - Get machine name of an SOC
+ * soc_get_machine() - Get machine name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
@@ -86,7 +86,7 @@ int soc_get(struct udevice **devp);
 int soc_get_machine(struct udevice *dev, char *buf, int size);
 
 /**
- * soc_get_revision() - Get revision name of an SOC
+ * soc_get_revision() - Get revision name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
@@ -96,7 +96,7 @@ int soc_get_machine(struct udevice *dev, char *buf, int size);
 int soc_get_revision(struct udevice *dev, char *buf, int size);
 
 /**
- * soc_get_family() - Get family name of an SOC
+ * soc_get_family() - Get family name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
-- 
2.17.1

[PATCH v4 0/4] Add Renesas SoC identification driver support

[Biju Das]

This patch series aims to support Renesas SoC identification driver.

Added a helper function of_match_node to find the matching of_match structure. 
This helper function can be used to replace the following code in u-boot [1] 
and [2]

[1] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/serial/serial_uniphier.c#L129
[2] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/usb/phy/rockchip_usb2_phy.c#L77

Also added soc_id attribute support in UCLASS_SOC which is required for Renesas 
SoC identification driver similar to mainline linux.

v3->v4
  * Added Simon's Rb tag
  * Updated patch description for SoC identification using soc_id
  * Updated probe function of Renesas SoC identification driver.

Biju Das (4):
  dm: core: Add of_match_node helper function
  soc: Fix comments from SOC to SoC
  dm: soc: Add SoC id for attribute matching
  dm: soc: SoC identification driver for Renesas SoC's

 drivers/core/device.c |  21 
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   1 +
 drivers/soc/soc-uclass.c  |  19 ++-
 drivers/soc/soc_renesas.c | 244 ++
 drivers/soc/soc_sandbox.c |   8 ++
 include/dm/device.h   |  13 ++
 include/soc.h |  39 +-
 test/dm/core.c|  31 +
 test/dm/soc.c |   8 ++
 10 files changed, 384 insertions(+), 7 deletions(-)
 create mode 100644 drivers/soc/soc_renesas.c

-- 
2.17.1

RE: [PATCH v3 3/4] dm: soc: Add SoC id for attribute matching

[Biju Das]

Hi Simon,

Thanks for the feedback.

> -Original Message-
> From: Simon Glass 
> Sent: 14 November 2020 15:17
> To: Biju Das 
> Cc: Dave Gerlach ; Prabhakar Mahadev Lad
> ; U-Boot Mailing List  b...@lists.denx.de>; Marek Vasut ; Nobuhiro
> Iwamatsu ; Chris Paterson
> 
> Subject: Re: [PATCH v3 3/4] dm: soc: Add SoC id for attribute matching
> 
> On Wed, 4 Nov 2020 at 04:56, Biju Das  wrote:
> >
> > Add SoC identification string for attribute matching.
> 
> Commit messages should  normally have a motivation followed by a
> description of what they do.

Ok. I will update the motivation and description like below. Please let me 
know, if it needs updating. 

Mainline kernel uses the "soc_id" attribute to identify the SoC for some
of the h/w platforms. On such platforms adding this attribute in u-boot
will make soc identification similar to the mainline kernel, so that it 
can be easily maintained.

Add a new attribute named "soc_id" to SOC uclass, in order to allow device
drivers for identifying the SoC using SoC identification string and also
for matching this attribute for selecting SoC specific data.

Regards,
Biju

> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar 
> > ---
> > v2->v3:
> >  * split the comments patch seperate.
> >
> > Ref:https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > patchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201102150959.4793-3
> > -biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.r
> > enesas.com%7Caac5daef6c8448b8bdba08d888b063c6%7C53d82571da1947e49cb462
> > 5a166a4a2a%7C0%7C0%7C637409638454773531%7CUnknown%7CTWFpbGZsb3d8eyJWIj
> > oiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000
> > p;sdata=GeuQRbk%2FmaHXfnGNFYg7hrk9Cns7IfKNJ8nFvjhtg2k%3Dreserved=
> > 0
> >
> > v1->v2: Changed the comments from "a SoC" to "an SoC"
> >  Ref:
> > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> > hwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201030140724.12773-1-bi
> > ju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.rene
> > sas.com%7Caac5daef6c8448b8bdba08d888b063c6%7C53d82571da1947e49cb4625a1
> > 66a4a2a%7C0%7C0%7C637409638454773531%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM
> > C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000s
> > data=%2Bmk374jkkx%2B4ejTWlmTevWcZmbcM%2F3YksKcuZ7NPdN0%3Dreserved
> > =0
> > ---
> >  drivers/soc/soc-uclass.c  | 19 ++-
> > drivers/soc/soc_sandbox.c |  8 
> >  include/soc.h | 27 +++
> >  test/dm/soc.c |  8 
> >  4 files changed, 61 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Simon Glass 

RE: [PATCH v3 4/4] dm: soc: SoC identification driver for Renesas SoC's

[Biju Das]

Hi All,

I need to update copyright information for this patch. This work is derived 
from linux
and linux  has extra copyright information. I have missed that.
 
Will send V4 for fixing it.

Regards,
Biju

> -Original Message-
> From: Biju Das 
> Sent: 04 November 2020 10:56
> To: Simon Glass ; Marek Vasut
> 
> Cc: Biju Das ; Dave Gerlach  gerl...@ti.com>; Prabhakar Mahadev Lad  lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu
> ; Chris Paterson 
> Subject: [PATCH v3 4/4] dm: soc: SoC identification driver for Renesas
> SoC's
> 
> Add SoC identification driver for Renesas SoC's. This allows to identify
> the SoC type and revision based on Product Register.
> 
> This can be checked where needed using soc_device_match().
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Lad Prabhakar 
> ---
> v2->v3: No Change.
> v2: New patch
> ---
>  drivers/soc/Kconfig   |   7 ++
>  drivers/soc/Makefile  |   1 +
>  drivers/soc/soc_renesas.c | 239 ++
>  3 files changed, 247 insertions(+)
>  create mode 100644 drivers/soc/soc_renesas.c
> 
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index
> 864d00a885..475e94cd77 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -16,6 +16,13 @@ config SOC_DEVICE_TI_K3
> This allows Texas Instruments Keystone 3 SoCs to identify
> specifics about the SoC in use.
> 
> +config SOC_DEVICE_RENESAS
> + depends on SOC_DEVICE
> + bool "Enable SoC driver for Renesas SoCs"
> + help
> +   This allows Renesas SoCs to identify specifics about the
> +   SoC in use.
> +
>  source "drivers/soc/ti/Kconfig"
> 
>  endmenu
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index
> 9ef20ca506..b143eac5fd 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -4,5 +4,6 @@
> 
>  obj-$(CONFIG_SOC_TI) += ti/
>  obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
> +obj-$(CONFIG_$(SPL_)SOC_DEVICE_RENESAS) += soc_renesas.o
>  obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
>  obj-$(CONFIG_SANDBOX) += soc_sandbox.o
> diff --git a/drivers/soc/soc_renesas.c b/drivers/soc/soc_renesas.c new
> file mode 100644 index 00..4543e0dbfd
> --- /dev/null
> +++ b/drivers/soc/soc_renesas.c
> @@ -0,0 +1,239 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +struct soc_renesas_priv {
> + const char *family;
> + const char *soc_id;
> + char revision[6];
> +};
> +
> +struct renesas_family {
> + const char name[16];
> + u32 reg;/* CCCR or PRR, if not in DT */
> +};
> +
> +static const struct renesas_family fam_rcar_gen3 __maybe_unused = {
> + .name   = "R-Car Gen3",
> + .reg= 0xfff00044,   /* PRR (Product Register) */
> +};
> +
> +static const struct renesas_family fam_rzg2 __maybe_unused = {
> + .name   = "RZ/G2",
> + .reg= 0xfff00044,   /* PRR (Product Register) */
> +};
> +
> +struct renesas_soc {
> + const struct renesas_family *family;
> + u8 id;
> +};
> +
> +#ifdef CONFIG_R8A774A1
> +static const struct renesas_soc soc_rz_g2m = {
> + .family = _rzg2,
> + .id = 0x52,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A774B1
> +static const struct renesas_soc soc_rz_g2n = {
> + .family = _rzg2,
> + .id = 0x55,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A774C0
> +static const struct renesas_soc soc_rz_g2e = {
> + .family = _rzg2,
> + .id = 0x57,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A774E1
> +static const struct renesas_soc soc_rz_g2h = {
> + .family = _rzg2,
> + .id = 0x4f,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A7795
> +static const struct renesas_soc soc_rcar_h3 = {
> + .family = _rcar_gen3,
> + .id = 0x4f,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A7796
> +static const struct renesas_soc soc_rcar_m3_w = {
> + .family = _rcar_gen3,
> + .id = 0x52,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A77965
> +static const struct renesas_soc soc_rcar_m3_n = {
> + .family = _rcar_gen3,
> + .id = 0x55,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A77970
> +static const struct renesas_soc soc_rcar_v3m = {
> + .family = _rcar_gen3,
> + .id = 0x54,
> +};
> +#endif
> +
> +#ifdef CONFIG_R8A77980
> +static const struct renesas_soc soc_rcar_v3h = {
> + .family = _rcar_gen3,
> + .i

RE: [PATCH v3 1/4] dm: core: Add of_match_node helper function

[Biju Das]

Hi Simon,

Gentle ping. Are you happy with this patch?


Regards,
Biju

> -Original Message-
> From: Biju Das 
> Sent: 04 November 2020 10:56
> To: Simon Glass 
> Cc: Biju Das ; u-boot@lists.denx.de; Marek
> Vasut ; Nobuhiro Iwamatsu
> ; Chris Paterson ;
> Prabhakar Mahadev Lad 
> Subject: [PATCH v3 1/4] dm: core: Add of_match_node helper function
> 
> Add of_match_node() helper function to iterate over the device tree and
> tell if a device_node has a matching of_match structure.
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Lad Prabhakar 
> ---
> v2->v3:
>  * Added a test case for of_match_node helper function.
>  (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201102150959.4793-2-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C1ce4430428ba43c09d5808d880b0454e%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637400841846720504%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=zrG4RLHHr
> MYhbDwohsqNoctNZLnoMK5ZPvieFergq2A%3Dreserved=0)
> v1->v2:
>   * No Change.
> ---
>  drivers/core/device.c | 21 +
>  include/dm/device.h   | 13 +
>  test/dm/core.c| 31 +++
>  3 files changed, 65 insertions(+)
> 
> diff --git a/drivers/core/device.c b/drivers/core/device.c index
> 4b3dcb3b37..5db4c5e78b 100644
> --- a/drivers/core/device.c
> +++ b/drivers/core/device.c
> @@ -1010,6 +1010,27 @@ bool of_machine_is_compatible(const char *compat)
>   return !fdt_node_check_compatible(fdt, 0, compat);  }
> 
> +static
> +const struct udevice_id *__of_match_node(const struct udevice_id
> *matches,
> +  const ofnode node)
> +{
> + if (!matches)
> + return NULL;
> +
> + for (; matches->compatible; matches++) {
> + if (ofnode_device_is_compatible(node, matches->compatible))
> + return matches;
> + }
> +
> + return NULL;
> +}
> +
> +const struct udevice_id *of_match_node(const struct udevice_id *matches,
> +const ofnode node)
> +{
> + return __of_match_node(matches, node); }
> +
>  int dev_disable_by_path(const char *path)  {
>   struct uclass *uc;
> diff --git a/include/dm/device.h b/include/dm/device.h index
> 5bef484247..4c357d46ec 100644
> --- a/include/dm/device.h
> +++ b/include/dm/device.h
> @@ -754,6 +754,19 @@ bool device_is_compatible(const struct udevice *dev,
> const char *compat);
>   */
>  bool of_machine_is_compatible(const char *compat);
> 
> +/**
> + * of_match_node() - Tell if a device_node has a matching of_match
> +structure
> + *
> + *
> + * Low level utility function used by device matching.
> + *
> + * @matches: array of of device match structures to search in
> + * @node:the of device structure to match against
> + * @return matching structure on success, NULL if the match is not
> +found  */ const struct udevice_id *of_match_node(const struct
> +udevice_id *matches,
> +const ofnode node);
> +
>  /**
>   * dev_disable_by_path() - Disable a device given its device tree path
>   *
> diff --git a/test/dm/core.c b/test/dm/core.c index 6f380a574c..b94b78d9ba
> 100644
> --- a/test/dm/core.c
> +++ b/test/dm/core.c
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1066,3 +1067,33 @@ static int dm_test_inactive_child(struct
> unit_test_state *uts)
>   return 0;
>  }
>  DM_TEST(dm_test_inactive_child, UT_TESTF_SCAN_PDATA);
> +
> +static int dm_test_of_match_node(struct unit_test_state *uts) {
> + const ulong test_data_expected = 0x1234;
> + ofnode root_node = ofnode_path("/");
> + const struct udevice_id *match;
> + unsigned long match_data;
> +
> + const struct udevice_id soc_device_ids[] = {
> + { .compatible = "sandbox", .data = test_data_expected, },
> + { /* sentinel */ }
> + };
> +
> + const struct udevice_id soc_device_nomatch_ids[] = {
> + { .compatible = "sandbox123", .data = test_data_expected, },
> + { /* sentinel */ }
> + };
> +
> + match = of_match_node(soc_device_ids, root_node);
> + ut_assert(match);
> +
> + match_data = match->data;
> + ut_asserteq(match_data, test_data_expected);
> +
> + match = of_match_node(soc_device_nomatch_ids, root_node);
> + ut_asserteq_ptr(match, NULL);
> +
> + return 0;
> +}
> +DM_TEST(dm_test_of_match_node, UT_TESTF_SCAN_PDATA |
> +UT_TESTF_SCAN_FDT);
> --
> 2.17.1

RE: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,


> On 11/3/20 11:06 AM, Biju Das wrote:
> > Hi Marek,
> 
> Hi,
> 
> [...]
> 
> >>> On the next version, I will send Renesas SoC identification driver,
> >>> which supports caching family type which can be used to provide
> >>> unique
> >> identification for CPU type.
> >>
> >> Please make sure to check it on RCar2 as well, those use SPL and the
> >> SPL size is quite limited.
> >
> > Currently SoC identification driver is enabled only for RZ/G2 boards and
> support is added to both R-Car Gen3 and RZ/G2 devices.
> >
> > For the disabled case, the UCLASS-SOC class functions are inlined to "NULL"
> for soc_device_match and rest of the api's it is "-ENOSYS".
> >
> > I agree, in future we need to add support for RCar2 as well, since we are
> going to add u-boot support for RZ/G1 devices.
> > Please find the size details related to R-Car Gen2(by adding support for R-
> Car M2-W and RZ/G1M SoC).
> >
> > There is increase of 944 bytes, for R-Car Gen2 device, if we enable Renesas
> SoC identification driver for Gen2 devices.
> >
> > Current u-boot-sh/master
> > ---
> > $ ls -al u-boot.bin
> > -rw-r--r-- 1 biju biju 523001 Nov  3 09:16 u-boot.bin
> >
> > Current u-boot-sh/master + SoC renesas driver (R-Car M2-W enabled only
> > case)
> > --
> > --
> > $ ls -al u-boot.bin
> > -rw-r--r-- 1 biju biju 523945 Nov  3 09:47 u-boot.bin
> >
> > If you agree, we will add support for Gen2 to SoC identification driver 
> > later.
> Currently there is no users for using it.
> > Please let me know.
> 
> The problem on Gen2 isn't the size of u-boot.bin , but of spl/u-boot-spl.bin .
> That one is severely limited and I don't think it's realistic to add any sort 
> of
> SoC identification driver into it. In fact, I think even the DM is somehow
> reduced in there.

Yes, I agree there is size constraint for Gen2 for spl/u-boot-spl.bin. Even in 
Gen3, we don't compile core/pinctrl driver for SPL.
See, from drivers/Makefile. 

obj-$(CONFIG_$(SPL_TPL_)DM)
obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/

if we enable this, then we get linker error related to region .sram overflow 
messages.

Please let me know, shall I post a patch series with SoC Identification and 
SDHI quirks or still have some open points?

Regards,
Biju

[PATCH v3 3/4] dm: soc: Add SoC id for attribute matching

[Biju Das]

Add SoC identification string for attribute matching.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v2->v3:
 * split the comments patch seperate.
 
Ref:https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-3-biju.das...@bp.renesas.com/

v1->v2: Changed the comments from "a SoC" to "an SoC"
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201030140724.12773-1-biju.das...@bp.renesas.com/
---
 drivers/soc/soc-uclass.c  | 19 ++-
 drivers/soc/soc_sandbox.c |  8 
 include/soc.h | 27 +++
 test/dm/soc.c |  8 
 4 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index c32d647864..a3f8be841b 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size)
return ops->get_revision(dev, buf, size);
 }
 
+int soc_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_ops *ops = soc_get_ops(dev);
+
+   if (!ops->get_soc_id)
+   return -ENOSYS;
+
+   return ops->get_soc_id(dev, buf, size);
+}
+
 const struct soc_attr *
 soc_device_match(const struct soc_attr *matches)
 {
@@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
 
while (1) {
if (!(matches->machine || matches->family ||
- matches->revision))
+ matches->revision || matches->soc_id))
break;
 
match = true;
@@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
}
}
 
+   if (matches->soc_id) {
+   if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
+   if (strcmp(matches->soc_id, str))
+   match = false;
+   }
+   }
+
if (match)
return matches;
 
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad84fc..1a81d3562a 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev, char 
*buf, int size)
return 0;
 }
 
+int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   snprintf(buf, size, "r8a774a1");
+
+   return 0;
+}
+
 static const struct soc_ops soc_sandbox_ops = {
.get_family = soc_sandbox_get_family,
.get_revision = soc_sandbox_get_revision,
.get_machine = soc_sandbox_get_machine,
+   .get_soc_id = soc_sandbox_get_soc_id,
 };
 
 int soc_sandbox_probe(struct udevice *dev)
diff --git a/include/soc.h b/include/soc.h
index 05058f9331..db0e8880d1 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -20,12 +20,14 @@
  *variants. Example: am33
  * @machine  - Name of a specific SoC. Example: am3352
  * @revision - Name of a specific SoC revision. Example: SR1.1
+ * @soc_id   - SoC identification string. Example: r8a774a1
  * @data - A pointer to user data for the SoC variant
  */
 struct soc_attr {
const char *family;
const char *machine;
const char *revision;
+   const char *soc_id;
const void *data;
 };
 
@@ -59,6 +61,16 @@ struct soc_ops {
 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
 */
int (*get_family)(struct udevice *dev, char *buf, int size);
+
+   /**
+* get_soc_id() - Get SoC identification name of an SoC
+*
+* @dev:Device to check (UCLASS_SOC)
+* @buf:Buffer to place string
+* @size:   Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+*/
+   int (*get_soc_id)(struct udevice *dev, char *buf, int size);
 };
 
 #define soc_get_ops(dev)((struct soc_ops *)(dev)->driver->ops)
@@ -105,6 +117,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size);
  */
 int soc_get_family(struct udevice *dev, char *buf, int size);
 
+/**
+ * soc_get_soc_id() - Get SoC identification name of an SoC
+ * @dev:   Device to check (UCLASS_SOC)
+ * @buf:   Buffer to place string
+ * @size:  Size of string space
+ *
+ * Return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int soc_get_soc_id(struct udevice *dev, char *buf, int size);
+
 /**
  * soc_device_match() - Return match from an array of soc_attr
  * @matches:   Array with any combination of family, revision or machine set
@@ -136,6 +158,11 @@ static inline int soc_get_family(struct udevice *dev, char 
*buf, int size)
return -ENOSYS;
 }
 
+static inline int soc_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   return -ENOSYS;
+}
+
 static inline const str

[PATCH v3 4/4] dm: soc: SoC identification driver for Renesas SoC's

[Biju Das]

Add SoC identification driver for Renesas SoC's. This allows
to identify the SoC type and revision based on Product Register.

This can be checked where needed using soc_device_match().

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v2->v3: No Change.
v2: New patch
---
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   1 +
 drivers/soc/soc_renesas.c | 239 ++
 3 files changed, 247 insertions(+)
 create mode 100644 drivers/soc/soc_renesas.c

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 864d00a885..475e94cd77 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -16,6 +16,13 @@ config SOC_DEVICE_TI_K3
  This allows Texas Instruments Keystone 3 SoCs to identify
  specifics about the SoC in use.
 
+config SOC_DEVICE_RENESAS
+   depends on SOC_DEVICE
+   bool "Enable SoC driver for Renesas SoCs"
+   help
+ This allows Renesas SoCs to identify specifics about the
+ SoC in use.
+
 source "drivers/soc/ti/Kconfig"
 
 endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 9ef20ca506..b143eac5fd 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,5 +4,6 @@
 
 obj-$(CONFIG_SOC_TI) += ti/
 obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
+obj-$(CONFIG_$(SPL_)SOC_DEVICE_RENESAS) += soc_renesas.o
 obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
 obj-$(CONFIG_SANDBOX) += soc_sandbox.o
diff --git a/drivers/soc/soc_renesas.c b/drivers/soc/soc_renesas.c
new file mode 100644
index 00..4543e0dbfd
--- /dev/null
+++ b/drivers/soc/soc_renesas.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct soc_renesas_priv {
+   const char *family;
+   const char *soc_id;
+   char revision[6];
+};
+
+struct renesas_family {
+   const char name[16];
+   u32 reg;/* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rcar_gen3 __maybe_unused = {
+   .name   = "R-Car Gen3",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rzg2 __maybe_unused = {
+   .name   = "RZ/G2",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+struct renesas_soc {
+   const struct renesas_family *family;
+   u8 id;
+};
+
+#ifdef CONFIG_R8A774A1
+static const struct renesas_soc soc_rz_g2m = {
+   .family = _rzg2,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A774B1
+static const struct renesas_soc soc_rz_g2n = {
+   .family = _rzg2,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A774C0
+static const struct renesas_soc soc_rz_g2e = {
+   .family = _rzg2,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A774E1
+static const struct renesas_soc soc_rz_g2h = {
+   .family = _rzg2,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7795
+static const struct renesas_soc soc_rcar_h3 = {
+   .family = _rcar_gen3,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7796
+static const struct renesas_soc soc_rcar_m3_w = {
+   .family = _rcar_gen3,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A77965
+static const struct renesas_soc soc_rcar_m3_n = {
+   .family = _rcar_gen3,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A77970
+static const struct renesas_soc soc_rcar_v3m = {
+   .family = _rcar_gen3,
+   .id = 0x54,
+};
+#endif
+
+#ifdef CONFIG_R8A77980
+static const struct renesas_soc soc_rcar_v3h = {
+   .family = _rcar_gen3,
+   .id = 0x56,
+};
+#endif
+
+#ifdef CONFIG_R8A77990
+static const struct renesas_soc soc_rcar_e3 = {
+   .family = _rcar_gen3,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A77995
+static const struct renesas_soc soc_rcar_d3 = {
+   .family = _rcar_gen3,
+   .id = 0x58,
+};
+#endif
+
+static int soc_renesas_get_family(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->family);
+
+   return 0;
+}
+
+static int soc_renesas_get_revision(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->revision);
+
+   return 0;
+}
+
+static int soc_renesas_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->soc_id);
+
+   return 0;
+}
+
+static const struct udevice_id renesas_socs[] = {
+#ifdef CONFIG_R8A774A1
+   { .compatible = "renesas,r8a774a1", .data = (ulong)_rz_g2m, },
+#endif
+#ifdef CONFIG_R8A774B1
+   { .compatible = "renesas,r8a774b1", .data = (ulong)_rz_g2n, },

[PATCH v3 2/4] soc: Fix comments from SOC to SoC

[Biju Das]

Fix the comments from "an SOC" to "an SoC".

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v3: 
 * New patch
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-3-biju.das...@bp.renesas.com/)
---
 include/soc.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/soc.h b/include/soc.h
index a55eb1b572..05058f9331 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -31,7 +31,7 @@ struct soc_attr {
 
 struct soc_ops {
/**
-* get_machine() - Get machine name of an SOC
+* get_machine() - Get machine name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -41,7 +41,7 @@ struct soc_ops {
int (*get_machine)(struct udevice *dev, char *buf, int size);
 
/**
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -51,7 +51,7 @@ struct soc_ops {
int (*get_revision)(struct udevice *dev, char *buf, int size);
 
/**
-* get_family() - Get family name of an SOC
+* get_family() - Get family name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -76,7 +76,7 @@ struct soc_ops {
 int soc_get(struct udevice **devp);
 
 /**
- * soc_get_machine() - Get machine name of an SOC
+ * soc_get_machine() - Get machine name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
@@ -86,7 +86,7 @@ int soc_get(struct udevice **devp);
 int soc_get_machine(struct udevice *dev, char *buf, int size);
 
 /**
- * soc_get_revision() - Get revision name of an SOC
+ * soc_get_revision() - Get revision name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
@@ -96,7 +96,7 @@ int soc_get_machine(struct udevice *dev, char *buf, int size);
 int soc_get_revision(struct udevice *dev, char *buf, int size);
 
 /**
- * soc_get_family() - Get family name of an SOC
+ * soc_get_family() - Get family name of an SoC
  * @dev:   Device to check (UCLASS_SOC)
  * @buf:   Buffer to place string
  * @size:  Size of string space
-- 
2.17.1

[PATCH v3 0/4] Add Renesas SoC identification driver support

[Biju Das]

This patch series aims to support Renesas SoC identification driver.

Added a helper function of_match_node to find the matching of_match structure.
This helper function can be used to replace the following code in u-boot [1] 
and [2]

[1] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/serial/serial_uniphier.c#L129
[2] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/usb/phy/rockchip_usb2_phy.c#L77

Also added soc_id attribute support in UCLASS_SOC which is required for Renesas
SoC identification driver similar to mainline linux.

Biju Das (4):
  dm: core: Add of_match_node helper function
  soc: Fix comments from SOC to SoC
  dm: soc: Add SoC id for attribute matching
  dm: soc: SoC identification driver for Renesas SoC's

 drivers/core/device.c |  21 
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   1 +
 drivers/soc/soc-uclass.c  |  19 ++-
 drivers/soc/soc_renesas.c | 239 ++
 drivers/soc/soc_sandbox.c |   8 ++
 include/dm/device.h   |  13 +++
 include/soc.h |  39 ++-
 test/dm/core.c|  31 +
 test/dm/soc.c |   8 ++
 10 files changed, 379 insertions(+), 7 deletions(-)
 create mode 100644 drivers/soc/soc_renesas.c

-- 
2.17.1

[PATCH v3 1/4] dm: core: Add of_match_node helper function

[Biju Das]

Add of_match_node() helper function to iterate over the device tree
and tell if a device_node has a matching of_match structure.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v2->v3:
 * Added a test case for of_match_node helper function.
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201102150959.4793-2-biju.das...@bp.renesas.com/)
v1->v2:
  * No Change.
---
 drivers/core/device.c | 21 +
 include/dm/device.h   | 13 +
 test/dm/core.c| 31 +++
 3 files changed, 65 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 4b3dcb3b37..5db4c5e78b 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -1010,6 +1010,27 @@ bool of_machine_is_compatible(const char *compat)
return !fdt_node_check_compatible(fdt, 0, compat);
 }
 
+static
+const struct udevice_id *__of_match_node(const struct udevice_id *matches,
+const ofnode node)
+{
+   if (!matches)
+   return NULL;
+
+   for (; matches->compatible; matches++) {
+   if (ofnode_device_is_compatible(node, matches->compatible))
+   return matches;
+   }
+
+   return NULL;
+}
+
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node)
+{
+   return __of_match_node(matches, node);
+}
+
 int dev_disable_by_path(const char *path)
 {
struct uclass *uc;
diff --git a/include/dm/device.h b/include/dm/device.h
index 5bef484247..4c357d46ec 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -754,6 +754,19 @@ bool device_is_compatible(const struct udevice *dev, const 
char *compat);
  */
 bool of_machine_is_compatible(const char *compat);
 
+/**
+ * of_match_node() - Tell if a device_node has a matching of_match structure
+ *
+ *
+ * Low level utility function used by device matching.
+ *
+ * @matches:   array of of device match structures to search in
+ * @node:  the of device structure to match against
+ * @return matching structure on success, NULL if the match is not found
+ */
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node);
+
 /**
  * dev_disable_by_path() - Disable a device given its device tree path
  *
diff --git a/test/dm/core.c b/test/dm/core.c
index 6f380a574c..b94b78d9ba 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1066,3 +1067,33 @@ static int dm_test_inactive_child(struct unit_test_state 
*uts)
return 0;
 }
 DM_TEST(dm_test_inactive_child, UT_TESTF_SCAN_PDATA);
+
+static int dm_test_of_match_node(struct unit_test_state *uts)
+{
+   const ulong test_data_expected = 0x1234;
+   ofnode root_node = ofnode_path("/");
+   const struct udevice_id *match;
+   unsigned long match_data;
+
+   const struct udevice_id soc_device_ids[] = {
+   { .compatible = "sandbox", .data = test_data_expected, },
+   { /* sentinel */ }
+   };
+
+   const struct udevice_id soc_device_nomatch_ids[] = {
+   { .compatible = "sandbox123", .data = test_data_expected, },
+   { /* sentinel */ }
+   };
+
+   match = of_match_node(soc_device_ids, root_node);
+   ut_assert(match);
+
+   match_data = match->data;
+   ut_asserteq(match_data, test_data_expected);
+
+   match = of_match_node(soc_device_nomatch_ids, root_node);
+   ut_asserteq_ptr(match, NULL);
+
+   return 0;
+}
+DM_TEST(dm_test_of_match_node, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-- 
2.17.1

RE: [PATCH v2 2/3] dm: soc: Add SoC id for attribute matching

[Biju Das]

Hi Simon,

Thanks for the feedback.

> Subject: Re: [PATCH v2 2/3] dm: soc: Add SoC id for attribute matching
> 
> Hi Biju,
> 
> On Mon, 2 Nov 2020 at 08:10, Biju Das  wrote:
> >
> > Add SoC identification string for attribute matching.
> > Also changed the comments from "an SOC" to "an SoC".
> 
> Please put this second bit in a separate patch, perhaps before this one in the
> series.

OK. Will split the patch into two and post v3.

Regards,
Biju

> Otherwise it looks good to me.
> 
> 
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar  lad...@bp.renesas.com>
> > ---
> > v1->v2: Changed the comments from "a SoC" to "an SoC"
> > ---
> >  drivers/soc/soc-uclass.c  | 19 ++-
> > drivers/soc/soc_sandbox.c |  8 
> >  include/soc.h | 39 +--
> >  test/dm/soc.c |  8 
> >  4 files changed, 67 insertions(+), 7 deletions(-)
> >

RE: [PATCH v2 1/3] dm: core: Add of_match_node helper function

[Biju Das]

Hi Simon,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/3] dm: core: Add of_match_node helper function
> 
> On Mon, 2 Nov 2020 at 08:10, Biju Das  wrote:
> >
> > Add of_match_node() helper function to iterate over the device tree
> > and tell if a device_node has a matching of_match structure.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar  lad...@bp.renesas.com>
> > ---
> > v1->v2:
> >   * No Change.
> >
> > ---
> >  drivers/core/device.c | 21 +
> >  include/dm/device.h   | 13 +
> >  2 files changed, 34 insertions(+)
> >
> 
> Please do add a test for this, perhaps in test/dm/core.c

OK, Will post v3 including the test.

Regards,
Biju

> 
> Regards,
> Simon

RE: [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support

[Biju Das]

Hi Marek,

> Subject: Re: [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support
> 
> On 11/2/20 5:16 PM, Biju Das wrote:
> > This patch series adds the required SoC/Board support to boot HopeRun
> > HiHope RZ/G2[HMN] boards.
> >
> > It uses SoC driver for unique cpu identification for RZ/G and R-Car
> > SoC's, since they share same PRR ID.
> >
> > SDHI quirks added using soc_device_match api.
> 
> Can you please split this into driver patch series and board patch series ? 
> And
> before you resend it, lets figure out the SoC identification first.

Ok, will split this series into driver patch series and board patch series. 
Will resend the patches after concluding SoC identification first.

Regards,
Biju

> Note that the driver patches look _much_ nicer, thanks.

RE: [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Biju Das]

Hi Jaehoon Chung,

Thanks for the feedback.

> Subject: Re: [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3
> and RZ/G2H
> 
> Hi,
> 
> On 11/3/20 1:16 AM, Biju Das wrote:
> > Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
> 
> Does it needs to use quirks? IMO, Using fixup for each SoC is better than
> quirks.

This work is based on linux[1]. For maintainability we want to make u-boot code 
similar to linux, so that in future if there
is any improvement in linux we can port here easily.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/renesas_sdhi_core.c?h=v5.10-rc2#n886

Regards,
Biju

> 
> Best Regards,
> Jaehoon Chung
> 
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar  lad...@bp.renesas.com>
> > ---
> >  v6: New patch. Quirks using soc_device_match.
> > ---
> >  drivers/mmc/renesas-sdhi.c | 37
> -
> >  1 file changed, 36 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> > index 0e4a44d973..e19daf8bf8 100644
> > --- a/drivers/mmc/renesas-sdhi.c
> > +++ b/drivers/mmc/renesas-sdhi.c
> > @@ -875,6 +875,16 @@ static const struct renesas_sdhi_quirks
> sdhi_quirks_4tap_nohs400 = {
> > .hs400_4taps = true,
> >  };
> >
> > +static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
> > +   .hs400_4taps = true,
> > +   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), };
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
> > +   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> > +   .hs400_calib_table = r8a7795_calib_table, };
> > +
> >  static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> > .hs400_4taps = true,
> > .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), @@ -916,6
> > +926,30 @@ static const struct soc_attr sdhi_quirks_match[]  = {
> > { .soc_id = "r8a774b1",
> >   .data = _quirks_r8a77965
> > },
> > +   { .soc_id = "r8a774e1",
> > + .revision = "ES2.0",
> > + .data = _quirks_4tap
> > +   },
> > +   { .soc_id = "r8a774e1",
> > + .revision = "ES3.0",
> > + .data = _quirks_r8a7795_es30
> > +   },
> > +   { .soc_id = "r8a7795",
> > + .revision = "ES1.0",
> > + .data = _quirks_4tap_nohs400_b17_dtrend
> > +   },
> > +   { .soc_id = "r8a7795",
> > + .revision = "ES1.1",
> > + .data = _quirks_4tap_nohs400_b17_dtrend
> > +   },
> > +   { .soc_id = "r8a7795",
> > + .revision = "ES2.0",
> > + .data = _quirks_4tap
> > +   },
> > +   { .soc_id = "r8a7795",
> > + .revision = "ES3.0",
> > + .data = _quirks_r8a7795_es30
> > +   },
> > { .soc_id = "r8a7796",
> >   .revision = "ES1.0",
> >   .data = _quirks_4tap_nohs400_b17_dtrend
> > @@ -965,7 +999,8 @@ static void renesas_sdhi_add_quirks(struct
> tmio_sd_plat *plat,
> > if (quirks == _quirks_r8a7796_es12 ||
> > quirks == _quirks_r8a77965)
> > priv->adjust_hs400_offset = 3;
> > -   else if (quirks == _quirks_r8a7796_es13)
> > +   else if (quirks == _quirks_r8a7796_es13 ||
> > +quirks == _quirks_r8a7795_es30)
> > priv->adjust_hs400_offset = 0;
> > }
> >  }
> >

RE: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Hi Jaehoon Chung,

Thanks for the feedback.

> Subject: Re: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car
> M3-W and RZ/G2M
> 
> On 11/3/20 1:16 AM, Biju Das wrote:
> > Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar  lad...@bp.renesas.com>
> > ---
> >  drivers/mmc/renesas-sdhi.c | 110
> > +
> >  1 file changed, 110 insertions(+)
> >
> > diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> > index d80b3fc28f..39deeb94d8 100644
> > --- a/drivers/mmc/renesas-sdhi.c
> > +++ b/drivers/mmc/renesas-sdhi.c
> > @@ -19,6 +19,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include "tmio-common.h"
> >
> > @@ -105,6 +106,15 @@ static const u8
> r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
> >  12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
> > };
> >
> > +#define SDHI_CALIB_TABLE_MAX 32
> > +
> > +struct renesas_sdhi_quirks {
> > +   bool hs400_disabled;
> > +   bool hs400_4taps;
> > +   u32 hs400_bad_taps;
> > +   const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
> > +};
> > +
> >  static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)  {
> > /* On R-Car Gen3, MMC0 is at 0xee14 */ @@ -855,6 +865,99 @@
> > static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
> > return clk_get_rate(>clk);
> >  }
> >
> > +static const struct renesas_sdhi_quirks
> sdhi_quirks_4tap_nohs400_b17_dtrend = {
> > +   .hs400_disabled = true,
> > +   .hs400_4taps = true,
> > +};
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> > +   .hs400_disabled = true,
> > +   .hs400_4taps = true,
> > +};
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> > +   .hs400_4taps = true,
> > +   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> 
> Use Macro, not magic code. We don't know what mean BIT(2), BIT(3), BIT(6)..

This work is based on linux[1]. For maintainability we want to make u-boot code 
similar to linux, so that in future if there
is any improvement in linux we can port here.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/renesas_sdhi_core.c?h=v5.10-rc2#n886

> 
> > +   .hs400_calib_table = r8a7796_rev1_calib_table, };
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
> > +   .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
> 
> Ditto.
> 
> > +   .hs400_calib_table = r8a7796_rev3_calib_table, };
> > +
> > +/*
> > + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of
> now.
> > + * So, we want to treat them equally and only have a match for ES1.2
> > +to enforce
> > + * this if there ever will be a way to distinguish ES1.2.
> > + */
> > +static const struct soc_attr sdhi_quirks_match[]  = {
> > +   { .soc_id = "r8a774a1",
> > + .revision = "ES1.0",
> > + .data = _quirks_4tap_nohs400_b17_dtrend
> > +   },
> > +   { .soc_id = "r8a774a1",
> > + .revision = "ES1.1",
> > + .data = _quirks_4tap_nohs400
> > +   },
> > +   { .soc_id = "r8a774a1",
> > + .revision = "ES1.2",
> > + .data = _quirks_r8a7796_es12
> > +   },
> > +   { .soc_id = "r8a774a1",
> > + .revision = "ES1.3",
> > + .data = _quirks_r8a7796_es13
> > +   },
> > +   { .soc_id = "r8a7796",
> > + .revision = "ES1.0",
> > + .data = _quirks_4tap_nohs400_b17_dtrend
> > +   },
> > +   { .soc_id = "r8a7796",
> > + .revision = "ES1.1",
> > + .data = _quirks_4tap_nohs400
> > +   },
> > +   { .soc_id = "r8a7796",
> > + .revision = "ES1.2",
> > + .data = _quirks_r8a7796_es12
> > +   },
> > +   { .soc_id = "r8a7796",
> > + .revision = "ES1.3",
> > + .data = _quirks_r8a7796_es13
> > +   },
> > +   { /* Sentinel. */ },
> > +};
> > +
> > +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> > +   struct tmio_sd_priv *priv,
> > +   const struct renesas_sdhi_quirks *quirks) {
> > +   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
> > +
> > +

RE: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

> Subject: Re: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> On 11/1/20 8:26 PM, Biju Das wrote:
> > Hi Marek,
> 
> Hi,
> 
> [...]
> 
> >>> @@ -23,7 +48,9 @@ static u32 rmobile_get_prr(void)
> >>>
> >>>   u32 rmobile_get_cpu_type(void)
> >>>   {
> >>> - return (rmobile_get_prr() & 0x7F00) >> 8;
> >>> + const u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
> >>
> >> The soc_id = ... can be inlined into get_cpu_type().
> >>
> >> However, you might want to cache the result of rmobile_get_cpu_type()
> >> , because doing OF match every time this is called is expensive.
> >
> > I agree calling OF match is expensive. So I have ported Renesas SoC
> > identification driver  from Linux to u-boot which will cache the
> > family type, soc_id and revision. I already sent a patch for
> > supporting soc_id in UCLASS_SOC in ML[4] [4]
> >
> https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> > work.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201030140724.12773-
> 1-bij
> >
> u.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.r
> enes
> >
> as.com%7C23804e7d89d0437047b308d87f654edd%7C53d82571da1947e49cb4
> 625a16
> >
> 6a4a2a%7C0%7C1%7C637399420383910105%7CUnknown%7CTWFpbGZsb3d8
> eyJWIjoiMC
> >
> 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&
> amp;sd
> >
> ata=%2Bu6HZyimz2%2Froy%2FEfTAzAxXupL0hDSBGUqT4%2B%2F2lVJ8%3D&
> amp;reser
> > ved=0
> >
> > On the next version, I will send Renesas SoC identification driver,
> > which supports caching family type which can be used to provide unique
> identification for CPU type.
> 
> Please make sure to check it on RCar2 as well, those use SPL and the SPL size
> is quite limited.

Currently SoC identification driver is enabled only for RZ/G2 boards and 
support is added to both R-Car Gen3 and RZ/G2 devices.

For the disabled case, the UCLASS-SOC class functions are inlined to "NULL"  
for soc_device_match and rest of the api's it is "-ENOSYS".

I agree, in future we need to add support for RCar2 as well, since we are going 
to add u-boot support for RZ/G1 devices.
Please find the size details related to R-Car Gen2(by adding support for R-Car 
M2-W and RZ/G1M SoC).

There is increase of 944 bytes, for R-Car Gen2 device, if we enable Renesas SoC 
identification driver for Gen2 devices.

Current u-boot-sh/master
---
$ ls -al u-boot.bin 
-rw-r--r-- 1 biju biju 523001 Nov  3 09:16 u-boot.bin

Current u-boot-sh/master + SoC renesas driver (R-Car M2-W enabled only case)

$ ls -al u-boot.bin 
-rw-r--r-- 1 biju biju 523945 Nov  3 09:47 u-boot.bin

If you agree, we will add support for Gen2 to SoC identification driver later. 
Currently there is no users for using it.
Please let me know.

Regards,
Biju

RE: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Hi All,

Please ignore this patch, it is giving compilation error for ARM 32 platforms. 
I will post v7 fixing this error.

   arm:  +   blanche
+drivers/mmc/renesas-sdhi.c:868:21: error: variable 
'sdhi_quirks_4tap_nohs400_b17_dtrend' has initializer but incomplete type
+  868 | static const struct renesas_sdhi_quirks 
sdhi_quirks_4tap_nohs400_b17_dtrend = {
+  |

Regards,
Biju

> Subject: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W
> and RZ/G2M
> 
> Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Lad Prabhakar 
> ---
>  v5->v6: Used soc_device_match api to add quirks.
>  v5 : New Patch
> (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201008085941.3600-2-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp
> .renesas.com%7Ca8731933d03d4e7e826f08d87f4ab9bd%7C53d82571da1947e
> 49cb4625a166a4a2a%7C0%7C0%7C637399306207070943%7CUnknown%7CTW
> FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> VCI6Mn0%3D%7C1000sdata=YEZTOITdq0M0iLuBr%2BLd9QTo3oe6hfy
> wNTl9bODUS6c%3Dreserved=0)
> ---
>  drivers/mmc/renesas-sdhi.c | 110
> +
>  1 file changed, 110 insertions(+)
> 
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index
> d80b3fc28f..39deeb94d8 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -19,6 +19,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include "tmio-common.h"
> 
> @@ -105,6 +106,15 @@ static const u8
> r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
>12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }  };
> 
> +#define SDHI_CALIB_TABLE_MAX 32
> +
> +struct renesas_sdhi_quirks {
> + bool hs400_disabled;
> + bool hs400_4taps;
> + u32 hs400_bad_taps;
> + const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
> +};
> +
>  static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)  {
>   /* On R-Car Gen3, MMC0 is at 0xee14 */ @@ -855,6 +865,99 @@
> static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
>   return clk_get_rate(>clk);
>  }
> 
> +static const struct renesas_sdhi_quirks
> sdhi_quirks_4tap_nohs400_b17_dtrend = {
> + .hs400_disabled = true,
> + .hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> + .hs400_disabled = true,
> + .hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> + .hs400_4taps = true,
> + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> + .hs400_calib_table = r8a7796_rev1_calib_table, };
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
> + .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
> + .hs400_calib_table = r8a7796_rev3_calib_table, };
> +
> +/*
> + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
> + * So, we want to treat them equally and only have a match for ES1.2 to
> +enforce
> + * this if there ever will be a way to distinguish ES1.2.
> + */
> +static const struct soc_attr sdhi_quirks_match[]  = {
> + { .soc_id = "r8a774a1",
> +   .revision = "ES1.0",
> +   .data = _quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a774a1",
> +   .revision = "ES1.1",
> +   .data = _quirks_4tap_nohs400
> + },
> + { .soc_id = "r8a774a1",
> +   .revision = "ES1.2",
> +   .data = _quirks_r8a7796_es12
> + },
> + { .soc_id = "r8a774a1",
> +   .revision = "ES1.3",
> +   .data = _quirks_r8a7796_es13
> + },
> + { .soc_id = "r8a7796",
> +   .revision = "ES1.0",
> +   .data = _quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a7796",
> +   .revision = "ES1.1",
> +   .data = _quirks_4tap_nohs400
> + },
> + { .soc_id = "r8a7796",
> +   .revision = "ES1.2",
> +   .data = _quirks_r8a7796_es12
> + },
> + { .soc_id = "r8a7796",
> +   .revision = "ES1.3",
> +   .data = _quirks_r8a7796_es13
> + },
> + { /* Sentinel. */ },
> +};
> +
> +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> + struct tmio_sd_priv *priv,
> + const struct renesas_sdhi_quirks *quirks) {
> + priv-

[PATCH v6 7/7] arm: rmobile: Add HopeRun HiHope RZ/G2H board support

[Biju Das]

The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.

DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and
r8a774e1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9").

This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v6: New patch.
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 15 +++
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 +++
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts| 26 ++
 arch/arm/dts/r8a774e1-u-boot.dtsi | 25 +
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  6 -
 configs/hihope_rzg2_defconfig |  2 +-
 8 files changed, 101 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9f14fb13ec..3715640bbb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -794,6 +794,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
+   r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 00..265355e0de
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+"renesas,r8a774e1";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
new file mode 100644
index 00..03a17bac7e
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "r8a774e1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts 
b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 00..cdbe527e93
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+   compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@5 {
+   device_type = "memory";
+   reg = <0x5 0x 0x0 0x8000>;
+   };
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi 
b/arch/arm/dts/r8a774e1-u-boot.dtsi
new file mode 100644
index 00..30c38dcfba
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ 
+/delete-node/ _sound;
+/delete-node/ 
+/delete-node/ _ca

[PATCH v6 5/7] arm: rmobile: Add HopeRun HiHope RZ/G2N board support

[Biju Das]

The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.

DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9")

This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v6: New patch
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 16 ++
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts| 41 ++
 arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++
 arch/arm/mach-rmobile/Kconfig.64  |  1 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  6 ++-
 configs/hihope_rzg2_defconfig |  2 +-
 8 files changed, 145 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba46785078..9f14fb13ec 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -793,6 +793,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
+   r8a774b1-hihope-rzg2n-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 00..a3edd55113
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N with sub board";
+   compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+"renesas,r8a774b1";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 00..09378a70a2
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+ {
+   bt_reg_on{
+   gpio-hog;
+   gpios = <13 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "bt-reg-on";
+   };
+};
+
+ {
+   wlan_reg_on{
+   gpio-hog;
+   gpios = <6 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "wlan-reg-on";
+   };
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts 
b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 00..f1883cbd1a
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+   model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+   compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@48000 {
+   device_type = "memory";
+   reg = <0x4 0x8000 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+<_clk>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+ {
+   mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi 
b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 00..2c0319fc39
--- /dev/null
+++ b/arch/arm/dts/r8a

[PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v5->v6: Used soc_device_match api to add quirks.
 v5 : New Patch
(Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-2-biju.das...@bp.renesas.com/)
---
 drivers/mmc/renesas-sdhi.c | 110 +
 1 file changed, 110 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d80b3fc28f..39deeb94d8 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "tmio-common.h"
 
@@ -105,6 +106,15 @@ static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = 
{
 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
 };
 
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+   bool hs400_disabled;
+   bool hs400_4taps;
+   u32 hs400_bad_taps;
+   const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
 {
/* On R-Car Gen3, MMC0 is at 0xee14 */
@@ -855,6 +865,99 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv 
*priv)
return clk_get_rate(>clk);
 }
 
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+   .hs400_disabled = true,
+   .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+   .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+   .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[]  = {
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = _quirks_r8a7796_es12
+   },
+   { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = _quirks_r8a7796_es13
+   },
+   { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+   struct tmio_sd_priv *priv,
+   const struct renesas_sdhi_quirks *quirks)
+{
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+
+   if (quirks && quirks->hs400_disabled) {
+   plat->cfg.host_caps &= ~MMC_MODE_HS400;
+   if (quirks == _quirks_4tap_nohs400_b17_dtrend)
+   priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+   }
+
+   if (quirks && quirks->hs400_4taps)
+   priv->nrtaps = 4;
+   else
+   priv->nrtaps = 8;
+
+   if (quirks && quirks->hs400_bad_taps)
+   priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+   if (quirks && quirks->hs400_calib_table) {
+   priv->adjust_hs400_enable = true;
+   priv->adjust_hs400_calib_table =
+   quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+   if (quirks == _quirks_r8a7796_es12)
+   priv->adjust_hs400_offset = 3;
+   else if (quirks == _quirks_r8a7796_es13)
+   priv->adjust_hs400_offset = 0;
+   }
+}
+
 static void renesas_sdhi_filter_caps(struct udevice *dev)
 {
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +969,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 CONFIG_IS_ENABLED(MMC_HS400_SUPPOR

[PATCH v6 1/7] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.

RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).

As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v5->v6
   * Optimized the unique CPU identification method by using Renesas SoC 
identification driver.
 v4->v5
   * Add support for unique identification of RZ/G2 CPU types
 (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das...@bp.renesas.com/)
 v3->v4
   * Dropped CPU info reporting logic for RZ/G2. Will address this later.
   * Added PRRID's for RZG2[HMNE]
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das...@bp.renesas.com/)

 v2->v3  
   * Reworked as per Marek's suggestion
   * Added rzg2_get_cpu_type function to get cpu_type by matching TFA 
compatible string
   * Removed SoC family type Enum
   (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das...@bp.renesas.com/)

 v1->v2:
  * Add comment's related to loop logic
   (ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das...@bp.renesas.com/)

 v1:
  * New patch
  
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das...@bp.renesas.com/
---
 arch/arm/mach-rmobile/cpu_info-rcar.c| 22 ++-
 arch/arm/mach-rmobile/cpu_info.c | 10 +++-
 arch/arm/mach-rmobile/include/mach/rmobile.h | 60 +++-
 3 files changed, 73 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c 
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..08345503a2 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -6,6 +6,7 @@
  */
 #include 
 #include 
+#include 
 
 #define PRR_MASK   0x7fff
 #define R8A7796_REV_1_00x5200
@@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
 #endif
 }
 
+static bool is_rzg_family(void)
+{
+   bool rzg_family_type = false;
+   struct udevice *soc;
+   char name[16];
+
+   if (!(soc_get() || soc_get_family(soc, name, 16))) {
+   if (!strcmp(name, "RZ/G2"))
+   rzg_family_type = true;
+   }
+
+   return rzg_family_type;
+}
+
 u32 rmobile_get_cpu_type(void)
 {
-   return (rmobile_get_prr() & 0x7F00) >> 8;
+   u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
+
+   if (is_rzg_family())
+   soc_id |= RZG_CPU_MASK;
+
+   return soc_id;
 }
 
 u32 rmobile_get_cpu_rev_integer(void)
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..b19b7e3044 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,12 +3,12 @@
  * (C) Copyright 2012 Nobuhiro Iwamatsu 
  * (C) Copyright 2012 Renesas Solutions Corp.
  */
-#include 
-#include 
 #include 
-#include 
 #include 
+#include 
+#include 
 #include 
+#include 
 #include 
 
 #ifdef CONFIG_ARCH_CPU_INIT
@@ -59,6 +59,10 @@ static const struct {
 } rmobile_cpuinfo[] = {
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
+   { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
+   { RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
+   { RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
+   { RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..da099fa4c3 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -24,21 +24,51 @@
 #endif
 #endif /* CONFIG_ARCH_RMOBILE */
 
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_SH73A00x37
-#define RMOBILE_CPU_TYPE_R8A7740   0x40
-#define RMOBILE_CPU_TYPE_R8A7790   0x45
-#define RMOBILE_CPU_TYPE_R8A7791   0x47
-#define RMOBILE_CPU_TYPE_R8A7792   0x4A
-#define RMOBILE_CPU_TYPE_R8A7793   0x4B
-#define RMOBILE_CPU_TYPE_R8A7794   0x4C
-#define RMOBILE_CPU_TYPE_R8A7795   0x4F
-#define RMOBILE_CPU_TYPE_R8A7796   0x52
-#define RMOBILE_CPU_TYPE_R8A77965  0x55
-#define RMOBILE_CPU_TYPE_R8A77970  0x54
-#define RMOBILE_CPU_TYPE_R8A77980  0x56
-#define RMOBILE_CPU_TYPE_R8A77990  0x57
-#define RMOBILE_CPU_TYPE_R8A77995  0x58
+/* PRR IDs */
+#define SOC_ID_SH73A0  0x37
+#define SOC_ID_R8A7740 0x40
+#define

[PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Biju Das]

Add SDHI quirks for R-Car H3 and RZ/G2H SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v6: New patch. Quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 37 -
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 0e4a44d973..e19daf8bf8 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -875,6 +875,16 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+   .hs400_4taps = true,
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a7795_calib_table,
+};
+
 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -916,6 +926,30 @@ static const struct soc_attr sdhi_quirks_match[]  = {
{ .soc_id = "r8a774b1",
  .data = _quirks_r8a77965
},
+   { .soc_id = "r8a774e1",
+ .revision = "ES2.0",
+ .data = _quirks_4tap
+   },
+   { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = _quirks_4tap_nohs400_b17_dtrend
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = _quirks_4tap
+   },
+   { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = _quirks_r8a7795_es30
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -965,7 +999,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
if (quirks == _quirks_r8a7796_es12 ||
quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
-   else if (quirks == _quirks_r8a7796_es13)
+   else if (quirks == _quirks_r8a7796_es13 ||
+quirks == _quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
 }
-- 
2.17.1

[PATCH v6 4/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N

[Biju Das]

Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
 v6: New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 39deeb94d8..0e4a44d973 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -886,6 +886,11 @@ static const struct renesas_sdhi_quirks 
sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+   .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+   .hs400_calib_table = r8a77965_calib_table,
+};
+
 /*
  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
  * So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -908,6 +913,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a774b1",
+ .data = _quirks_r8a77965
+   },
{ .soc_id = "r8a7796",
  .revision = "ES1.0",
  .data = _quirks_4tap_nohs400_b17_dtrend
@@ -924,6 +932,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
  .revision = "ES1.3",
  .data = _quirks_r8a7796_es13
},
+   { .soc_id = "r8a77965",
+ .data = _quirks_r8a77965
+   },
{ /* Sentinel. */ },
 };
 
@@ -951,7 +962,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat 
*plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
-   if (quirks == _quirks_r8a7796_es12)
+   if (quirks == _quirks_r8a7796_es12 ||
+   quirks == _quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == _quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
-- 
2.17.1

[PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support

[Biju Das]

This patch series adds the required SoC/Board support to boot HopeRun 
HiHope RZ/G2[HMN] boards.

It uses SoC driver for unique cpu identification for RZ/G and R-Car SoC's,
since they share same PRR ID.

SDHI quirks added using soc_device_match api.

This patch series depend upon [1]
[1] https://lists.denx.de/pipermail/u-boot/2020-November/431539.html

Note:
 1) This patch series tested on RZ/G2[HMN] boards.
 2) SOC_DEVICE_RENESAS option enabled only RZ/G2[HMN] boards. After testing
this needs to be enabled for other boards.


Biju Das (7):
  arm: rmobile: Add RZ/G2[HMNE] SoC support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
  arm: rmobile: Add HopeRun HiHope RZ/G2M board support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
  arm: rmobile: Add HopeRun HiHope RZ/G2N board support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
  arm: rmobile: Add HopeRun HiHope RZ/G2H board support

 arch/arm/dts/Makefile |   3 +
 arch/arm/dts/hihope-common.dtsi   | 377 ++
 arch/arm/dts/hihope-rev4.dtsi | 124 ++
 arch/arm/dts/hihope-rzg2-ex.dtsi  |  92 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts |  21 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts |  27 ++
 arch/arm/dts/r8a774a1-hihope-rzg2m.dts|  37 ++
 arch/arm/dts/r8a774a1-u-boot.dtsi |  55 +++
 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts |  16 +
 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts |  27 ++
 arch/arm/dts/r8a774b1-hihope-rzg2n.dts|  41 ++
 arch/arm/dts/r8a774b1-u-boot.dtsi |  53 +++
 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts |  15 +
 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts |  27 ++
 arch/arm/dts/r8a774e1-hihope-rzg2h.dts|  26 ++
 arch/arm/dts/r8a774e1-u-boot.dtsi |  25 ++
 arch/arm/mach-rmobile/Kconfig.64  |  16 +
 arch/arm/mach-rmobile/cpu_info-rcar.c |  22 +-
 arch/arm/mach-rmobile/cpu_info.c  |  10 +-
 arch/arm/mach-rmobile/include/mach/rmobile.h  |  60 ++-
 board/hoperun/hihope-rzg2/Kconfig |  15 +
 board/hoperun/hihope-rzg2/MAINTAINERS |   6 +
 board/hoperun/hihope-rzg2/Makefile|   9 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  99 +
 configs/hihope_rzg2_defconfig |  77 
 drivers/mmc/renesas-sdhi.c| 157 
 include/configs/hihope-rzg2.h |  20 +
 27 files changed, 1438 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/dts/hihope-common.dtsi
 create mode 100644 arch/arm/dts/hihope-rev4.dtsi
 create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
 create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
 create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
 create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

-- 
2.17.1

[PATCH v6 3/7] arm: rmobile: Add HopeRun HiHope RZ/G2M board support

[Biju Das]

The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.

DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9").

This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v5->v6
  * Rebased to U-boot-sh/master
  * Changed the logic for USB0 channel0 Host support.
  * Enabled CONFIG_SOC_DEVICE_RENESAS option

V4->V5
  * Rebased to U-boot-sh/next
  (Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201012151616.5384-4-biju.das...@bp.renesas.com/)

V3->V4
  * Added USB0 channel0 Host support
(Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-2-biju.das...@bp.renesas.com/)
V2->V3  
   * Reworked as per Marek's suggestion
   * Added rzg2_get_cpu_type function to get cpu_type by matching TFA 
compatible string
   * Removed SoC family type Enum
   Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-3-biju.das...@bp.renesas.com/

V1->V2
 * Fixed indentation for R8A774A1 config
 * Used GPIO hog for setting WLAN/BT REG ON
 * Removed USB related initialization
  Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-2-biju.das...@bp.renesas.com/

V1:-
 * New Patch
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-5-biju.das...@bp.renesas.com/
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/hihope-common.dtsi   | 377 ++
 arch/arm/dts/hihope-rev4.dtsi | 124 ++
 arch/arm/dts/hihope-rzg2-ex.dtsi  |  92 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts |  21 +
 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts |  27 ++
 arch/arm/dts/r8a774a1-hihope-rzg2m.dts|  37 ++
 arch/arm/dts/r8a774a1-u-boot.dtsi |  55 +++
 arch/arm/mach-rmobile/Kconfig.64  |  14 +
 board/hoperun/hihope-rzg2/Kconfig |  15 +
 board/hoperun/hihope-rzg2/MAINTAINERS |   6 +
 board/hoperun/hihope-rzg2/Makefile|   9 +
 board/hoperun/hihope-rzg2/hihope-rzg2.c   |  91 +
 configs/hihope_rzg2_defconfig |  77 
 include/configs/hihope-rzg2.h |  20 +
 15 files changed, 966 insertions(+)
 create mode 100644 arch/arm/dts/hihope-common.dtsi
 create mode 100644 arch/arm/dts/hihope-rev4.dtsi
 create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
 create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
 create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
 create mode 100644 board/hoperun/hihope-rzg2/Kconfig
 create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
 create mode 100644 board/hoperun/hihope-rzg2/Makefile
 create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
 create mode 100644 configs/hihope_rzg2_defconfig
 create mode 100644 include/configs/hihope-rzg2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5362b73441..ba46785078 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -792,6 +792,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
 
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
+   r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
new file mode 100644
index 00..51eb74fbe9
--- /dev/null
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include 
+
+/ {
+   aliases {
+   serial0 = 
+   serial1 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel";
+   stdout-path = "serial0:115200n8";
+   };
+
+   hdmi0-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi0_con: endpoint {
+   remote-endpoint = <_dw_hdmi0_out>;
+   };
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   led1 {
+   gpios = < 12 GPIO_ACTIVE_HIGH>;
+   };
+
+   led2 {
+   gpios = < 13 GPIO_ACTIVE_HIGH>;
+   };
+
+   led3 {
+   gpios = <  0 GPI

[PATCH v2 2/3] dm: soc: Add SoC id for attribute matching

[Biju Das]

Add SoC identification string for attribute matching.
Also changed the comments from "an SOC" to "an SoC".

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v1->v2: Changed the comments from "a SoC" to "an SoC"
 Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201030140724.12773-1-biju.das...@bp.renesas.com/
---
 drivers/soc/soc-uclass.c  | 19 ++-
 drivers/soc/soc_sandbox.c |  8 
 include/soc.h | 39 +--
 test/dm/soc.c |  8 
 4 files changed, 67 insertions(+), 7 deletions(-)

diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index c32d647864..a3f8be841b 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int 
size)
return ops->get_revision(dev, buf, size);
 }
 
+int soc_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_ops *ops = soc_get_ops(dev);
+
+   if (!ops->get_soc_id)
+   return -ENOSYS;
+
+   return ops->get_soc_id(dev, buf, size);
+}
+
 const struct soc_attr *
 soc_device_match(const struct soc_attr *matches)
 {
@@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
 
while (1) {
if (!(matches->machine || matches->family ||
- matches->revision))
+ matches->revision || matches->soc_id))
break;
 
match = true;
@@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
}
}
 
+   if (matches->soc_id) {
+   if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
+   if (strcmp(matches->soc_id, str))
+   match = false;
+   }
+   }
+
if (match)
return matches;
 
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad84fc..1a81d3562a 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev, char 
*buf, int size)
return 0;
 }
 
+int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   snprintf(buf, size, "r8a774a1");
+
+   return 0;
+}
+
 static const struct soc_ops soc_sandbox_ops = {
.get_family = soc_sandbox_get_family,
.get_revision = soc_sandbox_get_revision,
.get_machine = soc_sandbox_get_machine,
+   .get_soc_id = soc_sandbox_get_soc_id,
 };
 
 int soc_sandbox_probe(struct udevice *dev)
diff --git a/include/soc.h b/include/soc.h
index a55eb1b572..db0e8880d1 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -20,18 +20,20 @@
  *variants. Example: am33
  * @machine  - Name of a specific SoC. Example: am3352
  * @revision - Name of a specific SoC revision. Example: SR1.1
+ * @soc_id   - SoC identification string. Example: r8a774a1
  * @data - A pointer to user data for the SoC variant
  */
 struct soc_attr {
const char *family;
const char *machine;
const char *revision;
+   const char *soc_id;
const void *data;
 };
 
 struct soc_ops {
/**
-* get_machine() - Get machine name of an SOC
+* get_machine() - Get machine name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -41,7 +43,7 @@ struct soc_ops {
int (*get_machine)(struct udevice *dev, char *buf, int size);
 
/**
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -51,7 +53,7 @@ struct soc_ops {
int (*get_revision)(struct udevice *dev, char *buf, int size);
 
/**
-* get_family() - Get family name of an SOC
+* get_family() - Get family name of an SoC
 *
 * @dev:Device to check (UCLASS_SOC)
 * @buf:Buffer to place string
@@ -59,6 +61,16 @@ struct soc_ops {
 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
 */
int (*get_family)(struct udevice *dev, char *buf, int size);
+
+   /**
+* get_soc_id() - Get SoC identification name of an SoC
+*
+* @dev:Device to check (UCLASS_SOC)
+* @buf:Buffer to place string
+* @size:   Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+*/
+   int (*get_soc_id)(struct udevice *dev, char *buf, int size);
 };
 
 #define soc_get_ops(dev)((struct soc_ops *)(dev)->driver->ops)
@@ -76,7 +88,7 @@ struct soc_o

[PATCH v2 3/3] dm: soc: SoC identification driver for Renesas SoC's

[Biju Das]

Add SoC identification driver for Renesas SoC's. This allows
to identify the SoC type and revision based on Product Register.

This can be checked where needed using soc_device_match().

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v2: New patch
---
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   1 +
 drivers/soc/soc_renesas.c | 239 ++
 3 files changed, 247 insertions(+)
 create mode 100644 drivers/soc/soc_renesas.c

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 864d00a885..475e94cd77 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -16,6 +16,13 @@ config SOC_DEVICE_TI_K3
  This allows Texas Instruments Keystone 3 SoCs to identify
  specifics about the SoC in use.
 
+config SOC_DEVICE_RENESAS
+   depends on SOC_DEVICE
+   bool "Enable SoC driver for Renesas SoCs"
+   help
+ This allows Renesas SoCs to identify specifics about the
+ SoC in use.
+
 source "drivers/soc/ti/Kconfig"
 
 endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 9ef20ca506..b143eac5fd 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,5 +4,6 @@
 
 obj-$(CONFIG_SOC_TI) += ti/
 obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
+obj-$(CONFIG_$(SPL_)SOC_DEVICE_RENESAS) += soc_renesas.o
 obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
 obj-$(CONFIG_SANDBOX) += soc_sandbox.o
diff --git a/drivers/soc/soc_renesas.c b/drivers/soc/soc_renesas.c
new file mode 100644
index 00..4543e0dbfd
--- /dev/null
+++ b/drivers/soc/soc_renesas.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct soc_renesas_priv {
+   const char *family;
+   const char *soc_id;
+   char revision[6];
+};
+
+struct renesas_family {
+   const char name[16];
+   u32 reg;/* CCCR or PRR, if not in DT */
+};
+
+static const struct renesas_family fam_rcar_gen3 __maybe_unused = {
+   .name   = "R-Car Gen3",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+static const struct renesas_family fam_rzg2 __maybe_unused = {
+   .name   = "RZ/G2",
+   .reg= 0xfff00044,   /* PRR (Product Register) */
+};
+
+struct renesas_soc {
+   const struct renesas_family *family;
+   u8 id;
+};
+
+#ifdef CONFIG_R8A774A1
+static const struct renesas_soc soc_rz_g2m = {
+   .family = _rzg2,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A774B1
+static const struct renesas_soc soc_rz_g2n = {
+   .family = _rzg2,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A774C0
+static const struct renesas_soc soc_rz_g2e = {
+   .family = _rzg2,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A774E1
+static const struct renesas_soc soc_rz_g2h = {
+   .family = _rzg2,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7795
+static const struct renesas_soc soc_rcar_h3 = {
+   .family = _rcar_gen3,
+   .id = 0x4f,
+};
+#endif
+
+#ifdef CONFIG_R8A7796
+static const struct renesas_soc soc_rcar_m3_w = {
+   .family = _rcar_gen3,
+   .id = 0x52,
+};
+#endif
+
+#ifdef CONFIG_R8A77965
+static const struct renesas_soc soc_rcar_m3_n = {
+   .family = _rcar_gen3,
+   .id = 0x55,
+};
+#endif
+
+#ifdef CONFIG_R8A77970
+static const struct renesas_soc soc_rcar_v3m = {
+   .family = _rcar_gen3,
+   .id = 0x54,
+};
+#endif
+
+#ifdef CONFIG_R8A77980
+static const struct renesas_soc soc_rcar_v3h = {
+   .family = _rcar_gen3,
+   .id = 0x56,
+};
+#endif
+
+#ifdef CONFIG_R8A77990
+static const struct renesas_soc soc_rcar_e3 = {
+   .family = _rcar_gen3,
+   .id = 0x57,
+};
+#endif
+
+#ifdef CONFIG_R8A77995
+static const struct renesas_soc soc_rcar_d3 = {
+   .family = _rcar_gen3,
+   .id = 0x58,
+};
+#endif
+
+static int soc_renesas_get_family(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->family);
+
+   return 0;
+}
+
+static int soc_renesas_get_revision(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->revision);
+
+   return 0;
+}
+
+static int soc_renesas_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+   struct soc_renesas_priv *priv = dev_get_priv(dev);
+
+   snprintf(buf, size, "%s", priv->soc_id);
+
+   return 0;
+}
+
+static const struct udevice_id renesas_socs[] = {
+#ifdef CONFIG_R8A774A1
+   { .compatible = "renesas,r8a774a1", .data = (ulong)_rz_g2m, },
+#endif
+#ifdef CONFIG_R8A774B1
+   { .compatible = "renesas,r8a774b1", .data = (ulong)_rz_g2n, },
+#endif
+#ifdef

[PATCH v2 0/3] Add Renesas SoC identification driver support

[Biju Das]

This patch series aims to support Renesas SoC identification driver.

Added a helper function of_match_node to find the matching of_match
structure. This helper function can be used to replace the following
code in u-boot [1] and [2]
[1] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/serial/serial_uniphier.c#L129
[2] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/usb/phy/rockchip_usb2_phy.c#L77

Also added soc_id attribute support in UCLASS_SOC which is required for Renesas 
SoC
identification driver similar to mainline linux.

Biju Das (3):
  dm: core: Add of_match_node helper function
  dm: soc: Add SoC id for attribute matching
  dm: soc: SoC identification driver for Renesas SoC's

 drivers/core/device.c |  21 
 drivers/soc/Kconfig   |   7 ++
 drivers/soc/Makefile  |   1 +
 drivers/soc/soc-uclass.c  |  19 ++-
 drivers/soc/soc_renesas.c | 239 ++
 drivers/soc/soc_sandbox.c |   8 ++
 include/dm/device.h   |  13 +++
 include/soc.h |  39 ++-
 test/dm/soc.c |   8 ++
 9 files changed, 348 insertions(+), 7 deletions(-)
 create mode 100644 drivers/soc/soc_renesas.c

-- 
2.17.1

[PATCH v2 1/3] dm: core: Add of_match_node helper function

[Biju Das]

Add of_match_node() helper function to iterate over the device tree
and tell if a device_node has a matching of_match structure.

Signed-off-by: Biju Das 
Reviewed-by: Lad Prabhakar 
---
v1->v2:
  * No Change. 
  Ref: 
https://patchwork.ozlabs.org/project/uboot/patch/20201030140303.11773-1-biju.das...@bp.renesas.com/
---
 drivers/core/device.c | 21 +
 include/dm/device.h   | 13 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 4b3dcb3b37..348d63dc59 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -1010,6 +1010,27 @@ bool of_machine_is_compatible(const char *compat)
return !fdt_node_check_compatible(fdt, 0, compat);
 }
 
+static
+const struct udevice_id *__of_match_node(const struct udevice_id *matches,
+const ofnode node)
+{
+   if (!matches)
+   return NULL;
+
+   for (; matches && matches->compatible; matches++) {
+   if (ofnode_device_is_compatible(node, matches->compatible))
+   return matches;
+   }
+
+   return NULL;
+}
+
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node)
+{
+   return __of_match_node(matches, node);
+}
+
 int dev_disable_by_path(const char *path)
 {
struct uclass *uc;
diff --git a/include/dm/device.h b/include/dm/device.h
index 5bef484247..4c357d46ec 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -754,6 +754,19 @@ bool device_is_compatible(const struct udevice *dev, const 
char *compat);
  */
 bool of_machine_is_compatible(const char *compat);
 
+/**
+ * of_match_node() - Tell if a device_node has a matching of_match structure
+ *
+ *
+ * Low level utility function used by device matching.
+ *
+ * @matches:   array of of device match structures to search in
+ * @node:  the of device structure to match against
+ * @return matching structure on success, NULL if the match is not found
+ */
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+  const ofnode node);
+
 /**
  * dev_disable_by_path() - Disable a device given its device tree path
  *
-- 
2.17.1

RE: [PATCH v5 2/2] mmc: renesas-sdhi: Add R8A774A1 SDHI quirks

[Biju Das]

Hi Marek,

> Subject: Re: [PATCH v5 2/2] mmc: renesas-sdhi: Add R8A774A1 SDHI quirks
> 
> On 10/8/20 10:59 AM, Biju Das wrote:
> > Add various SDHI quirks for R8A774A1 SoC.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Lad Prabhakar  lad...@bp.renesas.com>
> > ---
> >  v5 : New Patch
> > ---
> >  drivers/mmc/renesas-sdhi.c | 18 --
> >  1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> > index d80b3fc28f..40e01ed890 100644
> > --- a/drivers/mmc/renesas-sdhi.c
> > +++ b/drivers/mmc/renesas-sdhi.c
> > @@ -870,7 +870,8 @@ static void renesas_sdhi_filter_caps(struct udevice
> *dev)
> > /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
> > if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
> > (rmobile_get_cpu_rev_integer() <= 1)) ||
> > -   ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
> > +   (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) ||
> > +   (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A774A1)) &&
> 
> Hmm ... this code is growing real complex.
> 
> Would it be too hard to add soc_device_attribute (see Linux) to U-Boot and
> clean that code above up ? Or maybe there is already something similar in U-
> Boot to match on SoC revision ?

OK, Agreed. will use soc_device_match to add quirks.

Regards,
Biju

RE: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

> Subject: Re: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> On 10/8/20 10:59 AM, Biju Das wrote:
> 
> [...]
> 
> > +static const struct udevice_id tfa_cpu_info[] = {
> > +   { .compatible = "renesas,r8a774a1", .data =
> RMOBILE_CPU_TYPE_R8A774A1 },
> > +   { .compatible = "renesas,r8a774b1", .data =
> RMOBILE_CPU_TYPE_R8A774B1 },
> > +   { .compatible = "renesas,r8a774c0", .data =
> RMOBILE_CPU_TYPE_R8A774C0 },
> > +   { .compatible = "renesas,r8a774e1", .data =
> RMOBILE_CPU_TYPE_R8A774E1 },
> > +   { },
> > +};
> > +
> > +static const u32 get_cpu_type(u32 soc_id) {
> > +   const struct udevice_id *of_match = tfa_cpu_info;
> > +   int i;
> 
> Isn't there already a function in U-Boot which can match on a table of OF
> compatible strings ? I suspect when drivers match on their table of OF
> compatible strings, somesuch function must be used.

of_match function for matching device compatible string. But it doesn't match 
SoC compatible string.
So I added a helper function  is of_match_node[1] to search from rootnode to 
find the soc compatible string.

[1] 
http://patchwork.ozlabs.org/project/uboot/patch/20201030140303.11773-1-biju.das...@bp.renesas.com/

Apart from this, This helper function can be used to replace the below codes in 
u-boot tree [2] [3]

[2] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/serial/serial_uniphier.c#L129

[3] 
https://elixir.bootlin.com/u-boot/latest/source/drivers/usb/phy/rockchip_usb2_phy.c#L77


> > +   for (i = 0; i < ARRAY_SIZE(tfa_cpu_info); i++) {
> > +   if (soc_id == (of_match->data & PRODUCT_MASK) &&
> > +   of_machine_is_compatible(of_match->compatible))
> > +   return of_match->data;
> > +   of_match++;
> > +   }
> > +
> > +   return soc_id;
> > +}
> > +
> >  static u32 rmobile_get_prr(void)
> >  {
> >  #ifdef CONFIG_RCAR_GEN3
> > @@ -23,7 +48,9 @@ static u32 rmobile_get_prr(void)
> >
> >  u32 rmobile_get_cpu_type(void)
> >  {
> > -   return (rmobile_get_prr() & 0x7F00) >> 8;
> > +   const u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
> 
> The soc_id = ... can be inlined into get_cpu_type().
> 
> However, you might want to cache the result of rmobile_get_cpu_type() ,
> because doing OF match every time this is called is expensive.

I agree calling OF match is expensive. So I have ported Renesas SoC 
identification driver  from Linux to u-boot 
which will cache the family type, soc_id and revision. I already sent a patch 
for supporting soc_id in UCLASS_SOC in ML[4]
[4]  
http://patchwork.ozlabs.org/project/uboot/patch/20201030140724.12773-1-biju.das...@bp.renesas.com/

On the next version, I will send Renesas SoC identification driver, which 
supports caching family type which
can be used to provide unique identification for CPU type.

> > +
> > +   return get_cpu_type(soc_id);
> >  }
> 
> [...]
> 
> > +/* CPU IDs */
> > +#define RMOBILE_CPU_TYPE_SH73A0(SOC_ID_SH73A0)
> > +#define RMOBILE_CPU_TYPE_R8A7740   (SOC_ID_R8A7740)
> > +#define RMOBILE_CPU_TYPE_R8A774A1  (SOC_ID_R8A774A1 |
> RZG_CPU_MASK)
> > +#define RMOBILE_CPU_TYPE_R8A774B1  (SOC_ID_R8A774B1 |
> RZG_CPU_MASK)
> > +#define RMOBILE_CPU_TYPE_R8A774C0  (SOC_ID_R8A774C0 |
> RZG_CPU_MASK)
> > +#define RMOBILE_CPU_TYPE_R8A774E1  (SOC_ID_R8A774E1 |
> RZG_CPU_MASK)
> > +#define RMOBILE_CPU_TYPE_R8A7790   (SOC_ID_R8A7790)
> > +#define RMOBILE_CPU_TYPE_R8A7791   (SOC_ID_R8A7791)
> > +#define RMOBILE_CPU_TYPE_R8A7792   (SOC_ID_R8A7792)
> > +#define RMOBILE_CPU_TYPE_R8A7793   (SOC_ID_R8A7793)
> > +#define RMOBILE_CPU_TYPE_R8A7794   (SOC_ID_R8A7794)
> > +#define RMOBILE_CPU_TYPE_R8A7795   (SOC_ID_R8A7795)
> > +#define RMOBILE_CPU_TYPE_R8A7796   (SOC_ID_R8A7796)
> > +#define RMOBILE_CPU_TYPE_R8A77965  (SOC_ID_R8A77965)
> > +#define RMOBILE_CPU_TYPE_R8A77970  (SOC_ID_R8A77970)
> > +#define RMOBILE_CPU_TYPE_R8A77980  (SOC_ID_R8A77980)
> > +#define RMOBILE_CPU_TYPE_R8A77990  (SOC_ID_R8A77990)
> > +#define RMOBILE_CPU_TYPE_R8A77995  (SOC_ID_R8A77995)
> 
> The () parentheses are not needed. Also, is there any need for this renaming
> of SOC_ID_R8... to RMOBILE_CPU... ?

OK, will take out parenthesis. RMOBILE_CPU_TYPE is unique, where SOC_ID_ is 
not unique.

> > +/* RZ/G CPU Identification Mask */
> > +#define RZG_CPU_MASK 0x1000
> 
> This mask should have a comment which explicitly states that it is not related
> to the PRR register content.

Ok. Agreed.

Thanks and regards,
Biju

RE: [PATCH 3/8] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1

[Biju Das]

Hi Marek,

> Subject: Re: [PATCH 3/8] pinctrl: renesas: r8a7796: Optimize pinctrl image 
> size
> for R8A774A1
> 
> On 10/28/20 11:34 AM, Biju Das wrote:
> > This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
> > Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
> > (R8A7796[01]) is not enabled.
> >
> > Based on the similar patch on Linux.
> 
> Is this patch now part of mainline Linux or is there a patchwork link?

This patch [1] is accepted by Renesas kernel maintainer and is hit on Renesas 
drivers linux kernel tree.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/commit/?h=renesas-pinctrl=ea750cfbb81cc45dee6fcb70b2f36db858f2d3ee

Regards,
Biju

> Applied, thanks