Re: [U-Boot] [PATCH] tools: imx8m_image: Fix 'unexpected operator' error
On 03/04/2019 15:56, Anatolij Gustschin wrote: Hi Carlo, On Wed, 3 Apr 2019 15:37:20 +0100 Carlo Caione ccai...@baylibre.com wrote: When sh is an alias for dash the script is failing with (for several files): ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator Thanks, but there is already a similar patch [1] waiting for merging. It already passed the build tests and I assume that Stefano will submit a pull request soon for inclusion in v2019.04. [1] http://patchwork.ozlabs.org/patch/1019908 Oh well, good to know. Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] tools: imx8m_image: Fix 'unexpected operator' error
When sh is an alias for dash the script is failing with (for several
files):
./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator
This is caused by the 'a == b' bashism that should be 'a = b'.
Signed-off-by: Carlo Caione
---
tools/imx8m_image.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh
index 6346fb64d8..ec0881a128 100755
--- a/tools/imx8m_image.sh
+++ b/tools/imx8m_image.sh
@@ -12,7 +12,7 @@ blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2}
/^SECOND_LOADER/ {pri
for f in $blobs; do
tmp=$srctree/$f
- if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then
+ if [ $f = "spl/u-boot-spl-ddr.bin" ] || [ $f = "u-boot.itb" ]; then
continue
fi
@@ -28,7 +28,7 @@ for f in $blobs; do
sed -in "s;$f;$tmp;" $file
done
-if [ $post_process == 1 ]; then
+if [ $post_process = 1 ]; then
if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then
objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0
$srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin
objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0
$srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin
--
2.20.1
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Re: [U-Boot] [PATCH v5 3/3] cmd: mdio: Switch to generic helpers when accessing the registers
On 15/02/2019 22:46, Vladimir Oltean wrote: On 2/12/19 2:20 PM, Vladimir Oltean wrote: /cut Carlo, Joe, One additional piece of information that for some reason escaped me initially is that Pankaj Bansal already added support for struct phy_device property is_c45 as part of this patch: http://patchwork.ozlabs.org/patch/998770/ Maybe this patchset should go in the direction of using that. Oh, that's nice. Joe, can you review this patchset before I send a new one? Thanks, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 2/3] net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/ti.c | 130 +--
1 file changed, 25 insertions(+), 105 deletions(-)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 6db6edd0d0..6ac890a7f5 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -73,16 +73,6 @@
#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
#define MII_DP83867_CFG2_MASK 0x003F
-#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
-#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
-
-/* MMD Access Control register fields */
-#define MII_MMD_CTRL_DEVAD_MASK0x1f /* Mask MMD DEVAD*/
-#define MII_MMD_CTRL_ADDR 0x /* Address */
-#define MII_MMD_CTRL_NOINCR0x4000 /* no post increment */
-#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
-#define MII_MMD_CTRL_INCR_ON_WT0xC000 /* post increment on writes only
*/
-
/* User setting - can be taken from DTS */
#define DEFAULT_RX_ID_DELAYDP83867_RGMIIDCTL_2_25_NS
#define DEFAULT_TX_ID_DELAYDP83867_RGMIIDCTL_2_75_NS
@@ -116,88 +106,20 @@ struct dp83867_private {
int clk_output_sel;
};
-/**
- * phy_read_mmd_indirect - reads data from the MMD registers
- * @phydev: The PHY device bus
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- *
- * Description: it reads data from the MMD registers (clause 22 to access to
- * clause 45) of the specified phy address.
- * To read these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Read reg 14 // Read MMD data
- */
-int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr)
-{
- int value = -1;
-
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Read the content of the MMD's selected register */
- value = phy_read(phydev, addr, MII_MMD_DATA);
- return value;
-}
-
-/**
- * phy_write_mmd_indirect - writes data to the MMD registers
- * @phydev: The PHY device
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- * @data: data to write in the MMD register
- *
- * Description: Write data from the MMD registers of the specified
- * phy address.
- * To write these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Write reg 14 // Write MMD data
- */
-void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr, u32 data)
-{
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Write the data into MMD's selected register */
- phy_write(phydev, addr, MII_MMD_DATA, data);
-}
-
static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
struct dp83867_private *dp83867 =
(struct dp83867_private *)phydev->priv;
u16 val;
- val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
val |= DP83867_CFG4_PORT_MIRROR_EN;
else
val &= ~DP83867_CFG4_PORT_MIRROR_EN;
- phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
return 0;
}
@@ -257,13 +179,13 @@ static int dp83867_of_init(struct phy_device *phydev)
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
- val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
[U-Boot] [PATCH v5 3/3] cmd: mdio: Switch to generic helpers when accessing the registers
Switch to use the generic helpers to access the MMD registers so that we
can used the same command also for C45 PHYs, C22 PHYs with direct and
indirect access and PHYs implementing a custom way to access the
registers.
Signed-off-by: Carlo Caione
---
cmd/mdio.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/cmd/mdio.c b/cmd/mdio.c
index 184868063a..efe8c9ef09 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -39,21 +39,24 @@ static int extract_range(char *input, int *plo, int *phi)
return 0;
}
-static int mdio_write_ranges(struct phy_device *phydev, struct mii_dev *bus,
+static int mdio_write_ranges(struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, unsigned short data,
int extended)
{
+ struct phy_device *phydev;
int addr, devad, reg;
int err = 0;
for (addr = addrlo; addr <= addrhi; addr++) {
+ phydev = bus->phymap[addr];
+
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
if (!extended)
- err = bus->write(bus, addr, devad,
-reg, data);
+ err = phy_write_mmd(phydev, devad,
+ reg, data);
else
err = phydev->drv->writeext(phydev,
addr, devad, reg, data);
@@ -68,15 +71,17 @@ err_out:
return err;
}
-static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
+static int mdio_read_ranges(struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, int extended)
{
int addr, devad, reg;
+ struct phy_device *phydev;
printf("Reading from bus %s\n", bus->name);
for (addr = addrlo; addr <= addrhi; addr++) {
+ phydev = bus->phymap[addr];
printf("PHY at address %x:\n", addr);
for (devad = devadlo; devad <= devadhi; devad++) {
@@ -84,7 +89,7 @@ static int mdio_read_ranges(struct phy_device *phydev, struct
mii_dev *bus,
int val;
if (!extended)
- val = bus->read(bus, addr, devad, reg);
+ val = phy_read_mmd(phydev, devad, reg);
else
val = phydev->drv->readext(phydev, addr,
devad, reg);
@@ -222,14 +227,14 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
bus = phydev->bus;
extended = 1;
} else {
- return -1;
+ return CMD_RET_FAILURE;
}
if (!phydev->drv ||
(!phydev->drv->writeext && (op[0] == 'w')) ||
(!phydev->drv->readext && (op[0] == 'r'))) {
puts("PHY does not have extended functions\n");
- return -1;
+ return CMD_RET_FAILURE;
}
}
}
@@ -242,13 +247,13 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (pos > 1)
if (extract_reg_range(argv[pos--], &devadlo, &devadhi,
®lo, ®hi))
- return -1;
+ return CMD_RET_FAILURE;
default:
if (pos > 1)
if (extract_phy_range(&argv[2], pos - 1, &bus,
&phydev, &addrlo, &addrhi))
- return -1;
+ return CMD_RET_FAILURE;
break;
}
@@ -264,12 +269,12 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
switch (op[0]) {
case 'w':
- mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+ mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi,
reglo, reghi, data, extended);
[U-Boot] [PATCH v5 1/3] net: phy: Add generic helpers to access MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione
---
drivers/net/phy/phy.c | 4 +++
include/phy.h | 70 +++
2 files changed, 74 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cda4caa803..6769047407 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -549,6 +549,10 @@ int phy_register(struct phy_driver *drv)
drv->readext += gd->reloc_off;
if (drv->writeext)
drv->writeext += gd->reloc_off;
+ if (drv->read_mmd)
+ drv->read_mmd += gd->reloc_off;
+ if (drv->write_mmd)
+ drv->write_mmd += gd->reloc_off;
#endif
return 0;
}
diff --git a/include/phy.h b/include/phy.h
index b86fdfb2ce..7ec2b4e86c 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -101,6 +101,14 @@ struct phy_driver {
int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
u16 val);
+
+ /* Phy specific driver override for reading a MMD register */
+ int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+ /* Phy specific driver override for writing a MMD register */
+ int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
+u16 val);
+
struct list_head list;
};
@@ -164,6 +172,68 @@ static inline int phy_write(struct phy_device *phydev, int
devad, int regnum,
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
+ (devad | MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ struct phy_driver *drv = phydev->drv;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ /* driver-specific access */
+ if (drv->read_mmd)
+ return drv->read_mmd(phydev, devad, regnum);
+
+ /* direct C45 / C22 access */
+ if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
+ devad == MDIO_DEVAD_NONE || !devad)
+ return phy_read(phydev, devad, regnum);
+
+ /* indirect C22 access */
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Read the content of the MMD's selected register */
+ return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+ int regnum, u16 val)
+{
+ struct phy_driver *drv = phydev->drv;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ /* driver-specific access */
+ if (drv->write_mmd)
+ return drv->write_mmd(phydev, devad, regnum, val);
+
+ /* direct C45 / C22 access */
+ if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
+ devad == MDIO_DEVAD_NONE || !devad)
+ return phy_write(phydev, devad, regnum, val);
+
+ /* indirect C22 access */
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Write the data into MMD's selected register */
+ return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
--
2.19.1
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[U-Boot] [PATCH v5 0/3] Add MMD PHY helpers
Introduce phy_{read|write}_mmd() helpers and modify the mdio command to
make good use of them. Fix the ti driver in the same patchset.
Carlo Caione (3):
net: phy: Add generic helpers to access MMD PHY registers
net: phy: ti: use generic helpers to access MMD registers
cmd: mdio: Switch to generic helpers when accessing the registers
cmd/mdio.c| 27 +
drivers/net/phy/phy.c | 4 ++
drivers/net/phy/ti.c | 130 --
include/phy.h | 70 +++
4 files changed, 115 insertions(+), 116 deletions(-)
--
2.19.1
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Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 06/02/2019 03:31, Joe Hershberger wrote:
/cut
Perhaps the default can be to attempt to auto select, but if it is
ambiguous, require the explicit specification. It could follow a
similar approach to the "md" command. We can add the ability to add
".22" and ".45" to the mdio command to explicitly select.
What about we go back to have a generic phy_{r|w}_mmd() and (in this order):
1) If the PHY driver is defining a generic {r|w}_mmd() hook we use that.
2) We do direct C45 access if (phy_driver->features & PHY_10G_FEATURES)
3) We do direct C22 access if (devad == MDIO_DEVAD_NONE)
4) We do indirect C22 access to C45 in all the other cases
Se we can have one single "mdio" command for all the cases.
--
Carlo Caione
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Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 05/02/2019 00:15, Joe Hershberger wrote: On Mon, Feb 4, 2019 at 5:39 PM Vladimir Oltean wrote: /cut Which brings me to my next point. If we can't properly make the distinction between an indirect C22 MMD access and a proper C45 MMD access, and hence not keeping proper API compatibility with Linux kernel, aren't we better off going back to square 1 and using phy_read_mmd_indirect and phy_write_mmd_indirect? I think we can and should make the new wrapper functions remain named phy_*_mmd_indirect and the names of the override functions in the phy driver ops should be *_mmd_indirect. The override is still for an indirect access of c45 registers, just an apparently non-standard one. It is this way in Linux as well. Alright then. I'll prepare a V5. A couple on notes: 1. I'd prefer the parameters of the "mdio" command to be name "rimmd" and "wimmd" for "r/w indirect MMD" to keep the (twisted) logic of the mdio command code of differentiating the parameters according to argv[1][1] and r/w according to argv[1][0] 2. Since [0] needs a respin as well after the requested changes, I'm going to embedded that patch into this patchset. Cheers [0] https://lists.denx.de/pipermail/u-boot/2019-January/356019.html -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 24/01/2019 20:48, Vladimir Oltean wrote: On 1/24/19 10:19 PM, Carlo Caione wrote: On 24/01/2019 20:12, Vladimir Oltean wrote: I can't completely answer that, TBH I don't even know who is supposed to make that distinction. In the kernel that distinction is made by the driver itself, hence my question. See [0]. For Freescale parts that is a call for the MDIO bus driver to make, for good or bad (see drivers/net/fm/memac_phy.c where dev_addr is compared to MDIO_DEVAD_NONE). And in your patch, phy_write_mmd is only a wrapper over bus->write in the end, with some more logic to handle C22 indirection. So my question of unifying "mdio rmmd" with "mdio read" translates into: Does it make sense to also handle the check with MDIO_DEVAD_NONE in phy_write_mmd, instead of jumping straight ahead to perform indirection? Honestly I'm not quite sure of all the possible implications here IMO the safest bet here is just to follow what's done by the kernel. Maybe Joe can step in about this. In general we have 3 possible cases: 1) your driver is doing something non-standard when accessing the MMDs and we deal with that using the PHY driver hooks 2) your PHY is C22 and you have to use the indirect method 3) your PHY is C45 and you can use the direct register reading (mangling a bit the address apparently) The kernel is dealing with all the cases, U-Boot is only dealing with C22 PHYs (cases 1 and 2) because AFAICT there isn't yet a generic way to detect if the PHY is C22 or C45. I'm not sure if the indirect method works also for C45 PHYs. The goal would then be to just call phy_write_mmd from cmd/mdio.c regardless of the target PHY's clause. Again I wrote that patch only assuming that we were going to deal with C22 PHYs. At this point I wonder if the C22 indirect method works also for C45 PHYs. If that's the case than the phy_write_mmd should already work regardless of the target PHY clause. Cheers. [0] https://elixir.bootlin.com/linux/latest/source/drivers/net/phy/phy-core.c#L296 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 24/01/2019 20:12, Vladimir Oltean wrote: I still think I haven't successfully made my point. If "mdio read 3.1" is a C45-only thing, "mdio read 1" is a C22-only thing, then why do you need a new command "mdio rmmd 3.1" to do C45 emulation over C22? Is there any overlap I'm missing that mandates a new syntax to differentiate? Can the command not simply see whether the PHY is C22, and if it is and the MMD address is non-zero, just emulate it via 0xd and 0xe writes? Ok, I got your point now. I didn't give much thought on this TBH, good question. Do we currently have a way in U-Boot to differentiate between C22 and C45 PHYs? The generic_10g PHY should be C45 but is that the only one currently supported? -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 24/01/2019 20:04, Vladimir Oltean wrote: On 1/24/19 10:01 PM, Carlo Caione wrote: On 24/01/2019 19:56, Vladimir Oltean wrote: On 1/24/19 10:56 AM, Carlo Caione wrote: No, I mean instead of doing "mdio rmmd 3.1" to do "mdio read 3.1" (basically not define a new command). Ooooh, I think you can do that only on C45 PHYs, not on C22. (tested on my board and it didn't work FWIW). Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 24/01/2019 19:56, Vladimir Oltean wrote: On 1/24/19 10:56 AM, Carlo Caione wrote: It works for me, but I do have a question. Is there any limitation preventing you to add this functionality via the standard "mdio read x.y" instead of "mdio rmmd x.y" if the PHY is known to be C22? You can used the standard "mdio read" but it's more verbose and hard to recall: mdio write 0 0.d 0x3 mdio write 0 0.e 0x1 mdio write 0 0.d 0x4003 mdio read 0 0.e vs mdio rmmd 3.1 -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
Two new parameters (rmmd and wmmd) are added to allow the `mdio` command
to access the content of the MMD PHY registers.
Signed-off-by: Carlo Caione
Acked-by: Joe Hershberger
---
cmd/mdio.c | 52 +---
1 file changed, 37 insertions(+), 15 deletions(-)
diff --git a/cmd/mdio.c b/cmd/mdio.c
index 184868063a..5138db505a 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -43,7 +43,7 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, unsigned short data,
-int extended)
+int extended, int mmd)
{
int addr, devad, reg;
int err = 0;
@@ -51,12 +51,15 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
for (addr = addrlo; addr <= addrhi; addr++) {
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
- if (!extended)
- err = bus->write(bus, addr, devad,
-reg, data);
- else
+ if (mmd)
+ err = phy_write_mmd(phydev, devad, reg,
+ data);
+ else if (extended)
err = phydev->drv->writeext(phydev,
addr, devad, reg, data);
+ else
+ err = bus->write(bus, addr, devad,
+reg, data);
if (err)
goto err_out;
@@ -71,7 +74,7 @@ err_out:
static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
- int reglo, int reghi, int extended)
+ int reglo, int reghi, int extended, int mmd)
{
int addr, devad, reg;
@@ -83,11 +86,13 @@ static int mdio_read_ranges(struct phy_device *phydev,
struct mii_dev *bus,
for (reg = reglo; reg <= reghi; reg++) {
int val;
- if (!extended)
- val = bus->read(bus, addr, devad, reg);
- else
+ if (mmd)
+ val = phy_read_mmd(phydev, devad, reg);
+ else if (extended)
val = phydev->drv->readext(phydev, addr,
devad, reg);
+ else
+ val = bus->read(bus, addr, devad, reg);
if (val < 0) {
printf("Error\n");
@@ -189,6 +194,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
struct mii_dev *bus;
struct phy_device *phydev = NULL;
int extended = 0;
+ int mmd = 0;
if (argc < 2)
return CMD_RET_USAGE;
@@ -222,14 +228,26 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
bus = phydev->bus;
extended = 1;
} else {
- return -1;
+ return CMD_RET_FAILURE;
}
if (!phydev->drv ||
(!phydev->drv->writeext && (op[0] == 'w')) ||
(!phydev->drv->readext && (op[0] == 'r'))) {
puts("PHY does not have extended functions\n");
- return -1;
+ return CMD_RET_FAILURE;
+ }
+ }
+ if (op[1] == 'm') {
+ phydev = mdio_phydev_for_ethname(argv[2]);
+
+ if (phydev) {
+ addrlo = phydev->addr;
+ addrhi = addrlo;
+ bus = phydev->bus;
+ mmd = 1;
+ } else {
+ return CMD_RET_FAILURE;
}
}
[U-Boot] [PATCH v4 1/3] net: phy: Add support for accessing MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by two means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione
Acked-by: Joe Hershberger
---
drivers/net/phy/phy.c | 4
include/phy.h | 52 +++
2 files changed, 56 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cda4caa803..6769047407 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -549,6 +549,10 @@ int phy_register(struct phy_driver *drv)
drv->readext += gd->reloc_off;
if (drv->writeext)
drv->writeext += gd->reloc_off;
+ if (drv->read_mmd)
+ drv->read_mmd += gd->reloc_off;
+ if (drv->write_mmd)
+ drv->write_mmd += gd->reloc_off;
#endif
return 0;
}
diff --git a/include/phy.h b/include/phy.h
index b86fdfb2ce..440013d000 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -101,6 +101,14 @@ struct phy_driver {
int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
u16 val);
+
+ /* Phy specific driver override for reading a MMD register */
+ int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+ /* Phy specific driver override for writing a MMD register */
+ int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
+u16 val);
+
struct list_head list;
};
@@ -164,6 +172,50 @@ static inline int phy_write(struct phy_device *phydev, int
devad, int regnum,
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
+ (devad | MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->read_mmd)
+ return phydev->drv->read_mmd(phydev, devad, regnum);
+
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Read the content of the MMD's selected register */
+ return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+ int regnum, u16 val)
+{
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->write_mmd)
+ return phydev->drv->write_mmd(phydev, devad, regnum, val);
+
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Write the data into MMD's selected register */
+ return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
--
2.19.1
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[U-Boot] [PATCH v4 2/3] net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/ti.c | 130 +--
1 file changed, 25 insertions(+), 105 deletions(-)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 6db6edd0d0..6ac890a7f5 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -73,16 +73,6 @@
#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
#define MII_DP83867_CFG2_MASK 0x003F
-#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
-#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
-
-/* MMD Access Control register fields */
-#define MII_MMD_CTRL_DEVAD_MASK0x1f /* Mask MMD DEVAD*/
-#define MII_MMD_CTRL_ADDR 0x /* Address */
-#define MII_MMD_CTRL_NOINCR0x4000 /* no post increment */
-#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
-#define MII_MMD_CTRL_INCR_ON_WT0xC000 /* post increment on writes only
*/
-
/* User setting - can be taken from DTS */
#define DEFAULT_RX_ID_DELAYDP83867_RGMIIDCTL_2_25_NS
#define DEFAULT_TX_ID_DELAYDP83867_RGMIIDCTL_2_75_NS
@@ -116,88 +106,20 @@ struct dp83867_private {
int clk_output_sel;
};
-/**
- * phy_read_mmd_indirect - reads data from the MMD registers
- * @phydev: The PHY device bus
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- *
- * Description: it reads data from the MMD registers (clause 22 to access to
- * clause 45) of the specified phy address.
- * To read these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Read reg 14 // Read MMD data
- */
-int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr)
-{
- int value = -1;
-
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Read the content of the MMD's selected register */
- value = phy_read(phydev, addr, MII_MMD_DATA);
- return value;
-}
-
-/**
- * phy_write_mmd_indirect - writes data to the MMD registers
- * @phydev: The PHY device
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- * @data: data to write in the MMD register
- *
- * Description: Write data from the MMD registers of the specified
- * phy address.
- * To write these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Write reg 14 // Write MMD data
- */
-void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr, u32 data)
-{
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Write the data into MMD's selected register */
- phy_write(phydev, addr, MII_MMD_DATA, data);
-}
-
static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
struct dp83867_private *dp83867 =
(struct dp83867_private *)phydev->priv;
u16 val;
- val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
val |= DP83867_CFG4_PORT_MIRROR_EN;
else
val &= ~DP83867_CFG4_PORT_MIRROR_EN;
- phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
return 0;
}
@@ -257,13 +179,13 @@ static int dp83867_of_init(struct phy_device *phydev)
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
- val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
[U-Boot] [PATCH v4 0/3] Add MMD PHY helpers
Introduce phy_(read|write)_mmd() generic 802.3 clause 45 register accessors for Clause 22 PHYs, using the indirect method. Allow this behaviour to be overriden by PHY drivers where necessary. Carlo Caione (3): net: phy: Add support for accessing MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Add new parameter to access MMD PHY registers cmd/mdio.c| 52 - drivers/net/phy/phy.c | 4 ++ drivers/net/phy/ti.c | 130 -- include/phy.h | 52 + 4 files changed, 118 insertions(+), 120 deletions(-) -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] net: phy: realtek: Introduce quirk to mark RXC not stoppable
When EEE is supported by the PHY and the driver allows it, libphy in the
kernel is configuring the PHY to stop receiving the xMII clock while it
is signaling LPI. While this (usually) works fine in the kernel this is
causing issues in U-Boot when rebooting from the linux kernel with this
bit set (without having the possibility to reset the PHY) where the PHY
suddenly stops working.
A new quirk is introduced to unconditionally reset this bit. If the
quirk is not enabled using the proper configuration symbol, the PHY state
is not changed.
Signed-off-by: Carlo Caione
Acked-by: Joe Hershberger
---
drivers/net/phy/Kconfig | 20
drivers/net/phy/realtek.c | 19 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 3dc0822d9c..631b52b1cf 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -202,6 +202,26 @@ config RTL8211X_PHY_FORCE_MASTER
If unsure, say N.
+config RTL8211F_PHY_FORCE_EEE_RXC_ON
+ bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock
during LPI"
+ depends on PHY_REALTEK
+ default n
+ help
+ The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
+ transitions to/from a lower power consumption level (Low Power Idle
+ mode) based on link utilization. When no packets are being
+ transmitted, the system goes to Low Power Idle mode to save power.
+
+ Under particular circumstances this setting can cause issues where
+ the PHY is unable to transmit or receive any packet when in LPI mode.
+ The problem is caused when the PHY is configured to stop receiving
+ the xMII clock while it is signaling LPI. For some PHYs the bit
+ configuring this behavior is set by the Linux kernel, causing the
+ issue in U-Boot on reboot if the PHY retains the register value.
+
+ Default n, which means that the PHY state is not changed. To work
+ around the issues, change this setting to y.
+
config PHY_SMSC
bool "Microchip(SMSC) Ethernet PHYs support"
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index b3e6578df9..fa11696fe2 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -12,6 +12,7 @@
#define PHY_RTL8211x_FORCE_MASTER BIT(1)
#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
+#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
@@ -75,6 +76,15 @@ static int rtl8211e_probe(struct phy_device *phydev)
return 0;
}
+static int rtl8211f_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
+ phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
+#endif
+
+ return 0;
+}
+
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
{
@@ -124,6 +134,14 @@ static int rtl8211f_config(struct phy_device *phydev)
{
u16 reg;
+ if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
+ unsigned int reg;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
+ reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
+ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
+ }
+
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
phy_write(phydev, MDIO_DEVAD_NONE,
@@ -333,6 +351,7 @@ static struct phy_driver RTL8211F_driver = {
.uid = 0x1cc916,
.mask = 0xff,
.features = PHY_GBIT_FEATURES,
+ .probe = &rtl8211f_probe,
.config = &rtl8211f_config,
.startup = &rtl8211f_startup,
.shutdown = &genphy_shutdown,
--
2.19.1
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Re: [U-Boot] [PATCH v3 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On 23/01/19 16:31, Joe Hershberger wrote: On Wed, Jan 23, 2019 at 10:23 AM Joe Hershberger wrote: On Wed, Jan 23, 2019 at 10:07 AM Carlo Caione wrote: > > Two new parameters (rmmd and wmmd) are added to allow the `mdio` command > to access the content of the MMD PHY registers. > > Signed-off-by: Carlo Caione Acked-by: Joe Hershberger checkpatch.pl failures... please address. Uhm, ok for the line over 80 characters but the quoted string split across lines warning is really there for consistency with the old code. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: phy: realtek: Introduce quirk to mark RXC not stoppable
On 23/01/19 16:19, Joe Hershberger wrote: /cut + transitions to/from a lower power consumption level (Low Power Idle + mode) based on link utilization. When no packets are being + transmitted, the system goes to Low Power Idle mode to save power. + + Under particular circumstances this setting can cause issues where + the PHY is unable to transmit or receive any packet when in LPI mode. + The problem is caused when the PHY is configured to stop receiving + the xMII clock while it is signaling LPI. When not stated otherwise + this bit is set by libphy in the linux kernel. This seems to be copied from Linux, please update to describe what happens in U-Boot. It is not copied from Linux. The problem is that the libphy in the kernel is flipping this bit and this is causing the issue in U-Boot on reboot. So I'm saying exactly that. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/3] net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/ti.c | 130 +--
1 file changed, 25 insertions(+), 105 deletions(-)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 6db6edd0d0..6ac890a7f5 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -73,16 +73,6 @@
#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
#define MII_DP83867_CFG2_MASK 0x003F
-#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
-#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
-
-/* MMD Access Control register fields */
-#define MII_MMD_CTRL_DEVAD_MASK0x1f /* Mask MMD DEVAD*/
-#define MII_MMD_CTRL_ADDR 0x /* Address */
-#define MII_MMD_CTRL_NOINCR0x4000 /* no post increment */
-#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
-#define MII_MMD_CTRL_INCR_ON_WT0xC000 /* post increment on writes only
*/
-
/* User setting - can be taken from DTS */
#define DEFAULT_RX_ID_DELAYDP83867_RGMIIDCTL_2_25_NS
#define DEFAULT_TX_ID_DELAYDP83867_RGMIIDCTL_2_75_NS
@@ -116,88 +106,20 @@ struct dp83867_private {
int clk_output_sel;
};
-/**
- * phy_read_mmd_indirect - reads data from the MMD registers
- * @phydev: The PHY device bus
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- *
- * Description: it reads data from the MMD registers (clause 22 to access to
- * clause 45) of the specified phy address.
- * To read these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Read reg 14 // Read MMD data
- */
-int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr)
-{
- int value = -1;
-
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Read the content of the MMD's selected register */
- value = phy_read(phydev, addr, MII_MMD_DATA);
- return value;
-}
-
-/**
- * phy_write_mmd_indirect - writes data to the MMD registers
- * @phydev: The PHY device
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- * @data: data to write in the MMD register
- *
- * Description: Write data from the MMD registers of the specified
- * phy address.
- * To write these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Write reg 14 // Write MMD data
- */
-void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr, u32 data)
-{
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Write the data into MMD's selected register */
- phy_write(phydev, addr, MII_MMD_DATA, data);
-}
-
static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
struct dp83867_private *dp83867 =
(struct dp83867_private *)phydev->priv;
u16 val;
- val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
val |= DP83867_CFG4_PORT_MIRROR_EN;
else
val &= ~DP83867_CFG4_PORT_MIRROR_EN;
- phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
return 0;
}
@@ -257,13 +179,13 @@ static int dp83867_of_init(struct phy_device *phydev)
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
- val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
[U-Boot] [PATCH v3 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
Two new parameters (rmmd and wmmd) are added to allow the `mdio` command
to access the content of the MMD PHY registers.
Signed-off-by: Carlo Caione
---
cmd/mdio.c | 51 ---
1 file changed, 36 insertions(+), 15 deletions(-)
diff --git a/cmd/mdio.c b/cmd/mdio.c
index 184868063a..f4ae4541e7 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -43,7 +43,7 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, unsigned short data,
-int extended)
+int extended, int mmd)
{
int addr, devad, reg;
int err = 0;
@@ -51,12 +51,14 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
for (addr = addrlo; addr <= addrhi; addr++) {
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
- if (!extended)
- err = bus->write(bus, addr, devad,
-reg, data);
- else
+ if (mmd)
+ err = phy_write_mmd(phydev, devad, reg,
data);
+ else if (extended)
err = phydev->drv->writeext(phydev,
addr, devad, reg, data);
+ else
+ err = bus->write(bus, addr, devad,
+reg, data);
if (err)
goto err_out;
@@ -71,7 +73,7 @@ err_out:
static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
- int reglo, int reghi, int extended)
+ int reglo, int reghi, int extended, int mmd)
{
int addr, devad, reg;
@@ -83,11 +85,13 @@ static int mdio_read_ranges(struct phy_device *phydev,
struct mii_dev *bus,
for (reg = reglo; reg <= reghi; reg++) {
int val;
- if (!extended)
- val = bus->read(bus, addr, devad, reg);
- else
+ if (mmd)
+ val = phy_read_mmd(phydev, devad, reg);
+ else if (extended)
val = phydev->drv->readext(phydev, addr,
devad, reg);
+ else
+ val = bus->read(bus, addr, devad, reg);
if (val < 0) {
printf("Error\n");
@@ -189,6 +193,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
struct mii_dev *bus;
struct phy_device *phydev = NULL;
int extended = 0;
+ int mmd = 0;
if (argc < 2)
return CMD_RET_USAGE;
@@ -222,14 +227,26 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
bus = phydev->bus;
extended = 1;
} else {
- return -1;
+ return CMD_RET_FAILURE;
}
if (!phydev->drv ||
(!phydev->drv->writeext && (op[0] == 'w')) ||
(!phydev->drv->readext && (op[0] == 'r'))) {
puts("PHY does not have extended functions\n");
- return -1;
+ return CMD_RET_FAILURE;
+ }
+ }
+ if (op[1] == 'm') {
+ phydev = mdio_phydev_for_ethname(argv[2]);
+
+ if (phydev) {
+ addrlo = phydev->addr;
+ addrhi = addrlo;
+ bus = phydev->bus;
+ mmd = 1;
+ } else {
+ return CMD_RET_FAILURE;
}
}
}
@@ -242,13 +259,13 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int ar
[U-Boot] [PATCH v3 1/3] net: phy: Add support for accessing MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by two means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione
---
drivers/net/phy/phy.c | 4
include/phy.h | 52 +++
2 files changed, 56 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cda4caa803..6769047407 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -549,6 +549,10 @@ int phy_register(struct phy_driver *drv)
drv->readext += gd->reloc_off;
if (drv->writeext)
drv->writeext += gd->reloc_off;
+ if (drv->read_mmd)
+ drv->read_mmd += gd->reloc_off;
+ if (drv->write_mmd)
+ drv->write_mmd += gd->reloc_off;
#endif
return 0;
}
diff --git a/include/phy.h b/include/phy.h
index b86fdfb2ce..f6f6f097af 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -101,6 +101,13 @@ struct phy_driver {
int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
u16 val);
+
+ /* Phy specific driver override for reading a MMD register */
+ int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+ /* Phy specific driver override for writing a MMD register */
+ int (*write_mmd)(struct phy_device *phydev, int devad, int reg, u16
val);
+
struct list_head list;
};
@@ -164,6 +171,51 @@ static inline int phy_write(struct phy_device *phydev, int
devad, int regnum,
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, (devad |
MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->read_mmd) {
+ return phydev->drv->read_mmd(phydev, devad, regnum);
+ } else {
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Read the content of the MMD's selected register */
+ return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+ }
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+ int regnum, u16 val)
+{
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->write_mmd) {
+ return phydev->drv->write_mmd(phydev, devad, regnum, val);
+ } else {
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Write the data into MMD's selected register */
+ return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+ }
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
--
2.19.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/3] Add MMD PHY helpers
Introduce phy_(read|write)_mmd() generic 802.3 clause 45 register accessors for Clause 22 PHYs, using the indirect method. Allow this behaviour to be overriden by PHY drivers where necessary. Carlo Caione (3): net: phy: Add support for accessing MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Add new parameter to access MMD PHY registers cmd/mdio.c| 51 - drivers/net/phy/phy.c | 4 ++ drivers/net/phy/ti.c | 130 -- include/phy.h | 52 + 4 files changed, 117 insertions(+), 120 deletions(-) -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] net: phy: realtek: Introduce quirk to mark RXC not stoppable
When EEE is supported by the PHY and the driver allows it, libphy in the
kernel is configuring the PHY to stop receiving the xMII clock while it
is signaling LPI. While this (usually) works fine in the kernel this is
causing issues in U-Boot when rebooting from the linux kernel with this
bit set (without having the possibility to reset the PHY) where the PHY
suddenly stops working.
A new quirk is introduced to unconditionally reset this bit. If the
quirk is not enabled using the proper configuration symbol, the PHY state
is not changed.
Signed-off-by: Carlo Caione
---
Hi Joe,
just an heads up that this patch depends on the MMD helpers patch I
submitted earlier.
---
drivers/net/phy/Kconfig | 19 +++
drivers/net/phy/realtek.c | 19 +++
2 files changed, 38 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 3dc0822d9c..d0dab3014e 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -202,6 +202,25 @@ config RTL8211X_PHY_FORCE_MASTER
If unsure, say N.
+config RTL8211F_PHY_FORCE_EEE_RXC_ON
+ bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock
during LPI"
+ depends on PHY_REALTEK
+ default n
+ help
+ The IEEE 802.3az-2010 (EEE) standar provides a protocol to coordinate
+ transitions to/from a lower power consumption level (Low Power Idle
+ mode) based on link utilization. When no packets are being
+ transmitted, the system goes to Low Power Idle mode to save power.
+
+ Under particular circumstances this setting can cause issues where
+ the PHY is unable to transmit or receive any packet when in LPI mode.
+ The problem is caused when the PHY is configured to stop receiving
+ the xMII clock while it is signaling LPI. When not stated otherwise
+ this bit is set by libphy in the linux kernel.
+
+ Default n, which means that the PHY state is not changed. To work
+ around the issues, change this setting to y.
+
config PHY_SMSC
bool "Microchip(SMSC) Ethernet PHYs support"
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index b3e6578df9..fa11696fe2 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -12,6 +12,7 @@
#define PHY_RTL8211x_FORCE_MASTER BIT(1)
#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
+#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
@@ -75,6 +76,15 @@ static int rtl8211e_probe(struct phy_device *phydev)
return 0;
}
+static int rtl8211f_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
+ phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
+#endif
+
+ return 0;
+}
+
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
{
@@ -124,6 +134,14 @@ static int rtl8211f_config(struct phy_device *phydev)
{
u16 reg;
+ if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
+ unsigned int reg;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
+ reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
+ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
+ }
+
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
phy_write(phydev, MDIO_DEVAD_NONE,
@@ -333,6 +351,7 @@ static struct phy_driver RTL8211F_driver = {
.uid = 0x1cc916,
.mask = 0xff,
.features = PHY_GBIT_FEATURES,
+ .probe = &rtl8211f_probe,
.config = &rtl8211f_config,
.startup = &rtl8211f_startup,
.shutdown = &genphy_shutdown,
--
2.19.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
Two new parameters (rmmd and wmmd) are added to allow the `mdio` command
to access the content of the MMD PHY registers.
Signed-off-by: Carlo Caione
---
cmd/mdio.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/cmd/mdio.c b/cmd/mdio.c
index 184868063a..010632b562 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -43,7 +43,7 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, unsigned short data,
-int extended)
+int extended, int mmd)
{
int addr, devad, reg;
int err = 0;
@@ -51,7 +51,9 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
for (addr = addrlo; addr <= addrhi; addr++) {
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
- if (!extended)
+ if (mmd)
+ err = phy_write_mmd(phydev, devad, reg,
data);
+ else if (!extended)
err = bus->write(bus, addr, devad,
reg, data);
else
@@ -71,7 +73,7 @@ err_out:
static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
- int reglo, int reghi, int extended)
+ int reglo, int reghi, int extended, int mmd)
{
int addr, devad, reg;
@@ -83,7 +85,9 @@ static int mdio_read_ranges(struct phy_device *phydev, struct
mii_dev *bus,
for (reg = reglo; reg <= reghi; reg++) {
int val;
- if (!extended)
+ if (mmd)
+ val = phy_read_mmd(phydev, devad, reg);
+ else if (!extended)
val = bus->read(bus, addr, devad, reg);
else
val = phydev->drv->readext(phydev, addr,
@@ -189,6 +193,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
struct mii_dev *bus;
struct phy_device *phydev = NULL;
int extended = 0;
+ int mmd = 0;
if (argc < 2)
return CMD_RET_USAGE;
@@ -232,6 +237,18 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
return -1;
}
}
+ if (op[1] == 'm') {
+ phydev = mdio_phydev_for_ethname(argv[2]);
+
+ if (phydev) {
+ addrlo = phydev->addr;
+ addrhi = addrlo;
+ bus = phydev->bus;
+ mmd = 1;
+ } else {
+ return -1;
+ }
+ }
}
switch (op[0]) {
@@ -265,12 +282,12 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
switch (op[0]) {
case 'w':
mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
- reglo, reghi, data, extended);
+ reglo, reghi, data, extended, mmd);
break;
case 'r':
mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
-reglo, reghi, extended);
+reglo, reghi, extended, mmd);
break;
}
@@ -303,6 +320,10 @@ U_BOOT_CMD(
"read PHY's extended register at .\n"
"mdio wx [.] - "
"write PHY's extended register at .\n"
+ "mdio rmmd [.] - "
+ "read PHY's extended register at .\n"
+ "mdio wmmd [.] - "
+ "write PHY's extended register at .\n"
" may be:\n"
" \n"
" \n"
--
2.19.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione
Signed-off-by: Vladimir Oltean
---
drivers/net/phy/ti.c | 130 +--
1 file changed, 25 insertions(+), 105 deletions(-)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 6db6edd0d0..6ac890a7f5 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -73,16 +73,6 @@
#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
#define MII_DP83867_CFG2_MASK 0x003F
-#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
-#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
-
-/* MMD Access Control register fields */
-#define MII_MMD_CTRL_DEVAD_MASK0x1f /* Mask MMD DEVAD*/
-#define MII_MMD_CTRL_ADDR 0x /* Address */
-#define MII_MMD_CTRL_NOINCR0x4000 /* no post increment */
-#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
-#define MII_MMD_CTRL_INCR_ON_WT0xC000 /* post increment on writes only
*/
-
/* User setting - can be taken from DTS */
#define DEFAULT_RX_ID_DELAYDP83867_RGMIIDCTL_2_25_NS
#define DEFAULT_TX_ID_DELAYDP83867_RGMIIDCTL_2_75_NS
@@ -116,88 +106,20 @@ struct dp83867_private {
int clk_output_sel;
};
-/**
- * phy_read_mmd_indirect - reads data from the MMD registers
- * @phydev: The PHY device bus
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- *
- * Description: it reads data from the MMD registers (clause 22 to access to
- * clause 45) of the specified phy address.
- * To read these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Read reg 14 // Read MMD data
- */
-int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr)
-{
- int value = -1;
-
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Read the content of the MMD's selected register */
- value = phy_read(phydev, addr, MII_MMD_DATA);
- return value;
-}
-
-/**
- * phy_write_mmd_indirect - writes data to the MMD registers
- * @phydev: The PHY device
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- * @data: data to write in the MMD register
- *
- * Description: Write data from the MMD registers of the specified
- * phy address.
- * To write these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Write reg 14 // Write MMD data
- */
-void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr, u32 data)
-{
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Write the data into MMD's selected register */
- phy_write(phydev, addr, MII_MMD_DATA, data);
-}
-
static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
struct dp83867_private *dp83867 =
(struct dp83867_private *)phydev->priv;
u16 val;
- val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
val |= DP83867_CFG4_PORT_MIRROR_EN;
else
val &= ~DP83867_CFG4_PORT_MIRROR_EN;
- phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
return 0;
}
@@ -257,13 +179,13 @@ static int dp83867_of_init(struct phy_device *phydev)
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
- val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
val |= (dp83867->clk_output_sel <<
[U-Boot] [PATCH v2 1/3] net: phy: Add support for accessing MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by two means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione
---
drivers/net/phy/phy.c | 4 +++
include/phy.h | 62 +++
2 files changed, 66 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cda4caa803..6769047407 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -549,6 +549,10 @@ int phy_register(struct phy_driver *drv)
drv->readext += gd->reloc_off;
if (drv->writeext)
drv->writeext += gd->reloc_off;
+ if (drv->read_mmd)
+ drv->read_mmd += gd->reloc_off;
+ if (drv->write_mmd)
+ drv->write_mmd += gd->reloc_off;
#endif
return 0;
}
diff --git a/include/phy.h b/include/phy.h
index b86fdfb2ce..0ce41661fa 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -101,6 +101,13 @@ struct phy_driver {
int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
u16 val);
+
+ /* Phy specific driver override for reading a MMD register */
+ int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+ /* Phy specific driver override for writing a MMD register */
+ int (*write_mmd)(struct phy_device *phydev, int devad, int reg, u16
val);
+
struct list_head list;
};
@@ -164,6 +171,61 @@ static inline int phy_write(struct phy_device *phydev, int
devad, int regnum,
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+static inline void phy_mmd_indirect(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, (devad |
MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ int ret;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->read_mmd) {
+ ret = phydev->drv->read_mmd(phydev, devad, regnum);
+ } else {
+ phy_mmd_indirect(phydev, devad, regnum);
+
+ /* Read the content of the MMD's selected register */
+ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+ }
+
+ return ret;
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+ int regnum, u16 val)
+{
+ int ret;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->write_mmd) {
+ ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
+ } else {
+ phy_mmd_indirect(phydev, devad, regnum);
+
+ /* Write the data into MMD's selected register */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+
+ ret = 0;
+ }
+
+ return ret;
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
--
2.19.1
___
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[U-Boot] [PATCH v2 0/3] Add MMD PHY helpers
Introduce phy_(read|write)_mmd() generic 802.3 clause 45 register accessors for Clause 22 PHYs, using the indirect method. Allow this behaviour to be overriden by PHY drivers where necessary. Carlo Caione (3): net: phy: Add support for accessing MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Add new parameter to access MMD PHY registers cmd/mdio.c| 33 +-- drivers/net/phy/phy.c | 4 ++ drivers/net/phy/ti.c | 130 -- include/phy.h | 62 4 files changed, 118 insertions(+), 111 deletions(-) -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot 1/2] net: phy: Add support for accessing MMD PHY registers
On 23/01/19 00:04, Joe Hershberger wrote: If we have to override the access then probably so. Maybe it would make more sense to have a v2 from you that removes the duplicate code from the ti phy driver and then have Vlad's smartEEE patch be rebased on that. I have not yet pushed Vlad's patches so we have an opportunity to do it more cleanly potentially. Thoughts from each of you? I'll rebase that patch on top of my set and I'll let Vlad submit the smartEEE patch on top. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot 1/2] net: phy: Add support for accessing MMD PHY registers
On 22/01/19 22:21, Joe Hershberger wrote: On Wed, Jan 16, 2019 at 12:06 PM Carlo Caione wrote: Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added to allow access to the MMD PHY registers. The MMD PHY registers can be accessed by two means: 1. Using two new MMD access function hooks in the PHY driver. These functions can be implemented when the PHY driver does not support the standard IEEE Compatible clause 45 access mechanism described in clause 22 or if the PHY uses its own non-standard access mechanism. 2. The standard clause 45 access extensions to the MMD registers through the indirection registers (clause 22) in all the other cases. Signed-off-by: Carlo Caione This seems like a duplicate of https://patchwork.ozlabs.org/patch/1015782/ Well, I should have looked better. Interestingly I was going to use my patch to fix the exact same issue on a different PHY. The problem I see with that patch is that it is assuming that all the PHY devices support clause 45 access extension using the clause 22 registers. This is not always true (see for example [0]). That's why I added two new hooks in the PHY driver. On a side note looking at that patch it seems that 'addr' (documented as the PHY address in the same patch) is being passed to 'phy_write' where we should have the 'devad' parameter instead (MDIO_DEVAD_NONE)? The command patch should probably be adapted to use that. Let me know if you think it is valuable still to add the two hooks on top of that patch. Thanks, [0] https://patchwork.ozlabs.org/patch/351634/ -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot 2/2] cmd: mdio: Add new parameter to access MMD PHY registers
Two new parameters (rmmd and wmmd) are added to allow the `mdio` command
to access the content of the MMD PHY registers.
Signed-off-by: Carlo Caione
---
cmd/mdio.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/cmd/mdio.c b/cmd/mdio.c
index 184868063a..010632b562 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -43,7 +43,7 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, unsigned short data,
-int extended)
+int extended, int mmd)
{
int addr, devad, reg;
int err = 0;
@@ -51,7 +51,9 @@ static int mdio_write_ranges(struct phy_device *phydev,
struct mii_dev *bus,
for (addr = addrlo; addr <= addrhi; addr++) {
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
- if (!extended)
+ if (mmd)
+ err = phy_write_mmd(phydev, devad, reg,
data);
+ else if (!extended)
err = bus->write(bus, addr, devad,
reg, data);
else
@@ -71,7 +73,7 @@ err_out:
static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
- int reglo, int reghi, int extended)
+ int reglo, int reghi, int extended, int mmd)
{
int addr, devad, reg;
@@ -83,7 +85,9 @@ static int mdio_read_ranges(struct phy_device *phydev, struct
mii_dev *bus,
for (reg = reglo; reg <= reghi; reg++) {
int val;
- if (!extended)
+ if (mmd)
+ val = phy_read_mmd(phydev, devad, reg);
+ else if (!extended)
val = bus->read(bus, addr, devad, reg);
else
val = phydev->drv->readext(phydev, addr,
@@ -189,6 +193,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
struct mii_dev *bus;
struct phy_device *phydev = NULL;
int extended = 0;
+ int mmd = 0;
if (argc < 2)
return CMD_RET_USAGE;
@@ -232,6 +237,18 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
return -1;
}
}
+ if (op[1] == 'm') {
+ phydev = mdio_phydev_for_ethname(argv[2]);
+
+ if (phydev) {
+ addrlo = phydev->addr;
+ addrhi = addrlo;
+ bus = phydev->bus;
+ mmd = 1;
+ } else {
+ return -1;
+ }
+ }
}
switch (op[0]) {
@@ -265,12 +282,12 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
switch (op[0]) {
case 'w':
mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
- reglo, reghi, data, extended);
+ reglo, reghi, data, extended, mmd);
break;
case 'r':
mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
-reglo, reghi, extended);
+reglo, reghi, extended, mmd);
break;
}
@@ -303,6 +320,10 @@ U_BOOT_CMD(
"read PHY's extended register at .\n"
"mdio wx [.] - "
"write PHY's extended register at .\n"
+ "mdio rmmd [.] - "
+ "read PHY's extended register at .\n"
+ "mdio wmmd [.] - "
+ "write PHY's extended register at .\n"
" may be:\n"
" \n"
" \n"
--
2.19.1
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[U-Boot] [PATCH u-boot 1/2] net: phy: Add support for accessing MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by two means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione
---
drivers/net/phy/phy.c | 4 +++
include/phy.h | 62 +++
2 files changed, 66 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cda4caa803..6769047407 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -549,6 +549,10 @@ int phy_register(struct phy_driver *drv)
drv->readext += gd->reloc_off;
if (drv->writeext)
drv->writeext += gd->reloc_off;
+ if (drv->read_mmd)
+ drv->read_mmd += gd->reloc_off;
+ if (drv->write_mmd)
+ drv->write_mmd += gd->reloc_off;
#endif
return 0;
}
diff --git a/include/phy.h b/include/phy.h
index b86fdfb2ce..0ce41661fa 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -101,6 +101,13 @@ struct phy_driver {
int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
u16 val);
+
+ /* Phy specific driver override for reading a MMD register */
+ int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+ /* Phy specific driver override for writing a MMD register */
+ int (*write_mmd)(struct phy_device *phydev, int devad, int reg, u16
val);
+
struct list_head list;
};
@@ -164,6 +171,61 @@ static inline int phy_write(struct phy_device *phydev, int
devad, int regnum,
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+static inline void phy_mmd_indirect(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, (devad |
MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ int ret;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->read_mmd) {
+ ret = phydev->drv->read_mmd(phydev, devad, regnum);
+ } else {
+ phy_mmd_indirect(phydev, devad, regnum);
+
+ /* Read the content of the MMD's selected register */
+ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+ }
+
+ return ret;
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+ int regnum, u16 val)
+{
+ int ret;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ if (phydev->drv->write_mmd) {
+ ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
+ } else {
+ phy_mmd_indirect(phydev, devad, regnum);
+
+ /* Write the data into MMD's selected register */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+
+ ret = 0;
+ }
+
+ return ret;
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
--
2.19.1
___
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[U-Boot] [PATCH u-boot 0/2] Add MMD PHY helpers
Introduce phy_(read|write)_mmd() generic 802.3 clause 45 register accessors for Clause 22 PHYs, using the indirect method. Allow this behaviour to be overriden by PHY drivers where necessary. Carlo Caione (2): net: phy: Add support for accessing MMD PHY registers cmd: mdio: Add new parameter to access MMD PHY registers cmd/mdio.c| 33 ++- drivers/net/phy/phy.c | 4 +++ include/phy.h | 62 +++ 3 files changed, 93 insertions(+), 6 deletions(-) -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot] net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x or 0xa42 (switch back to IEEE
Standard Registers)
Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.
Signed-off-by: Carlo Caione
---
drivers/net/phy/realtek.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index b3e6578df9..3bea1fa9d0 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -57,6 +57,31 @@
#define MIIM_RTL8211F_TX_DELAY 0x100
#define MIIM_RTL8211F_LCR 0x10
+static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
+ int devaddr, int regnum)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211F_PAGE_SELECT);
+ int val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
+
+ return val;
+}
+
+static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
+int devaddr, int regnum, u16 val)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211F_PAGE_SELECT);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
+ phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
+
+ return 0;
+}
+
static int rtl8211b_probe(struct phy_device *phydev)
{
#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
@@ -336,6 +361,8 @@ static struct phy_driver RTL8211F_driver = {
.config = &rtl8211f_config,
.startup = &rtl8211f_startup,
.shutdown = &genphy_shutdown,
+ .readext = &rtl8211f_phy_extread,
+ .writeext = &rtl8211f_phy_extwrite,
};
int phy_realtek_init(void)
--
2.19.1
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[U-Boot] [PATCH] pinctrl: meson: axg: Fix GPIO pin offsets
The pin number (first and last) in the bank definition is missing the
pin base offset shifting. This is causing a miscalculation when
retrieving the register and pin offsets in the GPIO driver causing the
'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip
(the AO bank is driven correctly because the shifting is already 0).
Signed-off-by: Carlo Caione
---
drivers/pinctrl/meson/pinctrl-meson-axg.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index a54fbce910..3bbbe817b4 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -14,7 +14,7 @@
#include "pinctrl-meson-axg.h"
-#define EE_OFF 14
+#define EE_OFF 15
/* emmc */
static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
@@ -893,17 +893,17 @@ static struct meson_pmx_func meson_axg_aobus_functions[]
= {
};
static struct meson_bank meson_axg_periphs_banks[] = {
- /* namefirst last pullen pulldir out in */
- BANK("Z",GPIOZ_0, GPIOZ_10, 3, 0, 3, 0, 9, 0, 10, 0, 11,
0),
- BANK("BOOT", BOOT_0,BOOT_14, 4, 0, 4, 0, 12, 0, 13, 0, 14,
0),
- BANK("A",GPIOA_0, GPIOA_20, 0, 0, 0, 0, 0, 0, 1, 0, 2,
0),
- BANK("X",GPIOX_0, GPIOX_22, 2, 0, 2, 0, 6, 0, 7, 0, 8,
0),
- BANK("Y",GPIOY_0, GPIOY_15, 1, 0, 1, 0, 3, 0, 4, 0, 5,
0),
+ /* namefirst lastpullen
pulldir out in */
+ BANK("Z",PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 3, 0,
3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 4, 0,
4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("A",PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0, 0,
0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("X",PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 2, 0,
2, 0, 6, 0, 7, 0, 8, 0),
+ BANK("Y",PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), 1, 0,
1, 0, 3, 0, 4, 0, 5, 0),
};
static struct meson_bank meson_axg_aobus_banks[] = {
- /* namefirst last pullen pulldir out in
*/
- BANK("AO", GPIOAO_0, GPIOAO_13, 0, 16, 0, 0, 0, 0, 0, 16, 1,
0),
+ /* namefirst last pullen pulldir
out in */
+ BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 16, 0, 0, 0,
0, 0, 16, 1, 0),
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
@@ -931,11 +931,11 @@ static struct meson_axg_pmx_data
meson_axg_aobus_pmx_banks_data = {
struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.name = "periphs-banks",
- .pin_base = 11,
+ .pin_base = 15,
.groups = meson_axg_periphs_groups,
.funcs = meson_axg_periphs_functions,
.banks = meson_axg_periphs_banks,
- .num_pins = 100,
+ .num_pins = 86,
.num_groups = ARRAY_SIZE(meson_axg_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_axg_periphs_functions),
.num_banks = ARRAY_SIZE(meson_axg_periphs_banks),
--
2.19.1
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[U-Boot] [PATCH] pinctrl: meson: Fix GPIO direction registers access
The macros used to set the direction of the GPIO pins are misused, resulting in a wrong behavior when trying to read the GPIO input level from U-Boot. A better macro is also used when setting the output direction. Signed-off-by: Carlo Caione --- drivers/pinctrl/meson/pinctrl-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 0bd6152803..b539749752 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -136,7 +136,7 @@ int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) if (ret) return ret; - clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1); + setbits_le32(priv->reg_gpio + reg, BIT(bit)); return 0; } @@ -152,7 +152,7 @@ int meson_gpio_direction_output(struct udevice *dev, if (ret) return ret; - clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0); + clrbits_le32(priv->reg_gpio + reg, BIT(bit)); ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit); if (ret) -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot 10/19] pinctrl: meson: add axg support
On Fri, 2018-11-09 at 16:26 +0100, Neil Armstrong wrote:
> From: Jerome Brunet
>
> This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
> using a specific set of pinctrl functions which differs from the GX
> SoCs.
>
> Signed-off-by: Jerome Brunet
> Signed-off-by: Neil Armstrong
/cut
> +struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
> + .name = "aobus-banks",
> + .pin_base = 0,
> + .groups = meson_axg_aobus_groups,
> + .funcs = meson_axg_aobus_functions,
> + .banks = meson_axg_aobus_banks,
> + .num_pins = 11,
Should this be 14?
--
Carlo Caione
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Re: [U-Boot] [PATCH u-boot 10/19] pinctrl: meson: add axg support
On Fri, 2018-11-09 at 16:26 +0100, Neil Armstrong wrote:
> From: Jerome Brunet
>
> This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
> using a specific set of pinctrl functions which differs from the GX
> SoCs.
>
> Signed-off-by: Jerome Brunet
> Signed-off-by: Neil Armstrong
> ---
/cut
> +static int meson_axg_gpio_request(struct udevice *dev,
> + unsigned int offset, const char
> *label)
> +{
> + return meson_axg_pmx_update_function(dev, offset, 0);
> +}
Hey Neil,
this should be:
meson_axg_pmx_update_function(dev->parent, offset, 0);
since you want to pass the pinctrl udevice (not the gpio one) otherwise
you get a Synchronous Abort when trying to access the pinctrl priv data
(and you can crash the board with `=> gpio input aobus-banks10`).
Cheers,
--
Carlo Caione
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Re: [U-Boot] [PATCH 2/9] rockchip: support 4GB DRAM on 32bit systems
On Thu, 2018-07-26 at 15:59 +0200, Philipp Tomsich wrote: > The calculation in `rockchip_sdram_size` would overflow for 4GB on > 32bit systems (i.e. when PHYS_64BIT is not defined). > > This makes the internal variables and the signature prototype use a > u64 to ensure that we can represent the 33rd bit (as in '4GB'). > Hi Philipp, just to let you know that this is still not working on the veyron jerry chromebook with 4GB I have here (RK3288). The boot stops at: U-Boot SPL 2018.07-00403-gdbe6ef8276 (Jul 26 2018 - 17:21:11 +0100) Trying to boot from SPI U-Boot 2018.07-00403-gdbe6ef8276 (Jul 26 2018 - 17:21:11 +0100) Model: Google Jerry DRAM: 0 Bytes I'm still investigating why but for sure there are several points to fix to have a proper debug, see [0]. Also I was wondering if we should also fix get_effective_memsize() and gd->bd->bi_dram[].size [0]https://gist.github.com/carlocaione/b93cfd9ee71e07fcf68d5c02256ff0fa Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/9] rockchip: support 4GB DRAM on 32bit systems
On Fri, 2018-07-27 at 00:54 +0200, Dr. Philipp Tomsich wrote: > > On 26 Jul 2018, at 22:05, Carlo Caione wrote: > > > > On Thu, 2018-07-26 at 15:59 +0200, Philipp Tomsich wrote: > > > The calculation in `rockchip_sdram_size` would overflow for 4GB > > > on > > > 32bit systems (i.e. when PHYS_64BIT is not defined). > > > > > > This makes the internal variables and the signature prototype use > > > a > > > u64 to ensure that we can represent the 33rd bit (as in '4GB'). > > > > > > > Hi Philipp, > > just to let you know that this is still not working on the veyron > > jerry > > chromebook with 4GB I have here (RK3288). The boot stops at: > > > > U-Boot SPL 2018.07-00403-gdbe6ef8276 (Jul 26 2018 - 17:21:11 +0100) > > Trying to boot from SPI > > > > U-Boot 2018.07-00403-gdbe6ef8276 (Jul 26 2018 - 17:21:11 +0100) > > > > Model: Google Jerry > > DRAM: 0 Bytes > > > > I'm still investigating why but for sure there are several points > > to > > fix to have a proper debug, see [0]. > > I reread ‘rockchip_sdram_size’ and it looks as if I forgot to mark > the value > shifted to create chipsize_mb as ULL. When looking at this code I > had an > uneasy feeling that this might run into the C type rules (i.e. 1 will > be a 32bit > integer and shifting it by 32 would result in 0), but I didn’t think > that this > would ever be the case and that any 4GB DRAM setup would be made > up of multiple channels or of multiple ranks. It doesn't hurt but rockchip_sdram_size() is returning the correct value of 0x1 in my tests. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] rockchip: fix incorrect detection of ram size
On Tue, 2018-07-24 at 10:07 +0200, Dr. Philipp Tomsich wrote: > > I have a patchset for changing the relevant fields in U-Boot to allow > for 33bits (i.e. using u64) for the RAM size and it finally passes > Travis cleanly. > It will be another round or two of cleanup before I can submit the > series — once this happens, I’ll copy you so you can give your > Tested-by if it works… I'm interested. Please put me in CC as well. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/4] rk3288: veyron: Enable SDMMC when booting from SPI
On Mon, 2018-06-11 at 20:00 +0100, Carlo Caione wrote: > From: Carlo Caione > > These patches toghether with the previously submitted patch [0] > enable > the chromebook veyron jerry to use the SDMMC interface when U-Boot is > not chainloaded by depthcharge but booted directly from SPI. > > [0] https://marc.info/?l=u-boot&m=152836928803742&w=2 Hey Philipp, any comment on this v3? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mmc: dw_mmc: Handle pin voltage configuration
On Thu, 2018-06-07 at 12:00 +0100, Carlo Caione wrote: > From: Carlo Caione > > Add support for pin voltage configuration. Besides to support UHS > mode > this is useful when the IO lines are connected to a configurable > regulator not enabled at boot or always on. > > Signed-off-by: Carlo Caione Ping? ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/3] rk3288: Disable JTAG function from sdmmc0 IO
On Mon, 2018-06-11 at 10:41 +0200, Dr. Philipp Tomsich wrote: > > On 11 Jun 2018, at 10:08, Carlo Caione wrote: /cut > > +#define GRF_SOC_CON0 0xff770244 > > #define GRF_SOC_CON2 0xff77024c > > Could you convert these to ‘const uintptr_t GRF_SOC_CON0 = …’ ? > The compiler will generate the same code for a const as if it’s a > define, but we’ll > have full type-safety. Yeah, no problem. But if this is ok with you in v3 I'm going to leave this patch as is and adding one more patch to convert both the lines at the same time. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/4] rk3288: veyron: Init boot-on regulators
From: Carlo Caione
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property.
Signed-off-by: Carlo Caione
Reviewed-by: Simon Glass
Reviewed-by: Philipp Tomsich
Acked-by: Philipp Tomsich
---
arch/arm/mach-rockchip/rk3288-board.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index 8c128d4f94..0365793009 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -122,6 +122,12 @@ static int veyron_init(void)
if (IS_ERR_VALUE(ret))
return ret;
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulators\n", __func__);
+ return ret;
+ }
+
return 0;
}
#endif
--
2.17.1
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[U-Boot] [PATCH v3 3/4] rockchip: veyron: Set vcc33_sd regulator value
From: Carlo Caione
On the veyron board the vcc33_sd regulator is used as vmmc-supply for
the SD card. This regulator is powered in the MMC core during power on
but its value is never actually set.
In the veyron platform the reset value for the LDO output is 1.8V while
the standard (min and max) value for this regulator defined in the DTS
is 3.3V. When the MMC core enable the regulator without setting its
value, the output is automatically set to 1.8V instead of 3.3V.
With this patch we preemptively set the value to 3.3V.
Signed-off-by: Carlo Caione
Reviewed-by: Simon Glass
Reviewed-by: Philipp Tomsich
Acked-by: Philipp Tomsich
---
arch/arm/mach-rockchip/rk3288-board.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index bf24d8e074..0e83c0a947 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -122,6 +122,16 @@ static int veyron_init(void)
if (IS_ERR_VALUE(ret))
return ret;
+ ret = regulator_get_by_platname("vcc33_sd", &dev);
+ if (ret) {
+ debug("Cannot get regulator name\n");
+ return ret;
+ }
+
+ ret = regulator_set_value(dev, 330);
+ if (ret)
+ return ret;
+
ret = regulators_enable_boot_on(false);
if (ret) {
debug("%s: Cannot enable boot on regulators\n", __func__);
--
2.17.1
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[U-Boot] [PATCH v3 4/4] rk3288: Convert register defines to const uintptr_t
From: Carlo Caione
No functional change but at least we can now guarantee type safety.
Signed-off-by: Carlo Caione
---
arch/arm/mach-rockchip/rk3288-board.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index 0e83c0a947..9c4f7f219f 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -317,11 +317,10 @@ U_BOOT_CMD(
""
);
-#define GRF_SOC_CON0 0xff770244
-#define GRF_SOC_CON2 0xff77024c
-
int board_early_init_f(void)
{
+ const uintptr_t GRF_SOC_CON0 = 0xff770244;
+ const uintptr_t GRF_SOC_CON2 = 0xff77024c;
struct udevice *pinctrl;
struct udevice *dev;
int ret;
--
2.17.1
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[U-Boot] [PATCH v3 2/4] rk3288: Disable JTAG function from sdmmc0 IO
From: Carlo Caione The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it is preventing the SDMMC to work correctly. Disable the JTAG function on the assumption that a working SD has higher priority over JTAG. Signed-off-by: Carlo Caione Reviewed-by: Simon Glass Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3288-board.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 0365793009..bf24d8e074 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -307,6 +307,7 @@ U_BOOT_CMD( "" ); +#define GRF_SOC_CON0 0xff770244 #define GRF_SOC_CON2 0xff77024c int board_early_init_f(void) @@ -339,5 +340,11 @@ int board_early_init_f(void) } rk_setreg(GRF_SOC_CON2, 1 << 0); + /* +* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is +* cleared +*/ + rk_clrreg(GRF_SOC_CON0, 1 << 12); + return 0; } -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/4] rk3288: veyron: Enable SDMMC when booting from SPI
From: Carlo Caione These patches toghether with the previously submitted patch [0] enable the chromebook veyron jerry to use the SDMMC interface when U-Boot is not chainloaded by depthcharge but booted directly from SPI. [0] https://marc.info/?l=u-boot&m=152836928803742&w=2 Changelog: V2: - Add Reviewed-by - Expand comment on PATCH 2/3 V3: - More Reviewed-by + Acked-by - New PATCH 4/4 Carlo Caione (4): rk3288: veyron: Init boot-on regulators rk3288: Disable JTAG function from sdmmc0 IO rockchip: veyron: Set vcc33_sd regulator value rk3288: Convert register defines to const uintptr_t arch/arm/mach-rockchip/rk3288-board.c | 26 -- 1 file changed, 24 insertions(+), 2 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] rk3288: Disable JTAG function from sdmmc0 IO
From: Carlo Caione The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it is preventing the SDMMC to work correctly. Disable the JTAG function on the assumption that a working SD has higher priority over JTAG. Signed-off-by: Carlo Caione Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/rk3288-board.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 0365793009..bf24d8e074 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -307,6 +307,7 @@ U_BOOT_CMD( "" ); +#define GRF_SOC_CON0 0xff770244 #define GRF_SOC_CON2 0xff77024c int board_early_init_f(void) @@ -339,5 +340,11 @@ int board_early_init_f(void) } rk_setreg(GRF_SOC_CON2, 1 << 0); + /* +* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is +* cleared +*/ + rk_clrreg(GRF_SOC_CON0, 1 << 12); + return 0; } -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/3] rockchip: veyron: Set vcc33_sd regulator value
From: Carlo Caione
On the veyron board the vcc33_sd regulator is used as vmmc-supply for
the SD card. This regulator is powered in the MMC core during power on
but its value is never actually set.
In the veyron platform the reset value for the LDO output is 1.8V while
the standard (min and max) value for this regulator defined in the DTS
is 3.3V. When the MMC core enable the regulator without setting its
value, the output is automatically set to 1.8V instead of 3.3V.
With this patch we preemptively set the value to 3.3V.
Signed-off-by: Carlo Caione
Reviewed-by: Simon Glass
---
arch/arm/mach-rockchip/rk3288-board.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index bf24d8e074..0e83c0a947 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -122,6 +122,16 @@ static int veyron_init(void)
if (IS_ERR_VALUE(ret))
return ret;
+ ret = regulator_get_by_platname("vcc33_sd", &dev);
+ if (ret) {
+ debug("Cannot get regulator name\n");
+ return ret;
+ }
+
+ ret = regulator_set_value(dev, 330);
+ if (ret)
+ return ret;
+
ret = regulators_enable_boot_on(false);
if (ret) {
debug("%s: Cannot enable boot on regulators\n", __func__);
--
2.17.1
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[U-Boot] [PATCH v2 1/3] rk3288: veyron: Init boot-on regulators
From: Carlo Caione
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property.
Signed-off-by: Carlo Caione
Reviewed-by: Simon Glass
---
arch/arm/mach-rockchip/rk3288-board.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index 8c128d4f94..0365793009 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -122,6 +122,12 @@ static int veyron_init(void)
if (IS_ERR_VALUE(ret))
return ret;
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulators\n", __func__);
+ return ret;
+ }
+
return 0;
}
#endif
--
2.17.1
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[U-Boot] [PATCH v2 0/3] rk3288: veyron: Enable SDMMC when booting from SPI
From: Carlo Caione These patches toghether with the previously submitted patch [0] enable the chromebook veyron jerry to use the SDMMC interface when U-Boot is not chainloaded by depthcharge but booted directly from SPI. [0] https://marc.info/?l=u-boot&m=152836928803742&w=2 Changelog: V2: - Add Reviewed-by - Expand comment on PATCH 2/3 Carlo Caione (3): rk3288: veyron: Init boot-on regulators rk3288: Disable JTAG function from sdmmc0 IO rockchip: veyron: Set vcc33_sd regulator value arch/arm/mach-rockchip/rk3288-board.c | 23 +++ 1 file changed, 23 insertions(+) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] rockchip: veyron: Set vcc33_sd regulator value
From: Carlo Caione
On the veyron board the vcc33_sd regulator is used as vmmc-supply for
the SD card. This regulator is powered in the MMC core during power on
but its value is never actually set.
In the veyron platform the reset value for the LDO output is 1.8V while
the standard (min and max) value for this regulator defined in the DTS
is 3.3V. When the MMC core enable the regulator without setting its
value, the output is automatically set to 1.8V instead of 3.3V.
With this patch we preemptively set the value to 3.3V.
Signed-off-by: Carlo Caione
---
arch/arm/mach-rockchip/rk3288-board.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index 7499201b73..2e95249bbe 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -122,6 +122,16 @@ static int veyron_init(void)
if (IS_ERR_VALUE(ret))
return ret;
+ ret = regulator_get_by_platname("vcc33_sd", &dev);
+ if (ret) {
+ debug("Cannot set regulator name\n");
+ return ret;
+ }
+
+ ret = regulator_set_value(dev, 330);
+ if (ret)
+ return ret;
+
ret = regulators_enable_boot_on(false);
if (ret) {
debug("%s: Cannot enable boot on regulators\n", __func__);
--
2.17.1
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[U-Boot] [PATCH 2/3] rk3288: Disable JTAG function from sdmmc0 IO
From: Carlo Caione The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it is preventing the SDMMC to work correctly. Disable the JTAG function on the assumption that a working SD has higher priority over JTAG. Signed-off-by: Carlo Caione --- arch/arm/mach-rockchip/rk3288-board.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 0365793009..7499201b73 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -307,6 +307,7 @@ U_BOOT_CMD( "" ); +#define GRF_SOC_CON0 0xff770244 #define GRF_SOC_CON2 0xff77024c int board_early_init_f(void) @@ -339,5 +340,8 @@ int board_early_init_f(void) } rk_setreg(GRF_SOC_CON2, 1 << 0); + /* Disable JTAG */ + rk_clrreg(GRF_SOC_CON0, 1 << 12); + return 0; } -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/3] rk3288: veyron: Enable SDMMC when booting from SPI
From: Carlo Caione These patches toghether with the previously submitted patch [0] enable the chromebook veyron jerry to use the SDMMC interface when U-Boot is not chainloaded by depthcharge but booted directly from SPI. [0] https://marc.info/?l=u-boot&m=152836928803742&w=2 Carlo Caione (3): rk3288: veyron: Init boot-on regulators rk3288: Disable JTAG function from sdmmc0 IO rockchip: veyron: Set vcc33_sd regulator value arch/arm/mach-rockchip/rk3288-board.c | 20 1 file changed, 20 insertions(+) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] rk3288: veyron: Init boot-on regulators
From: Carlo Caione
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property.
Signed-off-by: Carlo Caione
---
arch/arm/mach-rockchip/rk3288-board.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index 8c128d4f94..0365793009 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -122,6 +122,12 @@ static int veyron_init(void)
if (IS_ERR_VALUE(ret))
return ret;
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulators\n", __func__);
+ return ret;
+ }
+
return 0;
}
#endif
--
2.17.1
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[U-Boot] [PATCH] mmc: dw_mmc: Handle pin voltage configuration
From: Carlo Caione
Add support for pin voltage configuration. Besides to support UHS mode
this is useful when the IO lines are connected to a configurable
regulator not enabled at boot or always on.
Signed-off-by: Carlo Caione
---
drivers/mmc/dw_mmc.c | 34 ++
include/dwmmc.h | 26 ++
2 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 13180fc0d6..0841d516d2 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#define PAGE_SIZE 4096
@@ -382,6 +383,34 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
return 0;
}
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) && CONFIG_IS_ENABLED(DM_REGULATOR)
+static int dwmci_set_io_regulators(struct mmc *mmc)
+{
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ int uv = mmc_voltage_to_mv(mmc->signal_voltage) * 1000;
+ int ret = 0;
+
+ if (!mmc->vqmmc_supply)
+ return 0;
+
+ host->signal_voltage = mmc->signal_voltage;
+
+ ret = regulator_set_enable(mmc->vqmmc_supply, false);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ ret = regulator_set_value(mmc->vqmmc_supply, uv);
+ if (ret)
+ return ret;
+
+ ret = regulator_set_enable(mmc->vqmmc_supply, true);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DM_MMC
static int dwmci_set_ios(struct udevice *dev)
{
@@ -421,6 +450,11 @@ static int dwmci_set_ios(struct mmc *mmc)
if (host->clksel)
host->clksel(host);
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) && CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (host->signal_voltage != mmc->signal_voltage)
+ return dwmci_set_io_regulators(mmc);
+#endif
+
return 0;
}
diff --git a/include/dwmmc.h b/include/dwmmc.h
index bc1d6e3abb..461141af54 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -133,18 +133,19 @@
/**
* struct dwmci_host - Information about a designware MMC host
*
- * @name: Device name
- * @ioaddr:Base I/O address of controller
- * @quirks:Quick flags - see DWMCI_QUIRK_...
- * @caps: Capabilities - see MMC_MODE_...
- * @bus_hz:Bus speed in Hz, if @get_mmc_clk() is NULL
- * @div: Arbitrary clock divider value for use by controller
- * @dev_index: Arbitrary device index for use by controller
- * @dev_id:Arbitrary device ID for use by controller
- * @buswidth: Bus width in bits (8 or 4)
- * @fifoth_val:Value for FIFOTH register (or 0 to leave unset)
- * @mmc: Pointer to generic MMC structure for this device
- * @priv: Private pointer for use by controller
+ * @name: Device name
+ * @ioaddr:Base I/O address of controller
+ * @quirks:Quick flags - see DWMCI_QUIRK_...
+ * @caps: Capabilities - see MMC_MODE_...
+ * @bus_hz:Bus speed in Hz, if @get_mmc_clk() is NULL
+ * @div: Arbitrary clock divider value for use by controller
+ * @signal_voltage:Current voltage for the IO lines
+ * @dev_index: Arbitrary device index for use by controller
+ * @dev_id:Arbitrary device ID for use by controller
+ * @buswidth: Bus width in bits (8 or 4)
+ * @fifoth_val:Value for FIFOTH register (or 0 to leave unset)
+ * @mmc: Pointer to generic MMC structure for this device
+ * @priv: Private pointer for use by controller
*/
struct dwmci_host {
const char *name;
@@ -155,6 +156,7 @@ struct dwmci_host {
unsigned int clock;
unsigned int bus_hz;
unsigned int div;
+ unsigned int signal_voltage;
int dev_index;
int dev_id;
int buswidth;
--
2.17.1
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[U-Boot] [PATCH] sf: Add support for gd25q32b gigadevice flash
From: Carlo Caione
This flash IC is used in some chromebook models manufactured by Bitland.
Signed-off-by: Carlo Caione
---
drivers/mtd/spi/spi_flash_ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index 5d146e36c6..c45d2e80be 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -63,6 +63,7 @@ const struct spi_flash_info spi_flash_ids[] = {
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
{"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024,64, SECT_4K) },
{"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024,64, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
--
2.17.0
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[U-Boot] Booting Jerry chromebook from eMMC
Hi, I'm trying to boot a Veyron Jerry chromebook using U-Boot placed in the eMMC. Booting from SPI using 'chromebook_jerry_defconfig' works perfectly fine, but I'm hitting a wall when moving from SPI to eMMC (mostly related to the limited space for the SPL). Has anyone managed to boot this platform directly from eMMC? Reading sources and documentation there is explicitly nothing related to boot this platform from eMMC so I was wondering if this is feasible at all. Thank you, -- Carlo Caione | +44.7384.69.16.04 | Endless ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 2/3] mmc: meson: add MMC driver for Meson GX (S905)
This driver implements MMC support on Meson GX (S905) based systems.
It's based on Carlo Caione's work, changes:
- BLK support added
- general refactoring
Signed-off-by: Carlo Caione
Signed-off-by: Andreas Färber
Signed-off-by: Heiner Kallweit
---
v4:
- addressed review comments
- general refactoring
- remove config symbol MMC_MESON_GX_SD_PORT
- changed From: to Carlo Caione
- changed copyright year to 2016
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 89 +
drivers/mmc/Kconfig | 6 +
drivers/mmc/Makefile | 1 +
drivers/mmc/meson_gx_mmc.c| 291 ++
4 files changed, 387 insertions(+)
create mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h
create mode 100644 drivers/mmc/meson_gx_mmc.c
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h
b/arch/arm/include/asm/arch-meson/sd_emmc.h
new file mode 100644
index 000..a09e034
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2016 Carlo Caione
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include
+
+#define SDIO_PORT_A0
+#define SDIO_PORT_B1
+#define SDIO_PORT_C2
+
+#define SD_EMMC_CLKSRC_24M 2400/* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV210 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK0x00
+#define CLK_MAX_DIV 63
+#define CLK_SRC_24M (0 << 6)
+#define CLK_SRC_DIV2 (1 << 6)
+#define CLK_CO_PHASE_000 (0 << 8)
+#define CLK_CO_PHASE_090 (1 << 8)
+#define CLK_CO_PHASE_180 (2 << 8)
+#define CLK_CO_PHASE_270 (3 << 8)
+#define CLK_TX_PHASE_000 (0 << 10)
+#define CLK_TX_PHASE_090 (1 << 10)
+#define CLK_TX_PHASE_180 (2 << 10)
+#define CLK_TX_PHASE_270 (3 << 10)
+#define CLK_ALWAYS_ONBIT(24)
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASKGENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_OWNERBIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+struct meson_mmc_platdata {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ void *regbase;
+ void *w_buf;
+};
+
+#endif
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index df4913b..bc647c8 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -172,6 +172,12 @@ config ZYNQ_SDHCI
help
Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs
platform
+config MMC_MESON_GX
+ bool "Meson GX EMMC controller support"
+ depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_MESON
+ help
+ Support for EMMC host controller on Meson GX ARM SoCs platform (S905)
+
Re: [U-Boot] [PATCH v7 0/4] Amlogic Meson GXBaby and ODROID-C2 support
On Tue, Jul 12, 2016 at 12:54 AM, Andreas Färber wrote:
> Am 12.07.2016 um 00:52 schrieb Carlo Caione:
>> On Mon, Jul 11, 2016 at 11:38 PM, Andreas Färber wrote:
>>> Am 11.07.2016 um 22:36 schrieb Carlo Caione:
>>>> On Mon, Jul 11, 2016 at 10:15 PM, Andreas Färber wrote:
>>
>> [...]
>>
>>>>>
>>>>> DRAM: 2 GiB
>>>>> No maUsing default environment
>>>>>
>>>>> In:serial@4c0
>>>>> Out: serial@4c0
>>>>> Err: serial@4c0
>>>>> Net: No ethernet found.
>>>>> =>
>>>>>
>>>>> The eth_designware line (twice, if counting "No ma") is due to what Tom
>>>>> mentioned wrt DM GPIO, I guess.
>>>>>
>>>>> Shouldn't we get a version line from SPL, too? A serial driver issue?
>>>>
>>>> AFAIKT there is no SPL. U-Boot is loaded by BL3-1 also in the U-Boot
>>>> shipped by amlogic.
>>>
>>> You're right, Hardkernel's version is without SPL, too.
>>>
>>> Still I wonder about that "No ma" (after the DRAM line).
>>
>> drivers/core/lists.c: dm_warn("No match for driver
>> '%s'\n", entry->name);
>>
>> :)
>
> How does that explain the incomplete "No ma"?
The only thing I can think of is a shitty queueing by the UART driver
/ hardware.
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Re: [U-Boot] [PATCH v7 0/4] Amlogic Meson GXBaby and ODROID-C2 support
On Mon, Jul 11, 2016 at 11:38 PM, Andreas Färber wrote:
> Am 11.07.2016 um 22:36 schrieb Carlo Caione:
>> On Mon, Jul 11, 2016 at 10:15 PM, Andreas Färber wrote:
[...]
>>>
>>> DRAM: 2 GiB
>>> No maUsing default environment
>>>
>>> In:serial@4c0
>>> Out: serial@4c0
>>> Err: serial@4c0
>>> Net: No ethernet found.
>>> =>
>>>
>>> The eth_designware line (twice, if counting "No ma") is due to what Tom
>>> mentioned wrt DM GPIO, I guess.
>>>
>>> Shouldn't we get a version line from SPL, too? A serial driver issue?
>>
>> AFAIKT there is no SPL. U-Boot is loaded by BL3-1 also in the U-Boot
>> shipped by amlogic.
>
> You're right, Hardkernel's version is without SPL, too.
>
> Still I wonder about that "No ma" (after the DRAM line).
drivers/core/lists.c: dm_warn("No match for driver
'%s'\n", entry->name);
:)
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Re: [U-Boot] [PATCH v7 0/4] Amlogic Meson GXBaby and ODROID-C2 support
On Mon, Jul 11, 2016 at 10:15 PM, Andreas Färber wrote: > Am 11.07.2016 um 21:48 schrieb Beniamino Galvani: >> On Mon, Jul 11, 2016 at 05:23:15AM +0100, Peter Robinson wrote: >>> On Mon, Jul 11, 2016 at 4:57 AM, Andreas Färber wrote: >>>> Last output: >>>> >>>> NOTICE: BL3-1: v1.0(debug):4d2e34d >>>> NOTICE: BL3-1: Built : 17:08:35, Oct 29 2015 >>>> INFO:BL3-1: Initializing runtime services >>>> INFO:BL3-1: Preparing for EL3 exit to normal world >>>> INFO:BL3-1: Next image address = 0x100 >>>> INFO:BL3-1: Next image spsr = 0x3c9 >>>> >>>> I.e., no U-Boot SPL output on serial. >>> >>> I see similar on Pine64 with 2016.07rc3 >> >> Here the first non-booting commit is: >> >> commit d73718f3236c520a92efa401084c658e6cc067f3 >> Author: Mingkai Hu >> Date: Thu Jul 7 12:22:12 2016 +0800 >> >> armv8: Enable CPUECTLR.SMPEN for coherency > > Thanks! With that reverted I get: > > [...] > NOTICE: BL3-1: v1.0(debug):4d2e34d > NOTICE: BL3-1: Built : 17:08:35, Oct 29 2015 > INFO:BL3-1: Initializing runtime services > INFO:BL3-1: Preparing for EL3 exit to normal world > INFO:BL3-1: Next image address = 0x100 > INFO:BL3-1: Next image spsr = 0x3c9 > No match for driver 'eth_designware' > Some drivers were not found > > > U-Boot 2016.07-1-g10a9e48 (Jul 11 2016 - 21:58:13 +0200) odroid-c2 > > DRAM: 2 GiB > No maUsing default environment > > In:serial@4c0 > Out: serial@4c0 > Err: serial@4c0 > Net: No ethernet found. > => > > The eth_designware line (twice, if counting "No ma") is due to what Tom > mentioned wrt DM GPIO, I guess. > > Shouldn't we get a version line from SPL, too? A serial driver issue? AFAIKT there is no SPL. U-Boot is loaded by BL3-1 also in the U-Boot shipped by amlogic. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/2] Prepare U-Boot for more Amlogic boards
On 10/06/16 20:18, Carlo Caione wrote: > From: Carlo Caione > > Refactor the Odroid-C2 support code to prepare U-Boot for more Amlogic board > submissions. > The goal is to reduce the redundancy of the configuration files and unify all > the board support files onto a single amlogic directory. > > Changelog: > v2: > - Added Reviewed-by > - Now 2/2 clearly shows the renaming What's left for this patchset? I have a couple of submissions depending on this one. -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] board: amlogic: Rename folder for Amlogic boards
From: Carlo Caione
s/hardkernel/amlogic/ to have a single place for all the amlogic-based
boards.
Reviewed-by: Simon Glass
Signed-off-by: Carlo Caione
---
arch/arm/mach-meson/Kconfig | 2 +-
board/{hardkernel => amlogic}/odroid-c2/Kconfig | 2 +-
board/{hardkernel => amlogic}/odroid-c2/MAINTAINERS | 2 +-
board/{hardkernel => amlogic}/odroid-c2/Makefile| 0
board/{hardkernel => amlogic}/odroid-c2/README | 0
board/{hardkernel => amlogic}/odroid-c2/odroid-c2.c | 0
6 files changed, 3 insertions(+), 3 deletions(-)
rename board/{hardkernel => amlogic}/odroid-c2/Kconfig (85%)
rename board/{hardkernel => amlogic}/odroid-c2/MAINTAINERS (80%)
rename board/{hardkernel => amlogic}/odroid-c2/Makefile (100%)
rename board/{hardkernel => amlogic}/odroid-c2/README (100%)
rename board/{hardkernel => amlogic}/odroid-c2/odroid-c2.c (100%)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 77d3cfe..af3be59 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -26,6 +26,6 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
default 0x1000
-source "board/hardkernel/odroid-c2/Kconfig"
+source "board/amlogic/odroid-c2/Kconfig"
endif
diff --git a/board/hardkernel/odroid-c2/Kconfig
b/board/amlogic/odroid-c2/Kconfig
similarity index 85%
rename from board/hardkernel/odroid-c2/Kconfig
rename to board/amlogic/odroid-c2/Kconfig
index 687d9c6..2b16889 100644
--- a/board/hardkernel/odroid-c2/Kconfig
+++ b/board/amlogic/odroid-c2/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
default "odroid-c2"
config SYS_VENDOR
- default "hardkernel"
+ default "amlogic"
config SYS_CONFIG_NAME
default "odroid-c2"
diff --git a/board/hardkernel/odroid-c2/MAINTAINERS
b/board/amlogic/odroid-c2/MAINTAINERS
similarity index 80%
rename from board/hardkernel/odroid-c2/MAINTAINERS
rename to board/amlogic/odroid-c2/MAINTAINERS
index 23ae1e7..699850f 100644
--- a/board/hardkernel/odroid-c2/MAINTAINERS
+++ b/board/amlogic/odroid-c2/MAINTAINERS
@@ -1,6 +1,6 @@
ODROID-C2
M: Beniamino Galvani
S: Maintained
-F: board/hardkernel/odroid-c2/
+F: board/amlogic/odroid-c2/
F: include/configs/odroid-c2.h
F: configs/odroid-c2_defconfig
diff --git a/board/hardkernel/odroid-c2/Makefile
b/board/amlogic/odroid-c2/Makefile
similarity index 100%
rename from board/hardkernel/odroid-c2/Makefile
rename to board/amlogic/odroid-c2/Makefile
diff --git a/board/hardkernel/odroid-c2/README b/board/amlogic/odroid-c2/README
similarity index 100%
rename from board/hardkernel/odroid-c2/README
rename to board/amlogic/odroid-c2/README
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c
b/board/amlogic/odroid-c2/odroid-c2.c
similarity index 100%
rename from board/hardkernel/odroid-c2/odroid-c2.c
rename to board/amlogic/odroid-c2/odroid-c2.c
--
2.7.4
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[U-Boot] [PATCH v2 1/2] configs: gxbb: Introduce a common config header file
From: Carlo Caione Introduce a meson-gxbb-common.h header file and derive the configuration for Hardkernel Odroid-C2 board from that. Reviewed-by: Simon Glass Signed-off-by: Carlo Caione --- include/configs/meson-gxbb-common.h | 45 + include/configs/odroid-c2.h | 34 +--- 2 files changed, 46 insertions(+), 33 deletions(-) create mode 100644 include/configs/meson-gxbb-common.h diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h new file mode 100644 index 000..d1c0050 --- /dev/null +++ b/include/configs/meson-gxbb-common.h @@ -0,0 +1,45 @@ +/* + * Configuration for Amlogic Meson GXBB SoCs + * (C) Copyright 2016 Beniamino Galvani + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __MESON_GXBB_COMMON_CONFIG_H +#define __MESON_GXBB_COMMON_CONFIG_H + +#define CONFIG_CPU_ARMV8 +#define CONFIG_REMAKE_ELF +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE0x2000 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_TEXT_BASE 0x0100 +#define CONFIG_SYS_INIT_SP_ADDR0x2000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xc4301000 +#define GICC_BASE 0xc4302000 + +#define CONFIG_CMD_ENV + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#include + +#endif /* __MESON_GXBB_COMMON_CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h index 37a5671..bf5df9c 100644 --- a/include/configs/odroid-c2.h +++ b/include/configs/odroid-c2.h @@ -8,44 +8,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_CPU_ARMV8 -#define CONFIG_REMAKE_ELF -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_NO_FLASH -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE0x2000 -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_TEXT_BASE 0x0100 -#define CONFIG_SYS_INIT_SP_ADDR0x2000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xc4301000 -#define GICC_BASE 0xc4302000 - #define CONFIG_IDENT_STRING" odroid-c2" /* Serial setup */ #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE115200 -#define CONFIG_CMD_ENV - -/* Monitor Command Prompt */ -/* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -#include +#include #endif /* __CONFIG_H */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/2] Prepare U-Boot for more Amlogic boards
From: Carlo Caione
Refactor the Odroid-C2 support code to prepare U-Boot for more Amlogic board
submissions.
The goal is to reduce the redundancy of the configuration files and unify all
the board support files onto a single amlogic directory.
Changelog:
v2:
- Added Reviewed-by
- Now 2/2 clearly shows the renaming
Carlo Caione (2):
configs: gxbb: Introduce a common config header file
board: amlogic: Rename folder for Amlogic boards
arch/arm/mach-meson/Kconfig| 2 +-
board/{hardkernel => amlogic}/odroid-c2/Kconfig| 2 +-
.../{hardkernel => amlogic}/odroid-c2/MAINTAINERS | 2 +-
board/{hardkernel => amlogic}/odroid-c2/Makefile | 0
board/{hardkernel => amlogic}/odroid-c2/README | 0
.../{hardkernel => amlogic}/odroid-c2/odroid-c2.c | 0
include/configs/meson-gxbb-common.h| 45 ++
include/configs/odroid-c2.h| 34 +---
8 files changed, 49 insertions(+), 36 deletions(-)
rename board/{hardkernel => amlogic}/odroid-c2/Kconfig (85%)
rename board/{hardkernel => amlogic}/odroid-c2/MAINTAINERS (80%)
rename board/{hardkernel => amlogic}/odroid-c2/Makefile (100%)
rename board/{hardkernel => amlogic}/odroid-c2/README (100%)
rename board/{hardkernel => amlogic}/odroid-c2/odroid-c2.c (100%)
create mode 100644 include/configs/meson-gxbb-common.h
--
2.7.4
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Re: [U-Boot] [PATCH 2/2] board: amlogic: Rename folder for Amlogic boards
On 10/06/16 09:03, Ben Dooks wrote: > do you have git rename-detection enabled? I simply forgot to pass '-M' to git-format-patch. I can submit a v2 if requested. Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] board: amlogic: Rename folder for Amlogic boards
From: Carlo Caione s/hardkernel/amlogic/ to have a single place for all the amlogic-based boards. Signed-off-by: Carlo Caione --- arch/arm/mach-meson/Kconfig| 2 +- board/amlogic/odroid-c2/Kconfig| 12 ++ board/amlogic/odroid-c2/MAINTAINERS| 6 +++ board/amlogic/odroid-c2/Makefile | 7 board/amlogic/odroid-c2/README | 60 ++ board/amlogic/odroid-c2/odroid-c2.c| 67 ++ board/hardkernel/odroid-c2/Kconfig | 12 -- board/hardkernel/odroid-c2/MAINTAINERS | 6 --- board/hardkernel/odroid-c2/Makefile| 7 board/hardkernel/odroid-c2/README | 60 -- board/hardkernel/odroid-c2/odroid-c2.c | 67 -- 11 files changed, 153 insertions(+), 153 deletions(-) create mode 100644 board/amlogic/odroid-c2/Kconfig create mode 100644 board/amlogic/odroid-c2/MAINTAINERS create mode 100644 board/amlogic/odroid-c2/Makefile create mode 100644 board/amlogic/odroid-c2/README create mode 100644 board/amlogic/odroid-c2/odroid-c2.c delete mode 100644 board/hardkernel/odroid-c2/Kconfig delete mode 100644 board/hardkernel/odroid-c2/MAINTAINERS delete mode 100644 board/hardkernel/odroid-c2/Makefile delete mode 100644 board/hardkernel/odroid-c2/README delete mode 100644 board/hardkernel/odroid-c2/odroid-c2.c diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 77d3cfe..af3be59 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -26,6 +26,6 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x1000 -source "board/hardkernel/odroid-c2/Kconfig" +source "board/amlogic/odroid-c2/Kconfig" endif diff --git a/board/amlogic/odroid-c2/Kconfig b/board/amlogic/odroid-c2/Kconfig new file mode 100644 index 000..2b16889 --- /dev/null +++ b/board/amlogic/odroid-c2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_C2 + +config SYS_BOARD + default "odroid-c2" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "odroid-c2" + +endif diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/odroid-c2/MAINTAINERS new file mode 100644 index 000..699850f --- /dev/null +++ b/board/amlogic/odroid-c2/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-C2 +M: Beniamino Galvani +S: Maintained +F: board/amlogic/odroid-c2/ +F: include/configs/odroid-c2.h +F: configs/odroid-c2_defconfig diff --git a/board/amlogic/odroid-c2/Makefile b/board/amlogic/odroid-c2/Makefile new file mode 100644 index 000..571044b --- /dev/null +++ b/board/amlogic/odroid-c2/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Beniamino Galvani +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-c2.o diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README new file mode 100644 index 000..d6d266a --- /dev/null +++ b/board/amlogic/odroid-c2/README @@ -0,0 +1,60 @@ +U-Boot for ODROID-C2 + + +ODROID-C2 is a single board computer manufactured by Hardkernel +Co. Ltd with the following specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + +u-boot compilation +== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make odroid-c2_defconfig + > make + +Image creation +== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > DIR=odroid-c2 + > git clone --depth 1 \ + https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ + $DIR + > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ + --bl301 $DIR/fip/gxb/bl301.bin \ + --bl31 $DIR/fip/gxb/bl31.bin \ + --bl33 u-boot.bin \ + $DIR/fip.bin + > $DIR/fip/fip_create --dump $DIR/fip.bin + > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin + > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ +--input $DIR/boot_new.bin \ +--output $DIR/u-boot.img + > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > BL1=$DIR/sd_fuse/bl1.bin.hardkernel + > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 + > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 + > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 di
[U-Boot] [PATCH 1/2] configs: gxbb: Introduce a common config header file
From: Carlo Caione Introduce a meson-gxbb-common.h header file and derive the configuration for Hardkernel Odroid-C2 board from that. Signed-off-by: Carlo Caione --- include/configs/meson-gxbb-common.h | 45 + include/configs/odroid-c2.h | 34 +--- 2 files changed, 46 insertions(+), 33 deletions(-) create mode 100644 include/configs/meson-gxbb-common.h diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h new file mode 100644 index 000..d1c0050 --- /dev/null +++ b/include/configs/meson-gxbb-common.h @@ -0,0 +1,45 @@ +/* + * Configuration for Amlogic Meson GXBB SoCs + * (C) Copyright 2016 Beniamino Galvani + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __MESON_GXBB_COMMON_CONFIG_H +#define __MESON_GXBB_COMMON_CONFIG_H + +#define CONFIG_CPU_ARMV8 +#define CONFIG_REMAKE_ELF +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE0x2000 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_TEXT_BASE 0x0100 +#define CONFIG_SYS_INIT_SP_ADDR0x2000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xc4301000 +#define GICC_BASE 0xc4302000 + +#define CONFIG_CMD_ENV + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#include + +#endif /* __MESON_GXBB_COMMON_CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h index 37a5671..bf5df9c 100644 --- a/include/configs/odroid-c2.h +++ b/include/configs/odroid-c2.h @@ -8,44 +8,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_CPU_ARMV8 -#define CONFIG_REMAKE_ELF -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_NO_FLASH -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE0x2000 -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_TEXT_BASE 0x0100 -#define CONFIG_SYS_INIT_SP_ADDR0x2000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xc4301000 -#define GICC_BASE 0xc4302000 - #define CONFIG_IDENT_STRING" odroid-c2" /* Serial setup */ #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE115200 -#define CONFIG_CMD_ENV - -/* Monitor Command Prompt */ -/* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -#include +#include #endif /* __CONFIG_H */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] Prepare U-Boot for more Amlogic boards
From: Carlo Caione Refactor the Odroid-C2 support code to prepare U-Boot for more Amlogic board submissions. The goal is to reduce the redundancy of the configuration files and unify all the board support files onto a single amlogic directory. Carlo Caione (2): configs: gxbb: Introduce a common config header file board: amlogic: Rename folder for Amlogic boards arch/arm/mach-meson/Kconfig| 2 +- board/amlogic/odroid-c2/Kconfig| 12 ++ board/amlogic/odroid-c2/MAINTAINERS| 6 +++ board/amlogic/odroid-c2/Makefile | 7 board/amlogic/odroid-c2/README | 60 ++ board/amlogic/odroid-c2/odroid-c2.c| 67 ++ board/hardkernel/odroid-c2/Kconfig | 12 -- board/hardkernel/odroid-c2/MAINTAINERS | 6 --- board/hardkernel/odroid-c2/Makefile| 7 board/hardkernel/odroid-c2/README | 60 -- board/hardkernel/odroid-c2/odroid-c2.c | 67 -- include/configs/meson-gxbb-common.h| 45 +++ include/configs/odroid-c2.h| 34 + 13 files changed, 199 insertions(+), 186 deletions(-) create mode 100644 board/amlogic/odroid-c2/Kconfig create mode 100644 board/amlogic/odroid-c2/MAINTAINERS create mode 100644 board/amlogic/odroid-c2/Makefile create mode 100644 board/amlogic/odroid-c2/README create mode 100644 board/amlogic/odroid-c2/odroid-c2.c delete mode 100644 board/hardkernel/odroid-c2/Kconfig delete mode 100644 board/hardkernel/odroid-c2/MAINTAINERS delete mode 100644 board/hardkernel/odroid-c2/Makefile delete mode 100644 board/hardkernel/odroid-c2/README delete mode 100644 board/hardkernel/odroid-c2/odroid-c2.c create mode 100644 include/configs/meson-gxbb-common.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 0/4] Amlogic Meson GXBaby and ODROID-C2 support
On 08/05/16 08:30, Beniamino Galvani wrote: > Hi, > > this series adds a very basic support for Amlogic S905 SoC (GXBaby) > and for the ODROID-C2 board [1], and is based on u-boot sources > available from the board vendor [2]. At the moment the only supported > devices are the integrated UART and Ethernet adapter. Hey guys, what's left for this patchset to be merged? -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Add support for Amlogic Meson MMC controller
On 20/05/16 11:58, Robert Gadsdon wrote:
> On 05/20/2016 01:07 AM, Carlo Caione wrote:
> > On 20/05/16 08:27, Carlo Caione wrote:
> >> On 19/05/16 21:51, Robert Gadsdon wrote:
> >>> Applied this on my Odroid C2, and it worked OK when installed on the
> >>> SDcard, but failed when installed on the eMMC module:
> >
> > Oh, reading this again you meant that you put u-boot directly on the
> > eMMC? Ok then, something is wrong when using the driver with the eMMC.
> >
>
> Yes, I installed it directly on the eMMC, using the micro-sd adapter,
> and following the same instructions as for the SDcard..
Could you try with this patch?
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c
b/board/hardkernel/odroid-c2/odroid-c2.c
index 34b9a95..ab78328 100644
--- a/board/hardkernel/odroid-c2/odroid-c2.c
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -80,6 +80,11 @@ U_BOOT_DEVICE(meson_mmc) = {
.platdata = &gxbb_sd_platdata[CONFIG_MMC_MESON_SD_PORT],
};
+U_BOOT_DEVICE(meson_emmc) = {
+ .name = "meson_mmc",
+ .platdata = &gxbb_sd_platdata[2],
+};
+
static void meson_mmc_pinmux_setup(unsigned int port)
{
switch (port) {
Thanks,
--
Carlo Caione
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Re: [U-Boot] [PATCH v7 3/4] arm: add initial support for Amlogic Meson and ODROID-C2
On 08/05/16 08:30, Beniamino Galvani wrote: > This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a > board definition for ODROID-C2. This initial submission only supports > UART and Ethernet (through the existing Designware driver). DTS files > are the ones submitted to Linux arm-soc for 4.7 [1]. > > [1] https://patchwork.ozlabs.org/patch/603583/ > > Signed-off-by: Beniamino Galvani > Reviewed-by: Simon Glass > --- > arch/arm/Kconfig | 9 ++ > arch/arm/Makefile | 1 + > arch/arm/dts/Makefile | 2 + > arch/arm/dts/meson-gxbb-odroidc2.dts | 69 + > arch/arm/dts/meson-gxbb.dtsi | 178 > + > arch/arm/include/asm/arch-meson/gxbb.h | 52 ++ > arch/arm/mach-meson/Kconfig| 31 ++ > arch/arm/mach-meson/Makefile | 7 ++ > arch/arm/mach-meson/board.c| 66 > board/hardkernel/odroid-c2/Kconfig | 12 +++ > board/hardkernel/odroid-c2/MAINTAINERS | 6 ++ > board/hardkernel/odroid-c2/Makefile| 7 ++ > board/hardkernel/odroid-c2/README | 60 +++ > board/hardkernel/odroid-c2/odroid-c2.c | 51 ++ I suggest to have s/hardkernel/amlogic/ so that we can have all the amlogic boards in the same place. Also I wonder if it's worth to have one single board file board.c so to avoid duplicating code among the boards, especially now that the DT support is still incomplete. Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Add support for Amlogic Meson MMC controller
On 19/05/16 21:51, Robert Gadsdon wrote: > Applied this on my Odroid C2, and it worked OK when installed on the > SDcard, but failed when installed on the eMMC module: > > => version > U-Boot 2016.05-rc3 (May 14 2016 - 21:06:28 -0700) odroid-c2 > aarch64-linux-gnu-gcc (GCC) 5.3.1 20160212 (Red Hat Cross 5.3.1-2) > GNU ld version 2.26.20160125 > > => mmc info > Card did not respond to voltage select! Yes, this is expected since the muxing in the board file is only enabling the SDcard. Could you try to set the correct muxing also for the eMMC and check again? Unfortunately I don't have an eMMC for the Odroid-C2 to check this out. I'll try to prepare a board file also for the P20x so I can test this better. Thank you for testing this BTW. Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Add support for Amlogic Meson MMC controller
On 20/05/16 08:27, Carlo Caione wrote: > On 19/05/16 21:51, Robert Gadsdon wrote: > > Applied this on my Odroid C2, and it worked OK when installed on the > > SDcard, but failed when installed on the eMMC module: Oh, reading this again you meant that you put u-boot directly on the eMMC? Ok then, something is wrong when using the driver with the eMMC. I'll try to boot it on the P20x and check what's wrong with it. Thanks, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver
On Fri, May 13, 2016 at 3:46 PM, Kevin Hilman wrote:
> Carlo Caione writes:
>
>> From: Carlo Caione
>>
>> This is a port / rewrite of the Amlogic driver shipped whithin the
>> Amlogic SDK for the Meson GXBaby (S905) SoC.
>>
>> Signed-off-by: Carlo Caione
>
> [...]
>
>> +static const struct udevice_id meson_mmc_match[] = {
>> + { .compatible = "amlogic,meson-mmc" },
>> + { /* sentinel */ }
>
> IIUC, this controller is different between meson8* and gxbb. If that's
> the case, this compatible should probably be more specific.
Yes, this is a point I raised also on lkml when I submitted the MMC
driver for the Meson8b.
Since the registers mapping is different I assume that this is the
case. Just to be sure, given that you are the only one with a
datasheet for the GXBB, can you confirm that?
Actually for the same reason I was in doubt if CONFIG_MMC_MESON was a
right naming choice here, but since it is really unlikely that we will
ever see a U-Boot port for the Meson8b I stuck with that.
Cheers,
--
Carlo Caione
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[U-Boot] [PATCH 1/2] mmc: Add Amlogic Meson driver
From: Carlo Caione
This is a port / rewrite of the Amlogic driver shipped whithin the
Amlogic SDK for the Meson GXBaby (S905) SoC.
Signed-off-by: Carlo Caione
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 109 +++
drivers/mmc/Makefile | 1 +
drivers/mmc/meson_mmc.c | 305 ++
3 files changed, 415 insertions(+)
create mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h
create mode 100644 drivers/mmc/meson_mmc.c
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h
b/arch/arm/include/asm/arch-meson/sd_emmc.h
new file mode 100644
index 000..6781dca
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2016 Carlo Caione
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include
+
+#define SDIO_PORT_A0
+#define SDIO_PORT_B1
+#define SDIO_PORT_C2
+
+#define SD_EMMC_BASE_A 0xd007
+#define SD_EMMC_BASE_B 0xd0072000
+#define SD_EMMC_BASE_C 0xd0074000
+
+#define SD_IRQ_ALL 0x3fff
+
+#define SD_EMMC_CLKSRC_24M 2400
+#define SD_EMMC_CLKSRC_DIV210
+
+#define CLK_DIV0
+#define CLK_SRC6
+#define CLK_CO_PHASE 8
+#define CLK_ALWAYS_ON 24
+
+#define ADDR_USE_PING_BUF BIT(1)
+
+#define SD_EMMC_RXD_ERROR BIT(0)
+#define SD_EMMC_TXD_ERROR BIT(1)
+#define SD_EMMC_DESC_ERROR BIT(2)
+#define SD_EMMC_RESP_CRC_ERROR BIT(3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR BIT(4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR BIT(5)
+
+#define CFG_BUS_WIDTH 0
+#define CFG_BUS_WIDTH_MASK (0x3 << 0)
+#define CFG_BL_LEN 4
+#define CFG_BL_LEN_MASK(0xf << 4)
+#define CFG_RESP_TIMEOUT 8
+#define CFG_RESP_TIMEOUT_MASK (0xf << 8)
+#define CFG_RC_CC 12
+#define CFG_RC_CC_MASK (0xf << 12)
+
+#define STATUS_RXD_ERR_MASK0xff
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERRBIT(9)
+#define STATUS_RESP_ERRBIT(10)
+#define STATUS_RESP_TIMEOUTBIT(11)
+#define STATUS_DESC_TIMEOUTBIT(12)
+#define STATUS_END_OF_CHAINBIT(13)
+
+#define CMD_CFG_LENGTH_MASK0x1ff
+#define CMD_CFG_CMD_INDEX 24
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1BBIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_NO_RESPBIT(16)
+#define CMD_CFG_DATA_IOBIT(18)
+#define CMD_CFG_DATA_WRBIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_OWNER BIT(31)
+
+struct meson_mmc_regs {
+ uint32_t gclock;
+ uint32_t gdelay;
+ uint32_t gadjust;
+ uint32_t reserved_0c;
+ uint32_t gcalout;
+ uint32_t reserved_14[11];
+ uint32_t gstart;
+ uint32_t gcfg;
+ uint32_t gstatus;
+ uint32_t girq_en;
+ uint32_t gcmd_cfg;
+ uint32_t gcmd_arg;
+ uint32_t gcmd_dat;
+ uint32_t gcmd_rsp0;
+ uint32_t gcmd_rsp1;
+ uint32_t gcmd_rsp2;
+ uint32_t gcmd_rsp3;
+ uint32_t reserved_6c;
+ uint32_t gcurr_cfg;
+ uint32_t gcurr_arg;
+ uint32_t gcurr_dat;
+ uint32_t gcurr_rsp;
+ uint32_t gnext_cfg;
+ uint32_t gnext_arg;
+ uint32_t gnext_dat;
+ uint32_t gnext_rsp;
+ uint32_t grxd;
+ uint32_t gtxd;
+ uint32_t reserved_98[90];
+ uint32_t gdesc[128];
+ uint32_t gping[128];
+ uint32_t gpong[128];
+};
+
+struct meson_mmc_platdata {
+ struct mmc_config cfg;
+ struct meson_mmc_regs *sd_emmc_reg;
+ char *w_buf;
+};
+
+#endif
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 585aaf3..08ac9ba 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
obj-$(CONFIG_GENERIC_MMC) += mmc.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_MMC_MESON) += meson_mmc.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
diff --git a/drivers/mmc/meson_mmc.c b/drivers/mmc/meson_mmc.c
new file mode 100644
index 000..af224ec
--- /dev/null
+++ b/drivers/mmc/meson_mmc.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2016 Carlo Caione
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#inclu
[U-Boot] [PATCH 0/2] Add support for Amlogic Meson MMC controller
From: Carlo Caione This patchset is a port / rewrite of the Amlogic driver shipped in the SDK for the Meson GXBB (S905) platform. It has been tested on the Hardkernel Odroid-C2 board. The driver is enabled using U_BOOT_DEVICE in the board file because there is no MMC driver yet in the linux kernel. This patchset depends on the basic support for Amlogic S905 SoCs written by Beniamino[1] [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg212188.html Carlo Caione (2): mmc: Add Amlogic Meson driver arm: amlogic: Enable MMC driver on Odroid-C2 arch/arm/include/asm/arch-meson/sd_emmc.h | 109 +++ board/hardkernel/odroid-c2/odroid-c2.c| 42 configs/odroid-c2_defconfig | 5 + drivers/mmc/Makefile | 1 + drivers/mmc/meson_mmc.c | 305 ++ include/configs/odroid-c2.h | 7 + 6 files changed, 469 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h create mode 100644 drivers/mmc/meson_mmc.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] arm: amlogic: Enable MMC driver on Odroid-C2
From: Carlo Caione
Add support for the MMC on the Hardkernel Odroid-C2 board.
Signed-off-by: Carlo Caione
---
board/hardkernel/odroid-c2/odroid-c2.c | 42 ++
configs/odroid-c2_defconfig| 5
include/configs/odroid-c2.h| 7 ++
3 files changed, 54 insertions(+)
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c
b/board/hardkernel/odroid-c2/odroid-c2.c
index bd72100..34b9a95 100644
--- a/board/hardkernel/odroid-c2/odroid-c2.c
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
@@ -65,3 +66,44 @@ int misc_init_r(void)
return 0;
}
+
+#ifdef CONFIG_GENERIC_MMC
+
+static const struct meson_mmc_platdata gxbb_sd_platdata[] = {
+ { .sd_emmc_reg = (struct meson_mmc_regs *)SD_EMMC_BASE_A },
+ { .sd_emmc_reg = (struct meson_mmc_regs *)SD_EMMC_BASE_B },
+ { .sd_emmc_reg = (struct meson_mmc_regs *)SD_EMMC_BASE_C },
+};
+
+U_BOOT_DEVICE(meson_mmc) = {
+ .name = "meson_mmc",
+ .platdata = &gxbb_sd_platdata[CONFIG_MMC_MESON_SD_PORT],
+};
+
+static void meson_mmc_pinmux_setup(unsigned int port)
+{
+ switch (port) {
+ case SDIO_PORT_A:
+ setbits_le32(GXBB_PINMUX(8), 0x3f);
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(GXBB_PINMUX(2), 0x3f << 10);
+ break;
+ case SDIO_PORT_C:
+ clrbits_le32(GXBB_PINMUX(2), 0x1f << 22);
+ setbits_le32(GXBB_PINMUX(4), (0x3 << 18) | (3 << 30));
+ break;
+ default:
+ printf("meson: invalid MMC port %d for pinmux setup\n", port);
+ break;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ meson_mmc_pinmux_setup(CONFIG_MMC_MESON_SD_PORT);
+
+ return 0;
+}
+
+#endif
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index a771b20..a1ffe73 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -7,11 +7,16 @@ CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DEBUG_UART=y
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index 37a5671..4af7cc6 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -46,6 +46,13 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
+#ifdef CONFIG_DM_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_MESON
+#define CONFIG_MMC_MESON_SD_PORT 1
+#endif
+
#include
#endif /* __CONFIG_H */
--
2.7.4
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Re: [U-Boot] [PATCH v2 8/9] arm: dts: add ethernet node to Meson gxbb
On Sun, Apr 3, 2016 at 9:18 AM, Beniamino Galvani wrote:
> Add a node for the Synopsys Designware Ethernet adapter available on
> Meson SoCs to the Meson GXBaby DTS files. The node is not present in
> DTS files used in Linux kernel.
>
> Signed-off-by: Beniamino Galvani
> ---
> arch/arm/dts/meson-gxbb-odroidc2.dts | 4
> arch/arm/dts/meson-gxbb.dtsi | 9 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts
> b/arch/arm/dts/meson-gxbb-odroidc2.dts
> index 653c2fa..408235d 100644
> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> @@ -67,3 +67,7 @@
> &uart_AO {
> status = "okay";
> };
> +
> +&gmac0 {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
> index 832815d..44a54e7 100644
> --- a/arch/arm/dts/meson-gxbb.dtsi
> +++ b/arch/arm/dts/meson-gxbb.dtsi
> @@ -167,6 +167,15 @@
> };
> };
>
> + gmac0: ethernet@c941 {
> + compatible = "snps,dwmac";
> + reg = <0x0 0xc941 0x0 0x1>;
> + interrupts = <0 8 1>;
> + interrupt-names = "macirq";
> + phy-mode = "rgmii";
> + status = "disabled";
> + };
> +
> apb: apb@d000 {
> compatible = "simple-bus";
> reg = <0x0 0xd000 0x0 0x20>;
Adding this gmac node means that this DTS is already different from
the DTS we have in mainline. This makes me wonder how in u-boot we
manages the difference in the DT between the kernel and u-boot. Are
they supposed to be always in sync or we expect to have two different
DTs?
--
Carlo Caione
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Re: [U-Boot] [PATCH 5/5] meson: odroid-c2: enable serial
On Sun, Mar 27, 2016 at 10:22 PM, Beniamino Galvani wrote: > Enable serial support in the ODROID-C2 configuration. > > Signed-off-by: Beniamino Galvani > --- > configs/odroid-c2_defconfig | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig > index 66d9ab7..e0cd403 100644 > --- a/configs/odroid-c2_defconfig > +++ b/configs/odroid-c2_defconfig > @@ -4,6 +4,11 @@ CONFIG_MESON_GXBB=y > CONFIG_TARGET_ODROID_C2=y > CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" > CONFIG_OF_CONTROL=y > +CONFIG_MESON_SERIAL=y > +CONFIG_DEBUG_UART_MESON=y > +GONFIG_DEBUG_UART_BASE=0xc81004c0 s/GONFIG/CONFIG/ > +CONFIG_DEBUG_UART_ANNOUNCE=y > +CONFIG_DEBUG_UART_SKIP_INIT=y > # CONFIG_CMD_BDI is not set > # CONFIG_CMD_IMI is not set > # CONFIG_CMD_IMLS is not set > -- > 2.4.3 -- Carlo Caione | +39.340.80.30.096 | Endless ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/5] Basic support for Amlogic GXBaby and ODROID-C2
On Sun, Mar 27, 2016 at 10:22 PM, Beniamino Galvani wrote: > Hi, > > this series adds a very basic support for Amlogic S905 SoC (GXBaby) > and for the ODROID-C2 board [1], and is based on u-boot sources > available from the board vendor [2]. > > Mainline kernel support is still in early stages [3] and the plan is > to add more features to u-boot (mmc, ethernet, ...) as soon as they > are available in the kernel; this submission only includes definition > of platform, board and UART support. Tested-by: Carlo Caione Thank you Beniamino for this. Could you please keep linux-me...@googlegroups.com in CC for the next submissions? Cheers, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] v2010.12-rc2 released
On Thu, 2010-12-02 at 20:40 -0800, Prafulla Wadaskar wrote: > > > -Original Message- > > From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] > > On Behalf Of Carlo Caione > > Sent: Friday, December 03, 2010 3:11 AM > > To: U-Boot@lists.denx.de > > Subject: Re: [U-Boot] [STATUS] v2010.12-rc2 released > > > > > Some of the times, the boot hung after printing DRAM: 128 MiB, > > > but never did it hang without printing anything. > > > > The same here. > > Beagleboard xM rev.A hangs after DRAM: 256 MiB > > For fix this, needs to change global variables in timer.c > REF: http://lists.denx.de/pipermail/u-boot/2010-December/082834.html Applied but nothing is changed: Texas Instruments X-Loader 1.4.4ss (Dec 2 2010 - 21:40:58) Beagle xM Rev A Reading boot sector Loading u-boot.bin from mmc U-Boot 2010.12-rc2-00029-g49733aa-dirty (Dec 03 2010 - 22:05:44) OMAP3630/3730-GP ES1.0, CPU-OPP2, L3-165MHz, Max CPU Clock 1 Ghz OMAP3 Beagle board + LPDDR/NAND I2C: ready DRAM: 512 MiB Regards, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] v2010.12-rc2 released
> Some of the times, the boot hung after printing DRAM: 128 MiB, > but never did it hang without printing anything. The same here. Beagleboard xM rev.A hangs after DRAM: 256 MiB Regards, -- Carlo Caione ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
