[U-Boot] fs/fat: align disk buffers on cache line to enable DMA and cache

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 fs/fat/fat.c |   11 ++-
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 1f95eb4..c924ec0 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * Convert a string to lowercase.
@@ -62,7 +63,7 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf)
 
 int fat_register_device (block_dev_desc_t * dev_desc, int part_no)
 {
-   unsigned char buffer[dev_desc->blksz];
+   ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 
/* First close any currently found FAT filesystem */
cur_dev = NULL;
@@ -293,7 +294,7 @@ get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer,
return -1;
}
if (size % mydata->sect_size) {
-   __u8 tmpbuf[mydata->sect_size];
+   ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
 
idx = size / mydata->sect_size;
ret = disk_read(startsect + idx, 1, tmpbuf);
@@ -428,7 +429,7 @@ static int slot2str (dir_slot *slotptr, char *l_name, int 
*idx)
  * into 'retdent'
  * Return 0 on success, -1 otherwise.
  */
-__attribute__ ((__aligned__ (__alignof__ (dir_entry
+__attribute__ ((__aligned__ (ARCH_DMA_MINALIGN)))
 __u8 get_vfatname_block[MAX_CLUSTSIZE];
 
 static int
@@ -709,7 +710,7 @@ read_bootsectandvi (boot_sector *bs, volume_info *volinfo, 
int *fatsize)
return -1;
}
 
-   block = malloc(cur_dev->blksz);
+   block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);
if (block == NULL) {
debug("Error: allocating block\n");
return -1;
@@ -828,7 +829,7 @@ do_fat_read (const char *filename, void *buffer, unsigned 
long maxsize,
}
 
mydata->fatbufnum = -1;
-   mydata->fatbuf = malloc(FATBUFSIZE);
+   mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
return -1;
-- 
1.7.9

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[U-Boot] fs/fat alignment

[Eric Nelson]

Note that checkpatch fails on this patch with the following warning,
but I'm not sure how to resolve it.

Nothing else in the U-Boot code base seems to use __align() although
it's defined in include/linux/compiler-gcc.h.

#46: FILE: fs/fat/fat.c:432:
+__attribute__ ((__aligned__ (ARCH_DMA_MINALIGN)))

WARNING: __aligned(size) is preferred over __attribute__((aligned(size)))
#46: FILE: fs/fat/fat.c:432:
+__attribute__ ((__aligned__ (ARCH_DMA_MINALIGN)))

total: 0 errors, 2 warnings, 47 lines checked
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[U-Boot] [PATCH 1/2] part_dos: align disk buffers on cache line to enable DMA and cache

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 disk/part_dos.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/disk/part_dos.c b/disk/part_dos.c
index b5bcb37..c028aaf 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -87,7 +87,7 @@ static int test_block_type(unsigned char *buffer)
 
 int test_part_dos (block_dev_desc_t *dev_desc)
 {
-   unsigned char buffer[dev_desc->blksz];
+   ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 
if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) 
||
(buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
@@ -102,7 +102,7 @@ int test_part_dos (block_dev_desc_t *dev_desc)
 static void print_partition_extended (block_dev_desc_t *dev_desc, int 
ext_part_sector, int relative,
   int part_num)
 {
-   unsigned char buffer[dev_desc->blksz];
+   ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
int i;
 
@@ -166,7 +166,7 @@ static int get_partition_info_extended (block_dev_desc_t 
*dev_desc, int ext_part
 int relative, int part_num,
 int which_part, disk_partition_t *info)
 {
-   unsigned char buffer[dev_desc->blksz];
+   ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
int i;
 
-- 
1.7.9

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Re: [U-Boot] [PATCH] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

On 03/03/2012 12:35 PM, Wolfgang Grandegger wrote:

On 03/03/2012 05:09 PM, Eric Nelson wrote:

On 03/03/2012 02:00 AM, Stefano Babic wrote:

On 03/03/2012 01:46, Eric Nelson wrote:

This patch requires Stefano's driver for MX5/MX6.
 http://lists.denx.de/pipermail/u-boot/2012-February/118530.html


This is helpful, but should be not part of the commit message that is
stored in git. Move all additional info after the "---" line.



Signed-off-by: Eric Nelson
---
   arch/arm/include/asm/arch-mx6/imx-regs.h  |   11 +
   board/freescale/mx6qsabrelite/mx6qsabrelite.c |   54
+
   include/configs/mx6qsabrelite.h   |   13 ++
   3 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3e5c4c2..2441434 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -165,6 +165,17 @@
   #define IP2APB_USBPHY1_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x78000)
   #define IP2APB_USBPHY2_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x7C000)

+/*
+ * ANATOP register definitions
+ */
+#define ANATOP_PLL_LOCK 0x8000
+#define ANATOP_PLL_ENABLE_MASK  0x2000
+#define ANATOP_PLL_BYPASS_MASK  0x0001
+#define ANATOP_PLL_LOCK 0x8000
+#define ANATOP_PLL_PWDN_MASK0x1000
+#define ANATOP_PLL_HOLD_RING_OFF_MASK   0x0800
+#define ANATOP_SATA_CLK_ENABLE_MASK 0x0010


There is already a thread initiated by Wolfgang regarding the ANATOP
registers:

http://lists.denx.de/pipermail/u-boot/2012-February/117942.html

I think we need in any case a way to consolitate this stuff, even if
decided to postpone this activity



Thanks. I saw that but seem to have forgotten it.


Most, if not all, definitions above are already defined in
arch/arm/include/asm/arch-mx6/ccm_regs.h including a struct member.
Therefore there's also no need for magic offsets.

Wolfgang.


Thanks Wolfgang.

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Re: [U-Boot] Have there been any toughs of adding exFAT file system support?

[Eric Nelson]

On 03/03/2012 11:41 AM, Andreas Bäck wrote:

More and more people are starting to use exFat on their usb sticks
especially now when windows starts to be the majority of instalations


This looks to be patented.

http://www.google.com/patents?id=TXDHEBAJ&printsec=frontcover&dq=US2009164440&hl=en&sa=X&ei=S2lST5KEGazSiAK13aS0Bg&ved=0CDIQ6AEwAA
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Re: [U-Boot] [PATCH] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

On 03/03/2012 02:00 AM, Stefano Babic wrote:

On 03/03/2012 01:46, Eric Nelson wrote:

This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.html


This is helpful, but should be not part of the commit message that is
stored in git. Move all additional info after the "---" line.



Signed-off-by: Eric Nelson
---
  arch/arm/include/asm/arch-mx6/imx-regs.h  |   11 +
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   54 +
  include/configs/mx6qsabrelite.h   |   13 ++
  3 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3e5c4c2..2441434 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -165,6 +165,17 @@
  #define IP2APB_USBPHY1_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x78000)
  #define IP2APB_USBPHY2_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x7C000)

+/*
+ * ANATOP register definitions
+ */
+#define ANATOP_PLL_LOCK 0x8000
+#define ANATOP_PLL_ENABLE_MASK  0x2000
+#define ANATOP_PLL_BYPASS_MASK  0x0001
+#define ANATOP_PLL_LOCK 0x8000
+#define ANATOP_PLL_PWDN_MASK0x1000
+#define ANATOP_PLL_HOLD_RING_OFF_MASK   0x0800
+#define ANATOP_SATA_CLK_ENABLE_MASK 0x0010


There is already a thread initiated by Wolfgang regarding the ANATOP
registers:

http://lists.denx.de/pipermail/u-boot/2012-February/117942.html

I think we need in any case a way to consolitate this stuff, even if
decided to postpone this activity



Thanks. I saw that but seem to have forgotten it.


+
  #define CHIP_REV_1_0 0x10
  #define IRAM_SIZE0x0004
  #define IMX_IIM_BASE OCOTP_BASE_ADDR
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 2786482..e0ba6a4 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -273,10 +273,64 @@ int board_eth_init(bd_t *bis)
return 0;
  }

+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+   u32 reg = 0;
+   s32 timeout = 10;
+
+   /* Enable sata clock */
+   reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
+   reg |= 0x30;
+   writel(reg, CCM_BASE_ADDR + 0x7c);


We have not the Reference Manual, and using hexadecimal values makes
things ready for the Obfuscated C Code Contest:

http://www.ioccc.org/



I'll try to obfuscate more in a V2. We can win this thing! ;)


Do not use offsets. Instead of that, provide structures to access the
internal register. This must be fixed globally.



+
+   /* Enable PLLs */
+   reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
+   reg&= ~ANATOP_PLL_PWDN_MASK;
+   writel(reg, ANATOP_BASE_ADDR + 0xe0);
+   reg |= ANATOP_PLL_ENABLE_MASK;
+   while (timeout--) {
+   if (readl(ANATOP_BASE_ADDR + 0xe0)&  ANATOP_PLL_LOCK)
+   break;
+   }


Ditto



+   if (timeout<= 0)
+   return -1;
+   reg&= ~ANATOP_PLL_BYPASS_MASK;
+   writel(reg, ANATOP_BASE_ADDR + 0xe0);
+   reg |= ANATOP_SATA_CLK_ENABLE_MASK;
+   writel(reg, ANATOP_BASE_ADDR + 0xe0);
+
+   /* Enable sata phy */
+   reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */


We have functions to manage pinmux, use them




Right.


  int board_early_init_f(void)
  {
 setup_iomux_uart();

+#ifdef CONFIG_CMD_SATA
+   setup_sata();


Why do we need in early ? Is it really needed before relocation ?



Nope. Not needed in early.


Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] i.MX6: mx6qsabrelite: Add keypress support

[Eric Nelson]

On 03/03/2012 08:48 AM, Wolfgang Denk wrote:

Dear Eric Nelson,

In message<4f52390c.4080...@boundarydevices.com>  you wrote:



Why not make it an STDIN device as any other keyboard?


Is there a non-blocking read from stdin available to boot script?

How would we represent keys like "Menu", "Home", "Volume up" and "Volume down"?

Through ANSI escape sequences?


No.  You don't have to.  Mapping key presses to functions (bind them to
commands) is a different thing.  Keys could be "1", "2", "3" and "4",
and could be mapped to "run cmd_1", ... "run cmd_4" respectively.
Then the user can define what "cmd_1" etc. does.



That's perfect. All that's left is the details...

Thanks for your help.
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Re: [U-Boot] [PATCH] i.MX6: mx6qsabrelite: Add keypress support

[Eric Nelson]

On 03/03/2012 02:15 AM, Wolfgang Denk wrote:

Dear Eric Nelson,

In message<1330732824-15345-1-git-send-email-eric.nel...@boundarydevices.com>  
you wrote:

This patch adds support for the GPIO keyboard used on MX6Q SabreLite.

This is generally used for invoking Android "recovery mode" in
response to a long press of volume key down during boot.

This can be tested by a boot script like so:
 if keypress voldown&&  sleep 1&&  keypress voldown ; then
   echo "do recovery thing" ;
 fi

Key values can be seen by issuing keypress with no arguments:


I don't like introducing yet another way to handle key presses and
create menu like interfaces from this.

We already have two of these:

- We have the powerful and flexible method to map key preesses to
   envrionment variables which can in turn hold commands (variables
   "magic_keys" and "key_magic*") as used for example on the enbw_cmc,
   lwmon5, hmi1001, mucmc52, pcs440ep, r360mpi and mucmc52 boards.

- We have the menu system as implemented by common/menu.c etc.

Please use either of these, but don't invent a new one.  Thanks.



Thanks for the pointers. I'll rework accordingly.

Grepping the sources rarely results in this kind of insight.

Regards,


Eric
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Re: [U-Boot] [PATCH] i.MX6: mx6qsabrelite: Add keypress support

[Eric Nelson]

On 03/02/2012 07:18 PM, Marek Vasut wrote:

This patch adds support for the GPIO keyboard used on MX6Q SabreLite.

This is generally used for invoking Android "recovery mode" in
response to a long press of volume key down during boot.

This can be tested by a boot script like so:
 if keypress voldown&&  sleep 1&&  keypress voldown ; then
   echo "do recovery thing" ;
 fi

Key values can be seen by issuing keypress with no arguments:

MX6QSABRELITE U-Boot>  keypress
keys: !menu !back   !search !home   !volup  !voldown
---
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   76
+ 1 files changed, 76 insertions(+), 0
deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index e0ba6a4..0d45615
100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |   \
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
+   PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
  int dram_init(void)
  {
 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -122,6 +126,15 @@ iomux_v3_cfg_t enet_pads2[] = {
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  };

+static iomux_v3_cfg_t const button_pads[] = {
+   MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14

-

Menu Button */ +MX6Q_PAD_NANDF_D2__GPIO_2_2 |
MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 - Back Button */
+   MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14

-

Search Button */ +  MX6Q_PAD_NANDF_D4__GPIO_2_4 |
MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 - Home Button */
+   MX6Q_PAD_GPIO_19__GPIO_4_5  | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14

-

Volume Down */ +MX6Q_PAD_GPIO_18__GPIO_7_13 |
MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 - Volume Up */ +};
+
  static void setup_iomux_enet(void)
  {
gpio_direction_output(87, 0);  /* GPIO 3-23 */
@@ -323,10 +336,18 @@ int setup_sata(void)
  }
  #endif

+static void setup_buttons(void)
+{
+   imx_iomux_v3_setup_multiple_pads(button_pads,
+ARRAY_SIZE(button_pads));
+}
+
  int board_early_init_f(void)
  {
 setup_iomux_uart();

+   setup_buttons();
+
  #ifdef CONFIG_CMD_SATA
setup_sata();
  #endif
@@ -350,3 +371,58 @@ int checkboard(void)

 return 0;
  }
+
+struct button_key {
+   char const  *name;
+   unsignedgpnum;
+};
+
+static struct button_key const buttons[] = {
+   {"menu",  GPIO_NUMBER(2, 1)},
+   {"back",  GPIO_NUMBER(2, 2)},
+   {"search",GPIO_NUMBER(2, 3)},
+   {"home",  GPIO_NUMBER(2, 4)},
+   {"voldown",   GPIO_NUMBER(4, 5)},
+   {"volup", GPIO_NUMBER(7, 13)},
+};
+
+static int keypress(cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[]) +{
+   if (1<  argc) {
+   int arg;
+   int pressed = 1 ;
+   for (arg=1; arg
gpio_get_value(buttons[i].gpnum));

+   break;
+   }
+   }
+   if (ARRAY_SIZE(buttons) == i) {
+   printf ("unrecognized key %s\n", keyname);
+   pressed = 0;
+   break;
+   }
+   }
+   return (0 == pressed);
+   } else {
+   int i;
+   printf ("keys: ");
+   for (i=0; i

Why not make it an STDIN device as any other keyboard?


Is there a non-blocking read from stdin available to boot script?

How would we represent keys like "Menu", "Home", "Volume up" and "Volume down"?

Through ANSI escape sequences?

Please advise,


Eric
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[U-Boot] [PATCH] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.html

Signed-off-by: Eric Nelson 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h  |   11 +
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   54 +
 include/configs/mx6qsabrelite.h   |   13 ++
 3 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3e5c4c2..2441434 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -165,6 +165,17 @@
 #define IP2APB_USBPHY1_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x7C000)
 
+/*
+ * ANATOP register definitions
+ */
+#define ANATOP_PLL_LOCK 0x8000
+#define ANATOP_PLL_ENABLE_MASK  0x2000
+#define ANATOP_PLL_BYPASS_MASK  0x0001
+#define ANATOP_PLL_LOCK 0x8000
+#define ANATOP_PLL_PWDN_MASK0x1000
+#define ANATOP_PLL_HOLD_RING_OFF_MASK   0x0800
+#define ANATOP_SATA_CLK_ENABLE_MASK 0x0010
+
 #define CHIP_REV_1_0 0x10
 #define IRAM_SIZE0x0004
 #define IMX_IIM_BASE OCOTP_BASE_ADDR
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 2786482..e0ba6a4 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -273,10 +273,64 @@ int board_eth_init(bd_t *bis)
return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+   u32 reg = 0;
+   s32 timeout = 10;
+
+   /* Enable sata clock */
+   reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
+   reg |= 0x30;
+   writel(reg, CCM_BASE_ADDR + 0x7c);
+
+   /* Enable PLLs */
+   reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
+   reg &= ~ANATOP_PLL_PWDN_MASK;
+   writel(reg, ANATOP_BASE_ADDR + 0xe0);
+   reg |= ANATOP_PLL_ENABLE_MASK;
+   while (timeout--) {
+   if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)
+   break;
+   }
+   if (timeout <= 0)
+   return -1;
+   reg &= ~ANATOP_PLL_BYPASS_MASK;
+   writel(reg, ANATOP_BASE_ADDR + 0xe0);
+   reg |= ANATOP_SATA_CLK_ENABLE_MASK;
+   writel(reg, ANATOP_BASE_ADDR + 0xe0);
+
+   /* Enable sata phy */
+   reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */
+
+   reg &= ~0x07ff;
+   /*
+* rx_eq_val_0 = 5 [26:24] == 3.0 dB
+* los_lvl = 0x12 [23:19] == SATA2m
+* rx_dpll_mode_0 = 0x3 [18:16]
+* speed = 1 [15] == 3Gpbs
+* mpll_ss_en = 0x0 [14]
+* tx_atten_0 = 0x4 [13:11]
+* tx_boost_0 = 0x0 [10:7]
+* tx_lvl = 0x11 [6:2]  == 1.104 V
+* tx_edgerate_0 == 0x0 [0:1]
+* */
+   reg |= 0x0593a046;
+   writel(reg, IOMUXC_BASE_ADDR + 0x34);
+
+   return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
setup_iomux_uart();
 
+#ifdef CONFIG_CMD_SATA
+   setup_sata();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index a5dae73..01c6887 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -69,6 +69,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID  0
+#define CONFIG_DWC_AHSATA_BASE_ADDRSATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-- 
1.7.9

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Re: [U-Boot] [PATCH] i.MX6: mx6qsabrelite: Add keypress support

[Eric Nelson]

On 03/02/2012 05:00 PM, Eric Nelson wrote:

This patch adds support for the GPIO keyboard used on MX6Q SabreLite.

This is generally used for invoking Android "recovery mode" in
response to a long press of volume key down during boot.

This can be tested by a boot script like so:
 if keypress voldown&&  sleep 1&&  keypress voldown ; then
   echo "do recovery thing" ;
 fi

Key values can be seen by issuing keypress with no arguments:

MX6QSABRELITE U-Boot>  keypress
keys: !menu !back   !search !home   !volup  !voldown
---
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   76 +
  1 files changed, 76 insertions(+), 0 deletions(-)


> 

I didn't want to litter the commit message with a lot of extraneous
discussion, but it appears that Android recovery mode can be invoked
either by Android itself or by a user pressing keys.

When Android wants to invoke recovery mode, it creates a special
"recovery" file and then re-boots.

The Freescale U-Boot release accomplishes this by having special
code to detect the keypress or the presence of the magic file.

http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=blob;f=board/freescale/common/recovery.c;h=16e0be479ba543a8ceb865c3c2eee55379186bda;hb=imx_v2009.08_11.11.01

http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=blob;f=board/freescale/mx53_loco/mx53_loco.c;h=fda52dc4abff6482d6cb102002529a3f2edd3bbb;hb=imx_v2009.08_11.11.01#l733

Since U-Boot can test files using the hush parser, it seems cleaner to just
enable keyboard detection and allow express the boot flow in boot commands.

I looked for, but didn't find precedent for testing keys.

Please advise if there's a more standard way to accomplish keypress
detection.

Regards,


Eric
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[U-Boot] [PATCH] i.MX6: mx6qsabrelite: Add keypress support

[Eric Nelson]

This patch adds support for the GPIO keyboard used on MX6Q SabreLite.

This is generally used for invoking Android "recovery mode" in
response to a long press of volume key down during boot.

This can be tested by a boot script like so:
if keypress voldown && sleep 1 && keypress voldown ; then
  echo "do recovery thing" ;
fi

Key values can be seen by issuing keypress with no arguments:

MX6QSABRELITE U-Boot > keypress
keys: !menu !back   !search !home   !volup  !voldown
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   76 +
 1 files changed, 76 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index e0ba6a4..0d45615 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |   \
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
+   PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -122,6 +126,15 @@ iomux_v3_cfg_t enet_pads2[] = {
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const button_pads[] = {
+   MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 
- Menu Button */
+   MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 
- Back Button */
+   MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 
- Search Button */
+   MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 
- Home Button */
+   MX6Q_PAD_GPIO_19__GPIO_4_5  | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 
- Volume Down */
+   MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* J14 
- Volume Up */
+};
+
 static void setup_iomux_enet(void)
 {
gpio_direction_output(87, 0);  /* GPIO 3-23 */
@@ -323,10 +336,18 @@ int setup_sata(void)
 }
 #endif
 
+static void setup_buttons(void)
+{
+   imx_iomux_v3_setup_multiple_pads(button_pads,
+ARRAY_SIZE(button_pads));
+}
+
 int board_early_init_f(void)
 {
setup_iomux_uart();
 
+   setup_buttons();
+
 #ifdef CONFIG_CMD_SATA
setup_sata();
 #endif
@@ -350,3 +371,58 @@ int checkboard(void)
 
return 0;
 }
+
+struct button_key {
+   char const  *name;
+   unsignedgpnum;
+};
+
+static struct button_key const buttons[] = {
+   {"menu",GPIO_NUMBER(2, 1)},
+   {"back",GPIO_NUMBER(2, 2)},
+   {"search",  GPIO_NUMBER(2, 3)},
+   {"home",GPIO_NUMBER(2, 4)},
+   {"voldown", GPIO_NUMBER(4, 5)},
+   {"volup",   GPIO_NUMBER(7, 13)},
+};
+
+static int keypress(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   if (1 < argc) {
+   int arg;
+   int pressed = 1 ;
+   for (arg=1; arghttp://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 2/4] net: fec_mxc: allow use with cache enabled

[Eric Nelson]

On 03/02/2012 04:40 PM, Marek Vasut wrote:

Whoops.

Forgot to add the origin of this patch to the commit message:
http://lists.denx.de/pipermail/u-boot/2012-February/117695.html

Thanks Marek.


Eric, I hope you won't mind if we respin this patch a few times to make sure
nothing gets broken by this.

M



Not at all. I just wanted to get it out there along with the dcache
patch so we have something to test each of the drivers against.



On 03/02/2012 04:06 PM, Eric Nelson wrote:

ensure that transmit and receive buffers are cache-line aligned

  invalidate cache after each packet received
  flush cache before transmitting

Signed-off-by: Eric Nelson
---

   drivers/net/fec_mxc.c |  248
   -
   drivers/net/fec_mxc.h |   19 +
   2 files changed, 184 insertions(+), 83 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1fdd071..f72304b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -50,6 +50,33 @@ DECLARE_GLOBAL_DATA_PTR;

   #define  CONFIG_FEC_MXC_SWAP_PACKET
   #endif

+#ifndefCONFIG_FEC_DESC_ALIGNMENT
+#defineCONFIG_FEC_DESC_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+#ifndefCONFIG_FEC_DATA_ALIGNMENT
+#defineCONFIG_FEC_DATA_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+/* Check various alignment issues at compile time */
+#if ((CONFIG_FEC_DESC_ALIGNMENT<   16) || (CONFIG_FEC_DESC_ALIGNMENT % 16
!= 0)) +#error  "CONFIG_FEC_DESC_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((CONFIG_FEC_DATA_ALIGNMENT<   16) || (CONFIG_FEC_DATA_ALIGNMENT % 16
!= 0)) +#error  "CONFIG_FEC_DATA_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((PKTALIGN<   CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
+#if ((PKTSIZE_ALIGN<   CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTSIZE_ALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTSIZE_ALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+

   #undef DEBUG

   struct nbuf {

@@ -259,43 +286,47 @@ static int fec_tx_task_disable(struct fec_priv
*fec)

* Initialize receive task's buffer descriptors
* @param[in] fec all we know about the device yet
* @param[in] count receive buffer count to be allocated

- * @param[in] size size of each receive buffer
+ * @param[in] dsize desired size of each receive buffer

* @return 0 on success
*
* For this task we need additional memory for the data buffers. And
each * data buffer requires some alignment. Thy must be aligned to a
specific

- * boundary each (DB_DATA_ALIGNMENT).
+ * boundary each.

*/

-static int fec_rbd_init(struct fec_priv *fec, int count, int size)
+static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)

   {

-   int ix;
-   uint32_t p = 0;
-
-   /* reserve data memory and consider alignment */
-   if (fec->rdb_ptr == NULL)
-   fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
-   p = (uint32_t)fec->rdb_ptr;
-   if (!p) {
-   puts("fec_mxc: not enough malloc memory\n");
-   return -ENOMEM;
-   }
-   memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
-   p += DB_DATA_ALIGNMENT-1;
-   p&= ~(DB_DATA_ALIGNMENT-1);
-
-   for (ix = 0; ix<   count; ix++) {
-   writel(p,&fec->rbd_base[ix].data_pointer);
-   p += size;
-   writew(FEC_RBD_EMPTY,&fec->rbd_base[ix].status);
-   writew(0,&fec->rbd_base[ix].data_length);
-   }
+   uint32_t size;
+   int i;
+

/*

-* mark the last RBD to close the ring
+* Allocate memory for the buffers. This allocation respects the
+* alignment

 */

-   writew(FEC_RBD_WRAP | FEC_RBD_EMPTY,&fec->rbd_base[ix - 1].status);
+   size = roundup(dsize, CONFIG_FEC_DATA_ALIGNMENT);
+   for (i = 0; i<   count; i++) {
+   if (0 == fec->rbd_base[i].data_pointer) {
+   uint8_t *data = memalign(CONFIG_FEC_DATA_ALIGNMENT,

size);

+   if (!data) {
+   printf("%s: error allocating rxbuf %d\n",

__func__, i);

+   goto err;
+   }
+   fec->rbd_base[i].data_pointer = (uint32_t)data;
+   } // needs allocation
+   fec->rbd_base[i].status = FEC_RBD_EMPTY;
+   fec->rbd_base[i].data_length = 0;
+   }
+
+   /* Mark the last RBD to close the ring. */
+   fec->rbd_base[i - 1].status = FEC_RBD_EMPTY | FEC_RBD_WRAP;

fec->rbd_index = 0;

return 0;

+
+err:
+   for (; i>= 0; i--)
+   free((uint8_t *)fec->

Re: [U-Boot] [PATCH 2/4] net: fec_mxc: allow use with cache enabled

[Eric Nelson]

On 03/02/2012 04:06 PM, Eric Nelson wrote:

ensure that transmit and receive buffers are cache-line aligned
 invalidate cache after each packet received
 flush cache before transmitting

Signed-off-by: Eric Nelson
---
  drivers/net/fec_mxc.c |  248 -
  drivers/net/fec_mxc.h |   19 +
  2 files changed, 184 insertions(+), 83 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1fdd071..f72304b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -50,6 +50,33 @@ DECLARE_GLOBAL_DATA_PTR;
  #define   CONFIG_FEC_MXC_SWAP_PACKET
  #endif

+#ifndefCONFIG_FEC_DESC_ALIGNMENT
+#defineCONFIG_FEC_DESC_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+#ifndefCONFIG_FEC_DATA_ALIGNMENT
+#defineCONFIG_FEC_DATA_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+/* Check various alignment issues at compile time */
+#if ((CONFIG_FEC_DESC_ALIGNMENT<  16) || (CONFIG_FEC_DESC_ALIGNMENT % 16 != 0))
+#error "CONFIG_FEC_DESC_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((CONFIG_FEC_DATA_ALIGNMENT<  16) || (CONFIG_FEC_DATA_ALIGNMENT % 16 != 0))
+#error "CONFIG_FEC_DATA_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((PKTALIGN<  CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
+#if ((PKTSIZE_ALIGN<  CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTSIZE_ALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTSIZE_ALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
  #undef DEBUG

  struct nbuf {
@@ -259,43 +286,47 @@ static int fec_tx_task_disable(struct fec_priv *fec)
   * Initialize receive task's buffer descriptors
   * @param[in] fec all we know about the device yet
   * @param[in] count receive buffer count to be allocated
- * @param[in] size size of each receive buffer
+ * @param[in] dsize desired size of each receive buffer
   * @return 0 on success
   *
   * For this task we need additional memory for the data buffers. And each
   * data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each (DB_DATA_ALIGNMENT).
+ * boundary each.
   */
-static int fec_rbd_init(struct fec_priv *fec, int count, int size)
+static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
  {
-   int ix;
-   uint32_t p = 0;
-
-   /* reserve data memory and consider alignment */
-   if (fec->rdb_ptr == NULL)
-   fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
-   p = (uint32_t)fec->rdb_ptr;
-   if (!p) {
-   puts("fec_mxc: not enough malloc memory\n");
-   return -ENOMEM;
-   }
-   memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
-   p += DB_DATA_ALIGNMENT-1;
-   p&= ~(DB_DATA_ALIGNMENT-1);
-
-   for (ix = 0; ix<  count; ix++) {
-   writel(p,&fec->rbd_base[ix].data_pointer);
-   p += size;
-   writew(FEC_RBD_EMPTY,&fec->rbd_base[ix].status);
-   writew(0,&fec->rbd_base[ix].data_length);
-   }
+   uint32_t size;
+   int i;
+
/*
-* mark the last RBD to close the ring
+* Allocate memory for the buffers. This allocation respects the
+* alignment
 */
-   writew(FEC_RBD_WRAP | FEC_RBD_EMPTY,&fec->rbd_base[ix - 1].status);
+   size = roundup(dsize, CONFIG_FEC_DATA_ALIGNMENT);
+   for (i = 0; i<  count; i++) {
+   if (0 == fec->rbd_base[i].data_pointer) {
+   uint8_t *data = memalign(CONFIG_FEC_DATA_ALIGNMENT, 
size);
+   if (!data) {
+   printf("%s: error allocating rxbuf %d\n", 
__func__, i);
+   goto err;
+   }
+   fec->rbd_base[i].data_pointer = (uint32_t)data;
+   } // needs allocation
+   fec->rbd_base[i].status = FEC_RBD_EMPTY;
+   fec->rbd_base[i].data_length = 0;
+   }
+
+   /* Mark the last RBD to close the ring. */
+   fec->rbd_base[i - 1].status = FEC_RBD_EMPTY | FEC_RBD_WRAP;
fec->rbd_index = 0;

return 0;
+
+err:
+   for (; i>= 0; i--)
+   free((uint8_t *)fec->rbd_base[i].data_pointer);
+
+   return -ENOMEM;
  }

  /**
@@ -312,8 +343,8 @@ static int fec_rbd_init(struct fec_priv *fec, int count, 
int size)
   */
  static void fec_tbd_init(struct fec_priv *fec)
  {
-   writew(0x,&fec->tbd_base[0].status);
-   writew(FEC_TBD_WRAP,&fec->tbd_base[1].status);
+   fec->tbd_base[0].status = 0;
+   fec->tbd_base[1].status = FEC_TBD_WRAP;


Troy just pointed out that these changes aren't necessary or helpful.
I'll address 

Re: [U-Boot] i.MX6: mx6qsabrelite: allow use with Freescale 2.6.38 kernels

[Eric Nelson]

On 03/02/2012 04:25 PM, Wolfgang Denk wrote:

Dear Eric Nelson,

In message<1330728909-12203-1-git-send-email-eric.nel...@boundarydevices.com>  
you wrote:

This series of patches is needed to allow main-line U-Boot to be used
with Freescale's Linux 2.6.38 non-DT kernel releases.

These releases currently require at least the machine type and
revision atag entries and are configured to load boot scripts from
the ext3 filesystem.


Is this really needed?  I feel we should rather focus on current
mainline kernel code and support that well instead of adding backward
compatibility complexity for old, obsolete code.



I think new code is still being written for 2.6.38, so it may be obsolete,
but not necessarily old.


People who want to run FSL kernels should be able run FSL's version
of U-Boot.



They certainly can.

These small patches will be a big help to those of us who need to
support both though, and it's not yet clear how long the kernel
transition will take.


Best regards,

Wolfgang Denk


Regards,


Eric
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Re: [U-Boot] [PATCH 0/4] Add preliminary cache support to i.MX6

[Eric Nelson]

On 03/02/2012 04:06 PM, Eric Nelson wrote:

This series of patches defines the prerequisites for cache support on i.MX6
to allow further driver development to occur.

It does not enable the use of the data cache by default. To enable
data cache, comment out this line in mx6qsabrelite.h or mx6qarm2.h:

#define CONFIG_SYS_DCACHE_OFF



I meant to add a note to this commit message indicating the
drivers which are known to need work before cache is enabled:

- mmc
- usb host
- sata

Each of these is functional after issuing 'dcache off', but non-functional
with dcache enabled.
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Re: [U-Boot] [PATCH 2/4] net: fec_mxc: allow use with cache enabled

[Eric Nelson]

Whoops.

Forgot to add the origin of this patch to the commit message:
http://lists.denx.de/pipermail/u-boot/2012-February/117695.html

Thanks Marek.

On 03/02/2012 04:06 PM, Eric Nelson wrote:

ensure that transmit and receive buffers are cache-line aligned
 invalidate cache after each packet received
 flush cache before transmitting

Signed-off-by: Eric Nelson
---
  drivers/net/fec_mxc.c |  248 -
  drivers/net/fec_mxc.h |   19 +
  2 files changed, 184 insertions(+), 83 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1fdd071..f72304b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -50,6 +50,33 @@ DECLARE_GLOBAL_DATA_PTR;
  #define   CONFIG_FEC_MXC_SWAP_PACKET
  #endif

+#ifndefCONFIG_FEC_DESC_ALIGNMENT
+#defineCONFIG_FEC_DESC_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+#ifndefCONFIG_FEC_DATA_ALIGNMENT
+#defineCONFIG_FEC_DATA_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+/* Check various alignment issues at compile time */
+#if ((CONFIG_FEC_DESC_ALIGNMENT<  16) || (CONFIG_FEC_DESC_ALIGNMENT % 16 != 0))
+#error "CONFIG_FEC_DESC_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((CONFIG_FEC_DATA_ALIGNMENT<  16) || (CONFIG_FEC_DATA_ALIGNMENT % 16 != 0))
+#error "CONFIG_FEC_DATA_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((PKTALIGN<  CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
+#if ((PKTSIZE_ALIGN<  CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTSIZE_ALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTSIZE_ALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
  #undef DEBUG

  struct nbuf {
@@ -259,43 +286,47 @@ static int fec_tx_task_disable(struct fec_priv *fec)
   * Initialize receive task's buffer descriptors
   * @param[in] fec all we know about the device yet
   * @param[in] count receive buffer count to be allocated
- * @param[in] size size of each receive buffer
+ * @param[in] dsize desired size of each receive buffer
   * @return 0 on success
   *
   * For this task we need additional memory for the data buffers. And each
   * data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each (DB_DATA_ALIGNMENT).
+ * boundary each.
   */
-static int fec_rbd_init(struct fec_priv *fec, int count, int size)
+static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
  {
-   int ix;
-   uint32_t p = 0;
-
-   /* reserve data memory and consider alignment */
-   if (fec->rdb_ptr == NULL)
-   fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
-   p = (uint32_t)fec->rdb_ptr;
-   if (!p) {
-   puts("fec_mxc: not enough malloc memory\n");
-   return -ENOMEM;
-   }
-   memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
-   p += DB_DATA_ALIGNMENT-1;
-   p&= ~(DB_DATA_ALIGNMENT-1);
-
-   for (ix = 0; ix<  count; ix++) {
-   writel(p,&fec->rbd_base[ix].data_pointer);
-   p += size;
-   writew(FEC_RBD_EMPTY,&fec->rbd_base[ix].status);
-   writew(0,&fec->rbd_base[ix].data_length);
-   }
+   uint32_t size;
+   int i;
+
/*
-* mark the last RBD to close the ring
+* Allocate memory for the buffers. This allocation respects the
+* alignment
 */
-   writew(FEC_RBD_WRAP | FEC_RBD_EMPTY,&fec->rbd_base[ix - 1].status);
+   size = roundup(dsize, CONFIG_FEC_DATA_ALIGNMENT);
+   for (i = 0; i<  count; i++) {
+   if (0 == fec->rbd_base[i].data_pointer) {
+   uint8_t *data = memalign(CONFIG_FEC_DATA_ALIGNMENT, 
size);
+   if (!data) {
+   printf("%s: error allocating rxbuf %d\n", 
__func__, i);
+   goto err;
+   }
+   fec->rbd_base[i].data_pointer = (uint32_t)data;
+   } // needs allocation
+   fec->rbd_base[i].status = FEC_RBD_EMPTY;
+   fec->rbd_base[i].data_length = 0;
+   }
+
+   /* Mark the last RBD to close the ring. */
+   fec->rbd_base[i - 1].status = FEC_RBD_EMPTY | FEC_RBD_WRAP;
fec->rbd_index = 0;

return 0;
+
+err:
+   for (; i>= 0; i--)
+   free((uint8_t *)fec->rbd_base[i].data_pointer);
+
+   return -ENOMEM;
  }

  /**
@@ -312,8 +343,8 @@ static int fec_rbd_init(struct fec_priv *fec, int count, 
int size)
   */
  static void fec_tbd_init(struct fec_priv *fec)
  {
-   writew(0x,&fec->tbd_base[0].status);
-   writew(FEC_TBD_WRAP,&fec->tbd_base[1].status);
+   fec->tbd_b

[U-Boot] [PATCH 2/4] net: fec_mxc: allow use with cache enabled

[Eric Nelson]

ensure that transmit and receive buffers are cache-line aligned
invalidate cache after each packet received
flush cache before transmitting

Signed-off-by: Eric Nelson 
---
 drivers/net/fec_mxc.c |  248 -
 drivers/net/fec_mxc.h |   19 +
 2 files changed, 184 insertions(+), 83 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1fdd071..f72304b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -50,6 +50,33 @@ DECLARE_GLOBAL_DATA_PTR;
 #defineCONFIG_FEC_MXC_SWAP_PACKET
 #endif
 
+#ifndefCONFIG_FEC_DESC_ALIGNMENT
+#defineCONFIG_FEC_DESC_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+#ifndefCONFIG_FEC_DATA_ALIGNMENT
+#defineCONFIG_FEC_DATA_ALIGNMENT   ARCH_DMA_MINALIGN
+#endif
+
+/* Check various alignment issues at compile time */
+#if ((CONFIG_FEC_DESC_ALIGNMENT < 16) || (CONFIG_FEC_DESC_ALIGNMENT % 16 != 0))
+#error "CONFIG_FEC_DESC_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((CONFIG_FEC_DATA_ALIGNMENT < 16) || (CONFIG_FEC_DATA_ALIGNMENT % 16 != 0))
+#error "CONFIG_FEC_DATA_ALIGNMENT must be multiple of 16!"
+#endif
+
+#if ((PKTALIGN < CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
+#if ((PKTSIZE_ALIGN < CONFIG_FEC_DATA_ALIGNMENT) || \
+   (PKTSIZE_ALIGN % CONFIG_FEC_DATA_ALIGNMENT != 0))
+#error "PKTSIZE_ALIGN must be multiple of CONFIG_FEC_DATA_ALIGNMENT!"
+#endif
+
 #undef DEBUG
 
 struct nbuf {
@@ -259,43 +286,47 @@ static int fec_tx_task_disable(struct fec_priv *fec)
  * Initialize receive task's buffer descriptors
  * @param[in] fec all we know about the device yet
  * @param[in] count receive buffer count to be allocated
- * @param[in] size size of each receive buffer
+ * @param[in] dsize desired size of each receive buffer
  * @return 0 on success
  *
  * For this task we need additional memory for the data buffers. And each
  * data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each (DB_DATA_ALIGNMENT).
+ * boundary each.
  */
-static int fec_rbd_init(struct fec_priv *fec, int count, int size)
+static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
 {
-   int ix;
-   uint32_t p = 0;
-
-   /* reserve data memory and consider alignment */
-   if (fec->rdb_ptr == NULL)
-   fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
-   p = (uint32_t)fec->rdb_ptr;
-   if (!p) {
-   puts("fec_mxc: not enough malloc memory\n");
-   return -ENOMEM;
-   }
-   memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
-   p += DB_DATA_ALIGNMENT-1;
-   p &= ~(DB_DATA_ALIGNMENT-1);
-
-   for (ix = 0; ix < count; ix++) {
-   writel(p, &fec->rbd_base[ix].data_pointer);
-   p += size;
-   writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
-   writew(0, &fec->rbd_base[ix].data_length);
-   }
+   uint32_t size;
+   int i;
+
/*
-* mark the last RBD to close the ring
+* Allocate memory for the buffers. This allocation respects the
+* alignment
 */
-   writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
+   size = roundup(dsize, CONFIG_FEC_DATA_ALIGNMENT);
+   for (i = 0; i < count; i++) {
+   if (0 == fec->rbd_base[i].data_pointer) {
+   uint8_t *data = memalign(CONFIG_FEC_DATA_ALIGNMENT, 
size);
+   if (!data) {
+   printf("%s: error allocating rxbuf %d\n", 
__func__, i);
+   goto err;
+   }
+   fec->rbd_base[i].data_pointer = (uint32_t)data;
+   } // needs allocation
+   fec->rbd_base[i].status = FEC_RBD_EMPTY;
+   fec->rbd_base[i].data_length = 0;
+   }
+
+   /* Mark the last RBD to close the ring. */
+   fec->rbd_base[i - 1].status = FEC_RBD_EMPTY | FEC_RBD_WRAP;
fec->rbd_index = 0;
 
return 0;
+
+err:
+   for (; i >= 0; i--)
+   free((uint8_t *)fec->rbd_base[i].data_pointer);
+
+   return -ENOMEM;
 }
 
 /**
@@ -312,8 +343,8 @@ static int fec_rbd_init(struct fec_priv *fec, int count, 
int size)
  */
 static void fec_tbd_init(struct fec_priv *fec)
 {
-   writew(0x, &fec->tbd_base[0].status);
-   writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
+   fec->tbd_base[0].status = 0;
+   fec->tbd_base[1].status = FEC_TBD_WRAP;
fec->tbd_index = 0;
 }
 
@@ -387,12 +418,25 @@ static int fec_open(struct eth_device *edev)
 {
struct fec_priv *fec = (struct fec

[U-Boot] [PATCH 4/4] i.MX6: mx6qsabrelite: add cache commands if cache is enabled

[Eric Nelson]

---
 include/configs/mx6qsabrelite.h |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 3bd9bdb..a5dae73 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -212,4 +212,8 @@
 
 #define CONFIG_SYS_DCACHE_OFF
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.7.9

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[U-Boot] [PATCH 3/4] i.MX6: implement enable_caches()

[Eric Nelson]

disabled by default until drivers are fixed

Signed-off-by: Eric Nelson 
---
 arch/arm/cpu/armv7/mx6/soc.c|8 
 include/configs/mx6qarm2.h  |2 ++
 include/configs/mx6qsabrelite.h |2 ++
 3 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2ac74b5..eb418eb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -79,6 +79,14 @@ int arch_cpu_init(void)
 }
 #endif
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+   /* Enable D-cache. I-cache is already enabled in start.S */
+   dcache_enable();
+}
+#endif
+
 #if defined(CONFIG_FEC_MXC)
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 0962d3c..e83aec6 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -169,4 +169,6 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_DCACHE_OFF
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index a1a2267..3bd9bdb 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -210,4 +210,6 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_DCACHE_OFF
+
 #endif /* __CONFIG_H */
-- 
1.7.9

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[U-Boot] [PATCH 1/4] i.MX6: define CACHELINE_SIZE

[Eric Nelson]

---
 arch/arm/include/asm/arch-mx6/imx-regs.h |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 6a200bb..3e5c4c2 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -19,6 +19,8 @@
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
 #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE  32
+
 #define ROMCP_ARB_BASE_ADDR 0x
 #define ROMCP_ARB_END_ADDR  0x000F
 #define CAAM_ARB_BASE_ADDR  0x0010
-- 
1.7.9

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[U-Boot] [PATCH 0/4] Add preliminary cache support to i.MX6

[Eric Nelson]

This series of patches defines the prerequisites for cache support on i.MX6
to allow further driver development to occur.

It does not enable the use of the data cache by default. To enable
data cache, comment out this line in mx6qsabrelite.h or mx6qarm2.h:

#define CONFIG_SYS_DCACHE_OFF

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[U-Boot] [PATCH 3/3] i.MX6: mx6qsabrelite: add ext2 support

[Eric Nelson]

Current Ubuntu releases from Freescale contain a boot script in ext3 filesystem.

Signed-off-by: Eric Nelson 
---
 include/configs/mx6qsabrelite.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 53869a9..51ed791 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -66,6 +66,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-- 
1.7.9

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[U-Boot] [PATCH 2/3] i.MX6: mx6qsabrelite: add MACH_TYPE_MX6Q_SABRELITE

[Eric Nelson]

Allow non-dt kernels to boot

Signed-off-by: Troy Kisky 
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |6 --
 include/configs/mx6qsabrelite.h   |1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 590030b..2786482 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -282,8 +282,10 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-   /* address of boot parameters */
-   gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+   /* board id for linux */
+   gd->bd->bi_arch_number = MACH_TYPE_MX6Q_SABRELITE;
+   /* address of boot parameters */
+   gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
return 0;
 }
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 85f6f7a..53869a9 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -27,6 +27,7 @@
 #define CONFIG_SYS_MX6_CLK32   32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
+#define MACH_TYPE_MX6Q_SABRELITE   3769
 
 #include 
 
-- 
1.7.9

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[U-Boot] [PATCH 1/3] i.MX6: mx6qsabrelite: add CONFIG_REVISION_TAG

[Eric Nelson]

 Freescale 2.6.38 (Non-DT) kernels require the revision atag to
 enable the VPU.

Signed-off-by: Eric Nelson 
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |7 +++
 include/configs/mx6qsabrelite.h   |1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index db1bea9..590030b 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -215,6 +215,13 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+   return 0x63000 ;
+}
+#endif
+
 #ifdef CONFIG_MXC_SPI
 iomux_v3_cfg_t ecspi1_pads[] = {
/* SS1 */
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 93000f0..85f6f7a 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -33,6 +33,7 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-- 
1.7.9

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[U-Boot] i.MX6: mx6qsabrelite: allow use with Freescale 2.6.38 kernels

[Eric Nelson]

This series of patches is needed to allow main-line U-Boot to be used
with Freescale's Linux 2.6.38 non-DT kernel releases.

These releases currently require at least the machine type and
revision atag entries and are configured to load boot scripts from
the ext3 filesystem.

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Re: [U-Boot] ARM: Update mach-types

[Eric Nelson]

On 02/28/2012 02:28 AM, Fabio Estevam wrote:

On Tue, Feb 28, 2012 at 3:50 AM, Dirk Behme  wrote:


Just out of curiosity: Why do you need that?

It was my understanding that with recent U-Boot and Kernel on SabreLite
DeviceTree is the way to go? And this doesn't need the mach-types any more?


Maybe Troy wants to also allow U-boot to load a non-DT kernel, such as
the one provided by Freescale?



That's exactly right. With the addition of a couple of small things:

- machid
- revision tag (used by Freescale's kernel)

we can start shipping main-line U-Boot with Sabre Lite.

This seems like a worthwhile step, especially for those of us switching
between kernels.
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[U-Boot] [PATCH] mx6q: mx6qsabrelite: setup_spi() should be called in board_init to allow use for environment

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |8 
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index db1bea9..7fe2dc9 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -259,10 +259,6 @@ int board_eth_init(bd_t *bis)
if (ret)
printf("FEC MXC: %s:failed\n", __func__);
 
-#ifdef CONFIG_MXC_SPI
-   setup_spi();
-#endif
-
return 0;
 }
 
@@ -278,6 +274,10 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_MXC_SPI
+   setup_spi();
+#endif
+
return 0;
 }
 
-- 
1.7.9

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Re: [U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 02/02/2012 02:18 AM, Stefano Babic wrote:

On 01/02/2012 20:31, Eric Nelson wrote:


Hi Mike,

My comment was the inverse: I can't test just the 'sf probe' updates
unless I
have the core SPI flash support for mx6qsabrelite.

AFAIK, the update to cmd_sf doesn't have any dependencies and of course
the README update doesn't.


Then I think the best way is to proceed is as suggested by Mike - the
patches are orthogonal, and they can applied to different trees - and
merged together at the end by Wolfgang.

Stefano



Okay. I'll leave the process stuff in your capable hands.

Mine is just to code... (or so I like to think)
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Re: [U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 02/01/2012 10:00 AM, Mike Frysinger wrote:

On Wednesday 01 February 2012 06:30:04 Stefano Babic wrote:

On 31/01/2012 20:14, Eric Nelson wrote:

On 01/31/2012 11:11 AM, Mike Frysinger wrote:

On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:

Patch 1 modifies the 'sf' command to allow a default bus and
chip-select

to be specified by board headers. This allows a bare 'sf' probe command:
U-Boot>   sf probe

instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed

to specify GP3:19 on SabreLite:
U-Boot>   sf probe 0x5300

Patch 2 provides a description of usage and configuration of
CONFIG_CMD_SF.


you can drop these two SF patches from your mx6q series.  i don't want
to keep
checking to see if you've updated them :p.


I figured as much, but I can't really test them without the rest of the
series...


It does not matter - Mike, what do you think if I merge the whole
patchset into u-boot-imx ? Else the mx6qsabrelite board cannot be built
until all patches will be merged by Wolfgang.


i don't see why this series depends on the two spi flash patches.  they were
both "nice to have" patches which only change the default `sf` behavior.  the
boards will compile&  run perfectly fine without them.
-mike


Hi Mike,

My comment was the inverse: I can't test just the 'sf probe' updates unless I
have the core SPI flash support for mx6qsabrelite.

AFAIK, the update to cmd_sf doesn't have any dependencies and of course the 
README update doesn't.


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Re: [U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 01/31/2012 11:11 AM, Mike Frysinger wrote:

On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:

Patch 1 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
   U-Boot>  sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed
to specify GP3:19 on SabreLite:
   U-Boot>  sf probe 0x5300

Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.


you can drop these two SF patches from your mx6q series.  i don't want to keep
checking to see if you've updated them :p.
-mike


I figured as much, but I can't really test them without the rest of the
series...
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[U-Boot] [PATCH V6 - Part 2 - 2/2] README: Add description of SPI Flash (SF) command configuration

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 README |   20 
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/README b/README
index 9d713e8..4dbebcb 100644
--- a/README
+++ b/README
@@ -809,6 +809,7 @@ The following options need to be configured:
  (requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR  Support for DCR Register access
  (4xx only)
+   CONFIG_CMD_SF   * Read/write/erase SPI NOR flash
CONFIG_CMD_SHA1SUMprint sha1 memory digest
  (requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOURCE "source" command Support
@@ -2191,6 +2192,25 @@ The following options need to be configured:
allows to read/write in Dataflash via the standard
commands cp, md...
 
+- Serial Flash support
+   CONFIG_CMD_SF
+
+   Defining this option enables SPI flash commands
+   'sf probe/read/write/erase/update'.
+
+   Usage requires an initial 'probe' to define the serial
+   flash parameters, followed by read/write/erase/update
+   commands.
+
+   The following defaults may be provided by the platform
+   to handle the common case when only a single serial
+   flash is present on the system.
+
+   CONFIG_SF_DEFAULT_BUS   Bus identifier
+   CONFIG_SF_DEFAULT_CSChip-select
+   CONFIG_SF_DEFAULT_MODE  (see include/spi.h)
+   CONFIG_SF_DEFAULT_SPEED in Hz
+
 - SystemACE Support:
CONFIG_SYSTEMACE
 
-- 
1.7.1

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[U-Boot] [PATCH V6 - Part 4 - 1/1] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |2 +-
 include/configs/mx6qsabrelite.h   |2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 97a77e8..03a088a 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -208,7 +208,7 @@ iomux_v3_cfg_t ecspi1_pads[] = {
 
 void setup_spi(void)
 {
-   gpio_direction_output(GPIO_NUMBER(3, 19), 1);
+   gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 ARRAY_SIZE(ecspi1_pads));
 }
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index bcb1a42..2286bb0 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -49,6 +49,8 @@
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  0
+#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_NUMBER(3, 19)<<8))
 #define CONFIG_SF_DEFAULT_SPEED 2500
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
-- 
1.7.1

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[U-Boot] [PATCH V6 - Part 5 - 1/1] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Eric Nelson]

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

The SPI driver can take as chip select the controller's chip selects
as well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number.

The GPIO used on Sabre Lite is GP3:19 == 83.

Signed-off-by: Eric Nelson 

---
 include/configs/mx6qsabrelite.h |   18 +++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 2286bb0..c49e3ab 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,22 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
-#define CONFIG_ENV_SIZE(8 * 1024)
+#define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS  CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODECONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ  CONFIG_SF_DEFAULT_SPEED
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

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[U-Boot] [PATCH V6 - Part 2 - 1/3] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

Move (E)CSPI register declarations into the imx-regs.h files for each supported 
CPU

Introduce two new macros to control conditional setup
 MXC_CSPI - Used for processors with the Configurable Serial Peripheral 
Interface (MX3x)
 MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx31/imx-regs.h |   27 
 arch/arm/include/asm/arch-mx35/imx-regs.h |   25 
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +
 drivers/spi/mxc_spi.c |   93 ++---
 4 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h 
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 798cc74..6454acb 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -901,4 +901,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN(1 << 8)
 #define MXC_EHCI_IPPUE_UP  (1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001, \
+   0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h 
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
 #define IPU_CONF_IC_EN (1<<1)
 #define IPU_CONF_SCI_EN(1<<0)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001,
+
 #define GPIO_PORT_NUM  3
 #define GPIO_NUM_PIN   32
 
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M3
 
 /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   CSPI1_BASE_ADDR, \
+   CSPI2_BASE_ADDR, \
+   CSPI3_BASE_ADDR,
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN   

[U-Boot] [PATCH V6 - Part 2 - 2/3] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |   44 ++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 29841dd..326f865 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -194,6 +194,50 @@ struct src {
u32 gpr10;
 };
 
+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   ECSPI1_BASE_ADDR, \
+   ECSPI2_BASE_ADDR, \
+   ECSPI3_BASE_ADDR, \
+   ECSPI4_BASE_ADDR, \
+   ECSPI5_BASE_ADDR
+
 struct iim_regs {
u32 ctrl;
u32 ctrl_set;
-- 
1.7.1

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[U-Boot] [PATCH V6 - Part 2 - 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 board/freescale/mx6qsabrelite/imximage.cfg|2 +-
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +
 include/configs/mx6qsabrelite.h   |9 +
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/imximage.cfg 
b/board/freescale/mx6qsabrelite/imximage.cfg
index 83dee6f..c389427 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF0
 DATA 4 0x020c4078 0x00FFF300
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a53b01f..97a77e8 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |\
+   PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+   /* SS1 */
+   MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+   gpio_direction_output(GPIO_NUMBER(3, 19), 1);
+   imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL 0x9
 #define MII_EXTENDED_CTRL  0xb
 #define MII_EXTENDED_DATAW 0xc
@@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis)
return ret;
}
 
+#ifdef CONFIG_MXC_SPI
+   setup_spi();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index d650ee3..bcb1a42 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,15 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
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[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

Patch 1 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
  U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed
to specify GP3:19 on SabreLite:
  U-Boot> sf probe 0x5300

Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.

Signed-off-by: Eric Nelson 
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[U-Boot] [PATCH V6 - Part 3 - 1/2] sf command: allow default bus and chip selects

[Eric Nelson]

This patch allows a board configuration file to provide default bus
and chip-selects for SPI flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this allows
a much simpler command line:
U-Boot> sf probe
instead of
U-Boot> sf probe 0x5300
Signed-off-by: Eric Nelson 
---
 common/cmd_sf.c |   37 +
 1 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 612fd18..98e4162 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -17,6 +17,12 @@
 #ifndef CONFIG_SF_DEFAULT_MODE
 # define CONFIG_SF_DEFAULT_MODESPI_MODE_3
 #endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS  0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS 0
+#endif
 
 static struct spi_flash *flash;
 
@@ -63,27 +69,26 @@ static int sf_parse_len_arg(char *arg, ulong *len)
 
 static int do_spi_flash_probe(int argc, char * const argv[])
 {
-   unsigned int bus = 0;
-   unsigned int cs;
+   unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+   unsigned int cs = CONFIG_SF_DEFAULT_CS;
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
struct spi_flash *new;
 
-   if (argc < 2)
-   return -1;
-
-   cs = simple_strtoul(argv[1], &endp, 0);
-   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
-   return -1;
-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
-
-   bus = cs;
-   cs = simple_strtoul(endp + 1, &endp, 0);
-   if (*endp != 0)
+   if (argc >= 2) {
+   cs = simple_strtoul(argv[1], &endp, 0);
+   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
return -1;
+   if (*endp == ':') {
+   if (endp[1] == 0)
+   return -1;
+
+   bus = cs;
+   cs = simple_strtoul(endp + 1, &endp, 0);
+   if (*endp != 0)
+   return -1;
+   }
}
 
if (argc >= 3) {
@@ -299,7 +304,7 @@ usage:
 U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
-   "probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
+   "probe [[bus:]cs] [hz] [mode]   - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset len- read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
-- 
1.7.1

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[U-Boot] [PATCH V6 - Part 1 - 1/1] mx6q: define GPIO macros for translating between ordinals and port:index

[Eric Nelson]

The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The registers themselves
and much of the i.MX documentation are banked in groups of 32, and these
macros allow the use of the port:index numbering for clarity.

GPIO_NUMBER() converts to ordinal value from port:index
GPIO_PORT() returns the port of an ordinal value
GPIO_INDEX() returns the index or offset of the ordinal.

Discussion on the mailing list at
http://lists.denx.de/pipermail/u-boot/2012-January/116927.html

Signed-off-by: Eric Nelson 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5227b44..8a9eeb4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -164,6 +164,10 @@
 #define IRAM_SIZE0x0004
 #define IMX_IIM_BASE OCOTP_BASE_ADDR
 
+#define GPIO_NUMBER(port, index)   port)-1)*32)+((index)&31))
+#define GPIO_TO_PORT(number)   (((number)/32)+1)
+#define GPIO_TO_INDEX(number)  ((number)&31)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include 
 
-- 
1.7.1

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[U-Boot] [PATCH V6 - Part 2 - 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html   
and requested in 
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Signed-off-by: Eric Nelson 

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[U-Boot] MX6q SPI refactoring and related patches

[Eric Nelson]

I'm about to send an updated set of patches for mxc_spi re-factoring
and the related cleanup stemming from the discussions in
http://lists.denx.de/pipermail/u-boot/2012-January/116816.html

These are split into multiple patch sets as suggested by Dirk:
http://lists.denx.de/pipermail/u-boot/2012-January/116865.html

Because these are all re-sends, I'm tagging them as "V6" as requested
by Jason:
http://lists.denx.de/pipermail/u-boot/2012-January/116894.html

I'm also including a "PART #" to make it clear which patches are
grouped together.

-- Part 1 will contain basic support for translating between
   ordinal GPIO numbers and port:index forms.
   It is required for parts 2, 4, and 5

-- Part 2 (3 patches) re-factors mxc_spi by moving register
   declarations into their arch-specific headers. This changed from
   the previous submission by using GPIO_NUMBER() instead of the
   undefined IMX_GPIO_NR().
http://lists.denx.de/pipermail/u-boot/2012-January/116901.html

-- Part 3 (2 patches) allows a board to define default values
   for SPI ROM bus and chip-selects and add some documentation for the same.
   I believe these have already been approved by Mike Frysinger.

-- Part 4 defines defaults for the mx6qsabrelite board. Note
   that this is slightly different from previous submission by also
   changing a reference to GPIO_NUMBER(3,19) to use the new default
   value (CONFIG_SF_DEFAULT_CS).

-- Part 5 conditionally defines a configuration for use in
   booting and saving environment to SPI flash instead of SD card
   to make it easier to switch between them.

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Re: [U-Boot] [PATCH 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 01/31/2012 08:16 AM, Mike Frysinger wrote:

On Monday 30 January 2012 15:02:24 Eric Nelson wrote:

Patch 1 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
   U-Boot>  sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed
to specify GP3:19 on SabreLite:
   U-Boot>  sf probe 0x5300

Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.


thanks, i'll merge both into my sf branch and then push to wolfgang for next
merge window (if he doesn't pick things up directly himself)
-mike


Thanks Mike
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Re: [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

On 01/31/2012 02:31 AM, Jason Hui wrote:

Eric,

On Tue, Jan 31, 2012 at 3:52 AM, Eric Nelson
  wrote:

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---
  board/freescale/mx6qsabrelite/imximage.cfg|2 +-
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +
  include/configs/mx6qsabrelite.h   |9 +
  3 files changed, 35 insertions(+), 1 deletions(-)


After apply the patch, I have the build errors:
../mx6qsabrelite/mx6qsabrelite.c:211: undefined reference to `IMX_GPIO_NR'

So, the patch should depends on others. If one patch set is depend on
others, it's better to tell it
in the cover letter of your patch set. Thanks.



Ouch! It's all about the GPIO numbers...

This occurred when I re-based to Stefano's tree and will require
another patch to keep the BANK:OFFSET numbering scheme. There's a
patch lingering in Dirk's tree that defines IMX_GPIO_NR() in gpio.h.

See http://lists.denx.de/pipermail/u-boot/2012-January/116866.html
for details.

I was hoping to get some feedback before generating a patch and
revising this patch (and removing GPIO_3_19 macro):

http://lists.denx.de/pipermail/u-boot/2012-January/116874.html

That said, I'll revise and re-send along with a patch adding
support for:
GPIO_NUMBER(port,index)
GPIO_PORT(number)
GPIO_INDEX(number)
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Re: [U-Boot] Can u-Boot Ran from RAM?

[Eric Nelson]

On 01/30/2012 09:07 PM, Bud Miljkovic wrote:

Hi there,



While getting acquainted with possible u-Boot development issues, I read
FAQ "14.2.1.  Can U-Boot be configured such that it can be started in
RAM?" and was puzzled to learn that u-Boot cannot run from RAM.



Considering a custom platform, using i.MX536, I understand that the
i.MX53x processor has its own ROM-based code that performs boot time
essential devices initialisation, etc.  In the case when NAND flash is
the program-image medium at the boot stage, first, the ROM-based code
checks for Discovered Bad Blocks Table (DBBT) presence and searches for
valid Firmware Configuration Block (FCB) on external NAND Flash.



If FCB is found that points to the NAND Flash page(s) that contain the
first 4K of initial firmware to be loaded from NAND Flash. Then, it
loads the 4K of data, pointed by FCB, into the NFC RAM buffer. These
data contain a valid Image Vector Table (IVT).  Then, the ROM-based code
processes IVT, executes the Device Configuration Data (DCD) sequences to
initialize boot-related integrated peripherals (typically, these are
IOMUX, SDRAM controller and boot memory controller), then copies the
application code, also contained in IVT, to target memory (typically,
SDRAM) and jumps to it. Typically, this application code is the custom
primary bootloader that completes loading the application code (e.g.
main OS bootloader) and passes the control to it.



If FCB is not found the ROM-based code starts executing a download
protocol over UART or USB port in an attempt to get a valid IVT from a
host.  If the IVT is eventually obtained it is processed as before.



So the question is can this "custom primary bootloader" role, in fact,
be played by u-Boot.  Reading your text of FAQ 14.2.1., it seems to me
that it cannot.  On the other hand I know of some Freescale i.MX53x demo
boards (e.g. ARD, LOCO) that use u-Boot.



I wonder what I'm missing here.



I think that FAQ is a bit misleading and really refers to using another boot
loader to load U-Boot.

On all i.MX processors I've had the pleasure of using, U-Boot runs only
from RAM. I think you probably knew this because very few i.MX designs
even have other memory (i.e. NOR flash) that allows XIP.

For instance, the LOCO certainly isn't running __from__ SD card.

Take a look at the link maps for builds of these platforms to clarify.

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Re: [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

On 01/30/2012 11:51 PM, Jason Liu wrote:

Eric,

2012/1/31 Eric Nelson:

This patch set refactors mxc_spi as described in
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite
specifically.


If this patch-set is re-send, please specify version Vx and change-log. Thanks,


Hi Jason,

I wasn't quite sure how to handle that, since I split up a 7-patch
series into independent parts.

Any guidance?
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[U-Boot] [PATCH] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Eric Nelson]

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

The SPI driver can take as chip select the controller's chip selects
as well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number.

The GPIO used on Sabre Lite is GP3:19 == 83.
---
 include/configs/mx6qsabrelite.h |   18 +++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 3bf7819..70c9d10 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -175,10 +175,22 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
-#define CONFIG_ENV_SIZE(8 * 1024)
+#define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS  CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODECONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ  CONFIG_SF_DEFAULT_SPEED
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

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[U-Boot] [PATCH] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 include/configs/mx6qsabrelite.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index bcb1a42..3bf7819 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@
 
 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
+#define GPIO_3_19 ((2*32)+19)
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  0
+#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_3_19<<8))
 #define CONFIG_SF_DEFAULT_SPEED 2500
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
-- 
1.7.1

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[U-Boot] [PATCH 1/2] sf command: allow default bus and chip selects

[Eric Nelson]

This patch allows a board configuration file to provide default bus
and chip-selects for SPI flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this allows
a much simpler command line:
U-Boot> sf probe
instead of
U-Boot> sf probe 0x5300
Signed-off-by: Eric Nelson 
---
 common/cmd_sf.c |   37 +
 1 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 612fd18..98e4162 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -17,6 +17,12 @@
 #ifndef CONFIG_SF_DEFAULT_MODE
 # define CONFIG_SF_DEFAULT_MODESPI_MODE_3
 #endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS  0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS 0
+#endif
 
 static struct spi_flash *flash;
 
@@ -63,27 +69,26 @@ static int sf_parse_len_arg(char *arg, ulong *len)
 
 static int do_spi_flash_probe(int argc, char * const argv[])
 {
-   unsigned int bus = 0;
-   unsigned int cs;
+   unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+   unsigned int cs = CONFIG_SF_DEFAULT_CS;
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
struct spi_flash *new;
 
-   if (argc < 2)
-   return -1;
-
-   cs = simple_strtoul(argv[1], &endp, 0);
-   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
-   return -1;
-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
-
-   bus = cs;
-   cs = simple_strtoul(endp + 1, &endp, 0);
-   if (*endp != 0)
+   if (argc >= 2) {
+   cs = simple_strtoul(argv[1], &endp, 0);
+   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
return -1;
+   if (*endp == ':') {
+   if (endp[1] == 0)
+   return -1;
+
+   bus = cs;
+   cs = simple_strtoul(endp + 1, &endp, 0);
+   if (*endp != 0)
+   return -1;
+   }
}
 
if (argc >= 3) {
@@ -299,7 +304,7 @@ usage:
 U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
-   "probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
+   "probe [[bus:]cs] [hz] [mode]   - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset len- read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
-- 
1.7.1

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[U-Boot] [PATCH 2/2] README: Add description of SPI Flash (SF) command configuration

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 README |   20 
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/README b/README
index 9d713e8..4dbebcb 100644
--- a/README
+++ b/README
@@ -809,6 +809,7 @@ The following options need to be configured:
  (requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR  Support for DCR Register access
  (4xx only)
+   CONFIG_CMD_SF   * Read/write/erase SPI NOR flash
CONFIG_CMD_SHA1SUMprint sha1 memory digest
  (requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOURCE "source" command Support
@@ -2191,6 +2192,25 @@ The following options need to be configured:
allows to read/write in Dataflash via the standard
commands cp, md...
 
+- Serial Flash support
+   CONFIG_CMD_SF
+
+   Defining this option enables SPI flash commands
+   'sf probe/read/write/erase/update'.
+
+   Usage requires an initial 'probe' to define the serial
+   flash parameters, followed by read/write/erase/update
+   commands.
+
+   The following defaults may be provided by the platform
+   to handle the common case when only a single serial
+   flash is present on the system.
+
+   CONFIG_SF_DEFAULT_BUS   Bus identifier
+   CONFIG_SF_DEFAULT_CSChip-select
+   CONFIG_SF_DEFAULT_MODE  (see include/spi.h)
+   CONFIG_SF_DEFAULT_SPEED in Hz
+
 - SystemACE Support:
CONFIG_SYSTEMACE
 
-- 
1.7.1

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[U-Boot] [PATCH 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

Patch 1 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
  U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed
to specify GP3:19 on SabreLite:
  U-Boot> sf probe 0x5300

Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.

Signed-off-by: Eric Nelson 

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[U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 board/freescale/mx6qsabrelite/imximage.cfg|2 +-
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +
 include/configs/mx6qsabrelite.h   |9 +
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/imximage.cfg 
b/board/freescale/mx6qsabrelite/imximage.cfg
index 83dee6f..c389427 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF0
 DATA 4 0x020c4078 0x00FFF300
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a53b01f..b4282aa 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |\
+   PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+   /* SS1 */
+   MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+   gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+   imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL 0x9
 #define MII_EXTENDED_CTRL  0xb
 #define MII_EXTENDED_DATAW 0xc
@@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis)
return ret;
}
 
+#ifdef CONFIG_MXC_SPI
+   setup_spi();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index d650ee3..bcb1a42 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,15 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
1.7.1

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[U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

Move (E)CSPI register declarations into the imx-regs.h files for each supported 
CPU

Introduce two new macros to control conditional setup
 MXC_CSPI - Used for processors with the Configurable Serial Peripheral 
Interface (MX3x)
 MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx31/imx-regs.h |   27 
 arch/arm/include/asm/arch-mx35/imx-regs.h |   25 
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +
 drivers/spi/mxc_spi.c |   93 ++---
 4 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h 
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 798cc74..6454acb 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -901,4 +901,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN(1 << 8)
 #define MXC_EHCI_IPPUE_UP  (1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001, \
+   0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h 
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
 #define IPU_CONF_IC_EN (1<<1)
 #define IPU_CONF_SCI_EN(1<<0)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001,
+
 #define GPIO_PORT_NUM  3
 #define GPIO_NUM_PIN   32
 
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M3
 
 /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   CSPI1_BASE_ADDR, \
+   CSPI2_BASE_ADDR, \
+   CSPI3_BASE_ADDR,
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN   

[U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html   
and requested in 
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

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[U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |   44 ++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5227b44..ec74ff2 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -190,6 +190,50 @@ struct src {
u32 gpr10;
 };
 
+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   ECSPI1_BASE_ADDR, \
+   ECSPI2_BASE_ADDR, \
+   ECSPI3_BASE_ADDR, \
+   ECSPI4_BASE_ADDR, \
+   ECSPI5_BASE_ADDR
+
 struct iim_regs {
u32 ctrl;
u32 ctrl_set;
-- 
1.7.1

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Re: [U-Boot] [PATCH V4 6/7] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

On 01/30/2012 11:35 AM, Dirk Behme wrote:

On 30.01.2012 19:10, Eric Nelson wrote:

On 01/29/2012 07:36 PM, Marek Vasut wrote:

On 01/29/2012 03:16 PM, Marek Vasut wrote:

On 01/29/2012 01:11 PM, Marek Vasut wrote:

On 01/29/2012 12:18 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---

include/configs/mx6qsabrelite.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h
b/include/configs/mx6qsabrelite.h index 8dd6e39..cc770e2 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@

#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF

+#define GPIO_3_19 ((2*32)+19)


I'd expect this to be in platform headers?


This is a choice made in the SabreLite design. I don't think
the same choice has been made for other i.MX6 boards.


I mean the definition of the GPIO_3_19 ...


I don't think we want to set precedent for defining
constants for the 100s of GPIO numbers.

That said, I could achieve my objective of clarifying
what the number meant (that the constant refers to a GP) by

changing this:
#define CONFIG_SF_DEFAULT_CS (0|(GPIO_3_19<<8))

to this

#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3,19)<<8))


Why the (0| part ? Anyway, that indeed looks better, more standard
even.

And I think for MX5, there was even stuff defining the GPIO numbers
imported from Linux.

M


There's a bit of an issue with this. The IMX_GPIO_NR() macro
is defined in arch-mx6/gpio.h which is normally included after
mx6qsabrelite.h because the latter defines the machine.


And the CPP will choke on that ?


Assembler or linker. IMX_GPIO_NR will be undefined and treated as an
external unless we add this nested include into
include/configs/mx6qsabrelite.h:

#ifndef __ASSEMBLY__
#include
#endif

arch-mx6/gpio.h isn't directly ASM-friendly.

This seems like a lot of #include-foo for giving a name to a constant,
don't you think?


Better than redefining stuff, which will eventually lead to errors
and breakage.



Hmmm. I just noticed that the IMX_GPIO_NR() macro isn't in Stefano's
tree.
My previous patches were against Dirk's tree on GitHub, which has a patch
from Troy:
https://github.com/dirkbehme/u-boot-imx6/commit/c8b2870efd041f820a91eebcb888c84a4f79f1f6

If we move this macro into arch-mx6/imx-regs.h, we avoid the #if.

Looking at the remaining content of gpio.h, it seems that it's
driver-specific
anyway (only the driver should be worried about the register layout of
the GPIO
controller).

If there are no objections, I'll forward a separate patch to define
the macro.


Yes, please. I have this on my todo list, too. But I haven't found the time to
look at the consequences trying to mainline this patch. I.e. if we try to
mainline this, we have to touch all gpio_xxx() functions to use this new macro?
At least for i.MX6? Or does this macro apply for more i.MX SoCs? If yes, do we
have to find out for which it will work? And move it to a i.MX common gpio
header? And then touch all i.MX code it applies to?



At the moment, the only code which uses IMX_GPIO_NR() is specific to
MX6Q and Sabre-Lite.

I looked for some commonality, but didn't find any in the i.MX trees.

arch-mx35/mx35-pins.h defines GPIO_TO_PORT() and GPIO_TO_INDEX()
which are the opposite of IMX_GPIO_NR().

arch-mx5/mx5x_pins.h does the same.

arch-davinci and arch-tegra2 both define GPIO_BANK() and GPIO_PORT()
for the same purpose

mx28 defines PAD_BANK() and PAD_PIN() but use an input of iomux_cfg_t
and not an integer.

The Linux model allows the platform to define the mapping from GPIO
numbers <-> drivers but doesn't use the concept of banks except within
a driver.

IOW, it doesn't seem like there's an obvious right thing to do, so
I'd like to suggest that either:

- We define GPIO_NUMBER(bank,offset) inside imx-regs.h for
use in mapping to GPIO numbers

- We follow the convention of arch-mx5/ and arch-mx35 and
define macros GPIO_TO_PORT() and GPIO_TO_INDEX() to go the
other direction

- We update drivers/gpio/mxc_gpio.c to use the GPIO_TO_PORT()
and GPIO_TO_INDEX() macros instead of code like this:

unsigned int port = gpio >> 5;

Or we just use the constant 0x53 for this value (as is done for the
efikamx and vision2 boards).


Anyway, many thanks for your good work!

Best regards

Dirk

Btw.: It looks to me that the patch series to introduce the i.MX6 SPI driver
increases from each version of the patch series to the next one. I'm not sure if
this is ok? Or if we should try to split it to smaller chunks which would be
easier to get them merged?



Point taken. I've been wondering whether there was a way to steer clear
of the rabbit hole...

At the moment, I think patches 1-3 have been acked and really comprise
the 'refactoring' part.

I thi

Re: [U-Boot] [PATCH V4 6/7] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

On 01/29/2012 07:36 PM, Marek Vasut wrote:

On 01/29/2012 03:16 PM, Marek Vasut wrote:

On 01/29/2012 01:11 PM, Marek Vasut wrote:

On 01/29/2012 12:18 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---

 include/configs/mx6qsabrelite.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h
b/include/configs/mx6qsabrelite.h index 8dd6e39..cc770e2 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@

 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF

+#define GPIO_3_19 ((2*32)+19)


I'd expect this to be in platform headers?


This is a choice made in the SabreLite design. I don't think
the same choice has been made for other i.MX6 boards.


I mean the definition of the GPIO_3_19 ...


I don't think we want to set precedent for defining
constants for the 100s of GPIO numbers.

That said, I could achieve my objective of clarifying
what the number meant (that the constant refers to a GP) by

changing this:
#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_3_19<<8))

to this

#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3,19)<<8))


Why the (0| part ? Anyway, that indeed looks better, more standard even.

And I think for MX5, there was even stuff defining the GPIO numbers
imported from Linux.

M


There's a bit of an issue with this. The IMX_GPIO_NR() macro
is defined in arch-mx6/gpio.h which is normally included after
mx6qsabrelite.h because the latter defines the machine.


And the CPP will choke on that ?


Assembler or linker. IMX_GPIO_NR will be undefined and treated as an
external unless we add this nested include into
include/configs/mx6qsabrelite.h:

#ifndef __ASSEMBLY__
#include
#endif

arch-mx6/gpio.h isn't directly ASM-friendly.

This seems like a lot of #include-foo for giving a name to a constant,
don't you think?


Better than redefining stuff, which will eventually lead to errors and breakage.



Hmmm. I just noticed that the IMX_GPIO_NR() macro isn't in Stefano's tree.
My previous patches were against Dirk's tree on GitHub, which has a patch
from Troy:

https://github.com/dirkbehme/u-boot-imx6/commit/c8b2870efd041f820a91eebcb888c84a4f79f1f6

If we move this macro into arch-mx6/imx-regs.h, we avoid the #if.

Looking at the remaining content of gpio.h, it seems that it's driver-specific
anyway (only the driver should be worried about the register layout of the GPIO
controller).

If there are no objections, I'll forward a separate patch to define the macro.

Should this be based on Stefano's tree?

Please advise,


Eric
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Re: [U-Boot] [PATCH V4 6/7] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

On 01/29/2012 03:16 PM, Marek Vasut wrote:

On 01/29/2012 01:11 PM, Marek Vasut wrote:

On 01/29/2012 12:18 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---

include/configs/mx6qsabrelite.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h
b/include/configs/mx6qsabrelite.h index 8dd6e39..cc770e2 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@

#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF

+#define GPIO_3_19 ((2*32)+19)


I'd expect this to be in platform headers?


This is a choice made in the SabreLite design. I don't think
the same choice has been made for other i.MX6 boards.


I mean the definition of the GPIO_3_19 ...


I don't think we want to set precedent for defining
constants for the 100s of GPIO numbers.

That said, I could achieve my objective of clarifying
what the number meant (that the constant refers to a GP) by
changing this:

#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_3_19<<8))

to this

#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3,19)<<8))


Why the (0| part ? Anyway, that indeed looks better, more standard even.

And I think for MX5, there was even stuff defining the GPIO numbers imported
from Linux.

M



There's a bit of an issue with this. The IMX_GPIO_NR() macro
is defined in arch-mx6/gpio.h which is normally included after
mx6qsabrelite.h because the latter defines the machine.


And the CPP will choke on that ?



Assembler or linker. IMX_GPIO_NR will be undefined and treated as an
external unless we add this nested include into include/configs/mx6qsabrelite.h:

#ifndef __ASSEMBLY__
#include 
#endif

arch-mx6/gpio.h isn't directly ASM-friendly.

This seems like a lot of #include-foo for giving a name to a constant, don't
you think?
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Re: [U-Boot] [PATCH V4 6/7] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

On 01/29/2012 01:11 PM, Marek Vasut wrote:

On 01/29/2012 12:18 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---

   include/configs/mx6qsabrelite.h |3 +++
   1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h
b/include/configs/mx6qsabrelite.h index 8dd6e39..cc770e2 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@

   #define CONFIG_CMD_SF
   #ifdef CONFIG_CMD_SF

+#define GPIO_3_19 ((2*32)+19)


I'd expect this to be in platform headers?


This is a choice made in the SabreLite design. I don't think
the same choice has been made for other i.MX6 boards.


I mean the definition of the GPIO_3_19 ...



I don't think we want to set precedent for defining
constants for the 100s of GPIO numbers.

That said, I could achieve my objective of clarifying
what the number meant (that the constant refers to a GP) by
changing this:

#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_3_19<<8))

to this

#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3,19)<<8))

There's a bit of an issue with this. The IMX_GPIO_NR() macro
is defined in arch-mx6/gpio.h which is normally included after
mx6qsabrelite.h because the latter defines the machine.
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Re: [U-Boot] [PATCH V4 6/7] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

On 01/29/2012 12:18 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---
  include/configs/mx6qsabrelite.h |3 +++
  1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h
b/include/configs/mx6qsabrelite.h index 8dd6e39..cc770e2 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@

  #define CONFIG_CMD_SF
  #ifdef CONFIG_CMD_SF
+#define GPIO_3_19 ((2*32)+19)


I'd expect this to be in platform headers?



This is a choice made in the SabreLite design. I don't think
the same choice has been made for other i.MX6 boards.
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Re: [U-Boot] [PATCH V4 1/7] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

On 01/29/2012 12:16 PM, Marek Vasut wrote:

Move (E)CSPI register declarations into the imx-regs.h files for each
supported CPU

Introduce two new macros to control conditional setup
  MXC_CSPI - Used for processors with the Configurable Serial Peripheral
Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable...
(MX5x, MX6x)

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---
  arch/arm/include/asm/arch-mx31/imx-regs.h |   27 
  arch/arm/include/asm/arch-mx35/imx-regs.h |   25 
  arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +
  drivers/spi/mxc_spi.c |   93
++--- 4 files changed, 88 insertions(+), 87
deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h
b/arch/arm/include/asm/arch-mx31/imx-regs.h index 6a517dd..70e3338 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -890,4 +890,31 @@ struct esdc_regs {
  #define MXC_EHCI_IPPUE_DOWN   (1<<  8)
  #define MXC_EHCI_IPPUE_UP (1<<  9)

+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1<<  0)
+#define MXC_CSPICTRL_MODE  (1<<  1)
+#define MXC_CSPICTRL_XCH   (1<<  2)
+#define MXC_CSPICTRL_SMC   (1<<  3)
+#define MXC_CSPICTRL_POL   (1<<  4)
+#define MXC_CSPICTRL_PHA   (1<<  5)
+#define MXC_CSPICTRL_SSCTL (1<<  6)
+#define MXC_CSPICTRL_SSPOL (1<<  7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x)&  0x3)<<  24)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x)&  0x1f)<<  8)
+#define MXC_CSPICTRL_DATARATE(x)   (((x)&  0x7)<<  16)
+#define MXC_CSPICTRL_TC(1<<  8)
+#define MXC_CSPICTRL_RXOVF (1<<  6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1<<  15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001, \
+   0x53f84000,
+
  #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h
b/arch/arm/include/asm/arch-mx35/imx-regs.h index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
  #define IPU_CONF_IC_EN(1<<1)
  #define IPU_CONF_SCI_EN   (1<<0)

+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1<<  0)
+#define MXC_CSPICTRL_MODE  (1<<  1)
+#define MXC_CSPICTRL_XCH   (1<<  2)
+#define MXC_CSPICTRL_SMC   (1<<  3)
+#define MXC_CSPICTRL_POL   (1<<  4)
+#define MXC_CSPICTRL_PHA   (1<<  5)
+#define MXC_CSPICTRL_SSCTL (1<<  6)
+#define MXC_CSPICTRL_SSPOL (1<<  7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x)&  0x3)<<  12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x)&  0xfff)<<  20)
+#define MXC_CSPICTRL_DATARATE(x)   (((x)&  0x7)<<  16)
+#define MXC_CSPICTRL_TC(1<<  7)
+#define MXC_CSPICTRL_RXOVF (1<<  6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1<<  15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001,
+
  #define GPIO_PORT_NUM 3
  #define GPIO_NUM_PIN  32

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h
b/arch/arm/include/asm/arch-mx5/imx-regs.h index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
  #define CS0_32M_CS1_32M_CS2_32M_CS3_32M   3

  /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1<<  0)
+#define MXC_CSPICTRL_MODE  (1<<  1)
+#define MXC_CSPICTRL_XCH   (1<<  2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x)&  0x3)<<  12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x)&  0xfff)<<  20)
+#define MXC_CSPICTRL_PREDIV(x) (((x)&  0xF)<<  12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x)&  0xF)<<  8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x)&  0x3)<<  18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1<<  7)
+#define MXC_CSPICTRL_RXOVF (1<<  6)
+#define MXC_CSPIPERIOD_32KHZ   (1<<  15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   CSPI1_BASE_ADDR, \
+   CSPI2_BASE_ADDR, \
+   CSPI3_BASE_ADDR,
+
+/*
   * Number of GPIO pins pe

Re: [U-Boot] [PATCH V4 5/7] README: Add description of SPI Flash (SF) command configuration

[Eric Nelson]

On 01/29/2012 12:17 PM, Marek Vasut wrote:

---
  README |   20 
  1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/README b/README
index f6ab85c..1a98915 100644
--- a/README
+++ b/README
@@ -800,6 +800,7 @@ The following options need to be configured:
  (requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR  Support for DCR Register access
  (4xx only)
+   CONFIG_CMD_SF   * Read/write/erase SPI NOR flash


Why did you add the asterisk here ?


Because CONFIG_CMD_SF isn't included in the default build.


http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob;f=README;h=9d713e8f4398b9af70844ab7910c67e400817bf6;hb=HEAD#l740
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[U-Boot] [PATCH V4 7/7] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Eric Nelson]

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

The SPI driver can take as chip select the controller's chip selects
as well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number.

The GPIO used on Sabre Lite is GP3:19 == 83.
---
 include/configs/mx6qsabrelite.h |   14 +-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index cc770e2..77d30c9 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -176,10 +176,22 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS  CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODECONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ  CONFIG_SF_DEFAULT_SPEED
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

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[U-Boot] [PATCH V4 6/7] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 include/configs/mx6qsabrelite.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8dd6e39..cc770e2 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,9 +46,12 @@
 
 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
+#define GPIO_3_19 ((2*32)+19)
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  0
+#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_3_19<<8))
 #define CONFIG_SF_DEFAULT_SPEED 2500
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
-- 
1.7.1

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[U-Boot] [PATCH V4 5/7] README: Add description of SPI Flash (SF) command configuration

[Eric Nelson]

---
 README |   20 
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/README b/README
index f6ab85c..1a98915 100644
--- a/README
+++ b/README
@@ -800,6 +800,7 @@ The following options need to be configured:
  (requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR  Support for DCR Register access
  (4xx only)
+   CONFIG_CMD_SF   * Read/write/erase SPI NOR flash
CONFIG_CMD_SHA1SUMprint sha1 memory digest
  (requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOURCE "source" command Support
@@ -2179,6 +2180,25 @@ The following options need to be configured:
allows to read/write in Dataflash via the standard
commands cp, md...
 
+- Serial Flash support
+   CONFIG_CMD_SF
+
+   Defining this option enables SPI flash commands
+   'sf probe/read/write/erase/update'.
+
+   Usage requires an initial 'probe' to define the serial
+   flash parameters, followed by read/write/erase/update
+   commands.
+
+   The following defaults may be provided by the platform
+   to handle the common case when only a single serial
+   flash is present on the system.
+
+   CONFIG_SF_DEFAULT_BUS   Bus identifier
+   CONFIG_SF_DEFAULT_CSChip-select
+   CONFIG_SF_DEFAULT_MODE  (see include/spi.h)
+   CONFIG_SF_DEFAULT_SPEED in Hz
+
 - SystemACE Support:
CONFIG_SYSTEMACE
 
-- 
1.7.1

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[U-Boot] [PATCH V4 2/7] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |   44 ++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7650cb9..00040c4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -190,6 +190,50 @@ struct src {
u32 gpr10;
 };
 
+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   ECSPI1_BASE_ADDR, \
+   ECSPI2_BASE_ADDR, \
+   ECSPI3_BASE_ADDR, \
+   ECSPI4_BASE_ADDR, \
+   ECSPI5_BASE_ADDR
+
 struct iim_regs {
u32 ctrl;
u32 ctrl_set;
-- 
1.7.1

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[U-Boot] [PATCH V4 1/7] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

Move (E)CSPI register declarations into the imx-regs.h files for each supported 
CPU

Introduce two new macros to control conditional setup
 MXC_CSPI - Used for processors with the Configurable Serial Peripheral 
Interface (MX3x)
 MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx31/imx-regs.h |   27 
 arch/arm/include/asm/arch-mx35/imx-regs.h |   25 
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +
 drivers/spi/mxc_spi.c |   93 ++---
 4 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h 
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6a517dd..70e3338 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -890,4 +890,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN(1 << 8)
 #define MXC_EHCI_IPPUE_UP  (1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001, \
+   0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h 
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
 #define IPU_CONF_IC_EN (1<<1)
 #define IPU_CONF_SCI_EN(1<<0)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001,
+
 #define GPIO_PORT_NUM  3
 #define GPIO_NUM_PIN   32
 
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M3
 
 /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   CSPI1_BASE_ADDR, \
+   CSPI2_BASE_ADDR, \
+   CSPI3_BASE_ADDR,
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN   

[U-Boot] [PATCH V4 4/7] sf command: allow default bus and chip selects

[Eric Nelson]

This patch allows a board configuration file to provide default bus
and chip-selects for SPI flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this allows
a much simpler command line:
U-Boot> sf probe
instead of
U-Boot> sf probe 0x5300
---
 common/cmd_sf.c |   37 +
 1 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 7225656..04a3258 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -17,6 +17,12 @@
 #ifndef CONFIG_SF_DEFAULT_MODE
 # define CONFIG_SF_DEFAULT_MODESPI_MODE_3
 #endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS  0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS 0
+#endif
 
 static struct spi_flash *flash;
 
@@ -63,27 +69,26 @@ static int sf_parse_len_arg(char *arg, ulong *len)
 
 static int do_spi_flash_probe(int argc, char * const argv[])
 {
-   unsigned int bus = 0;
-   unsigned int cs;
+   unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+   unsigned int cs = CONFIG_SF_DEFAULT_CS;
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
struct spi_flash *new;
 
-   if (argc < 2)
-   return -1;
-
-   cs = simple_strtoul(argv[1], &endp, 0);
-   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
-   return -1;
-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
-
-   bus = cs;
-   cs = simple_strtoul(endp + 1, &endp, 0);
-   if (*endp != 0)
+   if (argc >= 2) {
+   cs = simple_strtoul(argv[1], &endp, 0);
+   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
return -1;
+   if (*endp == ':') {
+   if (endp[1] == 0)
+   return -1;
+
+   bus = cs;
+   cs = simple_strtoul(endp + 1, &endp, 0);
+   if (*endp != 0)
+   return -1;
+   }
}
 
if (argc >= 3) {
@@ -299,7 +304,7 @@ usage:
 U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
-   "probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
+   "probe [[bus:]cs] [hz] [mode]   - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset len- read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
-- 
1.7.1

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[U-Boot] [PATCH V4 3/7] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic 
---
 board/freescale/mx6qsabrelite/imximage.cfg|2 +-
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +
 include/configs/mx6qsabrelite.h   |9 +
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/imximage.cfg 
b/board/freescale/mx6qsabrelite/imximage.cfg
index b4ff010..fa40bff 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF0
 DATA 4 0x020c4078 0x00FFF300
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a0b648f..2ba6b0c 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |\
+   PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+   /* SS1 */
+   MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+   gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+   imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL 0x9
 #define MII_EXTENDED_CTRL  0xb
 #define MII_EXTENDED_DATAW 0xc
@@ -250,6 +271,10 @@ int board_early_init_f(void)
 {
setup_iomux_uart();
 
+#ifdef CONFIG_MXC_SPI
+   setup_spi();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 034fc40..8dd6e39 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,15 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
1.7.1

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[U-Boot] [PATCH V4 0/7] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in 
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Patch 4 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
 U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed  
to specify GP3:19 on SabreLite:
 U-Boot> sf probe 0x5300   

Patch 5 provides a description of usage and configuration of CONFIG_CMD_SF.

Patch 6 adds default chip-select values for mx6qsabrelite platform.

Patch 7 adds reference macros for use in storing the environment
in serial flash to match the use on Freescale's U-Boot release

This patch set has been compiled against the following configurations,
but only tested on mx6qsabrelite:
mx6qsabrelite
mx51evk
mx31pdk
mx35pdk

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[U-Boot] [PATCH V4 0/7] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Patch 4 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
 U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed
to specify GP3:19 on SabreLite:
 U-Boot> sf probe 0x5300

Patch 5 provides a description of usage and configuration of CONFIG_CMD_SF.

Patch 6 adds default chip-select values for mx6qsabrelite platform.

Patch 7 adds reference macros for use in storing the environment
in serial flash to match the use on Freescale's U-Boot release

This patch set has been compiled against the following configurations,
but only tested on mx6qsabrelite:
mx6qsabrelite
mx51evk
mx31pdk
mx35pdk
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Re: [U-Boot] [PATCH V3 4/6] sf command: allow default chip select through CONFIG_SPI_FLASH_CS

[Eric Nelson]

On 01/26/2012 07:50 PM, Mike Frysinger wrote:

On Thursday 26 January 2012 20:22:22 Eric Nelson wrote:

On 01/24/2012 11:08 AM, Mike Frysinger wrote:

On Tuesday 24 January 2012 11:18:22 Eric Nelson wrote:

This patch allows a board configuration file to provide a default
chip-select for serial flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this

allows a much simpler command line:
U-Boot>   sf probe

instead of

U-Boot>   sf probe 0x5300


NAK (to this version of the patch): missing README update, and other
issues below


Which README? The only references I find to serial flash support
are in board-specific README files.


all new CONFIG_xxx defines should be documented in the top level README.
granted, the existin SF ones have slipped in without being documented, but
that's bad for them ;).



Ok. I'll re-send with README updates.


--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c

-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
+   }
+#else
+   cs = CONFIG_SPI_FLASH_CS ;
+#endif


you're setting the default CS, not locking it in.  so a better config
knob name

would be something like:
CONFIG_SF_DEFAULT_CS

this matches the existing CONFIG_SF_XXX defines

also, you have a spurious space before the semicolon there


Thanks Mike,

FWIW, I chose this name on purpose to make life easier on a couple of
other boards immediately (efika and vision2):


those boards are dumb -- that define isn't used anywhere, so that's just dead
code.  cmd_sf has a standard already, so new defines specific to cmd_sf should
follow that.
-mike


Ok. I'll let their maintainers update appropriately.
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Re: [U-Boot] [PATCH V3 4/6] sf command: allow default chip select through CONFIG_SPI_FLASH_CS

[Eric Nelson]

On 01/25/2012 08:10 AM, Matthias Fuchs wrote:

Hi Eric,

please see my comments below.

On 24.01.2012 17:18, Eric Nelson wrote:

This patch allows a board configuration file to provide a default
chip-select for serial flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this allows
a much simpler command line:
U-Boot>  sf probe
instead of
U-Boot>  sf probe 0x5300

Signed-off-by: Eric Nelson
Acked-by: Dirk Behme
Acked-by: Stefano Babic
---
  common/cmd_sf.c |   34 +++---
  1 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 7225656..4b32171 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -70,20 +70,28 @@ static int do_spi_flash_probe(int argc, char * const argv[])
char *endp;
struct spi_flash *new;

-   if (argc<  2)
-   return -1;
-
-   cs = simple_strtoul(argv[1],&endp, 0);
-   if (*argv[1] == 0 || (*endp != 0&&  *endp != ':'))
+#ifndef CONFIG_SPI_FLASH_CS
+   if (argc<  2) {
+   printf("%s: missing arguments\n", __func__);

I think this format for the error message is a little bit untypical for
u-boot. We do not show up the internal C function name. Better would be
to show the command usage, right?



Looking at this area of the code in more detail, there are quite
a few cases where improper usage silently return -1.

I'm inclined to either follow that lead or toss them together
with a "goto usage" as done in do_spi_flash().

Any preferences?


return -1;
-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
+   }
+#else
+   cs = CONFIG_SPI_FLASH_CS ;

Other options for the spi flash subsystem are called
CONFIG_SF_DEFAULT_MODE|SPEED. It think it make sense to call
this CONFIG_SF_DEFAULT_CS and CONFIG_SF_DEFAULT_BUS (see below).



See include/configs/efikamx.h (reference to unused symbol CONFIG_SPI_FLASH_CS).


+#endif

-   bus = cs;
-   cs = simple_strtoul(endp + 1,&endp, 0);
-   if (*endp != 0)
+   if (argc>= 2) {
+   cs = simple_strtoul(argv[1],&endp, 0);
+   if (*argv[1] == 0 || (*endp != 0&&  *endp != ':'))
return -1;
+   if (*endp == ':') {
+   if (endp[1] == 0)
+   return -1;
+
+   bus = cs;
+   cs = simple_strtoul(endp + 1,&endp, 0);
+   if (*endp != 0)
+   return -1;
+   }
}

if (argc>= 3) {
@@ -299,7 +307,11 @@ usage:
  U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
+#ifndef CONFIG_SPI_FLASH_CS
"probe [bus:]cs [hz] [mode]- init flash device on given SPI 
bus\n"
+#else
+   "probe [[bus:]cs] [hz] [mode]  - init flash device on given SPI 
bus\n"
+#endif
"and chip select\n"
"sf read addr offset len   - read `len' bytes starting at\n"
"`offset' to memory at `addr'\n"

Can you also add a config option for the SPI bus number? I think these
two need to handled in the same patch.

So you could add this stuff:

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 9e97c8e..fa4312a 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -63,7 +63,11 @@ static int sf_parse_len_arg(char *arg, ulong *len)

  static int do_spi_flash_probe(int argc, char * const argv[])
  {
+#ifdef CONFIG_SF_DEFAULT_BUS
+   unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+#else
 unsigned int bus = 0;
+#endif
 unsigned int cs;
 unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
 unsigned int mode = CONFIG_SF_DEFAULT_MODE;



Can do.
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Re: [U-Boot] [PATCH V3 4/6] sf command: allow default chip select through CONFIG_SPI_FLASH_CS

[Eric Nelson]

On 01/24/2012 11:08 AM, Mike Frysinger wrote:

On Tuesday 24 January 2012 11:18:22 Eric Nelson wrote:

This patch allows a board configuration file to provide a default
chip-select for serial flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this
allows a much simpler command line:
U-Boot>  sf probe
instead of
U-Boot>  sf probe 0x5300


NAK (to this version of the patch): missing README update, and other issues
below



Which README? The only references I find to serial flash support
are in board-specific README files.

~/u-boot$ find . -iname \*readme\* | xargs grep -w sf
./doc/README.p2041rdb:  => sf erase 0 10
./doc/README.p2041rdb:  => sf write 100 0 $filesize
./doc/README.p2041rdb:  => sf erase 11 1
./doc/README.p2041rdb:  => sf write 100 11 $filesize
./doc/README.sh7757lcr:   => sf probe 0
./doc/README.sh7757lcr:   => sf erase 0 8
./doc/README.sh7757lcr:   => sf write 0x8900 0 8

I can start one of those for the SabreLite board, but that's un-related
to this patch.


--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c

+#ifndef CONFIG_SPI_FLASH_CS
+   if (argc<  2) {
+   printf("%s: missing arguments\n", __func__);
return -1;


return cmd_usage(cmdtp);


-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
+   }
+#else
+   cs = CONFIG_SPI_FLASH_CS ;
+#endif


you're setting the default CS, not locking it in.  so a better config knob name
would be something like:
CONFIG_SF_DEFAULT_CS
this matches the existing CONFIG_SF_XXX defines

also, you have a spurious space before the semicolon there


Thanks Mike,

FWIW, I chose this name on purpose to make life easier on a couple of
other boards immediately (efika and vision2):

~/u-boot$ grep CONFIG_SPI_FLASH_CS include/configs/*
include/configs/efikamx.h:#define CONFIG_SPI_FLASH_CS   (1 | 121 << 8)
include/configs/m28evk.h:#defineCONFIG_SPI_FLASH_CS 2
include/configs/mx6qsabrelite.h.rej:#define CONFIG_SPI_FLASH_CS 1
include/configs/vision2.h:#define CONFIG_SPI_FLASH_CS   (1 | (121 << 8))


  U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
+#ifndef CONFIG_SPI_FLASH_CS
"probe [bus:]cs [hz] [mode]- init flash device on given SPI 
bus\n"
+#else
+   "probe [[bus:]cs] [hz] [mode]  - init flash device on given SPI 
bus\n"
+#endif
"and chip select\n"
"sf read addr offset len   - read `len' bytes starting at\n"
"`offset' to memory at `addr'\n"


this is ugly.  i'd rather just omit it and not worry about the syntax being
perfect.


Works for me.
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[U-Boot] [PATCH V3 6/6] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Eric Nelson]

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

The SPI driver can take as chip select the controller's chip selects 
as well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number. 

The GPIO used on Sabre Lite is GP3:19 == 83.

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 include/configs/mx6qsabrelite.h |   12 +++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index e34f108..024a94c 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,20 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_CS  0x5300
+#define CONFIG_ENV_SPI_MODESPI_MODE_0
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

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[U-Boot] [PATCH V3 5/6] mx6q: mx6qsabrelite: Provide default chip-select for serial flash

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
Acked-by: Stefano Babic 
---
 include/configs/mx6qsabrelite.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8dd6e39..e34f108 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,6 +46,7 @@
 
 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_CS 0x5300
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
-- 
1.7.1

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[U-Boot] [PATCH V3 3/6] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
Acked-by: Stefano Babic 
---
 board/freescale/mx6qsabrelite/imximage.cfg|2 +-
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +
 include/configs/mx6qsabrelite.h   |9 +
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/imximage.cfg 
b/board/freescale/mx6qsabrelite/imximage.cfg
index b4ff010..fa40bff 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF0
 DATA 4 0x020c4078 0x00FFF300
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a0b648f..2ba6b0c 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |\
+   PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+   /* SS1 */
+   MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+   gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+   imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL 0x9
 #define MII_EXTENDED_CTRL  0xb
 #define MII_EXTENDED_DATAW 0xc
@@ -250,6 +271,10 @@ int board_early_init_f(void)
 {
setup_iomux_uart();
 
+#ifdef CONFIG_MXC_SPI
+   setup_spi();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 034fc40..8dd6e39 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,15 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
1.7.1

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[U-Boot] [PATCH V3 4/6] sf command: allow default chip select through CONFIG_SPI_FLASH_CS

[Eric Nelson]

This patch allows a board configuration file to provide a default 
chip-select for serial flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this allows 
a much simpler command line:
U-Boot> sf probe
instead of
U-Boot> sf probe 0x5300

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
Acked-by: Stefano Babic 
---
 common/cmd_sf.c |   34 +++---
 1 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 7225656..4b32171 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -70,20 +70,28 @@ static int do_spi_flash_probe(int argc, char * const argv[])
char *endp;
struct spi_flash *new;
 
-   if (argc < 2)
-   return -1;
-
-   cs = simple_strtoul(argv[1], &endp, 0);
-   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
+#ifndef CONFIG_SPI_FLASH_CS
+   if (argc < 2) {
+   printf("%s: missing arguments\n", __func__);
return -1;
-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
+   }
+#else
+   cs = CONFIG_SPI_FLASH_CS ;
+#endif
 
-   bus = cs;
-   cs = simple_strtoul(endp + 1, &endp, 0);
-   if (*endp != 0)
+   if (argc >= 2) {
+   cs = simple_strtoul(argv[1], &endp, 0);
+   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
return -1;
+   if (*endp == ':') {
+   if (endp[1] == 0)
+   return -1;
+
+   bus = cs;
+   cs = simple_strtoul(endp + 1, &endp, 0);
+   if (*endp != 0)
+   return -1;
+   }
}
 
if (argc >= 3) {
@@ -299,7 +307,11 @@ usage:
 U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
+#ifndef CONFIG_SPI_FLASH_CS
"probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
+#else
+   "probe [[bus:]cs] [hz] [mode]   - init flash device on given SPI bus\n"
+#endif
" and chip select\n"
"sf read addr offset len- read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
-- 
1.7.1

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[U-Boot] [PATCH V3 0/6] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in 
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Patch 4 modifies the 'sf' command to allow a default chip-select
to be specified by board headers as is done on efika et al. This allows
a bare 'sf' probe command:
 U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed  
to specify GP3:19 on SabreLite:
 U-Boot> sf probe 0x5300   

Patch 5 adds default chip-select values for mx6qsabrelite platform.

Patch 6 adds reference macros for use in storing the environment
in serial flash to match the use on Freescale's U-Boot release

This patch set has been compiled against the following configurations,
but only tested on mx6qsabrelite:
mx6qsabrelite
mx51evk
mx31pdk
mx35pdk

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[U-Boot] [PATCH V3 2/6] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |   44 ++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7650cb9..00040c4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -190,6 +190,50 @@ struct src {
u32 gpr10;
 };
 
+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   ECSPI1_BASE_ADDR, \
+   ECSPI2_BASE_ADDR, \
+   ECSPI3_BASE_ADDR, \
+   ECSPI4_BASE_ADDR, \
+   ECSPI5_BASE_ADDR
+
 struct iim_regs {
u32 ctrl;
u32 ctrl_set;
-- 
1.7.1

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[U-Boot] [PATCH V3 1/6] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

Move (E)CSPI register declarations into the imx-regs.h files for each supported 
CPU

Introduce two new macros to control conditional setup
 MXC_CSPI - Used for processors with the Configurable Serial Peripheral 
Interface (MX3x)
 MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
Acked-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx31/imx-regs.h |   27 
 arch/arm/include/asm/arch-mx35/imx-regs.h |   25 
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +
 drivers/spi/mxc_spi.c |   93 ++---
 4 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h 
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6a517dd..70e3338 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -890,4 +890,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN(1 << 8)
 #define MXC_EHCI_IPPUE_UP  (1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001, \
+   0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h 
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
 #define IPU_CONF_IC_EN (1<<1)
 #define IPU_CONF_SCI_EN(1<<0)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001,
+
 #define GPIO_PORT_NUM  3
 #define GPIO_NUM_PIN   32
 
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M3
 
 /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   CSPI1_BASE_ADDR, \
+   CSPI2_BASE_ADDR, \
+   CSPI3_BASE_ADDR,
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN 

Re: [U-Boot] [PATCH V2 0/6] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

On 01/23/2012 10:51 AM, Fabio Estevam wrote:



>  Patch 4 modifies the 'sf' command to allow a default chip-select
>  to be specified by board headers as is done on efika et al. This allows
>  a bare 'sf' probe command:
>U-Boot>  sf probe
>  instead of the more cumbersome usage when a GPIO is tacked onto
>  the chip-select. Otherwise, this command-line would be needed
>  to specify GP3:19 on SabreLite:
>U-Boot>  sf probe 0x5300

I think this comment is very useful and it would be nice to have it in
the commit log of the patch.



Works for me.

Any other requests before V3?
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[U-Boot] [PATCH V2 2/6] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |   44 ++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7650cb9..00040c4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -190,6 +190,50 @@ struct src {
u32 gpr10;
 };
 
+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   ECSPI1_BASE_ADDR, \
+   ECSPI2_BASE_ADDR, \
+   ECSPI3_BASE_ADDR, \
+   ECSPI4_BASE_ADDR, \
+   ECSPI5_BASE_ADDR
+
 struct iim_regs {
u32 ctrl;
u32 ctrl_set;
-- 
1.7.1

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[U-Boot] [PATCH V2 6/6] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Eric Nelson]

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

The SPI driver can take as chip select the controller's chip selects 
as well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number. 

The GPIO used on Sabre Lite is GP3:19 == 83.

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 include/configs/mx6qsabrelite.h |   12 +++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index e34f108..024a94c 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,20 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_CS  0x5300
+#define CONFIG_ENV_SPI_MODESPI_MODE_0
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

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[U-Boot] [PATCH V2 5/6] mx6q: mx6qsabrelite: Provide default chip-select for serial flash

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 include/configs/mx6qsabrelite.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8dd6e39..e34f108 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,6 +46,7 @@
 
 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_CS 0x5300
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
-- 
1.7.1

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[U-Boot] [PATCH V2 3/6] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 board/freescale/mx6qsabrelite/imximage.cfg|2 +-
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +
 include/configs/mx6qsabrelite.h   |9 +
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/imximage.cfg 
b/board/freescale/mx6qsabrelite/imximage.cfg
index b4ff010..fa40bff 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF0
 DATA 4 0x020c4078 0x00FFF300
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a0b648f..2ba6b0c 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |\
+   PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+   /* SS1 */
+   MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+   MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+   gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+   imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL 0x9
 #define MII_EXTENDED_CTRL  0xb
 #define MII_EXTENDED_DATAW 0xc
@@ -250,6 +271,10 @@ int board_early_init_f(void)
 {
setup_iomux_uart();
 
+#ifdef CONFIG_MXC_SPI
+   setup_spi();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 034fc40..8dd6e39 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,15 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE   UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
1.7.1

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[U-Boot] [PATCH V2 4/6] sf command: allow default chip select through CONFIG_SPI_FLASH_CS

[Eric Nelson]

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 common/cmd_sf.c |   34 +++---
 1 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 7225656..4b32171 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -70,20 +70,28 @@ static int do_spi_flash_probe(int argc, char * const argv[])
char *endp;
struct spi_flash *new;
 
-   if (argc < 2)
-   return -1;
-
-   cs = simple_strtoul(argv[1], &endp, 0);
-   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
+#ifndef CONFIG_SPI_FLASH_CS
+   if (argc < 2) {
+   printf("%s: missing arguments\n", __func__);
return -1;
-   if (*endp == ':') {
-   if (endp[1] == 0)
-   return -1;
+   }
+#else
+   cs = CONFIG_SPI_FLASH_CS ;
+#endif
 
-   bus = cs;
-   cs = simple_strtoul(endp + 1, &endp, 0);
-   if (*endp != 0)
+   if (argc >= 2) {
+   cs = simple_strtoul(argv[1], &endp, 0);
+   if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
return -1;
+   if (*endp == ':') {
+   if (endp[1] == 0)
+   return -1;
+
+   bus = cs;
+   cs = simple_strtoul(endp + 1, &endp, 0);
+   if (*endp != 0)
+   return -1;
+   }
}
 
if (argc >= 3) {
@@ -299,7 +307,11 @@ usage:
 U_BOOT_CMD(
sf, 5,  1,  do_spi_flash,
"SPI flash sub-system",
+#ifndef CONFIG_SPI_FLASH_CS
"probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
+#else
+   "probe [[bus:]cs] [hz] [mode]   - init flash device on given SPI bus\n"
+#endif
" and chip select\n"
"sf read addr offset len- read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
-- 
1.7.1

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[U-Boot] [PATCH V2 0/6] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in 
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Patch 4 modifies the 'sf' command to allow a default chip-select
to be specified by board headers as is done on efika et al. This allows
a bare 'sf' probe command:
 U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed  
to specify GP3:19 on SabreLite:
 U-Boot> sf probe 0x5300   

Patch 5 adds default chip-select values for mx6qsabrelite platform.

Patch 6 adds reference macros for use in storing the environment
in serial flash to match the use on Freescale's U-Boot release

This patch set has been compiled against the following configurations,
but only tested on mx6qsabrelite:
mx6qsabrelite
mx51evk
mx31pdk
mx35pdk

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[U-Boot] [PATCH V2 1/6] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

Move (E)CSPI register declarations into the imx-regs.h files for each supported 
CPU

Introduce two new macros to control conditional setup
 MXC_CSPI - Used for processors with the Configurable Serial Peripheral 
Interface (MX3x)
 MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson 
Acked-by: Dirk Behme  
---
 arch/arm/include/asm/arch-mx31/imx-regs.h |   27 
 arch/arm/include/asm/arch-mx35/imx-regs.h |   25 
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +
 drivers/spi/mxc_spi.c |   93 ++---
 4 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h 
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6a517dd..70e3338 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -890,4 +890,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN(1 << 8)
 #define MXC_EHCI_IPPUE_UP  (1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001, \
+   0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h 
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
 #define IPU_CONF_IC_EN (1<<1)
 #define IPU_CONF_SCI_EN(1<<0)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_SMC   (1 << 3)
+#define MXC_CSPICTRL_POL   (1 << 4)
+#define MXC_CSPICTRL_PHA   (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)   (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+   0x43fa4000, \
+   0x5001,
+
 #define GPIO_PORT_NUM  3
 #define GPIO_NUM_PIN   32
 
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M3
 
 /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE  (1 << 1)
+#define MXC_CSPICTRL_XCH   (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)   (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN  18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL  12
+#define MXC_SPI_BASE_ADDRESSES \
+   CSPI1_BASE_ADDR, \
+   CSPI2_BASE_ADDR, \
+   CSPI3_BASE_ADDR,
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN32
diff --git a/driver

Re: [U-Boot] mx6qsabrelite U-Boot from SPI-NOR

[Eric Nelson]

On 01/20/2012 02:15 AM, Wolfgang Grandegger wrote:


On 01/20/2012 01:56 AM, Eric Nelson wrote:


Yes. If you program u-boot.imx to offset 0x400, it will boot.

I just did so as shown below.

I started by placing SW1 in the 01 position (boot to USB), and
used imx_usb to dowload u-boot.imx:

 MX6QSABRELITE U-Boot>  dhcp 1080 192.168.0.112:u-boot.imx
 fec_open:Speed=100
 BOOTP broadcast 1
 BOOTP broadcast 2
 DHCP client bound to address 29.6.1.24
 Using FEC device
 TFTP from server 192.168.0.112; our IP address is 29.6.1.24;
 sending  through gateway 29.6.1.1
 Filename 'u-boot.imx'.
 Load address: 0x1080
 Loading: #
 done
 Bytes transferred = 207112 (32908 hex)
 MX6QSABRELITE U-Boot>  sf write 0x1080 0x400 $filesize


But above you used the network to load u-boot.imx. With imx_usb you
loaded and booted an image via USB first, I assume.



Yeah. USB to execute U-Boot, then Ethernet to get a pristine
image into RAM for programming.

I'd love to get USB support for MX6Q into U-Boot, but that's another
project...
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Re: [U-Boot] [PATCH 6/6] mx6q: mx6qsabrelite: Provide defaults for placing environment in serial flash

[Eric Nelson]

On 01/20/2012 01:47 AM, Stefano Babic wrote:

On 20/01/2012 08:48, Jason Hui wrote:



I'm wondering how the CONFIG_ENV_SPI_CS  could be 0x5300? Vague?


Then the left open question is only above one.


The SPI driver can take as chip select the controller's chip selects as
well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number. Reading this configuration, the GPIO used on this board should
be the number 83 (0x53).

Stefano


Thanks Stefano,

I like your description better than the one I just wrote... I should
have scanned all of my e-mails before drafting my earlier commit msg ;)
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Re: [U-Boot] [PATCH 6/6] mx6q: mx6qsabrelite: Provide defaults for placing environment in serial flash

[Eric Nelson]

On 01/19/2012 08:27 PM, Jason Hui wrote:

On Wed, Jan 18, 2012 at 6:09 AM, Eric Nelson
  wrote:

Signed-off-by: Eric Nelson
---
  include/configs/mx6qsabrelite.h |   12 +++-
  1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 44b028a..160894c 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,20 @@
  /* FLASH and environment organization */
  #define CONFIG_SYS_NO_FLASH

-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
  #define CONFIG_ENV_SIZE(8 * 1024)
+
  #define CONFIG_ENV_IS_IN_MMC
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */


From the commit log, it says the default is in serial flash, but
apparently in the code the env is default to MMC, which mismatch.

> please fix it.




You're asking that I change the comment not the default, right?


+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
  #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_CS  0x5300


I'm wondering how the CONFIG_ENV_SPI_CS  could be 0x5300? Vague?



Please review the updated patch below and see whether the
expanded commit message fixes things.

Regards,


Eric
commit 0443433bf80c5203a8ce67fb4faaf4032e398e1d
Author: Eric Nelson 
Date:   Tue Jan 17 14:11:54 2012 -0700

mx6q: mx6qsabrelite: Provide macros for environment in serial flash

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

Note that the mxc_spi driver (drivers/spi/mxc_spi.c) uses the
Chip-Select variable (CONFIG_ENV_SPI_CS) to allow the use of
a GPIO if the chip-select is greater than 3. The low 8-bits
set the chip select number and bits 8-15 set the GPIO number.

The GPIO used on Sabre Lite is GP3:19 == 83.

Signed-off-by: Eric Nelson 

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index e34f108..024a94c 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,20 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH

-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_CS  (0|(83<<8))
+#define CONFIG_ENV_SPI_MODESPI_MODE_0
+#endif

 #define CONFIG_OF_LIBFDT

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Re: [U-Boot] mx6qsabrelite U-Boot from SPI-NOR

[Eric Nelson]

Hi Wolfgang,

On 01/19/2012 03:26 AM, Dirk Behme wrote:

Dear Wolfgang,

On 19.01.2012 10:58, Wolfgang Grandegger wrote:


Where can I find the "SPI_to_SD_loader.bin" image?


Unfortunately, at the moment you have to ask your Freescale contact for this. We
ping Freescale since weeks for this. Last time I heard about this Freescale
planned to release this binary under a BSD license. They are still "working
through the licensing details", though :(


What means early
version of SabreLite boards?


Most probably Eric will be able to better answer this.



At this point **all** versions of SabreLite are configured to boot to SPI
NOR through the fuses.

As Dirk mentioned, we've had some conversations about booting to SD card,
but once the fuse is blown, it's blown.


What I understood: Up to now, the boards boot from SPI NOR by default. There was
some _discussion_ to change this to SD boot. Most probably "early version" was
written while this discussion under the impression that later boards might
switch to SD boot. To my understanding the result of this discussion was that
this change would be difficult, though.



We've discussed, but currently have no plans to support a physical switch
to control this decision. This would involve using the "Internal" boot mode
position of SW1 and then pulling a **bunch** of pins high or low to control
the boot flow.

Note that all of the pins are available on connector J12 (BOOT/EIM), so it
might be done with a small daughter-board.


How can I select boot from SD-Card on newer versions?


To my understanding there are no "newer versions" yet.



Right.


And will the u-boot.imx image also boot when loaded
to the SPI-NOR fash?


Hmm, I'm not sure about this as I haven't tested this.

Eric?



Yes. If you program u-boot.imx to offset 0x400, it will boot.

I just did so as shown below.

I started by placing SW1 in the 01 position (boot to USB), and
used imx_usb to dowload u-boot.imx:

MX6QSABRELITE U-Boot > dhcp 1080 192.168.0.112:u-boot.imx
fec_open:Speed=100
BOOTP broadcast 1
BOOTP broadcast 2
DHCP client bound to address 29.6.1.24
Using FEC device
	TFTP from server 192.168.0.112; our IP address is 29.6.1.24; sending 	through 
gateway 29.6.1.1

Filename 'u-boot.imx'.
Load address: 0x1080
Loading: #
done
Bytes transferred = 207112 (32908 hex)
MX6QSABRELITE U-Boot > sf write 0x1080 0x400 $filesize



U-Boot 2011.12-00048-g5c30101 (Jan 19 2012 - 17:14:32)
CPU:   Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: POR
Board: MX6Q-Sabre Lite
DRAM:  1 GiB
WARNING: Caches not enabled
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
MMC init failed
Using default environment

In:serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0
MX6QSABRELITE U-Boot >
MX6QSABRELITE U-Boot >

The imx_usb utility is available here:
http://boundarydevices.com/git?p=imx_usb_loader.git

It requires libusb-1.0-0-dev to build, but has few other dependencies.

Usage is simple: hand it the file you want to execute. It will look
at the header to find out where to place the image.
~/imx_usb_loader$ sudo sudo ./imx_usb u-boot.imx

> Please note that Eric is in the process of mainlining the SPI driver for
> i.MX6, atm.

If you use my latest patch set, you can place the environment in SPI-NOR as
well by commenting out CONFIG_ENV_IS_IN_MMC, and un-commenting ..._IN_SPI_FLASH
in include/configs/mx6qsabrelite.h.

Regards,


Eric
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Re: [U-Boot] [PATCH 2/6] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

On 01/18/2012 01:39 AM, Stefano Babic wrote:

On 18/01/2012 02:44, Eric Nelson wrote:

I'll defer to Stefano on this one, since I did this in response
to his request:


Yes, I admit I am guilty about this !

The layout of the CSPI registers is not exactly the same for all SOCs.
For example, the MXC_CSPICTRL_TC has a different position, as well as
the BITCOUNT (because the MX31 can send less bits in one shot) and
MXC_CSPICTRL_CHIPSELECT.

So they are similar, but not exactly the same.

Then we have the MX5 registers. Even if we check the CSPI (not eCSPI)
controller, the layout of the registers is different compared to the MX3
SOCs.


The struct cspi_regs is already present in mx31, mx35, and mx51 headers,
so I'm not breaking new ground here, only in the bitfield declarations.


Right, I see the same. The cspi_regs structure is already defined into
the imx_regs.h, only the bit layout was moved. And as the bit layout is
SOC dependent, I think the right place for it is inside the imx-regs.h
registers.


My interpretation of Stefano's intent is to clean up the driver at the
expense of extra defines in the arch-specific headers.


Yes, you're right - of course, I am open also to other solutions if they
are proofed to be better ;-).



I think this is about as good as things get with the current code base.
I would argue that the driver would be better if it explicitly supported
ECSPI and CSPI at the same time since the mx5x CPUs support it.

Implememting that would likely require a de-structuring (removing the
use of structs to represent the register set). IOW, a re-write.

That's probably not worth the effort unless someone's built hardware
that needs it (I'm not aware of any).

On our boards that use more than one channel of SPI (for PMIC and SF), we're 
using ECSPI on both. I think the same was true on the MX51 EVK.

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Re: [U-Boot] [PATCH 2/6] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

On 01/17/2012 06:47 PM, Marek Vasut wrote:

On 01/17/2012 06:27 PM, Marek Vasut wrote:

I'll defer to Stefano on this one, since I did this in response
to his request:

>>

Right - and we already discussed in the past how to avoid to put
specific SOC code inside the driver. In fact, the cspi_regs structure
was already moved into the specific SOC header (imx-regs.h) - but the
definitions of the single bits of the registers are still inside the
driver, as well as the base address of the (e)cspi controllers.

They should also be moved - take into acoount by implementing your
changes for i.mx6


The struct cspi_regs is already present in mx31, mx35, and mx51 headers,
so I'm not breaking new ground here, only in the bitfield declarations.

>> 


My interpretation of Stefano's intent is to clean up the driver at the
expense of extra defines in the arch-specific headers.


But they're all the same, right? So we have now the same structure defined
thrice?



Almost, but not quite: mx31 and mx35 both use the CSPI peripheral and have
one layout. mx5 and mx6 have the ECSPI peripheral, which has an extra
register "cfg" to control the polarity and phase of the signals.

Actually, that comment is wrong. The MX51 and MX53 have **both** CSPI and
ECSPI peripherals, but the existing code in mxc_spi only supports ECSPI.

The bitfields that my patches move into the imx-regs.h files are also
almost identical.
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Re: [U-Boot] [PATCH 2/6] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

On 01/17/2012 06:27 PM, Marek Vasut wrote:

On 01/17/2012 04:19 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};


Sigh ... it's no fun I can have only one remark :-)

Is this part common for all imx-es ?


All i.MX6's

This is a cut&  paste from MX51.

I was tempted to introduce an 'mxc_ecspi.h' to merge the declaration
for i.MX5x and i.MX6 which share the ECSPI peripheral and 'mxc_cspi.h'
for i.MX31 and i.MX35 that share the CSPI peripheral.


But you don't even need this outside of the spi driver so just put it into the
spi driver and be done with it. That'll solve your duplication issue.

M



I'll defer to Stefano on this one, since I did this in response
to his request:


Right - and we already discussed in the past how to avoid to put
specific SOC code inside the driver. In fact, the cspi_regs structure
was already moved into the specific SOC header (imx-regs.h) - but the
definitions of the single bits of the registers are still inside the
driver, as well as the base address of the (e)cspi controllers.

They should also be moved - take into acoount by implementing your
changes for i.mx6


The struct cspi_regs is already present in mx31, mx35, and mx51 headers,
so I'm not breaking new ground here, only in the bitfield declarations.


http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-mx31/imx-regs.h;h=6a517ddd931ca0d1e598bd7456c4c611741602eb;hb=HEAD#l60

http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-mx35/imx-regs.h;h=df74508a93ee87ae986f7c2f48f6c5fb36626070;hb=HEAD#l279

http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-mx5/imx-regs.h;h=0ee88d25b7800ae9e6aed809d02dd19d9cac9c82;hb=HEAD#l423

My interpretation of Stefano's intent is to clean up the driver at the expense
of extra defines in the arch-specific headers.

Regards,


Eric
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Re: [U-Boot] [PATCH 2/6] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

On 01/17/2012 04:19 PM, Marek Vasut wrote:

Signed-off-by: Eric Nelson
---
  arch/arm/include/asm/arch-mx6/imx-regs.h |   44
++ 1 files changed, 44 insertions(+), 0
deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7650cb9..00040c4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -190,6 +190,50 @@ struct src {
u32 gpr10;
  };

+/* ECSPI registers */
+struct cspi_regs {
+   u32 rxdata;
+   u32 txdata;
+   u32 ctrl;
+   u32 cfg;
+   u32 intr;
+   u32 dma;
+   u32 stat;
+   u32 period;
+};


Sigh ... it's no fun I can have only one remark :-)

Is this part common for all imx-es ?



All i.MX6's

This is a cut & paste from MX51.

I was tempted to introduce an 'mxc_ecspi.h' to merge the declaration
for i.MX5x and i.MX6 which share the ECSPI peripheral and 'mxc_cspi.h'
for i.MX31 and i.MX35 that share the CSPI peripheral.

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[U-Boot] [PATCH 5/6] mx6q: mx6qsabrelite: Provide default chip-select for serial flash

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 include/configs/mx6qsabrelite.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 8dd6e39..44b028a 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -46,6 +46,7 @@
 
 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_CS 0x5300
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
-- 
1.7.1

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[U-Boot] [PATCH 6/6] mx6q: mx6qsabrelite: Provide defaults for placing environment in serial flash

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 include/configs/mx6qsabrelite.h |   12 +++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 44b028a..160894c 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,20 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_ENV_SIZE(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET  (6 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET  (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE   (8 * 1024)
+#define CONFIG_ENV_SPI_CS  0x5300
+#define CONFIG_ENV_SPI_MODESPI_MODE_0
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

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[U-Boot] mxc_spi refactoring (for mx6q)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in 
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Patch 4 modifies the 'sf' command to allow a default chip-select
to be specified by board headers as is done on efika et al. This allows
a bare 'sf' probe command:
 U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed  
to specify GP3:19 on SabreLite:
 U-Boot> sf probe 0x5300   

Patch 5 adds default chip-select values for mx6qsabrelite platform.

Patch 6 adds reference macros for use in storing the environment
in serial flash to match the use on Freescale's U-Boot release

This patch set has been compiled against the following configurations,
but only tested on mx6qsabrelite:
mx6qsabrelite
mx51evk
mx31pdk
mx35pdk

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