from:"FUKAUMI Naoki"

[PATCH 3/3] configs: rockchip: enable RK806 SPI PMIC for Radxa ROCK 5B

2024-10-30 Thread FUKAUMI Naoki

enable RK806 SPI PMIC driver and related cmd/configs for Radxa ROCK 5B.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock5b-rk3588_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 47ee2109f8e..cf10965cf0f 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -44,6 +44,7 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_ROCKUSB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
@@ -78,6 +79,10 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_SCSI=y
@@ -85,6 +90,7 @@ CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SFC=y
+CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.43.0

[PATCH 1/3] configs: rockchip: enable RK806 SPI PMIC for Radxa ROCK 5A

2024-10-30 Thread FUKAUMI Naoki

enable RK806 SPI PMIC driver and related cmd/configs for Radxa ROCK 5A.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock5a-rk3588s_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index 9618d590009..d2770198ef2 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -28,6 +28,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
@@ -55,11 +56,16 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.43.0

[PATCH 2/3] configs: rockchip: run savedefconfig for TCPM related configs for Radxa ROCK 5B

2024-10-30 Thread FUKAUMI Naoki

run savedefconfig for next patch for Radxa ROCK 5B.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock5b-rk3588_defconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index c54e13e8732..47ee2109f8e 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -34,6 +34,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
+CONFIG_CMD_TCPM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -94,6 +95,8 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_FUSB302=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
@@ -106,6 +109,3 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
-CONFIG_TYPEC_TCPM=y
-CONFIG_TYPEC_FUSB302=y
-CONFIG_CMD_TCPM=y
-- 
2.43.0

Re: [PATCH v2 2/2] rockchip: add support for Radxa ROCK 5A with SPI NOR flash module

2024-10-30 Thread FUKAUMI Naoki


Hi,

On 10/30/24 19:39, Quentin Schulz wrote:

Hi Naoki,

On 10/30/24 4:09 AM, FUKAUMI Naoki wrote:

Hi,

could you review this patch, anyone?

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/25/24 07:33, FUKAUMI Naoki wrote:

on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins
(i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts
specifically for SPI NOR flash is required.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2
- fix subject
---
  arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 24 ++
  arch/arm/dts/rk3588s-rock-5a-spi.dts |  4 +
  board/radxa/rock5a-rk3588s/MAINTAINERS   |  5 +-
  configs/rock5a-spi-rk3588s_defconfig | 83 
  4 files changed, 113 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts
  create mode 100644 configs/rock5a-spi-rk3588s_defconfig

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi b/arch/arm/ 
dts/rk3588s-rock-5a-spi-u-boot.dtsi

new file mode 100644
index 000..5cd131d3cb1
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+&fspim0_pins {
+    bootph-pre-ram;
+    bootph-some-ram;
+};
+
+&sdhci {
+    status = "disabled";
+};
+
+&sfc {
+    status = "okay";
+
+    flash@0 {
+    bootph-pre-ram;
+    bootph-some-ram;
+    };
+};


I assume the board can only be fitted with an SPI NOR or an eMMC and not 
both at the same time? If that's the case, then the status = disabled 
and status = okay should be in the dts. I assume we want this to be in 
the Linux kernel first too, either as a separate DTS or with a DTSO (not 
sure what they will want).


maybe it's time to update this patch.

https://patchwork.kernel.org/project/linux-rockchip/patch/20230913064505.77393-2-na...@radxa.com/

rock-5a-base.dtsi (common part)
rock-5a.dts (same as current one)
rock-5a-spi-dts

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts b/arch/arm/dts/ 
rk3588s-rock-5a-spi.dts

new file mode 100644
index 000..780e90d041b
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588s-rock-5a.dts"
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/ 
rock5a-rk3588s/MAINTAINERS

index a569efa74e3..06ebc9829f4 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -4,6 +4,5 @@ R:    Jonas Karlman 
  S:    Maintained
  F:    board/radxa/rock5a-rk3588s
  F:    include/configs/rock5a-rk3588s.h
-F:    configs/rock5a-rk3588s_defconfig
-F:    arch/arm/dts/rk3588s-rock-5a.dts
-F:    arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F:    configs/rock5a*
+F:    arch/arm/dts/rk3588s-rock-5a*
diff --git a/configs/rock5a-spi-rk3588s_defconfig b/configs/rock5a- 
spi-rk3588s_defconfig

new file mode 100644
index 000..297278c7a06
--- /dev/null
+++ b/configs/rock5a-spi-rk3588s_defconfig


If Radxa starts having many such options, maybe it won't make a lot of 
sense to duplicate configs but rather have config fragments to change 
the default DT and add a few symbols that differ from the base (I assume 
we may have something similar needed for rock 5b+ compared to rock5b for 
example?


I'm thinking doing same for ROCK 5C...

https://github.com/RadxaNaoki/u-boot/commits/rock-5c/

Keeping all configs in sync for essentially same board with small 
differences may be difficult, maybe using config fragments will help?


any "config fragments" doc/example?

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFI

Re: [PATCH v3] rockchip: add support for Radxa ROCK 5A with SPI NOR flash module

2024-10-30 Thread FUKAUMI Naoki


Hi,

On 10/30/24 23:24, Eugen Hristev wrote:



On 10/30/24 08:30, Kever Yang wrote:

Hi Naoki,

On 2024/10/30 14:07, FUKAUMI Naoki wrote:

on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins
(i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts
specifically for SPI NOR flash is required.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v3
- drop first patch
- fix copyright
- run savedefconfig
- sync with changes for LED for Radxa boards
- add more SPI NOR flash chips
Changes in v2
- fix subject
---
  arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 32 +++
  arch/arm/dts/rk3588s-rock-5a-spi.dts |  4 +
  board/radxa/rock5a-rk3588s/MAINTAINERS   |  5 +-
  configs/rock5a-spi-rk3588s_defconfig | 87 
  4 files changed, 125 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts
  create mode 100644 configs/rock5a-spi-rk3588s_defconfig

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi b/arch/arm/ 
dts/rk3588s-rock-5a-spi-u-boot.dtsi

new file mode 100644
index 000..7723931d869
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+    leds {
+    io-led {
+    default-state = "on";
+    };
+    };
+};
+
+&fspim0_pins {
+    bootph-pre-ram;
+    bootph-some-ram;
+};
+
+&sdhci {
+    status = "disabled";
+};
+
+&sfc {
+    status = "okay";
+
+    flash@0 {
+    bootph-pre-ram;
+    bootph-some-ram;
+    };
+};
diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts b/arch/arm/dts/ 
rk3588s-rock-5a-spi.dts

new file mode 100644
index 000..780e90d041b
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588s-rock-5a.dts"
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/ 
rock5a-rk3588s/MAINTAINERS

index a569efa74e3..06ebc9829f4 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -4,6 +4,5 @@ R:    Jonas Karlman 
  S:    Maintained
  F:    board/radxa/rock5a-rk3588s
  F:    include/configs/rock5a-rk3588s.h
-F:    configs/rock5a-rk3588s_defconfig
-F:    arch/arm/dts/rk3588s-rock-5a.dts
-F:    arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F:    configs/rock5a*
+F:    arch/arm/dts/rk3588s-rock-5a*
diff --git a/configs/rock5a-spi-rk3588s_defconfig b/configs/rock5a- 
spi-rk3588s_defconfig

new file mode 100644
index 000..d6409a12a56
--- /dev/null
+++ b/configs/rock5a-spi-rk3588s_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y

MMC should removed


The eMMC is disabled, but this board has an SD-Card right ?


yes, it has microSD slot. I'll remove eMMC things.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned- 
clocks assigned-clock-rates assigned-clock-parents"

+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y


MMC relate driver should removed


Thanks,
- Kever

+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONF

[PATCH v3] rockchip: add support for Radxa ROCK 5A with SPI NOR flash module

2024-10-29 Thread FUKAUMI Naoki

on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins
(i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts
specifically for SPI NOR flash is required.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v3
- drop first patch
- fix copyright
- run savedefconfig
- sync with changes for LED for Radxa boards
- add more SPI NOR flash chips
Changes in v2
- fix subject
---
 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 32 +++
 arch/arm/dts/rk3588s-rock-5a-spi.dts |  4 +
 board/radxa/rock5a-rk3588s/MAINTAINERS   |  5 +-
 configs/rock5a-spi-rk3588s_defconfig | 87 
 4 files changed, 125 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts
 create mode 100644 configs/rock5a-spi-rk3588s_defconfig

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi 
b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
new file mode 100644
index 000..7723931d869
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   leds {
+   io-led {
+   default-state = "on";
+   };
+   };
+};
+
+&fspim0_pins {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+&sdhci {
+   status = "disabled";
+};
+
+&sfc {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts 
b/arch/arm/dts/rk3588s-rock-5a-spi.dts
new file mode 100644
index 000..780e90d041b
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588s-rock-5a.dts"
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS 
b/board/radxa/rock5a-rk3588s/MAINTAINERS
index a569efa74e3..06ebc9829f4 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -4,6 +4,5 @@ R:  Jonas Karlman 
 S: Maintained
 F: board/radxa/rock5a-rk3588s
 F: include/configs/rock5a-rk3588s.h
-F: configs/rock5a-rk3588s_defconfig
-F: arch/arm/dts/rk3588s-rock-5a.dts
-F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F: configs/rock5a*
+F: arch/arm/dts/rk3588s-rock-5a*
diff --git a/configs/rock5a-spi-rk3588s_defconfig 
b/configs/rock5a-spi-rk3588s_defconfig
new file mode 100644
index 000..d6409a12a56
--- /dev/null
+++ b/configs/rock5a-spi-rk3588s_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG

Re: [PATCH v2 2/2] rockchip: add support for Radxa ROCK 5A with SPI NOR flash module

2024-10-29 Thread FUKAUMI Naoki


Hi,

could you review this patch, anyone?

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/25/24 07:33, FUKAUMI Naoki wrote:

on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins
(i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts
specifically for SPI NOR flash is required.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2
- fix subject
---
  arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 24 ++
  arch/arm/dts/rk3588s-rock-5a-spi.dts |  4 +
  board/radxa/rock5a-rk3588s/MAINTAINERS   |  5 +-
  configs/rock5a-spi-rk3588s_defconfig | 83 
  4 files changed, 113 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts
  create mode 100644 configs/rock5a-spi-rk3588s_defconfig

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi 
b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
new file mode 100644
index 000..5cd131d3cb1
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+&fspim0_pins {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+&sdhci {
+   status = "disabled";
+};
+
+&sfc {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts 
b/arch/arm/dts/rk3588s-rock-5a-spi.dts
new file mode 100644
index 000..780e90d041b
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588s-rock-5a.dts"
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS 
b/board/radxa/rock5a-rk3588s/MAINTAINERS
index a569efa74e3..06ebc9829f4 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -4,6 +4,5 @@ R:  Jonas Karlman 
  S:Maintained
  F:board/radxa/rock5a-rk3588s
  F:include/configs/rock5a-rk3588s.h
-F: configs/rock5a-rk3588s_defconfig
-F: arch/arm/dts/rk3588s-rock-5a.dts
-F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F: configs/rock5a*
+F: arch/arm/dts/rk3588s-rock-5a*
diff --git a/configs/rock5a-spi-rk3588s_defconfig 
b/configs/rock5a-spi-rk3588s_defconfig
new file mode 100644
index 000..297278c7a06
--- /dev/null
+++ b/configs/rock5a-spi-rk3588s_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y

Re: [PATCH v2 1/2] arm64: dts: rockchip: add (but disabled) SFC node for Radxa ROCK 5A

2024-10-29 Thread FUKAUMI Naoki


Hi,

dts/upstream/src/ inclues this change now, please ignore this patch.

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/25/24 07:33, FUKAUMI Naoki wrote:

This commit adds SFC node for Radxa ROCK 5A.

since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot
be enabled both nodes at the same time. so status = "okay" is omitted
here.

you may be able to enable sfc (and disable sdhci) by fdt overlay.

SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.

Signed-off-by: FUKAUMI Naoki 
Link: https://lore.kernel.org/r/20240623023329.1044-2-na...@radxa.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 00224650dd45e166ea6eb1593f5f064583963ccf ]

(cherry picked from commit fde218de3133705f3f56dc8eb26baa878f0e0dc9)
---
Changes in v2
- none
---
  dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts | 13 +
  1 file changed, 13 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts 
b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 3b9a349362d..2e2f7f0e769 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -377,6 +377,19 @@
status = "okay";
  };
  
+&sfc {

+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim0_pins>;
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <10400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  &spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;

Re: [PATCH v2] rockchip: add SPI NOR flash support for Radxa E25(CM3I)

2024-09-10 Thread FUKAUMI Naoki


hi,

On 9/10/24 19:03, Kever Yang wrote:

Hi Naoki,

     Since you have send the patch to mainline kernel, pls update this 
with the dts from dts/upstream when available,


so that we can keep the dts sync with mainline kernel.


oh...? I forgot to send the patch to mainline kernel...?
anyway, I'll do what I should do ;)

thanks.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


Thanks,

- Kever

On 2024/8/25 06:08, FUKAUMI Naoki wrote:

some SKU for CM3I SoM have a SPI NOR flash. this patch enables related
configurations and changes devicetree.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, 
total 16 MiB


Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- reword commit message
---
  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
  configs/radxa-e25-rk3568_defconfig    | 14 ++
  2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi

index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
  mmc-hs400-enhanced-strobe;
  };
+&sfc {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    status = "okay";
+
+    flash@0 {
+    compatible = "jedec,spi-nor";
+    reg = <0>;
+    bootph-pre-ram;
+    bootph-some-ram;
+    spi-max-frequency = <2400>;
+    spi-rx-bus-width = <4>;
+    spi-tx-bus-width = <1>;
+    };
+};
+
  &usb_host0_xhci {
  dr_mode = "host";
  };
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig

index 496fee0e0a4..51bf0287198 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
  CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  CONFIG_COUNTER_FREQUENCY=2400
  CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
  CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
  CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
  CONFIG_SPL_SERIAL=y
  CONFIG_DEBUG_UART_BASE=0xFE66
  CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
  CONFIG_SYS_LOAD_ADDR=0xc00800
  CONFIG_PCI=y
  CONFIG_DEBUG_UART=y
@@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
  CONFIG_SPL_MAX_SIZE=0x4
  CONFIG_SPL_PAD_TO=0x7f8000
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_GPT=y
@@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
  CONFIG_RTL8169=y
  CONFIG_PCIE_DW_ROCKCHIP=y
  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y
  CONFIG_SCSI=y
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
  CONFIG_SYSRESET=y
  CONFIG_USB=y
  CONFIG_USB_XHCI_HCD=y

Re: [PATCH] rockchip: modify devicetree at runtime for Radxa ROCK Pi E v3.0

2024-09-10 Thread FUKAUMI Naoki


hi,

On 9/10/24 19:11, Kever Yang wrote:

Hi Naoki,

On 2024/8/27 09:31, FUKAUMI Naoki wrote:

since Radxa ROCK Pi E v3.0 is different to ROCK Pi E, "model" and
"compatible" in DT need to be different.
(specifically, sysupgrade[1] in OpenWrt)

also, "mmc0" and "mmc1" aliases need to be swapped to align with other
Radxa's boards.

modify them after loading DT for kernel.

[1] https://openwrt.org/docs/techref/sysupgrade#how_it_works

Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/mach-rockchip/rk3328/Kconfig   |  6 ++
  board/radxa/rockpie-rk3328/Kconfig  | 12 +++
  board/radxa/rockpie-rk3328/MAINTAINERS  |  6 ++
  board/radxa/rockpie-rk3328/Makefile |  3 +++
  board/radxa/rockpie-rk3328/rockpie-rk3328.c | 22 +
  configs/rock-pi-e-v3-rk3328_defconfig   |  2 ++
  6 files changed, 51 insertions(+)
  create mode 100644 board/radxa/rockpie-rk3328/Kconfig
  create mode 100644 board/radxa/rockpie-rk3328/MAINTAINERS
  create mode 100644 board/radxa/rockpie-rk3328/Makefile
  create mode 100644 board/radxa/rockpie-rk3328/rockpie-rk3328.c

diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig 
b/arch/arm/mach-rockchip/rk3328/Kconfig

index 70770da5fdf..654377672fe 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -10,6 +10,11 @@ config TARGET_EVB_RK3328
    with full function and phisical connectors support like
    usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+config TARGET_ROCK_PI_E_V3_RK3328
+    bool "Radxa ROCK Pi E v3.0"
+    help
+  Radxa ROCK Pi E v3.0 single board computers with a RK3328 SoC.
+
  endchoice
  config ROCKCHIP_BOOT_MODE_REG
@@ -37,5 +42,6 @@ config TPL_SYS_MALLOC_F_LEN
  default 0x800
  source "board/rockchip/evb_rk3328/Kconfig"
+source "board/radxa/rockpie-rk3328/Kconfig"
  endif
diff --git a/board/radxa/rockpie-rk3328/Kconfig 
b/board/radxa/rockpie-rk3328/Kconfig

new file mode 100644
index 000..73485d93513
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ROCK_PI_E_V3_RK3328
+
+config SYS_BOARD
+    default "rockpie-rk3328"
+
+config SYS_VENDOR
+    default "radxa"
+
+config SYS_CONFIG_NAME
+    default "evb_rk3328"
+
+endif
diff --git a/board/radxa/rockpie-rk3328/MAINTAINERS 
b/board/radxa/rockpie-rk3328/MAINTAINERS

new file mode 100644
index 000..f98ddce4e58
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/MAINTAINERS
@@ -0,0 +1,6 @@
+ROCK-PI-E-V3-RK3328
+M:    FUKAUMI Naoki 
+S:    Maintained
+F:    board/radxa/rockpie-rk3328
+F:    configs/rock-pi-e-v3-rk3328_defconfig
+F:    arch/arm/dts/rk3328-rock-pi-e*
diff --git a/board/radxa/rockpie-rk3328/Makefile 
b/board/radxa/rockpie-rk3328/Makefile

new file mode 100644
index 000..cede3b2605d
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += rockpie-rk3328.o
diff --git a/board/radxa/rockpie-rk3328/rockpie-rk3328.c 
b/board/radxa/rockpie-rk3328/rockpie-rk3328.c

new file mode 100644
index 000..3178af3e472
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/rockpie-rk3328.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+
+#define MODEL    "Radxa ROCK Pi E v3.0"
+#define COMPATIBLE1    "radxa,rockpi-e-v3"
+#define COMPATIBLE2    "rockchip,rk3328"
+
+#define MMC0    "mmc@ff52"
+#define MMC1    "mmc@ff50"
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+    fdt_setprop_string(blob, 0, "model", MODEL);
+    fdt_setprop_string(blob, 0, "compatible", COMPATIBLE1);
+    fdt_appendprop_string(blob, 0, "compatible", COMPATIBLE2);
+
+    fdt_find_and_setprop(blob, "/aliases", "mmc0", MMC0, 13, 1);
+    fdt_find_and_setprop(blob, "/aliases", "mmc1", MMC1, 13, 1);


There is already  available dts arch/arm/dts/rk3328-rock-pi-e-v3.dts,

so this change should go to to dts instead.

Does arch/arm/dts/rk3328-rock-pi-e-v3.dts also go to mainline kernel?


https://lore.kernel.org/linux-rockchip/20240816213429.1093-2-na...@radxa.com/t/#u

adding new dts for v3.0 will not be accepted for mainline kernel.
I need new compatible for v3.0 in DT for kernel, but I have no good idea 
to handle this issue...


Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


Thanks,

- Kever


+
+    return 0;
+}
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig

index 4c6cc634bd6..15036d01a40 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
  CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3"
  CONFIG_DM_RESET=y
  CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TARGET_ROCK_PI_E_V3_RK3328=y
  CONFIG_DEBUG_

Re: [PATCH] led: gpio: handle GPIO_ACTIVE_LOW flag properly

2024-08-28 Thread FUKAUMI Naoki


sorry, this patch seems to be wrong.
I'll check it again.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/28/24 21:15, FUKAUMI Naoki wrote:

invert gpio state if GPIO_ACTIVE_LOW is specified in dts.

Signed-off-by: FUKAUMI Naoki 
---
  drivers/led/led_gpio.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index ce22fb49f2a..54aa84e0726 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -25,6 +25,8 @@ static int gpio_led_set_state(struct udevice *dev, enum 
led_state_t state)
switch (state) {
case LEDST_OFF:
case LEDST_ON:
+   if (priv->gpio.flags & GPIOD_ACTIVE_LOW)
+   state = !state;
break;
case LEDST_TOGGLE:
ret = dm_gpio_get_value(&priv->gpio);
@@ -50,6 +52,9 @@ static enum led_state_t gpio_led_get_state(struct udevice 
*dev)
if (ret < 0)
return ret;
  
+	if (priv->gpio.flags & GPIOD_ACTIVE_LOW)

+   ret = !ret;
+
return ret ? LEDST_ON : LEDST_OFF;
  }

[PATCH] led: gpio: handle GPIO_ACTIVE_LOW flag properly

2024-08-28 Thread FUKAUMI Naoki

invert gpio state if GPIO_ACTIVE_LOW is specified in dts.

Signed-off-by: FUKAUMI Naoki 
---
 drivers/led/led_gpio.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index ce22fb49f2a..54aa84e0726 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -25,6 +25,8 @@ static int gpio_led_set_state(struct udevice *dev, enum 
led_state_t state)
switch (state) {
case LEDST_OFF:
case LEDST_ON:
+   if (priv->gpio.flags & GPIOD_ACTIVE_LOW)
+   state = !state;
break;
case LEDST_TOGGLE:
ret = dm_gpio_get_value(&priv->gpio);
@@ -50,6 +52,9 @@ static enum led_state_t gpio_led_get_state(struct udevice 
*dev)
if (ret < 0)
return ret;
 
+   if (priv->gpio.flags & GPIOD_ACTIVE_LOW)
+   ret = !ret;
+
return ret ? LEDST_ON : LEDST_OFF;
 }
 
-- 
2.43.0

[PATCH] rockchip: modify devicetree at runtime for Radxa ROCK Pi E v3.0

2024-08-26 Thread FUKAUMI Naoki

since Radxa ROCK Pi E v3.0 is different to ROCK Pi E, "model" and
"compatible" in DT need to be different.
(specifically, sysupgrade[1] in OpenWrt)

also, "mmc0" and "mmc1" aliases need to be swapped to align with other
Radxa's boards.

modify them after loading DT for kernel.

[1] https://openwrt.org/docs/techref/sysupgrade#how_it_works

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/mach-rockchip/rk3328/Kconfig   |  6 ++
 board/radxa/rockpie-rk3328/Kconfig  | 12 +++
 board/radxa/rockpie-rk3328/MAINTAINERS  |  6 ++
 board/radxa/rockpie-rk3328/Makefile |  3 +++
 board/radxa/rockpie-rk3328/rockpie-rk3328.c | 22 +
 configs/rock-pi-e-v3-rk3328_defconfig   |  2 ++
 6 files changed, 51 insertions(+)
 create mode 100644 board/radxa/rockpie-rk3328/Kconfig
 create mode 100644 board/radxa/rockpie-rk3328/MAINTAINERS
 create mode 100644 board/radxa/rockpie-rk3328/Makefile
 create mode 100644 board/radxa/rockpie-rk3328/rockpie-rk3328.c

diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig 
b/arch/arm/mach-rockchip/rk3328/Kconfig
index 70770da5fdf..654377672fe 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -10,6 +10,11 @@ config TARGET_EVB_RK3328
  with full function and phisical connectors support like
  usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
 
+config TARGET_ROCK_PI_E_V3_RK3328
+   bool "Radxa ROCK Pi E v3.0"
+   help
+ Radxa ROCK Pi E v3.0 single board computers with a RK3328 SoC.
+
 endchoice
 
 config ROCKCHIP_BOOT_MODE_REG
@@ -37,5 +42,6 @@ config TPL_SYS_MALLOC_F_LEN
default 0x800
 
 source "board/rockchip/evb_rk3328/Kconfig"
+source "board/radxa/rockpie-rk3328/Kconfig"
 
 endif
diff --git a/board/radxa/rockpie-rk3328/Kconfig 
b/board/radxa/rockpie-rk3328/Kconfig
new file mode 100644
index 000..73485d93513
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ROCK_PI_E_V3_RK3328
+
+config SYS_BOARD
+   default "rockpie-rk3328"
+
+config SYS_VENDOR
+   default "radxa"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3328"
+
+endif
diff --git a/board/radxa/rockpie-rk3328/MAINTAINERS 
b/board/radxa/rockpie-rk3328/MAINTAINERS
new file mode 100644
index 000..f98ddce4e58
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/MAINTAINERS
@@ -0,0 +1,6 @@
+ROCK-PI-E-V3-RK3328
+M: FUKAUMI Naoki 
+S: Maintained
+F: board/radxa/rockpie-rk3328
+F: configs/rock-pi-e-v3-rk3328_defconfig
+F: arch/arm/dts/rk3328-rock-pi-e*
diff --git a/board/radxa/rockpie-rk3328/Makefile 
b/board/radxa/rockpie-rk3328/Makefile
new file mode 100644
index 000..cede3b2605d
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += rockpie-rk3328.o
diff --git a/board/radxa/rockpie-rk3328/rockpie-rk3328.c 
b/board/radxa/rockpie-rk3328/rockpie-rk3328.c
new file mode 100644
index 000..3178af3e472
--- /dev/null
+++ b/board/radxa/rockpie-rk3328/rockpie-rk3328.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+
+#define MODEL  "Radxa ROCK Pi E v3.0"
+#define COMPATIBLE1"radxa,rockpi-e-v3"
+#define COMPATIBLE2"rockchip,rk3328"
+
+#define MMC0   "mmc@ff52"
+#define MMC1   "mmc@ff50"
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   fdt_setprop_string(blob, 0, "model", MODEL);
+   fdt_setprop_string(blob, 0, "compatible", COMPATIBLE1);
+   fdt_appendprop_string(blob, 0, "compatible", COMPATIBLE2);
+
+   fdt_find_and_setprop(blob, "/aliases", "mmc0", MMC0, 13, 1);
+   fdt_find_and_setprop(blob, "/aliases", "mmc1", MMC1, 13, 1);
+
+   return 0;
+}
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig
index 4c6cc634bd6..15036d01a40 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TARGET_ROCK_PI_E_V3_RK3328=y
 CONFIG_DEBUG_UART_BASE=0xFF13
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -18,6 +19,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-- 
2.43.0

Re: [PATCH] rockchip: add SPI NOR flash support for Radxa E25(CM3I)

2024-08-26 Thread FUKAUMI Naoki


hi,

On 8/27/24 01:11, Quentin Schulz wrote:

Hi Naoki,

On 8/25/24 12:07 AM, FUKAUMI Naoki wrote:

some SKU for CM3I SoM have a SPI NOR flash. this patch enables related
configurations and changes devicetree.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, 
total 16 MiB


Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- reword commit message
---
  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
  configs/radxa-e25-rk3568_defconfig    | 14 ++
  2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi

index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
  mmc-hs400-enhanced-strobe;
  };
+&sfc {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    status = "okay";
+
+    flash@0 {
+    compatible = "jedec,spi-nor";
+    reg = <0>;
+    bootph-pre-ram;
+    bootph-some-ram;
+    spi-max-frequency = <2400>;
+    spi-rx-bus-width = <4>;
+    spi-tx-bus-width = <1>;
+    };
+};
+


Was this sent upstream to the Linux kernel already? I did a very quick 
search on lore.kernel.org and didn't find anything. Is there anything 
that's preventing you from sending this to them first? I really would 
prefer to have only U-Boot specific stuff in -u-boot.dtsi DTSIs.


no, not yet, but I'll send this to Linux ASAP.

since SPI NOR flash is used for U-Boot, I sent this to here first.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


Cheers,
Quentin

[PATCH v2 1/2] arm64: dts: rockchip: add (but disabled) SFC node for Radxa ROCK 5A

2024-08-24 Thread FUKAUMI Naoki

This commit adds SFC node for Radxa ROCK 5A.

since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot
be enabled both nodes at the same time. so status = "okay" is omitted
here.

you may be able to enable sfc (and disable sdhci) by fdt overlay.

SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.

Signed-off-by: FUKAUMI Naoki 
Link: https://lore.kernel.org/r/20240623023329.1044-2-na...@radxa.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 00224650dd45e166ea6eb1593f5f064583963ccf ]

(cherry picked from commit fde218de3133705f3f56dc8eb26baa878f0e0dc9)
---
Changes in v2
- none
---
 dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts | 13 +
 1 file changed, 13 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts 
b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 3b9a349362d..2e2f7f0e769 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -377,6 +377,19 @@
status = "okay";
 };
 
+&sfc {
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim0_pins>;
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <10400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
 &spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
-- 
2.43.0

[PATCH v2 2/2] rockchip: add support for Radxa ROCK 5A with SPI NOR flash module

2024-08-24 Thread FUKAUMI Naoki

on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins
(i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts
specifically for SPI NOR flash is required.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2
- fix subject
---
 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 24 ++
 arch/arm/dts/rk3588s-rock-5a-spi.dts |  4 +
 board/radxa/rock5a-rk3588s/MAINTAINERS   |  5 +-
 configs/rock5a-spi-rk3588s_defconfig | 83 
 4 files changed, 113 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts
 create mode 100644 configs/rock5a-spi-rk3588s_defconfig

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi 
b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
new file mode 100644
index 000..5cd131d3cb1
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+&fspim0_pins {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+&sdhci {
+   status = "disabled";
+};
+
+&sfc {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts 
b/arch/arm/dts/rk3588s-rock-5a-spi.dts
new file mode 100644
index 000..780e90d041b
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588s-rock-5a.dts"
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS 
b/board/radxa/rock5a-rk3588s/MAINTAINERS
index a569efa74e3..06ebc9829f4 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -4,6 +4,5 @@ R:  Jonas Karlman 
 S: Maintained
 F: board/radxa/rock5a-rk3588s
 F: include/configs/rock5a-rk3588s.h
-F: configs/rock5a-rk3588s_defconfig
-F: arch/arm/dts/rk3588s-rock-5a.dts
-F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F: configs/rock5a*
+F: arch/arm/dts/rk3588s-rock-5a*
diff --git a/configs/rock5a-spi-rk3588s_defconfig 
b/configs/rock5a-spi-rk3588s_defconfig
new file mode 100644
index 000..297278c7a06
--- /dev/null
+++ b/configs/rock5a-spi-rk3588s_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
-- 
2.43.0

Re: [PATCH 2/2] arm: dts: rockchip: turn LEDs on at boot for Radxa boards

2024-08-24 Thread FUKAUMI Naoki


sorry, please ignore this patch.
https://patchwork.ozlabs.org/project/uboot/patch/20240808222325.2082-2-na...@radxa.com/
is right one.

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/16/24 09:12, FUKAUMI Naoki wrote:

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
add `default-state = "on"` to u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki 
---
this patch depends on
  
https://patchwork.ozlabs.org/project/uboot/patch/20240815223713.2479-1-na...@radxa.com/
---
  .../arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi |  6 +
  arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi  | 12 ++
  arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  8 +++
  arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi  |  8 +++
  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 23 +++
  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi   |  8 +++
  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi   |  8 +++
  arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi  |  8 +++
  8 files changed, 81 insertions(+)

diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
index 39bb66c4fcb..a30adb0be98 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
@@ -6,6 +6,12 @@
  #include "rk3328-u-boot.dtsi"
  
  / {

+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+
smbios {
compatible = "u-boot,sysinfo-smbios";
  
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi

index 50dae5cb5ef..7a6af430a6f 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -6,6 +6,18 @@
  #include "rk3399-u-boot.dtsi"
  #include "rk3399-sdram-lpddr4-100.dtsi"
  
+/ {

+   leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
  &pcfg_pull_none_18ma {
bootph-pre-ram;
bootph-some-ram;
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index b3bfc77f756..4861574636e 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -6,6 +6,14 @@
  #include "rk3399-u-boot.dtsi"
  #include "rk3399-sdram-lpddr4-100.dtsi"
  
+/ {

+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
  &sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index e0e501deccf..412f9e06aff 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -5,6 +5,14 @@
  
  #include "rk356x-u-boot.dtsi"
  
+/ {

+   leds {
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
  &sdhci {
cap-mmc-highspeed;
  };
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..efeab626d8a 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -2,6 +2,29 @@
  
  #include "rk356x-u-boot.dtsi"
  
+/ {

+   gpio-leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-red {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-green {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-blue {
+   default-state = "on";
+   gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+   };
+   };
+};
+
  &pcie3x1 {
pinctrl-0 = <&pcie30x1_reset_h>;
  };
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 0da3d9c56b8..29c18f5a340 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -6,6 +6,14 @@
  
  #include "rk356x-u-boot.dtsi"
  
+/ {

+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
  &pcie3x2 {
pinctrl-0 = <&pcie3x2_reset_h>;
  };
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
in

Re: [PATCH 1/2] configs: rockchip: enable gpio-leds driver for Radxa boards

2024-08-24 Thread FUKAUMI Naoki


sorry, please ignore this patch.
https://patchwork.ozlabs.org/project/uboot/patch/20240808222325.2082-1-na...@radxa.com/
is right one.

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/16/24 09:12, FUKAUMI Naoki wrote:

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
enable gpio-leds driver and led command.

Signed-off-by: FUKAUMI Naoki 
---
  configs/radxa-cm3-io-rk3566_defconfig | 2 ++
  configs/radxa-e25-rk3568_defconfig| 2 ++
  configs/rock-3a-rk3568_defconfig  | 2 ++
  configs/rock-4c-plus-rk3399_defconfig | 2 ++
  configs/rock-4se-rk3399_defconfig | 2 ++
  configs/rock-pi-4-rk3399_defconfig| 2 ++
  configs/rock-pi-4c-rk3399_defconfig   | 2 ++
  configs/rock-pi-e-rk3328_defconfig| 2 ++
  configs/rock-pi-e-v3-rk3328_defconfig | 2 ++
  configs/rock5a-rk3588s_defconfig  | 2 ++
  configs/rock5b-rk3588_defconfig   | 2 ++
  11 files changed, 22 insertions(+)

diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 48c8fcf5a66..9d8a59dfcbf 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -39,6 +39,8 @@ CONFIG_SPL_SYSCON=y
  CONFIG_SPL_CLK=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_MISC=y
  CONFIG_SUPPORT_EMMC_RPMB=y
  CONFIG_MMC_DW=y
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..314c3e18908 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -44,6 +44,8 @@ CONFIG_DWC_AHCI=y
  CONFIG_SPL_CLK=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_MISC=y
  CONFIG_SUPPORT_EMMC_RPMB=y
  CONFIG_MMC_DW=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7aa..f07ae545ac5 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -52,6 +52,8 @@ CONFIG_AHCI_PCI=y
  CONFIG_SPL_CLK=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_MISC=y
  CONFIG_SUPPORT_EMMC_RPMB=y
  CONFIG_MMC_DW=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
index 80dc44986e7..018926cead8 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -44,6 +44,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  CONFIG_DFU_MMC=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_ROCKCHIP_IODOMAIN=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-4se-rk3399_defconfig 
b/configs/rock-4se-rk3399_defconfig
index f52d4bf9913..4a31bc3cc58 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -48,6 +48,8 @@ CONFIG_AHCI_PCI=y
  CONFIG_DFU_MMC=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_ROCKCHIP_IODOMAIN=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index e71c4588b94..95a60335a43 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
  CONFIG_DFU_MMC=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_ROCKCHIP_IODOMAIN=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig 
b/configs/rock-pi-4c-rk3399_defconfig
index 14373933a34..9a03474a22a 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
  CONFIG_DFU_MMC=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_ROCKCHIP_IODOMAIN=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-e-rk3328_defconfig 
b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca5..9d4b2c32971 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -53,6 +53,8 @@ CONFIG_CLK=y
  CONFIG_SPL_CLK=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig
index 4c6cc634bd6..c82baceedfe 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -54,6 +54,8 @@ CONFIG_CLK=y
  CONFIG_SPL_CLK=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_PHY_REALTEK=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index c09e6655f02..6017a1cfecf 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -39,6 +39,8 @@ CONFIG_SPL_SYSCON=y
  CONFIG_SPL_CLK=y
  CONFIG_ROCKCHIP_G

Re: [PATCH] rockchip: add SPI NOR flash support for Radxa E25(CM3I)

2024-08-24 Thread FUKAUMI Naoki


sorry, please ignore this patch.
https://patchwork.ozlabs.org/project/uboot/patch/20240824220847.98136-1-na...@radxa.com/
is right one.

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/25/24 07:07, FUKAUMI Naoki wrote:

some SKU for CM3I SoM have a SPI NOR flash. this patch enables related
configurations and changes devicetree.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- reword commit message
---
  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
  configs/radxa-e25-rk3568_defconfig| 14 ++
  2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
mmc-hs400-enhanced-strobe;
  };
  
+&sfc {

+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   bootph-pre-ram;
+   bootph-some-ram;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  &usb_host0_xhci {
dr_mode = "host";
  };
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..51bf0287198 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
  CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  CONFIG_COUNTER_FREQUENCY=2400
  CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
  CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
  CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
  CONFIG_SPL_SERIAL=y
  CONFIG_DEBUG_UART_BASE=0xFE66
  CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
  CONFIG_SYS_LOAD_ADDR=0xc00800
  CONFIG_PCI=y
  CONFIG_DEBUG_UART=y
@@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
  CONFIG_SPL_MAX_SIZE=0x4
  CONFIG_SPL_PAD_TO=0x7f8000
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_GPT=y
@@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
  CONFIG_RTL8169=y
  CONFIG_PCIE_DW_ROCKCHIP=y
  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y
  CONFIG_SCSI=y
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
  CONFIG_SYSRESET=y
  CONFIG_USB=y
  CONFIG_USB_XHCI_HCD=y

[PATCH v2] rockchip: add SPI NOR flash support for Radxa E25(CM3I)

2024-08-24 Thread FUKAUMI Naoki

some SKU for CM3I SoM have a SPI NOR flash. this patch enables related
configurations and changes devicetree.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- reword commit message
---
 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
 configs/radxa-e25-rk3568_defconfig| 14 ++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
mmc-hs400-enhanced-strobe;
 };
 
+&sfc {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   bootph-pre-ram;
+   bootph-some-ram;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
 &usb_host0_xhci {
dr_mode = "host";
 };
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..51bf0287198 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
 CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_DEBUG_UART_BASE=0xFE66
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
@@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_RTL8169=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.43.0

[PATCH] rockchip: add SPI NOR flash support for Radxa E25(CM3I)

2024-08-24 Thread FUKAUMI Naoki

some SKU for CM3I SoM have a SPI NOR flash. this patch enables related
configurations and changes devicetree.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- reword commit message
---
 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
 configs/radxa-e25-rk3568_defconfig| 14 ++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
mmc-hs400-enhanced-strobe;
 };
 
+&sfc {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   bootph-pre-ram;
+   bootph-some-ram;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
 &usb_host0_xhci {
dr_mode = "host";
 };
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..51bf0287198 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
 CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_DEBUG_UART_BASE=0xFE66
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
@@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_RTL8169=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.43.0

Re: [PATCH] arm: dts: rockchip: add support for SPI NOR flash on Radxa E25(CM3I)

2024-08-24 Thread FUKAUMI Naoki


sorry, I'll send v2 tomorrow to rewrite terrible commit message...

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/24/24 18:00, FUKAUMI Naoki wrote:

my CM3I has a w25q128fw, so add support for it.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB

Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
  configs/radxa-e25-rk3568_defconfig| 14 ++
  2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
mmc-hs400-enhanced-strobe;
  };
  
+&sfc {

+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   bootph-pre-ram;
+   bootph-some-ram;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
  &usb_host0_xhci {
dr_mode = "host";
  };
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..51bf0287198 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
  CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  CONFIG_COUNTER_FREQUENCY=2400
  CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
  CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
  CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
  CONFIG_SPL_SERIAL=y
  CONFIG_DEBUG_UART_BASE=0xFE66
  CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
  CONFIG_SYS_LOAD_ADDR=0xc00800
  CONFIG_PCI=y
  CONFIG_DEBUG_UART=y
@@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
  CONFIG_SPL_MAX_SIZE=0x4
  CONFIG_SPL_PAD_TO=0x7f8000
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_GPT=y
@@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_SDMA=y
  CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
  CONFIG_RTL8169=y
  CONFIG_PCIE_DW_ROCKCHIP=y
  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y
  CONFIG_SCSI=y
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
  CONFIG_SYSRESET=y
  CONFIG_USB=y
  CONFIG_USB_XHCI_HCD=y

[PATCH] arm: dts: rockchip: add support for SPI NOR flash on Radxa E25(CM3I)

2024-08-24 Thread FUKAUMI Naoki

my CM3I has a w25q128fw, so add support for it.

=> sf probe
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 
 configs/radxa-e25-rk3568_defconfig| 14 ++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..1f0bacbf61f 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -21,6 +21,22 @@
mmc-hs400-enhanced-strobe;
 };
 
+&sfc {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   bootph-pre-ram;
+   bootph-some-ram;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
 &usb_host0_xhci {
dr_mode = "host";
 };
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..51bf0287198 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
 CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_DEBUG_UART_BASE=0xFE66
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
@@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_RTL8169=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.43.0

[PATCH 1/2] arm64: dts: rockchip: add (but disabled) SFC node for Radxa ROCK 5A

2024-08-16 Thread FUKAUMI Naoki

This commit adds SFC node for Radxa ROCK 5A.

since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot
be enabled both nodes at the same time. so status = "okay" is omitted
here.

you may be able to enable sfc (and disable sdhci) by fdt overlay.

SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.

Signed-off-by: FUKAUMI Naoki 
Link: https://lore.kernel.org/r/20240623023329.1044-2-na...@radxa.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 00224650dd45e166ea6eb1593f5f064583963ccf ]

(cherry picked from commit fde218de3133705f3f56dc8eb26baa878f0e0dc9)
---
 dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts | 13 +
 1 file changed, 13 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts 
b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 3b9a349362d..2e2f7f0e769 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -377,6 +377,19 @@
status = "okay";
 };
 
+&sfc {
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim0_pins>;
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <10400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
+
 &spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
-- 
2.43.0

[PATCH 2/2] arm: dts: rockchip: add support for Radxa ROCK 5A with SPI NOR flash module

2024-08-16 Thread FUKAUMI Naoki

on Radxa ROCK 5A, sdhci(eMMC) and fspim0(SPI NOR flash) share pins
(i.e. eMMC and SPI NOR flash are exclusive), new defconfig and dts
specifically for SPI NOR flash is required.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi | 24 ++
 arch/arm/dts/rk3588s-rock-5a-spi.dts |  4 +
 board/radxa/rock5a-rk3588s/MAINTAINERS   |  5 +-
 configs/rock5a-spi-rk3588s_defconfig | 83 
 4 files changed, 113 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-rock-5a-spi.dts
 create mode 100644 configs/rock5a-spi-rk3588s_defconfig

diff --git a/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi 
b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
new file mode 100644
index 000..5cd131d3cb1
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+
+&fspim0_pins {
+   bootph-pre-ram;
+   bootph-some-ram;
+};
+
+&sdhci {
+   status = "disabled";
+};
+
+&sfc {
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-rock-5a-spi.dts 
b/arch/arm/dts/rk3588s-rock-5a-spi.dts
new file mode 100644
index 000..780e90d041b
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-spi.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3588s-rock-5a.dts"
diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS 
b/board/radxa/rock5a-rk3588s/MAINTAINERS
index a569efa74e3..06ebc9829f4 100644
--- a/board/radxa/rock5a-rk3588s/MAINTAINERS
+++ b/board/radxa/rock5a-rk3588s/MAINTAINERS
@@ -4,6 +4,5 @@ R:  Jonas Karlman 
 S: Maintained
 F: board/radxa/rock5a-rk3588s
 F: include/configs/rock5a-rk3588s.h
-F: configs/rock5a-rk3588s_defconfig
-F: arch/arm/dts/rk3588s-rock-5a.dts
-F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F: configs/rock5a*
+F: arch/arm/dts/rk3588s-rock-5a*
diff --git a/configs/rock5a-spi-rk3588s_defconfig 
b/configs/rock5a-spi-rk3588s_defconfig
new file mode 100644
index 000..297278c7a06
--- /dev/null
+++ b/configs/rock5a-spi-rk3588s_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a-spi"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROCK5A_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
-- 
2.43.0

[PATCH 2/2] arm: dts: rockchip: turn LEDs on at boot for Radxa boards

2024-08-15 Thread FUKAUMI Naoki

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
add `default-state = "on"` to u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki 
---
this patch depends on
 
https://patchwork.ozlabs.org/project/uboot/patch/20240815223713.2479-1-na...@radxa.com/
---
 .../arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi |  6 +
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi  | 12 ++
 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  8 +++
 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi  |  8 +++
 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 23 +++
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi   |  8 +++
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi   |  8 +++
 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi  |  8 +++
 8 files changed, 81 insertions(+)

diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
index 39bb66c4fcb..a30adb0be98 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
@@ -6,6 +6,12 @@
 #include "rk3328-u-boot.dtsi"
 
 / {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+
smbios {
compatible = "u-boot,sysinfo-smbios";
 
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 50dae5cb5ef..7a6af430a6f 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -6,6 +6,18 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
 &pcfg_pull_none_18ma {
bootph-pre-ram;
bootph-some-ram;
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index b3bfc77f756..4861574636e 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -6,6 +6,14 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
 &sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index e0e501deccf..412f9e06aff 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -5,6 +5,14 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   leds {
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
 &sdhci {
cap-mmc-highspeed;
 };
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..efeab626d8a 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -2,6 +2,29 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   gpio-leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-red {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-green {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-blue {
+   default-state = "on";
+   gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+   };
+   };
+};
+
 &pcie3x1 {
pinctrl-0 = <&pcie30x1_reset_h>;
 };
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 0da3d9c56b8..29c18f5a340 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -6,6 +6,14 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
 &pcie3x2 {
pinctrl-0 = <&pcie3x2_reset_h>;
 };
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 4dd17ff408c..8cf78b19739 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -5,6 +5,14 @@
 
 #include "rk3588-u-boot.dtsi"
 
+/ {
+   leds {
+   led_rgb_b {
+   default-state = "on";
+   };
+

[PATCH 1/2] configs: rockchip: enable gpio-leds driver for Radxa boards

2024-08-15 Thread FUKAUMI Naoki

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
enable gpio-leds driver and led command.

Signed-off-by: FUKAUMI Naoki 
---
 configs/radxa-cm3-io-rk3566_defconfig | 2 ++
 configs/radxa-e25-rk3568_defconfig| 2 ++
 configs/rock-3a-rk3568_defconfig  | 2 ++
 configs/rock-4c-plus-rk3399_defconfig | 2 ++
 configs/rock-4se-rk3399_defconfig | 2 ++
 configs/rock-pi-4-rk3399_defconfig| 2 ++
 configs/rock-pi-4c-rk3399_defconfig   | 2 ++
 configs/rock-pi-e-rk3328_defconfig| 2 ++
 configs/rock-pi-e-v3-rk3328_defconfig | 2 ++
 configs/rock5a-rk3588s_defconfig  | 2 ++
 configs/rock5b-rk3588_defconfig   | 2 ++
 11 files changed, 22 insertions(+)

diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 48c8fcf5a66..9d8a59dfcbf 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -39,6 +39,8 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..314c3e18908 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -44,6 +44,8 @@ CONFIG_DWC_AHCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7aa..f07ae545ac5 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -52,6 +52,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
index 80dc44986e7..018926cead8 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -44,6 +44,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-4se-rk3399_defconfig 
b/configs/rock-4se-rk3399_defconfig
index f52d4bf9913..4a31bc3cc58 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -48,6 +48,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index e71c4588b94..95a60335a43 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig 
b/configs/rock-pi-4c-rk3399_defconfig
index 14373933a34..9a03474a22a 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-e-rk3328_defconfig 
b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca5..9d4b2c32971 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -53,6 +53,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig
index 4c6cc634bd6..c82baceedfe 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -54,6 +54,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index c09e6655f02..6017a1cfecf 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -39,6 +39,8 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 80a2f2fed58..51cdc96a546 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defc

[PATCH v2] arm: dts: rockchip: fix dts for Radxa ROCK 4C+

2024-08-15 Thread FUKAUMI Naoki

ROCK Pi 4 series and ROCK 4C+ cannot share .dtsi file because 4C+ is
different board.

add rk3399-rock-pi-4-u-boot.dtsi contents and remove dependency of it.

no functional change is intended.

Fixes: 71a95e2efd30 ("arm: dts: rockchip: add Radxa ROCK 4C+")
Suggested-by: Dragan Simic 
Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- reword commit message
---
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 5ec15a845c1..50dae5cb5ef 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -1,8 +1,10 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2019 Jagan Teki 
  * Copyright (c) 2023 Radxa Limited
  */
-#include "rk3399-rock-pi-4-u-boot.dtsi"
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
 
 &pcfg_pull_none_18ma {
bootph-pre-ram;
@@ -14,6 +16,12 @@
bootph-some-ram;
 };
 
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+};
+
 &spi1 {
status = "okay";
 
@@ -25,3 +33,7 @@
spi-max-frequency = <1000>;
};
 };
+
+&vdd_log {
+   regulator-init-microvolt = <95>;
+};
-- 
2.43.0

Re: [PATCH 8/8] rockchip: rk3308-rock-pi-s: Enable LED and IO Domain driver

2024-08-09 Thread FUKAUMI Naoki


Hi,

On 7/30/24 23:51, Jonas Karlman wrote:

Add LED=y and LED_GPIO=y to support the onboard leds.

Add ROCKCHIP_IODOMAIN=y to configure correct io voltage domains.

Add DM_MDIO=y now that the DT contain a Ethernet phy node.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang 


for the whole series,

Tested-by: FUKAUMI Naoki 

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


---
  configs/rock-pi-s-rk3308_defconfig | 4 
  1 file changed, 4 insertions(+)

diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index e450a0618020..54f7744c9895 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -38,10 +38,14 @@ CONFIG_CLK=y
  # CONFIG_USB_FUNCTION_FASTBOOT is not set
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_ROCKCHIP_IODOMAIN=y
  CONFIG_SUPPORT_EMMC_RPMB=y
  CONFIG_MMC_DW=y
  CONFIG_MMC_DW_ROCKCHIP=y
  CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
  CONFIG_DM_ETH_PHY=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y

Re: [PATCH] arm: dts: rockchip: fix dts for Radxa ROCK 4C+

2024-08-09 Thread FUKAUMI Naoki


Hi,

On 8/9/24 18:16, Kever Yang wrote:


On 2024/8/9 06:19, FUKAUMI Naoki wrote:

Radxa ROCK Pi 4 series and Radxa ROCK 4C+ are not compatible.


A little bit more detail about why not compatible?

The eMMC is different?


I should say "ROCK Pi 4 series and ROCK 4C+ cannot share dts file."

$ grep rk3399-rock-pi-4.dtsi dts/upstream/src/arm64/rockchip/*
dts/upstream/src/arm64/rockchip/rk3399-rock-4se.dts:#include 
"rk3399-rock-pi-4.dtsi"
dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4a-plus.dts:#include 
"rk3399-rock-pi-4.dtsi"
dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4a.dts:#include 
"rk3399-rock-pi-4.dtsi"
dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4b-plus.dts:#include 
"rk3399-rock-pi-4.dtsi"
dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4b.dts:#include 
"rk3399-rock-pi-4.dtsi"
dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4c.dts:#include 
"rk3399-rock-pi-4.dtsi"


4C+ is different board.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


Thanks,

- Kever


add
rk3399-rock-pi-4-u-boot.dtsi contents and remove dependency of it.

no functional change is intended.

Fixes: 71a95e2efd30 ("arm: dts: rockchip: add Radxa ROCK 4C+")
Suggested-by: Dragan Simic 
Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 16 ++--
  1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi

index 5ec15a845c1..50dae5cb5ef 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -1,8 +1,10 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0+
  /*
+ * Copyright (C) 2019 Jagan Teki 
   * Copyright (c) 2023 Radxa Limited
   */
-#include "rk3399-rock-pi-4-u-boot.dtsi"
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
  &pcfg_pull_none_18ma {
  bootph-pre-ram;
@@ -14,6 +16,12 @@
  bootph-some-ram;
  };
+&sdhci {
+    cap-mmc-highspeed;
+    mmc-ddr-1_8v;
+    mmc-hs200-1_8v;
+};
+
  &spi1 {
  status = "okay";
@@ -25,3 +33,7 @@
  spi-max-frequency = <1000>;
  };
  };
+
+&vdd_log {
+    regulator-init-microvolt = <95>;
+};

Re: [PATCH v6] board: rockchip: add Radxa ROCK 3 Model C

2024-08-08 Thread FUKAUMI Naoki


Hi,

On 8/9/24 04:37, Maxim Moskalets wrote:

From: Maxim Moskalets 

Based on rock-3a-rk3568_defconfig.
Tested on v1.31 revision.

Board Specifications:
- Rockchip RK3566
- 1/2/4GB LPDDR4 2112MT/s
- eMMC socket
- uSD card slot
- M.2 2230 Connector
- GbE LAN with POE
- 3.5mm jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host, USB 2.0 Host/OTG
- 40-pin GPIO expansion ports

Signed-off-by: Maxim Moskalets 
Suggested-by: Jonas Karlman 
Reviewed-by: Jonas Karlman 


I got following error when `usb start` and `usb reset`

```
Bus usb@fcc0: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd00: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd80: USB EHCI 1.00
Bus usb@fd84: USB OHCI 1.0
Bus usb@fd88: USB EHCI 1.00
Bus usb@fd8c: USB OHCI 1.0
scanning bus usb@fcc0 for devices... 1 USB Device(s) found
scanning bus usb@fd00 for devices... 1 USB Device(s) found
scanning bus usb@fd80 for devices... 1 USB Device(s) found
scanning bus usb@fd84 for devices... ERROR:  USB-error: 
DEVICENOTRESPONDING: Device did not respond to token (IN) or did

not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token 
(IN) or did

not provide a handshake (OUT) (5)
ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token 
(IN) or did

not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token 
(IN) or did

not provide a handshake (OUT) (5)
ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token 
(IN) or did

not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token 
(IN) or did

not provide a handshake (OUT) (5)
unable to get device descriptor (error=-1)
1 USB Device(s) found
scanning bus usb@fd88 for devices... 1 USB Device(s) found
scanning bus usb@fd8c for devices... 1 USB Device(s) found
```

but it happens only when no USB device is connected at usb@fd84 
(upper right port). if some device is connected, it doesn't happen, 
device is recognized properly.


if it's okay,

Tested-by: FUKAUMI Naoki 


Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


---
v6:
update dts to turn LED up in U-Boot
v5:
fixed board info
v4:
fixed typo in commit-msg
moved maintainers record to file for rk3568 boards
renamed from ROCK 3 Model C to ROCK3C
v3:
add suggested by Jonas Karlman  in

https://lore.kernel.org/all/bbb81dd1-e318-423d-8258-db7556ce6...@kwiboo.se/
v2:
rebase to updated upstream dts
---
  arch/arm/dts/rk3566-rock-3c-u-boot.dtsi | 18 +
  board/rockchip/evb_rk3568/MAINTAINERS   |  7 ++
  configs/rock-3c-rk3566_defconfig| 97 +
  doc/board/rockchip/rockchip.rst |  1 +
  4 files changed, 123 insertions(+)
  create mode 100644 arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
  create mode 100644 configs/rock-3c-rk3566_defconfig

diff --git a/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi 
b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
new file mode 100644
index 000..f4124aa48fc
--- /dev/null
+++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sfc {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
+
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS 
b/board/rockchip/evb_rk3568/MAINTAINERS
index e5b0986ead9..ba4884db8e1 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -69,3 +69,10 @@ S:   Maintained
  F:configs/rock-3a-rk3568_defconfig
  F:arch/arm/dts/rk3568-rock-3a.dts
  F:arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+
+ROCK-3C
+M: Jonas Karlman 
+M: Maxim Moskalets 
+S: Maintained
+F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
+F: configs/rock-3c-rk3566_defconfig
diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig
new file mode 100644
index 000..f44b202c8c3
--- /dev/null
+++ b/configs/rock-3c-rk3566_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE66
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_D

Re: [PATCH] arm: dts: rockchip: disable "usb_host0_ohci" to make boot faster for Radxa ROCK 3A

2024-08-08 Thread FUKAUMI Naoki


sorry, please ignore this patch.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/2/24 11:49, FUKAUMI Naoki wrote:

on-board USB 2.0 hub, FE1.1s, has Transaction Translator which can
handle USB 1.x devices via "usb_host0_ehci". so we can omit
"usb_host0_ohci" and make boot faster (a little).

=> usb start
starting USB...
Bus usb@fd00: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd80: USB EHCI 1.00
Bus usb@fd88: USB EHCI 1.00
Bus usb@fd8c: USB OHCI 1.0
scanning bus usb@fd00 for devices... 1 USB Device(s) found
scanning bus usb@fd80 for devices... 2 USB Device(s) found
scanning bus usb@fd88 for devices... 1 USB Device(s) found
scanning bus usb@fd8c for devices... 3 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
   1  Hub (5 Gb/s, 0mA)
  U-Boot XHCI Host Controller

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 100mA)
 USB 2.0 Hub

   1  Hub (480 Mb/s, 0mA)
  u-boot EHCI Host Controller

   1  Hub (12 Mb/s, 0mA)
   |   U-Boot Root Hub
   |
   +-2  Hub (12 Mb/s, 100mA)
 |  ALCOR Generic USB Hub
 |
 +-3  Mass Storage (12 Mb/s, 300mA)
  JetFlash Mass Storage Device 02K1RNH5MJFV4TX6

=> usb reset
resetting USB...
Host not halted after 16000 microseconds.
Bus usb@fd00: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd80: USB EHCI 1.00
Bus usb@fd88: USB EHCI 1.00
Bus usb@fd8c: USB OHCI 1.0
scanning bus usb@fd00 for devices... 1 USB Device(s) found
scanning bus usb@fd80 for devices... 4 USB Device(s) found
scanning bus usb@fd88 for devices... 1 USB Device(s) found
scanning bus usb@fd8c for devices... 1 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
   1  Hub (5 Gb/s, 0mA)
  U-Boot XHCI Host Controller

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 100mA)
 |   USB 2.0 Hub
 |
 +-3  Hub (12 Mb/s, 100mA)
   |  ALCOR Generic USB Hub
   |
   +-4  Mass Storage (12 Mb/s, 300mA)
JetFlash Mass Storage Device 02K1RNH5MJFV4TX6

   1  Hub (480 Mb/s, 0mA)
  u-boot EHCI Host Controller

   1  Hub (12 Mb/s, 0mA)
   U-Boot Root Hub

Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 4 
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b36..9078b9a67a2 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -40,3 +40,7 @@
spi-tx-bus-width = <1>;
};
  };
+
+&usb_host0_ohci {
+   status = "disabled";
+};

[PATCH v2 2/2] arm: dts: rockchip: turn LEDs on at boot for Radxa boards

2024-08-08 Thread FUKAUMI Naoki

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
add `default-state = "on"` to u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- remove irrelevant contents from rk3399-rock-4c-plus-u-boot.dtsi
- depend 
https://patchwork.ozlabs.org/project/uboot/patch/20240808221902.2006-1-na...@radxa.com/
---
 .../arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi |  6 +
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi  | 12 ++
 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  8 +++
 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi  |  8 +++
 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 23 +++
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi   |  8 +++
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi   |  8 +++
 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi  |  8 +++
 8 files changed, 81 insertions(+)

diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
index 39bb66c4fcb..a30adb0be98 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
@@ -6,6 +6,12 @@
 #include "rk3328-u-boot.dtsi"
 
 / {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+
smbios {
compatible = "u-boot,sysinfo-smbios";
 
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 50dae5cb5ef..7a6af430a6f 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -6,6 +6,18 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
 &pcfg_pull_none_18ma {
bootph-pre-ram;
bootph-some-ram;
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index b3bfc77f756..4861574636e 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -6,6 +6,14 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
 &sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index e0e501deccf..412f9e06aff 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -5,6 +5,14 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   leds {
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
 &sdhci {
cap-mmc-highspeed;
 };
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..efeab626d8a 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -2,6 +2,29 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   gpio-leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-red {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-green {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-blue {
+   default-state = "on";
+   gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+   };
+   };
+};
+
 &pcie3x1 {
pinctrl-0 = <&pcie30x1_reset_h>;
 };
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b36..c493352abc1 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -6,6 +6,14 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
 &pcie3x2 {
pinctrl-0 = <&pcie3x2_reset_h>;
 };
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 8e318e624a8..8ebba36f90a 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -5,6 +5,14 @@
 
 #include "rk3588-u-boot.dtsi"
 
+/ {
+   leds {
+   led_rgb_b {
+

[PATCH v2 1/2] configs: rockchip: enable gpio-leds driver for Radxa boards

2024-08-08 Thread FUKAUMI Naoki

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
enable gpio-leds driver and led command.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v2:
- none
---
 configs/radxa-cm3-io-rk3566_defconfig | 2 ++
 configs/radxa-e25-rk3568_defconfig| 2 ++
 configs/rock-3a-rk3568_defconfig  | 2 ++
 configs/rock-4c-plus-rk3399_defconfig | 2 ++
 configs/rock-4se-rk3399_defconfig | 2 ++
 configs/rock-pi-4-rk3399_defconfig| 2 ++
 configs/rock-pi-4c-rk3399_defconfig   | 2 ++
 configs/rock-pi-e-rk3328_defconfig| 2 ++
 configs/rock-pi-e-v3-rk3328_defconfig | 2 ++
 configs/rock-pi-s-rk3308_defconfig| 2 ++
 configs/rock5a-rk3588s_defconfig  | 2 ++
 configs/rock5b-rk3588_defconfig   | 2 ++
 12 files changed, 24 insertions(+)

diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 48c8fcf5a66..9d8a59dfcbf 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -39,6 +39,8 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..314c3e18908 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -44,6 +44,8 @@ CONFIG_DWC_AHCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7aa..f07ae545ac5 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -52,6 +52,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
index 80dc44986e7..018926cead8 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -44,6 +44,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-4se-rk3399_defconfig 
b/configs/rock-4se-rk3399_defconfig
index f52d4bf9913..4a31bc3cc58 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -48,6 +48,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index e71c4588b94..95a60335a43 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig 
b/configs/rock-pi-4c-rk3399_defconfig
index 14373933a34..9a03474a22a 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-e-rk3328_defconfig 
b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca5..9d4b2c32971 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -53,6 +53,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig
index 4c6cc634bd6..c82baceedfe 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -54,6 +54,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index e450a061802..de45d295fd5 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -38,6 +38,8 @@ CONFIG_CLK=y
 # CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defc

[PATCH] arm: dts: rockchip: fix dts for Radxa ROCK 4C+

2024-08-08 Thread FUKAUMI Naoki

Radxa ROCK Pi 4 series and Radxa ROCK 4C+ are not compatible. add
rk3399-rock-pi-4-u-boot.dtsi contents and remove dependency of it.

no functional change is intended.

Fixes: 71a95e2efd30 ("arm: dts: rockchip: add Radxa ROCK 4C+")
Suggested-by: Dragan Simic 
Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 5ec15a845c1..50dae5cb5ef 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -1,8 +1,10 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2019 Jagan Teki 
  * Copyright (c) 2023 Radxa Limited
  */
-#include "rk3399-rock-pi-4-u-boot.dtsi"
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
 
 &pcfg_pull_none_18ma {
bootph-pre-ram;
@@ -14,6 +16,12 @@
bootph-some-ram;
 };
 
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+};
+
 &spi1 {
status = "okay";
 
@@ -25,3 +33,7 @@
spi-max-frequency = <1000>;
};
 };
+
+&vdd_log {
+   regulator-init-microvolt = <95>;
+};
-- 
2.43.0

[PATCH 1/2] configs: rockchip: enable gpio-leds driver for Radxa boards

2024-08-08 Thread FUKAUMI Naoki

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
enable gpio-leds driver and led command.

Signed-off-by: FUKAUMI Naoki 
---
 configs/radxa-cm3-io-rk3566_defconfig | 2 ++
 configs/radxa-e25-rk3568_defconfig| 2 ++
 configs/rock-3a-rk3568_defconfig  | 2 ++
 configs/rock-4c-plus-rk3399_defconfig | 2 ++
 configs/rock-4se-rk3399_defconfig | 2 ++
 configs/rock-pi-4-rk3399_defconfig| 2 ++
 configs/rock-pi-4c-rk3399_defconfig   | 2 ++
 configs/rock-pi-e-rk3328_defconfig| 2 ++
 configs/rock-pi-e-v3-rk3328_defconfig | 2 ++
 configs/rock-pi-s-rk3308_defconfig| 2 ++
 configs/rock5a-rk3588s_defconfig  | 2 ++
 configs/rock5b-rk3588_defconfig   | 2 ++
 12 files changed, 24 insertions(+)

diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 48c8fcf5a66..9d8a59dfcbf 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -39,6 +39,8 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a4..314c3e18908 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -44,6 +44,8 @@ CONFIG_DWC_AHCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7aa..f07ae545ac5 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -52,6 +52,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
index 80dc44986e7..018926cead8 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -44,6 +44,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-4se-rk3399_defconfig 
b/configs/rock-4se-rk3399_defconfig
index f52d4bf9913..4a31bc3cc58 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -48,6 +48,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index e71c4588b94..95a60335a43 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig 
b/configs/rock-pi-4c-rk3399_defconfig
index 14373933a34..9a03474a22a 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_AHCI_PCI=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock-pi-e-rk3328_defconfig 
b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca5..9d4b2c32971 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -53,6 +53,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig
index 4c6cc634bd6..c82baceedfe 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -54,6 +54,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index e450a061802..de45d295fd5 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -38,6 +38,8 @@ CONFIG_CLK=y
 # CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index c09e66

[PATCH 2/2] arm: dts: rockchip: turn LEDs on at boot for Radxa boards

2024-08-08 Thread FUKAUMI Naoki

Basically, Radxa's boards are intended to turn LEDs on at U-Boot.
add `default-state = "on"` to u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki 
---
 .../arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi |  6 +
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi  | 25 ++-
 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi |  8 ++
 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi  |  8 ++
 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 23 +
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi   |  8 ++
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi   |  8 ++
 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi  |  8 ++
 8 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
index 39bb66c4fcb..a30adb0be98 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
@@ -6,6 +6,12 @@
 #include "rk3328-u-boot.dtsi"
 
 / {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+
smbios {
compatible = "u-boot,sysinfo-smbios";
 
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
index 5ec15a845c1..614e4ce0fa8 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -2,7 +2,20 @@
 /*
  * Copyright (c) 2023 Radxa Limited
  */
-#include "rk3399-rock-pi-4-u-boot.dtsi"
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
 
 &pcfg_pull_none_18ma {
bootph-pre-ram;
@@ -14,6 +27,12 @@
bootph-some-ram;
 };
 
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+};
+
 &spi1 {
status = "okay";
 
@@ -25,3 +44,7 @@
spi-max-frequency = <1000>;
};
 };
+
+&vdd_log {
+   regulator-init-microvolt = <95>;
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index b3bfc77f756..4861574636e 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -6,6 +6,14 @@
 #include "rk3399-u-boot.dtsi"
 #include "rk3399-sdram-lpddr4-100.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
 &sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index e0e501deccf..412f9e06aff 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -5,6 +5,14 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   leds {
+   led-1 {
+   default-state = "on";
+   };
+   };
+};
+
 &sdhci {
cap-mmc-highspeed;
 };
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi 
b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
index 74755a44eae..efeab626d8a 100644
--- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
@@ -2,6 +2,29 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   gpio-leds {
+   led-0 {
+   default-state = "on";
+   };
+
+   led-red {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-green {
+   default-state = "on";
+   gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+   };
+
+   led-blue {
+   default-state = "on";
+   gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+   };
+   };
+};
+
 &pcie3x1 {
pinctrl-0 = <&pcie30x1_reset_h>;
 };
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b36..c493352abc1 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -6,6 +6,14 @@
 
 #include "rk356x-u-boot.dtsi"
 
+/ {
+   leds {
+   led-0 {
+   default-state = "on";
+   };
+   };
+};
+
 &pcie3x2 {
pinctrl-0 = <&pcie3x2_reset_h>;
 };
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dt

Re: [PATCH v5] board: rockchip: add Radxa ROCK 3 Model C

2024-08-08 Thread FUKAUMI Naoki


Hi,

On 8/4/24 02:40, Maxim Moskalets wrote:

From: Maxim Moskalets 

Based on rock-3a-rk3568_defconfig.
Tested on v1.31 revision.

Board Specifications:
- Rockchip RK3566
- 1/2/4GB LPDDR4 2112MT/s
- eMMC socket
- uSD card slot
- M.2 2230 Connector
- GbE LAN with POE
- 3.5mm jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host, USB 2.0 Host/OTG
- 40-pin GPIO expansion ports

Signed-off-by: Maxim Moskalets 
Suggested-by: Jonas Karlman 
Reviewed-by: Jonas Karlman 
---
v5:
fixed board info
v4:
fixed typo in commit-msg
moved maintainers record to file for rk3568 boards
renamed from ROCK 3 Model C to ROCK3C
v3:
add suggested by Jonas Karlman  in

https://lore.kernel.org/all/bbb81dd1-e318-423d-8258-db7556ce6...@kwiboo.se/
v2:
rebase to updated upstream dts
---
  arch/arm/dts/rk3566-rock-3c-u-boot.dtsi | 10 +++
  board/rockchip/evb_rk3568/MAINTAINERS   |  7 ++
  configs/rock-3c-rk3566_defconfig| 97 +
  doc/board/rockchip/rockchip.rst |  1 +
  4 files changed, 115 insertions(+)
  create mode 100644 arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
  create mode 100644 configs/rock-3c-rk3566_defconfig

diff --git a/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi 
b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
new file mode 100644
index 000..fd7f5367b75
--- /dev/null
+++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"


please add

```
/ {
leds {
led-0 {
default-state = "on";
};
};
};
```

to turn LED on at U-Boot. (make CONFIG_LED_GPIO work)

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


+&sfc {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS 
b/board/rockchip/evb_rk3568/MAINTAINERS
index e5b0986ead9..ba4884db8e1 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -69,3 +69,10 @@ S:   Maintained
  F:configs/rock-3a-rk3568_defconfig
  F:arch/arm/dts/rk3568-rock-3a.dts
  F:arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+
+ROCK-3C
+M: Jonas Karlman 
+M: Maxim Moskalets 
+S: Maintained
+F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
+F: configs/rock-3c-rk3566_defconfig
diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig
new file mode 100644
index 000..f44b202c8c3
--- /dev/null
+++ b/configs/rock-3c-rk3566_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE66
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+

[PATCH] configs: rockchip: enable "ums" command for Radxa ROCK 5B

2024-08-05 Thread FUKAUMI Naoki

USB Type-C port is configured as "peripheral" port. so enable "ums"
command to use as USB Mass Storage device.
("rockusb" command is already enabled and working)

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock5b-rk3588_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index fc118cea7ba..80a2f2fed58 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
-- 
2.43.0

[PATCH] arm: dts: rockchip: remove upstreamed props for Radxa ROCK 5B

2024-08-05 Thread FUKAUMI Naoki

"usb_host1_xhci" and related node were already upstreamed. remove
unnecessary properties from u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 17 -
 1 file changed, 17 deletions(-)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 8e318e624a8..4dd17ff408c 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -39,18 +39,6 @@
status = "okay";
 };
 
-&u2phy1 {
-   status = "okay";
-};
-
-&u2phy1_otg {
-   status = "okay";
-};
-
-&usbdp_phy1 {
-   status = "okay";
-};
-
 &usbdp_phy0 {
status = "okay";
 };
@@ -60,8 +48,3 @@
maximum-speed = "high-speed";
status = "okay";
 };
-
-&usb_host1_xhci {
-   dr_mode = "host";
-   status = "okay";
-};
-- 
2.43.0

[PATCH] arm: dts: rockchip: remove upstreamed props for Radxa ROCK 3A

2024-08-05 Thread FUKAUMI Naoki

"sfc" node was already upstreamed. remove unnecessary properties from
u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 9 -
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b36..4df40eec975 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -26,17 +26,8 @@
 };
 
 &sfc {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   status = "okay";
-
flash@0 {
-   compatible = "jedec,spi-nor";
-   reg = <0>;
bootph-pre-ram;
bootph-some-ram;
-   spi-max-frequency = <2400>;
-   spi-rx-bus-width = <4>;
-   spi-tx-bus-width = <1>;
};
 };
-- 
2.43.0

Re: [PATCH] arm: dts: rockchip: sort usbdp_phy nodes for Radxa ROCK 5B

2024-08-05 Thread FUKAUMI Naoki


sorry, please ignore this patch.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/6/24 09:09, FUKAUMI Naoki wrote:

sort nodes alphanumerically.
no functional change is intended.

Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 8e318e624a8..fabbd717b61 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -47,11 +47,11 @@
status = "okay";
  };
  
-&usbdp_phy1 {

+&usbdp_phy0 {
status = "okay";
  };
  
-&usbdp_phy0 {

+&usbdp_phy1 {
status = "okay";
  };

[PATCH] arm: dts: rockchip: sort usbdp_phy nodes for Radxa ROCK 5B

2024-08-05 Thread FUKAUMI Naoki

sort nodes alphanumerically.
no functional change is intended.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 8e318e624a8..fabbd717b61 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -47,11 +47,11 @@
status = "okay";
 };
 
-&usbdp_phy1 {
+&usbdp_phy0 {
status = "okay";
 };
 
-&usbdp_phy0 {
+&usbdp_phy1 {
status = "okay";
 };
 
-- 
2.43.0

[PATCH] arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK 3C

2024-08-04 Thread FUKAUMI Naoki

SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.

Signed-off-by: FUKAUMI Naoki 
Link: https://lore.kernel.org/r/20240623023329.1044-3-na...@radxa.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 06f6dd4d607766a527e37529f2f3f90dd1464293 ]

(cherry picked from commit dd40945a1d0e28ae6eaf9da04f8e2dcebf8233ea)
---
 dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts 
b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts
index b242409d378..f2cc086e500 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts
@@ -633,7 +633,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
-   spi-max-frequency = <12000>;
+   spi-max-frequency = <10400>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
-- 
2.43.0

Re: [PATCH] configs: rockchip: enable USB gadget functions for Radxa ROCK 3A

2024-08-02 Thread FUKAUMI Naoki


hi,

please don't merge this for a while.

I'm thinking opposite change may be better to align with ROCK 4/5 
series. (OTG port is "host")


any comment?

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 8/2/24 11:58, FUKAUMI Naoki wrote:

since dr_mode of "usb_host0_xhci" is "otg", we can use USB gadget
functions on USB3 Type-A OTG (upper) port. enable it.

Signed-off-by: FUKAUMI Naoki 
---
  configs/rock-3a-rk3568_defconfig | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7aa..0568a730383 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_MMC=y
  CONFIG_CMD_PCI=y
  CONFIG_CMD_POWEROFF=y
  CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_CMD_PMIC=y
  CONFIG_CMD_REGULATOR=y
@@ -50,6 +52,7 @@ CONFIG_SPL_SYSCON=y
  CONFIG_SCSI_AHCI=y
  CONFIG_AHCI_PCI=y
  CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
  CONFIG_MISC=y
@@ -90,4 +93,7 @@ CONFIG_USB_OHCI_HCD=y
  CONFIG_USB_OHCI_GENERIC=y
  CONFIG_USB_DWC3=y
  CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
  CONFIG_ERRNO_STR=y

Re: [PATCH v4] board: rockchip: add Radxa ROCK 3 Model C

2024-08-01 Thread FUKAUMI Naoki


sorry,

On 8/2/24 10:54, FUKAUMI Naoki wrote:
since USB Type-A OTG port is peripheral mode, you can enable USB gadget 
functions. could you merge following patch?


it's wrong.

"usb_host0_xhci" dr_mode need to be deleted...

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

[PATCH] configs: rockchip: enable USB gadget functions for Radxa ROCK 3A

2024-08-01 Thread FUKAUMI Naoki

since dr_mode of "usb_host0_xhci" is "otg", we can use USB gadget
functions on USB3 Type-A OTG (upper) port. enable it.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock-3a-rk3568_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7aa..0568a730383 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -50,6 +52,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -90,4 +93,7 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
-- 
2.43.0

[PATCH] arm: dts: rockchip: disable "usb_host0_ohci" to make boot faster for Radxa ROCK 3A

2024-08-01 Thread FUKAUMI Naoki

on-board USB 2.0 hub, FE1.1s, has Transaction Translator which can
handle USB 1.x devices via "usb_host0_ehci". so we can omit
"usb_host0_ohci" and make boot faster (a little).

=> usb start
starting USB...
Bus usb@fd00: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd80: USB EHCI 1.00
Bus usb@fd88: USB EHCI 1.00
Bus usb@fd8c: USB OHCI 1.0
scanning bus usb@fd00 for devices... 1 USB Device(s) found
scanning bus usb@fd80 for devices... 2 USB Device(s) found
scanning bus usb@fd88 for devices... 1 USB Device(s) found
scanning bus usb@fd8c for devices... 3 USB Device(s) found
   scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (5 Gb/s, 0mA)
 U-Boot XHCI Host Controller

  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 100mA)
USB 2.0 Hub

  1  Hub (480 Mb/s, 0mA)
 u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  |   U-Boot Root Hub
  |
  +-2  Hub (12 Mb/s, 100mA)
|  ALCOR Generic USB Hub
|
+-3  Mass Storage (12 Mb/s, 300mA)
 JetFlash Mass Storage Device 02K1RNH5MJFV4TX6

=> usb reset
resetting USB...
Host not halted after 16000 microseconds.
Bus usb@fd00: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd80: USB EHCI 1.00
Bus usb@fd88: USB EHCI 1.00
Bus usb@fd8c: USB OHCI 1.0
scanning bus usb@fd00 for devices... 1 USB Device(s) found
scanning bus usb@fd80 for devices... 4 USB Device(s) found
scanning bus usb@fd88 for devices... 1 USB Device(s) found
scanning bus usb@fd8c for devices... 1 USB Device(s) found
   scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (5 Gb/s, 0mA)
 U-Boot XHCI Host Controller

  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 100mA)
|   USB 2.0 Hub
|
+-3  Hub (12 Mb/s, 100mA)
  |  ALCOR Generic USB Hub
  |
  +-4  Mass Storage (12 Mb/s, 300mA)
   JetFlash Mass Storage Device 02K1RNH5MJFV4TX6

  1  Hub (480 Mb/s, 0mA)
 u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  U-Boot Root Hub

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b36..9078b9a67a2 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -40,3 +40,7 @@
spi-tx-bus-width = <1>;
};
 };
+
+&usb_host0_ohci {
+   status = "disabled";
+};
-- 
2.43.0

Re: [PATCH v4] board: rockchip: add Radxa ROCK 3 Model C

2024-08-01 Thread FUKAUMI Naoki

lowing patch?


diff --git a/configs/rock-3c-rk3566_defconfig 
b/configs/rock-3c-rk3566_defconfig

index f44b202c8c3..707088657fc 100644
--- a/configs/rock-3c-rk3566_defconfig
+++ b/configs/rock-3c-rk3566_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -51,6 +53,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
@@ -94,4 +97,7 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index bedc52e03e2..60357af6caa 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -105,6 +105,7 @@ List of mainline supported Rockchip boards:
   - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
   - Powkiddy X55 (powkiddy-x55-rk3566)
   - Radxa CM3 IO Board (radxa-cm3-io-rk3566)
+ - Radxa ROCK 3C (rock-3c-rk3566)
  
  * rk3568

   - Rockchip Evb-RK3568 (evb-rk3568)

Re: [PATCH 2/2] board: rockchip: Add Radxa ROCK 3B

2024-08-01 Thread FUKAUMI Naoki


Hi,

On 7/31/24 16:28, Jonas Karlman wrote:

The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form
factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community
version based on the RK3568 SoC and an industrial version based on the
RK3568J SoC.

Features tested on ROCK 3B 8GB v1.51 (both variants):
- SD-card boot
- eMMC boot
- SPI Flash boot
- Ethernet
- PCIe/NVMe
- USB gadget
- USB host

Signed-off-by: Jonas Karlman 


for the whole series,

Tested-by: FUKAUMI Naoki 

thank you so much for your contribution!

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


---
  arch/arm/dts/rk3568-rock-3b-u-boot.dtsi |  15 
  board/rockchip/evb_rk3568/MAINTAINERS   |   6 ++
  configs/rock-3b-rk3568_defconfig| 100 
  doc/board/rockchip/rockchip.rst |   3 +-
  4 files changed, 123 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
  create mode 100644 configs/rock-3b-rk3568_defconfig

diff --git a/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
new file mode 100644
index ..b1f324282bac
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sdhci {
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+};
+
+&sfc {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS 
b/board/rockchip/evb_rk3568/MAINTAINERS
index ba4884db8e12..588134ecb27a 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -70,6 +70,12 @@ F:   configs/rock-3a-rk3568_defconfig
  F:arch/arm/dts/rk3568-rock-3a.dts
  F:arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
  
+ROCK-3B

+M: Jonas Karlman 
+S: Maintained
+F: configs/rock-3b-rk3568_defconfig
+F: arch/arm/dts/rk3568-rock-3b*
+
  ROCK-3C
  M:Jonas Karlman 
  M:Maxim Moskalets 
diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig
new file mode 100644
index ..937796811a97
--- /dev/null
+++ b/configs/rock-3b-rk3568_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3b"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE66
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3b.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/do

Re: [PATCH 5/5] board: rockchip: Add Radxa ZERO 3W/3E

2024-07-31 Thread FUKAUMI Naoki


Hi,

On 7/31/24 15:50, Jonas Karlman wrote:

The Radxa ZERO 3W/3E is an ultra-small, high-performance single board
computer based on the Rockchip RK3566, with a compact form factor and
rich interfaces.

Implement rk_board_late_init() to set correct fdtfile env var and
board_fit_config_name_match() to load correct FIT config based on what
board is detected at runtime so a single board target can be used for
both board models.

Features tested on a ZERO 3W 8GB v1.11:
- SD-card boot
- eMMC boot
- USB gadget
- USB host

Features tested on a ZERO 3E 4GB v1.2:
- SD-card boot
- Ethernet
- USB gadget
- USB host

Signed-off-by: Jonas Karlman 


for whole series,

Tested-by FUKAUMI Naoki 

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


---
  arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi | 11 +++
  arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi | 11 +++
  arch/arm/mach-rockchip/rk3568/Kconfig |  6 ++
  board/radxa/zero3-rk3566/Kconfig  | 12 +++
  board/radxa/zero3-rk3566/MAINTAINERS  |  6 ++
  board/radxa/zero3-rk3566/Makefile |  3 +
  board/radxa/zero3-rk3566/zero3-rk3566.c   | 59 +
  configs/radxa-zero-3-rk3566_defconfig | 85 +++
  doc/board/rockchip/rockchip.rst   |  1 +
  9 files changed, 194 insertions(+)
  create mode 100644 arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
  create mode 100644 board/radxa/zero3-rk3566/Kconfig
  create mode 100644 board/radxa/zero3-rk3566/MAINTAINERS
  create mode 100644 board/radxa/zero3-rk3566/Makefile
  create mode 100644 board/radxa/zero3-rk3566/zero3-rk3566.c
  create mode 100644 configs/radxa-zero-3-rk3566_defconfig

diff --git a/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
new file mode 100644
index ..4025f5097af5
--- /dev/null
+++ b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&saradc {
+   bootph-pre-ram;
+};
+
+&vcca_1v8 {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
new file mode 100644
index ..4025f5097af5
--- /dev/null
+++ b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&saradc {
+   bootph-pre-ram;
+};
+
+&vcca_1v8 {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig 
b/arch/arm/mach-rockchip/rk3568/Kconfig
index 014ebf9f0ba7..0f32f243be4e 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -32,6 +32,11 @@ config TARGET_QUARTZ64_RK3566
help
  Pine64 Quartz64 single board computer with a RK3566 SoC.
  
+config TARGET_RADXA_ZERO_3_RK3566

+   bool "Radxa ZERO 3W/3E"
+   help
+ Radxa ZERO 3W/3E single board computers with a RK3566 SoC.
+
  endchoice
  
  config ROCKCHIP_BOOT_MODE_REG

@@ -54,5 +59,6 @@ source "board/anbernic/rgxx3_rk3566/Kconfig"
  source "board/hardkernel/odroid_m1/Kconfig"
  source "board/pine64/quartz64_rk3566/Kconfig"
  source "board/powkiddy/x55/Kconfig"
+source "board/radxa/zero3-rk3566/Kconfig"
  
  endif

diff --git a/board/radxa/zero3-rk3566/Kconfig b/board/radxa/zero3-rk3566/Kconfig
new file mode 100644
index ..7d46efc9c40f
--- /dev/null
+++ b/board/radxa/zero3-rk3566/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RADXA_ZERO_3_RK3566
+
+config SYS_BOARD
+   default "zero3-rk3566"
+
+config SYS_VENDOR
+   default "radxa"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3568"
+
+endif
diff --git a/board/radxa/zero3-rk3566/MAINTAINERS 
b/board/radxa/zero3-rk3566/MAINTAINERS
new file mode 100644
index ..e5a5d856113d
--- /dev/null
+++ b/board/radxa/zero3-rk3566/MAINTAINERS
@@ -0,0 +1,6 @@
+RADXA-ZERO-3-RK3566
+M: Jonas Karlman 
+S: Maintained
+F: board/radxa/zero3-rk3566
+F: configs/radxa-zero-3-rk3566_defconfig
+F: arch/arm/dts/rk3566-radxa-zero-3*
diff --git a/board/radxa/zero3-rk3566/Makefile 
b/board/radxa/zero3-rk3566/Makefile
new file mode 100644
index ..b28b58ed5d87
--- /dev/null
+++ b/board/radxa/zero3-rk3566/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += zero3-rk3566.o
diff --git a/board/radxa/zero3-rk3566/zero3-rk3566.c 
b/board/radxa/zero3-rk3566/zero3-rk3566.c
new file mode 100644
index ..cf30c4e38987
--- /dev/null
+++ b/board/radxa/zero3-rk3566/zero3-rk3566.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+
+#define HW_ID_CHANNEL  1
+
+struct board_model {
+   unsigned int low;
+   unsigned int high;
+

Re: [PATCH v4] board: rockchip: add Radxa ROCK 3 Model C

2024-07-31 Thread FUKAUMI Naoki


Hi,

please cherry-pick below too
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/commit/src/arm64/rockchip/rk3566-rock-3c.dts?h=v6.11-rc1-dts&id=dd40945a1d0e28ae6eaf9da04f8e2dcebf8233ea

On 7/22/24 19:56, Maxim Moskalets wrote:

Based on rock-3a-rk3568_defconfig.
Tested on v1.31 revision.

Board Specifications:
- Rockchip RK3566
- 1/2/4GB LPDDR4 2112MT/s
- eMMC socket
- uSD card slot
- M.2 2230 Connector
- GbE LAN with POE


I saw "Waiting for PHY auto negotiation to complete.." message few 
seconds when trying to ping on u-boot.

it doesn't happen on RadxaZERO 3E

does it happen on your board?


- 3.5mm jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host


OTG is USB2.0 (upper) port
https://radxa.com/products/rock3/3c/#techspec

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


- 40-pin GPIO expansion ports

Signed-off-by: Maxim Moskalets 
Suggested-by: Jonas Karlman 
Reviewed-by: Jonas Karlman 
---
v4:
fixed typo in commit-msg
moved maintainers record to file for rk3568 boards
renamed from ROCK 3 Model C to ROCK3C
v3:
add suggested by Jonas Karlman  in

https://lore.kernel.org/all/bbb81dd1-e318-423d-8258-db7556ce6...@kwiboo.se/
v2:
rebase to updated upstream dts
---
  arch/arm/dts/rk3566-rock-3c-u-boot.dtsi | 10 +++
  board/rockchip/evb_rk3568/MAINTAINERS   |  7 ++
  configs/rock-3c-rk3566_defconfig| 97 +
  doc/board/rockchip/rockchip.rst |  1 +
  4 files changed, 115 insertions(+)
  create mode 100644 arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
  create mode 100644 configs/rock-3c-rk3566_defconfig

diff --git a/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi 
b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
new file mode 100644
index 000..fd7f5367b75
--- /dev/null
+++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sfc {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS 
b/board/rockchip/evb_rk3568/MAINTAINERS
index e5b0986ead9..ba4884db8e1 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -69,3 +69,10 @@ S:   Maintained
  F:configs/rock-3a-rk3568_defconfig
  F:arch/arm/dts/rk3568-rock-3a.dts
  F:arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+
+ROCK-3C
+M: Jonas Karlman 
+M: Maxim Moskalets 
+S: Maintained
+F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
+F: configs/rock-3c-rk3566_defconfig
diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig
new file mode 100644
index 000..f44b202c8c3
--- /dev/null
+++ b/configs/rock-3c-rk3566_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE66
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROC

Re: [PATCH v2 1/3] configs: rockchip: reduce diff for rk3308, rk3328, rk3399, rk3568, and rk3588

2024-07-16 Thread FUKAUMI Naoki


Hi

On 7/17/24 13:31, Kever Yang wrote:

Hi Naoki,

On 2024/6/18 17:53, FUKAUMI Naoki wrote:

this is cosmetic change. no functional change is intended.

- remove redundant white spaces
- replace white spaces with tab
- align position of last letter/word
- sort lines in CFG_EXTRA_ENV_SETTINGS
- add comment after #endif

Signed-off-by: FUKAUMI Naoki

Changes in v2:
- rewrite whole commit message


1. I can't find the 3/3 in the list, I don't know the reason;


I sent v3 just now. I wish 3/3 will be arrived this time ;)

2. How do you generate the change log here? This format is not correct 
because it will be applied in the patch;


I think you miss separator "---" after signature.


yes, thanks for pointing. it will be fixed in v3.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


Thanks,

- Kever


---
  include/configs/rk3308_common.h | 26 ++---
  include/configs/rk3328_common.h | 28 +++
  include/configs/rk3399_common.h | 40 -
  include/configs/rk3568_common.h | 14 ++--
  include/configs/rk3588_common.h | 12 +-
  5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 861154fbeb..80113220e4 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -8,24 +8,24 @@
  
  #include "rockchip-common.h"
  
-#define CFG_IRAM_BASE		0xfff8

+#define CFG_IRAM_BASE  0xfff8
  
  #define CFG_SYS_SDRAM_BASE		0

  #define SDRAM_MAX_SIZE0xff00
  
-#define ENV_MEM_LAYOUT_SETTINGS \

-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x03e0\0" \
-   "fdtoverlay_addr_r=0x03f0\0" \
-   "kernel_addr_r=0x0068\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0" \
+   "pxefile_addr_r=0x0060\0" \
+   "fdt_addr_r=0x03e0\0" \
+   "fdtoverlay_addr_r=0x03f0\0"  \
+   "kernel_addr_r=0x0068\0"  \
"ramdisk_addr_r=0x0400\0"
  
-#define CFG_EXTRA_ENV_SETTINGS \

-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT   \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
  
-#endif

+#endif /* __CONFIG_RK3308_COMMON_H */
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2c40674b22..f9e6634c5f 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,25 +8,25 @@
  
  #include "rockchip-common.h"
  
-#define CFG_IRAM_BASE		0xff09

+#define CFG_IRAM_BASE  0xff09
  
  #define CFG_SYS_SDRAM_BASE		0

  #define SDRAM_MAX_SIZE0xff00
  
-#define ENV_MEM_LAYOUT_SETTINGS \

-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \
-   "kernel_comp_addr_r=0x0800\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0" \
+   "pxefile_addr_r=0x0060\0" \
+   "fdt_addr_r=0x01f0\0" \
+   "kernel_addr_r=0x0208\0"  \
+   "ramdisk_addr_r=0x0600\0" \
+   "kernel_comp_addr_r=0x0800\0" \
"kernel_comp_size=0x200\0"
  
-#define CFG_EXTRA_ENV_SETTINGS \

-   ENV_MEM_LAYOUT_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT   \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
  
-#endif

+#endif /* __CONFIG_RK3328_COMMON_H */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 4e75771055..62007c8b27 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -8,36 +8,36 @@
  
  #include "rockchip-common.h"
  
-#define CFG_IRAM_BASE		0xff8c

+#define CFG_IRAM_BASE  0xff8c

[PATCH v3 1/3] configs: rockchip: reduce diff for rk3308, rk3328, rk3399, rk3568, and rk3588

2024-07-16 Thread FUKAUMI Naoki

this is cosmetic change. no functional change is intended.

- remove redundant white spaces
- replace white spaces with tab
- align position of last letter/word
- sort lines in CFG_EXTRA_ENV_SETTINGS
- add comment after #endif

Signed-off-by: FUKAUMI Naoki 
Reviewed-by: Kever Yang 
---
Changes in v3:
- add missing separator in commit message
- collect R-b tag
Changes in v2:
- rewrite whole commit message
---
 include/configs/rk3308_common.h | 26 ++---
 include/configs/rk3328_common.h | 28 +++
 include/configs/rk3399_common.h | 40 -
 include/configs/rk3568_common.h | 14 ++--
 include/configs/rk3588_common.h | 12 +-
 5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 861154fbeb..80113220e4 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -8,24 +8,24 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xfff8
+#define CFG_IRAM_BASE  0xfff8
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xff00
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x03e0\0" \
-   "fdtoverlay_addr_r=0x03f0\0" \
-   "kernel_addr_r=0x0068\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x03e0\0"   \
+   "fdtoverlay_addr_r=0x03f0\0"\
+   "kernel_addr_r=0x0068\0"\
"ramdisk_addr_r=0x0400\0"
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
 
-#endif
+#endif /* __CONFIG_RK3308_COMMON_H */
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2c40674b22..f9e6634c5f 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,25 +8,25 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xff09
+#define CFG_IRAM_BASE  0xff09
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xff00
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \
-   "kernel_comp_addr_r=0x0800\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x01f0\0"   \
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
"kernel_comp_size=0x200\0"
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
 
-#endif
+#endif /* __CONFIG_RK3328_COMMON_H */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 4e75771055..62007c8b27 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -8,36 +8,36 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xff8c
+#define CFG_IRAM_BASE  0xff8c
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xf800
 
 #ifndef CONFIG_SPL_BUILD
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "script_offset_f=0xffe000\0" \
-   "script_size_f=0x2000\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "fdtoverlay_add

[PATCH v3 2/3] configs: rockchip: sync ENV_MEM_LAYOUT_SETTINGS for rk3308, rk3328, and rk3399

2024-07-16 Thread FUKAUMI Naoki

- add support for compressed kernel for rk3308
- prepare support for fdtoverlay for rk3328

tested on ROCK Pi S 256MB, ROCK Pi E 2GB, and ROCK Pi 4A 4GB with
linux-next-20240613 defconfig kernel.

Signed-off-by: FUKAUMI Naoki 
Reviewed-by: Kever Yang 
---
Changes in v3:
- add missing separator in commit message
- collect R-b tag
Changes in v2:
- minor cosmetic change in commit message
---
 include/configs/rk3308_common.h | 12 
 include/configs/rk3328_common.h |  5 -
 include/configs/rk3399_common.h |  4 ++--
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 80113220e4..2de55538fd 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -15,11 +15,15 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS\
"scriptaddr=0x0050\0"   \
+   "script_offset_f=0xffe000\0"\
+   "script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x03e0\0"   \
-   "fdtoverlay_addr_r=0x03f0\0"\
-   "kernel_addr_r=0x0068\0"\
-   "ramdisk_addr_r=0x0400\0"
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
+   "kernel_comp_size=0x200\0"
 
 #define CFG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index f9e6634c5f..bd2bfe2910 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -15,8 +15,11 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS\
"scriptaddr=0x0050\0"   \
+   "script_offset_f=0xffe000\0"\
+   "script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x01f0\0"   \
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
"kernel_addr_r=0x0208\0"\
"ramdisk_addr_r=0x0600\0"   \
"kernel_comp_addr_r=0x0800\0"   \
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 62007c8b27..d652ae4ca3 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -24,8 +24,8 @@
"script_offset_f=0xffe000\0"\
"script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x01f0\0"   \
-   "fdtoverlay_addr_r=0x0200\0"\
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
"kernel_addr_r=0x0208\0"\
"ramdisk_addr_r=0x0600\0"   \
"kernel_comp_addr_r=0x0800\0"   \
-- 
2.43.0

[PATCH v3 3/3] configs: rockchip: imply OF_LIBFDT_OVERLAY for rk3308 and rk3328

2024-07-16 Thread FUKAUMI Naoki

for rk3308, all defconfigs have CONFIG_OF_LIBFDT_OVERLAY=y, so enable it
by default.

for rk3328, any defconfig doesn't have it. but there is no strong reason
not to enable it. at least it's required for ROCK Pi E.

Signed-off-by: FUKAUMI Naoki 
---
Changes in v3:
- add missing separator in commit message
Changes in v2:
- none
---
 arch/arm/mach-rockchip/Kconfig | 2 ++
 configs/evb-rk3308_defconfig   | 1 -
 configs/roc-cc-rk3308_defconfig| 1 -
 configs/rock-pi-s-rk3308_defconfig | 1 -
 4 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 661e7fd1c9..5f6a4dd24a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -166,6 +166,7 @@ config ROCKCHIP_RK3308
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_UPSTREAM
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
@@ -196,6 +197,7 @@ config ROCKCHIP_RK3328
imply ARMV8_SET_SMPEN
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_LIVE
imply OF_UPSTREAM
imply PRE_CONSOLE_BUFFER
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index f4c2ea12ad..6d090dba30 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_EVB_RK3308=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 862ea4301f..b1b59d9cb5 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -4,7 +4,6 @@ CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_ROC_RK3308_CC=y
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index c15ba3d8a4..e450a06180 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_EVB_RK3308=y
-- 
2.43.0

Re: [PATCH] rockchip: include cru_rk3588.h and define rockchip_cru for RK3588

2024-07-15 Thread FUKAUMI Naoki


hi

On 6/19/24 05:39, FUKAUMI Naoki wrote:
> sorry,
>
> On 6/19/24 05:29, FUKAUMI Naoki wrote:
>> Hello,
>>
>> this happens only if HOSTCC=clang. I can see several other errors on
>> several other targets with HOSTCC=clang.
>
> ^this happens only if clang is used at make foo-bar_defconfig stage.
>
> it seems
>
> make foo-bar_defconfig
> make HOSTCC=clang CC=clang all
>
> works.
>
>> CC=clang seems to be fine.
>>
>> Best regards,
>>
>> --
>> FUKAUMI Naoki
>> Radxa Computer (Shenzhen) Co., Ltd.

should I check/make patches for other RK3xxx targets?
or should I avoid to use clang for defconfig?

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 7/16/24 11:09, Kever Yang wrote:


On 2024/6/19 03:30, FUKAUMI Naoki wrote:

fix following error found by clang:

   CC  arch/arm/mach-rockchip/cpu-info.o
arch/arm/mach-rockchip/cpu-info.c:23:13: error: incomplete definition 
of type 'struct rockchip_cru'

    23 | switch (cru->glb_rst_st) {
   | ~~~^
./arch/arm/include/asm/arch-rockchip/clock.h:181:8: note: forward 
declaration of 'struct rockchip_cru'

   181 | struct rockchip_cru;
   |    ^
1 error generated.

Signed-off-by: FUKAUMI Naoki 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  arch/arm/include/asm/arch-rockchip/cru.h    | 2 ++
  arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
  2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h

index 9778790f34..c3259b8e7c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -17,6 +17,8 @@
  # include 
  #elif defined(CONFIG_ROCKCHIP_RK3568)
  #include 
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include 
  #endif
  /* CRU_GLB_RST_ST */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h

index a0e54d3965..dad484813f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -92,6 +92,8 @@ struct rk3588_cru {
  unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
  };
+#define rockchip_cru rk3588_cru
+
  check_member(rk3588_cru, mode_con00, 0x280);
  check_member(rk3588_cru, pmuclksel_con[1], 0x30304);

[PATCH] rockchip: add support for Radxa ROCK Pi E v3.0

2024-06-24 Thread FUKAUMI Naoki

ROCK Pi E v3.0 uses DDR4 SDRAM instead of DDR3 SDRAM used in v1.2x.

prepare new rk3328-rock-pi-e-v3.dts in u-boot which just includes
upstream rk3328-rock-pi-e.dts.

defconfig still uses
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"

because v3.0 and prior are compatible.

Suggested-by: Jonas Karlman 
Signed-off-by: FUKAUMI Naoki 
---
 ...dtsi => rk3328-rock-pi-e-base-u-boot.dtsi} |  1 -
 arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 47 +
 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi  |  4 +
 arch/arm/dts/rk3328-rock-pi-e-v3.dts  |  4 +
 board/rockchip/evb_rk3328/MAINTAINERS |  4 +-
 configs/rock-pi-e-v3-rk3328_defconfig | 97 +++
 6 files changed, 111 insertions(+), 46 deletions(-)
 copy arch/arm/dts/{rk3328-rock-pi-e-u-boot.dtsi => 
rk3328-rock-pi-e-base-u-boot.dtsi} (94%)
 rewrite arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi (88%)
 create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3.dts
 create mode 100644 configs/rock-pi-e-v3-rk3328_defconfig

diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
similarity index 94%
copy from arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
copy to arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
index d314bfad6f..39bb66c4fc 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
@@ -4,7 +4,6 @@
  */
 
 #include "rk3328-u-boot.dtsi"
-#include "rk3328-sdram-ddr3-666.dtsi"
 
 / {
smbios {
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
dissimilarity index 88%
index d314bfad6f..8e82f6a6f1 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -1,43 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2020 Radxa
- */
-
-#include "rk3328-u-boot.dtsi"
-#include "rk3328-sdram-ddr3-666.dtsi"
-
-/ {
-   smbios {
-   compatible = "u-boot,sysinfo-smbios";
-
-   smbios {
-   system {
-   manufacturer = "radxa";
-   product = "rock-pi-e_rk3328";
-   };
-
-   baseboard {
-   manufacturer = "radxa";
-   product = "rock-pi-e_rk3328";
-   };
-
-   chassis {
-   manufacturer = "radxa";
-   product = "rock-pi-e_rk3328";
-   };
-   };
-   };
-};
-
-&u2phy_host {
-   phy-supply = <&vcc_host_5v>;
-};
-
-&vcc_host_5v {
-   /delete-property/ regulator-always-on;
-   /delete-property/ regulator-boot-on;
-};
-
-&vcc_sd {
-   bootph-pre-ram;
-};
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3328-rock-pi-e-base-u-boot.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
new file mode 100644
index 00..4d89ae54e6
--- /dev/null
+++ b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3328-rock-pi-e-base-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3.dts 
b/arch/arm/dts/rk3328-rock-pi-e-v3.dts
new file mode 100644
index 00..f1c1c36a99
--- /dev/null
+++ b/arch/arm/dts/rk3328-rock-pi-e-v3.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3328-rock-pi-e.dts"
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS 
b/board/rockchip/evb_rk3328/MAINTAINERS
index 675b72dd06..8f619e54e0 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -64,5 +64,5 @@ M:  Banglang Huang 
 R:  Jonas Karlman 
 S:  Maintained
 F:  configs/rock-pi-e-rk3328_defconfig
-F:  arch/arm/dts/rk3328-rock-pi-e.dts
-F:  arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+F:  configs/rock-pi-e-v3-rk3328_defconfig
+F:  arch/arm/dts/rk3328-rock-pi-e*
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig 
b/configs/rock-pi-e-v3-rk3328_defconfig
new file mode 100644
index 00..4c6cc634bd
--- /dev/null
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=2000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_DEBUG_UART_BASE=0xFF13
+CONFIG_DEBUG_UART_CLOCK=2400

Re: [RFC] rockchip: add support for Radxa ROCK Pi E v3.0 which uses DDR4 SDRAM

2024-06-23 Thread FUKAUMI Naoki

Hi,

thank you for your comment!

On 6/24/24 05:22, Dragan Simic wrote:

+Cc: he...@sntech.de
+Cc: k...@kernel.org

Hello Peter and Fukaumi,

On 2024-06-23 15:08, Peter Robinson wrote:

On Sun, 23 Jun 2024 at 13:21, Dragan Simic  wrote:

On 2024-06-23 06:15, FUKAUMI Naoki wrote:
> rk3328-rock-pi-e-v3.dts is identical to rk3328-rock-pi-e.dts in
> upstream. only difference between v3.0 and prior ver. is, using
> rk3328-sdram-ddr4-666.dtsi instead of rk3328-sdram-ddr3-666.dtsi.

I think you'll need to get the device tree resolved on the Linux
kernel side first, and then imported into U-Boot following the
rules of the OF_UPSTREAM approach.

I think the question was more "given the only difference between the
two is the memory is there a way we can do a single U-Boot build that
supports both" and I think the answer to that is unfortunately no,
even if the DT, config etc are all the same. I would be interested if
you come up with a solution as I have a couple of devices like this.

Good point.  Maybe we could employ an approach similar to how the
bad CPU cores will be disabled by U-Boot on RK3582.  Though, is it
even possible to detect the board revision on the ROCK Pi E, e.g.
by reading the statuses of some GPIO lines that encode the board
revision?  I went quickly through the v3.0 schematic and haven't
spotted anything like that.

unfortunately there is nothing which encode the board revision...
(zero3e/3w and rock3c have it. hopefully new products do the same)

as you know, I'm preparing new dts for v3 for upstream.

https://lore.kernel.org/linux-rockchip/20240623201415.3205-1-na...@radxa.com/T/#t

I'll send new patch for u-boot after above patch is merged.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

> here is console output from ROCK Pi E v3.0:
>
> ```
> U-Boot TPL 2024.07-rc4-dirty (Jun 23 2024 - 12:53:09)
> DDR4, 333MHz
> BW=32 Col=10 Bk=4 BG=2 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> U-Boot SPL 2024.07-rc4-dirty (Jun 23 2024 - 12:53:09 +0900)
> Trying to boot from MMC2
> ```
>
> there is an another way which can share same u-boot-rockchip.bin
> between v3 and prior, using ddr blob from Rockchip instead of TPL in
> U-Boot. is it acceptable?
>
> Signed-off-by: FUKAUMI Naoki 
> ---
>  arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi |   43 +
>  arch/arm/dts/rk3328-rock-pi-e-v3.dts |  445 
>  arch/arm/dts/rk3328.dtsi | 1943 
++

>  configs/rock-pi-e-v3-rk3328_defconfig    |   97 +
>  4 files changed, 2528 insertions(+)
>  create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
>  create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3.dts
>  create mode 100644 arch/arm/dts/rk3328.dtsi
>  create mode 100644 configs/rock-pi-e-v3-rk3328_defconfig

[snip]

[RFC] rockchip: add support for Radxa ROCK Pi E v3.0 which uses DDR4 SDRAM

2024-06-22 Thread FUKAUMI Naoki

rk3328-rock-pi-e-v3.dts is identical to rk3328-rock-pi-e.dts in
upstream. only difference between v3.0 and prior ver. is, using
rk3328-sdram-ddr4-666.dtsi instead of rk3328-sdram-ddr3-666.dtsi.

here is console output from ROCK Pi E v3.0:

```
U-Boot TPL 2024.07-rc4-dirty (Jun 23 2024 - 12:53:09)
DDR4, 333MHz
BW=32 Col=10 Bk=4 BG=2 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2024.07-rc4-dirty (Jun 23 2024 - 12:53:09 +0900)
Trying to boot from MMC2
```

there is an another way which can share same u-boot-rockchip.bin
between v3 and prior, using ddr blob from Rockchip instead of TPL in
U-Boot. is it acceptable?

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi |   43 +
 arch/arm/dts/rk3328-rock-pi-e-v3.dts |  445 
 arch/arm/dts/rk3328.dtsi | 1943 ++
 configs/rock-pi-e-v3-rk3328_defconfig|   97 +
 4 files changed, 2528 insertions(+)
 create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3.dts
 create mode 100644 arch/arm/dts/rk3328.dtsi
 create mode 100644 configs/rock-pi-e-v3-rk3328_defconfig

diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
new file mode 100644
index 00..d7b22b01d7
--- /dev/null
+++ b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Radxa
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+
+/ {
+   smbios {
+   compatible = "u-boot,sysinfo-smbios";
+
+   smbios {
+   system {
+   manufacturer = "radxa";
+   product = "rock-pi-e_rk3328";
+   };
+
+   baseboard {
+   manufacturer = "radxa";
+   product = "rock-pi-e_rk3328";
+   };
+
+   chassis {
+   manufacturer = "radxa";
+   product = "rock-pi-e_rk3328";
+   };
+   };
+   };
+};
+
+&u2phy_host {
+   phy-supply = <&vcc_host_5v>;
+};
+
+&vcc_host_5v {
+   /delete-property/ regulator-always-on;
+   /delete-property/ regulator-boot-on;
+};
+
+&vcc_sd {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3.dts 
b/arch/arm/dts/rk3328-rock-pi-e-v3.dts
new file mode 100644
index 00..3cda6c627b
--- /dev/null
+++ b/arch/arm/dts/rk3328-rock-pi-e-v3.dts
@@ -0,0 +1,445 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2020 Chen-Yu Tsai 
+ *
+ * Based on ./rk3328-rock64.dts, which is
+ *
+ * Copyright (c) 2017 PINE64
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include 
+
+#include "rk3328.dtsi"
+
+/ {
+   model = "Radxa ROCK Pi E";
+   compatible = "radxa,rockpi-e", "rockchip,rk3328";
+
+   aliases {
+   ethernet0 = &gmac2io;
+   ethernet1 = &gmac2phy;
+   mmc0 = &sdmmc;
+   mmc1 = &emmc;
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   adc-keys {
+   compatible = "adc-keys";
+   io-channels = <&saradc 0>;
+   io-channel-names = "buttons";
+   keyup-threshold-microvolt = <175>;
+
+   /* This button is unpopulated out of the factory. */
+   button-recovery {
+   label = "Recovery";
+   linux,code = ;
+   press-threshold-microvolt = <1>;
+   };
+   };
+
+   gmac_clkin: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "gmac_clkin";
+   #clock-cells = <0>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-0 = <&led_pin>;
+   pinctrl-names = "default";
+
+   led-0 {
+   color = ;
+   gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc_sd: sdmmc-regulator {
+   compatible = "regulator-fixed";
+   gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sdmmc0m1_pin>;
+

Re: [PATCH] rockchip: include cru_rk3588.h and define rockchip_cru for RK3588

2024-06-18 Thread FUKAUMI Naoki


sorry,

On 6/19/24 05:29, FUKAUMI Naoki wrote:

Hello,

this happens only if HOSTCC=clang. I can see several other errors on 
several other targets with HOSTCC=clang.


^this happens only if clang is used at make foo-bar_defconfig stage.

it seems

make foo-bar_defconfig
make HOSTCC=clang CC=clang all

works.


CC=clang seems to be fine.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 6/19/24 04:30, FUKAUMI Naoki wrote:

fix following error found by clang:

   CC  arch/arm/mach-rockchip/cpu-info.o
arch/arm/mach-rockchip/cpu-info.c:23:13: error: incomplete definition 
of type 'struct rockchip_cru'

    23 | switch (cru->glb_rst_st) {
   | ~~~^
./arch/arm/include/asm/arch-rockchip/clock.h:181:8: note: forward 
declaration of 'struct rockchip_cru'

   181 | struct rockchip_cru;
   |    ^
1 error generated.

Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/include/asm/arch-rockchip/cru.h    | 2 ++
  arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
  2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h

index 9778790f34..c3259b8e7c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -17,6 +17,8 @@
  # include 
  #elif defined(CONFIG_ROCKCHIP_RK3568)
  #include 
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include 
  #endif
  /* CRU_GLB_RST_ST */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h

index a0e54d3965..dad484813f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -92,6 +92,8 @@ struct rk3588_cru {
  unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
  };
+#define rockchip_cru rk3588_cru
+
  check_member(rk3588_cru, mode_con00, 0x280);
  check_member(rk3588_cru, pmuclksel_con[1], 0x30304);

Re: [PATCH] rockchip: include cru_rk3588.h and define rockchip_cru for RK3588

2024-06-18 Thread FUKAUMI Naoki


Hello,

this happens only if HOSTCC=clang. I can see several other errors on 
several other targets with HOSTCC=clang.


CC=clang seems to be fine.

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

On 6/19/24 04:30, FUKAUMI Naoki wrote:

fix following error found by clang:

   CC  arch/arm/mach-rockchip/cpu-info.o
arch/arm/mach-rockchip/cpu-info.c:23:13: error: incomplete definition of type 
'struct rockchip_cru'
23 | switch (cru->glb_rst_st) {
   | ~~~^
./arch/arm/include/asm/arch-rockchip/clock.h:181:8: note: forward declaration 
of 'struct rockchip_cru'
   181 | struct rockchip_cru;
   |^
1 error generated.

Signed-off-by: FUKAUMI Naoki 
---
  arch/arm/include/asm/arch-rockchip/cru.h| 2 ++
  arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
  2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 9778790f34..c3259b8e7c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -17,6 +17,8 @@
  # include 
  #elif defined(CONFIG_ROCKCHIP_RK3568)
  #include 
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include 
  #endif
  
  /* CRU_GLB_RST_ST */

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a0e54d3965..dad484813f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -92,6 +92,8 @@ struct rk3588_cru {
unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
  };
  
+#define rockchip_cru rk3588_cru

+
  check_member(rk3588_cru, mode_con00, 0x280);
  check_member(rk3588_cru, pmuclksel_con[1], 0x30304);

[PATCH] rockchip: include cru_rk3588.h and define rockchip_cru for RK3588

2024-06-18 Thread FUKAUMI Naoki

fix following error found by clang:

  CC  arch/arm/mach-rockchip/cpu-info.o
arch/arm/mach-rockchip/cpu-info.c:23:13: error: incomplete definition of type 
'struct rockchip_cru'
   23 | switch (cru->glb_rst_st) {
  | ~~~^
./arch/arm/include/asm/arch-rockchip/clock.h:181:8: note: forward declaration 
of 'struct rockchip_cru'
  181 | struct rockchip_cru;
  |^
1 error generated.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/include/asm/arch-rockchip/cru.h| 2 ++
 arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 9778790f34..c3259b8e7c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -17,6 +17,8 @@
 # include 
 #elif defined(CONFIG_ROCKCHIP_RK3568)
 #include 
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a0e54d3965..dad484813f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -92,6 +92,8 @@ struct rk3588_cru {
unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
 };
 
+#define rockchip_cru rk3588_cru
+
 check_member(rk3588_cru, mode_con00, 0x280);
 check_member(rk3588_cru, pmuclksel_con[1], 0x30304);
 
-- 
2.43.0

Re: [PATCH 1/3] configs: rockchip: cosmetic changes for rk3308, rk3328, rk3399, rk3568, and rk3588

2024-06-18 Thread FUKAUMI Naoki


hi

On 6/18/24 18:18, Peter Robinson wrote:

On Tue, 18 Jun 2024 at 02:06, FUKAUMI Naoki  wrote:


no functional change is intended.


Can you please explain what the patch is doing then, the subject of
"cosmetic changes for rk3308, rk3328, rk3399, rk3568, and rk3588"
doesn't really explain it either. Something like "adjust indentation
for consistency" or what the patch actually does is useful.


thank you very much for your reply!

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.


Signed-off-by: FUKAUMI Naoki 
---
  include/configs/rk3308_common.h | 26 ++---
  include/configs/rk3328_common.h | 28 +++
  include/configs/rk3399_common.h | 40 -
  include/configs/rk3568_common.h | 14 ++--
  include/configs/rk3588_common.h | 12 +-
  5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 861154fbeb..80113220e4 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -8,24 +8,24 @@

  #include "rockchip-common.h"

-#define CFG_IRAM_BASE  0xfff8
+#define CFG_IRAM_BASE  0xfff8

  #define CFG_SYS_SDRAM_BASE 0
  #define SDRAM_MAX_SIZE 0xff00

-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x03e0\0" \
-   "fdtoverlay_addr_r=0x03f0\0" \
-   "kernel_addr_r=0x0068\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x03e0\0"   \
+   "fdtoverlay_addr_r=0x03f0\0"\
+   "kernel_addr_r=0x0068\0"\
 "ramdisk_addr_r=0x0400\0"

-#define CFG_EXTRA_ENV_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
 "boot_targets=" BOOT_TARGETS "\0"

-#endif
+#endif /* __CONFIG_RK3308_COMMON_H */
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2c40674b22..f9e6634c5f 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,25 +8,25 @@

  #include "rockchip-common.h"

-#define CFG_IRAM_BASE  0xff09
+#define CFG_IRAM_BASE  0xff09

  #define CFG_SYS_SDRAM_BASE 0
  #define SDRAM_MAX_SIZE 0xff00

-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \
-   "kernel_comp_addr_r=0x0800\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x01f0\0"   \
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
 "kernel_comp_size=0x200\0"

-#define CFG_EXTRA_ENV_SETTINGS \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
 "boot_targets=" BOOT_TARGETS "\0"

-#endif
+#endif /* __CONFIG_RK3328_COMMON_H */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 4e75771055..62007c8b27 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -8,36 +8,36 @@

  #include "rockchip-common.h"

-#define CFG_IRAM_BASE  0xff8c
+#define CFG_IRAM_BASE  0xff8c

  #define CFG_SYS_SDRAM_BASE 0
  #define SDRAM_MAX_SIZE 0xf800

  #ifndef CONFIG_SPL_BUILD

-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "script_offset_f=0xffe000\0" \
-   "script_size_f=0x200

[PATCH v2 3/3] configs: rockchip: imply OF_LIBFDT_OVERLAY for rk3308 and rk3328

2024-06-18 Thread FUKAUMI Naoki

for rk3308, all defconfigs have CONFIG_OF_LIBFDT_OVERLAY=y, so enable it
by default.

for rk3328, any defconfig doesn't have it. but there is no strong reason
not to enable it. at least it's required for ROCK Pi E.

Signed-off-by: FUKAUMI Naoki 

Changes in v2:
- none
---
 arch/arm/mach-rockchip/Kconfig | 2 ++
 configs/evb-rk3308_defconfig   | 1 -
 configs/roc-cc-rk3308_defconfig| 1 -
 configs/rock-pi-s-rk3308_defconfig | 1 -
 4 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 661e7fd1c9..5f6a4dd24a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -166,6 +166,7 @@ config ROCKCHIP_RK3308
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_UPSTREAM
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
@@ -196,6 +197,7 @@ config ROCKCHIP_RK3328
imply ARMV8_SET_SMPEN
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_LIVE
imply OF_UPSTREAM
imply PRE_CONSOLE_BUFFER
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index f4c2ea12ad..6d090dba30 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_EVB_RK3308=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 862ea4301f..b1b59d9cb5 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -4,7 +4,6 @@ CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_ROC_RK3308_CC=y
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index c15ba3d8a4..e450a06180 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_EVB_RK3308=y
-- 
2.43.0

[PATCH v2 1/3] configs: rockchip: reduce diff for rk3308, rk3328, rk3399, rk3568, and rk3588

2024-06-18 Thread FUKAUMI Naoki

this is cosmetic change. no functional change is intended.

- remove redundant white spaces
- replace white spaces with tab
- align position of last letter/word
- sort lines in CFG_EXTRA_ENV_SETTINGS
- add comment after #endif

Signed-off-by: FUKAUMI Naoki 

Changes in v2:
- rewrite whole commit message
---
 include/configs/rk3308_common.h | 26 ++---
 include/configs/rk3328_common.h | 28 +++
 include/configs/rk3399_common.h | 40 -
 include/configs/rk3568_common.h | 14 ++--
 include/configs/rk3588_common.h | 12 +-
 5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 861154fbeb..80113220e4 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -8,24 +8,24 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xfff8
+#define CFG_IRAM_BASE  0xfff8
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xff00
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x03e0\0" \
-   "fdtoverlay_addr_r=0x03f0\0" \
-   "kernel_addr_r=0x0068\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x03e0\0"   \
+   "fdtoverlay_addr_r=0x03f0\0"\
+   "kernel_addr_r=0x0068\0"\
"ramdisk_addr_r=0x0400\0"
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
 
-#endif
+#endif /* __CONFIG_RK3308_COMMON_H */
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2c40674b22..f9e6634c5f 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,25 +8,25 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xff09
+#define CFG_IRAM_BASE  0xff09
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xff00
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \
-   "kernel_comp_addr_r=0x0800\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x01f0\0"   \
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
"kernel_comp_size=0x200\0"
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
 
-#endif
+#endif /* __CONFIG_RK3328_COMMON_H */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 4e75771055..62007c8b27 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -8,36 +8,36 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xff8c
+#define CFG_IRAM_BASE  0xff8c
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xf800
 
 #ifndef CONFIG_SPL_BUILD
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "script_offset_f=0xffe000\0" \
-   "script_size_f=0x2000\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "fdtoverlay_addr_r=0x0200\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \

[PATCH v2 2/3] configs: rockchip: sync ENV_MEM_LAYOUT_SETTINGS for rk3308, rk3328, and rk3399

2024-06-18 Thread FUKAUMI Naoki

- add support for compressed kernel for rk3308
- prepare support for fdtoverlay for rk3328

tested on ROCK Pi S 256MB, ROCK Pi E 2GB, and ROCK Pi 4A 4GB with
linux-next-20240613 defconfig kernel.

Signed-off-by: FUKAUMI Naoki 

Changes in v2:
- minor cosmetic change in commit message
---
 include/configs/rk3308_common.h | 12 
 include/configs/rk3328_common.h |  5 -
 include/configs/rk3399_common.h |  4 ++--
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 80113220e4..2de55538fd 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -15,11 +15,15 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS\
"scriptaddr=0x0050\0"   \
+   "script_offset_f=0xffe000\0"\
+   "script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x03e0\0"   \
-   "fdtoverlay_addr_r=0x03f0\0"\
-   "kernel_addr_r=0x0068\0"\
-   "ramdisk_addr_r=0x0400\0"
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
+   "kernel_comp_size=0x200\0"
 
 #define CFG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index f9e6634c5f..bd2bfe2910 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -15,8 +15,11 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS\
"scriptaddr=0x0050\0"   \
+   "script_offset_f=0xffe000\0"\
+   "script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x01f0\0"   \
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
"kernel_addr_r=0x0208\0"\
"ramdisk_addr_r=0x0600\0"   \
"kernel_comp_addr_r=0x0800\0"   \
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 62007c8b27..d652ae4ca3 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -24,8 +24,8 @@
"script_offset_f=0xffe000\0"\
"script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x01f0\0"   \
-   "fdtoverlay_addr_r=0x0200\0"\
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
"kernel_addr_r=0x0208\0"\
"ramdisk_addr_r=0x0600\0"   \
"kernel_comp_addr_r=0x0800\0"   \
-- 
2.43.0

[PATCH 2/3] configs: rockchip: sync ENV_MEM_LAYOUT_SETTINGS for rk3308, rk3328, and rk3399

2024-06-17 Thread FUKAUMI Naoki

add support for compressed kernel for rk3308.
prepare support for fdtoverlay for rk3328.

tested on ROCK Pi S 256MB, ROCK Pi E 2GB, and ROCK Pi 4A 4GB with
linux-next-20240613 defconfig kernel.

Signed-off-by: FUKAUMI Naoki 
---
 include/configs/rk3308_common.h | 12 
 include/configs/rk3328_common.h |  5 -
 include/configs/rk3399_common.h |  4 ++--
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 80113220e4..2de55538fd 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -15,11 +15,15 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS\
"scriptaddr=0x0050\0"   \
+   "script_offset_f=0xffe000\0"\
+   "script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x03e0\0"   \
-   "fdtoverlay_addr_r=0x03f0\0"\
-   "kernel_addr_r=0x0068\0"\
-   "ramdisk_addr_r=0x0400\0"
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
+   "kernel_comp_size=0x200\0"
 
 #define CFG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index f9e6634c5f..bd2bfe2910 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -15,8 +15,11 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS\
"scriptaddr=0x0050\0"   \
+   "script_offset_f=0xffe000\0"\
+   "script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x01f0\0"   \
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
"kernel_addr_r=0x0208\0"\
"ramdisk_addr_r=0x0600\0"   \
"kernel_comp_addr_r=0x0800\0"   \
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 62007c8b27..d652ae4ca3 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -24,8 +24,8 @@
"script_offset_f=0xffe000\0"\
"script_size_f=0x2000\0"\
"pxefile_addr_r=0x0060\0"   \
-   "fdt_addr_r=0x01f0\0"   \
-   "fdtoverlay_addr_r=0x0200\0"\
+   "fdt_addr_r=0x01e0\0"   \
+   "fdtoverlay_addr_r=0x01f0\0"\
"kernel_addr_r=0x0208\0"\
"ramdisk_addr_r=0x0600\0"   \
"kernel_comp_addr_r=0x0800\0"   \
-- 
2.43.0

[PATCH 1/3] configs: rockchip: cosmetic changes for rk3308, rk3328, rk3399, rk3568, and rk3588

2024-06-17 Thread FUKAUMI Naoki

no functional change is intended.

Signed-off-by: FUKAUMI Naoki 
---
 include/configs/rk3308_common.h | 26 ++---
 include/configs/rk3328_common.h | 28 +++
 include/configs/rk3399_common.h | 40 -
 include/configs/rk3568_common.h | 14 ++--
 include/configs/rk3588_common.h | 12 +-
 5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 861154fbeb..80113220e4 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -8,24 +8,24 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xfff8
+#define CFG_IRAM_BASE  0xfff8
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xff00
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x03e0\0" \
-   "fdtoverlay_addr_r=0x03f0\0" \
-   "kernel_addr_r=0x0068\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x03e0\0"   \
+   "fdtoverlay_addr_r=0x03f0\0"\
+   "kernel_addr_r=0x0068\0"\
"ramdisk_addr_r=0x0400\0"
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
 
-#endif
+#endif /* __CONFIG_RK3308_COMMON_H */
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2c40674b22..f9e6634c5f 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,25 +8,25 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xff09
+#define CFG_IRAM_BASE  0xff09
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xff00
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \
-   "kernel_comp_addr_r=0x0800\0" \
+#define ENV_MEM_LAYOUT_SETTINGS\
+   "scriptaddr=0x0050\0"   \
+   "pxefile_addr_r=0x0060\0"   \
+   "fdt_addr_r=0x01f0\0"   \
+   "kernel_addr_r=0x0208\0"\
+   "ramdisk_addr_r=0x0600\0"   \
+   "kernel_comp_addr_r=0x0800\0"   \
"kernel_comp_size=0x200\0"
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   ENV_MEM_LAYOUT_SETTINGS \
-   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   "partitions=" PARTS_DEFAULT \
-   ROCKCHIP_DEVICE_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS\
"boot_targets=" BOOT_TARGETS "\0"
 
-#endif
+#endif /* __CONFIG_RK3328_COMMON_H */
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 4e75771055..62007c8b27 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -8,36 +8,36 @@
 
 #include "rockchip-common.h"
 
-#define CFG_IRAM_BASE  0xff8c
+#define CFG_IRAM_BASE  0xff8c
 
 #define CFG_SYS_SDRAM_BASE 0
 #define SDRAM_MAX_SIZE 0xf800
 
 #ifndef CONFIG_SPL_BUILD
 
-#define ENV_MEM_LAYOUT_SETTINGS \
-   "scriptaddr=0x0050\0" \
-   "script_offset_f=0xffe000\0" \
-   "script_size_f=0x2000\0" \
-   "pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
-   "fdtoverlay_addr_r=0x0200\0" \
-   "kernel_addr_r=0x0208\0" \
-   "ramdisk_addr_r=0x0600\0" \
-   "kernel_comp_addr_r=0x0800\0" \
-   "kernel_comp_size=0x200\0"
-
 #ifndef ROCKCHIP_DEVICE_SETTINGS
 #define ROCKCHIP_DEVICE_SETTINGS
 #endif
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   ENV_MEM

[PATCH 3/3] configs: rockchip: imply OF_LIBFDT_OVERLAY for rk3308 and rk3328

2024-06-17 Thread FUKAUMI Naoki

for rk3308, all defconfigs have CONFIG_OF_LIBFDT_OVERLAY=y, so enable it
by default.

for rk3328, any defconfig doesn't have it. but there is no strong reason
not to enable it. at least it's required for ROCK Pi E.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/mach-rockchip/Kconfig | 2 ++
 configs/evb-rk3308_defconfig   | 1 -
 configs/roc-cc-rk3308_defconfig| 1 -
 configs/rock-pi-s-rk3308_defconfig | 1 -
 4 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 661e7fd1c9..5f6a4dd24a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -166,6 +166,7 @@ config ROCKCHIP_RK3308
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_UPSTREAM
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
@@ -196,6 +197,7 @@ config ROCKCHIP_RK3328
imply ARMV8_SET_SMPEN
imply MISC
imply MISC_INIT_R
+   imply OF_LIBFDT_OVERLAY
imply OF_LIVE
imply OF_UPSTREAM
imply PRE_CONSOLE_BUFFER
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index f4c2ea12ad..6d090dba30 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_EVB_RK3308=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 862ea4301f..b1b59d9cb5 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -4,7 +4,6 @@ CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_ROC_RK3308_CC=y
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index c15ba3d8a4..e450a06180 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s"
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_TARGET_EVB_RK3308=y
-- 
2.43.0

Re: [PATCH 1/3] rockchip: rock-3a: rock5a: rock5b: add USB GADGET related configs

2024-06-16 Thread FUKAUMI Naoki


Hi,

On 6/16/24 18:24, Jonas Karlman wrote:

On 2024-06-15 09:46, FUKAUMI Naoki wrote:

add USB GADGET related configs for USB OTG port on ROCK 3A/5A/5B.

Signed-off-by: FUKAUMI Naoki 
---
  configs/rock-3a-rk3568_defconfig | 6 ++
  configs/rock5a-rk3588s_defconfig | 6 ++
  configs/rock5b-rk3588_defconfig  | 1 +
  3 files changed, 13 insertions(+)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7a..0568a73038 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_MMC=y
  CONFIG_CMD_PCI=y
  CONFIG_CMD_POWEROFF=y
  CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_CMD_PMIC=y
  CONFIG_CMD_REGULATOR=y
@@ -50,6 +52,7 @@ CONFIG_SPL_SYSCON=y
  CONFIG_SCSI_AHCI=y
  CONFIG_AHCI_PCI=y
  CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
  CONFIG_MISC=y
@@ -90,4 +93,7 @@ CONFIG_USB_OHCI_HCD=y
  CONFIG_USB_OHCI_GENERIC=y
  CONFIG_USB_DWC3=y
  CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
  CONFIG_ERRNO_STR=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index c09e6655f0..e06052cd80 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -27,6 +27,8 @@ CONFIG_CMD_GPT=y
  CONFIG_CMD_I2C=y
  CONFIG_CMD_MMC=y
  CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_CMD_REGULATOR=y
  # CONFIG_SPL_DOS_PARTITION is not set
@@ -37,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
  CONFIG_SPL_REGMAP=y
  CONFIG_SPL_SYSCON=y
  CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
  CONFIG_MISC=y
@@ -67,4 +70,7 @@ CONFIG_USB_OHCI_HCD=y
  CONFIG_USB_OHCI_GENERIC=y
  CONFIG_USB_DWC3=y
  CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y


I do not think there is any usb port that use dr_mode otg/peripheral,
so enabling gadget support probably have no impact on ROCK 5A.

Regards,
Jonas


my patch 2/3 doesn't add "dr_mode = "host";", so it will be "otg".
I may need to fix upstream dts first...

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.




  CONFIG_ERRNO_STR=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index fc118cea7b..80a2f2fed5 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y
  CONFIG_CMD_PCI=y
  CONFIG_CMD_USB=y
  CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_CMD_REGULATOR=y
  # CONFIG_SPL_DOS_PARTITION is not set

[PATCH 1/3] rockchip: rock-3a: rock5a: rock5b: add USB GADGET related configs

2024-06-15 Thread FUKAUMI Naoki

add USB GADGET related configs for USB OTG port on ROCK 3A/5A/5B.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock-3a-rk3568_defconfig | 6 ++
 configs/rock5a-rk3588s_defconfig | 6 ++
 configs/rock5b-rk3588_defconfig  | 1 +
 3 files changed, 13 insertions(+)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7a..0568a73038 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -50,6 +52,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SCSI_AHCI=y
 CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -90,4 +93,7 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index c09e6655f0..e06052cd80 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -27,6 +27,8 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -37,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -67,4 +70,7 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index fc118cea7b..80a2f2fed5 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
-- 
2.43.0

[PATCH 2/3] arm: dts: rockchip: rock-5a: enable USB3 OTG port

2024-06-15 Thread FUKAUMI Naoki

enable USB3 OTG (upper) port for ums and rockusb commands on ROCK 5A.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi 
b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
index efba0c359b..5ae1a3cdd9 100644
--- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
@@ -9,3 +9,19 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
 };
+
+&u2phy0 {
+   status = "okay";
+};
+
+&u2phy0_otg {
+   status = "okay";
+};
+
+&usbdp_phy0 {
+   status = "okay";
+};
+
+&usb_host0_xhci {
+   status = "okay";
+};
-- 
2.43.0

[PATCH 3/3] arm: dts: rockchip: rock-5b: sort usbdp_phy nodes

2024-06-15 Thread FUKAUMI Naoki

sort alphanumerically.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 8e318e624a..fabbd717b6 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -47,11 +47,11 @@
status = "okay";
 };
 
-&usbdp_phy1 {
+&usbdp_phy0 {
status = "okay";
 };
 
-&usbdp_phy0 {
+&usbdp_phy1 {
status = "okay";
 };
 
-- 
2.43.0

[PATCH] configs: rockchip: rock-pi-s: use default bootdelay (2s)

2023-09-11 Thread FUKAUMI Naoki

align with other boards.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock-pi-s-rk3308_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index cc3274a98b..cd0a996ee7 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -24,7 +24,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=0
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x2
-- 
2.39.2

[PATCH 1/2] configs: rockchip: rk3308: use CONFIG_DEFAULT_FDT_FILE

2023-09-11 Thread FUKAUMI Naoki

all rk3308 boards should use their own dtb file.

also, change fdt_addr_r to avoid following error:
 "ERROR: Did not find a cmdline Flattened Device Tree"
it happens on Radxa ROCK Pi S (256MB/512MB) with kernel built from
Radxa BSP.

Signed-off-by: FUKAUMI Naoki 
---
 configs/evb-rk3308_defconfig   | 1 +
 configs/roc-cc-rk3308_defconfig| 1 +
 configs/rock-pi-s-rk3308_defconfig | 1 +
 include/configs/rk3308_common.h| 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index a13a809c1e..2c7ac88ed9 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -24,6 +24,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=0
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 9a789b212f..9cb90f6ee6 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -24,6 +24,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=0
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index cc3274a98b..e2abe4b4f7 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -25,6 +25,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=0
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 7d55fcd975..a413af1bd4 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -16,11 +16,12 @@
 #define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x0050\0" \
"pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x0280\0" \
+   "fdt_addr_r=0x03e0\0" \
"kernel_addr_r=0x0068\0" \
"ramdisk_addr_r=0x0400\0"
 
 #define CFG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
ENV_MEM_LAYOUT_SETTINGS \
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
-- 
2.39.2

[PATCH 2/2] configs: rockchip: rk3308: enable CONFIG_OF_LIBFDT_OVERLAY

2023-09-11 Thread FUKAUMI Naoki

enable CONFIG_OF_LIBFDT_OVERLAY and use it on Radxa ROCK Pi S.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock-pi-s-rk3308_defconfig | 1 +
 include/configs/rk3308_common.h| 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index e2abe4b4f7..ca4a1800e7 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80
 CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3308=y
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index a413af1bd4..861154fbeb 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -17,6 +17,7 @@
"scriptaddr=0x0050\0" \
"pxefile_addr_r=0x0060\0" \
"fdt_addr_r=0x03e0\0" \
+   "fdtoverlay_addr_r=0x03f0\0" \
"kernel_addr_r=0x0068\0" \
"ramdisk_addr_r=0x0400\0"
 
-- 
2.39.2

Re: [PATCH v2 1/2] rockchip: Kconfig: Enable external TPL binary for rk3308

2023-09-11 Thread FUKAUMI Naoki


hi,

On 9/9/23 18:33, Massimo Pegorer wrote:

There is no support to initialize DRAM on rk3308 SoC using U-Boot
TPL or SPL, and therefore an external TPL binary must be used to
package a bootable u-boot-rockchip.bin image.

Default ROCKCHIP_EXTERNAL_TPL to yes if ROCKCHIP_RK3308.
Remove useless TPL_SERIAL.

Signed-off-by: Massimo Pegorer 
---
  arch/arm/mach-rockchip/Kconfig | 3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)


Tested-by: FUKAUMI Naoki 

thank you very much for your work!


diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a279582f4f..3b044269bd 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -166,7 +166,6 @@ config ROCKCHIP_RK3308
imply SPL_SYSCON
imply SPL_RAM
imply SPL_SERIAL
-   imply TPL_SERIAL
imply SPL_SEPARATE_BSS
help
  The Rockchip RK3308 is a ARM-based Soc which embedded with quad
@@ -436,7 +435,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
  
  config ROCKCHIP_EXTERNAL_TPL

bool "Use external TPL binary"
-   default y if ROCKCHIP_RK3568 || ROCKCHIP_RK3588
+   default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
help
  Some Rockchip SoCs require an external TPL to initialize DRAM.
  Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to

[PATCH v2 1/2] arm: dts: rockchip: sync DT for RK3588 series with Linux

2023-09-05 Thread FUKAUMI Naoki

Sync the device tree for RK3588 series with Linux 6.6-rc1.

Signed-off-by: FUKAUMI Naoki 
---
 .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi   |   1 -
 arch/arm/dts/rk3588-edgeble-neu6a.dtsi|   1 -
 .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi   |   6 -
 arch/arm/dts/rk3588-edgeble-neu6b-io.dts  |  66 ++
 arch/arm/dts/rk3588-edgeble-neu6b.dtsi| 359 -
 arch/arm/dts/rk3588-evb1-v10.dts  | 720 +-
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi   | 113 +--
 arch/arm/dts/rk3588-rock-5b.dts   | 448 ++-
 arch/arm/dts/rk3588.dtsi  | 215 ++
 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi  |  12 -
 arch/arm/dts/rk3588s-rock-5a.dts  | 665 +++-
 arch/arm/dts/rk3588s-u-boot.dtsi  | 162 
 arch/arm/dts/rk3588s.dtsi | 367 +
 include/dt-bindings/ata/ahci.h|  20 +
 14 files changed, 2866 insertions(+), 289 deletions(-)
 create mode 100644 include/dt-bindings/ata/ahci.h

diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 373f369c65..dd0058262b 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -11,7 +11,6 @@
};
 
chosen {
-   stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc;
};
 };
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
index 38e1a1e25f..727580aaa1 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
@@ -25,7 +25,6 @@
no-sdio;
no-sd;
non-removable;
-   max-frequency = <2>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index cd7626b24b..a45b3f5e86 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -11,12 +11,6 @@
};
 
chosen {
-   stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc;
};
 };
-
-&sdmmc {
-   bus-width = <4>;
-   status = "okay";
-};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts 
b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
index e9d5a8bab5..9933765e40 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
@@ -21,7 +21,73 @@
};
 };
 
+&combphy0_ps {
+   status = "okay";
+};
+
+&i2c6 {
+   status = "okay";
+
+   hym8563: rtc@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   interrupt-parent = <&gpio0>;
+   interrupts = ;
+   #clock-cells = <0>;
+   clock-output-names = "hym8563";
+   pinctrl-names = "default";
+   pinctrl-0 = <&hym8563_int>;
+   wakeup-source;
+   };
+};
+
+&pinctrl {
+   hym8563 {
+   hym8563_int: hym8563-int {
+   rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+   };
+};
+
+/* FAN */
+&pwm2 {
+   pinctrl-0 = <&pwm2m1_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
+&sata0 {
+   status = "okay";
+};
+
+&sdmmc {
+   bus-width = <4>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   disable-wp;
+   no-sdio;
+   no-mmc;
+   sd-uhs-sdr104;
+   vmmc-supply = <&vcc_3v3_s3>;
+   vqmmc-supply = <&vccio_sd_s0>;
+   status = "okay";
+};
+
 &uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
 };
+
+/* RS232 */
+&uart6 {
+   pinctrl-0 = <&uart6m0_xfer>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
+/* RS485 */
+&uart7 {
+   pinctrl-0 = <&uart7m2_xfer>;
+   pinctrl-names = "default";
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi 
b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
index 1c5bcf1280..017559bba3 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
@@ -18,6 +18,42 @@
regulator-min-microvolt = <1200>;
regulator-max-microvolt = <1200>;
};
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   reg

[PATCH v2 2/2] arm: dts: rockchip: rock-5b: add support for PCIe3 and NVMe

2023-09-05 Thread FUKAUMI Naoki

this patch adds support for PCIe3 (M.2 M key) and enables NVMe.

 => pci
 BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
 _
 00.00.00   0x1d87 0x3588 Bridge device   0x04
 01.00.00   0x10ec 0x8125 Network controller  0x00
 02.00.00   0x1d87 0x3588 Bridge device   0x04
 03.00.00   0x1179 0x011a Mass storage controller 0x08
 => nvme scan
 => nvme info
 Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN
 Type: Hard Disk
 Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)

Signed-off-by: FUKAUMI Naoki 

this patch depends:
- "rockchip: rk3568: Fix use of PCIe bifurcation" [1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=366997
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 33 +
 configs/rock5b-rk3588_defconfig |  1 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 03626e71ea..96cc84e5aa 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -23,6 +23,19 @@
regulator-max-microvolt = <1200>;
};
 
+   vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_pcie30";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   enable-active-high;
+   gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <5000>;
+   vin-supply = <&vcc5v0_sys>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pcie3_vcc3v3_en>;
+   };
+
vcc5v0_usbdcin: vcc5v0-usbdcin {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
@@ -71,6 +84,18 @@
status = "okay";
 };
 
+&pcie30phy {
+   status = "okay";
+};
+
+&pcie3x4 {
+   reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+   vpcie3v3-supply = <&vcc3v3_pcie30>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pcie3_rst>;
+   status = "okay";
+};
+
 &pinctrl {
pcie {
pcie_reset_h: pcie-reset-h {
@@ -81,6 +106,14 @@
rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
<3 RK_PD0 4 &pcfg_pull_none>;
};
+
+   pcie3_rst: pcie3-rst {
+   rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+   rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
};
 
usb-typec {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 3fa65cbf9b..50551c70f2 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -81,6 +81,7 @@ CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RTL8169=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-- 
2.39.2

[PATCH RESEND 1/2] arm: dts: rockchip: rk3588, rk3588s: sync with Linux

2023-08-31 Thread FUKAUMI Naoki

Sync the devicetree with linux-next tag: next-20230831

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588.dtsi   | 215 +++
 arch/arm/dts/rk3588s.dtsi  | 367 +
 include/dt-bindings/ata/ahci.h |  20 ++
 3 files changed, 602 insertions(+)
 create mode 100644 include/dt-bindings/ata/ahci.h

diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 8be75556af..5519c1430c 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -7,6 +7,16 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+   pcie30_phy_grf: syscon@fd5b8000 {
+   compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+   reg = <0x0 0xfd5b8000 0x0 0x1>;
+   };
+
+   pipe_phy1_grf: syscon@fd5c {
+   compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+   reg = <0x0 0xfd5c 0x0 0x100>;
+   };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -75,6 +85,159 @@
status = "disabled";
};
 
+   pcie3x4: pcie@fe15 {
+   compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0x0f>;
+   clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+   device_type = "pci";
+   interrupts = ,
+,
+,
+,
+;
+   interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+   <0 0 0 2 &pcie3x4_intc 1>,
+   <0 0 0 3 &pcie3x4_intc 2>,
+   <0 0 0 4 &pcie3x4_intc 3>;
+   linux,pci-domain = <0>;
+   max-link-speed = <3>;
+   msi-map = <0x &its1 0x 0x1000>;
+   num-lanes = <4>;
+   phys = <&pcie30phy>;
+   phy-names = "pcie-phy";
+   power-domains = <&power RK3588_PD_PCIE>;
+   ranges = <0x0100 0x0 0xf010 0x0 0xf010 0x0 
0x0010>,
+<0x0200 0x0 0xf020 0x0 0xf020 0x0 
0x00e0>,
+<0x0300 0x0 0x4000 0x9 0x 0x0 
0x4000>;
+   reg = <0xa 0x4000 0x0 0x0040>,
+ <0x0 0xfe15 0x0 0x0001>,
+ <0x0 0xf000 0x0 0x0010>;
+   reg-names = "dbi", "apb", "config";
+   resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+   reset-names = "pwr", "pipe";
+   status = "disabled";
+
+   pcie3x4_intc: legacy-interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-parent = <&gic>;
+   interrupts = ;
+   };
+   };
+
+   pcie3x2: pcie@fe16 {
+   compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x10 0x1f>;
+   clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+   device_type = "pci";
+   interrupts = ,
+,
+

[PATCH RESEND 2/2] arm: dts: rockchip: rock-5b: add support for PCIe3 and NVMe

2023-08-31 Thread FUKAUMI Naoki

this patch adds support for PCIe3 (M.2 M key) and enables NVMe.

 => pci
 BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
 _
 00.00.00   0x1d87 0x3588 Bridge device   0x04
 01.00.00   0x10ec 0x8125 Network controller  0x00
 02.00.00   0x1d87 0x3588 Bridge device   0x04
 03.00.00   0x1179 0x011a Mass storage controller 0x08
 => nvme scan
 => nvme info
 Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN
 Type: Hard Disk
 Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)

Signed-off-by: FUKAUMI Naoki 

this patch depends:
- "rockchip: rk3568: Fix use of PCIe bifurcation" [1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=366997
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 33 +
 configs/rock5b-rk3588_defconfig |  1 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1b2fcbb0bb..c790894170 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -27,6 +27,19 @@
regulator-max-microvolt = <1200>;
};
 
+   vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_pcie30";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   enable-active-high;
+   gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <5000>;
+   vin-supply = <&vcc5v0_sys>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pcie3_vcc3v3_en>;
+   };
+
vcc5v0_usbdcin: vcc5v0-usbdcin {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
@@ -87,6 +100,18 @@
status = "okay";
 };
 
+&pcie30phy {
+   status = "okay";
+};
+
+&pcie3x4 {
+   reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+   vpcie3v3-supply = <&vcc3v3_pcie30>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pcie3_rst>;
+   status = "okay";
+};
+
 &pinctrl {
pcie {
pcie_reset_h: pcie-reset-h {
@@ -97,6 +122,14 @@
rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
<3 RK_PD0 4 &pcfg_pull_none>;
};
+
+   pcie3_rst: pcie3-rst {
+   rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+   rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
};
 
usb {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 3fa65cbf9b..50551c70f2 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -81,6 +81,7 @@ CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RTL8169=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-- 
2.39.2

[PATCH 2/2] arm: dts: rockchip: rock-5b: add support for PCIe3 and NVMe

2023-08-31 Thread FUKAUMI Naoki

this patch adds support for PCIe3 (M.2 M key) and enables NVMe.

=> pci
BusDevFun  VendorId   DeviceId   Device Class   Sub-Class
_
00.00.00   0x1d87 0x3588 Bridge device   0x04
01.00.00   0x10ec 0x8125 Network controller  0x00
02.00.00   0x1d87 0x3588 Bridge device   0x04
03.00.00   0x1179 0x011a Mass storage controller 0x08
=> nvme scan
=> nvme info
Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN
Type: Hard Disk
Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)

Signed-off-by: FUKAUMI Naoki 

this patch depends:
- "rockchip: rk3568: Fix use of PCIe bifurcation" [1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=366997
---
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 33 +
 configs/rock5b-rk3588_defconfig |  1 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi 
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1b2fcbb0bb..c790894170 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -27,6 +27,19 @@
regulator-max-microvolt = <1200>;
};
 
+   vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_pcie30";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   enable-active-high;
+   gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <5000>;
+   vin-supply = <&vcc5v0_sys>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pcie3_vcc3v3_en>;
+   };
+
vcc5v0_usbdcin: vcc5v0-usbdcin {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
@@ -87,6 +100,18 @@
status = "okay";
 };
 
+&pcie30phy {
+   status = "okay";
+};
+
+&pcie3x4 {
+   reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+   vpcie3v3-supply = <&vcc3v3_pcie30>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pcie3_rst>;
+   status = "okay";
+};
+
 &pinctrl {
pcie {
pcie_reset_h: pcie-reset-h {
@@ -97,6 +122,14 @@
rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
<3 RK_PD0 4 &pcfg_pull_none>;
};
+
+   pcie3_rst: pcie3-rst {
+   rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+   rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
};
 
usb {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 3fa65cbf9b..50551c70f2 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -81,6 +81,7 @@ CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RTL8169=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
 CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
-- 
2.39.2

[PATCH 1/2] arm: dts: rockchip: rk3588, rk3588s: sync with Linux

2023-08-31 Thread FUKAUMI Naoki

Sync the devicetree with linux-next tag: next-20230831

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/rk3588.dtsi   | 215 +++
 arch/arm/dts/rk3588s.dtsi  | 367 +
 include/dt-bindings/ata/ahci.h |  20 ++
 3 files changed, 602 insertions(+)
 create mode 100644 include/dt-bindings/ata/ahci.h

diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
index 8be75556af..5519c1430c 100644
--- a/arch/arm/dts/rk3588.dtsi
+++ b/arch/arm/dts/rk3588.dtsi
@@ -7,6 +7,16 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+   pcie30_phy_grf: syscon@fd5b8000 {
+   compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+   reg = <0x0 0xfd5b8000 0x0 0x1>;
+   };
+
+   pipe_phy1_grf: syscon@fd5c {
+   compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+   reg = <0x0 0xfd5c 0x0 0x100>;
+   };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -75,6 +85,159 @@
status = "disabled";
};
 
+   pcie3x4: pcie@fe15 {
+   compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0x0f>;
+   clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+   device_type = "pci";
+   interrupts = ,
+,
+,
+,
+;
+   interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+   <0 0 0 2 &pcie3x4_intc 1>,
+   <0 0 0 3 &pcie3x4_intc 2>,
+   <0 0 0 4 &pcie3x4_intc 3>;
+   linux,pci-domain = <0>;
+   max-link-speed = <3>;
+   msi-map = <0x &its1 0x 0x1000>;
+   num-lanes = <4>;
+   phys = <&pcie30phy>;
+   phy-names = "pcie-phy";
+   power-domains = <&power RK3588_PD_PCIE>;
+   ranges = <0x0100 0x0 0xf010 0x0 0xf010 0x0 
0x0010>,
+<0x0200 0x0 0xf020 0x0 0xf020 0x0 
0x00e0>,
+<0x0300 0x0 0x4000 0x9 0x 0x0 
0x4000>;
+   reg = <0xa 0x4000 0x0 0x0040>,
+ <0x0 0xfe15 0x0 0x0001>,
+ <0x0 0xf000 0x0 0x0010>;
+   reg-names = "dbi", "apb", "config";
+   resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+   reset-names = "pwr", "pipe";
+   status = "disabled";
+
+   pcie3x4_intc: legacy-interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-parent = <&gic>;
+   interrupts = ;
+   };
+   };
+
+   pcie3x2: pcie@fe16 {
+   compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x10 0x1f>;
+   clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+   clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+   device_type = "pci";
+   interrupts = ,
+,
+

[PATCH] sunxi: MAINTAINERS: drop myself

2023-08-03 Thread FUKAUMI Naoki

I no longer maintain them.

Signed-off-by: FUKAUMI Naoki 
---
 board/sunxi/MAINTAINERS | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 98bbd2dd25..d89a25db7c 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -82,8 +82,8 @@ S:Maintained
 F: configs/A20-Olimex-SOM-EVB_defconfig
 
 A20-OLINUXINO-LIME BOARD
-M: FUKAUMI Naoki 
-S: Maintained
+M:
+S:
 F: configs/A20-OLinuXino-Lime_defconfig
 
 A20-OLINUXINO-LIME2 BOARD
@@ -379,8 +379,8 @@ S:  Maintained
 F: configs/nanopi_a64_defconfig
 
 NINTENDO NES CLASSIC EDITION BOARD
-M: FUKAUMI Naoki 
-S: Maintained
+M:
+S:
 F: configs/Nintendo_NES_Classic_Edition_defconfig
 
 OCEANIC 5205 5INMFD BOARD
-- 
2.39.2

[PATCH] rockchip: MAINTAINERS: fix board name for Radxa ROCK 4C+

2023-08-03 Thread FUKAUMI Naoki

align with other ROCK series.

Fixes: 2b506407c8 ("rockchip: Add MAINTAINERS entry for Radxa Rock 4C+")
Signed-off-by: FUKAUMI Naoki 
---
 board/rockchip/evb_rk3399/MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/rockchip/evb_rk3399/MAINTAINERS 
b/board/rockchip/evb_rk3399/MAINTAINERS
index cb44bc9fda..c7e412b54e 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -80,7 +80,7 @@ F:configs/orangepi-rk3399_defconfig
 F: arch/arm/dts/rk3399-u-boot.dtsi
 F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
 
-RADXA ROCK 4C+
+ROCK-4C+
 M:     FUKAUMI Naoki 
 S: Maintained
 F: configs/rock-4c-plus-rk3399_defconfig
-- 
2.39.2

Re: [PATCH v2 0/7] rockchip: rk3568: Fix use of PCIe bifurcation

2023-08-02 Thread FUKAUMI Naoki


hi,

On 8/3/23 04:22, Jonas Karlman wrote:

This series add support for use of PCIe bifurcation on RK3568, and as a
bonus support for the RK3588 PHY is also included. With PCIe bifurcation
supported it is possible to enable PCIe on more RK3568 boards, e.g. on
NanoPi R5C and NanoPi R5S. This series only include fixing the mini PCIe
slot on Radxa E25.

Most parts of this series was imported almost 1:1 from mainline linux.

Patch 1 fixes configuration of number of lanes in pcie_dw_rockchip.
Patch 2-3 refactor the snps-pcie3 phy driver.
Patch 4 add bifurcation support for RK3568.
Patch 5 add support for RK3588 to snps-pcie3 driver.
Patch 6 fixes use of pcie2x1l0 on ROCK 5B.
Patch 7 enables the mini PCIe slot on Radxa E25.

Changes in v2:
- Fix use of signal from comb PHY on RK3588
- Add fixes tag

The RK3588 PHY part was tested on a ROCK 5B together with device tree
files picked from Sebastian Reichel's rk3588 branch at [1].

Patches in this series is also aviliable at [2].

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-misc.git/tree/?h=rk3588
[2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-pcie-bifurcation-v2

Jonas Karlman (7):
   pci: pcie_dw_rockchip: Configure number of lanes and link width speed
   phy: rockchip: snps-pcie3: Refactor to use clk_bulk API
   phy: rockchip: snps-pcie3: Refactor to use a phy_init ops
   phy: rockchip: snps-pcie3: Add bifurcation support for RK3568
   phy: rockchip: snps-pcie3: Add support for RK3588
   phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588
   rockchip: rk3568-radxa-e25: Enable pcie3x1 node

  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi |  11 +-
  configs/radxa-e25-rk3568_defconfig|   1 -
  drivers/pci/pcie_dw_rockchip.c|  58 -
  .../rockchip/phy-rockchip-naneng-combphy.c|   6 +
  .../phy/rockchip/phy-rockchip-snps-pcie3.c| 230 ++
  5 files changed, 241 insertions(+), 65 deletions(-)


for the whole series,

Tested-by: FUKAUMI Naoki 

on ROCK 5B with NVMe and linux-next 20230802 device tree.

Re: [PATCH v3] board: rockchip: Add Radxa E25 Carrier Board

2023-07-31 Thread FUKAUMI Naoki

 };
+
+   pcie30x1_enable_h: pcie30x1-enable-h {
+   rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   pcie30x2_reset_h: pcie30x2-reset-h {
+   rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   pcie_enable_h: pcie-enable-h {
+   rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+   };
+
+   usb {
+   minipcie_enable_h: minipcie-enable-h {
+   rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   ngffpcie_enable_h: ngffpcie-enable-h {
+   rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+
+   vbus_typec_en: vbus_typec_en {
+   rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+   };
+   };
+};
+
+&pwm1 {
+   status = "okay";
+};
+
+&pwm2 {
+   status = "okay";
+};
+
+&pwm12 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwm12m1_pins>;
+   status = "okay";
+};
+
+&sata1 {
+   status = "okay";
+};
+
+&sdmmc0 {
+   bus-width = <4>;
+   cap-sd-highspeed;
+   cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+   /* Also used in pcie30x1_clkreqnm0 */
+   disable-wp;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
+   sd-uhs-sdr104;
+   vmmc-supply = <&vcc3v3_sd>;
+   vqmmc-supply = <&vccio_sd>;
+   status = "okay";
+};
+
+&usb_host0_ehci {
+   status = "okay";
+};
+
+&usb_host0_ohci {
+   status = "okay";
+};
+
+&usb_host0_xhci {
+   status = "okay";
+};
+
+&usb_host1_ehci {
+   status = "okay";
+};
+
+&usb_host1_ohci {
+   status = "okay";
+};
+
+&usb2phy0_otg {
+   phy-supply = <&vbus_typec>;
+   status = "okay";
+};
+
+&usb2phy1_host {
+   phy-supply = <&vcc3v3_minipcie>;
+   status = "okay";
+};
+
+&usb2phy1_otg {
+   phy-supply = <&vcc3v3_ngff>;
+   status = "okay";
+};
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS 
b/board/rockchip/evb_rk3568/MAINTAINERS
index a8ed2508a162..82a92b89fa64 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -27,6 +27,14 @@ M:   Jagan Teki 
  S:Maintained
  F:configs/radxa-cm3-io-rk3566_defconfig
  
+RADXA-E25

+M: Jonas Karlman 
+S: Maintained
+F: configs/radxa-e25-rk3568_defconfig
+F: arch/arm/dts/rk3568-radxa-cm3i.dtsi
+F: arch/arm/dts/rk3568-radxa-e25.dts
+F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+
  ROCK-3A
  M:  Akash Gajjar 
  S:  Maintained
diff --git a/configs/radxa-e25-rk3568_defconfig 
b/configs/radxa-e25-rk3568_defconfig
new file mode 100644
index ..a905100a794d
--- /dev/null
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a0
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_SPL_STACK=0x40
+CONFIG_DEBUG_UART_BASE=0xFE66
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x400
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y


AHCI_PCI is not required for SATA on Carrier Board.

Tested-by: FUKAUMI Naoki 

 => scsi scan
 scanning bus for devices...
 Target spinup took 0 ms.
 AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
 flags: ncq stag pm led clo only pmp fbss pio slum part ccc apst
   Device 0: (0:0) Vendor: ATA Prod.: TS120GMTS420S Rev: V011
 Type: Hard Disk
 Capacity: 114473.4 MB = 111.7 GB (234441648 x 512)

Best regards,


+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index e23237e453f3..10fffb56f13d 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -101,6 +101,7 @@ List of mainline supported Rockchip boards:
   - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig)
   - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig)
   - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
+ - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig)
  
  * rk3588

   - Rockchip EVB (evb-rk3588)

Re: AW: EXTERNAL - [PATCH] menu: Ignore prompt variable if timeout is != 0

2023-07-25 Thread FUKAUMI Naoki


hi,

On 7/25/23 17:23, Traut Manuel LCPF-CH wrote:

Hi,


Since 739e8361f3fe78038251216df6096a32bc2d5839, a system with the
following /boot/extlinux/extlinux.conf (which sets timeout to 50)
immediately boots the first entry in the config without displaying
a boot menu.  According to the description, that should only happen
if both prompt and timeout are set to zero in the config, but it also happens 
with timeout set to a non-zero value.

Reported-by: Karsten Merker 
Signed-off-by: Manuel Traut 
---
   common/menu.c | 3 +++
   1 file changed, 3 insertions(+)

diff --git a/common/menu.c b/common/menu.c index
8fe00965c0..8eab87 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -277,6 +277,9 @@ int menu_get_choice(struct menu *m, void **choice)
if (!m->item_cnt)
return -ENOENT;
   
+	if (m->timeout)

+   return menu_interactive_choice(m, choice);


This should not be needed, if the user wants to prompt the menu
there is the PROMPT keyword that can be used in extlinux.conf, e.g.:

PROMPT 1
TIMEOUT 50

See https://wiki.archlinux.org/title/Syslinux#Boot_prompt

That should set pxe cfg->prompt = 1 and that in turn menu m->prompt = 1.


https://source.denx.de/u-boot/u-boot/-/blob/master/common/menu.c#L346
-351

this description is unclear for me if (timeout > 0) && (prompt == 0)


This is my current understanding after reading the description multiple times:

 | timeout == 0 | timeout > 0
+--+-
prompt == 0 | boot default | wait for timeout or user interrupt
+--+-
prompt != 0 | ask user | ask user

so for (timeout > 0) && (prompt == 0) I would expect to boot the default choice 
immediately.

Without reading the documentation I would expect PROMPT 1 TIMEOUT 50
to show a prompt for 5 seconds and afterwards boot the default choice.
This also matches the current implantation and the explanation in the arch wiki.

The current implementation, behaves like this:

 | timeout == 0 | timeout > 0
+--+-
prompt == 0 | boot default | boot default
+--+-
prompt != 0 | ask user | wait for timeout or user input

The patch under discussion considers a configuration of:
PROMPT 0
TIMEOUT 50
that currently is booting the default target immediately.
This clearly does not match the description.

The patch would change the behavior like this:

 | timeout == 0 | timeout > 0
+--+-
prompt == 0 | boot default | wait for timeout or user input
+--+-
prompt != 0 | ask user | wait for timeout or user input

It does not match the description regarding:
"prompt - If 1, the user will be prompted for input regardless of the value of 
timeout"

If I write a configuration like:
PROMPT 1
TIMEOUT 50
I would expect to get a prompt for 5 seconds, than boot the default target.

I can update the patch to include changing the documentation along with table 
above as a comment to make it easier understandable.
Or shall I update the patch to match the behavior described in the first table?
Just let me know..


I agree that the documentation is not clear, because this is a common menu 
function I would expect the use of timeout and prompt to be explicit and that 
each control a single function.

prompt: 0 = do not ask user, 1 = ask user
timeout: 0 = wait indefinitely, > 0 time to wait for input


This should match the current implementation (but not documentation..)

@FUKAUMI Naoki, @mer...@debian.org - is it ok for you if we keep this behavior 
and I will fix the documentation?


I'm fine.


If anything needs to be done related to how extlinux.conf handles menu options 
the menu config should probably be changed in pxe_utils.c and not in the common 
menu.c.

My expectations related to extlinux.conf would be:
- No need to prompt or wait for timeout if there is only one bootable
   choice, regardless of PROMPT or TIMEOUT values
- Should not prompt when I have explicitly specified PROMPT 0
- Having multiple bootable choices and a TIMEOUT > 0 or PROMPT 1 should
   prompt, at least if I have some way to see and control the menu


This is also fine for me, we could implement this as an additional feature, if 
we have agreed on the basic behavior.


I like this too.

Best regards,

--
FUKAUMI Naoki
Radxa


Best regards
Manuel

Re: [PATCH] menu: Ignore prompt variable if timeout is != 0

2023-07-18 Thread FUKAUMI Naoki


hi,

thank you for your reply!

On 7/18/23 23:08, Jonas Karlman wrote:

On 2023-07-14 09:36, FUKAUMI Naoki wrote:

From: Manuel Traut 

Since 739e8361f3fe78038251216df6096a32bc2d5839, a system with the following
/boot/extlinux/extlinux.conf (which sets timeout to 50) immediately boots the
first entry in the config without displaying a boot menu.  According to the
description, that should only happen if both prompt and timeout are set to zero
in the config, but it also happens with timeout set to a non-zero value.

Reported-by: Karsten Merker 
Signed-off-by: Manuel Traut 
---
  common/menu.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/common/menu.c b/common/menu.c
index 8fe00965c0..8eab87 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -277,6 +277,9 @@ int menu_get_choice(struct menu *m, void **choice)
if (!m->item_cnt)
return -ENOENT;
  
+	if (m->timeout)

+   return menu_interactive_choice(m, choice);


This should not be needed, if the user wants to prompt the menu there is
the PROMPT keyword that can be used in extlinux.conf, e.g.:

   PROMPT 1
   TIMEOUT 50

See https://wiki.archlinux.org/title/Syslinux#Boot_prompt

That should set pxe cfg->prompt = 1 and that in turn menu m->prompt = 1.


 https://source.denx.de/u-boot/u-boot/-/blob/master/common/menu.c#L346-351

this description is unclear for me if (timeout > 0) && (prompt == 0)

Best regards,

--
FUKAUMI Naoki
Radxa


Regards,
Jonas


+
if (!m->prompt)
return menu_default_choice(m, choice);

[PATCH] menu: Ignore prompt variable if timeout is != 0

2023-07-14 Thread FUKAUMI Naoki

From: Manuel Traut 

Since 739e8361f3fe78038251216df6096a32bc2d5839, a system with the following
/boot/extlinux/extlinux.conf (which sets timeout to 50) immediately boots the
first entry in the config without displaying a boot menu.  According to the
description, that should only happen if both prompt and timeout are set to zero
in the config, but it also happens with timeout set to a non-zero value.

Reported-by: Karsten Merker 
Signed-off-by: Manuel Traut 
---
 common/menu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/common/menu.c b/common/menu.c
index 8fe00965c0..8eab87 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -277,6 +277,9 @@ int menu_get_choice(struct menu *m, void **choice)
if (!m->item_cnt)
return -ENOENT;
 
+   if (m->timeout)
+   return menu_interactive_choice(m, choice);
+
if (!m->prompt)
return menu_default_choice(m, choice);
 
-- 
2.39.0

Re: [PATCH v2 2/3] rockchip: rk356x: update the dwc3_device register offset

2023-05-29 Thread FUKAUMI Naoki


hi,

could you tell me current status of this patch?

--
FUKAUMI Naoki

On 2/26/23 22:22, Manoj Sai wrote:

update the dwc3_device register offset in board_usb_init()
for rk3568 platforms.

Signed-off-by: Manoj Sai 
Reviewed-by: Jagan Teki 
---
Changes for v2:-
- None
---
  arch/arm/mach-rockchip/board.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index f1f70c81d0..c7729c966a 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -300,6 +300,9 @@ int usb_gadget_handle_interrupts(int index)
  
  int board_usb_init(int index, enum usb_init_type init)

  {
+   if (IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+   dwc3_device_data.base = 0xfcc0;
+
return dwc3_uboot_init(&dwc3_device_data);
  }
  #endif /* CONFIG_USB_DWC3_GADGET */

[PATCH 3/5] arm: dts: rockchip: add Radxa ROCK 4C+

2023-04-25 Thread FUKAUMI Naoki

Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+

Add support for Radxa ROCK 4C+ SBC.

Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec

Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.

Signed-off-by: Stephen Chen 
Signed-off-by: Manoj Sai 
Signed-off-by: Jagan Teki 
Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi |   5 +
 arch/arm/dts/rk3399-rock-4c-plus.dts | 709 +++
 arch/arm/dts/rk3399-t-opp.dtsi   | 114 +++
 4 files changed, 829 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-rock-4c-plus.dts
 create mode 100644 arch/arm/dts/rk3399-t-opp.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1d674b90af..2e0dbf8720 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -157,6 +157,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
+   rk3399-rock-4c-plus.dtb \
rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
new file mode 100644
index 00..5c1c451b8f
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Radxa Limited
+ */
+#include "rk3399-rock-pi-4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts 
b/arch/arm/dts/rk3399-rock-4c-plus.dts
new file mode 100644
index 00..028eb508ae
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2022 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include 
+#include "rk3399.dtsi"
+#include "rk3399-t-opp.dtsi"
+
+/ {
+   model = "Radxa ROCK 4C+";
+   compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
+
+   aliases {
+   mmc0 = &sdhci;
+   mmc1 = &sdmmc;
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   clkin_gmac: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "clkin_gmac";
+   #clock-cells = <0>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_led1 &user_led2>;
+
+   /* USER_LED1 */
+   led-0 {
+   function = LED_FUNCTION_POWER;
+   color = ;
+   gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+   linux,default-trigger = "default-on";
+   };
+
+   /* USER_LED2 */
+   led-1 {
+   function = LED_FUNCTION_STATUS;
+   color = ;
+   gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <&rk809 1>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <&wifi_enable_h>;
+   reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+   };
+
+   vcc_3v3: vcc-3v3-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_3v3";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&vcc3v3_sys>;
+   };
+
+   vcc3v3_phy1: vcc3v3-phy1-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_phy1";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&vcc_3v3>;
+   };
+
+   vcc5v0_host1: vcc5v0-host

[PATCH 1/5] arm: dts: rockchip: rock-pi-4: sync with Linux 6.3

2023-04-25 Thread FUKAUMI Naoki

sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.

because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.

Signed-off-by: FUKAUMI Naoki 
---
 arch/arm/dts/Makefile |   1 -
 arch/arm/dts/rk3399-rock-pi-4.dtsi| 229 --
 ...oot.dtsi => rk3399-rock-pi-4a-u-boot.dtsi} |   0
 arch/arm/dts/rk3399-rock-pi-4b.dts|  46 
 arch/arm/dts/rk3399-rock-pi-4c.dts|  20 +-
 5 files changed, 174 insertions(+), 122 deletions(-)
 rename arch/arm/dts/{rk3399-rock-pi-4b-u-boot.dtsi => 
rk3399-rock-pi-4a-u-boot.dtsi} (100%)
 delete mode 100644 arch/arm/dts/rk3399-rock-pi-4b.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3385948d22..1d674b90af 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -158,7 +158,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4a.dtb \
-   rk3399-rock-pi-4b.dtb \
rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb \
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4.dtsi
index b2ea92..907071d4fe 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -6,14 +6,15 @@
 
 /dts-v1/;
 #include 
+#include 
 #include 
 #include "rk3399.dtsi"
 #include "rk3399-opp.dtsi"
 
 / {
aliases {
-   mmc0 = &sdmmc;
-   mmc1 = &sdhci;
+   mmc0 = &sdhci;
+   mmc1 = &sdmmc;
};
 
chosen {
@@ -27,6 +28,20 @@
#clock-cells = <0>;
};
 
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_led2>;
+
+   /* USER_LED2 */
+   led-0 {
+   function = LED_FUNCTION_STATUS;
+   color = ;
+   gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
@@ -36,32 +51,56 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
 
-   vcc12v_dcin: dc-12v {
+   sound: sound {
+   compatible = "audio-graph-card";
+   label = "Analog";
+   dais = <&i2s0_p0>;
+   };
+
+   sound-dit {
+   compatible = "audio-graph-card";
+   label = "SPDIF";
+   dais = <&spdif_p0>;
+   };
+
+   spdif-dit {
+   compatible = "linux,spdif-dit";
+   #sound-dai-cells = <0>;
+
+   port {
+   dit_p0_0: endpoint {
+   remote-endpoint = <&spdif_p0_0>;
+   };
+   };
+   };
+
+   vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
-   regulator-name = "vcc12v_dcin";
+   enable-active-high;
+   gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&vcc5v0_typec_en>;
+   regulator-name = "vbus_typec";
regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <1200>;
-   regulator-max-microvolt = <1200>;
+   vin-supply = <&vcc5v0_sys>;
};
 
-   vcc5v0_sys: vcc-sys {
+   vcc12v_dcin: dc-12v {
compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_sys";
+   regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   vin-supply = <&vcc12v_dcin>;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
};
 
-   vcc_0v9: vcc-0v9 {
+   vcc3v3_lan: vcc3v3-lan-regulator {
compatible = "regulator-fixed";
-   regulator-name = "vcc_0v9";
+   regulator-name = "vcc3v3_lan";
regulator-always-on;
regulator-boot-on;
-   regulator-min-microvolt = <90>;
-   regulator-max-microvolt = <90>;
+   regulator-min-microvolt = <330&

[PATCH 4/5] configs: rockchip: add Radxa ROCK 4C+

2023-04-25 Thread FUKAUMI Naoki

add defconfig for Radxa ROCK 4C+.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock-4c-plus-rk3399_defconfig | 97 +++
 1 file changed, 97 insertions(+)
 create mode 100644 configs/rock-4c-plus-rk3399_defconfig

diff --git a/configs/rock-4c-plus-rk3399_defconfig 
b/configs/rock-4c-plus-rk3399_defconfig
new file mode 100644
index 00..97693166d9
--- /dev/null
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x0020
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_SPL_STACK=0x40
+CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x40
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
-- 
2.39.2

[PATCH 2/5] configs: rockchip: rock-pi-4: use dtb for ROCK Pi 4A instead of 4B

2023-04-25 Thread FUKAUMI Naoki

rk3399-rock-pi-4a.dtb is enough for Radxa ROCK Pi 4A/B/A+/B+ and ROCK 4SE.

Signed-off-by: FUKAUMI Naoki 
---
 configs/rock-pi-4-rk3399_defconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index 4ecc06d92b..fde1ee2eb5 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30
 CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
@@ -17,7 +17,7 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2e000
-- 
2.39.2

[PATCH 5/5] doc: rockchip: update list of Radxa ROCK (Pi) 4 boards

2023-04-25 Thread FUKAUMI Naoki

add Radxa ROCK (Pi) 4 variants.

Signed-off-by: FUKAUMI Naoki 
---
 doc/board/rockchip/rockchip.rst | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 1dccb17d72..749e40de01 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -83,7 +83,10 @@ List of mainline supported Rockchip boards:
  - Khadas Edge-V (hadas-edge-v-rk3399)
  - Orange Pi RK3399 (orangepi-rk3399)
  - Pine64 RockPro64 (rockpro64-rk3399)
- - Radxa ROCK Pi 4 (rock-pi-4-rk3399)
+ - Radxa ROCK 4C+ (rock-4c-plus-rk3399)
+ - Radxa ROCK 4SE (rock-pi-4-rk3399)
+ - Radxa ROCK Pi 4A/B/A+/B+ (rock-pi-4-rk3399)
+ - Radxa ROCK Pi 4C (rock-pi-4c-rk3399)
  - Rockchip Evb-RK3399 (evb_rk3399)
  - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
 
-- 
2.39.2

Re: [PATCH 1/2] arm: dts: rk3399: rock-pi-4: sync with Linux 6.3-rc5

2023-04-25 Thread FUKAUMI Naoki


hi,

On 4/13/23 11:18, Kever Yang wrote:


On 2023/4/8 17:11, FUKAUMI Naoki wrote:

sync *.dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3-rc5.

Signed-off-by: FUKAUMI Naoki 

Reviewed-by: Kever Yang 


this is not merged yet, right?
I want to modify this change.

Best regards,

--
FUKAUMI Naoki


Thanks,
- Kever

---
  arch/arm/dts/Makefile |   2 +
  arch/arm/dts/rk3399-rock-pi-4.dtsi    | 229 --
  .../dts/rk3399-rock-pi-4a-plus-u-boot.dtsi    |   5 +
  arch/arm/dts/rk3399-rock-pi-4a-plus.dts   |  25 ++
  arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi    |   6 +
  .../dts/rk3399-rock-pi-4b-plus-u-boot.dtsi    |   5 +
  arch/arm/dts/rk3399-rock-pi-4b-plus.dts   |  61 +
  arch/arm/dts/rk3399-rock-pi-4b.dts    |   9 +-
  arch/arm/dts/rk3399-rock-pi-4c.dts    |  20 +-
  9 files changed, 284 insertions(+), 78 deletions(-)
  create mode 100644 arch/arm/dts/rk3399-rock-pi-4a-plus-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3399-rock-pi-4a-plus.dts
  create mode 100644 arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3399-rock-pi-4b-plus-u-boot.dtsi
  create mode 100644 arch/arm/dts/rk3399-rock-pi-4b-plus.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c160e884bf..8a5eb6225c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -157,7 +157,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
  rk3399-puma-haikou.dtb \
  rk3399-roc-pc.dtb \
  rk3399-roc-pc-mezzanine.dtb \
+    rk3399-rock-pi-4a-plus.dtb \
  rk3399-rock-pi-4a.dtb \
+    rk3399-rock-pi-4b-plus.dtb \
  rk3399-rock-pi-4b.dtb \
  rk3399-rock-pi-4c.dtb \
  rk3399-rock960.dtb \
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4.dtsi

index b2ea92..907071d4fe 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -6,14 +6,15 @@
  /dts-v1/;
  #include 
+#include 
  #include 
  #include "rk3399.dtsi"
  #include "rk3399-opp.dtsi"
  / {
  aliases {
-    mmc0 = &sdmmc;
-    mmc1 = &sdhci;
+    mmc0 = &sdhci;
+    mmc1 = &sdmmc;
  };
  chosen {
@@ -27,6 +28,20 @@
  #clock-cells = <0>;
  };
+    leds {
+    compatible = "gpio-leds";
+    pinctrl-names = "default";
+    pinctrl-0 = <&user_led2>;
+
+    /* USER_LED2 */
+    led-0 {
+    function = LED_FUNCTION_STATUS;
+    color = ;
+    gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+    linux,default-trigger = "heartbeat";
+    };
+    };
+
  sdio_pwrseq: sdio-pwrseq {
  compatible = "mmc-pwrseq-simple";
  clocks = <&rk808 1>;
@@ -36,32 +51,56 @@
  reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
  };
-    vcc12v_dcin: dc-12v {
+    sound: sound {
+    compatible = "audio-graph-card";
+    label = "Analog";
+    dais = <&i2s0_p0>;
+    };
+
+    sound-dit {
+    compatible = "audio-graph-card";
+    label = "SPDIF";
+    dais = <&spdif_p0>;
+    };
+
+    spdif-dit {
+    compatible = "linux,spdif-dit";
+    #sound-dai-cells = <0>;
+
+    port {
+    dit_p0_0: endpoint {
+    remote-endpoint = <&spdif_p0_0>;
+    };
+    };
+    };
+
+    vbus_typec: vbus-typec-regulator {
  compatible = "regulator-fixed";
-    regulator-name = "vcc12v_dcin";
+    enable-active-high;
+    gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&vcc5v0_typec_en>;
+    regulator-name = "vbus_typec";
  regulator-always-on;
-    regulator-boot-on;
-    regulator-min-microvolt = <1200>;
-    regulator-max-microvolt = <1200>;
+    vin-supply = <&vcc5v0_sys>;
  };
-    vcc5v0_sys: vcc-sys {
+    vcc12v_dcin: dc-12v {
  compatible = "regulator-fixed";
-    regulator-name = "vcc5v0_sys";
+    regulator-name = "vcc12v_dcin";
  regulator-always-on;
  regulator-boot-on;
-    regulator-min-microvolt = <500>;
-    regulator-max-microvolt = <500>;
-    vin-supply = <&vcc12v_dcin>;
+    regulator-min-microvolt = <1200>;
+    regulator-max-microvolt = <1200>;
  };
-    vcc_0v9: vcc-0v9 {
+    vcc3v3_lan: vcc3v3-lan-regulator {
  compatible = "regulator-fixed";
-    regulator-name = "vcc_0v9";
+    regulator-name = "vcc3v3_lan";
  regulator-always-on;
  regulator-boot-on;
-    regulator-min-microvolt = <90>;
-    regulator-max-micr

[PATCH v2 4/4] configs: rockchip: radxa-cm3-io: drop CONFIG_USB_DWC3_GENERIC

2023-04-20 Thread FUKAUMI Naoki

it's not used by rk35xx

Signed-off-by: FUKAUMI Naoki 
---
v2:
- new patch

 configs/radxa-cm3-io-rk3566_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/radxa-cm3-io-rk3566_defconfig 
b/configs/radxa-cm3-io-rk3566_defconfig
index 9b99181714..1df9cab79d 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -77,5 +77,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y
-- 
2.39.2

[PATCH v2 3/4] arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb

2023-04-20 Thread FUKAUMI Naoki

enable regulators for usb host function

Signed-off-by: FUKAUMI Naoki 
Reviewed-by: Kever Yang 
---
v2:
- collect R-b

 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 4 
 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi  | 8 
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi 
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index 4e79173833..d183e93575 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -16,3 +16,7 @@
bootph-all;
status = "okay";
 };
+
+&vcc5v0_usb30 {
+   regulator-boot-on;
+};
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi 
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9ef1e84770..b7b18e131a 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -26,3 +26,11 @@
bootph-all;
status = "okay";
 };
+
+&vcc5v0_usb_host {
+   regulator-boot-on;
+};
+
+&vcc5v0_usb_hub {
+   regulator-boot-on;
+};
-- 
2.39.2

1 2 >

1 - 100 of 125 matches

Mail list logo