Re: [PATCH V2 5/6] configs: Update anbernic-rgxx3_defconfig for panel detection
On 2023/5/16 00:00, Chris Morgan wrote: From: Chris Morgan Update the anbernic-rgxx3_defconfig file to support panel autodetection and automatically updating the compatible string in the devicetree. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang Thanks, - Kever --- configs/anbernic-rgxx3_defconfig | 15 +++ 1 file changed, 15 insertions(+) diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3_defconfig index b17e917914..ed6643d9d4 100644 --- a/configs/anbernic-rgxx3_defconfig +++ b/configs/anbernic-rgxx3_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x60 @@ -24,9 +25,13 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb" +# CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_RNG_SEED=y CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -41,6 +46,7 @@ CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_CLS is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y @@ -60,6 +66,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y @@ -69,10 +76,18 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_RNG_SMCCC_TRNG is not set CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_VIDEO=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y +CONFIG_VIDEO_BRIDGE=y CONFIG_REGEX=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set
Re: [PATCH V2 3/6] board: rockchip: Add support for RG353PS to RGxx3
On 2023/5/16 00:00, Chris Morgan wrote:
From: Chris Morgan
Add support for the RG353PS to the Anbernic RGxx3. This device is a
slightly pared down version of the RG353P with no eMMC, no touchscreen,
and only 1GB of RAM.
Refactor board logic so that all supported devices are defined with
ADC values and that future boards can be added by just defining the
board values in the device array.
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 126 ++---
1 file changed, 86 insertions(+), 40 deletions(-)
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index decc46db78..4d3c724b9c 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -7,24 +7,30 @@
#include
#include
#include
+#include
+#include
+#include
#include
+#include
#include
#include
#include
-#include
-#include
#define GPIO0_BASE 0xfdd6
+#define GPIO_SWPORT_DR_L 0x
#define GPIO_SWPORT_DR_H 0x0004
+#define GPIO_SWPORT_DDR_L 0x0008
#define GPIO_SWPORT_DDR_H 0x000c
-#define GPIO_A5BIT(5)
-#define GPIO_A6BIT(6)
+#define GPIO_C5BIT(5)
+#define GPIO_C6BIT(6)
+#define GPIO_C7BIT(7)
#define GPIO_WRITEMASK(bits) ((bits) << 16)
#define DTB_DIR "rockchip/"
struct rg3xx_model {
+ const u16 adc_value;
const char *board;
const char *board_name;
const char *fdtfile;
@@ -34,49 +40,64 @@ enum rgxx3_device_id {
RG353M,
RG353P,
RG353V,
- RG353VS,
RG503,
+ /* Devices with duplicate ADC value */
+ RG353PS,
+ RG353VS,
};
static const struct rg3xx_model rg3xx_model_details[] = {
[RG353M] = {
+ 517, /* Observed average from device */
"rk3566-anbernic-rg353m",
"RG353M",
- DTB_DIR "rk3566-anbernic-rg353m.dtb",
+ DTB_DIR "rk3566-anbernic-rg353p.dtb", /* Identical devices */
},
[RG353P] = {
+ 860, /* Documented value of 860 */
"rk3566-anbernic-rg353p",
"RG353P",
DTB_DIR "rk3566-anbernic-rg353p.dtb",
},
[RG353V] = {
+ 695, /* Observed average from device */
"rk3566-anbernic-rg353v",
"RG353V",
DTB_DIR "rk3566-anbernic-rg353v.dtb",
},
- [RG353VS] = {
- "rk3566-anbernic-rg353vs",
- "RG353VS",
- DTB_DIR "rk3566-anbernic-rg353vs.dtb",
- },
[RG503] = {
+ 1023, /* Observed average from device */
"rk3566-anbernic-rg503",
"RG503",
DTB_DIR "rk3566-anbernic-rg503.dtb",
},
+ /* Devices with duplicate ADC value */
+ [RG353PS] = {
+ 860, /* Observed average from device */
+ "rk3566-anbernic-rg353ps",
+ "RG353PS",
+ DTB_DIR "rk3566-anbernic-rg353ps.dtb",
+ },
+ [RG353VS] = {
+ 695, /* Gathered from second hand information */
+ "rk3566-anbernic-rg353vs",
+ "RG353VS",
+ DTB_DIR "rk3566-anbernic-rg353vs.dtb",
+ },
};
/*
* Start LED very early so user knows device is on. Set color
- * to amber.
+ * to red.
*/
void spl_board_init(void)
{
- /* Set GPIO0_A5 and GPIO0_A6 to output. */
- writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5),
+ /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
+ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
+ (GPIO_C7 | GPIO_C6 | GPIO_C5),
(GPIO0_BASE + GPIO_SWPORT_DDR_H));
- /* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */
- writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6,
+ /* Set GPIO0_C5 and GPIO_C6 to 0 and GPIO0_C7 to 1. */
+ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C7,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
}
@@ -129,12 +150,12 @@ void __maybe_unused startup_buzz(void)
/* Detect which Anbernic RGXX3 device we are using so as to load the
* correct devicetree for Linux. Set an environment variable once
* found. The detection depends on the value of ADC channel 1, the
- * presence of an eMMC on mmc0, and querying the DSI panel (TODO).
+ * presence of an eMMC on mmc0, and querying the DSI panel.
*/
int rgxx3_detect_device(void)
{
u32 adc_info;
- int ret;
+ in
Re: [PATCH 3/4] rockchip: dts: rk3328: Add rng details to u-boot.dtsi
Hi Peter,
On 2023/6/14 20:43, Peter Robinson wrote:
Add the rk3328 rng details to the u-boot.dtsi and
enable the RNG on the Rock64 to be able to provide
a rnadom seed via UEFI.
typo: random
Thanks,
- Kever
Signed-off-by: Peter Robinson
---
The DT snippet will allow this to be enabled on other rk3328 devices but
I only have the Rock54 to test on.
arch/arm/dts/rk3328-u-boot.dtsi | 6 ++
configs/rock64-rk3328_defconfig | 2 ++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index ce96ce40a73..a9f2536de2a 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -26,6 +26,12 @@
0x0 0xff72 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
+
+ rng: rng@ff06 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff06 0x0 0x4000>;
+ status = "okay";
+ };
};
&cru {
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 97ac8734d1b..1820deee373 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -77,6 +77,8 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
Re: [PATCH V2 1/6] board: rockchip: Correct i2c2 pinctrl for RGxx3
On 2023/5/16 00:00, Chris Morgan wrote:
From: Chris Morgan
The pinctrl on the Anbernic RGxx3 for the i2c2 bus does not use the
default value, so explicitly define it.
Fixes: 6cf6fe25370c ("board: rockchip: add Anbernic RGXX3 Series Devices")
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index a18e5d1cf7..62e75223af 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -47,6 +47,8 @@
};
&i2c2 {
+ pinctrl-0 = <&i2c2m1_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
Re: [PATCH v2 2/2] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
On 2023/5/20 19:20, Tianling Shen wrote:
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
changed from DDR4 to LPDDR3.
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v2:
* Rebased upon the latest git HEAD
* Fixed memory profile (rk3328-sdram-lpddr3-1600.dtsi ->
rk3328-sdram-lpddr3-666.dtsi)
* Removed kernel link from commit message
---
arch/arm/dts/Makefile | 1 +
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++
board/rockchip/evb_rk3328/MAINTAINERS | 6 +
configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++
5 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d189788aa..425bf4e7a9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
+ rk3328-orangepi-r1-plus-lts.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
new file mode 100644
index 00..ebe33e48cb
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 David Bauer
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-lpddr3-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&gpio0 {
+ bootph-pre-ram;
+};
+
+&pinctrl {
+ bootph-pre-ram;
+};
+
+&sdmmc0m1_pin {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_up_4ma {
+ bootph-pre-ram;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ bootph-pre-ram;
+};
+
+&gmac2io {
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+};
+
+&spi0 {
+ spi_flash: spiflash@0 {
+ bootph-all;
+ };
+};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 00..5d7d567283
--- /dev/null
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
+ * (http://www.orangepi.org)
+ *
+ * Copyright (c) 2021-2023 Tianling Shen
+ */
+
+/dts-v1/;
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus LTS";
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+&gmac2io {
+ phy-handle = <&yt8531c>;
+ tx_delay = <0x19>;
+ rx_delay = <0x05>;
+
+ mdio {
+ /delete-node/ ethernet-phy@1;
+
+ yt8531c: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+
+ motorcomm,clk-out-frequency-hz = <12500>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+
+ pinctrl-0 = <ð_phy_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <15000>;
+ reset-deassert-us = <5>;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS
b/board/rockchip/evb_rk3328/MAINTAINERS
index 91dc6b58cf..8a19eb373d 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -24,6 +24,12 @@ S: Maintained
F: configs/orangepi-r1-plus-rk3328_defconfig
F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+ORANGEPI-R1-PLUS-LTS-RK3328
+M: Tianling Shen
+S: Maintained
+F: configs/orangepi-r1-plus-lts-rk3328_defconfig
+F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+
ROC-RK3328-CC
M: Loic Devulder
M: Chen-Yu Tsai
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig
b/configs/orangepi-r1-plus-lts-rk3328_d
Re: [PATCH v2 5/7] phy: rockchip-inno-usb2: Add USB2 PHY for RK3328
On 2023/6/7 01:09, Jagan Teki wrote:
USB2.0 Host and OTG controllers in RK3328 are using USB2PHY.
Add support for it.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v2:
- add clkout_ctl
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index e43a5ba9b5..d8738f891d 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -345,6 +345,36 @@ bind_fail:
return ret;
}
+static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
+ {
+ .reg = 0x100,
+ .clkout_ctl = { 0x108, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus= { 0x0100, 15, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
+ .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
+ .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
+ .ls_det_en = { 0x0110, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0114, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
+ .utmi_avalid= { 0x0120, 10, 10, 0, 1 },
+ .utmi_bvalid= { 0x0120, 9, 9, 0, 1 },
+ .utmi_ls= { 0x0120, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus= { 0x104, 15, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x110, 1, 1, 0, 1 },
+ .ls_det_st = { 0x114, 1, 1, 0, 1 },
+ .ls_det_clr = { 0x118, 1, 1, 0, 1 },
+ .utmi_ls= { 0x120, 17, 16, 0, 1 },
+ .utmi_hstdet= { 0x120, 19, 19, 0, 1 }
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
{
.reg= 0xe450,
@@ -498,6 +528,10 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[]
= {
};
static const struct udevice_id rockchip_usb2phy_ids[] = {
+ {
+ .compatible = "rockchip,rk3328-usb2phy",
+ .data = (ulong)&rk3328_usb2phy_cfgs,
+ },
{
.compatible = "rockchip,rk3399-usb2phy",
.data = (ulong)&rk3399_usb2phy_cfgs,
Re: [PATCH v2 1/7] arm64: dts: rockchip: Drop unused rk3328-xhci node
On 2023/6/7 01:09, Jagan Teki wrote:
rk3328-xhci has been added due to the fact that the upstream
dwc3 is unsupported. Moreover, the driver for rk3328-xhci is
not added to the code tree.
By considering these facts and unsupported rk3328-xhci this
patch is dropping all related code from DT. However, the DWC3
is fixed now in dwc3-generic and RK3328 USB 3.0 is functional
in upcoming patches.
Let's drop it.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v2:
- none
arch/arm/dts/rk3328-evb-u-boot.dtsi | 5 -
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 14 --
arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 5 -
arch/arm/dts/rk3328-rock64-u-boot.dtsi| 15 ---
arch/arm/dts/rk3328-u-boot.dtsi | 11 ---
5 files changed, 50 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4bfa0c2330..f9c729d3bd 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -44,8 +44,3 @@
/* Integrated PHY unsupported by U-boot */
status = "broken";
};
-
-&usb_host0_xhci {
- vbus-supply = <&vcc5v0_host_xhci>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 27a454f017..2062f34bf8 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -48,20 +48,6 @@
bootph-pre-ram;
};
-&usb_host0_xhci {
- vbus-supply = <&vcc_host1_5v>;
- status = "okay";
-};
-
-/*
- * This makes XHCI responsible for toggling VBUS. This is needed to work
- * around an issue where either XHCI only works with USB 2.0 or OTG doesn't
- * work, depending on how VBUS is configured. Having USB 3.0 seems better.
- */
-&vcc_host1_5v {
- /delete-property/ regulator-always-on;
-};
-
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
index 088e21c76a..1f220c6dcd 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -45,11 +45,6 @@
bootph-pre-ram;
};
-&usb_host0_xhci {
- vbus-supply = <&vcc_host_5v>;
- status = "okay";
-};
-
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index c20a99a620..849854302e 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -48,21 +48,6 @@
bootph-pre-ram;
};
-&usb_host0_xhci {
- vbus-supply = <&vcc_host_5v>;
- status = "okay";
-};
-
-/*
- * This makes XHCI responsible for toggling VBUS. This is needed to work
- * around an issue where either XHCI only works with USB 2.0 or OTG doesn't
- * work, depending on how VBUS is configured. Having USB 3.0 seems better.
- */
-&vcc_host_5v {
- /delete-property/ regulator-always-on;
- /delete-property/ regulator-boot-on;
-};
-
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 668f8ca29d..ce96ce40a7 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -26,17 +26,6 @@
0x0 0xff72 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
-
- usb_host0_xhci: usb@ff60 {
- compatible = "rockchip,rk3328-xhci";
- reg = <0x0 0xff60 0x0 0x10>;
- interrupts = ;
- snps,dis-enblslpm-quirk;
- snps,phyif-utmi-bits = <16>;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-u2-susphy-quirk;
- status = "disabled";
- };
};
&cru {
Re: [PATCH v2 2/7] configs: Drop unused XHCI_DWC3 for RK3328 boards
On 2023/6/7 01:09, Jagan Teki wrote: Driver support for rk3328 is not supported so drop this unused XHCI_DWC3. Cc: Tianling Shen Cc: David Bauer Cc: Loic Devulder Cc: Chen-Yu Tsai Cc: Banglang Huang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- Changes for v2: - none configs/evb-rk3328_defconfig| 1 - configs/nanopi-r2c-rk3328_defconfig | 1 - configs/nanopi-r2s-rk3328_defconfig | 1 - configs/roc-cc-rk3328_defconfig | 1 - configs/rock-pi-e-rk3328_defconfig | 1 - configs/rock64-rk3328_defconfig | 1 - 6 files changed, 6 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 580ee502dc..5ab7abff9e 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -93,7 +93,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 84710c185b..6af874ca2c 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -97,7 +97,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 21d7a073e2..7b0fadbce9 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -97,7 +97,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 6b3bc75ae9..477179e80e 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -102,7 +102,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 9c67d0c5fe..633d5417a9 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -103,7 +103,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 74a9cc0a7d..ae761d08a1 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -100,7 +100,6 @@ CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y
Re: [PATCH v2 4/7] configs: Enable DWC3 USB 3.0 on RK3328 boards
On 2023/6/7 01:09, Jagan Teki wrote: Enable USB 3.0 in all RK3328 boards. => usb start starting USB... Bus usb@ff5c: ehci_generic usb@ff5c: Failed to get clocks (ret=-19) Port not available. Bus usb@ff5d: USB OHCI 1.0 Bus usb@ff60: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@ff58: 1 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found => usb tree USB device tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 040130e3ee554b7078843f4eb331646 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Cc: Tianling Shen Cc: David Bauer Cc: Loic Devulder Cc: Chen-Yu Tsai Cc: Banglang Huang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- Changes for v2: - none configs/evb-rk3328_defconfig| 2 ++ configs/nanopi-r2c-rk3328_defconfig | 2 ++ configs/nanopi-r2s-rk3328_defconfig | 2 ++ configs/roc-cc-rk3328_defconfig | 2 ++ configs/rock-pi-e-rk3328_defconfig | 2 ++ configs/rock64-rk3328_defconfig | 2 ++ 6 files changed, 12 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 5ab7abff9e..5183d65451 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -69,6 +69,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -100,6 +101,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 6af874ca2c..fb0b8719fb 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -104,6 +105,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 7b0fadbce9..79cb17d751 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -104,6 +105,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 477179e80e..f5912ceca9 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -72,6 +72,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y @@ -109,6 +110,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 633d5417a9..e86a6f7b1a 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -73,6 +73,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y @@ -101,6 +102,7 @@ CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index ae761d08a1..4acbca0140 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -71,6 +71,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y @@ -107,6 +108,7 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_
Re: [PATCH] rockchip: rk3568: Fix alloc space exhausted in SPL
On 2023/7/2 18:43, Jonas Karlman wrote:
Current SYS_MALLOC_F_LEN of 0x2000 (8 KB) used in SPL is too small for
some RK3568 boards. SPL will print following during boot:
alloc space exhausted
Increase the default SYS_MALLOC_F_LEN to 0x2 (128 KB) to mitigate.
Fixes: 2a950e3ba506 ("rockchip: Add rk3568 architecture core")
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3568/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig
b/arch/arm/mach-rockchip/rk3568/Kconfig
index 94e04b79e7d8..4424a3c47be1 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -29,7 +29,7 @@ config SYS_SOC
default "rk3568"
config SYS_MALLOC_F_LEN
- default 0x2000
+ default 0x2
source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
Re: [PATCH v3 5/5] rockchip: rk3568: Use dwc3-generic driver
On 2023/7/17 06:35, Jonas Karlman wrote: Change RK3568 devices to use the newer dwc3-generic driver instead of the old xhci-dwc3 driver for USB 3.0 support. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v3: - No change v2: - No change configs/radxa-cm3-io-rk3566_defconfig | 2 +- configs/rock-3a-rk3568_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 488723dfaa30..f89777184ceb 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -75,8 +75,8 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 753d03914d90..ddb43249654e 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -85,10 +85,10 @@ CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y
Re: [PATCH] rockchip: board: Update Odroid Go2 to Support Additional Revisions
On 2023/5/10 23:55, Chris Morgan wrote:
From: Chris Morgan
Update the board.c file for the Odroid Go Advance to support the
Black Edition and the Odroid Go Super. The Odroid Go Advance Black
Edition differs from the original model with the addition of 2
extra buttons and an ESP8266 WiFi module. The Odroid Go Super
adds an additional 2 buttons compared to the Black Edition, along
with a larger panel and larger battery.
This change uses the value of ADC0 to determine which of these
3 models it is, and then changes the ${fdtfile} environment variable
to match the proper devicetree name in mainline Linux.
Tested on an Odroid Go Advance (first revision) and an Odroid Go Super.
The correct ${fdtfile} variable was set for each device.
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/hardkernel/odroid_go2/go2.c | 103 ++
configs/odroid-go2_defconfig | 1 +
2 files changed, 104 insertions(+)
diff --git a/board/hardkernel/odroid_go2/go2.c
b/board/hardkernel/odroid_go2/go2.c
index 29464ae63e..a0338ead3b 100644
--- a/board/hardkernel/odroid_go2/go2.c
+++ b/board/hardkernel/odroid_go2/go2.c
@@ -2,3 +2,106 @@
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DTB_DIR"rockchip/"
+
+struct oga_model {
+ const u16 adc_value;
+ const char *board;
+ const char *board_name;
+ const char *fdtfile;
+};
+
+enum oga_device_id {
+ OGA,
+ OGA_V11,
+ OGS,
+};
+
+/*
+ * All ADC values from schematic of Odroid Go Advance Black Edition.
+ * Value for OGS is inferred based on schematic and observed values.
+ */
+static const struct oga_model oga_model_details[] = {
+ [OGA] = {
+ 856,
+ "rk3326-odroid-go2",
+ "ODROID-GO Advance",
+ DTB_DIR "rk3326-odroid-go2.dtb",
+ },
+ [OGA_V11] = {
+ 677,
+ "rk3326-odroid-go2-v11",
+ "ODROID-GO Advance Black Edition",
+ DTB_DIR "rk3326-odroid-go2-v11.dtb",
+ },
+ [OGS] = {
+ 85,
+ "rk3326-odroid-go3",
+ "ODROID-GO Super",
+ DTB_DIR "rk3326-odroid-go3.dtb",
+ },
+};
+
+/* Detect which Odroid Go Advance device we are using so as to load the
+ * correct devicetree for Linux. Set an environment variable once
+ * found. The detection depends on the value of ADC channel 0.
+ */
+int oga_detect_device(void)
+{
+ u32 adc_info;
+ int ret, i;
+ int board_id = -ENXIO;
+
+ ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info);
+ if (ret) {
+ printf("Read SARADC failed with error %d\n", ret);
+ return ret;
+ }
+
+ /*
+* Get the correct device from the table. The ADC value is
+* determined by a resistor on ADC channel 0. The manufacturer
+* accounted for this with a 5% tolerance, so assume a +- value
+* of 50 should be enough.
+*/
+ for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) {
+ u32 adc_min = oga_model_details[i].adc_value - 50;
+ u32 adc_max = oga_model_details[i].adc_value + 50;
+
+ if (adc_min < adc_info && adc_max > adc_info) {
+ board_id = i;
+ break;
+ }
+ }
+
+ if (board_id < 0)
+ return board_id;
+
+ env_set("board", oga_model_details[board_id].board);
+ env_set("board_name",
+ oga_model_details[board_id].board_name);
+ env_set("fdtfile", oga_model_details[board_id].fdtfile);
+
+ return 0;
+}
+
+int rk_board_late_init(void)
+{
+ int ret;
+
+ ret = oga_detect_device();
+ if (ret) {
+ printf("Unable to detect device type: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 459ae3d59c..bdc2288af6 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2
CONFIG_SPL_PAD_TO=0x7f8000
Re: [PATCH v3 3/5] usb: dwc3-generic: Relax unsupported dr_mode check
Hi Marek,
Could you help to look at this patch, is there any further comment
for the change?
Thanks,
- Kever
On 2023/7/17 06:35, Jonas Karlman wrote:
When dr_mode is peripheral or otg and U-Boot has not been built with
DM_USB_GADGET support, booting such device may end up with:
dwc3_glue_bind_common: subnode name: usb@fcc0
Error binding driver 'dwc3-generic-wrapper': -6
Some drivers failed to bind
initcall sequence effbca08 failed at call 00a217c8 (err=-6)
### ERROR ### Please RESET the board ###
Instead fail gracfully with ENODEV to allow board continue booting.
dwc3_glue_bind_common: subnode name: usb@fcc0
dwc3_glue_bind_common: unsupported dr_mode 3
Also use CONFIG_IS_ENABLED(USB_HOST) and change switch to if statements
to improve readability of the code.
Signed-off-by: Jonas Karlman
---
v3:
- Update debug message to include dr_mode (Marek Vasut)
v2:
- Change to use CONFIG_IS_ENABLED for USB_HOST
- Refactor switch to if statements (Marek Vasut)
drivers/usb/dwc3/dwc3-generic.c | 27 ---
1 file changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 4d5d500aefab..2331ac453132 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -226,8 +226,7 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
};
#endif
-#if defined(CONFIG_SPL_USB_HOST) || \
- !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)
+#if CONFIG_IS_ENABLED(USB_HOST)
static int dwc3_generic_host_probe(struct udevice *dev)
{
struct xhci_hcor *hcor;
@@ -409,7 +408,7 @@ struct dwc3_glue_ops ti_ops = {
static int dwc3_glue_bind_common(struct udevice *parent, ofnode node)
{
const char *name = ofnode_get_name(node);
- const char *driver = NULL;
+ const char *driver;
enum usb_dr_mode dr_mode;
struct udevice *dev;
int ret;
@@ -421,27 +420,17 @@ static int dwc3_glue_bind_common(struct udevice *parent,
ofnode node)
if (!dr_mode)
dr_mode = usb_get_dr_mode(node);
- switch (dr_mode) {
- case USB_DR_MODE_PERIPHERAL:
- case USB_DR_MODE_OTG:
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+ if (CONFIG_IS_ENABLED(DM_USB_GADGET) &&
+ (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) {
debug("%s: dr_mode: OTG or Peripheral\n", __func__);
driver = "dwc3-generic-peripheral";
-#endif
- break;
-#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
- case USB_DR_MODE_HOST:
+ } else if (CONFIG_IS_ENABLED(USB_HOST) && dr_mode == USB_DR_MODE_HOST) {
debug("%s: dr_mode: HOST\n", __func__);
driver = "dwc3-generic-host";
- break;
-#endif
- default:
- debug("%s: unsupported dr_mode\n", __func__);
+ } else {
+ debug("%s: unsupported dr_mode %d\n", __func__, dr_mode);
return -ENODEV;
- };
-
- if (!driver)
- return -ENXIO;
+ }
ret = device_bind_driver_to_node(parent, driver, name,
node, &dev);
Re: [PATCH v2 7/7] configs: rockchip: Enable USB2PHY for RK3328 boards
On 2023/6/7 01:09, Jagan Teki wrote: Enable USB2PHY for all RK3328 boards. => usb start starting USB... Bus usb@ff5c: USB EHCI 1.00 Bus usb@ff5d: USB OHCI 1.0 Bus usb@ff60: generic_phy_get_bulk : no phys property Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@ff58: USB DWC2 scanning bus usb@ff5c for devices... 2 USB Device(s) found scanning bus usb@ff5d for devices... 1 USB Device(s) found scanning bus usb@ff60 for devices... 2 USB Device(s) found scanning bus usb@ff58 for devices... 2 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Mass Storage (480 Mb/s, 500mA) TS-RDF5A Transcend 0009 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 040130e3ee554b7078843f4eb331646 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Human Interface (12 Mb/s, 98mA) Logitech USB Receiver => dm tree -s Class Index Probed DriverName --- syscon1 [ + ] syscon|-- syscon@ff45 phy 0 [ + ] rockchip_usb2phy | `-- usb2phy@100 clk 2 [ + ] rockchip_usb2phy_clo | |-- usb480m_phy phy 1 [ + ] rockchip_usb2phy_por | |-- otg-port phy 2 [ + ] rockchip_usb2phy_por | `-- host-port sysinfo 0 [ + ] sysinfo_smbios|-- smbios usb 3 [ + ] dwc2_usb |-- usb@ff58 usb_hub 3 [ + ] usb_hub | `-- usb_hub usb_dev_ge0 [ + ] usb_dev_generic_drv | `-- generic_bus_3_dev_2 usb 0 [ + ] ehci_generic |-- usb@ff5c usb_hub 0 [ + ] usb_hub | `-- usb_hub usb_mass_s0 [ + ] usb_mass_storage | `-- usb_mass_storage blk 2 [ + ] usb_storage_blk | |-- usb_mass_storage.lun0 partition 4 [ + ] blk_partition | | |-- usb_mass_storage.lun0:1 partition 5 [ + ] blk_partition | | `-- usb_mass_storage.lun0:2 bootdev 3 [ ] usb_bootdev | `-- usb_mass_storage.lun0.bootdev usb 1 [ + ] ohci_generic `-- usb@ff5d usb_hub 1 [ + ] usb_hub `-- usb_hub Cc: Tianling Shen Cc: David Bauer Cc: Loic Devulder Cc: Chen-Yu Tsai Cc: Banglang Huang Cc: Matwey V. Kornilov Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- Changes for v2: - update commit message. configs/evb-rk3328_defconfig| 1 + configs/nanopi-r2c-rk3328_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 5183d65451..8f53aadbb6 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -74,6 +74,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index fb0b8719fb..583179d7c5 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -76,6 +76,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 79cb17d751..f7ed71e412 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -76,6 +76,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index f5912ceca9..4ac3c9403b 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -79,6 +79,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index e86a6f7b1a..277f691d4d 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig
Re: [PATCH v2 3/7] usb: dwc3-generic: Restrict single ctrl node for RK3328
On 2023/6/7 01:09, Jagan Teki wrote:
Like Rockchip RK3568, the RK3328 also have single node to
represent the glue and ctrl for USB 3.0.
So, use the driver data to use single ctrl for RK3328 DWC3.
Reviewed-by: Marek Vasut
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v2:
- collect Marek RB
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 5f8c2613a4..dcf420bafd 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -621,7 +621,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
{ .compatible = "ti,am654-dwc3" },
- { .compatible = "rockchip,rk3328-dwc3" },
+ { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3" },
Re: [PATCH v2 6/7] clk: rockchip: rk3328: Handle usb480m phy clock
On 2023/6/7 01:09, Jagan Teki wrote: Handle USB480M clock ID in set_rate() and set_parent() to allow the dt assigned-clocks and assigned-clock-parents work on rk3328.dtsi Cc: Lukasz Majewski Cc: Sean Anderson Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- Changes for v2: - add USB480M to set_parent drivers/clk/rockchip/clk_rk3328.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 969b7a8581..ef97381f0e 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case ACLK_GMAC: case PCLK_GMAC: case SCLK_USB3OTG_SUSPEND: + case USB480M: return 0; default: return -ENOENT; @@ -771,6 +772,7 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) case SCLK_MAC2IO_EXT: return rk3328_gmac2io_ext_set_parent(clk, parent); case DCLK_LCDC: + case USB480M: case SCLK_PDM: case SCLK_RTC32K: case SCLK_UART0:
Re: [PATCH 2/2] power: regulator: rk8xx: Add 500us delay after LDO regulator is enabled
Hi Jonas,
On 2023/7/2 20:41, Jonas Karlman wrote:
A quick power cycle of a LDO regulator during dw-mmc signal voltage
change has shown that SD-card does not always get recognized.
Linux driver use an enable_time of 400us for LDO regulators. Apply a
500us delay when a LDO regulator is enabled to fix possible issues.
Does 400us not enough for the board you test?
Hi Elaine,
Could help to check this change?
Thanks,
- Kever
Fixes: 94afc1cb466a ("power: regulator: rk8xx: update the driver for rk808 and
rk818")
Signed-off-by: Jonas Karlman
---
drivers/power/regulator/rk8xx.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index 0ee07ad299d7..e95640a39b0a 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -616,6 +617,9 @@ static int _ldo_set_enable(struct udevice *pmic, int ldo,
bool enable)
break;
}
+ if (enable)
+ udelay(500);
+
return ret;
}
Re: [PATCH 4/4] rockchip: rk356x-u-boot: Use relaxed u-boot,spl-boot-order
On 2023/7/3 01:34, Jonas Karlman wrote:
BootRom will try to load TPL+SPL from media in the following order:
- SPI NOR Flash
- SPI NAND Flash
- NAND Flash
- eMMC
- SDMMC
SPL will try to load FIT from media in the order defined in the device
tree u-boot,spl-boot-order property.
Change the default order to load FIT from to:
- same media as TPL+SPL
- SDMMC
- eMMC
Boards with strict load order requirements should override the
u-boot,spl-boot-order property in the board specific u-boot.dtsi.
Fixes: 42f67fb51cb4 ("rockchip: rk3568: Fix boot device detection")
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk356x-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 89c0d830b632..5644f78ec774 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -12,7 +12,7 @@
};
chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
};
dmc: dmc {
Re: [PATCH 3/4] rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes
On 2023/7/3 01:34, Jonas Karlman wrote:
Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and
UART2 that are typically used by multiple boards. Unreferenced nodes are
removed from the SPL device tree during a normal build.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 -
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 54 -
arch/arm/dts/rk356x-u-boot.dtsi | 64
3 files changed, 64 insertions(+), 110 deletions(-)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index 57b77151c57c..c925439f71cd 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,67 +11,11 @@
};
};
-&emmc_bus8 {
- bootph-all;
-};
-
-&emmc_clk {
- bootph-all;
-};
-
-&emmc_cmd {
- bootph-all;
-};
-
-&emmc_datastrobe {
- bootph-all;
-};
-
-&pinctrl {
- bootph-all;
-};
-
-&pcfg_pull_none {
- bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
- bootph-all;
-};
-
-&pcfg_pull_up {
- bootph-all;
-};
-
-&sdmmc0_bus4 {
- bootph-all;
-};
-
-&sdmmc0_clk {
- bootph-all;
-};
-
-&sdmmc0_cmd {
- bootph-all;
-};
-
-&sdmmc0_det {
- bootph-all;
-};
-
-&sdmmc0_pwren {
- bootph-all;
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
};
-&uart2m0_xfer {
- bootph-all;
-};
-
&uart2 {
clock-frequency = <2400>;
bootph-all;
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 0ba38851c25e..45e9390f202d 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -16,26 +16,6 @@
};
};
-&emmc_bus8 {
- bootph-all;
-};
-
-&emmc_clk {
- bootph-all;
-};
-
-&emmc_cmd {
- bootph-all;
-};
-
-&emmc_datastrobe {
- bootph-all;
-};
-
-&fspi_pins {
- bootph-all;
-};
-
&pcie2x1 {
pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
/* Shared vpcie3v3-supply may cause a sys freeze, disable for now */
@@ -47,8 +27,6 @@
};
&pinctrl {
- bootph-all;
-
pcie {
pcie3x2_reset_h: pcie3x2-reset-h {
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -56,34 +34,6 @@
};
};
-&pcfg_pull_none {
- bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
- bootph-all;
-};
-
-&pcfg_pull_up {
- bootph-all;
-};
-
-&sdmmc0_bus4 {
- bootph-all;
-};
-
-&sdmmc0_clk {
- bootph-all;
-};
-
-&sdmmc0_cmd {
- bootph-all;
-};
-
-&sdmmc0_det {
- bootph-all;
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -117,10 +67,6 @@
status = "disabled";
};
-&uart2m0_xfer {
- bootph-all;
-};
-
&uart2 {
clock-frequency = <2400>;
bootph-all;
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index c340c2bba6ff..89c0d830b632 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -59,6 +59,70 @@
status = "okay";
};
+&pinctrl {
+ bootph-all;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&emmc_bus8 {
+ bootph-all;
+};
+
+&emmc_clk {
+ bootph-all;
+};
+
+&emmc_cmd {
+ bootph-all;
+};
+
+&emmc_datastrobe {
+ bootph-all;
+};
+
+&emmc_rstnout {
+ bootph-all;
+};
+
+&fspi_pins {
+ bootph-all;
+};
+
+&sdmmc0_bus4 {
+ bootph-all;
+};
+
+&sdmmc0_clk {
+ bootph-all;
+};
+
+&sdmmc0_cmd {
+ bootph-all;
+};
+
+&sdmmc0_det {
+ bootph-all;
+};
+
+&sdmmc0_pwren {
+ bootph-all;
+};
+
+&uart2m0_xfer {
+ bootph-all;
+};
+
&sdhci {
bootph-pre-ram;
status = "okay";
Re: [PATCH 2/4] rockchip: rk3566-radxa-cm3-io: Sync dts from linux v6.4
On 2023/7/3 01:34, Jonas Karlman wrote:
Sync rk3566-radxa-cm3-io.dts from linux v6.4.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-radxa-cm3-io.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts
b/arch/arm/dts/rk3566-radxa-cm3-io.dts
index d89d5263cb5e..5e4236af4fcb 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io.dts
+++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts
@@ -254,6 +254,14 @@
status = "okay";
};
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Re: [PATCH 1/4] rockchip: rk356x: Sync dtsi from linux v6.4
On 2023/7/3 01:34, Jonas Karlman wrote:
Sync rk356x.dtsi from linux v6.4.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3568-pinctrl.dtsi | 94
arch/arm/dts/rk356x.dtsi | 14 +++--
2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi
index 8f90c66dd9e9..0a979bfb63d9 100644
--- a/arch/arm/dts/rk3568-pinctrl.dtsi
+++ b/arch/arm/dts/rk3568-pinctrl.dtsi
@@ -3117,4 +3117,98 @@
<0 RK_PA1 0 &pcfg_pull_none>;
};
};
+
+ lcdc {
+ /omit-if-no-ref/
+ lcdc_clock: lcdc-clock {
+ rockchip,pins =
+ /* lcdc_clk */
+ <3 RK_PA0 1 &pcfg_pull_none>,
+ /* lcdc_den */
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ /* lcdc_hsync */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* lcdc_vsync */
+ <3 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ lcdc_data16: lcdc-data16 {
+ rockchip,pins =
+ /* lcdc_d3 */
+ <2 RK_PD3 1 &pcfg_pull_none>,
+ /* lcdc_d4 */
+ <2 RK_PD4 1 &pcfg_pull_none>,
+ /* lcdc_d5 */
+ <2 RK_PD5 1 &pcfg_pull_none>,
+ /* lcdc_d6 */
+ <2 RK_PD6 1 &pcfg_pull_none>,
+ /* lcdc_d7 */
+ <2 RK_PD7 1 &pcfg_pull_none>,
+ /* lcdc_d10 */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* lcdc_d11 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* lcdc_d12 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* lcdc_d13 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* lcdc_d14 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* lcdc_d15 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* lcdc_d19 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* lcdc_d20 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* lcdc_d21 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* lcdc_d22 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* lcdc_d23 */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ lcdc_data18: lcdc-data18 {
+ rockchip,pins =
+ /* lcdc_d2 */
+ <2 RK_PD2 1 &pcfg_pull_none>,
+ /* lcdc_d3 */
+ <2 RK_PD3 1 &pcfg_pull_none>,
+ /* lcdc_d4 */
+ <2 RK_PD4 1 &pcfg_pull_none>,
+ /* lcdc_d5 */
+ <2 RK_PD5 1 &pcfg_pull_none>,
+ /* lcdc_d6 */
+ <2 RK_PD6 1 &pcfg_pull_none>,
+ /* lcdc_d7 */
+ <2 RK_PD7 1 &pcfg_pull_none>,
+ /* lcdc_d10 */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* lcdc_d11 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* lcdc_d12 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* lcdc_d13 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* lcdc_d14 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* lcdc_d15 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* lcdc_d18 */
+ <3 RK_PB3 1 &pcfg
Re: [PATCH v2 2/2] rockchip: edgeble-neu6: Append eMMC into spl-boot-order
Hi Jagan,
On 2023/7/19 16:17, Jagan Teki wrote:
Now, edgeble-neu6 NCM IO boards support eMMC and SDMMC.
So, Update the spl-boot-order to include both.
Signed-off-by: Jagan Teki
---
Changes for v2:
- None
arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 10 ++
arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 10 ++
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 373f369c65..7ddfd98770 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -7,16 +7,10 @@
/ {
aliases {
- mmc0 = &sdmmc;
It would be better to keep "mmc0 = &sdhci " than remove it, otherwise
you may need to add it back for emmc support in U-Boot proper later.
Thanks,
- Kever
+ mmc1 = &sdmmc;
};
chosen {
- stdout-path = &uart2;
- u-boot,spl-boot-order = &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
-
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
index cd7626b24b..2bc1a98ff8 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -7,16 +7,10 @@
/ {
aliases {
- mmc0 = &sdmmc;
+ mmc1 = &sdmmc;
};
chosen {
- stdout-path = &uart2;
- u-boot,spl-boot-order = &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
-
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
Re: [PATCH v2 1/2] arm64: dts: rockchip: Sync DT from linux-next
Hi Jagan,
On 2023/7/19 16:17, Jagan Teki wrote:
Sync the linux-next from below commit,
commit <1642bf66e270> ("arm64: dts: rockchip: add USB2 to
rk3588s-rock5a")
How much difference for the linux-next and the latest linux release version?
It would be better if we can have sync with a release version unless
many important patches are on the way.
Also rops the duplicate usb nodes from rk3588s-u-boot.dtsi
Signed-off-by: Jagan Teki
---
Changes for v2:
- Keep sdhci modes for ROCK5B
arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 -
arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 66 +++
arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 359 ++-
arch/arm/dts/rk3588-evb1-v10.dts | 720 ++-
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 7 -
arch/arm/dts/rk3588-rock-5b.dts | 578 +-
arch/arm/dts/rk3588.dtsi | 112
arch/arm/dts/rk3588s-u-boot.dtsi | 119
arch/arm/dts/rk3588s.dtsi| 499 +++-
include/dt-bindings/ata/ahci.h | 20 +
Why need this ahci header file in the patch?
Thanks,
- Kever
10 files changed, 2346 insertions(+), 135 deletions(-)
create mode 100644 include/dt-bindings/ata/ahci.h
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
index 38e1a1e25f..727580aaa1 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
@@ -25,7 +25,6 @@
no-sdio;
no-sd;
non-removable;
- max-frequency = <2>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
index e9d5a8bab5..9933765e40 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
@@ -21,7 +21,73 @@
};
};
+&combphy0_ps {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = ;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* FAN */
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+/* RS232 */
+&uart6 {
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* RS485 */
+&uart7 {
+ pinctrl-0 = <&uart7m2_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
index 1c5bcf1280..017559bba3 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
@@ -18,6 +18,42 @@
regulator-min-microvolt = <1200>;
regulator-max-microvolt = <1200>;
};
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <110>;
+ regulator-max-microvolt = <110>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
};
&sdhci {
@@ -25,8 +61,329 @@
no-sdio;
no-sd;
non-removable;
- max-frequency = <2>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
+
+&spi2 {
+ status = "okay";
+ assigned-clocks
Re: [PATCH v2 5/5] optee: Support Rockchip OP-TEE binaries
On 2023/7/20 15:39, Alex Bee wrote: Hi Kever, Am 19.07.23 um 09:28 schrieb Kever Yang: Hi Alex, On 2023/7/18 22:57, Alex Bee wrote: Currently the only ARM Rockchip SoC which is supported by upstream optee-os is RK322x. For all other ARM SoCs a vendor-provided OP-TEE binary has to be used to have a TEE available. Those are using a calling convension different from upstream optee-os. This introduces CONFIG_ROCKCHIP_OPTEE_BINARY which signals that any of those vendor binaries is used and changes the calling convension accordingly. Signed-off-by: Alex Bee --- arch/arm/mach-rockchip/Kconfig | 8 common/spl/spl_optee.S | 4 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 17dd43155d..83d8a2a056 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -449,6 +449,14 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_OPTEE_BINARY + bool "Use a OP-TEE binary provided by Rockchip" + depends on SPL_OPTEE_IMAGE + default y if ROCKCHIP_RK3036 || ROCKCHIP_RK3128 || ROCKCHIP_RK3288 This patch is not need for now. the rk3036 works without OPTEE, and rk3288 is able to use ATF instead for OPTEE which upstreamed by Heiko. Thanks for your review. I'm aware of Heiko's ATF BL32 implemenation for RK3288. But what about RK3128/RK3036? They might wwork w/o RK OPTEE-binaries in regards of SMP bringup, but still you have no TEE. You're right: It's not strictly required to have support for RK OPTEE-binaries, but also it doesn't hurt and it's fully optional to use it for those SoCs. Besides RK's TEE-implementations provide some more services via SMCC calls (DVFS for DRAM, for instance) which are not supported (yet) by upstream variants. The mainline U-Boot is target to work with mainline kernel, so we don't need this patch for now. I don't like the requirement of this patch either, but unfortunately the TEE binaries RK provides are built with wrong/incompatible flags. The better way is to push Rockchip TEE to use the same parameter with mainline OP-TEE, I will sync with rockchip OPTEE owner, and I would like this patch stay out of tree for now. Thanks, - Kever Regards, Alex Thanks, - Kever + help + This option enables the usage of vendor-provided OP-TEE binaries. + Say Y if you are using OP-TEE binary provided by Rockchip. + config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S index a269904d38..ea41d8adb6 100644 --- a/common/spl/spl_optee.S +++ b/common/spl/spl_optee.S @@ -7,6 +7,10 @@ #include ENTRY(spl_optee_entry) +#ifdef CONFIG_ROCKCHIP_OPTEE_BINARY + ldr r1, =CONFIG_TEXT_BASE +#else ldr lr, =CONFIG_TEXT_BASE +#endif mov pc, r3 ENDPROC(spl_optee_entry)
Re: [PATCH 7/7] rockchip: chromebook_speedy: Enable sound
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
Commit ec107f04b619 ("rockchip: chromebook_minnie: Enable sound") and
commit 2d0c01b8f0ad ("sound: rockchip: Add sound support for jerry")
enable audio support for chromebook_minnie and chromebook_jerry. Enable
it for chromebook_speedy as well, but put the non-upstream sound node
in the board -u-boot.dtsi instead.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Not enabling these for chromebit_mickey, as that'd use HDMI in a way I
don't know how.
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 14 ++
configs/chromebook_speedy_defconfig | 5 +
2 files changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
index 2a4ba44e0bf9..6bfa84906e35 100644
--- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
@@ -5,6 +5,20 @@
#include "rk3288-veyron-u-boot.dtsi"
+/ {
+ sound {
+ compatible = "rockchip,audio-max98090-jerry";
+
+ cpu {
+ sound-dai = <&i2s 0>;
+ };
+
+ codec {
+ sound-dai = <&max98090 0>;
+ };
+ };
+};
+
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
diff --git a/configs/chromebook_speedy_defconfig
b/configs/chromebook_speedy_defconfig
index f8f2a280f6cf..15b6e21095db 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -52,6 +52,7 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
@@ -99,6 +100,10 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_SOUND=y
+CONFIG_I2S=y
+CONFIG_I2S_ROCKCHIP=y
+CONFIG_SOUND_MAX98090=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
Re: [PATCH 6/7] rockchip: chromebook_jerry: Re-enable MAX98090 codec driver
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
Sound support for chromebook_jerry needs the MAX98090 codec driver. This
was enabled in commit 2d0c01b8f0ad ("sound: rockchip: Add sound support
for jerry"), but apparently lost in commit 7ae2729401bb ("configs:
Resync with savedefconfig"). Enable it again.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/chromebook_jerry_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/chromebook_jerry_defconfig
b/configs/chromebook_jerry_defconfig
index 1a54986d089e..5b601a0b5809 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -102,6 +102,7 @@ CONFIG_ROCKCHIP_SERIAL=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_ROCKCHIP=y
+CONFIG_SOUND_MAX98090=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
Re: [PATCH 5/7] rockchip: veyron: Use TrueType fonts
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
Commit 815ed79d8338 ("video: rockchip: Use TrueType fonts with jerry")
enables makes chromebook_jerry use TrueType fonts. Make other veyron
boards switch to it as well.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
I have no idea why that commit disables USE_PRIVATE_LIBGCC, but I'm
following that change here.
configs/chromebit_mickey_defconfig | 2 ++
configs/chromebook_minnie_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/chromebit_mickey_defconfig
b/configs/chromebit_mickey_defconfig
index f45b14b9d3d1..81efa0fd4cc6 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -107,9 +107,11 @@ CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
+CONFIG_CONSOLE_TRUETYPE=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+# CONFIG_USE_PRIVATE_LIBGCC is not set
CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_minnie_defconfig
b/configs/chromebook_minnie_defconfig
index 01964d13754e..e2302074e8b3 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -112,10 +112,12 @@ CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
+CONFIG_CONSOLE_TRUETYPE=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+# CONFIG_USE_PRIVATE_LIBGCC is not set
CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
Re: [PATCH] pci: rockchip: Release resources on failing probe
On 2023/7/12 07:13, Jonas Karlman wrote:
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4c1 ("pci: pcie_dw_rockchip: release
resources on failing probe").
Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.
Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.
Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pci/pcie_rockchip.c | 108 +++-
1 file changed, 57 insertions(+), 51 deletions(-)
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 72b41398f27b..624841e9d8b8 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -12,23 +12,15 @@
*/
#include
-#include
#include
-#include
#include
#include
#include
-#include
#include
#include
-#include
-#include
#include
-#include
#include
-DECLARE_GLOBAL_DATA_PTR;
-
#define HIWORD_UPDATE(mask, val)(((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
@@ -383,41 +375,38 @@ static int rockchip_pcie_set_vpcie(struct udevice *dev)
struct rockchip_pcie *priv = dev_get_priv(dev);
int ret;
- if (priv->vpcie3v3) {
- ret = regulator_set_enable(priv->vpcie3v3, true);
- if (ret) {
- dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
- ret);
- return ret;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie12v, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie12v (ret=%d)\n", ret);
+ return ret;
}
- if (priv->vpcie1v8) {
- ret = regulator_set_enable(priv->vpcie1v8, true);
- if (ret) {
- dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n",
- ret);
- goto err_disable_3v3;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+ goto err_disable_12v;
}
- if (priv->vpcie0v9) {
- ret = regulator_set_enable(priv->vpcie0v9, true);
- if (ret) {
- dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n",
- ret);
- goto err_disable_1v8;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie1v8, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
+ goto err_disable_3v3;
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->vpcie0v9, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
+ goto err_disable_1v8;
}
return 0;
err_disable_1v8:
- if (priv->vpcie1v8)
- regulator_set_enable(priv->vpcie1v8, false);
+ regulator_set_enable_if_allowed(priv->vpcie1v8, false);
err_disable_3v3:
- if (priv->vpcie3v3)
- regulator_set_enable(priv->vpcie3v3, false);
+ regulator_set_enable_if_allowed(priv->vpcie3v3, false);
+err_disable_12v:
+ regulator_set_enable_if_allowed(priv->vpcie12v, false);
return ret;
}
@@ -427,19 +416,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
int ret;
priv->axi_base = dev_read_addr_name(dev, "axi-base");
- if (!priv->axi_base)
- return -ENODEV;
+ if (priv->axi_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
priv->apb_base = dev_read_addr_name(dev, "apb-base");
- if (!priv->axi_base)
- return -ENODEV;
-
- ret = gpio_request_by_name(dev, "ep-gpios", 0,
- &priv->ep_gpio, GPIOD_IS_OUT);
- if (ret) {
- dev_err(dev, "failed to find ep-gpios property\n");
- return ret;
- }
+ if (priv->apb_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
ret = reset_get_by_name(dev, "core", &priv->core_rst);
if (ret) {
@@ -483,6 +465,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
return r
Re: [PATCH 4/7] rockchip: veyron: Add serial, logging, silent console support
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
Commit eba768c54587 ("rockchip: jerry: Add serial support") enables
ROCKCHIP_SERIAL for chromebook_jerry to make the serial console work
correctly. Enable it also for other veyron boards.
Also enable logging and disable scrolling multiple lines at once as in
chromebook_jerry, and enable silent console as chromebook_minnie does.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/chromebit_mickey_defconfig | 3 +++
configs/chromebook_minnie_defconfig | 3 ++-
configs/chromebook_speedy_defconfig | 1 +
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/configs/chromebit_mickey_defconfig
b/configs/chromebit_mickey_defconfig
index a7c6213a9892..f45b14b9d3d1 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -26,6 +26,8 @@ CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -96,6 +98,7 @@ CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
diff --git a/configs/chromebook_minnie_defconfig
b/configs/chromebook_minnie_defconfig
index 8a4e1858c8bd..01964d13754e 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -27,6 +27,7 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
CONFIG_SILENT_CONSOLE=y
+CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -98,6 +99,7 @@ CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SERIAL=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_ROCKCHIP=y
@@ -114,7 +116,6 @@ CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_speedy_defconfig
b/configs/chromebook_speedy_defconfig
index 45c22f5b103a..f8f2a280f6cf 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -27,6 +27,7 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
CONFIG_SILENT_CONSOLE=y
+CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
Re: [PATCH 3/7] rockchip: veyron: Unify u-boot.dtsi bootph-all fragments
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
The rk3288-veyron-speedy-u-boot.dtsi file duplicates the bootphase dts
fragments from rk3288-veyron-u-boot.dtsi even though it #inclues that.
Deduplicate these into the latter file, which should also make the eMMC
available to the other veyron boards' SPL.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 16
arch/arm/dts/rk3288-veyron-u-boot.dtsi| 4
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
index 90ce9e1395de..2a4ba44e0bf9 100644
--- a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
@@ -15,19 +15,3 @@ &dmc {
0x0 0xc3 0x6 0x1>;
rockchip,sdram-params = <0x20D266A4 0x5B6 6 53300 6 13 0>;
};
-
-&sdmmc {
- bootph-all;
-};
-
-&emmc {
- bootph-all;
-};
-
-&uart2 {
- bootph-all;
-};
-
-&pinctrl {
- bootph-all;
-};
diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
index ab564e73ed00..4f9c59c67573 100644
--- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
@@ -31,6 +31,10 @@ &dmc {
>;
};
+&emmc {
+ bootph-all;
+};
+
&gpio3 {
bootph-all;
};
Re: [PATCH 1/7] rockchip: veyron: Enable RESET driver
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
Commit 70e351bdfeee ("rockchip: jerry: Enable RESET driver") enables
DM_RESET for chromebook_jerry to fix its display as required by changes
to the Rockchip video drivers. Enable it for other veyron boards as
well.
Fixes: cd529f7ad62 ("rockchip: video: edp: Add missing reset support")
Fixes: 9749d2ea29e ("rockchip: video: vop: Add reset support")
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/chromebit_mickey_defconfig | 1 +
configs/chromebook_minnie_defconfig | 1 +
configs/chromebook_speedy_defconfig | 1 +
3 files changed, 3 insertions(+)
diff --git a/configs/chromebit_mickey_defconfig
b/configs/chromebit_mickey_defconfig
index d4302353c5df..a7c6213a9892 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10
CONFIG_SF_DEFAULT_SPEED=2000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC is not set
diff --git a/configs/chromebook_minnie_defconfig
b/configs/chromebook_minnie_defconfig
index 73ab2f62af5e..8a4e1858c8bd 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10
CONFIG_SF_DEFAULT_SPEED=2000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC is not set
diff --git a/configs/chromebook_speedy_defconfig
b/configs/chromebook_speedy_defconfig
index 06437aae18d6..45c22f5b103a 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10
CONFIG_SF_DEFAULT_SPEED=2000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC is not set
Re: [PATCH 5/5] board: rockchip: Add Edgeble Neural Compute Module 6B
On 2023/6/11 14:57, Jagan Teki wrote:
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
based on Rockchip RK3588J from Edgeble AI.
Add support for this SoM and IO board.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 22 +++
arch/arm/mach-rockchip/rk3588/Kconfig | 10 +++
.../neural-compute-module-6/MAINTAINERS | 1 +
configs/neu6b-io-rk3588_defconfig | 64 +++
doc/board/rockchip/rockchip.rst | 1 +
5 files changed, 98 insertions(+)
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
create mode 100644 configs/neu6b-io-rk3588_defconfig
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
new file mode 100644
index 00..cd7626b24b
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rk3588j-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = &sdmmc;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 5eecd26f86..82fe142264 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -19,6 +19,16 @@ config TARGET_RK3588_NEU6
IO board and Neu6a needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform.
+ Neu6B:
+ Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
+ based on Rockchip RK3588J from Edgeble AI.
+
+ Neu6A-IO:
+ Neural Compute Module 6B(Neu6B) IO board is an industrial form factor
+ IO board and Neu6a needs to mount on top of this IO board in order to
+ create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform.
+
+config TARGET_ROCK5B_RK3588
config TARGET_ROCK5B_RK3588
bool "Radxa ROCK5B RK3588 board"
select BOARD_LATE_INIT
diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS
b/board/edgeble/neural-compute-module-6/MAINTAINERS
index 249df957f1..bc7f9b0e68 100644
--- a/board/edgeble/neural-compute-module-6/MAINTAINERS
+++ b/board/edgeble/neural-compute-module-6/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F:board/edgeble/neural-compute-module-6
F:include/configs/neural-compute-module-6.h
F:configs/neu6a-io-rk3588_defconfig
+F: configs/neu6b-io-rk3588_defconfig
diff --git a/configs/neu6b-io-rk3588_defconfig
b/configs/neu6b-io-rk3588_defconfig
new file mode 100644
index 00..c7bc3b1965
--- /dev/null
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a0
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_TARGET_RK3588_NEU6=y
+CONFIG_SPL_STACK=0x40
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x400
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 1f46924a3d..32df1497
Re: [PATCH 4/5] arm64: dts: rockchip: Add rk3588 Edgeble Neu6B
On 2023/6/11 14:57, Jagan Teki wrote:
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
based on Rockchip RK3588J from Edgeble AI.
General features:
- Rockchip RK3588J
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
- On module WiFi6/BT
Neural Compute Module 6B(Neu6B) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
General features:
- microSD slot
- 1x HDMI Out
- 1x HDMI In
- 2x DP
- 1x eDP
- 2x MIPI DSI connector
- 4x MIPI CSI2 connector
- 2x USB Host
- 2x USB 3.0 OTG/Host
- 1x SATA
- 1x 2.5Gbps Ethernet
- 1x M.2 B-Key for 4G/5G cards
- 1x M.2 M-Key slot
- 1x Onboard PoE
- 1x RS485, RS232, CAN
- 1x Audio, MIC port
- RTC battery slot
- 40-pin GPIO expansion
Neu6B needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6B(Neu6B) IO platform.
Kernel commits:
commit <5f06c3f508f7> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6
Model B SoM")
commit <3a9181a43b94> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6
Model B IO")
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 27
arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 32
3 files changed, 60 insertions(+)
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6b-io.dts
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6b.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..145e14eae9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -173,6 +173,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
+ rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
rk3588-rock-5b.dtb
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
new file mode 100644
index 00..e9d5a8bab5
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rk3588j.dtsi"
+#include "rk3588-edgeble-neu6b.dtsi"
+
+/ {
+ model = "Edgeble Neu6B IO Board";
+ compatible = "edgeble,neural-compute-module-6b-io",
+"edgeble,neural-compute-module-6b", "rockchip,rk3588";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
new file mode 100644
index 00..1c5bcf1280
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <2>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
Re: [PATCH 2/7] rockchip: veyron: Enable building SPI ROM images
On 2023/7/8 03:16, Alper Nebi Yasak wrote:
Commit 9b312e26fc77 ("rockchip: Enable building a SPI ROM image on
jerry") produces a u-boot.rom file for chromebook_jerry, intended to be
written to SPI flash. Build this file for other veyron boards as well,
especially because they are already configured only to boot from SPI.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig
b/arch/arm/mach-rockchip/rk3288/Kconfig
index ea94ad114247..69a5614b449a 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,7 +16,9 @@ config TARGET_CHROMEBOOK_JERRY
config TARGET_CHROMEBIT_MICKEY
bool "Google/Rockchip Veyron-Mickey Chromebit"
+ select HAS_ROM
select BOARD_LATE_INIT
+ select ROCKCHIP_SPI_IMAGE
help
Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
and WiFi. It has a separate power port and is designed to connect
@@ -26,7 +28,9 @@ config TARGET_CHROMEBIT_MICKEY
config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
+ select HAS_ROM
select BOARD_LATE_INIT
+ select ROCKCHIP_SPI_IMAGE
help
Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
@@ -37,7 +41,9 @@ config TARGET_CHROMEBOOK_MINNIE
config TARGET_CHROMEBOOK_SPEEDY
bool "Google/Rockchip Veyron-Speedy Chromebook"
+ select HAS_ROM
select BOARD_LATE_INIT
+ select ROCKCHIP_SPI_IMAGE
help
Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
micro HDMI, an 11.6 inch display, micro-SD card,
Re: [PATCH 2/5] arm64: dts: rockchip: Add Rockchip RK3588J
On 2023/6/11 14:57, Jagan Teki wrote:
Rockchip RK3588J is the industrial-grade version of RK3588 SoC and
is operated with -40 °C to +85 °C temparature.
Add rk3588j specific dtsi for adding rk3588j specific operating points
and other changes to be add in future.
Kernel commit:
commit <8274a04ff1dc> ("arm64: dts: rockchip: Add Rockchip RK3588J")
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588j.dtsi | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 arch/arm/dts/rk3588j.dtsi
diff --git a/arch/arm/dts/rk3588j.dtsi b/arch/arm/dts/rk3588j.dtsi
new file mode 100644
index 00..38b9dbf38a
--- /dev/null
+++ b/arch/arm/dts/rk3588j.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "rk3588.dtsi"
Re: [PATCH 3/5] ARM: dts: rockchip: Add rk3588j-u-boot.dtsi
On 2023/6/11 14:57, Jagan Teki wrote: Add rk3588j-u-boot.dtsi for adding U-Boot specific nodes and properties for Rockchip RK3588J SoC. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/dts/rk3588j-u-boot.dtsi | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 arch/arm/dts/rk3588j-u-boot.dtsi diff --git a/arch/arm/dts/rk3588j-u-boot.dtsi b/arch/arm/dts/rk3588j-u-boot.dtsi new file mode 100644 index 00..f5c9e329a5 --- /dev/null +++ b/arch/arm/dts/rk3588j-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rk3588-u-boot.dtsi"
Re: [PATCH 1/5] arch: rockchip: rk3588: Fix missing suffix 'A' for Edgeble Neu6A
On 2023/6/11 14:57, Jagan Teki wrote:
Add missing suffix 'A' for Edgeble Neu6A SoM and IO boards.
Fixes: <15b2d1fb727> ("board: rockchip: Add Edgeble Neural Compute
Module 6")
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10 +-
doc/board/rockchip/rockchip.rst | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 3596b82f1f..5eecd26f86 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -10,14 +10,14 @@ config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
help
- Neu6:
- Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module
+ Neu6A:
+ Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
- Neu6-IO:
- Neural Compute Module 6(Neu6) IO board is an industrial form factor
+ Neu6A-IO:
+ Neural Compute Module 6A(Neu6A) IO board is an industrial form factor
IO board and Neu6a needs to mount on top of this IO board in order to
- create complete Edgeble Neural Compute Module 6(Neu6) IO platform.
+ create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform.
config TARGET_ROCK5B_RK3588
bool "Radxa ROCK5B RK3588 board"
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 99376fb54c..1f46924a3d 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -98,7 +98,7 @@ List of mainline supported Rockchip boards:
* rk3588
- Rockchip EVB (evb-rk3588)
- - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588)
+ - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Radxa ROCK 5B (rock5b-rk3588)
* rv1108
Re: [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget
On 2023/5/29 18:01, Eugen Hristev wrote: Enable configuration for USB 3.0 controller, the commands required, and the gadget drivers. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock5b-rk3588_defconfig | 14 ++ 1 file changed, 14 insertions(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index a4a3c0afd178..3f28a68f0c94 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,9 +47,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x6 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -59,6 +61,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -76,6 +79,7 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y @@ -86,10 +90,16 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y @@ -98,4 +108,8 @@ CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_PRODUCT_NUM=0x350b +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y
Re: [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support
On 2023/5/29 18:01, Eugen Hristev wrote:
Enable the USB3.0 host node, and gadget node.
The gadget is available through the USB type C connector on the board.
The connector is tied to a Fairchild fusb302b device, which currently
does not have a driver in U-boot, but the node is here for correct
description of the board + Linux future compatibility.
It will be easier to move the node as-is when it will be available
in the DT from Linux
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 197
1 file changed, 197 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1cd8a57a6fa6..5a3292699640 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
/ {
aliases {
@@ -18,6 +19,25 @@
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -29,6 +49,28 @@
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ enable-active-high;
+ gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_usb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ };
};
&combphy0_ps {
@@ -85,6 +127,16 @@
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pcfg_pull_none {
@@ -168,6 +220,15 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ rockchip,typec-vbus-det;
+ status = "okay";
+};
+
&u2phy2 {
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
reset-names = "phy", "apb";
@@ -209,3 +270,139 @@
status = "okay";
};
+&usbdp_phy0 {
+ orientation-switch;
+ svid = <0xff01>;
+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+ };
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0
Re: [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices
On 2023/5/29 18:01, Eugen Hristev wrote:
From: Joseph Chen
Add support for the USB 3.0 devices in rk3588:
- USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in
rk3588s
- USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in
rk3588 only
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface
as usbdp_phy0
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface
as usbdp_phy1
- USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0
mode
- associated GRFs (general register files) for the devices.
Signed-off-by: Joseph Chen
[eugen.hris...@collabora.com: move nodes to right place, adapt from latest
linux kernel]
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588-u-boot.dtsi | 93 +++
arch/arm/dts/rk3588s-u-boot.dtsi | 105 +++
2 files changed, 198 insertions(+)
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 4c8ac804d615..68b419f3abd5 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -5,3 +5,96 @@
#include "rockchip-u-boot.dtsi"
#include "rk3588s-u-boot.dtsi"
+
+/ {
+ usbdrd3_1: usbdrd3_1 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+<&cru ACLK_USB3OTG1>;
+ clock-names = "ref", "suspend", "bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_1: usb@fc40 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfc40 0x0 0x40>;
+ interrupts = ;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ reset-names = "usb3-otg";
+ dr_mode = "host";
+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ };
+ };
+
+ usbdpphy1_grf: syscon@fd5cc000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+"simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2-phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ interrupts = ;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru
SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ rockchip,usbctrl-grf = <&usb_grf>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usbdp_phy1: phy@fed9 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed9 0x0 0x1>;
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+<&cru CLK_USBDP_PHY1_IMMORTAL>,
+<&cru PCLK_USBDPPHY1>,
+<&u2phy1>;
+ clock-names = "refclk", "immortal"
Re: [PATCH v1] configs: rockchip: rock5b-rk3588: Enable CONFIG_PCI_INIT_R
On 2023/7/3 18:41, Christopher Obbard wrote: Enable CONFIG_PCI_INIT_R for rock5b pci enumeration during boot in order to autodetect the PCI ethernet NIC during the boot process. Signed-off-by: Christopher Obbard Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock5b-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index c1155c20ef..ed2d0cc54a 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -33,6 +33,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
Re: [PATCH 1/4] phy: rockchip: add usbdp combo phy driver
On 2023/5/29 18:01, Eugen Hristev wrote:
From: Frank Wang
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.
Signed-off-by: Frank Wang
[eugen.hris...@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++
include/linux/usb/phy-rockchip-usbdp.h| 70 ++
4 files changed, 958 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
create mode 100644 include/linux/usb/phy-rockchip-usbdp.h
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index f87ca8c31060..0247d93ab401 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3
It could support PCIe Gen3 single root complex, and could
also be able splited into multiple combinations of lanes.
+config PHY_ROCKCHIP_USBDP
+ tristate "Rockchip USBDP COMBO PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip USB3.0/DP
+ combo PHY with Samsung IP block.
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 25a803a8a86f..7fdbd107976d 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c
b/drivers/phy/rockchip/phy-rockchip-usbdp.c
new file mode 100644
index ..baf92529348c
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define BIT_WRITEABLE_SHIFT16
+
+enum {
+ UDPHY_MODE_NONE = 0,
+ UDPHY_MODE_USB = BIT(0),
+ UDPHY_MODE_DP = BIT(1),
+ UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
+};
+
+struct udphy_grf_reg {
+ unsigned intoffset;
+ unsigned intbitend;
+ unsigned intbitstart;
+ unsigned intdisable;
+ unsigned intenable;
+};
+
+/**
+ * struct reg_sequence - An individual write from a sequence of writes.
+ *
+ * @reg: Register address.
+ * @def: Register value.
+ * @delay_us: Delay to be applied after the register write in microseconds
+ *
+ * Register/value pairs for sequences of writes with an optional delay in
+ * microseconds to be applied after each write.
+ */
+struct reg_sequence {
+ unsigned int reg;
+ unsigned int def;
+ unsigned int delay_us;
+};
+
+struct udphy_grf_cfg {
+ /* u2phy-grf */
+ struct udphy_grf_regbvalid_phy_con;
+ struct udphy_grf_regbvalid_grf_con;
+
+ /* usb-grf */
+ struct udphy_grf_regusb3otg0_cfg;
+ struct udphy_grf_regusb3otg1_cfg;
+
+ /* usbdpphy-grf */
+ struct udphy_grf_reglow_pwrn;
+ struct udphy_grf_regrx_lfps;
+};
+
+struct rockchip_udphy;
+
+struct rockchip_udphy_cfg {
+ /* resets to be requested */
+ const char * const *rst_list;
+ int num_rsts;
+
+ struct udphy_grf_cfg grfcfg;
+ int (*combophy_init)(struct rockchip_udphy *udphy);
+};
+
+struct rockchip_udphy {
+ struct udevice *dev;
+ struct regmap *pma_regmap;
+ struct regmap *u2phygrf;
+ struct regmap *udphygrf;
+ struct regmap *usbgrf;
+ struct regmap *vogrf;
+
+ /* clocks and rests */
+ struct reset_ctl *rsts;
+
+ /* PHY status management */
+ bool flip;
+ bool mode_change;
+ u8 mode;
+ u8 status;
+
+ /* utilized for USB */
+ bool hs; /* flag for high-speed */
+
+ /* utilized for DP */
+ struct gpio_desc *sbu1_dc_gpio;
+ struct gpio_desc *sbu2_dc_gpio;
+ u32 lane_mux_sel[4];
+ u32 dp_lane_sel[4];
+ u32 dp_aux_dout_sel;
+ u32 dp_aux_din_sel;
+ int id;
+
+ /* PHY const config */
+ const struct rockchip_udphy_cfg *cfgs;
+};
+
+static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
+ {0x0090,
Re: [PATCH v4 2/2] board: rockchip: add Radxa ROCK5A Rk3588 board
On 2023/7/5 03:05, Eugen Hristev wrote:
ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specifications:
Rockchip Rk3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
4-lane MIPI DSI connector
Audio – 3.5mm earphone jack
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60
Gigabit Ethernet RJ45 with optional PoE support
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 56mm (Raspberry Pi 4 form factor)
Kernel commits:
d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board")
991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a")
304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a")
cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on
rk3588s-rock5a")
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Resent with correct email addresses
Changes in v4:
- tweaked the defconfig as reviewed by Jonas
- moved some of bootph-all to rk3588s-u-boot.dtsi
- renamed fdt fixup function
Changes in v3:
- forgot to add defconfig and include file, added now, sorry
Changes in v2:
-fixed wrong Kconfig text (rk3588s instead of rk3588)
-changed doc name (rk3588s instead of rk3588)
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi| 34 ++
arch/arm/dts/rk3588s-rock-5a.dts| 73 +
arch/arm/mach-rockchip/rk3588/Kconfig | 28
board/radxa/rock5a-rk3588s/Kconfig | 15 +
board/radxa/rock5a-rk3588s/MAINTAINERS | 6 ++
board/radxa/rock5a-rk3588s/Makefile | 6 ++
board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 +++
configs/rock5a-rk3588s_defconfig| 72
doc/board/rockchip/rockchip.rst | 1 +
include/configs/rock5a-rk3588s.h| 15 +
11 files changed, 290 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588s-rock-5a.dts
create mode 100644 board/radxa/rock5a-rk3588s/Kconfig
create mode 100644 board/radxa/rock5a-rk3588s/MAINTAINERS
create mode 100644 board/radxa/rock5a-rk3588s/Makefile
create mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
create mode 100644 configs/rock5a-rk3588s_defconfig
create mode 100644 include/configs/rock5a-rk3588s.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa6065..cd9b96c5ba7c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
new file mode 100644
index ..9bb0e4f89e11
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588s-u-boot.dtsi"
+#include
+#include
+#include
+#include
+
+/ {
+ aliases {
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe
&emmc_rstnout>;
+};
+
diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts
new file mode 100644
index ..901825514f9d
--- /dev/null
+++ b/arch/arm/dts/rk3588s-rock-5a.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Radxa ROCK 5 Model A";
+ compatible = "radxa,rock-5a", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii";
+ pinctrl-0 = <&gmac1_miim
+&gmac1_tx_bus2
+
Re: [PATCH v4 1/2] ARM: dts: rockchip: rk3588: Move bootph-all props to common file
On 2023/7/5 03:05, Eugen Hristev wrote:
Move bootph-all prop to common SoC dt file, because they are typically used
by multiple boards.
Unreferenced nodes are removed from the SPL device tree during a
normal build.
Suggested-by: Jonas Karlman
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Resent with correct mail addresses
Changes in v4:
- new patch
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 54
arch/arm/dts/rk3588s-u-boot.dtsi| 56 +
2 files changed, 56 insertions(+), 54 deletions(-)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index f453aeeaf526..2a80422390e7 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -77,26 +77,6 @@
status = "okay";
};
-&emmc_bus8 {
- bootph-all;
-};
-
-&emmc_clk {
- bootph-all;
-};
-
-&emmc_cmd {
- bootph-all;
-};
-
-&emmc_data_strobe {
- bootph-all;
-};
-
-&emmc_rstnout {
- bootph-all;
-};
-
&fspim2_pins {
bootph-all;
};
@@ -109,8 +89,6 @@
};
&pinctrl {
- bootph-all;
-
pcie {
pcie_reset_h: pcie-reset-h {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -139,39 +117,11 @@
};
};
-&pcfg_pull_none {
- bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
- bootph-all;
-};
-
-&pcfg_pull_up {
- bootph-all;
-};
-
&sdmmc {
bus-width = <4>;
status = "okay";
};
-&sdmmc_bus4 {
- bootph-all;
-};
-
-&sdmmc_clk {
- bootph-all;
-};
-
-&sdmmc_cmd {
- bootph-all;
-};
-
-&sdmmc_det {
- bootph-all;
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -199,10 +149,6 @@
};
};
-&uart2m0_xfer {
- bootph-all;
-};
-
&usb_host0_ehci {
companion = <&usb_host0_ohci>;
phys = <&u2phy2_host>;
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index acb1cfe20063..2d0b0d8ce2fc 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -302,6 +302,42 @@
};
};
+&emmc_bus8 {
+ bootph-all;
+};
+
+&emmc_clk {
+ bootph-all;
+};
+
+&emmc_cmd {
+ bootph-all;
+};
+
+&emmc_data_strobe {
+ bootph-all;
+};
+
+&emmc_rstnout {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
&xin24m {
bootph-all;
status = "okay";
@@ -335,12 +371,32 @@
u-boot,spl-fifo-mode;
};
+&sdmmc_bus4 {
+ bootph-all;
+};
+
+&sdmmc_clk {
+ bootph-all;
+};
+
+&sdmmc_cmd {
+ bootph-all;
+};
+
+&sdmmc_det {
+ bootph-all;
+};
+
&uart2 {
clock-frequency = <2400>;
bootph-pre-ram;
status = "okay";
};
+&uart2m0_xfer {
+ bootph-all;
+};
+
&ioc {
bootph-pre-ram;
};
Re: [PATCH 2/2] rockchip: rk3588-rock-5b: Fix SPI Flash alias
On 2023/7/12 20:22, Jonas Karlman wrote:
The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") enabled SPI flash support by adding a spi0 alias.
Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and
SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.
Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 1 -
arch/arm/dts/rk3588s-u-boot.dtsi| 9 +
configs/rock5b-rk3588_defconfig | 3 +++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1cd8a57a6fa6..fc2825931a30 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,7 +11,6 @@
/ {
aliases {
mmc1 = &sdmmc;
- spi0 = &sfc;
};
chosen {
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index c703e41802b6..53b514ac52c0 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -7,6 +7,15 @@
#include
/ {
+ aliases {
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ spi5 = &sfc;
+ };
+
dmc {
compatible = "rockchip,rk3588-dmc";
bootph-all;
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 17205a56cd99..f35886d9ffd1 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -56,6 +56,7 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -68,6 +69,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_ETH_DESIGNWARE=y
Re: [PATCH 1/2] rockchip: rk3568-rock-3a: Fix SPI Flash alias
On 2023/7/12 20:22, Jonas Karlman wrote:
The commit 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI
NOR flash") enabled SPI flash support by overriding the spi0 alias.
Correct this by adding a new spi4 alias in rk356x-u-boot.dtsi and
SF_DEFAULT_BUS=4 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.
Fixes: 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 4
arch/arm/dts/rk356x-u-boot.dtsi | 1 +
configs/rock-3a-rk3568_defconfig| 3 +++
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 45e9390f202d..6d1d3731d1da 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -7,10 +7,6 @@
#include "rk356x-u-boot.dtsi"
/ {
- aliases {
- spi0 = &sfc;
- };
-
chosen {
stdout-path = &uart2;
};
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 5644f78ec774..d21b18205220 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -9,6 +9,7 @@
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
+ spi4 = &sfc;
};
chosen {
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index cc3677e93b7a..c8b3e0430b6d 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -56,6 +56,7 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -68,6 +69,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_ETH_DESIGNWARE=y
Re: [PATCH] configs: rockchip: drop useless DEBUG_UART_SKIP_INIT
On 2023/7/17 00:53, Pegorer Massimo wrote: DEBUG_UART_SKIP_INIT feature is implemented only by s5p (DEBUG_UART_S5P) and pl01x (DEBUG_UART_PL010 or DEBUG_UART_PL011) serial drivers, but all ARCH_ROCKCHIP configs rely on default DEBUG_UART_NS16550. The ns16550 serial driver does not depends on DEBUG_UART_SKIP_INIT, so drop it from rockchip configs. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang Thanks, - Kever --- I have tested this building all of next configs, and the resulting images do not depend on DEBUG_UART_SKIP_INIT (i.e. they are the same with or without DEBUG_UART_SKIP_INIT), as expected. IMO, DEBUG_UART_SKIP_INIT name and its description seem a little bit misleading, as suggesting this feature provides skipping debug uart init at all, while instead its related just to skip init of serial driver used for debug uart. BTW maybe depends on DEBUG_UART_PL010 || DEBUG_UART_PL011 || DEBUG_UART_S5P can be added to DEBUG_UART_SKIP_INIT. configs/evb-px30_defconfig| 1 - configs/evb-px5_defconfig | 1 - configs/evb-rk3308_defconfig | 1 - configs/evb-rk3328_defconfig | 1 - configs/firefly-px30_defconfig| 1 - configs/geekbox_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/odroid-go2_defconfig | 1 - configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/ringneck-px30_defconfig | 1 - configs/roc-cc-rk3308_defconfig | 1 - configs/rock-pi-e-rk3328_defconfig| 1 - configs/rock-pi-s-rk3308_defconfig| 1 - configs/sheep-rk3368_defconfig| 1 - 16 files changed, 16 deletions(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 4ac161683c..d75329d385 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -100,7 +100,6 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 29f7516e75..5f32c92674 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -76,7 +76,6 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_PANIC_HANG=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 6950b5ba06..a13a809c1e 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 580ee502dc..9bfb8f1df2 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -87,7 +87,6 @@ CONFIG_TPL_RAM=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 47c924c3df..11a3baa7a3 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -99,7 +99,6 @@ CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index fdd01b6494..8f4be79831 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -26,7 +26,6 @@ CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 2a180609b2..7c55b3be0d 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -95,7 +95,6 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 459ae3d59c..0a20a3011c 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -103,7 +103,6 @@ CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_SKIP_INIT=y
Re: [PATCH v1 2/2] arm: rockchip: Add Radxa ROCK 4SE
On 2023/7/20 00:33, Christopher Obbard wrote:
Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE
board. This board offers similar peripherals in a similar form-factor to
the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor
(which has different OPP table than the RK3399) and other minimal hardware
changes.
Kernel tag: next-20230719
Kernel commits:
- 86a0e14a82ea ("arm64: dts: rockchip: Add Radxa ROCK 4SE")
Signed-off-by: Christopher Obbard
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-rock-4se.dts | 65 +++
board/rockchip/evb_rk3399/MAINTAINERS| 6 ++
configs/rock-4se-rk3399_defconfig| 100 +++
doc/board/rockchip/rockchip.rst | 2 +-
6 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rock-4se.dts
create mode 100644 configs/rock-4se-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 07b26df275..69c6f74636 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -159,6 +159,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-4c-plus.dtb \
+ rk3399-rock-4se.dtb \
rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \
diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
new file mode 100644
index 00..85ee5770ad
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-rock-pi-4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rock-4se.dts b/arch/arm/dts/rk3399-rock-4se.dts
new file mode 100644
index 00..7cfc198bba
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4se.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar
+ * Copyright (c) 2019 Pragnesh Patel
+ */
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-t-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK 4SE";
+ compatible = "radxa,rock-4se", "rockchip,rk3399";
+
+ aliases {
+ mmc2 = &sdio0;
+ };
+};
+
+&pinctrl {
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio0 {
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = ;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ max-speed = <150>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&vcc5v0_host {
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index 5be58f80f9..7d931dfd3a 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -80,6 +80,12 @@ F: configs/orangepi-rk3399_defconfig
F:arch/arm/dts/rk3399-u-boot.dtsi
F:arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+ROCK-4SE
+M: Christopher Obbard
+S: Maintained
+F: configs/rock-4se-rk3399_defconfig
+F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
+
ROCK-PI-4
M:Akash Gajjar
M:Jagan Teki
diff --git a/configs/rock-4se-rk3399_defconfig
b/configs/rock-4se-rk3399_defconfig
new file mode 100644
index 00..9abe8bf853
--- /dev/null
+++ b/configs/rock-4se-rk3399_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER
Re: [PATCH v1 1/2] arm: rockchip: sync ROCK Pi 4 SoCs from Linux
On 2023/7/20 00:33, Christopher Obbard wrote:
To prepare for ROCK 4 SE support, changes are needed to the common ROCK
Pi 4 devicetree to move the OPP from the common devicetree to individual
board devicetrees. Sync the Rockchip RK3399 ROCK Pi 4-related DTs from
Linux to gain from these changes.
Kernel tag: next-20230719
Kernel commits:
cfa12c32b96f ("arm64: dts: rockchip: correct wifi interrupt flag in Rock \
Pi 4B")
cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4")
2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+")
fd2762a62646 ("arm64: dts: rockchip: Move OPP table from ROCK Pi 4 dtsi")
Signed-off-by: Christopher Obbard
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-rock-4c-plus.dts | 3 +--
arch/arm/dts/rk3399-rock-pi-4.dtsi | 5 ++---
arch/arm/dts/rk3399-rock-pi-4a.dts | 1 +
arch/arm/dts/rk3399-rock-pi-4c.dts | 1 +
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts
b/arch/arm/dts/rk3399-rock-4c-plus.dts
index 028eb508ae..8bfd5f88d1 100644
--- a/arch/arm/dts/rk3399-rock-4c-plus.dts
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -548,9 +548,8 @@
&sdhci {
max-frequency = <15000>;
bus-width = <8>;
- mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
non-removable;
- mmc-hs400-enhanced-strobe;
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi
index 907071d4fe..b1b7f4ffb1 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi
@@ -9,7 +9,6 @@
#include
#include
#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
/ {
aliases {
@@ -645,9 +644,9 @@
};
&sdhci {
+ max-frequency = <15000>;
bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
+ mmc-hs200-1_8v;
non-removable;
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts
b/arch/arm/dts/rk3399-rock-pi-4a.dts
index 89f2af5e11..931334aa3d 100644
--- a/arch/arm/dts/rk3399-rock-pi-4a.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4a.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-opp.dtsi"
/ {
model = "Radxa ROCK Pi 4A";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts
b/arch/arm/dts/rk3399-rock-pi-4c.dts
index 4053ba7261..d32efab74e 100644
--- a/arch/arm/dts/rk3399-rock-pi-4c.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4c.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
+#include "rk3399-opp.dtsi"
/ {
model = "Radxa ROCK Pi 4C";
Re: [PATCH v1 0/2] Add support for Radxa ROCK 4SE
Hi Tom, On 2023/7/20 02:43, Tom Rini wrote: On Wed, Jul 19, 2023 at 05:33:55PM +0100, Christopher Obbard wrote: Add support for the RK3399T-based Radxa ROCK 4SE board. This board offers similar peripherals and form-factor to the ROCK Pi 4B but uses the cost-optimised RK3399T processor (which has different a OPP table but otherwise minimal changes) and some other minor hardware changes between the Rock Pi 4B (described in the devicetree). The first patch syncs the RK3399-based ROCK Pi 4 boards from Linux, moving the RK3399 OPP table from the generic Radxa ROCK Pi 4 dtsi into board-specific devicetree files, in preparation for the ROCK 4SE devicetree file. The second patch adds support for the Radxa ROCK 4SE. Christopher Obbard (2): arm: rockchip: sync ROCK Pi 4 SoCs from Linux arm: rockchip: Add Radxa ROCK 4SE It would be really good for someone to convert include/configs/rk3399_common.h to using the plain text environment, I will do this convert. Thanks, - Kever is my main feedback on this series. That's not a NAK mind you, but, it would be good to get some cleanups done in this area. Thanks!
Re: [PATCH] rockchip: px30: Define variables for compressed image support
On 2023/7/25 20:58, Paul Kocialkowski wrote: The standard boot path expects the kernel_comp_addr_r and kernel_comp_size variables for booting compressed kernel images. Define them using the previous kernel_addr_c value (likely initially meant for this purpose) and usual size. This was tested on the PX30 EVB to successfully boot compressed Linux kernel images. Signed-off-by: Paul Kocialkowski Reviewed-by: Kever Yang Thanks, - Kever --- include/configs/px30_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 6fbd2679f099..13ed9011764b 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -21,8 +21,9 @@ "pxefile_addr_r=0x0060\0" \ "fdt_addr_r=0x0830\0" \ "kernel_addr_r=0x0028\0" \ - "kernel_addr_c=0x03e8\0" \ - "ramdisk_addr_r=0x0a20\0" + "ramdisk_addr_r=0x0a20\0" \ + "kernel_comp_addr_r=0x03e8\0" \ + "kernel_comp_size=0x200\0" #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \
Re: [PATCH v2] board: rockchip: Add Radxa E25 Carrier Board
On 2023/7/25 20:05, Jonas Karlman wrote:
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header.
Features tested on a Radxa E25 v1.4:
- SD-card boot
- eMMC boot
- USB host
- PCIe/Ethernet adapters is detected
- SATA
Device tree is imported from linux v6.4.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v2:
- Remove the unneeded always-on/boot-on prop of vcc3v3_pi6c_05
- Drop PCI_INIT_R=y and add MMC_HS200_SUPPORT=y to speed up boot
- Enable sata1 node and set correct regulator to combphy1 node,
can be dropped in a future DT sync once linux patch [1] lands
This patch depends on the series "board: rockchip: Add Pine64 Quartz64
and SOQuartz boards" [2] and all its depends.
A copy of this patch and all its depends can be found at [3].
[1]
https://lore.kernel.org/linux-rockchip/20230724145213.3833099-1-jo...@kwiboo.se/
[2] https://patchwork.ozlabs.org/project/uboot/list/?series=365266
[3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-radxa-e25-v2
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++
arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 57 +++
arch/arm/dts/rk3568-radxa-e25.dts | 228
board/rockchip/evb_rk3568/MAINTAINERS | 8 +
configs/radxa-e25-rk3568_defconfig| 94 +
doc/board/rockchip/rockchip.rst | 1 +
7 files changed, 804 insertions(+)
create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi
create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts
create mode 100644 configs/radxa-e25-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dabbf116914c..f973f42169cc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
+ rk3568-radxa-e25.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi
b/arch/arm/dts/rk3568-radxa-cm3i.dtsi
new file mode 100644
index ..c50fbdd48680
--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ compatible = "radxa,cm3i", "rockchip,rk3568";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_user: led-0 {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = ;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
+ };
+
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc5v_input>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc5v_input
Re: [PATCH] board: rockchip: Add Radxa E25 Carrier Board
On 2023/7/24 06:25, Jonas Karlman wrote:
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD and nano sim card slot.
Features tested on a Radxa E25 v1.4:
- SD-card boot
- eMMC boot
- USB host
- PCIe/Ethernet adapters is detected
Device tree is imported from linux v6.4.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
This patch depends on the series "board: rockchip: Add Pine64 Quartz64
and SOQuartz boards" [1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=365266
Boot log with ROCKCHIP_TPL=rk3568_ddr_1560MHz_v1.17.bin and
BL31=rk3568_bl31_v1.43.elf:
U-Boot SPL 2023.07 (Jul 23 2023 - 22:03:27 +)
Trying to boot from MMC2
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
## Checking hash(es) for Image atf-4 ... sha256+ OK
## Checking hash(es) for Image atf-5 ... sha256+ OK
## Checking hash(es) for Image atf-6 ... sha256+ OK
U-Boot 2023.07 (Jul 23 2023 - 22:03:27 +)
Model: Radxa E25 Carrier Board
DRAM: 2 GiB
PMIC: RK8090 (on=0x40, off=0x00)
Core: 316 devices, 27 uclasses, devicetree: separate
MMC: mmc@fe2b: 1, mmc@fe31: 0
Loading Environment from nowhere... OK
In:serial@fe66
Out: serial@fe66
Err: serial@fe66
Model: Radxa E25 Carrier Board
Net: eth0: eth_rtl8169, eth1: eth_rtl8169
Hit any key to stop autoboot: 0
=> pci
BusDevFun VendorId DeviceId Device Class Sub-Class
_
00.00.00 0x1d87 0x3566 Bridge device 0x04
01.00.00 0x10ec 0x8125 Network controller 0x00
02.00.00 0x1d87 0x3566 Bridge device 0x04
03.00.00 0x10ec 0x8125 Network controller 0x00
=>
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++
arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 56 +++
arch/arm/dts/rk3568-radxa-e25.dts | 228
board/rockchip/evb_rk3568/MAINTAINERS | 8 +
configs/radxa-e25-rk3568_defconfig| 94 +
doc/board/rockchip/rockchip.rst | 1 +
7 files changed, 803 insertions(+)
create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi
create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts
create mode 100644 configs/radxa-e25-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dabbf116914c..f973f42169cc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
+ rk3568-radxa-e25.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi
b/arch/arm/dts/rk3568-radxa-cm3i.dtsi
new file mode 100644
index ..c50fbdd48680
--- /dev/null
+++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ compatible = "radxa,cm3i", "rockchip,rk3568";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_user: led-0 {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = ;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
+ };
+
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <90>;
+ regulator-max-microvolt = <90>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regu
Re: [PATCH 5/5] board: rockchip: Add Pine64 SOQuartz on CM4-IO
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi
CM4 form factor. Therefore, it can slot into the official Raspberry Pi
CM4 IO carrier board. Add this configuration to U-Boot.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 +
arch/arm/dts/rk3566-soquartz-cm4.dts | 192 +++
board/pine64/quartz64_rk3566/MAINTAINERS | 3 +
configs/soquartz-cm4-rk3566_defconfig| 90 +
doc/board/rockchip/rockchip.rst | 1 +
6 files changed, 290 insertions(+)
create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts
create mode 100644 configs/soquartz-cm4-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7a41675ef89d..dabbf116914c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
rk3566-soquartz-blade.dtb \
+ rk3566-soquartz-cm4.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
new file mode 100644
index ..0e662eafa4c7
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-soquartz-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts
b/arch/arm/dts/rk3566-soquartz-cm4.dts
new file mode 100644
index ..cddf6cd2fecb
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-cm4.dts
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
+ compatible = "pine64,soquartz-cm4io", "pine64,soquartz",
"rockchip,rk3566";
+
+ /* labeled +12v in schematic */
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ /* labeled +5v in schematic */
+ vcc_5v: vcc-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_sd_pwr: vcc-sd-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sd_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+};
+
+/* phy for pcie */
+&combphy2 {
+ phy-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+ /*
+* the rtc interrupt is tied to PMIC_PWRON,
+* it will force reset the board if triggered.
+*/
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/*
+ * i2s1_8ch
Re: [PATCH 4/5] board: rockchip: Add Pine64 SOQuartz on Blade
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz
CM4-compatible compute module. It features PoE, an M.2 slot, an SD card
slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
.../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 +
arch/arm/dts/rk3566-soquartz-blade.dts| 194 ++
board/pine64/quartz64_rk3566/MAINTAINERS | 3 +
configs/soquartz-blade-rk3566_defconfig | 90
doc/board/rockchip/rockchip.rst | 1 +
6 files changed, 292 insertions(+)
create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts
create mode 100644 configs/soquartz-blade-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aca2ec44a888..7a41675ef89d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-quartz64-a.dtb \
rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
+ rk3566-soquartz-blade.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
new file mode 100644
index ..0e662eafa4c7
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-soquartz-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts
b/arch/arm/dts/rk3566-soquartz-blade.dts
new file mode 100644
index ..4e49bebf548b
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-blade.dts
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "PINE64 RK3566 SOQuartz on Blade carrier board";
+ compatible = "pine64,soquartz-blade", "pine64,soquartz",
"rockchip,rk3566";
+
+ /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
+ vcc3v0_sd: vcc3v0-sd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* labeled VCC_SSD in schematic */
+ vcc3v3_pcie_p: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie_p";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vbus>;
+ };
+
+ vcc5v_dcin: vcc5v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+};
+
+&combphy2 {
+ phy-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi
Re: [PATCH 3/5] board: rockchip: Add Pine64 SOQuartz on Model A
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz
CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI,
CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
.../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 +
arch/arm/dts/rk3566-soquartz-model-a.dts | 232 ++
arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 30 +
arch/arm/dts/rk3566-soquartz.dtsi | 688 ++
board/pine64/quartz64_rk3566/MAINTAINERS | 5 +
configs/soquartz-model-a-rk3566_defconfig | 90 +++
doc/board/rockchip/rockchip.rst | 1 +
8 files changed, 1050 insertions(+)
create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts
create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi
create mode 100644 configs/soquartz-model-a-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3cc921e5cc1e..aca2ec44a888 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-quartz64-a.dtb \
rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
+ rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
rk3568-rock-3a.dtb
diff --git a/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
new file mode 100644
index ..0e662eafa4c7
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-soquartz-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts
b/arch/arm/dts/rk3566-soquartz-model-a.dts
new file mode 100644
index ..2208dbfb7f0a
--- /dev/null
+++ b/arch/arm/dts/rk3566-soquartz-model-a.dts
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "PINE64 RK3566 SOQuartz on Model A carrier board";
+ compatible = "pine64,soquartz-model-a", "pine64,soquartz",
"rockchip,rk3566";
+
+ /* labeled DCIN_12V in schematic */
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ /*
+* Labelled VCC3V0_SD in schematic to not conflict with PMIC
+* regulator, it's 3.3v in actuality
+*/
+ vcc3v0_sd: vcc3v0-sd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc12v_pcie: vcc12v-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+/* phy for pcie */
+&combphy2 {
+ phy-supply = <
Re: [PATCH 2/5] board: rockchip: Add Pine64 Quartz64-B Board
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model B is a credit-card sized single-board
computer based on the Rockchip RK3566 SoC. The board features an M.2
PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a
40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi.
Features tested on a Quartz64-B 4GB v1.4 2022-06-06:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 47 ++
arch/arm/dts/rk3566-quartz64-b.dts | 739 +
board/pine64/quartz64_rk3566/MAINTAINERS | 3 +
configs/quartz64-b-rk3566_defconfig| 106 +++
doc/board/rockchip/rockchip.rst| 1 +
6 files changed, 897 insertions(+)
create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts
create mode 100644 configs/quartz64-b-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 45ef73fdf0ca..3cc921e5cc1e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -168,6 +168,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-quartz64-a.dtb \
+ rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
new file mode 100644
index ..bdbb921c66e2
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&pcie2x1 {
+ pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&uart2 {
+ bootph-all;
+ clock-frequency = <2400>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+};
+
+&vcc5v0_usb30_host {
+ /delete-property/ regulator-always-on;
+};
+
+&vcc5v0_usb_otg {
+ /delete-property/ regulator-always-on;
+};
diff --git a/arch/arm/dts/rk3566-quartz64-b.dts
b/arch/arm/dts/rk3566-quartz64-b.dts
new file mode 100644
index ..b276eb0810c7
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-b.dts
@@ -0,0 +1,739 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 Quartz64-B Board";
+ compatible = "pine64,quartz64-b", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple
Re: [PATCH 1/5] board: rockchip: Add Pine64 Quartz64-A Board
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the
Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0,
CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a
20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli
Signed-off-by: Nicolas Frattaroli
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi| 55 ++
arch/arm/dts/rk3566-quartz64-a.dts| 839 ++
arch/arm/mach-rockchip/rk3568/Kconfig | 6 +
board/pine64/quartz64_rk3566/Kconfig | 15 +
board/pine64/quartz64_rk3566/MAINTAINERS | 9 +
board/pine64/quartz64_rk3566/Makefile | 3 +
.../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 +
configs/quartz64-a-rk3566_defconfig | 110 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/quartz64_rk3566.h | 10 +
11 files changed, 1050 insertions(+)
create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts
create mode 100644 board/pine64/quartz64_rk3566/Kconfig
create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS
create mode 100644 board/pine64/quartz64_rk3566/Makefile
create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c
create mode 100644 configs/quartz64-a-rk3566_defconfig
create mode 100644 include/configs/quartz64_rk3566.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6764ded580ab..45ef73fdf0ca 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -167,6 +167,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
+ rk3566-quartz64-a.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
new file mode 100644
index ..700c2d3edfe6
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&pcie2x1 {
+ pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&uart2 {
+ bootph-all;
+ clock-frequency = <2400>;
+ status = "okay";
+};
+
+/*
+ * U-Boot does not support multiple regulators using the same gpio,
+ * use vcc5v0_usb20_host to fix use of USB 2.0 port
+ */
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb20_host>;
+};
+
+&vcc3v3_sd {
+ bootph-pre-ram;
+};
+
+&vcc_sd_h {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3566-quartz64-a.dts
b/arch/arm/dts/rk3566-quartz64-a.dts
new file mode 100644
index ..25a8c781f4e7
--- /dev/null
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -0,0 +1,839 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 Quartz64-A Board";
+ compatible = "pine64,quartz64-a", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ fan: gpio_fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <00
+ 4500 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fan_en_h>;
+ #cooling-cells = <2>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+
Re: [PATCH] rockchip: veyron: Enable Winbond SPI flash
On 2023/7/21 16:46, Alper Nebi Yasak wrote: Some veyron boards seem to have Winbond SPI flash chips instead of GigaDevice ones. At the very least, coreboot builds for veyron boards have them enabled [1]. Enable support for them here as well. [1] https://review.coreboot.org/c/coreboot/+/9719 Signed-off-by: Alper Nebi Yasak Reviewed-by: Kever Yang Thanks, - Kever --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index d4302353c5df..253ef99f9939 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -81,6 +81,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 1a54986d089e..3172f04a2648 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -84,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 73ab2f62af5e..25a56f45fe6c 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -83,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 06437aae18d6..ff2a12b25c34 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -82,6 +82,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y
Re: [PATCH v3 0/3] board: rockchip: Add Hardkernel ODROID-M1
Hi Jonas, Could you split this patchset into two patch set? I can take the patch 3, but the patch 1~2 is suppose to go to other maintainer's tree, unless those patches got ACK from maintainer. Thanks, - Kever On 2023/7/22 22:02, Jonas Karlman wrote: This series add support for Hardkernel ODROID-M1, a single board computer with a RK3568B2 SoC. First patch fixes a build issue in the dwc_ahci driver. Second patch fixes a build warning in the ini command. Third patch import the device tree from linux v6.4 and add a defconfig for Hardkernel ODROID-M1. Following was tested on a ODROID-M1 8GB v1.0 2022-06-13: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe/AHCI - SATA port - USB host Changes in v3: - Remove vcc5v0_usb_host regulator-always-on workaround - Remove CONFIG_ETH_DESIGNWARE=y and CONFIG_GMAC_ROCKCHIP=y Changes in v2: - Add new patch to fix build warning in the ini command - Enable CMD_MTD, CMD_INI and CMD_CRAMFS to closer match downstream legacy U-Boot - Do not override spi0 alias, use SF_DEFAULT_BUS=4 - Collect r-b and t-b tags With the new options added in v2 it is possible to load downstream petitboot from SD-card using following commands: load mmc 1:1 $fdt_addr_r rk3568-odroid-m1.dtb load mmc 1:1 $cramfsaddr ODROIDBIOS.BIN cramfsload $scriptaddr boot.scr source $scriptaddr This series have loose dependencies on the following series: - rockchip: Fix PCIe and NVMe support on RK3568 [1] - rockchip: rk3568: Use dwc3-generic driver [2] - rockchip: rk3568: Fix alloc space exhausted in SPL [3] - rockchip: rk3568: Device Tree updates [4] - rockchip: rk35xx: Fix SPI Flash alias [5] [1] https://patchwork.ozlabs.org/project/uboot/list/?series=365195 [2] https://patchwork.ozlabs.org/project/uboot/list/?series=364127 [3] https://patchwork.ozlabs.org/project/uboot/list/?series=361999 [4] https://patchwork.ozlabs.org/project/uboot/list/?series=362030 [5] https://patchwork.ozlabs.org/project/uboot/list/?series=363527 Jonas Karlman (3): ata: dwc_ahci: Fix support for other platforms cmd: ini: Fix build warning board: rockchip: Add Hardkernel ODROID-M1 arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 37 ++ arch/arm/dts/rk3568-odroid-m1.dts | 744 ++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/hardkernel/odroid_m1/Kconfig| 15 + board/hardkernel/odroid_m1/MAINTAINERS| 8 + board/hardkernel/odroid_m1/Makefile | 3 + board/hardkernel/odroid_m1/odroid_m1.c| 1 + cmd/ini.c | 2 +- configs/odroid-m1-rk3568_defconfig| 111 doc/board/rockchip/rockchip.rst | 1 + drivers/ata/dwc_ahci.c| 4 + include/configs/odroid_m1.h | 11 + 13 files changed, 943 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-odroid-m1.dts create mode 100644 board/hardkernel/odroid_m1/Kconfig create mode 100644 board/hardkernel/odroid_m1/MAINTAINERS create mode 100644 board/hardkernel/odroid_m1/Makefile create mode 100644 board/hardkernel/odroid_m1/odroid_m1.c create mode 100644 configs/odroid-m1-rk3568_defconfig create mode 100644 include/configs/odroid_m1.h
Re: [PATCH v3 3/3] board: rockchip: Add Hardkernel ODROID-M1
On 2023/7/22 22:02, Jonas Karlman wrote:
Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC,
a slightly modified version of the RK3568 SoC.
Features tested on a ODROID-M1 8GB v1.0 2022-06-13:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe/AHCI
- SATA port
- USB host
Device tree is imported from linux v6.4.
Signed-off-by: Jonas Karlman
Reviewed-by: Stefan Agner
Tested-by: Stefan Agner
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v3:
- Remove vcc5v0_usb_host regulator-always-on workaround
- Remove CONFIG_ETH_DESIGNWARE=y and CONFIG_GMAC_ROCKCHIP=y
v2:
- Enable CMD_MTD, CMD_INI and CMD_CRAMFS to closer
match downstream legacy U-Boot
- Do not override spi0 alias, use SF_DEFAULT_BUS=4
- Collect r-b and t-b tags
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 37 ++
arch/arm/dts/rk3568-odroid-m1.dts | 744 ++
arch/arm/mach-rockchip/rk3568/Kconfig | 6 +
board/hardkernel/odroid_m1/Kconfig| 15 +
board/hardkernel/odroid_m1/MAINTAINERS| 8 +
board/hardkernel/odroid_m1/Makefile | 3 +
board/hardkernel/odroid_m1/odroid_m1.c| 1 +
configs/odroid-m1-rk3568_defconfig| 111
doc/board/rockchip/rockchip.rst | 1 +
include/configs/odroid_m1.h | 11 +
11 files changed, 938 insertions(+)
create mode 100644 arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-odroid-m1.dts
create mode 100644 board/hardkernel/odroid_m1/Kconfig
create mode 100644 board/hardkernel/odroid_m1/MAINTAINERS
create mode 100644 board/hardkernel/odroid_m1/Makefile
create mode 100644 board/hardkernel/odroid_m1/odroid_m1.c
create mode 100644 configs/odroid-m1-rk3568_defconfig
create mode 100644 include/configs/odroid_m1.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b7780de776b6..6764ded580ab 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-odroid-m1.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
new file mode 100644
index ..0fc360b06df7
--- /dev/null
+++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&fspi_dual_io_pins {
+ bootph-all;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&uart2 {
+ bootph-all;
+ clock-frequency = <2400>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-odroid-m1.dts
b/arch/arm/dts/rk3568-odroid-m1.dts
new file mode 100644
index ..59ecf868dbd0
--- /dev/null
+++ b/arch/arm/dts/rk3568-odroid-m1.dts
@@ -0,0 +1,744 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Hardkernel Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include
+#include
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Hardkernel ODROID-M1";
+ compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ i2c0 = &i2c3;
+ i2c3 = &i2c0;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = &
Re: [PATCH v4 8/9] rockchip: rk3568-rock-3a: Enable PCIe and NVMe support
On 2023/7/22 21:30, Jonas Karlman wrote:
Add missing pinctrl and defconfig options to enable PCIe and NVMe
support on Radxa ROCK 3 Model A.
Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1.
The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is
restored to the perstn pin, a workaround to avoid having to define
a new rockchip,pins.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v4:
- No change
v3:
- Drop now unneeded sys freeze workaround
- Enable options for AHCI/SCSI
v2:
- Update commit message
- Disable pcie2x1 to work around a possible sys freeze issue
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 14 ++
configs/rock-3a-rk3568_defconfig| 9 +
2 files changed, 23 insertions(+)
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index bbf54f888fa0..9ee7b494ee25 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -36,8 +36,22 @@
bootph-all;
};
+&pcie2x1 {
+ pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
+};
+
+&pcie3x2 {
+ pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>;
+};
+
&pinctrl {
bootph-all;
+
+ pcie {
+ pcie3x2_reset_h: pcie3x2-reset-h {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pcfg_pull_none {
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 753d03914d90..8e3fe0a25e1d 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -22,7 +22,9 @@ CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
@@ -46,6 +48,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
@@ -56,6 +59,8 @@ CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -70,6 +75,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
@@ -78,6 +85,8 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
Re: [PATCH v4 5/9] pci: pcie_dw_rockchip: Disable unused BARs of the root complex
On 2023/7/22 21:30, Jonas Karlman wrote:
From: Jon Lin
The Root Complex BARs default to claim the full 1 GiB memory region on
RK3568, leaving no space for any attached device.
Fix this by disable the unused BAR 0 and BAR 1 of the RC.
Signed-off-by: Jon Lin
[jo...@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const]
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v4:
- New patch, based on vendor commit 1f4523203c2a ("driver: pci: rockchip:
Disable RC BAR0 and BAR1")
drivers/pci/pcie_dw_rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 82a8b9c96e2b..1a35fae5c3a8 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,6 +61,8 @@ struct rk_pcie {
#define PCIE_CLIENT_DBG_TRANSITION_DATA 0x
#define PCIE_CLIENT_DBF_EN0x0003
+#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x10
+
static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
{
if ((uintptr_t)addr & (size - 1)) {
@@ -158,6 +160,12 @@ static void rk_pcie_configure(struct rk_pcie *pci, u32
cap_speed)
{
dw_pcie_dbi_write_enable(&pci->dw, true);
+ /* Disable BAR 0 and BAR 1 */
+ writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
+ PCI_BASE_ADDRESS_0);
+ writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
+ PCI_BASE_ADDRESS_1);
+
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
TARGET_LINK_SPEED_MASK, cap_speed);
Re: rk3588 status
Hi Simon, These pending patches are on my todo list and suppose to be handled in this week. Will check the u-boot-rockchip.bin for rk3588. Thanks, - Kever On 2023/7/26 02:02, Simon Glass wrote: Hi, What is the mainline status of this board? I see a lot of pending patches, for example [1]. I would expect these to have been applied by now since we just hit RC1. I notice that building this board does not produce a u-boot-rockchip.bin as I would expect. Any thoughts? Regards, Simon [1] https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=rk3588&archive=&delegate=
Re: [PATCH 4/4] rockchip: rk3308: fix same-as-spl boot order
On 2023/7/15 18:19, Pegorer Massimo wrote:
Boot devices defined in rk3308.c and in rk3308.dtsi do not match, causing
'same-as-spl' feature not to work. Update DTS definitions, aligning to
Linux kernel DTS and to other Rockchip DTS files, i.e. from dwmmc to mmc.
Add rk3308-rock-pi-s.dtb in dtb-y targets for CONFIG_ROCKCHIP_RK3308.
Signed-off-by: Massimo Pegorer
It would be better to sync the dtsi from mainline kernel, this patch is
fine for it's the
same with the mainline kernel after change.
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile| 3 ++-
arch/arm/dts/rk3308.dtsi | 6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 17f506a8fa..14c957d237 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -119,7 +119,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
dtb-$(CONFIG_ROCKCHIP_RK3308) += \
rk3308-evb.dtb \
- rk3308-roc-cc.dtb
+ rk3308-roc-cc.dtb \
+ rk3308-rock-pi-s.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
index a5c0b72ae0..9a152a8a90 100644
--- a/arch/arm/dts/rk3308.dtsi
+++ b/arch/arm/dts/rk3308.dtsi
@@ -584,7 +584,7 @@
status = "disabled";
};
- sdmmc: dwmmc@ff48 {
+ sdmmc: mmc@ff48 {
compatible = "rockchip,rk3308-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xff48 0x0 0x4000>;
max-frequency = <15000>;
@@ -599,7 +599,7 @@
status = "disabled";
};
- emmc: dwmmc@ff49 {
+ emmc: mmc@ff49 {
compatible = "rockchip,rk3308-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xff49 0x0 0x4000>;
max-frequency = <15000>;
@@ -612,7 +612,7 @@
status = "disabled";
};
- sdio: dwmmc@ff4a {
+ sdio: mmc@ff4a {
compatible = "rockchip,rk3308-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xff4a 0x0 0x4000>;
max-frequency = <15000>;
Re: [PATCH 3/4] rockchip: rk3308: add support for sdmmc boot
On 2023/7/15 18:19, Pegorer Massimo wrote:
Some ROCK Pi S SKU/models are not equipped with SD-NAND (eMMC),
therefore SPL needs access to sdmmc: add it to rk3308-u-boot.dtsi
with bootph-all property.
Signed-off-by: Massimo Pegorer
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 2 +-
arch/arm/dts/rk3308-u-boot.dtsi | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index a27a3adc08..09694b41e5 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -6,7 +6,7 @@
/ {
chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc;
+ u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
};
};
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index c8451b2475..db2c20a705 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -26,6 +26,11 @@
bootph-all;
};
+&sdmmc {
+ bootph-all;
+ u-boot,spl-fifo-mode;
+};
+
&grf {
bootph-all;
};
Re: [PATCH 2/4] rockchip: rk3308: no DEBUG_UART_BOARD_INIT for ROCK Pi S
On 2023/7/15 18:19, Pegorer Massimo wrote: Call to board_debug_uart_init() is useless, as mainline U-Boot can not build TPL for rk3308, and proprietary ddr.bin to be used as TPL is responsible to init debug uart. Moreover current implementation of board_debug_uart_init() is not compatible with ROCK Pi S, as it sets pins for UART2 channel 1 breaking access to sdmmc due to pinmux conflict. Debug uart for ROCK Pi S is UART0. Thus, avoid ROCKCHIP_RK3308 to select DEBUG_UART_BOARD_INIT and allow to deselct it in rock-pi-s-rk3308_defconfig. The DEBUG_UART_BOARD_INIT is already implied by ARCH_ROCKCHIP, therefore other boards based on rk3308 chip are not affected by change. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/mach-rockchip/Kconfig | 1 - configs/rock-pi-s-rk3308_defconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9d6d20bf8e..3f8c6d3e3c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -152,7 +152,6 @@ config ROCKCHIP_RK3288 config ROCKCHIP_RK3308 bool "Support Rockchip RK3308" select ARM64 - select DEBUG_UART_BOARD_INIT select SUPPORT_SPL select SUPPORT_TPL select SPL diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index c6fae07913..d306b58b8e 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_STACK_R_ADDR=0xc0 CONFIG_SPL_STACK=0x40 CONFIG_DEBUG_UART_BASE=0xFF0A CONFIG_DEBUG_UART_CLOCK=2400 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y
Re: [PATCH 1/4] rockchip: rk3308: fix board_debug_uart_init
On 2023/7/15 18:19, Pegorer Massimo wrote:
Definition of function board_debug_uart_init() must be under
CONFIG_DEBUG_UART_BOARD_INIT and not under CONFIG_DEBUG_UART,
as it was: see debug_uart.h. In this way the debug uart can
be used but its board-specific initialization skipped by
configuration, if useless.
Signed-off-by: Massimo Pegorer
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3308/rk3308.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c
b/arch/arm/mach-rockchip/rk3308/rk3308.c
index dd9109b7c3..5763604dc3 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -174,7 +174,7 @@ int rk_board_init(void)
return 0;
}
-#if defined(CONFIG_DEBUG_UART)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
__weak void board_debug_uart_init(void)
{
static struct rk3308_grf * const grf = (void *)GRF_BASE;
Re: [PATCH v3 5/9] pci: pcie_dw_rockchip: Hide BARs of the root complex
Hi Jonas,
Pls check if below patch available for you:
https://patchwork.ozlabs.org/project/uboot/patch/20230719081749.976334-1-kever.y...@rock-chips.com/
Thanks,
- Kever
On 2023/7/18 15:55, Jonas Karlman wrote:
PCI Autoconfig read the Root Complex BARs and try to claim the entire
1 GiB memory region on RK3568, leaving no space for any attached device.
With a memory region less than 1 GiB this was not a real issue:
PCI Autoconfig: Bus Memory region: [0-3eef],
PCI Autoconfig: Bus I/O region: [3ef0-3eff],
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: BAR 0, Mem, size=0x4000, No room in resource, avail
start=1000 / size=3ef0, need=4000
PCI: Failed autoconfig bar 10
PCI Autoconfig: BAR 1, Mem, size=0x4000, No room in resource, avail
start=1000 / size=3ef0, need=4000
PCI: Failed autoconfig bar 14
PCI Autoconfig: ROM, size=0x1, address=0x1 bus_lower=0x2
PCI Autoconfig: BAR 0, Mem64, size=0x4000, address=0x10
bus_lower=0x104000
With a memory region of the entire 1 GiB this leads to:
PCI Autoconfig: Bus Memory region: [4000-7fff],
PCI Autoconfig: Bus I/O region: [f010-f01f],
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: BAR 0, Mem, size=0x4000, address=0x4000
bus_lower=0x8000
PCI Autoconfig: BAR 1, Mem, size=0x4000, No room in resource, avail
start=8000 / size=4000, need=4000
PCI: Failed autoconfig bar 14
PCI Autoconfig: ROM, size=0x1, No room in resource, avail start=8000
/ size=4000, need=1
PCI Autoconfig: BAR 0, Mem64, size=0x4000, No room in resource, avail
start=8000 / size=4000, need=4000
PCI: Failed autoconfig bar 10
After this change with a memory region of the entire 1 GiB:
PCI Autoconfig: Bus Memory region: [4000-7fff],
PCI Autoconfig: Bus I/O region: [f010-f01f],
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: ROM, size=0x1, address=0x4000 bus_lower=0x4001
PCI Autoconfig: BAR 0, Mem64, size=0x4000, address=0x4010
bus_lower=0x40104000
Return an invalid value during config read of Root Complex BARs during
autoconfig to work around such issue.
Signed-off-by: Jonas Karlman
---
v3:
- No change
v2:
- Update commit message
drivers/pci/pcie_dw_rockchip.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 82a8b9c96e2b..f56773c2e58c 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -146,6 +146,32 @@ static inline void rk_pcie_writel_apb(struct rk_pcie
*rk_pcie, u32 reg,
__rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
}
+/**
+ * The BARs of bridge should be hidden during enumeration to avoid
+ * allocation of the entire memory region by PCIe core on RK3568.
+ */
+static bool rk_pcie_hide_rc_bar(struct pcie_dw *pcie, pci_dev_t bdf,
+ uint offset)
+{
+ int bus = PCI_BUS(bdf) - pcie->first_busno;
+
+ return bus == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ offset >= PCI_BASE_ADDRESS_0 && offset <= PCI_BASE_ADDRESS_1;
+}
+
+static int rk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct pcie_dw *pcie = dev_get_priv(bus);
+ int ret = pcie_dw_read_config(bus, bdf, offset, valuep, size);
+
+ if (!ret && rk_pcie_hide_rc_bar(pcie, bdf, offset))
+ *valuep = pci_get_ff(size);
+
+ return ret;
+}
+
/**
* rk_pcie_configure() - Configure link capabilities and speed
*
@@ -476,7 +502,7 @@ rockchip_pcie_probe_err_init_port:
}
static const struct dm_pci_ops rockchip_pcie_ops = {
- .read_config= pcie_dw_read_config,
+ .read_config= rk_pcie_read_config,
.write_config = pcie_dw_write_config,
};
[PATCH] pci: pcie_dw_rockchip: Disable no used BAR0/BAR1
The BAR0/BAR1 is not used by RC, but it may affect the space allocate
during RC scan.
Signed-off-by: Jon Lin
Signed-off-by: Kever Yang
---
drivers/pci/pcie_dw_rockchip.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 6da618055cb..0091fb62bae 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -64,6 +64,8 @@ struct rk_pcie {
/* Parameters for the waiting for #perst signal */
#define MACRO_US 1000
+#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x10
+
static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
{
if ((uintptr_t)addr & (size - 1)) {
@@ -210,6 +212,17 @@ static inline void rk_pcie_enable_ltssm(struct rk_pcie
*rk_pcie)
rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
}
+static void rk_pcie_disable_bar01(struct rk_pcie *pci)
+{
+ dw_pcie_dbi_write_enable(&pci->dw, true);
+
+ /* Disable BAR0 BAR1 */
+ writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);
+ writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);
+
+ dw_pcie_dbi_write_enable(&pci->dw, false);
+}
+
static int is_link_up(struct rk_pcie *priv)
{
u32 val;
@@ -331,6 +344,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
/* Set RC mode */
rk_pcie_writel_apb(priv, 0x0, 0xf00040);
pcie_dw_setup_host(&priv->dw);
+ rk_pcie_disable_bar01(priv);
ret = rk_pcie_link_up(priv, priv->gen);
if (ret < 0)
--
2.25.1
Re: [PATCH v2 5/5] optee: Support Rockchip OP-TEE binaries
Hi Alex, On 2023/7/18 22:57, Alex Bee wrote: Currently the only ARM Rockchip SoC which is supported by upstream optee-os is RK322x. For all other ARM SoCs a vendor-provided OP-TEE binary has to be used to have a TEE available. Those are using a calling convension different from upstream optee-os. This introduces CONFIG_ROCKCHIP_OPTEE_BINARY which signals that any of those vendor binaries is used and changes the calling convension accordingly. Signed-off-by: Alex Bee --- arch/arm/mach-rockchip/Kconfig | 8 common/spl/spl_optee.S | 4 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 17dd43155d..83d8a2a056 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -449,6 +449,14 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_OPTEE_BINARY + bool "Use a OP-TEE binary provided by Rockchip" + depends on SPL_OPTEE_IMAGE + default y if ROCKCHIP_RK3036 || ROCKCHIP_RK3128 || ROCKCHIP_RK3288 This patch is not need for now. the rk3036 works without OPTEE, and rk3288 is able to use ATF instead for OPTEE which upstreamed by Heiko. Thanks, - Kever + help + This option enables the usage of vendor-provided OP-TEE binaries. + Say Y if you are using OP-TEE binary provided by Rockchip. + config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S index a269904d38..ea41d8adb6 100644 --- a/common/spl/spl_optee.S +++ b/common/spl/spl_optee.S @@ -7,6 +7,10 @@ #include ENTRY(spl_optee_entry) +#ifdef CONFIG_ROCKCHIP_OPTEE_BINARY + ldr r1, =CONFIG_TEXT_BASE +#else ldr lr, =CONFIG_TEXT_BASE +#endif mov pc, r3 ENDPROC(spl_optee_entry)
Re: [PATCH v2 4/5] rockchip: evb_rk3229: Update/fix README
On 2023/7/18 22:57, Alex Bee wrote: This updates the evb_rk3229's README on howto create / use the FIT image created by binman. Also fix some wrong paths and update filenames which have changed in recent upstream optee-os versions. Signed-off-by: Alex Bee Reviewed-by: Kever Yang Thanks, - Kever --- board/rockchip/evb_rk3229/README | 72 +--- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README index 9068225e27..a8dcc40f09 100644 --- a/board/rockchip/evb_rk3229/README +++ b/board/rockchip/evb_rk3229/README @@ -13,25 +13,23 @@ Compile the OP-TEE > cd optee_os > make clean - > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x - Get tee.bin in this step, copy it to U-Boot root dir: - > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin + > make CROSS_COMPILE=arm-none-eabi- PLATFORM=rockchip-rk322x + Get tee-raw.bin in this step, copy it to U-Boot root dir: + > cp out/arm-plat-rockchip/core/tee-raw.bin ../u-boot/tee.bin Compile the U-Boot == > cd ../u-boot - > export CROSS_COMPILE=arm-linux-gnueabihf- > make evb-rk3229_defconfig - > make - > make u-boot.itb + > TEE=tee.bin CROSS_COMPILE=arm-linux-gnueabihf- make - Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. + Get u-boot-rockchip.bin in this step. Compile the rkdeveloptool === Follow instructions in latest README - > cd ../rkflashtool + > cd ../rkdeveloptool > autoreconf -i > ./configure > make @@ -42,30 +40,56 @@ Compile the rkdeveloptool Both origin binaries and Tool are ready now, choose either option 1 or option 2 to deploy U-Boot. -Package the image -= - - > cd ../u-boot - > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img - > cat spl/u-boot-spl.bin >> idbloader.img - - Get idbloader.img in this step. - Flash the image to eMMC === Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: > cd .. - > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin - > rkdeveloptool wl 64 u-boot/idbloader.img - > rkdeveloptool wl 0x4000 u-boot/u-boot.itb - > rkdeveloptool rd + > rkdeveloptool/rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin + > rkdeveloptool/rkdeveloptool wl 64 u-boot/u-boot-rockchip.bin + > rkdeveloptool/rkdeveloptool rd Flash the image to SD card == - > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 - > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 + > dd if=u-boot/u-boot-rockchip.bin of=/dev/sdb seek=64 + +You should be able to get U-Boot log message with OP-TEE boot info: + +U-Boot TPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51) +Trying to boot from BOOTROM +Returning to boot ROM... + +U-Boot SPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200) +Trying to boot from MMC1 +I/TC: +I/TC: Non-secure external DT found +I/TC: Switching console to device: /serial@1103 +I/TC: OP-TEE version: 3.22.0-27-g893a762d1 (gcc version 10.3.1 20210621 (release) (15:10.3-2021.07-4)) #1 Sat Jul 15 12:14:36 UTC 2023 arm +I/TC: WARNING: This OP-TEE configuration might be insecure! +I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html +I/TC: Primary CPU initializing +M/TC: Not protecting region 1: 0x6840-0x6860 +I/TC: Primary CPU switching to normal world boot + + +U-Boot 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200) + +Model: Rockchip RK3229 Evaluation board +DRAM: 1 GiB (effective 992 MiB) +Core: 113 devices, 16 uclasses, devicetree: separate +MMC: mmc@3000: 1, mmc@3002: 0 +Loading Environment from MMC... Card did not respond to voltage select! : -110 +*** Warning - No block device, using default environment + +In:serial@1103 +Out: serial@1103 +Err: serial@1103 +Model: Rockchip RK3229 Evaluation board +Net: +Warning: ethernet@3020 (eth0) using random MAC address - 72:65:2b:f1:c5:0a +eth0: ethernet@3020 +Hit any key to stop autoboot: 0 +=> -You should be able to get U-Boot log message with OP-TEE boot info. For more detail, please reference to: http://opensource.rock-chips.com/wiki_Boot_option
Re: [PATCH v2 3/5] rockchip: RK322x: Select SPL_OPTEE_IMAGE
On 2023/7/18 22:57, Alex Bee wrote: For RK322x series ARM SoCs the OP-TEE is non-optional, as besides the TEE it also provides the PSCI implementation, which is expected to be available by upstream linux. Select CONFIG_SPL_OPTEE_IMAGE if an FIT image is built. Signed-off-by: Alex Bee Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9d6d20bf8e..17dd43155d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -106,6 +106,7 @@ config ROCKCHIP_RK322X imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD select TPL_LIBCOMMON_SUPPORT
Re: [PATCH v2 2/5] configs: evb-rk3229: Increase SPL_STACK_R_MALLOC_SIMPLE_LEN
On 2023/7/18 22:57, Alex Bee wrote: An OP-TEE FIT image will fail to extract in SPL because the malloc stack size is currently limited to 0x2000 for evb-rk3229 board. In SPL we do not have to care about size limitations, since we are no longer bound to SRAM limits after DRAM initialization has been done in TPL. Use the default value for CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN in order successfully unpack the FIT image. Signed-off-by: Alex Bee Reviewed-by: Kever Yang Thanks, - Kever --- configs/evb-rk3229_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index cf73afeded..73015f098c 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10 CONFIG_SPL_OPTEE_IMAGE=y CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_GPT=y
Re: [PATCH v2 1/5] rockchip: Support OP-TEE for ARM in FIT images created by binman
On 2023/7/18 22:57, Alex Bee wrote:
CONFIG_SPL_OPTEE_IMAGE option is used during DRAM size detection for
Rockchip ARM platform to indicate that an OP-TEE binary was already loaded
and a Trusted Execution Environment (TEE) is available in order to
block/reserve a memory-region for it.
This adds a bunch of new `#if's` to u-boot-rockchip.dtsi to include the
OP-TEE binary in the FIT image for ARM SOCs if CONFIG_SPL_OPTEE_IMAGE is
selected.
That makes it a little harder to read, but I opted for that, because all
the duplicates in an extra ARM-OP-TEE-specfic .dtsi would be the greater
evil, IMHO. Besides it's more likley being "forgotten" to sync when changes
in u-boot-rockchip.dtsi are made.
The no longer required rockchip-optee.dtsi and it's inclusions are dropped.
The hardcoded load address is common across all OP-TEE implemenations for
Rockchip (vendor and upstream).
The OP-TEE-binary is non-optional if CONFIG_SPL_OPTEE_IMAGE is selected and
there will be an error if the file does not exist and/or `TEE=` build
option is missing.
Signed-off-by: Alex Bee
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288-u-boot.dtsi | 1 -
arch/arm/dts/rockchip-optee.dtsi | 64 ---
arch/arm/dts/rockchip-u-boot.dtsi | 38 --
3 files changed, 35 insertions(+), 68 deletions(-)
delete mode 100644 arch/arm/dts/rockchip-optee.dtsi
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index 1920698884..c4c5a2d225 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -4,7 +4,6 @@
*/
#include "rockchip-u-boot.dtsi"
-#include "rockchip-optee.dtsi"
/ {
aliases {
diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi
deleted file mode 100644
index d84c10cf43..00
--- a/arch/arm/dts/rockchip-optee.dtsi
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2020 Google LLC
- */
-
-#include
-
-#if defined(CONFIG_HAS_ROM) && defined(CONFIG_FIT)
-&binman {
- itb {
- filename = "u-boot.itb";
- fit {
- fit,external-offset = ;
- description = "FIT image with OP-TEE support";
- #address-cells = <1>;
-
- images {
- uboot {
- description = "U-Boot";
- type = "standalone";
- os = "U-Boot";
- arch = "arm";
- compression = "none";
- load = ;
-
- u-boot-nodtb {
- };
- };
- optee {
- description = "OP-TEE";
- type = "firmware";
- arch = "arm";
- os = "tee";
- compression = "none";
- load = <(CFG_SYS_SDRAM_BASE +
0x840)>;
- entry = <(CFG_SYS_SDRAM_BASE +
0x840)>;
-
- blob-ext {
- filename = "tee.bin";
- };
- };
- fdt {
- description = CONFIG_SYS_BOARD;
- type = "flat_dt";
- compression = "none";
-
- u-boot-dtb {
- };
- };
- };
-
- configurations {
- default = "conf";
- conf {
- description = CONFIG_SYS_BOARD;
- firmware = "optee";
- loadables = "uboot";
- fdt = "fdt";
- };
- };
- };
- };
-};
-#endif
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 2878b80926..be2658e8ef 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -33,9 +33,13 @@
};
};
-#if defined(CO
Pull request: u-boot-rockchip-20230629
Hi Tom, Please pull the fixex for rockchip platform: - rockchip inno phy fix; - pinctrl driver in SPL arort in specific case; - fix IO port voltage for rock5b-rk3588 board; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/16732 Thanks, - Kever The following changes since commit 580eb31199be8a822e62f20965854a242f895d03: Merge branch 'riscv-fixes' of https://source.denx.de/u-boot/custodians/u-boot-riscv (2023-06-27 09:39:58 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20230629 for you to fetch changes up to d77d5301d7dc333db0425ee82499fe362abd259d: board: rockchip: rock5b-rk3588: fix description (2023-06-29 18:43:42 +0800) Eugen Hristev (2): phy: rockchip: inno-usb2: fix phy reg=0 case board: rockchip: rock5b-rk3588: fix description Jonas Karlman (1): pinctrl: rockchip: Fix Data Abort exception in SPL Ondrej Jirman (1): pinephone-pro: Fix I/O port voltage (GPIO3D4A is 1.8V) arch/arm/mach-rockchip/rk3588/Kconfig | 10 .../pinephone-pro-rk3399/pinephone-pro-rk3399.c| 6 +++-- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 28 +- 4 files changed, 16 insertions(+), 30 deletions(-)
Re: [PATCH v1] mtd: nand: raw: rockchip_nfc: copy hwecc PA data to oob_poi buffer
On 2023/6/22 21:59, Johan Jonker wrote:
Rockchip boot blocks are written per 4 x 512 byte sectors per page.
Each page must have a page address (PA) pointer in OOB to the next page.
Pages are written in a pattern depending on the NAND chip ID.
This logic used to build a page pattern table is not fully disclosed and
is not easy to fit in the MTD framework.
The formula in rk_nfc_write_page_hwecc() function is not correct.
Make hwecc and raw behavior identical.
Generate boot block page address and pattern for hwecc in user space
and copy PA data to/from the already reserved last 4 bytes before EEC
in the chip->oob_poi data layout.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/mtd/nand/raw/rockchip_nfc.c | 34 ++---
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c
b/drivers/mtd/nand/raw/rockchip_nfc.c
index 5fcf6a6b..274489ec 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -525,7 +525,7 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
int pages_per_blk = mtd->erasesize / mtd->writesize;
int ret = 0, i, boot_rom_mode = 0;
dma_addr_t dma_data, dma_oob;
- u32 reg;
+ u32 tmp;
u8 *oob;
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
@@ -552,6 +552,13 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
*
* 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
*
+* The code here just swaps the first 4 bytes with the last
+* 4 bytes without losing any data.
+*
+* The chip->oob_poi data layout:
+*
+*BBM OOB1 OOB2 OOB3 |..| PA0 PA1 PA2 PA3
+*
* Configure the ECC algorithm supported by the boot ROM.
*/
if (page < (pages_per_blk * rknand->boot_blks)) {
@@ -561,21 +568,17 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
}
for (i = 0; i < ecc->steps; i++) {
- if (!i) {
- reg = 0x;
- } else {
+ if (!i)
+ oob = chip->oob_poi + (ecc->steps - 1) *
NFC_SYS_DATA_SIZE;
+ else
oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
- reg = oob[0] | oob[1] << 8 | oob[2] << 16 |
- oob[3] << 24;
- }
- if (!i && boot_rom_mode)
- reg = (page & (pages_per_blk - 1)) * 4;
+ tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24;
if (nfc->cfg->type == NFC_V9)
- nfc->oob_buf[i] = reg;
+ nfc->oob_buf[i] = tmp;
else
- nfc->oob_buf[i * (oob_step / 4)] = reg;
+ nfc->oob_buf[i * (oob_step / 4)] = tmp;
}
dma_data = dma_map_single((void *)nfc->page_buf,
@@ -720,12 +723,17 @@ static int rk_nfc_read_page_hwecc(struct mtd_info *mtd,
goto timeout_err;
}
- for (i = 1; i < ecc->steps; i++) {
- oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
+ for (i = 0; i < ecc->steps; i++) {
+ if (!i)
+ oob = chip->oob_poi + (ecc->steps - 1) *
NFC_SYS_DATA_SIZE;
+ else
+ oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
+
if (nfc->cfg->type == NFC_V9)
tmp = nfc->oob_buf[i];
else
tmp = nfc->oob_buf[i * (oob_step / 4)];
+
*oob++ = (u8)tmp;
*oob++ = (u8)(tmp >> 8);
*oob++ = (u8)(tmp >> 16);
--
2.30.2
Re: [PATCH] rockchip: Restore support for boot scripts in legacy image format
Hi Jonas,
What is the legacy image format, does these boards really use than?
I think most of the board using linux distro image.
Thanks,
- Kever
On 2023/6/27 03:43, Jonas Karlman wrote:
Use of CONFIG_SPL_FIT_SIGNATURE=y cause CONFIG_LEGACY_IMAGE_FORMAT=n as
default, this prevent boot scripts in legacy image format from working
and was an unintended change in the listed fixes commits:
Wrong image format for "source" command
Add CONFIG_LEGACY_IMAGE_FORMAT=y to defconfig for affected boards to
restore support for boot scripts in legacy image format.
Fixes: 3bf8e4080763 ("board: rockchip: add Radxa ROCK5B Rk3588 board")
Fixes: cf777572ca31 ("rockchip: rockpro64: Use SDMA to boost eMMC performance")
Fixes: 6e2b8344d60c ("rockchip: rock-pi-4: Use SDMA to boost eMMC performance")
Fixes: 1bf49d5a4a7c ("rockchip: rk3566-radxa-cm3-io: Update defconfig")
Fixes: 703c170b40f2 ("rockchip: rk3568-evb: Update defconfig")
Fixes: 68000f750acd ("rockchip: rk3568-rock-3a: Update defconfig")
Fixes: 6fb02589a608 ("rockchip: rk3588-evb: Update defconfig")
Signed-off-by: Jonas Karlman
---
configs/evb-rk3568_defconfig | 1 +
configs/evb-rk3588_defconfig | 1 +
configs/radxa-cm3-io-rk3566_defconfig | 1 +
configs/rock-3a-rk3568_defconfig | 1 +
configs/rock-pi-4-rk3399_defconfig| 1 +
configs/rock5b-rk3588_defconfig | 1 +
configs/rockpro64-rk3399_defconfig| 1 +
7 files changed, 7 insertions(+)
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 07819d105441..5f3fab7304c2 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -22,6 +22,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index d5f1c4b9ebc7..f49c2ca686a8 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -23,6 +23,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/radxa-cm3-io-rk3566_defconfig
b/configs/radxa-cm3-io-rk3566_defconfig
index 56802d85cc25..488723dfaa30 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -22,6 +22,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 616499f2f82b..753d03914d90 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -27,6 +27,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/rock-pi-4-rk3399_defconfig
b/configs/rock-pi-4-rk3399_defconfig
index 4b984adc6ef8..466868d80b03 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -20,6 +20,7 @@ CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index c1155c20efa8..17205a56cd99 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -29,6 +29,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/rockpro64-rk3399_defconfig
b/configs/rockpro64-rk3399_defconfig
index f41c03067903..dc4392c7451c 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -23,6 +23,7 @@ CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_LTO=y
CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_USE_PREBOOT=y
Re: [PATCH] board: rockchip: rock5b-rk3588: fix description
On 2023/6/23 18:05, Eugen Hristev wrote:
Update description with correct specifications
Fixes: 3bf8e4080763 ("board: rockchip: add Radxa ROCK5B Rk3588 board")
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 3596b82f1f1c..b7d5f13bebbf 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -34,15 +34,15 @@ config TARGET_ROCK5B_RK3588
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
- MIPI CSI 2 multiple lanes connector
+ 2x MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
- 2x USB 2.0, 2x USB 3.0
- 2x HDMI output, 1x HDMI input
- Ethernet port
+ 2x USB 2.0 Type-A, 2x USB 3.0 Type-A, 1x USB 3.0 Type-C
+ 2x HDMI 2.1 output, 1x micro HDMI input
+ 2.5 Gbps Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
- Size: 85mm x 54mm
+ Size: 100mm x 72mm (Pico-ITX form factor)
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
Re: [PATCH] pinctrl: rockchip: Fix Data Abort exception in SPL
On 2023/6/8 18:59, Jonas Karlman wrote:
Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers
a Data Abort exception from unaligned memory access when the pinctrl
driver iterate node properties, e.g. for UART2 on RK3568.
setting mux of GPIO0-24 to 1
setting mux of GPIO0-24 to 1
"Synchronous Abort" handler, esr 0x9621
elr: e554 lr : e54c
x 0: 0a5c x 1: 0a5c
x 2: 0007 x 3: 0065
x 4: 0007 x 5: 00022d4e
x 6: 0a7c x 7: 000227a4
x 8: 00021cf0 x 9: 0a7c
x10: 00021cf0 x11: 00021cf0
x12: 003fda1c x13: 0007
x14: 003fd9ec x15: 0001c0ff
x16: 0700 x17: fdccd028
x18: 003fde20 x19: 0018
x20: 00020670 x21:
x22: 003fdb00 x23: 003fef90
x24: 00020688 x25:
x26: 0001 x27: 003ffc50
x28: x29: 003fda60
Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038)
Resetting CPU ...
Fix this by replacing the loop to access node properties with use of
ofnode_for_each_prop instead of the current ifdef.
Also continue to next prop instead of aborting at first sign of an
unknown property.
This fixes the Data Abort exception and also pinconf of e.g. pull and
drive in SPL, e.g. for UART2 on RK3568.
setting mux of GPIO0-24 to 1
setting mux of GPIO0-24 to 1
setting pull of GPIO0-24 to 5
setting mux of GPIO0-25 to 1
setting mux of GPIO0-25 to 1
setting pull of GPIO0-25 to 5
Fixes: e7ae4cf27a6d ("pinctrl: rockchip: Add common rockchip pinctrl driver")
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 28 ---
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index d9d61fdb726a..8ef089994f46 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include "pinctrl-rockchip.h"
@@ -433,13 +432,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
int prop_len, param;
const u32 *data;
ofnode node;
-#ifdef CONFIG_OF_LIVE
- const struct device_node *np;
- struct property *pp;
-#else
- int property_offset, pcfg_node;
- const void *blob = gd->fdt_blob;
-#endif
+ struct ofprop prop;
data = dev_read_prop(config, "rockchip,pins", &count);
if (count < 0) {
debug("%s: bad array size %d\n", __func__, count);
@@ -473,24 +466,15 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
node = ofnode_get_by_phandle(conf);
if (!ofnode_valid(node))
return -ENODEV;
-#ifdef CONFIG_OF_LIVE
- np = ofnode_to_np(node);
- for (pp = np->properties; pp; pp = pp->next) {
- prop_name = pp->name;
- prop_len = pp->length;
- value = pp->value;
-#else
- pcfg_node = ofnode_to_offset(node);
- fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
- value = fdt_getprop_by_offset(blob, property_offset,
- &prop_name, &prop_len);
+ ofnode_for_each_prop(prop, node) {
+ value = ofprop_get_property(&prop, &prop_name,
&prop_len);
if (!value)
- return -ENOENT;
-#endif
+ continue;
+
param = rockchip_pinconf_prop_name_to_param(prop_name,
&default_val);
if (param < 0)
- break;
+ continue;
if (prop_len >= sizeof(fdt32_t))
arg = fdt32_to_cpu(*(fdt32_t *)value);
Re: [PATCH] phy: rockchip: inno-usb2: fix phy reg=0 case
On 2023/5/22 16:39, Eugen Hristev wrote:
The support for #address-cells=2 has a loophole: if the reg is actually 0,
but the #address-cells is actually 1, like in such case below:
syscon {
#address-cells = <1>;
phy {
reg = <0 0x10>;
};
};
then the second u32 of the 'reg' is the size, not the address.
The code should check for the parent's #address-cells value, and not
assume that if the first u32 is 0, then the #address-cells is 2, and the
reg property is something like
reg = <0 0xff00 0x10>;
Fixed this by looking for the #address-cells value and retrieving the
reg address only if this is ==2.
To avoid breaking anything I also kept the check `if reg==0` as some DT's
may have a wrong #address-cells as parent and even if this commit is
correct, it might break the existing wrong device-trees.
Fixes: d538efb9adcf ("phy: rockchip: inno-usb2: Add support #address_cells = 2")
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 22e2797eea28..e5e02b6765b1 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -186,7 +186,7 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
}
/* support address_cells=2 */
- if (reg == 0) {
+ if (dev_read_addr_cells(dev) == 2 && reg == 0) {
if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, ®)) {
dev_err(dev, "%s must have reg[1]\n",
ofnode_get_name(dev_ofnode(dev)));
Re: [PATCH v2 5/9] pci: pcie_dw_rockchip: Hide BARs of the root complex
Hi Jonas,
Sorry for reply late for this patch.
I have check internally again for this BAR issue, the BAR alloce
fail for RC would not affect other process, and it always works on
vendor U-Boot tree.
And if we have to handle this, we can disable the BAR instead of
this workaround.
Thanks,
- Kever
On 2023/5/18 06:53, Jonas Karlman wrote:
PCI Autoconfig read the Root Complex BARs and try to claim the entire
1 GiB memory region on RK3568, leaving no space for any attached device.
With a memory region less than 1 GiB this was not a real issue:
PCI Autoconfig: Bus Memory region: [0-3eef],
PCI Autoconfig: Bus I/O region: [3ef0-3eff],
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: BAR 0, Mem, size=0x4000, No room in resource, avail
start=1000 / size=3ef0, need=4000
PCI: Failed autoconfig bar 10
PCI Autoconfig: BAR 1, Mem, size=0x4000, No room in resource, avail
start=1000 / size=3ef0, need=4000
PCI: Failed autoconfig bar 14
PCI Autoconfig: ROM, size=0x1, address=0x1 bus_lower=0x2
PCI Autoconfig: BAR 0, Mem64, size=0x4000, address=0x10
bus_lower=0x104000
With a memory region of the entire 1 GiB this leads to:
PCI Autoconfig: Bus Memory region: [4000-7fff],
PCI Autoconfig: Bus I/O region: [f010-f01f],
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: BAR 0, Mem, size=0x4000, address=0x4000
bus_lower=0x8000
PCI Autoconfig: BAR 1, Mem, size=0x4000, No room in resource, avail
start=8000 / size=4000, need=4000
PCI: Failed autoconfig bar 14
PCI Autoconfig: ROM, size=0x1, No room in resource, avail start=8000
/ size=4000, need=1
PCI Autoconfig: BAR 0, Mem64, size=0x4000, No room in resource, avail
start=8000 / size=4000, need=4000
PCI: Failed autoconfig bar 10
After this change with a memory region of the entire 1 GiB:
PCI Autoconfig: Bus Memory region: [4000-7fff],
PCI Autoconfig: Bus I/O region: [f010-f01f],
PCI Autoconfig: Found P2P bridge, device 0
PCI Autoconfig: ROM, size=0x1, address=0x4000 bus_lower=0x4001
PCI Autoconfig: BAR 0, Mem64, size=0x4000, address=0x4010
bus_lower=0x40104000
Return an invalid value during config read of Root Complex BARs during
autoconfig to work around such issue.
Signed-off-by: Jonas Karlman
---
v2:
- Update commit message
drivers/pci/pcie_dw_rockchip.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 82a8b9c96e2b..f56773c2e58c 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -146,6 +146,32 @@ static inline void rk_pcie_writel_apb(struct rk_pcie
*rk_pcie, u32 reg,
__rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
}
+/**
+ * The BARs of bridge should be hidden during enumeration to avoid
+ * allocation of the entire memory region by PCIe core on RK3568.
+ */
+static bool rk_pcie_hide_rc_bar(struct pcie_dw *pcie, pci_dev_t bdf,
+ uint offset)
+{
+ int bus = PCI_BUS(bdf) - pcie->first_busno;
+
+ return bus == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ offset >= PCI_BASE_ADDRESS_0 && offset <= PCI_BASE_ADDRESS_1;
+}
+
+static int rk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct pcie_dw *pcie = dev_get_priv(bus);
+ int ret = pcie_dw_read_config(bus, bdf, offset, valuep, size);
+
+ if (!ret && rk_pcie_hide_rc_bar(pcie, bdf, offset))
+ *valuep = pci_get_ff(size);
+
+ return ret;
+}
+
/**
* rk_pcie_configure() - Configure link capabilities and speed
*
@@ -476,7 +502,7 @@ rockchip_pcie_probe_err_init_port:
}
static const struct dm_pci_ops rockchip_pcie_ops = {
- .read_config= pcie_dw_read_config,
+ .read_config= rk_pcie_read_config,
.write_config = pcie_dw_write_config,
};
Re: [PATCH] rockchip: allow env defines for SPL build
Hi Eugen,
On 2023/6/16 16:55, Eugen Hristev wrote:
For environment in SPL, all these defines are required, otherwise
build fails:
[...]
include/env_default.h:120:9: note: in expansion of macro
‘CFG_EXTRA_ENV_SETTINGS’
120 | CFG_EXTRA_ENV_SETTINGS
| ^~
In file included from env/common.c:32:
[...]
Environment in SPL is needed e.g. for DFU, as dfu_alt is kept as
env variable.
Signed-off-by: Eugen Hristev
---
include/configs/rockchip-common.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/configs/rockchip-common.h
b/include/configs/rockchip-common.h
index 9121bba37384..be20b135066e 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -11,8 +11,6 @@
#define CFG_CPUID_OFFSET 0x7
#endif
-#ifndef CONFIG_SPL_BUILD
-
#define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi"
These boot targets are for U-Boot proper only, not available for SPL, so
I don't think remove
the SPL_BUILD limit is correct.
The DFU you mentioned is also used in U-Boot instead of SPL for most of
the project.
Thanks,
- Kever
#ifdef CONFIG_ARM64
@@ -28,6 +26,4 @@
"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
"name=rootfs,size=-,uuid="ROOT_UUID
-#endif
-
#endif /* _ROCKCHIP_COMMON_H_ */
Re: [PATCH v7 2/2] phy: rockchip-inno-usb2: Implement clock operations for usb2phy clock
On 2023/6/5 23:06, Xavier Drudis Ferran wrote:
This clock doesn't seem needed but appears in a phandle list used by
ehci-generic.c to bulk enable it. The phandle list comes from linux,
where it is needed for suspend/resume to work [1].
My tests give the same results with or without this patch, but Marek
Vasut found it weird to declare an empty clk_ops [2].
So I adapted the code from linux 6.1-rc8 so that it hopefully works
if it ever has some user. For now, without real use, it seems to
at least not give any errors when called.
Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
[2]
https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Cc: Christoph Fritz
Cc: Jagan Teki
Signed-off-by: Xavier Drudis Ferran
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v7: add clkout_ctl values for rk3568 (from linux).
UNTESTED (I don't have the hardware).
v6: just retested over current next branch and some corrections
to message and headers
(no changes to code).
v5: ignores the return value from property_enable() which is not
an error code in U-Boot (unlike in linux). This avoid a false
failure of rockchip_usb2phy_clk_disable() that interfered with
clock disable and appeared to cause hang or reset.
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 80 ++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 732d37201d..be5f79490c 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -56,6 +56,7 @@ struct rockchip_usb2phy_port_cfg {
struct rockchip_usb2phy_cfg {
unsigned int reg;
+ struct usb2phy_reg clkout_ctl;
const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
};
@@ -77,6 +78,18 @@ static inline int property_enable(void *reg_base,
return writel(val, reg_base + reg->offset);
}
+static inline bool property_enabled(void *reg_base,
+ const struct usb2phy_reg *reg)
+{
+ unsigned int tmp, orig;
+ unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
+
+ orig = readl(reg_base + reg->offset);
+
+ tmp = (orig & mask) >> reg->bitstart;
+ return tmp != reg->disable;
+}
+
static const
struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
{
@@ -169,7 +182,63 @@ static struct phy_ops rockchip_usb2phy_ops = {
.of_xlate = rockchip_usb2phy_of_xlate,
};
+/**
+ * round_rate() - Adjust a rate to the exact rate a clock can provide.
+ * @clk: The clock to manipulate.
+ * @rate: Desidered clock rate in Hz.
+ *
+ * Return: rounded rate in Hz, or -ve error code.
+ */
+ulong rockchip_usb2phy_clk_round_rate(struct clk *clk, ulong rate)
+{
+ return 48000;
+}
+
+/**
+ * enable() - Enable a clock.
+ * @clk: The clock to manipulate.
+ *
+ * Return: zero on success, or -ve error code.
+ */
+int rockchip_usb2phy_clk_enable(struct clk *clk)
+{
+ struct udevice *parent = dev_get_parent(clk->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+ /* turn on 480m clk output if it is off */
+ if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) {
+ property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true);
+
+ /* waiting for the clk become stable */
+ usleep_range(1200, 1300);
+ }
+
+ return 0;
+}
+
+/**
+ * disable() - Disable a clock.
+ * @clk: The clock to manipulate.
+ *
+ * Return: zero on success, or -ve error code.
+ */
+int rockchip_usb2phy_clk_disable(struct clk *clk)
+{
+ struct udevice *parent = dev_get_parent(clk->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+ /* turn off 480m clk output */
+ property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false);
+
+ return 0;
+}
+
static struct clk_ops rockchip_usb2phy_clk_ops = {
+ .enable = rockchip_usb2phy_clk_enable,
+ .disable = rockchip_usb2phy_clk_disable,
+ .round_rate = rockchip_usb2phy_clk_round_rate
};
static int rockchip_usb2phy_probe(struct udevice *dev)
@@ -255,8 +324,11 @@ static int rockchip_usb2phy_bind(struct udevice *dev)
}
node = dev_ofnode(dev);
- name = ofnode_get_name(node);
- dev_dbg(dev, "clk for node %s\n", name);
+ name = "clk_usbphy_480m";
+ dev_read_string_index(dev, "clock-output-names", 0, &name);
+
+
Re: [PATCH v7 1/2] phy: rockchip-inno-usb2: Add usb2phy clock provider of 480MHz clock
On 2023/6/5 23:05, Xavier Drudis Ferran wrote:
arch/arm/dts/rk3399.dtsi has a node
usb_host0_ehci: usb@fe38 {
compatible = "generic-ehci";
with clocks:
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
<&u2phy0>;
The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0
has class UCLASS_PHY.
u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
Since clk_get_bulk() only looks for devices with UCLASS_CLK,
it fails with -ENODEV and then ehci_usb_probe() aborts.
The consequence is peripherals connected to a USB 2 port (e.g. in a
Rock Pi 4 the white port, nearer the edge) not being detected.
They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig,
because ohci_usb_probe() does not abort when one clk_get_by_index()
fails, but then they work in USB 1 mode.
rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock
list in:
commit b5d1c57299734f5b54035ef2e61706b83041f20c
Author: William wu
Date: Wed Dec 21 18:41:05 2016 +0800
arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
[...]
Suspend concerns don't apply to U-Boot, and the problem with U-Boot
failing to probe EHCI doesn't apply to linux, because in linux
rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider
when called by rockchip_usb2phy_probe().
So I can think of a few alternative solutions:
1- Change ehci_usb_probe() to make it more similar to
ohci_usb_probe(), and survive failure to get one clock. Looks a
little harder, and I don't know whether it could break something if
it ignored a clock that was important for something else than
suspend.
2- Change rk3399.dtsi effectively reverting the linux commit
b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi
from linux and seems fragile at the next synchronisation.
3- Change the clock list in rk3399-u-boot.dtsi or somewhere else.
This survives .dts* sync but may survive "too much" and miss some
change from linux that we might want.
4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode.
This would need to be made for all boards using rk3399. In a
simple test reading one file from USB storage it gave 769.5 KiB/s
instead of 20.5 MiB/s with solution 2.
5- Trying to replicate linux and have usb2phy somehow provide a clk,
or have a separate clock device for usb2phy in addition to the phy
device.
This patch tries to implement option 5 as Marek Vasut requested in
December 5th. Options 1 and 3 didn't get through [2][3].
It just registers usb2phy as a clock driver (device_bind_driver()
didn't work but device_bind_driver_to_node() did), without any
specific operations, so that ehci-generic.c finds it and is happy. It
worked in my tests on a Rock Pi 4 B+ (rk3399).
Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
[2]
https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/
[3]
https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Cc: Christoph Fritz
Cc: Jagan Teki
Signed-off-by: Xavier Drudis Ferran
Reviewed-by: Kever Yang
Thanks,
- Kever
---
V7: improve error handling. Call device_chld_unbind() on error.
Remove unnecessary if.
v6: just retested over current next branch and some corrections
to message and headers
(no changes to code).
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 33 +--
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 55e1dbcfef..732d37201d 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -7,10 +7,11 @@
*/
#include
-#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -168,6 +169,9 @@ static struct phy_ops rockchip_usb2phy_ops = {
.of_xlate = rockchip_usb2phy_of_xlate,
};
+static struct clk_ops rockchip_usb2phy_clk_ops = {
+};
+
static int rockchip_usb2phy_probe(struct udevice *dev)
{
struct rockchip_usb2phy *priv = dev_get_priv(dev);
@@ -234,7 +238,8 @@ static int rockchip_usb2phy_bind(struct udevice *dev)
dev_for_each_subnode(node, dev) {
if (!ofnode_valid(node)) {
dev_info(dev, "subnode %s not found\n", dev->name);
- return -ENXIO;
+ ret = -ENXIO;
+ goto bind_fail;
}
Re: [PATCH] i2c: rockchip: De-initialize the bus after start bit failure
On 2023/5/25 20:18, Ondřej Jirman wrote:
From: Ondrej Jirman
Failure can happen when i2c is used without initializing pinctrl properly,
which U-Boot happily allows in SPL. Without this fix, further I2C access would
fail, even after proper pinctrl initialization.
Signed-off-by: Ondrej Jirman
Cc: Heiko Schocher
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/i2c/rk_i2c.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index f8fac45b6ca0..9927af94a80b 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -342,7 +342,7 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct
i2c_msg *msg,
int nmsgs)
{
struct rk_i2c *i2c = dev_get_priv(bus);
- int ret;
+ int ret = 0;
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
@@ -356,14 +356,15 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct
i2c_msg *msg,
}
if (ret) {
debug("i2c_write: error sending\n");
- return -EREMOTEIO;
+ ret = -EREMOTEIO;
+ break;
}
}
rk_i2c_send_stop_bit(i2c);
rk_i2c_disable(i2c);
- return 0;
+ return ret;
}
int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
Re: [PATCH] video: rockchip: Add support for RK3399 to dw-mipi-dsi bridge
On 2023/5/25 20:29, Ondřej Jirman wrote:
From: Ondrej Jirman
This just needs some extra clocks enabled, and different registers
configured. Copied from Linux, just like the original submitter
of this driver did for rk3568.
Tested on Pinephone Pro.
Signed-off-by: Ondrej Jirman
Cc: Anatolij Gustschin
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 99 +++
1 file changed, 99 insertions(+)
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 1bb1c7c67d07..9ec3a48bf2a5 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -134,6 +134,32 @@
#define HS_RX_CONTROL_OF_LANE_2 0x84
#define HS_RX_CONTROL_OF_LANE_3 0x94
+#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
+#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
+
+#define RK3399_GRF_SOC_CON20 0x6250
+#define RK3399_DSI0_LCDC_SEL BIT(0)
+#define RK3399_DSI1_LCDC_SEL BIT(4)
+
+#define RK3399_GRF_SOC_CON22 0x6258
+#define RK3399_DSI0_TURNREQUEST(0xf << 12)
+#define RK3399_DSI0_TURNDISABLE(0xf << 8)
+#define RK3399_DSI0_FORCETXSTOPMODE(0xf << 4)
+#define RK3399_DSI0_FORCERXMODE(0xf << 0)
+
+#define RK3399_GRF_SOC_CON23 0x625c
+#define RK3399_DSI1_TURNDISABLE(0xf << 12)
+#define RK3399_DSI1_FORCETXSTOPMODE(0xf << 8)
+#define RK3399_DSI1_FORCERXMODE(0xf << 4)
+#define RK3399_DSI1_ENABLE (0xf << 0)
+
+#define RK3399_GRF_SOC_CON24 0x6260
+#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
+#define RK3399_TXRX_ENABLECLK BIT(6)
+#define RK3399_TXRX_BASEDIRBIT(5)
+#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
+#define RK3399_TXRX_TURNREQUESTGENMASK(3, 0)
+
#define RK3568_GRF_VO_CON20x0368
#define RK3568_DSI0_SKEWCALHS (0x1f << 11)
#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4)
@@ -209,6 +235,8 @@ struct dw_rockchip_dsi_priv {
struct clk *pclk;
struct clk *ref;
+ struct clk *grf_clk;
+ struct clk *phy_cfg_clk;
struct reset_ctl *rst;
unsigned int lane_mbps; /* per lane */
u16 input_div;
@@ -844,6 +872,28 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
}
}
+ if (cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
+ priv->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+ if (IS_ERR(priv->phy_cfg_clk)) {
+ ret = PTR_ERR(priv->phy_cfg_clk);
+ dev_err(dev, "phy_cfg_clk clock get error %d\n", ret);
+ return ret;
+ }
+
+ clk_enable(priv->phy_cfg_clk);
+ }
+
+ if (cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
+ priv->grf_clk = devm_clk_get(dev, "grf");
+ if (IS_ERR(priv->grf_clk)) {
+ ret = PTR_ERR(priv->grf_clk);
+ dev_err(dev, "grf_clk clock get error %d\n", ret);
+ return ret;
+ }
+
+ clk_enable(priv->grf_clk);
+ }
+
priv->rst = devm_reset_control_get_by_index(device->dev, 0);
if (IS_ERR(priv->rst)) {
ret = PTR_ERR(priv->rst);
@@ -864,6 +914,52 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = {
.set_backlight = dw_mipi_dsi_rockchip_set_bl,
};
+static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
+ {
+ .reg = 0xff96,
+ .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+ .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
+ .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
+ RK3399_DSI0_LCDC_SEL),
+
+ .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
+RK3399_DSI0_TURNDISABLE |
+RK3399_DSI0_FORCETXSTOPMODE |
+RK3399_DSI0_FORCERXMODE),
+
+ .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
+ .max_data_lanes = 4,
+ },
+ {
+ .reg = 0xff968000,
+ .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+ .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
+ .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
+ R
Re: [PATCH v2 2/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5C
On 2023/5/29 12:59, Tianling Shen wrote:
FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
Specification:
- Rockchip RK3568
- 1/4GB LPDDR4X RAM
- 8/32GB eMMC
- SD card slot
- M.2 Connector
- 2x USB 3.0 Port
- 2x 2500 Base-T (PCIe, r8125)
- HDMI 2.0
- MIPI DSI/CSI
- USB Type C 5V
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v2: add dtb to Makefile
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 +
arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +
board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
configs/nanopi-r5c-rk3568_defconfig| 90 +
5 files changed, 213 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts
create mode 100644 configs/nanopi-r5c-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e2eda3ffcb..507bfb512a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-rock-3a.dtb
diff --git a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
new file mode 100644
index 00..fe5bc6af47
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rk3568-nanopi-r5s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts
b/arch/arm/dts/rk3568-nanopi-r5c.dts
new file mode 100644
index 00..f70ca9f047
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5C";
+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_button_pin>;
+
+ button-reset {
+ debounce-interval = <50>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = ;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>,
<&wlan_led_pin>;
+
+ led-lan {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = ;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = ;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wlan {
+ color = ;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20_reset_pin>;
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-leds {
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ power_led_pin: power-led-pin {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+
Re: [PATCH v2 1/2] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
On 2023/5/29 12:59, Tianling Shen wrote:
FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
Board Specifications
- Rockchip RK3568
- 2 or 4GB LPDDR4X
- 8GB or 16GB eMMC, SD card slot
- GbE LAN (Native)
- 2x 2.5G LAN (PCIe)
- M.2 Connector
- HDMI 2.0, MIPI DSI/CSI
- 2xUSB 3.0 Host
- USB Type C PD, 5V/9V/12V
- GPIO: 12-pin 0.5mm FPC connector
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen
Reviewed-by: Kever Yang
Thanks,
- Kever
---
No changes in v2.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 33 ++
arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +
arch/arm/dts/rk3568-nanopi-r5s.dtsi| 590 +
board/rockchip/evb_rk3568/MAINTAINERS | 8 +
configs/nanopi-r5s-rk3568_defconfig| 90
6 files changed, 858 insertions(+)
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
create mode 100644 configs/nanopi-r5s-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..e2eda3ffcb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,6 +169,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+ rk3568-nanopi-r5s.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
new file mode 100644
index 00..b37ad1e72d
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ bootph-pre-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+ clock-frequency = <2400>;
+ bootph-pre-ram;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts
b/arch/arm/dts/rk3568-nanopi-r5s.dts
new file mode 100644
index 00..b6ad8328c7
--- /dev/null
+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5S";
+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>,
<&wan_led_pin>;
+
+ led-lan1 {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-lan2 {
+ color = ;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = ;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = ;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru
CLK_MAC0_2TOP>;
+ assigned-clock-rates = <0>, <12500>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+
Re: [PATCH] ARM: dts: rockchip: rk3588: sync with Linux
On 2023/5/29 15:34, Eugen Hristev wrote:
Sync the devicetree with linux-next tag: next-20230525
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588-rock-5b.dts | 152
arch/arm/dts/rk3588.dtsi | 68 +
arch/arm/dts/rk3588s-u-boot.dtsi | 12 --
arch/arm/dts/rk3588s.dtsi| 234 ++-
4 files changed, 449 insertions(+), 17 deletions(-)
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
index 95805cb0adfa..3e4aee8f70c1 100644
--- a/arch/arm/dts/rk3588-rock-5b.dts
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -2,6 +2,7 @@
/dts-v1/;
+#include
#include "rk3588.dtsi"
/ {
@@ -17,6 +18,31 @@
stdout-path = "serial2:150n8";
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm1 0 5 0>;
+ #cooling-cells = <2>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "Analog";
+
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+
+ dais = <&i2s0_8ch_p0>;
+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ };
+
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -27,6 +53,132 @@
};
};
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <55>;
+ regulator-max-microvolt = <105>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <55>;
+ regulator-max-microvolt = <105>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = ;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 =
Re: [PATCH] pinephone-pro: Fix I/O port voltage (GPIO3D4A is 1.8V)
Hi Ondrej, Thanks for your patch. On 2023/5/25 21:27, Ondřej Jirman wrote: From: Ondrej Jirman This fixes access to camera sensor over I2C during probe time in the kernel. (Kernel will fix I/0 port voltage by itself, but the timing depends on probe order of the drivers, so the fix can come after the camera sensor driver already failed to probe.) Signed-off-by: Ondrej Jirman Cc: Kever Yang Reviewed-by: Kever Yang Thanks, - Kever --- board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c index eb639cd0d070..b6ccbb9c1c4b 100644 --- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -15,7 +15,8 @@ #include #include -#define GRF_IO_VSEL_BT565_SHIFT 0 +#define GRF_IO_VSEL_BT565_GPIO2AB 1 +#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2 #define PMUGRF_CON0_VSEL_SHIFT 8 #ifndef CONFIG_SPL_BUILD @@ -48,7 +49,8 @@ static void setup_iodomain(void) syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); /* BT565 is in 1.8v domain */ - rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + rk_setreg(&grf->io_vsel, + GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A); /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
Re: [PATCH 1/8] video: rockchip: vop: Fix whitespace
Hi Ondrej,
Thanks for you patches.
On 2023/5/23 05:47, m...@xff.cz wrote:
From: Ondrej Jirman
Fix confusing use of indentation.
Signed-off-by: Ondrej Jirman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/video/rockchip/rk_vop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index dab9902fda73..c514e2a0e449 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -432,7 +432,7 @@ int rk_vop_probe(struct udevice *dev)
ret = reset_assert(&ahb_rst);
if (ret) {
dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
- return ret;
+ return ret;
}
udelay(20);
Pull request: u-boot-rockchip-20230519
Hi Tom, Please pull the updates for rockchip platform: rk3588 driver: - Sync the reset driver with kernel code; - Enable pcie controller and phy support; - Enable USB controller and phy support; Board level dts and config update: - boost eMMC performance for some of rk3399 boards; - boot from SPI NOR flash for rk356x boards; - Other board level updates; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/16404 Thanks, - Kever The following changes since commit 6e1852ca2c418e2536ead4b51c4d84a59926b3f1: Merge tag 'efi-2023-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-05-16 11:23:30 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20230519 for you to fetch changes up to fd6e425be243dce518a02710482514faccf3c211: rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash (2023-05-19 08:50:44 +0800) Christopher Obbard (1): ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy Eugen Hristev (10): ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host configs: rockchip: rock5b-rk3588: enable USB and regulators phy: add support for phy-supply phy: remove phy-supply related code phy: rockchip-inno-usb2: add initial support for rk3588 PHY ARM: dts: rk3588-rock-5b-u-boot: add bootph-all to pinctrl for sdmmc configs: rockchip: rock5b-rk3588: add pinctrl to SPL reset: rockchip: implement rk3588 lookup table phy: rockchip: naneng-combphy: Add support for multiple resets configs: rock5b-rk3588: add PCI drivers and command Jon Lin (3): pci: pcie_dw_rockchip: Add rk3588 compatible pci: pcie_dw_rockchip: Support max_link_speed dts property phy: rockchip: naneng-combphy: Support rk3588 Jonas Karlman (19): phy: Keep balance of counts when ops is missing mmc: rockchip_sdhci: Skip blocks read workaround on RK3399 mmc: rockchip_sdhci: Disable DMA mode using a device tree property rockchip: rockpro64: Use SDMA to boost eMMC performance rockchip: rock-pi-4: Use SDMA to boost eMMC performance rockchip: rockpro64: Build u-boot-rockchip-spi.bin spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop rockchip: rk356x-u-boot: Add xin24m clock node to SPL rockchip: rk3566-radxa-cm3-io: Update defconfig rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL rockchip: rk3568-evb: Update defconfig rockchip: rk3568-rock-3a: Update defconfig rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch Kconfig rockchip: rk3588-evb: Update defconfig rockchip: rk3588-rock-5b: Update defconfig rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhci rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash Joseph Chen (1): ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY Wadim Egorov (1): configs: phycore-rk3288: Enable CONFIG_LTO Wolfgang Zarre (1): rockchip: Pinebook Pro: Fix emmc default configuration arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 + arch/arm/dts/rk3399-u-boot.dtsi| 1 + arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 61 ++ arch/arm/dts/rk3568-rock-3a-u-boot.dtsi| 77 ++ arch/arm/dts/rk356x-u-boot.dtsi| 16 + arch/arm/dts/rk3588-rock-5b-u-boot.dtsi| 182 + arch/arm/dts/rk3588s-u-boot.dtsi | 184 + arch/arm/include/asm/arch-rockchip/bootrom.h | 1 + arch/arm/include/asm/arch-rockchip/clock.h | 21 + arch/arm/mach-rockchip/Kconfig | 2 + arch/arm/mach-rockchip/rk3588/rk3588.c | 1 + configs/evb-rk3568_defconfig | 15 +- configs/evb-rk3588_defconfig | 9 +- configs/neu6a-io-rk3588_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 8 + configs/radxa-cm3-io-rk3566_defconfig | 10 +- configs/rock-3a-rk3568_defconfig | 20 +- configs/rock-pi-4-rk3399_defconfig | 2 + configs/rock5b-rk3588_defconfig| 42 +- configs/rockpro64-rk3399_defconfig | 5 + drivers/clk/rockchip/clk_rk3588.c | 2 +- drivers/mmc/rockchip_sdhci.c | 12 +- drivers/pci/pcie_dw_rockchip.c | 7 +- drivers/phy/meson-g12a-usb2.c | 48 -- drivers/phy/meson-gxbb-usb2.c | 38 - drivers/phy/meson-gxl-usb2.c
Re: [PATCH v2 4/9] pci: pcie_dw_rockchip: Speed up link probe
On 2023/5/18 06:53, Jonas Karlman wrote:
Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.
Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- No change
drivers/pci/pcie_dw_rockchip.c | 68 ++
1 file changed, 37 insertions(+), 31 deletions(-)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 1b8a1409f6df..82a8b9c96e2b 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,9 +61,6 @@ struct rk_pcie {
#define PCIE_CLIENT_DBG_TRANSITION_DATA 0x
#define PCIE_CLIENT_DBF_EN0x0003
-/* Parameters for the waiting for #perst signal */
-#define MACRO_US 1000
-
static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
{
if ((uintptr_t)addr & (size - 1)) {
@@ -242,43 +239,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32
cap_speed)
/* DW pre link configurations */
rk_pcie_configure(priv, cap_speed);
- /* Rest the device */
- if (dm_gpio_is_valid(&priv->rst_gpio)) {
- dm_gpio_set_value(&priv->rst_gpio, 0);
- /*
-* Minimal is 100ms from spec but we see
-* some wired devices need much more, such as 600ms.
-* Add a enough delay to cover all cases.
-*/
- udelay(MACRO_US * 1000);
- dm_gpio_set_value(&priv->rst_gpio, 1);
- }
-
rk_pcie_disable_ltssm(priv);
rk_pcie_link_status_clear(priv);
rk_pcie_enable_debug(priv);
+ /* Reset the device */
+ if (dm_gpio_is_valid(&priv->rst_gpio))
+ dm_gpio_set_value(&priv->rst_gpio, 0);
+
/* Enable LTSSM */
rk_pcie_enable_ltssm(priv);
- for (retries = 0; retries < 5; retries++) {
- if (is_link_up(priv)) {
- dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv,
PCIE_CLIENT_LTSSM_STATUS));
- rk_pcie_debug_dump(priv);
- return 0;
- }
-
- dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
-rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
- rk_pcie_debug_dump(priv);
- udelay(MACRO_US * 1000);
+ /*
+* PCIe requires the refclk to be stable for 100ms prior to releasing
+* PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
+* Express Card Electromechanical Specification, 1.1. However, we don't
+* know if the refclk is coming from RC's PHY or external OSC. If it's
+* from RC, so enabling LTSSM is the just right place to release #PERST.
+*/
+ mdelay(100);
+ if (dm_gpio_is_valid(&priv->rst_gpio))
+ dm_gpio_set_value(&priv->rst_gpio, 1);
+
+ /* Check if the link is up or not */
+ for (retries = 0; retries < 10; retries++) {
+ if (is_link_up(priv))
+ break;
+
+ mdelay(100);
+ }
+
+ if (retries >= 10) {
+ dev_err(priv->dw.dev, "PCIe-%d Link Fail\n",
+ dev_seq(priv->dw.dev));
+ return -EIO;
}
- dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
- /* Link maybe in Gen switch recovery but we need to wait more 1s */
- udelay(MACRO_US * 1000);
- return -EIO;
+ dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
+rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
+ rk_pcie_debug_dump(priv);
+ return 0;
}
static int rockchip_pcie_init_port(struct udevice *dev)
@@ -287,6 +287,12 @@ static int rockchip_pcie_init_port(struct udevice *dev)
u32 val;
struct rk_pcie *priv = dev_get_priv(dev);
+ ret = reset_assert_bulk(&priv->rsts);
+ if (ret) {
+ dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
+ return ret;
+ }
+
/* Set power and maybe external ref clk input */
ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
if (ret && ret != -ENOSYS) {
Re: [PATCH v2 3/9] pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed
Hi Jonas,
On 2023/5/18 06:53, Jonas Karlman wrote:
The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.
Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- Update commit message
drivers/pci/pcie_dw_rockchip.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 83737e62bc6a..1b8a1409f6df 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -288,21 +288,16 @@ static int rockchip_pcie_init_port(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
/* Set power and maybe external ref clk input */
- if (priv->vpcie3v3) {
- ret = regulator_set_value(priv->vpcie3v3, 330);
- if (ret) {
- dev_err(priv->dw.dev, "failed to enable vpcie3v3
(ret=%d)\n",
- ret);
- return ret;
- }
+ ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
+ return ret;
}
- udelay(MACRO_US * 1000);
-
ret = generic_phy_init(&priv->phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
- return ret;
+ goto err_disable_regulator;
}
ret = generic_phy_power_on(&priv->phy);
@@ -345,6 +340,8 @@ err_power_off_phy:
generic_phy_power_off(&priv->phy);
err_exit_phy:
generic_phy_exit(&priv->phy);
+err_disable_regulator:
+ regulator_set_enable_if_allowed(priv->vpcie3v3, false);
return ret;
}
Re: [PATCH v2 1/9] core: read: add dev_read_addr_size_index_ptr function
On 2023/5/18 06:53, Jonas Karlman wrote:
Add dev_read_addr_size_index_ptr function with the same functionality as
dev_read_addr_size_index, but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- New patch
drivers/core/read.c | 11 +++
include/dm/read.h | 21 +
2 files changed, 32 insertions(+)
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 0289a2edb6a4..d3c939530aa5 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice
*dev, int index,
return devfdt_get_addr_size_index(dev, index, size);
}
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+ fdt_size_t *size)
+{
+ fdt_addr_t addr = dev_read_addr_size_index(dev, index, size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
void *dev_remap_addr_index(const struct udevice *dev, int index)
{
fdt_addr_t addr = dev_read_addr_index(dev, index);
diff --git a/include/dm/read.h b/include/dm/read.h
index 56ac076c9f13..7dd43d61a665 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -246,6 +246,20 @@ void *dev_read_addr_index_ptr(const struct udevice *dev,
int index);
fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size);
+/**
+ * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device
+ * as a pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of pairs
+ *and @index is used to select which one is required
+ * @size: place to put size value (on success)
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
+ fdt_size_t *size);
+
/**
* dev_remap_addr_index() - Get the indexed reg property of a device
* as a memory-mapped I/O pointer
@@ -957,6 +971,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const
struct udevice *dev,
return devfdt_get_addr_size_index(dev, index, size);
}
+static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev,
+int index,
+fdt_size_t *size)
+{
+ return devfdt_get_addr_size_index_ptr(dev, index, size);
+}
+
static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev,
const char *name)
{
Re: [PATCH 2/2] configs: rock5b-rk3588: add rtl8169 driver
On 2023/4/25 21:06, Eugen Hristev wrote: Add the rtl8169 driver, which supports the rtl8125b device, which is connected on the pciE bus on this board. Enable also CONFIG_SYS_HAS_NONCACHED_MEMORY to have the descriptors stored. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock5b-rk3588_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index a14fcd2ee924..bfa48227aee2 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00a0 @@ -71,6 +72,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_ETH_DESIGNWARE=y +CONFIG_RTL8169=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y
Re: [PATCH] rockchip: Pinebook Pro: Fix emmc default configuration
On 2023/5/1 15:43, Wolfgang Zarre wrote: If u-boot is installed on the internal emmc, then this will allow to boot without failure. Signed-off-by: Wolfgang Zarre Reviewed-by: Kever Yang Thanks, - Kever --- configs/pinebook-pro-rk3399_defconfig | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index dff4695e37..58a8b91aa6 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_TEXT_BASE=0x0020 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 +CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" @@ -18,6 +19,7 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -57,17 +59,23 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_NVME_PCI=y -CONFIG_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y
Re: [PATCH v2 13/13] rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash
Hi Jonas,
On 2023/5/18 02:26, Jonas Karlman wrote:
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
---
v2:
- Add and use BROM_BOOTSOURCE_SPINOR_RK3588 enum value
- Rebased to resolve conflicts
- Collect r-b tag
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 24
arch/arm/dts/rk3588s-u-boot.dtsi | 20
arch/arm/include/asm/arch-rockchip/bootrom.h | 1 +
arch/arm/mach-rockchip/rk3588/rk3588.c | 1 +
configs/rock5b-rk3588_defconfig | 10
5 files changed, 56 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index db342e6a9391..1cd8a57a6fa6 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,6 +11,7 @@
/ {
aliases {
mmc1 = &sdmmc;
+ spi0 = &sfc;
};
chosen {
@@ -54,6 +55,10 @@
bootph-all;
};
+&fspim2_pins {
+ bootph-all;
+};
+
&pcie2x1l2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
@@ -123,6 +128,25 @@
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe
&emmc_rstnout>;
};
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim2_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2400>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
&uart2m0_xfer {
bootph-all;
};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 2c4cad82b38f..64c309046587 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -165,6 +165,15 @@
};
};
+ sfc: spi@fe2b {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe2b 0x0 0x4000>;
+ interrupts = ;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ status = "disabled";
+ };
+
otp: nvmem@fecc {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc 0x0 0x400>;
@@ -241,3 +250,14 @@
&ioc {
bootph-pre-ram;
};
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h
b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 4276a0f6811a..7dab18fbc3fb 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -48,6 +48,7 @@ enum {
BROM_BOOTSOURCE_SPINOR = 3,
BROM_BOOTSOURCE_SPINAND = 4,
BROM_BOOTSOURCE_SD = 5,
+ BROM_BOOTSOURCE_SPINOR_RK3588 = 6,
Why we need a new type of SPINOR_RK3588?
And this patch not able to apply due to conflict at rk3588s-u-boot.dtsi.
BROM_BOOTSOURCE_USB = 10,
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
};
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b2..b1f535fad505 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e",
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe2c",
+ [BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b/flash@0",
BROM_BOOTSOURCE_SPINOR is already there, why add BROM_BOOTSOURCE_SPINOR_RK3588 ?
Thanks,
- Kever
};
static struct mm_region rk3588_mem_map[] = {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 5fe3a3542e11..9d0b55c01ac9 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
+CONFIG_SF_DEFAULT_SPEED=2400
+CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk358
Re: [PATCH resend v3 3/3] configs: rock5b-rk3588: add PCI drivers and command
On 2023/5/17 18:01, Eugen Hristev wrote: Add drivers for PCIe , phy, and command. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock5b-rk3588_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index fc76d9347db1..f8a9c783764b 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y @@ -63,7 +64,10 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y
