Re: [PATCH 20/30] pinctrl: renesas: Implement unlock register masks
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut wrote:
>
> The V3U SoC has several unlock registers, one per register group. They
> reside at offset zero in each 0x200 bytes-sized block.
>
> To avoid adding yet another table to the PFC implementation, this
> patch adds the option to specify an address mask instead of the fixed
> address in sh_pfc_soc_info::unlock_reg.
>
> This is a direct port of Linux 5.12 commit e127ef2ed0a6
> ("pinctrl: renesas: Implement unlock register masks") by
> Ulrich Hecht
>
> Signed-off-by: Marek Vasut
> ---
> drivers/pinctrl/renesas/pfc.c| 39
> drivers/pinctrl/renesas/sh_pfc.h | 2 +-
> 2 files changed, 20 insertions(+), 21 deletions(-)
>
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
> index 07fcc3d393..2498eb5716 100644
> --- a/drivers/pinctrl/renesas/pfc.c
> +++ b/drivers/pinctrl/renesas/pfc.c
> @@ -131,14 +131,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
> return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
> }
>
> -void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
> +static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
> {
> - void __iomem *unlock_reg =
> - (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
> + u32 unlock;
> +
> + if (!pfc->info->unlock_reg)
> + return;
>
> - if (pfc->info->unlock_reg)
> - sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
> + if (pfc->info->unlock_reg >= 0x8000UL)
> + unlock = pfc->info->unlock_reg;
> + else
> + /* unlock_reg is a mask */
> + unlock = reg & ~pfc->info->unlock_reg;
> +
> + sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
> +}
>
> +void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
> +{
> + sh_pfc_unlock_reg(pfc, reg, data);
> sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
> }
>
> @@ -168,8 +179,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
> unsigned int field, u32 value)
> {
> void __iomem *mapped_reg;
> - void __iomem *unlock_reg =
> - (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
> unsigned int pos;
> u32 mask, data;
>
> @@ -186,9 +195,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
> data &= mask;
> data |= value;
>
> - if (pfc->info->unlock_reg)
> - sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
> -
> + sh_pfc_unlock_reg(pfc, crp->reg, data);
> sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
> }
>
> @@ -679,8 +686,6 @@ static int sh_pfc_pinconf_set_drive_strength(struct
> sh_pfc *pfc,
> unsigned int size;
> unsigned int step;
> void __iomem *reg;
> - void __iomem *unlock_reg =
> - (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
> u32 val;
>
> reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, ,
> );
> @@ -701,9 +706,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct
> sh_pfc *pfc,
> val &= ~GENMASK(offset + 4 - 1, offset);
> val |= strength << offset;
>
> - if (unlock_reg)
> - sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
> -
> + sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
> sh_pfc_write_raw_reg(reg, 32, val);
>
> return 0;
> @@ -743,8 +746,6 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx,
> unsigned _pin,
> {
> struct sh_pfc *pfc = pmx->pfc;
> void __iomem *pocctrl;
> - void __iomem *unlock_reg =
> - (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
> u32 addr, val;
> int bit, ret;
>
> @@ -790,9 +791,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx,
> unsigned _pin,
> else
> val &= ~BIT(bit);
>
> - if (unlock_reg)
> - sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
> -
> + sh_pfc_unlock_reg(pfc, addr, val);
> sh_pfc_write_raw_reg(pocctrl, 32, val);
>
> break;
> diff --git a/drivers/pinctrl/renesas/sh_pfc.h
> b/drivers/pinctrl/renesas/sh_pfc.h
> index 9d74f5fb4e..48d737a141 100644
> --- a/drivers/pinctrl/renesas/sh_pfc.h
> +++ b/drivers/pinctrl/renesas/sh_pfc.h
> @@ -294,7 +294,7 @@ struct sh_pfc_soc_info {
> const struct pinmux_irq *gpio_irq;
> unsigned int gpio_irq_size;
>
> - u32 unlock_reg;
> + u32 unlock_reg; /* can be literal address or mask */
> };
>
> u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
> --
> 2.30.2
>
Re: [PATCH 15/30] gpio: renesas: Pass struct udevice to rcar_gpio_set_direction()
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut wrote:
>
> Pass struct udevice to rcar_gpio_set_direction() in preparation of
> quirk handling in rcar_gpio_set_direction(). No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> drivers/gpio/gpio-rcar.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
> index daaac5e784..5f1ec39a9b 100644
> --- a/drivers/gpio/gpio-rcar.c
> +++ b/drivers/gpio/gpio-rcar.c
> @@ -66,9 +66,12 @@ static int rcar_gpio_set_value(struct udevice *dev,
> unsigned offset,
> return 0;
> }
>
> -static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
> +static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
> bool output)
> {
> + struct rcar_gpio_priv *priv = dev_get_priv(dev);
> + void __iomem *regs = priv->regs;
> +
> /*
> * follow steps in the GPIO documentation for
> * "Setting General Output Mode" and
> @@ -90,9 +93,7 @@ static void rcar_gpio_set_direction(void __iomem *regs,
> unsigned offset,
>
> static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
> {
> - struct rcar_gpio_priv *priv = dev_get_priv(dev);
> -
> - rcar_gpio_set_direction(priv->regs, offset, false);
> + rcar_gpio_set_direction(dev, offset, false);
>
> return 0;
> }
> @@ -100,11 +101,9 @@ static int rcar_gpio_direction_input(struct udevice
> *dev, unsigned offset)
> static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
> int value)
> {
> - struct rcar_gpio_priv *priv = dev_get_priv(dev);
> -
> /* write GPIO value to output before selecting output mode of pin */
> rcar_gpio_set_value(dev, offset, value);
> - rcar_gpio_set_direction(priv->regs, offset, true);
> + rcar_gpio_set_direction(dev, offset, true);
>
> return 0;
> }
> --
> 2.30.2
>
Re: [PATCH 12/30] clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut wrote:
>
> Most of the PLLx, MAIN, FIXED clock handlers are calling very similar
> code, which determines parent rate and then applies multiplication and
> division. The only difference is whether multiplication is fixed factor
> or coming from CRx register. Deduplicate the code into a single function.
>
> Signed-off-by: Marek Vasut
> ---
> drivers/clk/renesas/clk-rcar-gen3.c | 86 ++---
> 1 file changed, 43 insertions(+), 43 deletions(-)
>
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 49ab9134af..7b42e28e83 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -153,6 +153,30 @@ static int gen3_clk_disable(struct clk *clk)
> return renesas_clk_endisable(clk, priv->base, priv->info, false);
> }
>
> +static u64 gen3_clk_get_rate64(struct clk *clk);
> +
> +static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
> + struct clk *parent,
> + const struct cpg_core_clk *core,
> + u32 mul_reg, u32 mult, u32 div,
> + char *name)
> +{
> + u32 value;
> + u64 rate;
> +
> + if (mul_reg) {
> + value = readl(priv->base + mul_reg);
> + mult = (((value >> 24) & 0x7f) + 1) * 2;
> + div = 1;
> + }
> +
> + rate = (gen3_clk_get_rate64(parent) * mult) / div;
> +
> + debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
> + __func__, __LINE__, name, core->parent, mult, div, rate);
> + return rate;
> +}
> +
> static u64 gen3_clk_get_rate64(struct clk *clk)
> {
> struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -161,7 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
> const struct cpg_core_clk *core;
> const struct rcar_gen3_cpg_pll_config *pll_config =
> priv->cpg_pll_config;
> - u32 value, mult, div, prediv, postdiv;
> + u32 value, div, prediv, postdiv;
> u64 rate = 0;
> int i, ret;
>
> @@ -203,60 +227,36 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
> return -EINVAL;
>
> case CLK_TYPE_GEN3_MAIN:
> - rate = gen3_clk_get_rate64() / pll_config->extal_div;
> - debug("%s[%i] MAIN clk: parent=%i extal_div=%i =>
> rate=%llu\n",
> - __func__, __LINE__,
> - core->parent, pll_config->extal_div, rate);
> - return rate;
> + return gen3_clk_get_rate64_pll_mul_reg(priv, , core,
> + 0, 1, pll_config->extal_div,
> + "MAIN");
>
> case CLK_TYPE_GEN3_PLL0:
> - value = readl(priv->base + CPG_PLL0CR);
> - mult = (((value >> 24) & 0x7f) + 1) * 2;
> - rate = gen3_clk_get_rate64() * mult;
> - debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
> - __func__, __LINE__, core->parent, mult, rate);
> - return rate;
> + return gen3_clk_get_rate64_pll_mul_reg(priv, , core,
> + CPG_PLL0CR, 0, 0, "PLL0");
>
> case CLK_TYPE_GEN3_PLL1:
> - rate = gen3_clk_get_rate64() * pll_config->pll1_mult;
> - rate /= pll_config->pll1_div;
> - debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i =>
> rate=%llu\n",
> - __func__, __LINE__,
> - core->parent, pll_config->pll1_mult,
> - pll_config->pll1_div, rate);
> - return rate;
> + return gen3_clk_get_rate64_pll_mul_reg(priv, , core,
> + 0, pll_config->pll1_mult,
> + pll_config->pll1_div, "PLL1");
>
> case CLK_TYPE_GEN3_PLL2:
> - value = readl(priv->base + CPG_PLL2CR);
> - mult = (((value >> 24) & 0x7f) + 1) * 2;
> - rate = gen3_clk_get_rate64() * mult;
> - debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
>
Re: [PATCH 11/30] clk: renesas: Add register pointers into struct cpg_mssr_info
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:32 PM Marek Vasut wrote:
>
> From: Hai Pham
>
> Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda
> To support other register layouts in the future, add register pointers
> of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
>
> Signed-off-by: Hai Pham
> Signed-off-by: Marek Vasut
> ---
> drivers/clk/renesas/clk-rcar-gen3.c| 9 +
> drivers/clk/renesas/renesas-cpg-mssr.c | 49 ++--
> drivers/clk/renesas/renesas-cpg-mssr.h | 52 ++
> 3 files changed, 65 insertions(+), 45 deletions(-)
>
Tested on RZ/G2{EHMN} board
Tested-by: Lad Prabhakar
Cheers,
Prabhaka
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 27939d6318..49ab9134af 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -389,6 +389,15 @@ int gen3_clk_probe(struct udevice *dev)
>
> priv->sscg = !(cpg_mode & BIT(12));
>
> + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
> + priv->info->status_regs = mstpsr;
> + priv->info->control_regs = smstpcr;
> + priv->info->reset_regs = srcr;
> + priv->info->reset_clear_regs = srstclr;
> + } else {
> + return -EINVAL;
> + }
> +
> ret = clk_get_by_name(dev, "extal", >clk_extal);
> if (ret < 0)
> return ret;
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
> b/drivers/clk/renesas/renesas-cpg-mssr.c
> index 0cf80a9866..b1cf7f599c 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -22,47 +22,6 @@
>
> #include "renesas-cpg-mssr.h"
>
> -/*
> - * Module Standby and Software Reset register offets.
> - *
> - * If the registers exist, these are valid for SH-Mobile, R-Mobile,
> - * R-Car Gen2, R-Car Gen3, and RZ/G1.
> - * These are NOT valid for R-Car Gen1 and RZ/A1!
> - */
> -
> -/*
> - * Module Stop Status Register offsets
> - */
> -
> -static const u16 mstpsr[] = {
> - 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
> - 0x9A0, 0x9A4, 0x9A8, 0x9AC,
> -};
> -
> -#defineMSTPSR(i) mstpsr[i]
> -
> -
> -/*
> - * System Module Stop Control Register offsets
> - */
> -
> -static const u16 smstpcr[] = {
> - 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
> - 0x990, 0x994, 0x998, 0x99C,
> -};
> -
> -#defineSMSTPCR(i) smstpcr[i]
> -
> -
> -/* Realtime Module Stop Control Register offsets */
> -#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
> -
> -/* Modem Module Stop Control Register offsets (r8a73a4) */
> -#define MMSTPCR(i) (smstpcr[i] + 0x20)
> -
> -/* Software Reset Clearing Register offsets */
> -#defineSRSTCLR(i) (0x940 + (i) * 4)
> -
> bool renesas_clk_is_mod(struct clk *clk)
> {
> return (clk->id >> 16) == CPG_MOD;
> @@ -147,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem
> *base,
> clkid, reg, bit, enable ? "ON" : "OFF");
>
> if (enable) {
> - clrbits_le32(base + SMSTPCR(reg), bitmask);
> - return wait_for_bit_le32(base + MSTPSR(reg),
> + clrbits_le32(base + info->control_regs[reg], bitmask);
> + return wait_for_bit_le32(base + info->status_regs[reg],
> bitmask, 0, 100, 0);
> } else {
> - setbits_le32(base + SMSTPCR(reg), bitmask);
> + setbits_le32(base + info->control_regs[reg], bitmask);
> return 0;
> }
> }
> @@ -165,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct
> cpg_mssr_info *info)
>
> /* Stop module clock */
> for (i = 0; i < info->mstp_table_size; i++) {
> - clrsetbits_le32(base + SMSTPCR(i),
> + clrsetbits_le32(base + info->control_regs[i],
> info->mstp_table[i].sdis,
> info->mstp_table[i].sen);
> clrsetbits_le32(base + RMSTPCR(i),
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
> b/drivers/clk/renesas/renesas-cpg-mssr.h
> index 3c3b128c4c..92421b15ee 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.h
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.h
> @@ -37,6 +37,10 @@ struct cpg_mssr_info {
> unsigned int
Re: [PATCH 08/30] clk: renesas: Make reset controller modemr register offset configurable
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:32 PM Marek Vasut wrote:
>
> The MODEMR register offset changed on R8A779A0, make the MODEMR offset
> configurable. Fill the offset in on all clock drivers. No functional
> change.
>
> Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
> struct cpg_mssr_info" by Hai Pham
>
> Signed-off-by: Marek Vasut
> ---
> drivers/clk/renesas/clk-rcar-gen2.c | 2 --
> drivers/clk/renesas/clk-rcar-gen3.c | 4 +---
> drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a7790-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a7791-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a7792-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a7794-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 +
> drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
> drivers/clk/renesas/rcar-gen2-cpg.h | 2 ++
> drivers/clk/renesas/rcar-gen3-cpg.h | 2 ++
> drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
> 20 files changed, 21 insertions(+), 5 deletions(-)
>
For RZ/G2{EHMN}
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/clk/renesas/clk-rcar-gen2.c
> b/drivers/clk/renesas/clk-rcar-gen2.c
> index b423c9414b..b0164a6486 100644
> --- a/drivers/clk/renesas/clk-rcar-gen2.c
> +++ b/drivers/clk/renesas/clk-rcar-gen2.c
> @@ -23,8 +23,6 @@
> #include "renesas-cpg-mssr.h"
> #include "rcar-gen2-cpg.h"
>
> -#define CPG_RST_MODEMR 0x0060
> -
> #define CPG_PLL0CR 0x00d8
> #define CPG_SDCKCR 0x0074
>
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 763e268937..938d98546b 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -25,8 +25,6 @@
> #include "renesas-cpg-mssr.h"
> #include "rcar-gen3-cpg.h"
>
> -#define CPG_RST_MODEMR 0x0060
> -
> #define CPG_PLL0CR 0x00d8
> #define CPG_PLL2CR 0x002c
> #define CPG_PLL4CR 0x01f4
> @@ -382,7 +380,7 @@ int gen3_clk_probe(struct udevice *dev)
> if (rst_base == FDT_ADDR_T_NONE)
> return -EINVAL;
>
> - cpg_mode = readl(rst_base + CPG_RST_MODEMR);
> + cpg_mode = readl(rst_base + info->reset_modemr_offset);
>
> priv->cpg_pll_config =
> (struct rcar_gen3_cpg_pll_config
> *)info->get_pll_config(cpg_mode);
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index ef2bb6d777..48da65cd3d 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -321,6 +321,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info
> = {
> .mstp_table = r8a774a1_mstp_table,
> .mstp_table_size= ARRAY_SIZE(r8a774a1_mstp_table),
> .reset_node = "renesas,r8a774a1-rst",
> + .reset_modemr_offset= CPG_RST_MODEMR,
> .extalr_node= "extalr",
> .mod_clk_base = MOD_CLK_BASE,
> .clk_extal_id = CLK_EXTAL,
> diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> index a8b242dc47..418c393a20 100644
> --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> @@ -318,6 +318,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info
> = {
> .mstp_table = r8a774b1_mstp_table,
> .mstp_table_size= ARRAY_SIZE(r8a774b1_mstp_table),
> .reset_node = "renesas,r8a774b1-rst",
> + .reset_modemr_offset= CPG_RST_MODEMR,
> .extalr_node= "extalr",
> .mod_clk_base = MOD_CLK_BASE,
> .clk_extal_id = CLK_EXTAL,
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index 6e9558a107..c1283d2614 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -292,6 +292,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = {
> .mstp_table = r8a774c0_mstp_table,
> .mstp_tab
Re: [PATCH 05/30] clk: renesas: Fix incorrect return RPC clk_get_rate
Hi Marek, Thank you for the patch. On Wed, Apr 28, 2021 at 8:31 PM Marek Vasut wrote: > > From: Hai Pham > > RPC clk_get_rate will return error code instead of expected clock rate. > Fix this. > > Signed-off-by: Hai Pham > Signed-off-by: Marek Vasut > --- > drivers/clk/renesas/clk-rcar-gen3.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Tested on RZ/G2E board Tested-by: Lad Prabhakar Cheers, Prabhakar > diff --git a/drivers/clk/renesas/clk-rcar-gen3.c > b/drivers/clk/renesas/clk-rcar-gen3.c > index 3223becd75..09d84c44e1 100644 > --- a/drivers/clk/renesas/clk-rcar-gen3.c > +++ b/drivers/clk/renesas/clk-rcar-gen3.c > @@ -310,7 +310,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) > __func__, __LINE__, > core->parent, prediv, postdiv, rate); > > - return -EINVAL; > + return rate; > > } > > -- > 2.30.2 >
Re: [PATCH 07/30] clk: renesas: Add support for RPCD2 clock
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:30 PM Marek Vasut wrote:
>
> From: Hai Pham
>
> This supports RPCD2 clock handling. While at it, add the check point
> for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
> number
>
> Signed-off-by: Hai Pham
> Signed-off-by: Marek Vasut
> ---
> drivers/clk/renesas/clk-rcar-gen3.c | 19 ++-
> drivers/clk/renesas/rcar-gen3-cpg.h | 3 +++
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
Tested on RZ/G2E board
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 09d84c44e1..763e268937 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -289,6 +289,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
> return -EINVAL;
>
> case CLK_TYPE_GEN3_RPC:
> + case CLK_TYPE_GEN3_RPCD2:
> rate = gen3_clk_get_rate64();
>
> value = readl(priv->base + core->offset);
> @@ -304,13 +305,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
>
> postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
> CPG_RPC_POSTDIV_MASK;
> - rate /= postdiv + 1;
>
> - debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i =>
> rate=%llu\n",
> - __func__, __LINE__,
> - core->parent, prediv, postdiv, rate);
> + if (postdiv % 2 != 0) {
> + rate /= postdiv + 1;
>
> - return rate;
> + if (core->type == CLK_TYPE_GEN3_RPCD2)
> + rate /= 2;
> +
> + debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i
> => rate=%llu\n",
> + __func__, __LINE__,
> + core->parent, prediv, postdiv, rate);
> +
> + return rate;
> + }
> +
> + return -EINVAL;
>
> }
>
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
> b/drivers/clk/renesas/rcar-gen3-cpg.h
> index 8265c96cf6..52526a0cab 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.h
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.h
> @@ -35,6 +35,9 @@ enum rcar_gen3_clk_types {
> #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
> DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
>
> +#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
> + DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
> +
> #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
> DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
> (_parent0) << 16 | (_parent1), \
> --
> 2.30.2
>
Re: [PATCH 01/30] clk: renesas: Synchronize RZ/G2 tables with Linux 5.12
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:30 PM Marek Vasut wrote:
>
> Synchronize RZ/G2 clock tables with Linux 5.12,
> commit 9f4ad9e425a1 ("Linux 5.12") .
>
> Signed-off-by: Marek Vasut
> ---
> drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 +-
> drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +
> 3 files changed, 26 insertions(+), 5 deletions(-)
>
Tested on RZ/G2{EMN} boards.
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index 1c54eca6c0..ef2bb6d777 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -68,13 +68,18 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
> DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
> DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
> DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
> - DEF_FIXED(".rpcsrc",CLK_RPCSRC,CLK_PLL1, 2, 1),
> + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
> +
> + DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
> +CLK_RPCSRC),
> + DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> +R8A774A1_CLK_RPC),
>
> DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
>
> /* Core Clock Outputs */
> - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z,
> CLK_PLL0, 2, 8),
> - DEF_GEN3_Z("z2",R8A774A1_CLK_Z2,CLK_TYPE_GEN3_Z,
> CLK_PLL2, 2, 0),
> + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z,
> CLK_PLL0, 2, 8),
> + DEF_GEN3_Z("z2",R8A774A1_CLK_Z2,CLK_TYPE_GEN3_Z,
> CLK_PLL2, 2, 0),
> DEF_FIXED("ztr",R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
> DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
> DEF_FIXED("zt", R8A774A1_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
> @@ -99,7 +104,6 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
> DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
> DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
> DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
> - DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC,0x238),
>
> DEF_FIXED("cl", R8A774A1_CLK_CL,CLK_PLL1_DIV2, 48, 1),
> DEF_FIXED("cp", R8A774A1_CLK_CP,CLK_EXTAL, 2, 1),
> @@ -203,7 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
> DEF_MOD("can-fd",914, R8A774A1_CLK_S3D2),
> DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
> DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
> - DEF_MOD("rpc", 917, R8A774A1_CLK_RPC),
> + DEF_MOD("rpc-if",917, R8A774A1_CLK_RPCD2),
> DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
> DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
> DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
> diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> index 03851d0b5a..a8b242dc47 100644
> --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> @@ -39,6 +39,7 @@ enum clk_ids {
> CLK_S2,
> CLK_S3,
> CLK_SDSRC,
> + CLK_RPCSRC,
> CLK_RINT,
>
> /* Module Clocks */
> @@ -64,6 +65,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
> DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
> DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
> DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
> + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
> +
> + DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
> +CLK_RPCSRC),
> + DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> +R8A774B1_CLK_RPC),
>
> DEF_GEN3_OSC(".r",
Re: [PATCH] board: hoperun: Enable recovery SPL for HiHope RZ/G2[HMN] boards
Hi Marek, Thank you for the review. On Mon, Mar 15, 2021 at 11:40 PM Marek Vasut wrote: > > On 3/15/21 11:07 PM, Lad Prabhakar wrote: > > Enable building SPL for HiHope RZ/G2[HMN] boards. > > What is the reason for building the SPL ? > To enable support for recovery using SPL (as done on R-Car platforms) Cheers, Prabhakar
[PATCH 4/5] arm: rmobile: Add Silicon Linux EK874 board support
The EK874 development kit from Silicon Linux is made of CAT874 (the main
board) and CAT875 (the sub board that goes on top of CAT874).
This patch adds the required board support to boot Si-Linux EK874 board
based on R8A774C0 SoC.
DTS files apart from r8a774c0-ek874-u-boot.dts and r8a774c0-u-boot.dtsi
have been imported from Linux kernel 5.11 commit f40ddce88593
("Linux 5.11").
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/cat875.dtsi | 64
arch/arm/dts/r8a774c0-cat874.dts | 453 +
arch/arm/dts/r8a774c0-ek874-u-boot.dts | 33 ++
arch/arm/dts/r8a774c0-ek874.dts| 14 +
arch/arm/dts/r8a774c0-u-boot.dtsi | 53 +++
arch/arm/mach-rmobile/Kconfig.64 | 7 +
board/silinux/ek874/Kconfig| 15 +
board/silinux/ek874/MAINTAINERS| 6 +
board/silinux/ek874/Makefile | 9 +
board/silinux/ek874/ek874.c| 30 ++
configs/silinux_ek874_defconfig| 83 +
include/configs/silinux-ek874.h| 20 ++
include/dt-bindings/display/tda998x.h | 8 +
14 files changed, 796 insertions(+)
create mode 100644 arch/arm/dts/cat875.dtsi
create mode 100644 arch/arm/dts/r8a774c0-cat874.dts
create mode 100644 arch/arm/dts/r8a774c0-ek874-u-boot.dts
create mode 100644 arch/arm/dts/r8a774c0-ek874.dts
create mode 100644 arch/arm/dts/r8a774c0-u-boot.dtsi
create mode 100644 board/silinux/ek874/Kconfig
create mode 100644 board/silinux/ek874/MAINTAINERS
create mode 100644 board/silinux/ek874/Makefile
create mode 100644 board/silinux/ek874/ek874.c
create mode 100644 configs/silinux_ek874_defconfig
create mode 100644 include/configs/silinux-ek874.h
create mode 100644 include/dt-bindings/display/tda998x.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d2f2212f86..f5fe327b6c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -824,6 +824,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774e1-beacon-rzg2h-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
+ r8a774c0-ek874-u-boot.dtb \
r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
diff --git a/arch/arm/dts/cat875.dtsi b/arch/arm/dts/cat875.dtsi
new file mode 100644
index 00..4a2f6fa955
--- /dev/null
+++ b/arch/arm/dts/cat875.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/ {
+ model = "Silicon Linux sub board for CAT874 (CAT875)";
+
+ aliases {
+ ethernet0 =
+ };
+};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupt-parent = <>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = < 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ avb_pins: avb {
+ mux {
+ groups = "avb_mii";
+ function = "avb";
+ };
+ };
+
+ can0_pins: can0 {
+ groups = "can0_data";
+ function = "can0";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data";
+ function = "can1";
+ };
+};
diff --git a/arch/arm/dts/r8a774c0-cat874.dts b/arch/arm/dts/r8a774c0-cat874.dts
new file mode 100644
index 00..676fdef9e0
--- /dev/null
+++ b/arch/arm/dts/r8a774c0-cat874.dts
@@ -0,0 +1,453 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774c0.dtsi"
+#include
+#include
+
+/ {
+ model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
+ compatible = "si-linux,cat874", "renesas,r8a774c0";
+
+ aliases {
+ serial0 =
+ serial1 =
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+
[PATCH 5/5] board: silinux: Enable recovery SPL for EK874 board
Enable building SPL for EK874 board which is based on R8A774C0 SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- arch/arm/mach-rmobile/Makefile | 2 +- board/silinux/ek874/Makefile| 4 configs/silinux_ek874_defconfig | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 3206bce722..9f56af465e 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -22,7 +22,7 @@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ spl/u-boot-spl.srec: spl/u-boot-spl FORCE $(call if_changed,objcopy) -ifneq ($(CONFIG_R8A77990)$(CONFIG_R8A77995),) +ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),) # # The first 6 generate statements generate the R-Car Gen3 SCIF loader header. # The subsequent generate statements represent the following chunk of assembler diff --git a/board/silinux/ek874/Makefile b/board/silinux/ek874/Makefile index 32a3a00990..4c8f0925f1 100644 --- a/board/silinux/ek874/Makefile +++ b/board/silinux/ek874/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y := ../../renesas/rcar-common/gen3-spl.o +else obj-y := ek874.o ../../renesas/rcar-common/common.o +endif diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 442e24a3d7..dcd75604a2 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x5000 +CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x1 CONFIG_ENV_OFFSET=0x3F @@ -9,7 +10,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SILINUX_EK874=y # CONFIG_BOARD_EARLY_INIT_F is not set -# CONFIG_SPL is not set CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_RENESAS=y CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot" -- 2.17.1
[PATCH 3/5] pinctrl: renesas: Add support for R8A774C0
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals.
This patch hooks R8A774C0 SoC with the pfc driver.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm/mach-rmobile/Kconfig.64 | 1 +
drivers/pinctrl/renesas/Kconfig | 10 ++
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pfc.c| 11 +++
drivers/pinctrl/renesas/sh_pfc.h | 1 +
5 files changed, 24 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 7eec65d8ea..28c2628a3c 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -15,6 +15,7 @@ config R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
imply CLK_R8A774C0
+ imply PINCTRL_PFC_R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index d2be4c84ba..8fb9cba387 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -77,6 +77,16 @@ config PINCTRL_PFC_R8A774B1
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A774C0
+bool "Renesas RZ/G2 R8A774C0 pin control driver"
+depends on PINCTRL_PFC
+help
+ Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_PFC_R8A774E1
bool "Renesas RZ/G2 R8A774E1 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1d00752051..0e2ac3c513 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 6ff948420c..07fcc3d393 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -34,6 +34,7 @@ enum sh_pfc_model {
SH_PFC_R8A7796,
SH_PFC_R8A774A1,
SH_PFC_R8A774B1,
+ SH_PFC_R8A774C0,
SH_PFC_R8A774E1,
SH_PFC_R8A77965,
SH_PFC_R8A77970,
@@ -927,6 +928,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A774B1)
priv->pfc.info = _pinmux_info;
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A774C0
+ if (model == SH_PFC_R8A774C0)
+ priv->pfc.info = _pinmux_info;
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
if (model == SH_PFC_R8A774E1)
priv->pfc.info = _pinmux_info;
@@ -1014,6 +1019,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.data = SH_PFC_R8A774B1,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A774C0
+ {
+ .compatible = "renesas,pfc-r8a774c0",
+ .data = SH_PFC_R8A774C0,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
{
.compatible = "renesas,pfc-r8a774e1",
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 22cc860f29..f563916f10 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -295,6 +295,7 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned
int pin,
extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
+extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
--
2.17.1
[PATCH 2/5] pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11
Sync the R8A77990 SoC PFC tables with Linux 5.11 , commit f40ddce88593.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 87 +-
1 file changed, 85 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index b13fc0ba63..572b041b83 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -1603,6 +1603,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -1795,6 +1796,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -2818,6 +2820,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 --
*/
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ /* QSPI0_IO2, QSPI0_IO3 */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 --
*/
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ /* QSPI1_IO2, QSPI1_IO3 */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SCIF0 --
*/
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@@ -3770,8 +3823,10 @@ static const unsigned int vin5_clk_b_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group common[253];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_pin_group automotive[21];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -3916,6 +3971,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a),
@@ -4022,6 +4083,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clk_a),
SH_PFC_PIN_GROUP(vin5_clk_b),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4045,6 +4107,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
};
static const char * const audio_clk_groups[] = {
@@ -4098,6 +4161,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -
[PATCH 1/5] arm: dts: r8a774c0: Resync R8A774C0 SoC DTSI with Linux 5.11
Resync the R8A774C0 SoC DTSI with Linux kernel 5.11 commit f40ddce88593
("Linux 5.11").
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a774c0.dtsi | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/r8a774c0.dtsi b/arch/arm/dts/r8a774c0.dtsi
index e14db4d363..2bdd571bd8 100644
--- a/arch/arm/dts/r8a774c0.dtsi
+++ b/arch/arm/dts/r8a774c0.dtsi
@@ -256,7 +256,7 @@
resets = < 906>;
};
- pfc: pin-controller@e606 {
+ pfc: pinctrl@e606 {
compatible = "renesas,pfc-r8a774c0";
reg = <0 0xe606 0 0x508>;
};
@@ -960,6 +960,7 @@
power-domains = < R8A774C0_PD_ALWAYS_ON>;
resets = < 812>;
phy-mode = "rgmii";
+ rx-internal-delay-ps = <0>;
iommus = <_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1214,9 +1215,8 @@
reg = <0 0xe6ea 0 0x0064>;
interrupts = ;
clocks = < CPG_MOD 210>;
- dmas = < 0x43>, < 0x42>,
- < 0x43>, < 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
+ dmas = < 0x43>, < 0x42>;
+ dma-names = "tx", "rx";
power-domains = < R8A774C0_PD_ALWAYS_ON>;
resets = < 210>;
#address-cells = <1>;
@@ -1698,6 +1698,25 @@
status = "disabled";
};
+ pciec0_ep: pcie-ep@fe00 {
+ compatible = "renesas,r8a774c0-pcie-ep",
+"renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe00 0 0x8>,
+ <0x0 0xfe10 0 0x10>,
+ <0x0 0xfe20 0 0x20>,
+ <0x0 0x3000 0 0x800>,
+ <0x0 0x3800 0 0x800>;
+ reg-names = "apb-base", "memory0", "memory1",
"memory2", "memory3";
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = < 319>;
+ power-domains = < R8A774C0_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
vspb0: vsp@fe96 {
compatible = "renesas,vsp2";
reg = <0 0xfe96 0 0x8000>;
--
2.17.1
[PATCH 0/5] Add Silicon Linux EK874 board
Hi All, This patch series adds support for Silicon Linux EK874 board support which is based on Renesas R8A774C0 SoC. Cheers, Prabhakar Lad Prabhakar (5): arm: dts: r8a774c0: Resync R8A774C0 SoC DTSI with Linux 5.11 pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11 pinctrl: renesas: Add support for R8A774C0 arm: rmobile: Add Silicon Linux EK874 board support board: silinux: Enable recovery SPL for EK874 board arch/arm/dts/Makefile | 1 + arch/arm/dts/cat875.dtsi | 64 arch/arm/dts/r8a774c0-cat874.dts | 453 + arch/arm/dts/r8a774c0-ek874-u-boot.dts | 33 ++ arch/arm/dts/r8a774c0-ek874.dts| 14 + arch/arm/dts/r8a774c0-u-boot.dtsi | 53 +++ arch/arm/dts/r8a774c0.dtsi | 27 +- arch/arm/mach-rmobile/Kconfig.64 | 8 + arch/arm/mach-rmobile/Makefile | 2 +- board/silinux/ek874/Kconfig| 15 + board/silinux/ek874/MAINTAINERS| 6 + board/silinux/ek874/Makefile | 13 + board/silinux/ek874/ek874.c| 30 ++ configs/silinux_ek874_defconfig| 83 + drivers/pinctrl/renesas/Kconfig| 10 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc-r8a77990.c | 87 - drivers/pinctrl/renesas/pfc.c | 11 + drivers/pinctrl/renesas/sh_pfc.h | 1 + include/configs/silinux-ek874.h| 20 ++ include/dt-bindings/display/tda998x.h | 8 + 21 files changed, 933 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/cat875.dtsi create mode 100644 arch/arm/dts/r8a774c0-cat874.dts create mode 100644 arch/arm/dts/r8a774c0-ek874-u-boot.dts create mode 100644 arch/arm/dts/r8a774c0-ek874.dts create mode 100644 arch/arm/dts/r8a774c0-u-boot.dtsi create mode 100644 board/silinux/ek874/Kconfig create mode 100644 board/silinux/ek874/MAINTAINERS create mode 100644 board/silinux/ek874/Makefile create mode 100644 board/silinux/ek874/ek874.c create mode 100644 configs/silinux_ek874_defconfig create mode 100644 include/configs/silinux-ek874.h create mode 100644 include/dt-bindings/display/tda998x.h -- 2.17.1
[PATCH] board: hoperun: Enable recovery SPL for HiHope RZ/G2[HMN] boards
Enable building SPL for HiHope RZ/G2[HMN] boards. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- board/hoperun/hihope-rzg2/Makefile | 4 configs/hihope_rzg2_defconfig | 2 +- include/configs/rcar-gen3-common.h | 4 +++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile index e989e7aacc..fbac612d3a 100644 --- a/board/hoperun/hihope-rzg2/Makefile +++ b/board/hoperun/hihope-rzg2/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y := ../../renesas/rcar-common/gen3-spl.o +else obj-y := hihope-rzg2.o ../../renesas/rcar-common/common.o +endif diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 69eaab073e..8acca194d4 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x5000 +CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_ENV_SIZE=0x2 CONFIG_ENV_OFFSET=0xFFFE CONFIG_DM_GPIO=y CONFIG_RCAR_GEN3=y CONFIG_TARGET_HIHOPE_RZG2=y -# CONFIG_SPL is not set CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index b9762f5beb..24ba5a0c38 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -67,7 +67,9 @@ "booti 0x4808 - 0x4800" /* SPL support */ -#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965) +#if defined(CONFIG_R8A774A1) || defined(CONFIG_R8A774B1) || \ + defined(CONFIG_R8A774E1) || defined(CONFIG_R8A7795) || \ + defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965) #define CONFIG_SPL_BSS_START_ADDR 0xe633f000 #define CONFIG_SPL_BSS_MAX_SIZE0x1000 #else -- 2.17.1
Re: [PATCH 4/8] M: dts: r8a77950-u-boot: Remove leading 0x from rpc node
Hi Marek, Thank you for the review. On Sun, Nov 29, 2020 at 1:06 PM Marek Vasut wrote: > > On 11/18/20 12:32 PM, Prabhakar Mahadev Lad wrote: > > [...] > > >> Subject: [PATCH 4/8] M: dts: r8a77950-u-boot: Remove leading 0x from rpc > >> node > >> > > I missed the typo in the subject s/M/ARM shall I just resend this patch if > > that's OK with you. > > If you could squash all the RPC fixes into a single patch and send that > as one patch -- since they are all fixing the exact same problem -- that > would help. > Done posted a v2. Cheers, Prabhakar
[PATCH v2] ARM: dts: renesas: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
Squashed the changes into single patch.
---
arch/arm/dts/r7s72100-gr-peach-u-boot.dts | 2 +-
arch/arm/dts/r8a77950-u-boot.dtsi | 2 +-
arch/arm/dts/r8a77960-u-boot.dtsi | 2 +-
arch/arm/dts/r8a77965-u-boot.dtsi | 2 +-
arch/arm/dts/r8a77970-u-boot.dtsi | 2 +-
arch/arm/dts/r8a77980-u-boot.dtsi | 2 +-
arch/arm/dts/r8a77990-u-boot.dtsi | 2 +-
arch/arm/dts/r8a77995-u-boot.dtsi | 2 +-
8 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
index 30e35e47d6..f48121a9a8 100644
--- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
+++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
@@ -46,7 +46,7 @@
};
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r7s72100", "renesas,rpc";
reg = <0x3fefa000 0x100>, <0x1800 0x0800>;
bank-width = <2>;
diff --git a/arch/arm/dts/r8a77950-u-boot.dtsi
b/arch/arm/dts/r8a77950-u-boot.dtsi
index 0317f47f0f..5a11651464 100644
--- a/arch/arm/dts/r8a77950-u-boot.dtsi
+++ b/arch/arm/dts/r8a77950-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a7795", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi
b/arch/arm/dts/r8a77960-u-boot.dtsi
index 826c2384bc..f1cae1c359 100644
--- a/arch/arm/dts/r8a77960-u-boot.dtsi
+++ b/arch/arm/dts/r8a77960-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a7796", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi
b/arch/arm/dts/r8a77965-u-boot.dtsi
index 33ff5b148b..9cc6f20537 100644
--- a/arch/arm/dts/r8a77965-u-boot.dtsi
+++ b/arch/arm/dts/r8a77965-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77965", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi
b/arch/arm/dts/r8a77970-u-boot.dtsi
index eabab7ce58..ac3c6be4ad 100644
--- a/arch/arm/dts/r8a77970-u-boot.dtsi
+++ b/arch/arm/dts/r8a77970-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77970", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi
b/arch/arm/dts/r8a77980-u-boot.dtsi
index 1050f6e991..365d40ac49 100644
--- a/arch/arm/dts/r8a77980-u-boot.dtsi
+++ b/arch/arm/dts/r8a77980-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77980", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi
b/arch/arm/dts/r8a77990-u-boot.dtsi
index ddf8b62627..6655abe875 100644
--- a/arch/arm/dts/r8a77990-u-boot.dtsi
+++ b/arch/arm/dts/r8a77990-u-boot.dtsi
@@ -9,7 +9,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77990", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi
b/arch/arm/dts/r8a77995-u-boot.dtsi
index 8e9f6b7a7d..0917a80f09 100644
--- a/arch/arm/dts/r8a77995-u-boot.dtsi
+++ b/arch/arm/dts/r8a77995-u-boot.dtsi
@@ -9,7 +9,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH v4 1/2] pinctrl: renesas: Make sure the pin type is updated after setting the MUX
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).
So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.
This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.
This also avoids pin re-muxing to same type that is for example from
command line device is asked to re-probe/select (mmc dev x) we return
early with success in this case as the pin is already muxed.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 52 +++
1 file changed, 47 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 6cccd33c40..1b1f583ee6 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -45,6 +45,7 @@ enum sh_pfc_model {
struct sh_pfc_pin_config {
u32 type;
+ const char *name;
};
struct sh_pfc_pinctrl {
@@ -488,14 +489,21 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev,
idx = sh_pfc_get_pin_index(pfc, pin->pin);
cfg = >configs[idx];
- if (cfg->type != PINMUX_TYPE_NONE)
+ if (cfg->type != PINMUX_TYPE_NONE) {
+ if (!strcmp(cfg->name, pin->name))
+ return 0;
+
+ dev_err(pfc->dev, "Pin already used as %s\n",
+ cfg->name);
return -EBUSY;
+ }
ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
if (ret)
return ret;
cfg->type = PINMUX_TYPE_GPIO;
+ cfg->name = "gpio";
return 0;
}
@@ -525,6 +533,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev,
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->name = "none";
return 0;
}
@@ -538,11 +547,25 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
const struct sh_pfc_pin *pin = >pfc.info->pins[pin_selector];
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
struct sh_pfc_pin_config *cfg = >configs[idx];
+ int ret;
- if (cfg->type != PINMUX_TYPE_NONE)
+ if (cfg->type != PINMUX_TYPE_NONE) {
+ if (!strcmp(cfg->name, pin->name))
+ return 0;
+
+ dev_err(pfc->dev, "Pin already used as %s\n",
+ cfg->name);
return -EBUSY;
+ }
+
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ if (ret)
+ return ret;
- return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->name = "function";
+
+ return 0;
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned
group_selector,
@@ -552,23 +575,41 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
struct sh_pfc_pinctrl *pmx = >pmx;
struct sh_pfc *pfc = >pfc;
const struct sh_pfc_pin_group *grp =
>pfc.info->groups[group_selector];
+ bool grp_pins_configured = true;
+ struct sh_pfc_pin_config *cfg;
unsigned int i;
int ret = 0;
+ int idx;
for (i = 0; i < grp->nr_pins; ++i) {
- int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
- struct sh_pfc_pin_config *cfg = >configs[idx];
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
+ if (!strcmp(cfg->name, grp->name))
+ continue;
+
+ dev_err(pfc->dev, "Pin already used as %s\n",
+ cfg->name);
ret = -EBUSY;
goto done;
+ } else {
+ grp_pins_configured = false;
}
}
+ if (grp_pins_configured)
+ return 0;
+
for (i = 0; i < grp->nr_pins; ++i) {
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
+
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+
[PATCH v4 2/2] pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 1b1f583ee6..c45fdca64d 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -450,6 +450,30 @@ static const char *sh_pfc_pinctrl_get_group_name(struct
udevice *dev,
return priv->pfc.info->groups[selector].name;
}
+static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
+unsigned int selector,
+char *buf, int size)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = >pmx;
+ struct sh_pfc *pfc = >pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin;
+ int idx;
+
+ pin = >pfc.info->pins[selector];
+ if (!pin) {
+ snprintf(buf, size, "Unknown");
+ return -EINVAL;
+ }
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = >configs[idx];
+ snprintf(buf, size, "%s", cfg->name);
+
+ return 0;
+}
+
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
@@ -816,6 +840,7 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
.get_group_name = sh_pfc_pinctrl_get_group_name,
+ .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
.get_functions_count= sh_pfc_pinctrl_get_functions_count,
.get_function_name = sh_pfc_pinctrl_get_function_name,
--
2.17.1
[PATCH v4 0/2] pinctrl: renesas: trivial fixes and enhancements
Hi All, This patch series includes trivial fixes and enhancements to renesas pfc driver. Cheers, Prabhakar v3->v4 * Avoided pin to be re-muxed for the same device. v2->v3 * Patch 1/2 print a warning message if the current pin is being overwritten before abort as suggested by Marek. * Patch 2/2 unchanged v1->v2 * Patch 1/2 updated commit message * Patch 2/2 unchanged Lad Prabhakar (2): pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback drivers/pinctrl/renesas/pfc.c | 77 --- 1 file changed, 72 insertions(+), 5 deletions(-) -- 2.17.1
[PATCH 8/8] ARM: dts: r7s72100-gr-peach-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r7s72100-gr-peach-u-boot.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
index 30e35e47d6..f48121a9a8 100644
--- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
+++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
@@ -46,7 +46,7 @@
};
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r7s72100", "renesas,rpc";
reg = <0x3fefa000 0x100>, <0x1800 0x0800>;
bank-width = <2>;
--
2.17.1
[PATCH 7/8] ARM: dts: r8a77970-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77970-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi
b/arch/arm/dts/r8a77970-u-boot.dtsi
index eabab7ce58..ac3c6be4ad 100644
--- a/arch/arm/dts/r8a77970-u-boot.dtsi
+++ b/arch/arm/dts/r8a77970-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77970", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 6/8] ARM: dts: r8a77995-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77995-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi
b/arch/arm/dts/r8a77995-u-boot.dtsi
index 8e9f6b7a7d..0917a80f09 100644
--- a/arch/arm/dts/r8a77995-u-boot.dtsi
+++ b/arch/arm/dts/r8a77995-u-boot.dtsi
@@ -9,7 +9,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 5/8] ARM: dts: r8a77960-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77960-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi
b/arch/arm/dts/r8a77960-u-boot.dtsi
index 826c2384bc..f1cae1c359 100644
--- a/arch/arm/dts/r8a77960-u-boot.dtsi
+++ b/arch/arm/dts/r8a77960-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a7796", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 4/8] M: dts: r8a77950-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77950-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77950-u-boot.dtsi
b/arch/arm/dts/r8a77950-u-boot.dtsi
index 0317f47f0f..5a11651464 100644
--- a/arch/arm/dts/r8a77950-u-boot.dtsi
+++ b/arch/arm/dts/r8a77950-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a7795", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 3/8] ARM: dts: 8a77980-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77980-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi
b/arch/arm/dts/r8a77980-u-boot.dtsi
index 1050f6e991..365d40ac49 100644
--- a/arch/arm/dts/r8a77980-u-boot.dtsi
+++ b/arch/arm/dts/r8a77980-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77980", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 2/8] ARM: dts: r8a77990-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77990-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi
b/arch/arm/dts/r8a77990-u-boot.dtsi
index ddf8b62627..6655abe875 100644
--- a/arch/arm/dts/r8a77990-u-boot.dtsi
+++ b/arch/arm/dts/r8a77990-u-boot.dtsi
@@ -9,7 +9,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77990", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 1/8] ARM: dts: r8a77965-u-boot: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee20 simple-bus unit
address format error, expected "ee20"
Signed-off-by: Lad Prabhakar
---
arch/arm/dts/r8a77965-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi
b/arch/arm/dts/r8a77965-u-boot.dtsi
index 33ff5b148b..9cc6f20537 100644
--- a/arch/arm/dts/r8a77965-u-boot.dtsi
+++ b/arch/arm/dts/r8a77965-u-boot.dtsi
@@ -13,7 +13,7 @@
/ {
soc {
- rpc: rpc@0xee20 {
+ rpc: rpc@ee20 {
compatible = "renesas,rpc-r8a77965", "renesas,rpc";
reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
clocks = < CPG_MOD 917>;
--
2.17.1
[PATCH 0/8] Renesas drop leading 0x from rpc nodes
Hi All, This patch series drops leading 0x from rpc nodes. Cheers, Prabhakar Lad Prabhakar (8): ARM: dts: r8a77965-u-boot: Remove leading 0x from rpc node ARM: dts: r8a77990-u-boot: Remove leading 0x from rpc node ARM: dts: 8a77980-u-boot: Remove leading 0x from rpc node M: dts: r8a77950-u-boot: Remove leading 0x from rpc node ARM: dts: r8a77960-u-boot: Remove leading 0x from rpc node ARM: dts: r8a77995-u-boot: Remove leading 0x from rpc node ARM: dts: r8a77970-u-boot: Remove leading 0x from rpc node ARM: dts: r7s72100-gr-peach-u-boot: Remove leading 0x from rpc node arch/arm/dts/r7s72100-gr-peach-u-boot.dts | 2 +- arch/arm/dts/r8a77950-u-boot.dtsi | 2 +- arch/arm/dts/r8a77960-u-boot.dtsi | 2 +- arch/arm/dts/r8a77965-u-boot.dtsi | 2 +- arch/arm/dts/r8a77970-u-boot.dtsi | 2 +- arch/arm/dts/r8a77980-u-boot.dtsi | 2 +- arch/arm/dts/r8a77990-u-boot.dtsi | 2 +- arch/arm/dts/r8a77995-u-boot.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) -- 2.17.1
[PATCH] pinctrl: renesas: Add support for R8A774C0
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals.
This patch hooks R8A774C0 SoC with the pfc driver.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm/mach-rmobile/Kconfig.64 | 1 +
drivers/pinctrl/renesas/Kconfig | 10 ++
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pfc.c| 11 +++
drivers/pinctrl/renesas/sh_pfc.h | 1 +
5 files changed, 24 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 56c522596a..90bc4acd08 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -15,6 +15,7 @@ config R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
imply CLK_R8A774C0
+ imply PINCTRL_PFC_R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index d2be4c84ba..8fb9cba387 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -77,6 +77,16 @@ config PINCTRL_PFC_R8A774B1
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A774C0
+bool "Renesas RZ/G2 R8A774C0 pin control driver"
+depends on PINCTRL_PFC
+help
+ Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_PFC_R8A774E1
bool "Renesas RZ/G2 R8A774E1 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1d00752051..0e2ac3c513 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 4c1e770422..8a566f7139 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -34,6 +34,7 @@ enum sh_pfc_model {
SH_PFC_R8A7796,
SH_PFC_R8A774A1,
SH_PFC_R8A774B1,
+ SH_PFC_R8A774C0,
SH_PFC_R8A774E1,
SH_PFC_R8A77965,
SH_PFC_R8A77970,
@@ -909,6 +910,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A774B1)
priv->pfc.info = _pinmux_info;
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A774C0
+ if (model == SH_PFC_R8A774C0)
+ priv->pfc.info = _pinmux_info;
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
if (model == SH_PFC_R8A774E1)
priv->pfc.info = _pinmux_info;
@@ -996,6 +1001,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.data = SH_PFC_R8A774B1,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A774C0
+ {
+ .compatible = "renesas,pfc-r8a774c0",
+ .data = SH_PFC_R8A774C0,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
{
.compatible = "renesas,pfc-r8a774e1",
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 22cc860f29..f563916f10 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -295,6 +295,7 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned
int pin,
extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
+extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
--
2.17.1
[PATCH v3 1/2] pinctrl: renesas: Make sure the pin type is updated after setting the MUX
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).
So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.
This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index fb811a95bc..174e91923a 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -487,8 +487,10 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev,
idx = sh_pfc_get_pin_index(pfc, pin->pin);
cfg = >configs[idx];
- if (cfg->type != PINMUX_TYPE_NONE)
+ if (cfg->type != PINMUX_TYPE_NONE) {
+ dev_err(pfc->dev, "Pin already used\n");
return -EBUSY;
+ }
ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
if (ret)
@@ -537,11 +539,20 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
const struct sh_pfc_pin *pin = >pfc.info->pins[pin_selector];
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
struct sh_pfc_pin_config *cfg = >configs[idx];
+ int ret;
- if (cfg->type != PINMUX_TYPE_NONE)
+ if (cfg->type != PINMUX_TYPE_NONE) {
+ dev_err(pfc->dev, "Pin already used\n");
return -EBUSY;
+ }
+
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ if (ret)
+ return ret;
- return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ cfg->type = PINMUX_TYPE_FUNCTION;
+
+ return 0;
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned
group_selector,
@@ -551,14 +562,17 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
struct sh_pfc_pinctrl *pmx = >pmx;
struct sh_pfc *pfc = >pfc;
const struct sh_pfc_pin_group *grp =
>pfc.info->groups[group_selector];
+ struct sh_pfc_pin_config *cfg;
unsigned int i;
int ret = 0;
+ int idx;
for (i = 0; i < grp->nr_pins; ++i) {
- int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
- struct sh_pfc_pin_config *cfg = >configs[idx];
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
+ dev_err(pfc->dev, "Pin already used\n");
ret = -EBUSY;
goto done;
}
@@ -568,6 +582,10 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
+
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
+ cfg->type = PINMUX_TYPE_FUNCTION;
}
done:
--
2.17.1
[PATCH v3 0/2] pinctrl: renesas: trivial fixes and enhancements
Hi All, This patch series includes trivial fixes and enhancements to renesas pfc driver. Oops sorry to miss the u-boot ML earlier resent a V3 again. Cheers, Prabhakar v2->v3 * Patch 1/2 print a warning message if the current pin is being overwritten before abort as suggested by Marek. * Patch 2/2 unchanged v1->v2 * Patch 1/2 updated commit message * Patch 2/2 unchanged Lad Prabhakar (2): pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback drivers/pinctrl/renesas/pfc.c | 59 --- 1 file changed, 54 insertions(+), 5 deletions(-) -- 2.17.1
[PATCH v3 2/2] pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 174e91923a..4c1e770422 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -44,6 +44,7 @@ enum sh_pfc_model {
struct sh_pfc_pin_config {
u32 type;
+ const char *function_name;
};
struct sh_pfc_pinctrl {
@@ -448,6 +449,30 @@ static const char *sh_pfc_pinctrl_get_group_name(struct
udevice *dev,
return priv->pfc.info->groups[selector].name;
}
+static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
+unsigned int selector,
+char *buf, int size)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = >pmx;
+ struct sh_pfc *pfc = >pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin;
+ int idx;
+
+ pin = >pfc.info->pins[selector];
+ if (!pin) {
+ snprintf(buf, size, "Unknown");
+ return -EINVAL;
+ }
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = >configs[idx];
+ snprintf(buf, size, "%s", cfg->function_name);
+
+ return 0;
+}
+
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
@@ -497,6 +522,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev,
return ret;
cfg->type = PINMUX_TYPE_GPIO;
+ cfg->function_name = "gpio";
return 0;
}
@@ -526,6 +552,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev,
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
return 0;
}
@@ -551,6 +578,7 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
return ret;
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name = "function";
return 0;
}
@@ -586,6 +614,7 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name =
priv->pfc.info->groups[group_selector].name;
}
done:
@@ -792,6 +821,7 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
.get_group_name = sh_pfc_pinctrl_get_group_name,
+ .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
.get_functions_count= sh_pfc_pinctrl_get_functions_count,
.get_function_name = sh_pfc_pinctrl_get_function_name,
@@ -822,6 +852,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct
sh_pfc_pinctrl *pmx)
for (i = 0; i < pfc->info->nr_pins; ++i) {
struct sh_pfc_pin_config *cfg = >configs[i];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
}
return 0;
--
2.17.1
[PATCH v2 2/2] pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 275702d13a..a1da45db2e 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -44,6 +44,7 @@ enum sh_pfc_model {
struct sh_pfc_pin_config {
u32 type;
+ const char *function_name;
};
struct sh_pfc_pinctrl {
@@ -448,6 +449,30 @@ static const char *sh_pfc_pinctrl_get_group_name(struct
udevice *dev,
return priv->pfc.info->groups[selector].name;
}
+static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
+unsigned int selector,
+char *buf, int size)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = >pmx;
+ struct sh_pfc *pfc = >pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin;
+ int idx;
+
+ pin = >pfc.info->pins[selector];
+ if (!pin) {
+ snprintf(buf, size, "Unknown");
+ return -EINVAL;
+ }
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = >configs[idx];
+ snprintf(buf, size, "%s", cfg->function_name);
+
+ return 0;
+}
+
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
@@ -495,6 +520,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev,
return ret;
cfg->type = PINMUX_TYPE_GPIO;
+ cfg->function_name = "gpio";
return 0;
}
@@ -524,6 +550,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev,
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
return 0;
}
@@ -547,6 +574,7 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
return ret;
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name = "function";
return 0;
}
@@ -581,6 +609,7 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name =
priv->pfc.info->groups[group_selector].name;
}
done:
@@ -787,6 +816,7 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
.get_group_name = sh_pfc_pinctrl_get_group_name,
+ .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
.get_functions_count= sh_pfc_pinctrl_get_functions_count,
.get_function_name = sh_pfc_pinctrl_get_function_name,
@@ -817,6 +847,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct
sh_pfc_pinctrl *pmx)
for (i = 0; i < pfc->info->nr_pins; ++i) {
struct sh_pfc_pin_config *cfg = >configs[i];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
}
return 0;
--
2.17.1
[PATCH v2 0/2] pinctrl: renesas: trivial fixes and enhancements
Hi All, This patch series includes trivial fixes and enhancements to renesas pfc driver. Cheers, Prabhakar v1->v2 * Patch 1/2 updated commit message * patch 2/2 unchanged Lad Prabhakar (2): pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback drivers/pinctrl/renesas/pfc.c | 50 --- 1 file changed, 47 insertions(+), 3 deletions(-) -- 2.17.1
[PATCH v2 1/2] pinctrl: renesas: Make sure the pin type is updated after setting the MUX
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).
So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.
This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index fb811a95bc..275702d13a 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -537,11 +537,18 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
const struct sh_pfc_pin *pin = >pfc.info->pins[pin_selector];
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
struct sh_pfc_pin_config *cfg = >configs[idx];
+ int ret;
if (cfg->type != PINMUX_TYPE_NONE)
return -EBUSY;
- return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ if (ret)
+ return ret;
+
+ cfg->type = PINMUX_TYPE_FUNCTION;
+
+ return 0;
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned
group_selector,
@@ -551,12 +558,14 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
struct sh_pfc_pinctrl *pmx = >pmx;
struct sh_pfc *pfc = >pfc;
const struct sh_pfc_pin_group *grp =
>pfc.info->groups[group_selector];
+ struct sh_pfc_pin_config *cfg;
unsigned int i;
int ret = 0;
+ int idx;
for (i = 0; i < grp->nr_pins; ++i) {
- int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
- struct sh_pfc_pin_config *cfg = >configs[idx];
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
ret = -EBUSY;
@@ -568,6 +577,10 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
+
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
+ cfg->type = PINMUX_TYPE_FUNCTION;
}
done:
--
2.17.1
Re: [RESEND PATCH 2/3] pinctrl: renesas: Make sure the pin type is updated after setting the MUX
Hi Marek,
Thank you for the review.
On Wed, Nov 4, 2020 at 7:29 PM Marek Vasut wrote:
>
> On 11/4/20 6:27 PM, Lad Prabhakar wrote:
> > Update pin type after every successful call to sh_pfc_config_mux().
> >
> > This fixes pin functionality from being overwritten.
>
> Can you please provide more details about the problem you are fixing
> here ? What is the problem ? What triggers it ?
>
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in
sh_pfc_pinctrl_pin_set()/sh_pfc_pinctrl_group_set() calls (although
these calls have a check if pin type is not PINMUX_TYPE_NONE). So with
the current implementation suppose initially the pin is configured as
USB function and later as SPI function this driver does not complain
and makes USB unusable.
With this patch on every successful call to
sh_pfc_pinctrl_pin_set()/sh_pfc_pinctrl_group_set() the pin type is
updated so that the functionality of the pin is not overwritten as
these functions already have the below check,
if (cfg->type != PINMUX_TYPE_NONE) {
ret = -EBUSY;
Cheers,
Prabhakar
[RESEND PATCH 2/3] pinctrl: renesas: Make sure the pin type is updated after setting the MUX
Update pin type after every successful call to sh_pfc_config_mux().
This fixes pin functionality from being overwritten.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index fb811a95bc..275702d13a 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -537,11 +537,18 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
const struct sh_pfc_pin *pin = >pfc.info->pins[pin_selector];
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
struct sh_pfc_pin_config *cfg = >configs[idx];
+ int ret;
if (cfg->type != PINMUX_TYPE_NONE)
return -EBUSY;
- return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ if (ret)
+ return ret;
+
+ cfg->type = PINMUX_TYPE_FUNCTION;
+
+ return 0;
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned
group_selector,
@@ -551,12 +558,14 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
struct sh_pfc_pinctrl *pmx = >pmx;
struct sh_pfc *pfc = >pfc;
const struct sh_pfc_pin_group *grp =
>pfc.info->groups[group_selector];
+ struct sh_pfc_pin_config *cfg;
unsigned int i;
int ret = 0;
+ int idx;
for (i = 0; i < grp->nr_pins; ++i) {
- int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
- struct sh_pfc_pin_config *cfg = >configs[idx];
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
ret = -EBUSY;
@@ -568,6 +577,10 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
+
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
+ cfg->type = PINMUX_TYPE_FUNCTION;
}
done:
--
2.17.1
[RESEND PATCH 3/3] pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 275702d13a..a1da45db2e 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -44,6 +44,7 @@ enum sh_pfc_model {
struct sh_pfc_pin_config {
u32 type;
+ const char *function_name;
};
struct sh_pfc_pinctrl {
@@ -448,6 +449,30 @@ static const char *sh_pfc_pinctrl_get_group_name(struct
udevice *dev,
return priv->pfc.info->groups[selector].name;
}
+static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
+unsigned int selector,
+char *buf, int size)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = >pmx;
+ struct sh_pfc *pfc = >pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin;
+ int idx;
+
+ pin = >pfc.info->pins[selector];
+ if (!pin) {
+ snprintf(buf, size, "Unknown");
+ return -EINVAL;
+ }
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = >configs[idx];
+ snprintf(buf, size, "%s", cfg->function_name);
+
+ return 0;
+}
+
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
@@ -495,6 +520,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev,
return ret;
cfg->type = PINMUX_TYPE_GPIO;
+ cfg->function_name = "gpio";
return 0;
}
@@ -524,6 +550,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev,
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
return 0;
}
@@ -547,6 +574,7 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
return ret;
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name = "function";
return 0;
}
@@ -581,6 +609,7 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name =
priv->pfc.info->groups[group_selector].name;
}
done:
@@ -787,6 +816,7 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
.get_group_name = sh_pfc_pinctrl_get_group_name,
+ .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
.get_functions_count= sh_pfc_pinctrl_get_functions_count,
.get_function_name = sh_pfc_pinctrl_get_function_name,
@@ -817,6 +847,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct
sh_pfc_pinctrl *pmx)
for (i = 0; i < pfc->info->nr_pins; ++i) {
struct sh_pfc_pin_config *cfg = >configs[i];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
}
return 0;
--
2.17.1
[RESEND PATCH 0/3] pinctrl: renesas: trivial fixes and enhancements
Hi All, This patch series includes trivial fixes and enhancements to renesas pfc driver. This is exactly the same series posted earlier [1]. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=203651 Cheers, Prabhakar Lad Prabhakar (3): pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback drivers/pinctrl/renesas/pfc.c | 54 ++- 1 file changed, 47 insertions(+), 7 deletions(-) -- 2.17.1
[RESEND PATCH 1/3] pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl
Drop unused members from struct sh_pfc_pinctrl.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index db0fa9b728..fb811a95bc 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -50,10 +50,6 @@ struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
struct sh_pfc_pin_config *configs;
-
- const char *func_prop_name;
- const char *groups_prop_name;
- const char *pins_prop_name;
};
struct sh_pfc_pin_range {
--
2.17.1
[PATCH v2] cmd: fat: Use do_save() for fatwrite
do_save() function defined in fs.c also supports FAT file system
re-use the same for fatwrite command.
Also fix the FAT test script to match the expected output.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2
* Fixed FAT test scripts
* Sandbox test results: 655 passed, 76 skipped in 127.02s (0:02:07)
v1 -
* https://patchwork.ozlabs.org/project/uboot/patch/
20200929071300.19866-1-prabhakar.mahadev-lad...@bp.renesas.com/
---
cmd/fat.c | 43 +--
test/py/tests/test_fs/test_ext.py | 6 ++---
2 files changed, 4 insertions(+), 45 deletions(-)
diff --git a/cmd/fat.c b/cmd/fat.c
index b438ce16c9..69ce1fa530 100644
--- a/cmd/fat.c
+++ b/cmd/fat.c
@@ -98,48 +98,7 @@ U_BOOT_CMD(
static int do_fat_fswrite(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- loff_t size;
- int ret;
- unsigned long addr;
- unsigned long count;
- long offset;
- struct blk_desc *dev_desc = NULL;
- struct disk_partition info;
- int dev = 0;
- int part = 1;
- void *buf;
-
- if (argc < 5)
- return cmd_usage(cmdtp);
-
- part = blk_get_device_part_str(argv[1], argv[2], _desc, , 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->devnum;
-
- if (fat_set_blk_dev(dev_desc, ) != 0) {
- printf("\n** Unable to use %s %d:%d for fatwrite **\n",
- argv[1], dev, part);
- return 1;
- }
- addr = simple_strtoul(argv[3], NULL, 16);
- count = (argc <= 5) ? 0 : simple_strtoul(argv[5], NULL, 16);
- /* offset should be a hex, but "-1" is allowed */
- offset = (argc <= 6) ? 0 : simple_strtol(argv[6], NULL, 16);
-
- buf = map_sysmem(addr, count);
- ret = file_fat_write(argv[4], buf, offset, count, );
- unmap_sysmem(buf);
- if (ret < 0) {
- printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
- argv[4], argv[1], dev, part);
- return 1;
- }
-
- printf("%llu bytes written\n", size);
-
- return 0;
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_FAT);
}
U_BOOT_CMD(
diff --git a/test/py/tests/test_fs/test_ext.py
b/test/py/tests/test_fs/test_ext.py
index 6b7fc48701..dba874fc59 100644
--- a/test/py/tests/test_fs/test_ext.py
+++ b/test/py/tests/test_fs/test_ext.py
@@ -74,7 +74,7 @@ class TestFsExt(object):
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/none/%s.w3 $filesize'
% (fs_type, ADDR, MIN_FILE)])
-assert('Unable to write "/dir1/none/' in ''.join(output))
+assert('Unable to write file /dir1/none/' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
def test_fs_ext4(self, u_boot_console, fs_obj_ext):
@@ -216,7 +216,7 @@ class TestFsExt(object):
output = u_boot_console.run_command(
'%swrite host 0:0 %x /dir1/%s.w8 0x1400 %x'
% (fs_type, ADDR, MIN_FILE, 0x10 + 0x1400))
-assert('Unable to write "/dir1' in output)
+assert('Unable to write file /dir1' in output)
assert_fs_integrity(fs_type, fs_img)
def test_fs_ext9(self, u_boot_console, fs_obj_ext):
@@ -231,7 +231,7 @@ class TestFsExt(object):
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
% (fs_type, ADDR, MIN_FILE)])
-assert('Unable to write "/dir1' in ''.join(output))
+assert('Unable to write file /dir1' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
def test_fs_ext10(self, u_boot_console, fs_obj_ext):
--
2.17.1
Re: [PATCH 0/3] pinctrl: renesas: trivial fixes and enhancements
On Wed, Sep 23, 2020 at 11:27 AM Lad Prabhakar wrote: > > Hi All, > > This patch series includes trivial fixes and enhancements to > renesas pfc driver. > > Cheers, > Prabhakar > > Lad Prabhakar (3): > pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl > pinctrl: renesas: Make sure the pin type is updated after setting the > MUX > pinctrl: renesas: Implement get_pin_muxing() callback > > drivers/pinctrl/renesas/pfc.c | 54 ++- > 1 file changed, 47 insertions(+), 7 deletions(-) > Gentle ping. Cheers, Prabhakar
[PATCH 2/3] arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm/dts/r8a774c0.dtsi| 1960 +
include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 61 +
include/dt-bindings/power/r8a774c0-sysc.h | 25 +
3 files changed, 2046 insertions(+)
create mode 100644 arch/arm/dts/r8a774c0.dtsi
create mode 100644 include/dt-bindings/clock/r8a774c0-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a774c0-sysc.h
diff --git a/arch/arm/dts/r8a774c0.dtsi b/arch/arm/dts/r8a774c0.dtsi
new file mode 100644
index 00..e14db4d363
--- /dev/null
+++ b/arch/arm/dts/r8a774c0.dtsi
@@ -0,0 +1,1960 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZ/G2E (R8A774C0) SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "renesas,r8a774c0";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ cluster1_opp: opp_table10 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ opp-suspend;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ power-domains = < R8A774C0_PD_CA53_CPU0>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ dynamic-power-coefficient = <277>;
+ clocks = < CPG_CORE R8A774C0_CLK_Z2>;
+ operating-points-v2 = <_opp>;
+ };
+
+ a53_1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <1>;
+ device_type = "cpu";
+ power-domains = < R8A774C0_PD_CA53_CPU1>;
+ next-level-cache = <_CA53>;
+ enable-method = "psci";
+ clocks = < CPG_CORE R8A774C0_CLK_Z2>;
+ operating-points-v2 = <_opp>;
+ };
+
+ L2_CA53: cache-controller-0 {
+ compatible = "cache";
+ power-domains = < R8A774C0_PD_CA53_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0
[PATCH 1/3] arm: renesas: Add config option for R8A774C0 SoC
Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- arch/arm/mach-rmobile/Kconfig.64 | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 59cb072096..b80505db26 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -9,6 +9,9 @@ config R8A774B1 bool "Renesas SoC R8A774B1" imply CLK_R8A774B1 +config R8A774C0 + bool "Renesas SoC R8A774C0" + config R8A774E1 bool "Renesas SoC R8A774E1" imply CLK_R8A774E1 -- 2.17.1
[PATCH 3/3] clk: renesas: Import R8A774C0 clock tables from Linux 5.9
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm/mach-rmobile/Kconfig.64| 1 +
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile| 1 +
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 308
4 files changed, 316 insertions(+)
create mode 100644 drivers/clk/renesas/r8a774c0-cpg-mssr.c
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index b80505db26..be3ea3c1a9 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -11,6 +11,7 @@ config R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
+ imply CLK_R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 44afcecbfa..0c8b9eb47d 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -61,6 +61,12 @@ config CLK_R8A774B1
help
Enable this to support the clocks on Renesas R8A774B1 SoC.
+config CLK_R8A774C0
+ bool "Renesas R8A774C0 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A774C0 SoC.
+
config CLK_R8A774E1
bool "Renesas R8A774E1 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index da353e811d..ed1a1252c4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
new file mode 100644
index 00..c9f0f7221d
--- /dev/null
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ * Based on r8a77990-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A774C0_CLK_CANFD,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL0D4,
+ CLK_PLL0D6,
+ CLK_PLL0D8,
+ CLK_PLL0D20,
+ CLK_PLL0D24,
+ CLK_PLL1D2,
+ CLK_PE,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RINT,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a774c0_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
+ DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
+ DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
+ DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
+ DEF_FIXED(".pll0d20", CLK_PLL0D20,CLK_PLL0, 20, 1),
+ DEF_FIXED(".pll0d24", CLK_PLL0D24,CLK_PLL0, 24, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20,1, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
+
+ DEF_RATE(".oco", CLK_OCO
[PATCH 0/3] Renesas R8A774C0 import DTSI and clocks
Hi All, This patch series imports DTSI and clocks from Linux 5.9 for R8A774C0 (RZ/G2E) SoC. This series applies on top of [1]. [1] https://github.com/marex/u-boot-sh/tree/next Cheers, Prabhakar Lad Prabhakar (3): arm: renesas: Add config option for R8A774C0 SoC arm: dts: r8a774c0: Import DTS from Linux 5.9 clk: renesas: Import R8A774C0 clock tables from Linux 5.9 arch/arm/dts/r8a774c0.dtsi| 1960 + arch/arm/mach-rmobile/Kconfig.64 |4 + drivers/clk/renesas/Kconfig |6 + drivers/clk/renesas/Makefile |1 + drivers/clk/renesas/r8a774c0-cpg-mssr.c | 308 +++ include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 61 + include/dt-bindings/power/r8a774c0-sysc.h | 25 + 7 files changed, 2365 insertions(+) create mode 100644 arch/arm/dts/r8a774c0.dtsi create mode 100644 drivers/clk/renesas/r8a774c0-cpg-mssr.c create mode 100644 include/dt-bindings/clock/r8a774c0-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774c0-sysc.h -- 2.17.1
Re: [PATCH] mtd: spi-nor-ids: Add Winbond W25M512JV flash entry
On Thu, Sep 17, 2020 at 3:50 PM Lad Prabhakar
wrote:
>
> Add Winbond W25M512JV flash device description.
>
> Linux already has the flash entry present. A snippet below:
> { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...},
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Biju Das
> ---
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
Gentle ping.
Cheers,
Prabhakar
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 114ebacde1..4ed997706a 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -314,6 +314,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> #endif
> #ifdef CONFIG_SPI_FLASH_XMC
> /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
> --
> 2.17.1
>
[PATCH v3] pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v2->v3
* Synced with Linux 5.9 instead of 5.8.
* Updated commit message.
v1->v2
* Updated commit message
* Synced with Linux 5.8 instead of 5.9.rc4
v1: https://patchwork.ozlabs.org/project/uboot/patch/
20200917150256.29721-1-prabhakar.mahadev-lad...@bp.renesas.com/
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 57 ++
1 file changed, 30 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index de22e49ebe..b13fc0ba63 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -217,8 +217,8 @@
#define IP2_11_8 FM(AVB_MDC) F_(0, 0)F_(0,
0)F_(0, 0)F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(BS_N)FM(PWM0_A)
FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0)
FM(TX3_C) F_(0, 0)FM(VI5_CLK_B) F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(RD_N)FM(PWM1_A)
FM(AVB_LINK)FM(VI4_FIELD) F_(0, 0)
FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A)
FM(AVB_AVTP_MATCH_A)FM(VI4_VSYNC_N) FM(TX5_B)
FM(SCK3_C) FM(PWM5_A) F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(EX_WAIT0)FM(SDA7_A)
FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B)
FM(PWM6_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A)
FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B)
FM(SCK3_C) FM(PWM5_A) F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(EX_WAIT0)FM(SDA7_A)
FM(AVB_AVTP_CAPTURE)FM(VI4_HSYNC_N) FM(RX5_B)
FM(PWM6_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A0) FM(IRQ0)
FM(PWM2_A) FM(MSIOF3_SS1_B)FM(VI5_CLK_A)
FM(DU_CDE) FM(HRX3_D) FM(IERX)FM(QSTB_QHE)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0FM(A1) FM(IRQ1)
FM(PWM3_A) FM(DU_DOTCLKIN1)FM(VI5_DATA0_A)
FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX)FM(QCPV_QDE)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4FM(A2) FM(IRQ2)
FM(AVB_AVTP_PPS)FM(VI4_CLKENB) FM(VI5_DATA1_A)
FM(DU_DISP) FM(SCL6_B) F_(0, 0)FM(QSTVB_QVE) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -433,6 +433,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28)
IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0),
FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */
/* 2 */ /* 3 */ /* 4 */
/* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL1_31FM(SEL_SIMCARD_0)
FM(SEL_SIMCARD_1)
+#define MOD_SEL1_30FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29FM(SEL_TIMER_TMU_0)
FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28FM(SEL_USB_20_CH0_0)
FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -453,7 +455,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28)
IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define PINMUX_MOD_SELS\
\
-MOD_SEL0_30_29 \
+ MOD_SEL1_31 \
+MOD_SEL0_30_29 MOD_SEL1_30 \
MOD_SEL1_29 \
MOD_SEL0_28MOD_SEL1_28 \
MOD_SEL0_27_26 \
@@ -619,7 +622,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
- PINMUX_IPSR_GPSR(IP2
[PATCH v3] i2c: rcar_i2c: Fix i2c read/write errors
commit 7c8f821e ("i2c: rcar_i2c: Set the slave address from
rcar_i2c_xfer") blindly called rcar_i2c_set_addr() with read argument
always set to 1 during xfer which introduced read/write errors, whereas
earlier rcar_i2c_read_common() called rcar_i2c_set_addr() with read set to
1 and rcar_i2c_write_common() called rcar_i2c_set_addr() with read set 0.
Fixes: 7c8f821e ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer")
Signed-off-by: Lad Prabhakar
---
v2->v3
* Made sure value of read is ether 0/1 as pointed by Marek
v1->v2
* Incorporated suggestion from Heiko
v1:
https://patchwork.ozlabs.org/project/uboot/patch/
20200921163353.5540-1-prabhakar.mahadev-lad...@bp.renesas.com/
Without this patch below errors are seen:
=> i2c probe
Valid chip addresses: 34 47 68
=> i2c md 0x47 0 100
Error reading the chip: -110
=> i2c mw 0x47 0x0a 0x06
Error writing the chip: -110
=>
---
drivers/i2c/rcar_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 4267bbfa5a..663c342cd8 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -211,7 +211,7 @@ static int rcar_i2c_xfer(struct udevice *dev, struct
i2c_msg *msg, int nmsgs)
int ret;
for (; nmsgs > 0; nmsgs--, msg++) {
- ret = rcar_i2c_set_addr(dev, msg->addr, 1);
+ ret = rcar_i2c_set_addr(dev, msg->addr, !!(msg->flags &
I2C_M_RD));
if (ret)
return ret;
--
2.17.1
Re: [PATCH v2] i2c: rcar_i2c: Fix i2c read/write errors
Hi Marek,
Thank you for the review.
On Wed, Sep 30, 2020 at 10:57 AM Marek Vasut wrote:
>
> On 9/30/20 11:16 AM, Lad Prabhakar wrote:
> [...]
> > diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
> > index 4267bbfa5a..e76201df6b 100644
> > --- a/drivers/i2c/rcar_i2c.c
> > +++ b/drivers/i2c/rcar_i2c.c
> > @@ -211,7 +211,7 @@ static int rcar_i2c_xfer(struct udevice *dev, struct
> > i2c_msg *msg, int nmsgs)
> > int ret;
> >
> > for (; nmsgs > 0; nmsgs--, msg++) {
> > - ret = rcar_i2c_set_addr(dev, msg->addr, 1);
> > + ret = rcar_i2c_set_addr(dev, msg->addr, msg->flags &
> > I2C_M_RD);
>
> Don't you need !!(msg->flags & I2C_M_RD) here ? There is
> 140 writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
> in rcar_i2c_set_addr(), so if I2C_M_RD is ever changed from 0x1 to
> anything else, this will fail.
>
Agreed will fix that and post a v3.
Cheers,
Prabhakar
[PATCH v2] i2c: rcar_i2c: Fix i2c read/write errors
commit 7c8f821e ("i2c: rcar_i2c: Set the slave address from
rcar_i2c_xfer"), blindly called rcar_i2c_set_addr() with read argument
always set to 1 during xfer which introduced read/write errors, whereas
earlier rcar_i2c_read_common() called rcar_i2c_set_addr() with read set to
1 and rcar_i2c_write_common() called rcar_i2c_set_addr() with read set 0.
Fixes: 7c8f821e ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer")
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2
* Incorporated suggestion from Heiko
v1:
https://patchwork.ozlabs.org/project/uboot/patch/
20200921163353.5540-1-prabhakar.mahadev-lad...@bp.renesas.com/
Without this patch below errors are seen:
=> i2c probe
Valid chip addresses: 34 47 68
=> i2c md 0x47 0 100
Error reading the chip: -110
=> i2c mw 0x47 0x0a 0x06
Error writing the chip: -110
=>
---
drivers/i2c/rcar_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 4267bbfa5a..e76201df6b 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -211,7 +211,7 @@ static int rcar_i2c_xfer(struct udevice *dev, struct
i2c_msg *msg, int nmsgs)
int ret;
for (; nmsgs > 0; nmsgs--, msg++) {
- ret = rcar_i2c_set_addr(dev, msg->addr, 1);
+ ret = rcar_i2c_set_addr(dev, msg->addr, msg->flags & I2C_M_RD);
if (ret)
return ret;
--
2.17.1
Re: [PATCH] Revert "i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer"
Hi Heiko,
Thank you for the review.
On Wed, Sep 30, 2020 at 8:18 AM Heiko Schocher wrote:
>
> Hello Lad,
>
> Am 21.09.2020 um 18:33 schrieb Lad Prabhakar:
> > This reverts commit 7c8f821e ("i2c: rcar_i2c: Set the
> > slave address from rcar_i2c_xfer"), as it blindly called
> > rcar_i2c_set_addr() with read argument always set to 1
> > during xfer which introduced read errors, whereas
> > earlier rcar_i2c_read_common() called rcar_i2c_set_addr()
> > with read set to 1 and rcar_i2c_write_common() called
> > rcar_i2c_set_addr() with read set 0.
> >
> > Signed-off-by: Lad Prabhakar
> > Reviewed-by: Biju Das
> > ---
> > drivers/i2c/rcar_i2c.c | 14 +-
> > 1 file changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
> > index 4267bbfa5a..75448c8368 100644
> > --- a/drivers/i2c/rcar_i2c.c
> > +++ b/drivers/i2c/rcar_i2c.c
> > @@ -162,6 +162,10 @@ static int rcar_i2c_read_common(struct udevice *dev,
> > struct i2c_msg *msg)
> > u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
> > int i, ret = -EREMOTEIO;
> >
> > + ret = rcar_i2c_set_addr(dev, msg->addr, 1);
> > + if (ret)
> > + return ret;
> > +
> > for (i = 0; i < msg->len; i++) {
> > if (msg->len - 1 == i)
> > icmcr |= RCAR_I2C_ICMCR_FSB;
> > @@ -188,6 +192,10 @@ static int rcar_i2c_write_common(struct udevice *dev,
> > struct i2c_msg *msg)
> > u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
> > int i, ret = -EREMOTEIO;
> >
> > + ret = rcar_i2c_set_addr(dev, msg->addr, 0);
> > + if (ret)
> > + return ret;
> > +
> > for (i = 0; i < msg->len; i++) {
> > writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
> > writel(icmcr, priv->base + RCAR_I2C_ICMCR);
> > @@ -211,10 +219,6 @@ static int rcar_i2c_xfer(struct udevice *dev, struct
> > i2c_msg *msg, int nmsgs)
> > int ret;
> >
> > for (; nmsgs > 0; nmsgs--, msg++) {
> > - ret = rcar_i2c_set_addr(dev, msg->addr, 1);
>
> Instead of reverting, can you do:
>
> rcar_i2c_set_addr(dev, msg->addr, msg->flags & I2C_M_RD);
>
Sure that too fixes the issue. I'll post a v2 soon.
Cheers,
Prabhakar
[PATCH] cmd: fat: Use do_save() for fatwrite
do_save() function defined in fs.c also supports FAT file system
re-use the same for fatwrite command.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
cmd/fat.c | 43 +--
1 file changed, 1 insertion(+), 42 deletions(-)
diff --git a/cmd/fat.c b/cmd/fat.c
index b438ce16c9..69ce1fa530 100644
--- a/cmd/fat.c
+++ b/cmd/fat.c
@@ -98,48 +98,7 @@ U_BOOT_CMD(
static int do_fat_fswrite(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- loff_t size;
- int ret;
- unsigned long addr;
- unsigned long count;
- long offset;
- struct blk_desc *dev_desc = NULL;
- struct disk_partition info;
- int dev = 0;
- int part = 1;
- void *buf;
-
- if (argc < 5)
- return cmd_usage(cmdtp);
-
- part = blk_get_device_part_str(argv[1], argv[2], _desc, , 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->devnum;
-
- if (fat_set_blk_dev(dev_desc, ) != 0) {
- printf("\n** Unable to use %s %d:%d for fatwrite **\n",
- argv[1], dev, part);
- return 1;
- }
- addr = simple_strtoul(argv[3], NULL, 16);
- count = (argc <= 5) ? 0 : simple_strtoul(argv[5], NULL, 16);
- /* offset should be a hex, but "-1" is allowed */
- offset = (argc <= 6) ? 0 : simple_strtol(argv[6], NULL, 16);
-
- buf = map_sysmem(addr, count);
- ret = file_fat_write(argv[4], buf, offset, count, );
- unmap_sysmem(buf);
- if (ret < 0) {
- printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
- argv[4], argv[1], dev, part);
- return 1;
- }
-
- printf("%llu bytes written\n", size);
-
- return 0;
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_FAT);
}
U_BOOT_CMD(
--
2.17.1
[PATCH 3/3] pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 1ca1334775..57ad1d116b 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -45,6 +45,7 @@ enum sh_pfc_model {
struct sh_pfc_pin_config {
u32 type;
+ const char *function_name;
};
struct sh_pfc_pinctrl {
@@ -449,6 +450,30 @@ static const char *sh_pfc_pinctrl_get_group_name(struct
udevice *dev,
return priv->pfc.info->groups[selector].name;
}
+static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
+unsigned int selector,
+char *buf, int size)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = >pmx;
+ struct sh_pfc *pfc = >pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin;
+ int idx;
+
+ pin = >pfc.info->pins[selector];
+ if (!pin) {
+ snprintf(buf, size, "Unknown");
+ return -EINVAL;
+ }
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = >configs[idx];
+ snprintf(buf, size, "%s", cfg->function_name);
+
+ return 0;
+}
+
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
@@ -496,6 +521,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev,
return ret;
cfg->type = PINMUX_TYPE_GPIO;
+ cfg->function_name = "gpio";
return 0;
}
@@ -525,6 +551,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev,
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
return 0;
}
@@ -548,6 +575,7 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
return ret;
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name = "function";
return 0;
}
@@ -582,6 +610,7 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
cfg = >configs[idx];
cfg->type = PINMUX_TYPE_FUNCTION;
+ cfg->function_name =
priv->pfc.info->groups[group_selector].name;
}
done:
@@ -788,6 +817,7 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
.get_group_name = sh_pfc_pinctrl_get_group_name,
+ .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
.get_functions_count= sh_pfc_pinctrl_get_functions_count,
.get_function_name = sh_pfc_pinctrl_get_function_name,
@@ -818,6 +848,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct
sh_pfc_pinctrl *pmx)
for (i = 0; i < pfc->info->nr_pins; ++i) {
struct sh_pfc_pin_config *cfg = >configs[i];
cfg->type = PINMUX_TYPE_NONE;
+ cfg->function_name = "none";
}
return 0;
--
2.17.1
[PATCH 0/3] pinctrl: renesas: trivial fixes and enhancements
Hi All, This patch series includes trivial fixes and enhancements to renesas pfc driver. Cheers, Prabhakar Lad Prabhakar (3): pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback drivers/pinctrl/renesas/pfc.c | 54 ++- 1 file changed, 47 insertions(+), 7 deletions(-) -- 2.17.1
[PATCH 1/3] pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl
Drop unused members from struct sh_pfc_pinctrl.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index f79dc411d8..6cccd33c40 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -51,10 +51,6 @@ struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
struct sh_pfc_pin_config *configs;
-
- const char *func_prop_name;
- const char *groups_prop_name;
- const char *pins_prop_name;
};
struct sh_pfc_pin_range {
--
2.17.1
[PATCH 2/3] pinctrl: renesas: Make sure the pin type is updated after setting the MUX
Update pin type after every successful call to sh_pfc_config_mux().
This fixes pin functionality from being overwritten.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 6cccd33c40..1ca1334775 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -538,11 +538,18 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev,
unsigned pin_selector,
const struct sh_pfc_pin *pin = >pfc.info->pins[pin_selector];
int idx = sh_pfc_get_pin_index(pfc, pin->pin);
struct sh_pfc_pin_config *cfg = >configs[idx];
+ int ret;
if (cfg->type != PINMUX_TYPE_NONE)
return -EBUSY;
- return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
+ if (ret)
+ return ret;
+
+ cfg->type = PINMUX_TYPE_FUNCTION;
+
+ return 0;
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned
group_selector,
@@ -552,12 +559,14 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
struct sh_pfc_pinctrl *pmx = >pmx;
struct sh_pfc *pfc = >pfc;
const struct sh_pfc_pin_group *grp =
>pfc.info->groups[group_selector];
+ struct sh_pfc_pin_config *cfg;
unsigned int i;
int ret = 0;
+ int idx;
for (i = 0; i < grp->nr_pins; ++i) {
- int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
- struct sh_pfc_pin_config *cfg = >configs[idx];
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
ret = -EBUSY;
@@ -569,6 +578,10 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev,
unsigned group_selector
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
+
+ idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+ cfg = >configs[idx];
+ cfg->type = PINMUX_TYPE_FUNCTION;
}
done:
--
2.17.1
[PATCH] spi: renesas_rpc_spi: Return -ENOTSUPP if bitlen cannot be handled during xfer
Return -ENOTSUPP if bitlen cannot be handled by the controller
during xfer.
This fixes board reset when sspi command is hit with no arguments
where bitlen is passed as 0.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/spi/renesas_rpc_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 9d9e767d87..c2ff5b157c 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -252,7 +252,7 @@ static int rpc_spi_xfer(struct udevice *dev, unsigned int
bitlen,
if (!priv->cmdstarted) {
if (!wlen || rlen)
- BUG();
+ return -ENOTSUPP;
memcpy(priv->cmdcopy, dout, wlen);
priv->cmdlen = wlen;
--
2.17.1
[PATCH] usb: xhci-rcar: Add support for R8A774A1 SoC
The R8A774A1 is compatible with the generic rcar-gen3-xhci controller.
This patch adds the compatibility flag, to support the xHCI controller.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/usb/host/xhci-rcar.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index 8fc51df3d1..5379dba566 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -146,6 +146,7 @@ static int xhci_rcar_ofdata_to_platdata(struct udevice *dev)
}
static const struct udevice_id xhci_rcar_ids[] = {
+ { .compatible = "renesas,rcar-gen3-xhci" },
{ .compatible = "renesas,xhci-r8a7795" },
{ .compatible = "renesas,xhci-r8a7796" },
{ .compatible = "renesas,xhci-r8a77965" },
--
2.17.1
[PATCH] Revert "i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer"
This reverts commit 7c8f821e ("i2c: rcar_i2c: Set the
slave address from rcar_i2c_xfer"), as it blindly called
rcar_i2c_set_addr() with read argument always set to 1
during xfer which introduced read errors, whereas
earlier rcar_i2c_read_common() called rcar_i2c_set_addr()
with read set to 1 and rcar_i2c_write_common() called
rcar_i2c_set_addr() with read set 0.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/i2c/rcar_i2c.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 4267bbfa5a..75448c8368 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -162,6 +162,10 @@ static int rcar_i2c_read_common(struct udevice *dev,
struct i2c_msg *msg)
u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
int i, ret = -EREMOTEIO;
+ ret = rcar_i2c_set_addr(dev, msg->addr, 1);
+ if (ret)
+ return ret;
+
for (i = 0; i < msg->len; i++) {
if (msg->len - 1 == i)
icmcr |= RCAR_I2C_ICMCR_FSB;
@@ -188,6 +192,10 @@ static int rcar_i2c_write_common(struct udevice *dev,
struct i2c_msg *msg)
u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
int i, ret = -EREMOTEIO;
+ ret = rcar_i2c_set_addr(dev, msg->addr, 0);
+ if (ret)
+ return ret;
+
for (i = 0; i < msg->len; i++) {
writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
writel(icmcr, priv->base + RCAR_I2C_ICMCR);
@@ -211,10 +219,6 @@ static int rcar_i2c_xfer(struct udevice *dev, struct
i2c_msg *msg, int nmsgs)
int ret;
for (; nmsgs > 0; nmsgs--, msg++) {
- ret = rcar_i2c_set_addr(dev, msg->addr, 1);
- if (ret)
- return ret;
-
if (msg->flags & I2C_M_RD)
ret = rcar_i2c_read_common(dev, msg);
else
@@ -224,7 +228,7 @@ static int rcar_i2c_xfer(struct udevice *dev, struct
i2c_msg *msg, int nmsgs)
return ret;
}
- return 0;
+ return ret;
}
static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
--
2.17.1
[PATCH v2] pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.8
Sync the R8A77990 SoC PFC tables with Linux 5.8 , commit bcf876870b95.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2
* Updated commit message
* Synced with Linux 5.8 instead of 5.9.rc4
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 57 ++
1 file changed, 30 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index de22e49ebe..b13fc0ba63 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -217,8 +217,8 @@
#define IP2_11_8 FM(AVB_MDC) F_(0, 0)F_(0,
0)F_(0, 0)F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(BS_N)FM(PWM0_A)
FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0)
FM(TX3_C) F_(0, 0)FM(VI5_CLK_B) F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(RD_N)FM(PWM1_A)
FM(AVB_LINK)FM(VI4_FIELD) F_(0, 0)
FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A)
FM(AVB_AVTP_MATCH_A)FM(VI4_VSYNC_N) FM(TX5_B)
FM(SCK3_C) FM(PWM5_A) F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(EX_WAIT0)FM(SDA7_A)
FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B)
FM(PWM6_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A)
FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B)
FM(SCK3_C) FM(PWM5_A) F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(EX_WAIT0)FM(SDA7_A)
FM(AVB_AVTP_CAPTURE)FM(VI4_HSYNC_N) FM(RX5_B)
FM(PWM6_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A0) FM(IRQ0)
FM(PWM2_A) FM(MSIOF3_SS1_B)FM(VI5_CLK_A)
FM(DU_CDE) FM(HRX3_D) FM(IERX)FM(QSTB_QHE)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0FM(A1) FM(IRQ1)
FM(PWM3_A) FM(DU_DOTCLKIN1)FM(VI5_DATA0_A)
FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX)FM(QCPV_QDE)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4FM(A2) FM(IRQ2)
FM(AVB_AVTP_PPS)FM(VI4_CLKENB) FM(VI5_DATA1_A)
FM(DU_DISP) FM(SCL6_B) F_(0, 0)FM(QSTVB_QVE) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -433,6 +433,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28)
IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0),
FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */
/* 2 */ /* 3 */ /* 4 */
/* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL1_31FM(SEL_SIMCARD_0)
FM(SEL_SIMCARD_1)
+#define MOD_SEL1_30FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29FM(SEL_TIMER_TMU_0)
FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28FM(SEL_USB_20_CH0_0)
FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -453,7 +455,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28)
IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define PINMUX_MOD_SELS\
\
-MOD_SEL0_30_29 \
+ MOD_SEL1_31 \
+MOD_SEL0_30_29 MOD_SEL1_30 \
MOD_SEL1_29 \
MOD_SEL0_28MOD_SEL1_28 \
MOD_SEL0_27_26 \
@@ -619,7 +622,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
- PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
+ PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
PINMUX_IPSR_GPSR(IP2_23
[PATCH] pinctrl: renesas: pfc-r8a77990: Import PFC table
Sync the R8A77990 SoC PFC with mainline linux 5.9-rc4 commit
f4d51dffc6c0 ("Linux 5.9-rc4")
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 57 ++
1 file changed, 30 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index de22e49ebe..b13fc0ba63 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -217,8 +217,8 @@
#define IP2_11_8 FM(AVB_MDC) F_(0, 0)F_(0,
0)F_(0, 0)F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(BS_N)FM(PWM0_A)
FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0)
FM(TX3_C) F_(0, 0)FM(VI5_CLK_B) F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(RD_N)FM(PWM1_A)
FM(AVB_LINK)FM(VI4_FIELD) F_(0, 0)
FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A)
FM(AVB_AVTP_MATCH_A)FM(VI4_VSYNC_N) FM(TX5_B)
FM(SCK3_C) FM(PWM5_A) F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(EX_WAIT0)FM(SDA7_A)
FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B)
FM(PWM6_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A)
FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B)
FM(SCK3_C) FM(PWM5_A) F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(EX_WAIT0)FM(SDA7_A)
FM(AVB_AVTP_CAPTURE)FM(VI4_HSYNC_N) FM(RX5_B)
FM(PWM6_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A0) FM(IRQ0)
FM(PWM2_A) FM(MSIOF3_SS1_B)FM(VI5_CLK_A)
FM(DU_CDE) FM(HRX3_D) FM(IERX)FM(QSTB_QHE)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0FM(A1) FM(IRQ1)
FM(PWM3_A) FM(DU_DOTCLKIN1)FM(VI5_DATA0_A)
FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX)FM(QCPV_QDE)F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4FM(A2) FM(IRQ2)
FM(AVB_AVTP_PPS)FM(VI4_CLKENB) FM(VI5_DATA1_A)
FM(DU_DISP) FM(SCL6_B) F_(0, 0)FM(QSTVB_QVE) F_(0, 0) F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -433,6 +433,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28)
IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0),
FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */
/* 2 */ /* 3 */ /* 4 */
/* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL1_31FM(SEL_SIMCARD_0)
FM(SEL_SIMCARD_1)
+#define MOD_SEL1_30FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29FM(SEL_TIMER_TMU_0)
FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28FM(SEL_USB_20_CH0_0)
FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -453,7 +455,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28)
IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define PINMUX_MOD_SELS\
\
-MOD_SEL0_30_29 \
+ MOD_SEL1_31 \
+MOD_SEL0_30_29 MOD_SEL1_30 \
MOD_SEL1_29 \
MOD_SEL0_28MOD_SEL1_28 \
MOD_SEL0_27_26 \
@@ -619,7 +622,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
- PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
+ PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
PINMUX_IPSR_MSEL
[PATCH] board: renesas: ebisu: Drop CA57 check in reset_cpu()
Renesas Ebisu board is based on R-Car E3 SoC which has dual CA53 and
a CR7.
This patch drops check for cputype from reset_cpu() and also drops the
corresponding CA57 macros. While at it also dropped RST_RSTOUTCR macro
which is unused.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
board/renesas/ebisu/ebisu.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
index d164a36361..b6531f61ed 100644
--- a/board/renesas/ebisu/ebisu.c
+++ b/board/renesas/ebisu/ebisu.c
@@ -47,23 +47,10 @@ int board_init(void)
}
#define RST_BASE 0xE616
-#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(ulong addr)
{
- unsigned long midr, cputype;
-
- asm volatile("mrs %0, midr_el1" : "=r" (midr));
- cputype = (midr >> 4) & 0xfff;
-
- if (cputype == 0xd03)
- writel(RST_CA53_CODE, RST_CA53RESCNT);
- else if (cputype == 0xd07)
- writel(RST_CA57_CODE, RST_CA57RESCNT);
- else
- hang();
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
}
--
2.17.1
[PATCH] mtd: spi-nor-ids: Add Winbond W25M512JV flash entry
Add Winbond W25M512JV flash device description.
Linux already has the flash entry present. A snippet below:
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...},
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 114ebacde1..4ed997706a 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -314,6 +314,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_XMC
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
--
2.17.1
[U-Boot] [PATCH v2] spi: zynq_spi: Fix infinite looping while xfer
From: "Lad, Prabhakar" <prabhakar.cse...@gmail.com>
During spi transfer, for example:
sspi 1:1.0 8 ff
the rx_len values will be:
rx_len = 0
rx_len = 4294967295
This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo
Signed-off-by: Lad, Prabhakar <prabhakar.cse...@gmail.com>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva...@xilinx.com>
Cc: Jagan Teki <jt...@openedev.com>
---
Changes for v2: None
drivers/spi/zynq_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 09ae1be..dd3de27 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -230,7 +230,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int
bitlen,
/* Read the data from RX FIFO */
status = readl(>isr);
- while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
+ while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
buf = readl(>rxdr);
if (rx_buf)
*rx_buf++ = buf;
--
1.9.1
___
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Re: [U-Boot] [PATCH] spi: zynq_spi: Fix infinite looping while xfer
On Sat, Jul 23, 2016 at 5:19 PM, Jagan Teki <jagannadh.t...@gmail.com> wrote:
>
> On 23 June 2016 at 19:28, Lad, Prabhakar <prabhakar.cse...@gmail.com> wrote:
> > During spi transfer, for example:
> > sspi 1:1.0 8 ff
> >
> > the rx_len values will be:
> > rx_len = 0
> > rx_len = 4294967295
> >
> > This caused a busy looping during xfer, this patch fixes it
> > by adding a check while reading the rx fifo
> >
> > Signed-off-by: Lad, Prabhakar <prabhakar@racelogic.co.uk>
> > Cc: Michal Simek <michal.si...@xilinx.com>
> > Cc: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> > Cc: Jagan Teki <jt...@openedev.com>
> > ---
> > drivers/spi/zynq_spi.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
> > index 09ae1be..dd3de27 100644
> > --- a/drivers/spi/zynq_spi.c
> > +++ b/drivers/spi/zynq_spi.c
> > @@ -230,7 +230,7 @@ static int zynq_spi_xfer(struct udevice *dev,
> > unsigned int bitlen,
> >
> > /* Read the data from RX FIFO */
> > status = readl(>isr);
> > -while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
> > +while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
>
> Do post-decrement directly on while.
>
Its the matter of taste, I usually prefer minimal changes.
Anyway above in the function tx_len isnt done in while
just keeping it consistent.
Cheers,
--Prabhakar Lad
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Re: [U-Boot] [PATCH] spi: zynq_spi: Fix infinite looping while xfer
On Thu, Jul 21, 2016 at 7:58 AM, Jagan Teki <jagannadh.t...@gmail.com> wrote: > On 23 June 2016 at 19:28, Lad, Prabhakar <prabhakar.cse...@gmail.com> wrote: >> During spi transfer, for example: >> sspi 1:1.0 8 ff >> >> the rx_len values will be: >> rx_len = 0 >> rx_len = 4294967295 > > Does these number during 'sspi' or during data transfer? why rx_len is > 4294967295? > As mentioned in the commit, if you run the command 'sspi 1:1.0 8 ff' It just keeps busy looping. Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: zynq_spi: Fix infinite looping while xfer
On Thu, Jun 23, 2016 at 2:58 PM, Lad, Prabhakar <prabhakar.cse...@gmail.com> wrote: > During spi transfer, for example: > sspi 1:1.0 8 ff > > the rx_len values will be: > rx_len = 0 > rx_len = 4294967295 > > This caused a busy looping during xfer, this patch fixes it > by adding a check while reading the rx fifo > Gentle ping.. Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] spi: zynq_spi: Fix infinite looping while xfer
During spi transfer, for example:
sspi 1:1.0 8 ff
the rx_len values will be:
rx_len = 0
rx_len = 4294967295
This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo
Signed-off-by: Lad, Prabhakar <prabhakar@racelogic.co.uk>
Cc: Michal Simek <michal.si...@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva...@xilinx.com>
Cc: Jagan Teki <jt...@openedev.com>
---
drivers/spi/zynq_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 09ae1be..dd3de27 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -230,7 +230,7 @@ static int zynq_spi_xfer(struct udevice *dev,
unsigned int bitlen,
/* Read the data from RX FIFO */
status = readl(>isr);
-while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
+while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
buf = readl(>rxdr);
if (rx_buf)
*rx_buf++ = buf;
--
2.1.4
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Re: [U-Boot] Adding SPI slave devices To DM
Hi Simon, On Sat, May 14, 2016 at 8:34 PM, Simon Glass <s...@chromium.org> wrote: > Hi, > > On 13 May 2016 at 10:58, Lad, Prabhakar <prabhakar.cse...@gmail.com> wrote: >> >> Hello All, >> >> It's quite a long time, since I touched u-boot code, I was working on >> adding a slave SPI device to DM, can anyone point me to a sample >> driver. > > I think you mean a device that uses SPI, so you could try cro_ec_spi.c > or tpm_tis_st33zp24_spi.c. > Thanks for the pointers. My intention was, to use sspi command, just to power up the LCD, but since there is no slave driver for it in the u-boot source, the device didnt populate as I am using devicetree. So would it be good to have spidev driver in u-boot as well ? Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Adding SPI slave devices To DM
Hello All, It's quite a long time, since I touched u-boot code, I was working on adding a slave SPI device to DM, can anyone point me to a sample driver. Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] spidev in FDT
Hello, I have a display connected to spi-1, there is no driver for display, we want to use sspi commands to program the display. since there isnt any device node to spi-1 connected and when issued with sspi commands it returns with invalid device 1:0 Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] sspi on xilinx
Hi Jagannadha, I am working on the zynq board, we have spi0 connected to flash chip, which works fine. The spi1 is connected to display we want to use sspi command to power up the display. I have enabled, the CONFIG_SPI command, but when I use the sspi command I get tx timeouts. Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TI8148 EVM
Hi Tom, Thanks for the quick reply. On Thu, Oct 22, 2015 at 12:22 PM, Tom Rini <tr...@konsulko.com> wrote: > On Thu, Oct 22, 2015 at 12:12:32PM +0100, Lad, Prabhakar wrote: > >> Copy the MLO and u-boot.bin to SD card boot partition which is >> bootable, I see no prints coming from the 1st stage bootlaoder, cant >> debug it as I don’t have access to JTAG. >> >> Any pointers is this code tested ? > > First, you need to use u-boot.img not u-boot.bin. Second, which PG do > you have on the board? We only have support for PG1.0 today and not > PG2.0 as Matt did the initial bring-up and only has a PG1.0 board. The > code should be easily ported from the old PSP tree to support PG2.0 > however. > I tried this on PG2.0, PG1.0 should also be handy. Regarding u-boot.img, just copying this should work or also MLO needs to be copied ? Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] TI8148 EVM
Hi Tom, I was trying the latest master branch for ti8148 evm to boot from SD card, following are the steps which I followed: 1: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- clean distclean 2: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- ti814x_evm_config 3: make ARCH=arm CROSS_COMPILE=arm-cortex_a8-linux-gnueabi- Copy the MLO and u-boot.bin to SD card boot partition which is bootable, I see no prints coming from the 1st stage bootlaoder, cant debug it as I don’t have access to JTAG. Any pointers is this code tested ? Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] ARM: remove non-generic boards.
Hi Masahiro, On Wed, Apr 8, 2015 at 10:15 AM, Masahiro Yamada yamada.masah...@socionext.com wrote: In spite of several times alerts, there are still many boards left unconverted. This series removes some of non-generic (=unmaitained) boards. If there is a problem with this series, please speak up! Masahiro Yamada (3): ARM: at91: remove non-generic boards ARM: davinci: remove non-generic boards ARM: omap3: remove non-generic boards arch/arm/cpu/armv7/omap3/Kconfig | 21 - arch/arm/mach-at91/Kconfig | 15 - arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c |2 +- arch/arm/mach-davinci/Kconfig | 37 - arch/arm/mach-davinci/Makefile |5 - arch/arm/mach-davinci/cpu.c| 54 - arch/arm/mach-davinci/dm355.c | 30 - arch/arm/mach-davinci/dm365.c | 20 - arch/arm/mach-davinci/dm365_lowlevel.c | 460 I have a DM365 evm I can take care of it, so no need to drop it. arch/arm/mach-davinci/dm644x.c | 81 -- arch/arm/mach-davinci/dm646x.c | 26 - arch/arm/mach-davinci/include/mach/aintc_defs.h| 36 - arch/arm/mach-davinci/include/mach/emac_defs.h | 25 +- arch/arm/mach-davinci/include/mach/gpio.h |5 +- arch/arm/mach-davinci/include/mach/hardware.h | 61 -- arch/arm/mach-davinci/include/mach/psc_defs.h | 70 -- arch/arm/mach-davinci/include/mach/syscfg_defs.h | 50 - arch/arm/mach-davinci/lowlevel_init.S | 664 arch/arm/mach-davinci/psc.c| 63 -- Removing this will cause build failures for da850. Cheers, --Prabhakar Lad ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] include/mmc.h: Remove declaration for spl_mmc_load()
From: Lad, Prabhakar prabhakar.cse...@gmail.com The spl_mmc_load() was removed while converting to CONFIG_SPL_FRAMEWORK usage the definition was removed but the declaration was missed. This patch removes this declaration. Signed-off-by: Lad, Prabhakar prabhakar.cse...@gmail.com --- include/mmc.h |1 - 1 file changed, 1 deletion(-) diff --git a/include/mmc.h b/include/mmc.h index cb558da..8f51c93 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -304,7 +304,6 @@ int board_mmc_getcd(struct mmc *mmc); int mmc_switch_part(int dev_num, unsigned int part_num); int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); -void spl_mmc_load(void) __noreturn; /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Board-specific commands unintentionally linked into SPL?
Hi Tyler/Christian, On Fri, Jul 27, 2012 at 00:24:20, Tyler Olmstead wrote: Hi Christian, On Thu, Jul 26, 2012 at 10:03 AM, Christian Riesch christian.rie...@omicron.at wrote: [cc'd Prabhakar Lad, Tom Rini, and Scott Wood] Tyler, On Thu, Jul 26, 2012 at 5:37 PM, Tyler Olmstead tyler.j.olmst...@gmail.com wrote: Hi all, I have encountered some issues adding a board-specific command to the board file of a project I have been working on. Specifically, after adding a U-Boot shell command to my board file, I have been seeing link-stage failures when attempting to build SPL. It's hard to tell without having your code, but I think this problem was already discussed in [1]. However I do not remember how Prabhakar solved it in the end. #ifndef CONFIG_SPL_BUILD solved my problem. Thx, --Prabhakar Lad Yes, I ran into this thread while debugging the problem, which ultimately lead me to my solution. From that same thread [1], Wolfgang Denk writes: quote *I want to add a command using U_BOOT_CMD in uboot, where SPL_BUILD is enabled for example for da850evm in spl frame work how can i do that * This makes no sense. Commands can only be executed when we have full U-Boot running (actually even only after relocation). You cannot run commands in the SPL. /quote I understand of course why it makes no sense to have command support in the SPL. However, the crux of this problem is that U-Boot and SPL both link in the same board object file, so in that sense compile-time switches wont work. From later in [1], Scott Wood writes: quote Maybe we should poke command.h to nop out U_BOOT_CMD for CONFIG_SPL_BUILD? OTOH, #ifndef'ing U_BOOT_CMD and the code itself gets us a space savings we wouldn't get otherwise (I suspect giving the MTD/NAND issue I've mentioned before)... Commands should be stripped out already with the new SPL -- that's what the (unfortunately uncommented) sed command in GEN_UBOOT appears to be doing. -Scott /quote Unfortunately, this is incorrect. From the ld man page [2]: -u symbol --undefined=symbol Force symbol to be entered in the output file as an undefined symbol. Doing this may, for example, trigger linking of additional modules from standard libraries. -u may be repeated with different option arguments to enter additional undefined symbols. This option is equivalent to the EXTERN linker script command. Which means that the sed command in GEN_UBOOT in the SPL makefile actually forces the *inclusion* of the command table, and therefore forces the resolution of any undefined symbols in the command function (hence my problem). This same command also appears in the top-level U-Boot makefile, and I find it likely that it was included in the SPL makefile as the result of a copy-paste error. This problem would only arise for commands in object files that are linked into the SPL image, such as the board file. -- Tyler [2] http://unixhelp.ed.ac.uk/CGI/man-cgi?ld In [1] I suggested to put an #ifndef CONFIG_SPL_BUILD U_BOOT_CMD( ... ); #endif around the command definition in the board file. But also other solutions were discussed in that thread, please have a look. Regards, Christian [1] http://marc.info/?t=13274854893 snip UNDEF_SYM=`arm-arago-linux-gnueabi-objdump -x /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/arch/arm/cpu/arm926ejs/davinci/libdavinci.o /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/arch/arm/cpu/arm926ejs/libarm926ejs.o /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/arch/arm/lib/libarm.o /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/board/davinci/da8xxevm/libda8xxevm.o /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/drivers/mtd/nand/libnand.o /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/drivers/serial/libserial.o /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/lib/libgeneric.o | sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`; cd /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/ arm-arago-linux-gnueabi-ld -T /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/u-boot-spl.lds --gc-sections -Bstatic -Ttext 0xc108 $UNDEF_SYM arch/arm/cpu/arm926ejs/start.o --start-group arch/arm/cpu/arm926ejs/davinci/libdavinci.o arch/arm/cpu/arm926ejs/libarm926ejs.o arch/arm/lib/libarm.o board/davinci/da8xxevm/libda8xxevm.o drivers/mtd/nand/libnand.o drivers/serial/libserial.o lib/libgeneric.o --end-group /home/tolmstead/tolmstead_lab-OptiPlex-380/uboot/uboot_nand/spl/arch/arm/lib/eabi_compat.o -L /usr/local/ti-sdk-am180x-evm/linux-devkit/bin/../lib/gcc/arm-arago-linux-gnueabi/4.3.3 -lgcc -Map u-boot-spl.map -o u-boot-spl board/davinci/da8xxevm/libda8xxevm.o: In function `do_mycmd':
Re: [U-Boot] [PATCH] Davinci: Utility for MMC boot
Hi Wolfgang,
On Wed, Jun 27, 2012 at 03:12:07, Wolfgang Denk wrote:
Dear Prabhakar Lad,
In message 1340708826-26707-1-git-send-email-prabhakar@ti.com you wrote:
From: Alagu Sankar alagusan...@embwise.com
This is a Linux command line tool specific to TI's Davinci platforms, for
flashing UBL (User Boot Loader), u-boot and u-boot Environment in the MMC/SD
card. This MMC/SD card can be used for booting Davinci platforms that
supports
MMC/SD boot option.
Do we also build UBL as part of the U-Boot source tree?
No, we do not build UBL as part of U-Boot.
If not, then why is this tool supposed to be part of the U-Boot tree?
How does this work with a SPL?
This command has options to flash u-boot images to MMC/SD card. When SPL
is supported, this command can be used to flash the single SPL image to
MMC/SD card.
--- a/Makefile
+++ b/Makefile
@@ -726,7 +726,7 @@ clean:
@rm -f $(obj)examples/api/demo{,.bin}
@rm -f $(obj)tools/bmp_logo$(obj)tools/easylogo/easylogo \
$(obj)tools/env/{fw_printenv,fw_setenv}\
- $(obj)tools/envcrc \
+ $(obj)tools/envcrc $(obj)tools/uflash/uflash \
$(obj)tools/gdb/{astest,gdbcont,gdbsend} \
$(obj)tools/gen_eth_addr$(obj)tools/img2srec \
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
Please keep list sorted.
Ok.
+e. Using the 'uflash' utility, place the UBL and u-uoot binaries on the MMC
+ card. Copy the u-boot.bin to tools/uflash directory
Why is this copy operation needed?
This copy is not needed as long as the path to u-boot.bin is specified
Correctly in command line.
And where is the UBL binary coming from?
UBL binary is optional. We can flash only u-boot.bin.
diff --git a/tools/uflash/config.txt b/tools/uflash/config.txt
new file mode 100644
index 000..f6acb22
--- /dev/null
+++ b/tools/uflash/config.txt
@@ -0,0 +1,11 @@
+bootargs=console=ttyS0,115200n8 root=/dev/mmcblk0p1 rootwait
rootfstype=ext3 rw
+bootcmd=ext2load mmc 0 0x8070 boot/uImage; bootm 0x8070
+bootdelay=1
+baudrate=115200
+bootfile=uImage
+stdin=serial
+stdout=serial
+stderr=serial
+ethact=dm9000
+videostd=ntsc
This looks like U-Boot environment settings? Why are these in the
tools/uflash/ directory? I would expect these are board specific?
For example, what in case a board uses a different baud rate?
Is this really supposed to be board independent? It doesn't look
so...
I agree with this. Can you think of any other scenario?
+
And please, no trailing empty lines!
Ok.
...
+ if (!strcmp(platform, DM3XX)) {
+ if (!uboot_load_address)
+ uboot_load_address = DM3XX_UBOOT_LOAD_ADDRESS;
+ if (!uboot_entry_point)
+ uboot_entry_point = DM3XX_UBOOT_LOAD_ADDRESS;
+ }
+
+ if (!strcmp(platform, OMAPL138)) {
+ if (!uboot_load_address)
+ uboot_load_address = DA850_UBOOT_LOAD_ADDRESS;
+ if (!uboot_entry_point)
+ uboot_entry_point = DA850_UBOOT_LOAD_ADDRESS;
+ }
So this is actually all hardwired for a few very specific board
configurations, right?
Yes.
.
+static int get_file_size(char *fname)
+{
+ FILE *fp;
+ int size;
+
+ fp = fopen(fname, rb);
+ if (fp == NULL) {
+ fprintf(stdout, File %s Open Error : %s\n,
+ fname, strerror(errno));
+ return -1;
+ }
+
+ fseek(fp, 0, SEEK_END);
+ size = ftell(fp);
+ fclose(fp);
Why not simply using stat() ?
Yes that makes sense.
+static int write_file(int devfd, char *fname)
+{
+ FILE *fp;
+ int readlen, writelen;
+
+ fp = fopen(fname, rb);
+ if (fp == NULL) {
+ fprintf(stderr, File %s Open Error: %s,
+ fname, strerror(errno));
+ return -1;
+ }
+
+ while ((readlen = fread(readbuf, 1, BLOCK_SIZE, fp)) 0) {
+ if (readlen BLOCK_SIZE)
+ memset(readbuf[readlen], 0, BLOCK_SIZE-readlen);
+
+ writelen = write(devfd, readbuf, BLOCK_SIZE);
+ if (writelen BLOCK_SIZE) {
+ close(devfd);
+ return -1;
+ }
+ }
+
+ fclose(fp);
You don't even print a warning or error message in case of read
errors? Ouch...
Ok , I'll fix it in V2 version.
Thx,
--Prabhakar Lad
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
C makes it easy for you to shoot yourself in the foot. C++ makes that
Re: [U-Boot] [PATCH v2 3/7] da850/omap-l138: Add support to read u-boot image from MMC/SD
Hi Christian, On Wed, Jun 20, 2012 at 14:50:41, Christian Riesch wrote: Hi Prabhakar, On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar prabhakar@ti.com wrote: Hi Christian, On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote: Hi, Sorry for the delay, had a lot of other work to do :-/ On Thursday, June 7, 2012, Prabhakar Lad wrote: From: Lad, Prabhakar prabhakar@ti.com javascript:; DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will be in SPI flash and U-Boot image will be in MMC/SD card. SPL will do the low level initialization and then loads the u-boot image from MMC/SD card. Define the CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138 configuration file to enable this feature. Signed-off-by: Lad, Prabhakar prabhakar@ti.com javascript:; Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com javascript:; Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com javascript:; --- arch/arm/cpu/arm926ejs/davinci/spl.c | 12 ++- drivers/mmc/Makefile | 4 ++ drivers/mmc/spl_mmc_load.c | 62 ++ include/configs/da850evm.h | 8 include/mmc.h | 2 + 5 files changed, 87 insertions(+), 1 deletions(-) create mode 100644 drivers/mmc/spl_mmc_load.c diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index 74632e5..be397ce 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -28,6 +28,11 @@ #include ns16550.h #include malloc.h #include spi_flash.h +#include mmc.h +#include fat.h +#include version.h +#include asm/arch/davinci_misc.h +#include asm/arch/pinmux_defs.h #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -91,6 +96,11 @@ void board_init_r(gd_t *id, ulong dummy) gd-have_console = 1; puts(SPI boot...\n); +#ifdef CONFIG_SPL_MMC_LOAD + spl_mmc_load(); +#else spi_boot(); -#endif Hmm, now the code prints SPI boot and then it boots from MMC, right? Please output correct messages. Ok The board is booted up in SPI boot mode only, ie the SPL is loaded from SPI flash itself and finally when low level initialization is completed The SPL loads the U-boot image in MMC/SD card when CONFIG_SPL_MMC_LOAD Config is defined. If CONFIG_SPL_MMC_LOAD is not defined by default the SPL loads the U-boot image from SPI flash itself. Yes, but your code prints SPI boot for both cases, doesn't it? +#endif /* CONFIG_SPL_MMC_LOAD */ + +#endif /* CONFIG_SPL_SPI_LOAD */ So, CONFIG_SPL_SPI_LOAD must be defined to boot from MMC?? Ths does not make sense to me. No not to boot from MMC, its indicating to SPL which is flashed in SPI flash to load the U-boot image(u-boot.bin) from MMC. Yes, but your code requires both CONFIG_SPL_MMC_LOAD and CONFIG_SPL_SPI_LOAD to be defined to load u-boot from MMC, right? This is confusing. Of course SPL itself is loaded from SPI flash in both cases, but this does not matter here, since the SPL has already loaded to the internal SRAM of the SoC by the ROM bootloader of the chip. The SPL could have been loaded from some other kind of memory (or UART) as well and would not know the difference. Ok I'll use CONFIG_SPL_MMC_LOAD while loading from MMC. I'll incorporate These changes for v3. Thx, --Prabhakar Lad Regards, Christian Thx, --Prabhakar Lad Regards, Christian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/7] da850/omap-l138: Add support to read u-boot image from MMC/SD
Hi Christian, On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote: Hi, Sorry for the delay, had a lot of other work to do :-/ On Thursday, June 7, 2012, Prabhakar Lad wrote: From: Lad, Prabhakar prabhakar@ti.com javascript:; DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will be in SPI flash and U-Boot image will be in MMC/SD card. SPL will do the low level initialization and then loads the u-boot image from MMC/SD card. Define the CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138 configuration file to enable this feature. Signed-off-by: Lad, Prabhakar prabhakar@ti.com javascript:; Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com javascript:; Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com javascript:; --- arch/arm/cpu/arm926ejs/davinci/spl.c | 12 ++- drivers/mmc/Makefile |4 ++ drivers/mmc/spl_mmc_load.c | 62 ++ include/configs/da850evm.h |8 include/mmc.h|2 + 5 files changed, 87 insertions(+), 1 deletions(-) create mode 100644 drivers/mmc/spl_mmc_load.c diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index 74632e5..be397ce 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -28,6 +28,11 @@ #include ns16550.h #include malloc.h #include spi_flash.h +#include mmc.h +#include fat.h +#include version.h +#include asm/arch/davinci_misc.h +#include asm/arch/pinmux_defs.h #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -91,6 +96,11 @@ void board_init_r(gd_t *id, ulong dummy) gd-have_console = 1; puts(SPI boot...\n); +#ifdef CONFIG_SPL_MMC_LOAD + spl_mmc_load(); +#else spi_boot(); -#endif Hmm, now the code prints SPI boot and then it boots from MMC, right? Please output correct messages. The board is booted up in SPI boot mode only, ie the SPL is loaded from SPI flash itself and finally when low level initialization is completed The SPL loads the U-boot image in MMC/SD card when CONFIG_SPL_MMC_LOAD Config is defined. If CONFIG_SPL_MMC_LOAD is not defined by default the SPL loads the U-boot image from SPI flash itself. +#endif /* CONFIG_SPL_MMC_LOAD */ + +#endif /* CONFIG_SPL_SPI_LOAD */ So, CONFIG_SPL_SPI_LOAD must be defined to boot from MMC?? Ths does not make sense to me. No not to boot from MMC, its indicating to SPL which is flashed in SPI flash to load the U-boot image(u-boot.bin) from MMC. Thx, --Prabhakar Lad Regards, Christian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Eric, On Wed, Jun 06, 2012 at 22:47:46, Eric Bénard wrote: Hi Prabhakar, Le Fri, 1 Jun 2012 19:04:37 +0530, Prabhakar Lad prabhakar@ti.com a écrit : From: Rajashekhara, Sudhakar sudhakar@ti.com On DA850/OMAP-L138 it was observed that in RMII mode, auto negotiation was not performed. This patch enables auto negotiation in RMII mode. Without this patch, EMAC initialization takes more time and sometimes tftp fails in RMII mode. Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com Tested-by: Eric Bénard e...@eukrea.com on an AM1808 with a RMII PHY where tftp was nearly always failing. This patch had some build warnings which has been fixed in v2 version (http://www.mail-archive.com/u-boot@lists.denx.de/msg85270.html) can you test this patch and Ack it. Thx, --Prabhakar Lad Eric ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] da850/omap-l138: Add MMC support for DA850/OMAP-L138
Hi Tom, On Tue, Jun 05, 2012 at 03:58:03, Rini, Tom wrote: On Fri, Jun 01, 2012 at 08:00:43PM +0530, Prabhakar Lad wrote: From: Lad, Prabhakar prabhakar@ti.com This patch adds support for MMC/SD on DA850/OMAP-L138. [snip] +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_DAVINCI_MMC_SD1 +#define CONFIG_MMC_MBLOCK CONFIG_MMC_MBLOCK isn't used anywhere in code, remove it please. Ok. +#define CONFIG_GENERIC_MMC +#define CONFIG_DAVINCI_MMC + +#ifdef CONFIG_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +#endif I'm not a fan of #define FOO, then checking right away for #ifdef FOO. Just add a comment about these only been needed when you have MMC support so it's clear to folks working from this as a template for their custom board they can remove it. Ok I'll add a comment over here. Thx, --Prabhakar Lad -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Tom, On Tue, Jun 05, 2012 at 03:59:08, Rini, Tom wrote: On Fri, Jun 01, 2012 at 07:04:37PM +0530, Prabhakar Lad wrote: From: Rajashekhara, Sudhakar sudhakar@ti.com On DA850/OMAP-L138 it was observed that in RMII mode, auto negotiation was not performed. This patch enables auto negotiation in RMII mode. Without this patch, EMAC initialization takes more time and sometimes tftp fails in RMII mode. Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com --- drivers/net/davinci_emac.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index fbd0f1b..9bbd625 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -895,5 +895,10 @@ int davinci_emac_initialize(void) miiphy_register(phy[i].name, davinci_mii_phy_read, davinci_mii_phy_write); } + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + gen_auto_negotiate(active_phy_addr); +#endif Why not just check on CONFIG_DRIVER_TI_EMAC_USE_RMII ? Would it be harmful to try and re-auto negotiate on some RMII hardware that already did it? Some of the phy's might not support auto negotiation, Not sure what will be the behavior on these phy's on enabling auto negotiation. So as to avoid this case this check is added. Thx, --Prabhakar Lad -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] da850/omap-l138: add support for direct NOR boot mode
Hi Tom, On Tue, Jun 05, 2012 at 04:02:01, Rini, Tom wrote: On Fri, Jun 01, 2012 at 08:00:49PM +0530, Prabhakar Lad wrote: From: Lad, Prabhakar prabhakar@ti.com This patch adds support for direct NOR boot mode on da850/omap-l138. Define the CONFIG_DIRECT_NOR_BOOT macro along with CONFIG_USE_NOR in the DA850/OMAP-L138 configuration file to enable this feature. We should be using boards.cfg to add additional build targets that will toggle CONFIG_DIRECT_NOR_BOOT and other cases where we can't have SW that works in conflicting cases. Ok I'll add a new entry in boards.cfg. Thx, --Prabhakar Lad -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] da850/omap-l138: Add MMC support for DA850/OMAP-L138
Hi Christian,
On Tue, Jun 05, 2012 at 15:33:07, Christian Riesch wrote:
Hi,
On Fri, Jun 1, 2012 at 4:30 PM, Prabhakar Lad prabhakar@ti.com wrote:
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for MMC/SD on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c | 13 ++
arch/arm/include/asm/arch-davinci/hardware.h | 1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h | 3 ++
board/davinci/da8xxevm/da850evm.c | 28
+++
include/configs/da850evm.h | 14 +++
5 files changed, 59 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..a95e419 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -169,3 +169,16 @@ const struct pinmux_config emifa_pins_nor[] = {
{ pinmux(12), 1, 6 }, /* EMA_A[1] */
{ pinmux(12), 1, 7 }, /* EMA_A[0] */
};
+
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+ /* GP0[11] is required for SD to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
Please move GP0[11] to the board specific file, e.g., add it to static
const struct pinmux_config gpio_pins[] in
board/davinci/da8xxevm/da850evm.c. Other boards might use other (or
no) GPIOs for this purpose...
Ok.
Thx,
--Prabhakar Lad
+ { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
+ { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
+ { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
+ { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
+ { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
+ { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
+ /* DA850 supports only 4-bit mode, remaining pins are not
configured */
+};
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..f6b7a2c 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -446,6 +446,7 @@ struct davinci_pllc_regs {
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */
enum davinci_clk_ids {
+ DAVINCI_MMCSD_CLKID = 2,
DAVINCI_SPI0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..c9ac697 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -48,4 +48,7 @@ extern const struct pinmux_config emifa_pins_cs4[1];
extern const struct pinmux_config emifa_pins_nand[12];
extern const struct pinmux_config emifa_pins_nor[43];
+/* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins[7];
+
#endif
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index 82d707f..608c652 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -36,6 +36,11 @@
#include asm/errno.h
#include hwconfig.h
+#ifdef CONFIG_DAVINCI_MMC
+#include mmc.h
+#include asm/arch/sdmmc_defs.h
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DRIVER_TI_EMAC
@@ -204,6 +209,23 @@ int misc_init_r(void)
return 0;
}
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC
*/
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, mmc_sd0);
+}
+#endif
+
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
@@ -236,6 +258,9 @@ const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(emifa_pins_nor),
#endif
PINMUX_ITEM(gpio_pins),
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins),
+#endif
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
@@ -246,6 +271,9 @@ const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
};
const int lpsc_size = ARRAY_SIZE(lpsc);
diff --git a/include
Re: [U-Boot] [PATCH] da850/omap-l138: enable SPI flash in RMII mode
Hi Christian, On Tue, Jun 05, 2012 at 15:38:53, Christian Riesch wrote: Hi, On Fri, Jun 1, 2012 at 3:48 PM, Prabhakar Lad prabhakar@ti.com wrote: From: Rajashekhara, Sudhakar sudhakar@ti.com According to DA850/OMAP-L138 schematics, GP2[6] line has to be driven high for RMII mode to work. In RMII mode, SPI flash becomes un-usable. But during testing it was found out that, driving GP2[6] low also enables RMII and in this configuration SPI flash is also accessible. How about just removing all the code that is related to GP2[6]? There's a pull-down resistor on the board and the pin is high impedance by default. Yes, this patch is not required I'll drop this patch. Thx, --Prabhakar Lad Regards, Christian Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com --- board/davinci/da8xxevm/da850evm.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 004d5ad..82d707f 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -438,10 +438,10 @@ int rmii_hw_init(void) CONFIG_SYS_I2C_EXPANDER_ADDR); } - /* Set the output as high */ - temp = REG(GPIO_BANK2_REG_SET_ADDR); + /* Set the output as low */ + temp = REG(GPIO_BANK2_REG_CLR_ADDR); temp |= (0x01 6); - REG(GPIO_BANK2_REG_SET_ADDR) = temp; + REG(GPIO_BANK2_REG_CLR_ADDR) = temp; /* Set the GPIO direction as output */ temp = REG(GPIO_BANK2_REG_DIR_ADDR); -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7] da850/omap-l138: Add support for NAND SPL
Hi Christian,
On Tue, Jun 05, 2012 at 16:56:01, Christian Riesch wrote:
Hi,
On Fri, Jun 1, 2012 at 4:30 PM, Prabhakar Lad prabhakar@ti.com wrote:
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for NAND SPL on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/spl.c | 13 ++-
include/configs/da850evm.h | 39
+
2 files changed, 41 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index be397ce..53df581 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -79,12 +79,6 @@ void board_init_f(ulong dummy)
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
@@ -95,6 +89,13 @@ void board_init_r(gd_t *id, ulong dummy)
serial_init(); /* serial communications setup */
gd-have_console = 1;
This breaks the build for the cam_enc_4xx board and the hawkboard.
You may do this initializations only if CONFIG_SPL_LIBCOMMON_SUPPORT
is defined. Please test your patchset with ./MAKEALL -s davinci
Ok I'll fix this.
Thx,
--Prabhakar Lad
Regards, Christian
+#ifdef CONFIG_SPL_NAND_LOAD
+ puts(Nand boot...\n);
+ nand_init();
+ puts(Nand Initalized...\n);
+ nand_boot();
+#endif
+#ifdef CONFIG_SPL_SPI_LOAD
puts(SPI boot...\n);
#ifdef CONFIG_SPL_MMC_LOAD
spl_mmc_load();
[...]
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Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Christian, On Tue, Jun 05, 2012 at 17:04:13, Christian Riesch wrote: Hi, On Fri, Jun 1, 2012 at 3:34 PM, Prabhakar Lad prabhakar@ti.com wrote: From: Rajashekhara, Sudhakar sudhakar@ti.com On DA850/OMAP-L138 it was observed that in RMII mode, auto negotiation was not performed. This patch enables auto negotiation in RMII mode. Without this patch, EMAC initialization takes more time and sometimes tftp fails in RMII mode. This patch causes a warning for the ea20 board: davinci_emac.c: In function 'davinci_emac_initialize': davinci_emac.c:901:2: warning: passing argument 1 of 'gen_auto_negotiate' makes integer from pointer without a cast davinci_emac.c:355:12: note: expected 'int' but argument is of type 'u_int8_t *' (found with ./MAKEALL -s davinci) Ok I'll fix this. Thx, --Prabhakar Lad Regards, Christian Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com --- drivers/net/davinci_emac.c | 5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index fbd0f1b..9bbd625 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -895,5 +895,10 @@ int davinci_emac_initialize(void) miiphy_register(phy[i].name, davinci_mii_phy_read, davinci_mii_phy_write); } + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + gen_auto_negotiate(active_phy_addr); +#endif return(1); } -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
