[U-Boot] [UBOOT][PATCH 3/3] ti: qspi: populate slave device to set flash quad bit.
The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- drivers/spi/ti_qspi.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index c5d2245..fd7fea8 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -106,6 +106,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave-memory_map = (void *)MMAP_START_ADDR_DRA; #else slave-memory_map = (void *)MMAP_START_ADDR_AM43x; + slave-op_mode_rx = 8; #endif memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 1/3] am33xx: Rework #ifdef's around s_init for clarity
From: Tom Rini tr...@ti.com
The s_init function is only called on SPL or XIP cases, so lets only
build it for them. This makes the #if logic within the function a bit
clearer as to when we are or are not calling things, and makes it easier
to see that for example preloader_console_init isn't ever called in the
non-XIP full U-Boot case.
Signed-off-by: Tom Rini tr...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 2b15a64..fb44cc8 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -202,6 +202,7 @@ static void watchdog_disable(void)
}
#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*
@@ -220,22 +221,19 @@ void s_init(void)
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
watchdog_disable();
timer_init();
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#endif
#ifdef CONFIG_NOR_BOOT
gd-baudrate = CONFIG_BAUDRATE;
serial_init();
gd-have_console = 1;
-#else
+#elif defined(CONFIG_SPL_BUILD)
gd = gdata;
preloader_console_init();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
@@ -243,8 +241,8 @@ void s_init(void)
rtc32k_enable();
#endif
sdram_init();
-#endif
}
+#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 2/3] am43xx_evm: Add qspi and qspiboot targets
Only the ePOS EVM has QSPI as an option and QSPI and NAND are mutually
exclusive. Add a qspi target that can see QSPI and work with it (as we
cannot do the pinmux for both QSPI and NAND at the same time) and a
qspiboot target that can be written to QSPI and booted (we are XIP and
thus need a different CONFIG_SYS_TEXT_BASE than normal).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |6 --
arch/arm/cpu/armv7/am33xx/emif4.c |3 ++-
board/ti/am43xx/Makefile |2 +-
board/ti/am43xx/board.c |2 +-
board/ti/am43xx/mux.c |4
boards.cfg|3 +++
include/configs/am43xx_evm.h | 39 ++---
include/configs/ti_armv7_common.h |2 +-
8 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index fb44cc8..93bdd9d 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -142,7 +142,8 @@ int arch_misc_init(void)
return 0;
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) || \
+ defined(CONFIG_QSPI_XIP)
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
@@ -202,7 +203,8 @@ static void watchdog_disable(void)
}
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) || \
+ defined(CONFIG_QSPI_XIP)
void s_init(void)
{
/*
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c
b/arch/arm/cpu/armv7/am33xx/emif4.c
index 3e39752..f3fe53b 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -35,7 +35,8 @@ void dram_init_banksize(void)
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) || \
+ defined(CONFIG_QSPI_XIP)
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index cb5fe88..7d12363 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -6,7 +6,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_QSPI_XIP),y)
obj-y := mux.o
endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d744977..7cc5a0e 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -70,7 +70,7 @@ static int read_eeprom(struct am43xx_board_id *header)
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_QSPI_XIP)
#define NUM_OPPS 6
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 77c53d2..3cfaf7c 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -73,6 +73,7 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
{-1},
};
+#ifdef CONFIG_QSPI
static struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
@@ -82,6 +83,7 @@ static struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
{-1},
};
+#endif
void enable_uart0_pin_mux(void)
{
@@ -99,7 +101,9 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(rgmii1_pin_mux);
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
+#ifdef CONFIG_QSPI
configure_module_pin_mux(qspi_pin_mux);
+#endif
}
}
diff --git a/boards.cfg b/boards.cfg
index d6d5bb3..588ef5d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -276,6 +276,9 @@ Active arm armv7 am33xx ti
am335x
Active arm armv7 am33xx ti am335x
am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND
Tom Rini tr...@ti.com
Active arm armv7 am33xx ti am335x
am335x_evm_usbspl
am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT
Tom Rini tr...@ti.com
Active arm armv7 am33xx ti am43xx
am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1
Lokesh Vutla lokeshvu...@ti.com
+Active arm armv7 am33xx ti
[U-Boot] [UBOOT][PATCH 0/3] am43xx: add xip support for ti qspi
This add support for am43xx qspi XIP boot. In this mode, we will
use only u-boot.bin.
This patch series is tested with a small hack change-
===
--- u-boot.orig/drivers/i2c/i2c_core.c 2014-05-05 16:14:08.305216507 +0530
+++ u-boot/drivers/i2c/i2c_core.c 2014-05-05 18:36:34.837855777 +0530
@@ -258,6 +258,7 @@
*/
unsigned int i2c_get_bus_num(void)
{
+ gd-cur_i2c_bus = 0;
return gd-cur_i2c_bus;
}
We need to do this, beacuse global data(gd) gets populated in _main api
which gets called after s_init. In s_init, we do a i2c_init for which we access
a gd-cur_bus_num, but since gd is not
initilaised, so I get a data abort here.
Sourav Poddar (2):
am43xx_evm: Add qspi and qspiboot targets
ti: qspi: Notify core to use quad command.
Tom Rini (1):
am33xx: Rework #ifdef's around s_init for clarity
arch/arm/cpu/armv7/am33xx/board.c | 12 ++--
arch/arm/cpu/armv7/am33xx/emif4.c |3 ++-
board/ti/am43xx/Makefile |2 +-
board/ti/am43xx/board.c |2 +-
board/ti/am43xx/mux.c |4
boards.cfg|3 +++
drivers/spi/ti_qspi.c |1 +
include/configs/am43xx_evm.h | 39 ++---
include/configs/ti_armv7_common.h |2 +-
9 files changed, 47 insertions(+), 21 deletions(-)
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH] mtd: spi: fix quad bit set path
Currently, flash quad bit is set in spi_flash_validate_params and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in spi_flash_probe_slave
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spi/sf_probe.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 0a46fe3..8482f08 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -197,16 +197,6 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Go for default supported write cmd */
flash-write_cmd = CMD_PAGE_PROGRAM;
- /* Set the quad enable bit - only for quad commands */
- if ((flash-read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
- (flash-read_cmd == CMD_READ_QUAD_IO_FAST) ||
- (flash-write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- if (spi_flash_set_qeb(flash, idcode[0])) {
- debug(SF: Fail to set QEB for %02x\n, idcode[0]);
- return NULL;
- }
- }
-
/* Read dummy_byte: dummy byte is determined based on the
* dummy cycles of a particular command.
* Fast commands - dummy_byte = dummy_cycles/8
@@ -327,6 +317,16 @@ static struct spi_flash *spi_flash_probe_slave(struct
spi_slave *spi)
if (!flash)
goto err_read_id;
+ /* Set the quad enable bit - only for quad commands */
+ if ((flash-read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash-read_cmd == CMD_READ_QUAD_IO_FAST) ||
+ (flash-write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash, idcode[0])) {
+ debug(SF: Fail to set QEB for %02x\n, idcode[0]);
+ return NULL;
+ }
+ }
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd-fdt_blob, flash)) {
debug(SF: FDT decode error\n);
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/5] spi: ti_qspi: Add delay for successful bulk erase.
On Monday 07 April 2014 10:51 PM, Tom Rini wrote: On Thu, Apr 03, 2014 at 08:45:42PM +0530, Jagan Teki wrote: On Thu, Apr 3, 2014 at 5:22 PM, Tom Rinitr...@ti.com wrote: From: Poddar, Souravsourav.pod...@ti.com Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddarsourav.pod...@ti.com Tested-by: Yebio Mesfinymes...@ti.com --- drivers/spi/ti_qspi.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index dfa5d0c..c5d2245 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -314,6 +314,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave-cmd |= QSPI_RD_SNGL; debug(rx cmd %08x dc %08x\n, qslave-cmd, qslave-dc); + #ifdef CONFIG_DRA7XX + udelay(500); + #endif writel(qslave-cmd,qslave-base-cmd); status = readl(qslave-base-status); timeout = QSPI_TIMEOUT; Can't we fix this? discussed the same in previous version thread as well. Sorry, I kicked out v2 before checking my mbox again. Sourav, do you have some time to look at this again? I can look at this sometime this week, but I am not sure if there is anything which can be done. I had tried few stuffs to get rid of this in the past, but those attempts failed. Still, I will check if there is anything more that can be done to get rid of this. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 5/5] spi: ti_qspi: Add delay for successful bulk erase.
On Thursday 03 April 2014 11:30 AM, Jagan Teki wrote: Hi Sourav, On Wednesday 02 April 2014 04:06 PM, Sourav Poddar wrote: Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddar sourav.pod...@ti.com Tested-by: Yebio Mesfin ymes...@ti.com --- drivers/spi/ti_qspi.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index dfa5d0c..c5d2245 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -314,6 +314,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave-cmd |= QSPI_RD_SNGL; debug(rx cmd %08x dc %08x\n, qslave-cmd, qslave-dc); + #ifdef CONFIG_DRA7XX + udelay(500); + #endif I myself not conveyed these delays on spi_xfer() (looks odd to me), we already have AM43XX delay on code, can't it be possible to manage through status poll? I know, its little out of place but with status poll way, erase is inconsistent, might be some board timing constraints. Hence, I am force to add this delay for dra board. I tried the status poll way, but erase is inconsistent, might be some board timing constraints. thanks! -- Jagan. This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 3/5] configs: dra7-evm: Add mtd parts info for qspi.
On Thursday 03 April 2014 11:59 AM, Jagan Teki wrote: On Wed, Apr 2, 2014 at 4:06 PM, Sourav Poddarsourav.pod...@ti.com wrote: Add MTD partition info for qspi on dra7 evm Signed-off-by: Sourav Poddarsourav.pod...@ti.com --- include/configs/dra7xx_evm.h | 46 ++ 1 file changed, 46 insertions(+) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 291c538..68496dc 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -75,6 +75,52 @@ #define CONFIG_SF_DEFAULT_SPEED4800 #define CONFIG_DEFAULT_SPI_MODESPI_MODE_3 +/* + * Default to using SPI for environment, etc. + * 0x00 - 0x01 : QSPI.SPL (64KiB) + * 0x01 - 0x02 : QSPI.SPL.backup1 (64KiB) + * 0x02 - 0x03 : QSPI.SPL.backup2 (64KiB) + * 0x03 - 0x04 : QSPI.SPL.backup3 (64KiB) + * 0x04 - 0x14 : QSPI.u-boot (1MiB) + * 0x14 - 0x15 : QSPI.u-boot-spl-os (64KiB) + * 0x15 - 0x16 : QSPI.u-boot-env (64KiB) + * 0x16 - 0x17 : QSPI.u-boot-env.backup1 (64KiB) + * 0x17 - 0x97 : QSPI.kernel (8MiB) + * 0x97 - 0x200 : USERLAND + */ +#if defined(CONFIG_QSPI_BOOT) +#undef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (64 10) /* 64 KiB */ +#define CONFIG_ENV_SECT_SIZE (64 10) /* 64 KB sectors */ +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET 0x15 +#undef CONFIG_ENV_OFFSET_REDUND +#define CONFIG_ENV_OFFSET_REDUND 0x16 + +#ifdef MTDIDS_DEFAULT +#undef MTDIDS_DEFAULT +#endif +#define MTDIDS_DEFAULT nor0=m25p80-flash.0 + +#ifdef MTDPARTS_DEFAULT +#undef MTDPARTS_DEFAULT +#endif +#define MTDPARTS_DEFAULT mtdparts=qspi.0:64k(SPL), \ + 64k(QSPI.SPL.backup1), \ + 64k(QSPI.SPL.backup2), \ + 64k(QSPI.SPL.backup3), \ + 1m(QSPI.u-boot), \ + 64k(QSPI.u-boot-spl-os), \ + 64k(QSPI.u-boot-env), \ + 64k(QSPI.u-boot-env.backup1), \ + 8m(QSPI.kernel), \ + -(QSPI.rootfs) +#endif + /* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_LOAD Can you add log file for this qspi mtd tests on your next version patches. Good to have this as we didn't mtd partitioning on qspi yet. thanks! Tom is planning to send the next version with few other cleanups. Once, he does that, I will add a log file on top of that for my testing? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 2/5] qspi: add support for qspi4 device
Add support to enable boot from qspi in qspi4 pin mode. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- arch/arm/include/asm/arch-omap5/spl.h |4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index f707998..77eb943 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -16,7 +16,11 @@ #define BOOT_DEVICE_MMC26 #define BOOT_DEVICE_MMC2_2 7 #define BOOT_DEVICE_SATA 9 +#ifdef CONFIG_QSPI_BOOT +#define BOOT_DEVICE_SPI11 +#else #define BOOT_DEVICE_SPI10 +#endif #define BOOT_DEVICE_UART 0x43 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 1/5] board.cfg: dra7: Add QSPI boot config.
These add a qspi boot config for dra7 board. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- boards.cfg |2 ++ 1 file changed, 2 insertions(+) diff --git a/boards.cfg b/boards.cfg index 69c8936..d6d5bb3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -356,6 +356,8 @@ Active arm armv7 omap4 ti panda Active arm armv7 omap4 ti sdp4430 omap4_sdp4430- Sricharan R r.sricha...@ti.com Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla lokeshvu...@ti.com Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla lokeshvu...@ti.com +Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT + Sourav Poddar sourav.pod...@ti.com Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800evaarmadillo-800eva - Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Active arm armv7 rmobile kmc kzm9g kzm9g- Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com:Tetsuyuki Kobayashi k...@kmckk.co.jp -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 0/5] dra7: Add partition table entry and qspi boot config
The following patch series aims at 1. adding a seperate defconfig for qspi on dra7. 2. Also populate the qspi partition table for dra7 evm boards. 3. cleanup and fixes around qspi4 pin mode and bulk erase respectively. Tested on J6 evm(PG1.1) with the following sysconfig boot settings. sysconfig[5:0] = 100111. Here is the log till uboot prompt: - U-Boot SPL 2014.04-rc3-5-ge97693a (Apr 02 2014 - 15:35:24) DRA752 ES1.1 U-Boot 2014.04-rc3-5-ge97693a (Apr 02 2014 - 15:35:24) CPU : DRA752 ES1.1 Board: DRA7xx I2C: ready DRAM: 1.5 GiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 SCSI: SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c00 *** Warning - bad CRC, using default environment SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... Found 0 device(s). Net: ethaddr not set. Validating first E-fuse MAC cpsw Warning: Your board does not use generic board. Please read doc/README.generic-board and take action. Boards not upgraded by the late 2014 may break or be removed. Hit any key to stop autoboot: 0 Sourav Poddar (5): board.cfg: am43xx: Add QSPI boot config. qspi: add support for qspi4 device configs: dra7-evm: Add mtd parts info for qspi. configs: dra7-evm: change uboot offset spi: ti_qspi: Add delay for successful bulk erase. arch/arm/include/asm/arch-omap5/spl.h |4 +++ boards.cfg|2 ++ drivers/spi/ti_qspi.c |3 +++ include/configs/dra7xx_evm.h | 48 - 4 files changed, 56 insertions(+), 1 deletion(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 4/5] configs: dra7-evm: change uboot offset
Change uboot offset in accordance with the partition formed. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- include/configs/dra7xx_evm.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 68496dc..cd2f8d9 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -127,7 +127,7 @@ #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x4 #define CONFIG_SUPPORT_EMMC_BOOT -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 3/5] configs: dra7-evm: Add mtd parts info for qspi.
Add MTD partition info for qspi on dra7 evm Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- include/configs/dra7xx_evm.h | 46 ++ 1 file changed, 46 insertions(+) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 291c538..68496dc 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -75,6 +75,52 @@ #define CONFIG_SF_DEFAULT_SPEED4800 #define CONFIG_DEFAULT_SPI_MODESPI_MODE_3 +/* + * Default to using SPI for environment, etc. + * 0x00 - 0x01 : QSPI.SPL (64KiB) + * 0x01 - 0x02 : QSPI.SPL.backup1 (64KiB) + * 0x02 - 0x03 : QSPI.SPL.backup2 (64KiB) + * 0x03 - 0x04 : QSPI.SPL.backup3 (64KiB) + * 0x04 - 0x14 : QSPI.u-boot (1MiB) + * 0x14 - 0x15 : QSPI.u-boot-spl-os (64KiB) + * 0x15 - 0x16 : QSPI.u-boot-env (64KiB) + * 0x16 - 0x17 : QSPI.u-boot-env.backup1 (64KiB) + * 0x17 - 0x97 : QSPI.kernel (8MiB) + * 0x97 - 0x200 : USERLAND + */ +#if defined(CONFIG_QSPI_BOOT) +#undef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (64 10) /* 64 KiB */ +#define CONFIG_ENV_SECT_SIZE (64 10) /* 64 KB sectors */ +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET 0x15 +#undef CONFIG_ENV_OFFSET_REDUND +#define CONFIG_ENV_OFFSET_REDUND 0x16 + +#ifdef MTDIDS_DEFAULT +#undef MTDIDS_DEFAULT +#endif +#define MTDIDS_DEFAULT nor0=m25p80-flash.0 + +#ifdef MTDPARTS_DEFAULT +#undef MTDPARTS_DEFAULT +#endif +#define MTDPARTS_DEFAULT mtdparts=qspi.0:64k(SPL), \ + 64k(QSPI.SPL.backup1), \ + 64k(QSPI.SPL.backup2), \ + 64k(QSPI.SPL.backup3), \ + 1m(QSPI.u-boot), \ + 64k(QSPI.u-boot-spl-os), \ + 64k(QSPI.u-boot-env), \ + 64k(QSPI.u-boot-env.backup1), \ + 8m(QSPI.kernel), \ + -(QSPI.rootfs) +#endif + /* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_LOAD -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 5/5] spi: ti_qspi: Add delay for successful bulk erase.
Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddar sourav.pod...@ti.com Tested-by: Yebio Mesfin ymes...@ti.com --- drivers/spi/ti_qspi.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index dfa5d0c..c5d2245 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -314,6 +314,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave-cmd |= QSPI_RD_SNGL; debug(rx cmd %08x dc %08x\n, qslave-cmd, qslave-dc); + #ifdef CONFIG_DRA7XX + udelay(500); + #endif writel(qslave-cmd, qslave-base-cmd); status = readl(qslave-base-status); timeout = QSPI_TIMEOUT; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,PATCHv3,1/5] am43xx: Add qspi support
On Monday 06 January 2014 01:06 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:10 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Saturday 21 December 2013 12:50 PM, Jagannadha Sutradharudu Teki wrote:
From: Jagannadha Sutradharudu
Tekijagannadha.sutradharudu-t...@xilinx.com
From: Poddar, Souravsourav.pod...@ti.com
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
Reviewed-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
V3: Added review tag
V2:
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 97c00b4..fb654bb 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -98,6 +98,7 @@ void enable_basic_clocks(void)
cmper-emiffwclkctrl,
cmper-emifclkctrl,
cmper-otfaemifclkctrl,
+cmper-qspiclkctrl,
0
};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 9febfa2..0736258 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -332,7 +332,9 @@ struct cm_perpll {
unsigned int mcasp1clkctrl; /* offset 0x240 */
unsigned int resv11;
unsigned int mmc2clkctrl; /* offset 0x248 */
- unsigned int resv12[5];
+ unsigned int resv12[3];
+ unsigned int qspiclkctrl; /* offset 0x258 */
+ unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
unsigned int resv13[103];
unsigned int l4lsclkstctrl; /* offset 0x400 */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index 7a7d91b..0855d16 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -29,5 +29,6 @@
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE 0x4790
#endif
#endif
This looks Ok to me.
How you want this to go?
I mean as Tom suggested in some earlier version through his tree? or yours?
Tom told in earlier that - he will take this series as there are some
conflicts w.r.t u-boot-ti
http://u-boot.10912.n7.nabble.com/UBOOT-PATCHv2-0-5-qspi-Add-AM437x-support-td170188.html
I sent this series again to fix one warning and added Reviewed-by tag.
Ok thanks,
Tom,
Can you pick this one?
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
On Monday 06 January 2014 01:10 PM, Jagan Teki wrote:
On Mon, Jan 6, 2014 at 12:39 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 11 ---
drivers/mtd/spi/sf_ops.c | 75
+++
drivers/mtd/spi/sf_probe.c| 44 +
3 files changed, 77 insertions(+), 53 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c69b53d..c77961f 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const
u8 *cmd, size_t cmd_len,
/* Flash erase(sectors) operation, support all possible erase commands
*/
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t
len);
+/* Read the status register */
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
+
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit for macronix flashes */
-int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+/* Read the config register */
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
-/* Set quad enbale bit for winbond and spansion flashes */
-int spi_flash_set_qeb_winspan(struct spi_flash *flash);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 9681042..658294c 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
cmd[3] = addr 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
{
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash,cmd, 1,sr, 1);
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash,cmd, 1, rs, 1);
if (ret 0) {
- debug(SF: fail to write status register\n);
+ debug(SF: fail to read status register\n);
return ret;
}
return 0;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
-int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
{
- u8 qeb_status;
u8 cmd;
int ret;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash,cmd, 1,qeb_status, 1);
+ cmd = CMD_WRITE_STATUS;
+ ret = spi_flash_write_common(flash,cmd, 1,sr, 1);
if (ret 0) {
- debug(SF: fail to read status register\n);
+ debug(SF: fail to write status register\n);
return ret;
}
- if (qeb_status STATUS_QEB_MXIC) {
- debug(SF: Quad enable bit is already set\n);
- } else {
- ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
- if (ret 0)
- return ret;
- }
-
- return ret;
+ return 0;
}
-#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) ||
defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
{
- u8 data[2];
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash,cmd, 1,data[0], 1);
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash,cmd, 1, rc, 1);
if (ret 0) {
- debug(SF: fail to read status register\n);
- return ret;
- }
-
- cmd = CMD_WRITE_STATUS;
- data[1] = cr;
- ret = spi_flash_write_common(flash,cmd, 1,data, 2);
- if (ret) {
- debug(SF: fail to write config register\n);
+ debug(SF: fail to read config register\n);
return ret;
}
return 0;
}
-int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
{
- u8 qeb_status;
+ u8 data[2];
u8 cmd;
int ret;
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash,cmd, 1,qeb_status, 1);
- if (ret 0) {
- debug(SF: fail to read config register\n);
+ ret = spi_flash_cmd_read_status(flash,data[0]);
+ if (ret 0)
return ret;
- }
- if (qeb_status
Re: [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 10 ++
drivers/mtd/spi/sf_probe.c| 12
include/spi_flash.h | 2 ++
4 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7be0292..a9f5a81 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,8 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x100
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 827f719..dda75b1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#includecommon.h
+#includemalloc.h
#includespi.h
#includespi_flash.h
#includewatchdog.h
@@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash,
const u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t
len)
{
u32 erase_size;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash-erase_size;
@@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
u32 offset,
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
page_size = flash-page_size;
@@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
+ u8 *cmd, bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
u32 offset,
return 0;
}
+ cmd = malloc(SPI_FLASH_CMD_LEN + flash-dummy_cycles);
+ memset(cmd, 0, SPI_FLASH_CMD_LEN + flash-dummy_cycles);
cmd[0] = flash-read_cmd;
- cmd[4] = 0x00;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a049e72..b070adc 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -140,6 +140,18 @@ static struct spi_flash
*spi_flash_validate_params(struct spi_slave *spi,
}
}
+ /* Read dummy cycles */
+ switch (flash-read_cmd) {
+ case CMD_READ_QUAD_IO_FAST:
+ flash-dummy_cycles = 2;
+ break;
+ case CMD_READ_ARRAY_SLOW:
+ flash-dummy_cycles = 0;
+ break;
+ default:
+ flash-dummy_cycles = 1;
+ }
+
what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
cycles(macronix), so
by your code you keep it to 1(8 bit) dummy cycle. ?
Yes- Actually i miss used the names here.
These are dummy_byte_count
Ex: Except fast reads (array, dual and quad fast)
dummy_byte_count = dummy_cycles * no.of lines
dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
is this calculation documented in any of the flash sheet?
fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
reason why I am not including
no.of lines here is irrespective of fast(1 line), dual(2 lines) and
quad(4 lines) only data can travel among the difference lines
but the cmd,inst, dummy can travel only on single line. this can be
opposite in i/o commands.
Hope you understand - I just said based on my knowledge.
I will change the dummy_cycles into dummy_bytes - nevertheless everything same.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
On Monday 06 January 2014 04:00 PM, Jagan Teki wrote:
On Mon, Jan 6, 2014 at 3:51 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 10 ++
drivers/mtd/spi/sf_probe.c| 12
include/spi_flash.h | 2 ++
4 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h
b/drivers/mtd/spi/sf_internal.h
index 7be0292..a9f5a81 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,8 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x100
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 827f719..dda75b1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#includecommon.h
+#includemalloc.h
#includespi.h
#includespi_flash.h
#includewatchdog.h
@@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash,
const u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset,
size_t
len)
{
u32 erase_size;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash-erase_size;
@@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
u32 offset,
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
page_size = flash-page_size;
@@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
+ u8 *cmd, bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
u32 offset,
return 0;
}
+ cmd = malloc(SPI_FLASH_CMD_LEN + flash-dummy_cycles);
+ memset(cmd, 0, SPI_FLASH_CMD_LEN + flash-dummy_cycles);
cmd[0] = flash-read_cmd;
- cmd[4] = 0x00;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a049e72..b070adc 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -140,6 +140,18 @@ static struct spi_flash
*spi_flash_validate_params(struct spi_slave *spi,
}
}
+ /* Read dummy cycles */
+ switch (flash-read_cmd) {
+ case CMD_READ_QUAD_IO_FAST:
+ flash-dummy_cycles = 2;
+ break;
+ case CMD_READ_ARRAY_SLOW:
+ flash-dummy_cycles = 0;
+ break;
+ default:
+ flash-dummy_cycles = 1;
+ }
+
what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
cycles(macronix), so
by your code you keep it to 1(8 bit) dummy cycle. ?
Yes- Actually i miss used the names here.
These are dummy_byte_count
Ex: Except fast reads (array, dual and quad fast)
dummy_byte_count = dummy_cycles * no.of lines
dual i/o (4 dummy_cycles) - 4 * 2 = 1 dummy_byte
quad i/o (4 dummy_cycles) - 4 * 4 = 2 dummy_byte
is this calculation documented in any of the flash sheet?
I haven't see the exact calculation but ie. how the I/O operation usually works.
quad read - cmd, 3byte_inst, 1 dummy_byte(8 dummy_cycles) goes on
single line and data goes in 4 lines
quad i/o - except cmd(1 lines) remaining goes in 4 lines.
Ok, got the point.
fast, dual and quad fast have 8 dummy_cycles means 1 byte dummy the
reason why I am not including
no.of lines here is irrespective of fast(1 line), dual(2 lines) and
quad(4 lines) only data can travel among the difference lines
but the cmd,inst, dummy can travel only on single line. this can be
opposite in i/o commands.
Hope you understand - I just said based on my knowledge.
I will change the dummy_cycles into dummy_bytes - nevertheless everything
same.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,PATCHv3,1/5] am43xx: Add qspi support
Hi Jagan,
On Saturday 21 December 2013 12:50 PM, Jagannadha Sutradharudu Teki wrote:
From: Jagannadha Sutradharudu Tekijagannadha.sutradharudu-t...@xilinx.com
From: Poddar, Souravsourav.pod...@ti.com
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
Reviewed-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
V3: Added review tag
V2:
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 97c00b4..fb654bb 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -98,6 +98,7 @@ void enable_basic_clocks(void)
cmper-emiffwclkctrl,
cmper-emifclkctrl,
cmper-otfaemifclkctrl,
+ cmper-qspiclkctrl,
0
};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 9febfa2..0736258 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -332,7 +332,9 @@ struct cm_perpll {
unsigned int mcasp1clkctrl; /* offset 0x240 */
unsigned int resv11;
unsigned int mmc2clkctrl; /* offset 0x248 */
- unsigned int resv12[5];
+ unsigned int resv12[3];
+ unsigned int qspiclkctrl; /* offset 0x258 */
+ unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
unsigned int resv13[103];
unsigned int l4lsclkstctrl; /* offset 0x400 */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index 7a7d91b..0855d16 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -29,5 +29,6 @@
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE 0x4790
#endif
#endif
This looks Ok to me.
How you want this to go?
I mean as Tom suggested in some earlier version through his tree? or yours?
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 08/12] sf: Discover read dummy_cycles
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 10 ++
drivers/mtd/spi/sf_probe.c| 12
include/spi_flash.h | 2 ++
4 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7be0292..a9f5a81 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,8 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x100
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 827f719..dda75b1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#includecommon.h
+#includemalloc.h
#includespi.h
#includespi_flash.h
#includewatchdog.h
@@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash-erase_size;
@@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
page_size = flash-page_size;
@@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
+ u8 *cmd, bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -335,8 +336,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return 0;
}
+ cmd = malloc(SPI_FLASH_CMD_LEN + flash-dummy_cycles);
+ memset(cmd, 0, SPI_FLASH_CMD_LEN + flash-dummy_cycles);
cmd[0] = flash-read_cmd;
- cmd[4] = 0x00;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a049e72..b070adc 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -140,6 +140,18 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
}
}
+ /* Read dummy cycles */
+ switch (flash-read_cmd) {
+ case CMD_READ_QUAD_IO_FAST:
+ flash-dummy_cycles = 2;
+ break;
+ case CMD_READ_ARRAY_SLOW:
+ flash-dummy_cycles = 0;
+ break;
+ default:
+ flash-dummy_cycles = 1;
+ }
+
what about dummy cycles for dual i/o(0xbb), it has 4 clock bit dummy
cycles(macronix), so
by your code you keep it to 1(8 bit) dummy cycle. ?
/* Poll cmd seclection */
flash-poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
diff --git a/include/spi_flash.h b/include/spi_flash.h
index d24e40a..bdd4141 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -72,6 +72,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
* @erase_cmd:Erase cmd 4K, 32K, 64K
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd:Write cmd - page and quad program.
+ * @dummy_cycles: Dummy cycles for read operation.
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
*Supported cmds: Fast Array Read
@@ -98,6 +99,7 @@ struct spi_flash {
u8 erase_cmd;
u8 read_cmd;
u8 write_cmd;
+ u8 dummy_cycles;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 11 ---
drivers/mtd/spi/sf_ops.c | 75 +++
drivers/mtd/spi/sf_probe.c| 44 +
3 files changed, 77 insertions(+), 53 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c69b53d..c77961f 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8
*cmd, size_t cmd_len,
/* Flash erase(sectors) operation, support all possible erase commands */
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
+/* Read the status register */
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
+
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit for macronix flashes */
-int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+/* Read the config register */
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
-/* Set quad enbale bit for winbond and spansion flashes */
-int spi_flash_set_qeb_winspan(struct spi_flash *flash);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 9681042..658294c 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
cmd[3] = addr 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
{
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash,cmd, 1,sr, 1);
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash,cmd, 1, rs, 1);
if (ret 0) {
- debug(SF: fail to write status register\n);
+ debug(SF: fail to read status register\n);
return ret;
}
return 0;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
-int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
{
- u8 qeb_status;
u8 cmd;
int ret;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash,cmd, 1,qeb_status, 1);
+ cmd = CMD_WRITE_STATUS;
+ ret = spi_flash_write_common(flash,cmd, 1,sr, 1);
if (ret 0) {
- debug(SF: fail to read status register\n);
+ debug(SF: fail to write status register\n);
return ret;
}
- if (qeb_status STATUS_QEB_MXIC) {
- debug(SF: Quad enable bit is already set\n);
- } else {
- ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
- if (ret 0)
- return ret;
- }
-
- return ret;
+ return 0;
}
-#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
{
- u8 data[2];
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash,cmd, 1,data[0], 1);
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash,cmd, 1, rc, 1);
if (ret 0) {
- debug(SF: fail to read status register\n);
- return ret;
- }
-
- cmd = CMD_WRITE_STATUS;
- data[1] = cr;
- ret = spi_flash_write_common(flash,cmd, 1,data, 2);
- if (ret) {
- debug(SF: fail to write config register\n);
+ debug(SF: fail to read config register\n);
return ret;
}
return 0;
}
-int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
{
- u8 qeb_status;
+ u8 data[2];
u8 cmd;
int ret;
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash,cmd, 1,qeb_status, 1);
- if (ret 0) {
- debug(SF: fail to read config register\n);
+ ret = spi_flash_cmd_read_status(flash,data[0]);
+ if (ret 0)
return ret;
- }
- if (qeb_status STATUS_QEB_WINSPAN) {
- debug(SF: Quad enable bit is already set\n);
- } else {
- ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
-
Re: [U-Boot] [PATCH v6 00/12] sf: Add Extended read and quad read/write commands support
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote: This a suffix series for http://u-boot.10912.n7.nabble.com/PATCH-v4-00-36-sf-Add-common-probe-and-extended-quad-read-write-cmds-support-td163949.html for adding extended read and quad read/write commands support. Concept: Implementation will discover the fastest command by taking the supported commands from flash and a controller. Controller supported commands will always been a priority. The above concept is changed in this series as couple of reviews from earlier ones. - Implementation concept will apply on read commands. - As we have two write commands as of now – so this series is not trying to discover the fastest write command - The respective command modes are given to the controller driver side as a form of SPI RX/RX operation modes - so sf definitions will not be part of SPI driver side. Testing branch: $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b master-quad origin/master-quad REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. -- Thanks, Jagan. Changes for v6: - Divided flash reg ops code - sf_ops.c clean Changes for v5: - Re-implemented write command log - not trying to discover the fastest write - Added SPI RX/TX operation modes - SPI flash parts are moved into sf_params.c file - Added QUAD_IO_FAST read support - Discovred the read dummy_cycles based on configured read cmd - Added set QEB support for macronix flash - Enabled quad read/write cmd support for macronix flash Changes for v4: Changes for v3: Changes for v2: - none Jagannadha Sutradharudu Teki (12): sf: Add extended read commands support sf: Add quad read/write commands support sf: ops: Add configuration register writing support sf: Set quad enable bit support sf: probe: Enable RD_FULL and WR_QPP sf: Separate the flash params table sf: Add QUAD_IO_FAST read support sf: Discover read dummy_cycles sf: Add macronix set QEB support sf: probe: Enable macronix quad read/write cmds support sf: Divide flash register ops from QEB code sf: Code cleanups drivers/mtd/spi/Makefile | 4 +- drivers/mtd/spi/sf_internal.h | 31 +- drivers/mtd/spi/sf_ops.c | 71 ++-- drivers/mtd/spi/sf_params.c | 130 ++ drivers/mtd/spi/sf_probe.c| 246 +++--- include/spi.h | 17 +++ include/spi_flash.h | 43 7 files changed, 393 insertions(+), 149 deletions(-) create mode 100644 drivers/mtd/spi/sf_params.c Apart from the couple of comments given, this series looks good to me. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv2 0/5] qspi: Add AM437x support
On Friday 20 December 2013 11:56 PM, Tom Rini wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 12/20/2013 01:18 PM, Jagan Teki wrote: Hi Sourav, On Fri, Dec 20, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. v1-v2: Remove patch 3 of previous version, as support was already added for macronix flash. Created a doc explaining the test details. This patches are developed and tested on top of the following tree: git://git.denx.de/u-boot-ti.git branch: master These are no apply directly to master may be some dependencies require - please check. This probably requires patches in u-boot-ti that haven't hit mainline yet. I can take the series if you're OK with the spi parts. Thanks! Yes, thats the case. As, mentioned in cover letter it is developed on ti uboot as it has dependency. - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJStIu4AAoJENk4IS6UOR1Wh1AP/iRK8PL9sM2+co+GV21faWR1 v4WYAtliAqETerod5W9c3R9ZGN24FrdDQQYJF8i7Dq31j6PkmvQMyM4Uq3D1h8x6 kbLoDp6HpRdY5l7XmbTFXSvN2XOHekK6kqLA7lHn3jFJevc0Iq5B7lZ6Rj6I+FHM IQ/P1oMng4usf19ChrxvqWgB2i2wUqaGxL7bFUBLOMrFLAEKh1wFBahRzF7wBqLn SGmdqBGrHMcJ5fYy6utDeG94HCQksowrg6R89ZolLd9leVsYOvpd6NrNoxD5aT4m LXZYLwyr54O+Hi8AKs20yc7qjxihBI8BjjMu5W+DoAf42LI7cfZfFnczt8X5JyKq y3j7ccUzP1lOuyD7ODVjFtNOUx2b/lhmvbHicfmBufROcnlCDdAbr4qeG+9/1FJl d4miYgfrGQ8DWzAdr/oeISDDJWhM6nJw7LIyVSRhfstsethlLUByOr7qF1zQ/xlL EHoeL8cOyzD6Pi7xJ0cnwv5jM5038eszAkUKcSKQyQlWszySOSEFVKFYYn/pQrRD 8gDcx6Zg5b1EblHH17iErK40PxDOKmN36DYJE7NJGhFjRo1rcrPSAgGzqq7X924D t6i647Q79AU/3J3F3rA3uOXyClg2V1nswZqNZlAZgtFD8xbc7vBVo7zhlJewjhKH P3BR4+rNJIetRzA/+PvN =Z1qH -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote: On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? Please send the next version patches - fix the comments as we discussed so far. I will send the next version. But, what about the delay patch, I tried other stuffs but could not see any thing that helps. So, I will send the delay patch also as of now, to make it work out of mainline. I am some how OK with that as that change is in ur driver.. Just try this change /* FIXME: comments here... */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif And also write the bug log on commit message(means with out delay) Try to ass the testing logs on doc/ - for each time you tested a new flash or new driver. Jagan, Just realised that this patches depends on AM43x base patches which are in ti-uboot mainline tree. So, what should I do in that case. ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote: On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? Please send the next version patches - fix the comments as we discussed so far. I will send the next version. But, what about the delay patch, I tried other stuffs but could not see any thing that helps. So, I will send the delay patch also as of now, to make it work out of mainline. I am some how OK with that as that change is in ur driver.. Just try this change /* FIXME: comments here... */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif And also write the bug log on commit message(means with out delay) Try to ass the testing logs on doc/ - for each time you tested a new flash or new driver. Jagan, Just realised that this patches depends on AM43x base patches which are in ti-uboot mainline tree. So, what should I do in that case. ? Send all of them together..! So, I should send all the base patches also? Note: These dependendt patches are already there in tom ti-uboot mainline tree. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 19 December 2013 02:50 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 2:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote: On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? Please send the next version patches - fix the comments as we discussed so far. I will send the next version. But, what about the delay patch, I tried other stuffs but could not see any thing that helps. So, I will send the delay patch also as of now, to make it work out of mainline. I am some how OK with that as that change is in ur driver.. Just try this change /* FIXME: comments here... */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif And also write the bug log on commit message(means with out delay) Try to ass the testing logs on doc/ - for each time you tested a new flash or new driver. Jagan, Just realised that this patches depends on AM43x base patches which are in ti-uboot mainline tree. So, what should I do in that case. ? Send all of them together..! So, I should send all the base patches also? am43xx_evm is already available - all patches means related to spi for this board. If OK then send Ok. Actually bassic board support is already there. But there were few updated done on baseport side to make these reach uboot prompt. I will test with those patches and send you only the spi part for pull bsed on your master branch. Note: These dependendt patches are already there in tom ti-uboot mainline tree. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 19 December 2013 02:50 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 2:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote: On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? Please send the next version patches - fix the comments as we discussed so far. I will send the next version. But, what about the delay patch, I tried other stuffs but could not see any thing that helps. So, I will send the delay patch also as of now, to make it work out of mainline. I am some how OK with that as that change is in ur driver.. Just try this change /* FIXME: comments here... */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif And also write the bug log on commit message(means with out delay) Try to ass the testing logs on doc/ - for each time you tested a new flash or new driver. Jagan, Just realised that this patches depends on AM43x base patches which are in ti-uboot mainline tree. So, what should I do in that case. ? Send all of them together..! So, I should send all the base patches also? am43xx_evm is already available - all patches means related to spi for this board. If OK then send Note: These dependendt patches are already there in tom ti-uboot mainline tree. I am getting this error while building with this patches drivers/spi/built-in.o: In function `spi_setup_slave': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:180: undefined reference to `gpio_request' /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:181: undefined reference to `gpio_direction_output' arm-linux-gnueabihf-ld.bfd: BFD (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) 2.23.1 assertion fail /cbuild/slaves/oorts/crosstool-ng/builds/arm-linux-gnueabihf-linux/.build/src/binutils-2.23.1/bfd/elf32-arm.c:7677 arm-linux-gnueabihf-ld.bfd: BFD (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) 2.23.1 assertion fail /cbuild/slaves/oorts/crosstool-ng/builds/arm-linux-gnueabihf-linux/.build/src/binutils-2.23.1/bfd/elf32-arm.c:7677 arm-linux-gnueabihf-ld.bfd: error: required section '.rel.plt' not found in the linker script arm-linux-gnueabihf-ld.bfd: final link failed: Invalid operation I think there is something else that need to be merged from ti-uboot tree as I am not facing this issue there ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv2 2/5] am437x_epos_evm: add SPL API, QSPI, and serial flash support
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/am43xx/mux.c| 11 +++
include/configs/am43xx_evm.h | 20
2 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 810b194..4db3d78 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -38,6 +38,16 @@ static struct module_pin_mux gpio0_22_pin_mux[] = {
{-1},
};
+static struct module_pin_mux qspi_pin_mux[] = {
+ {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /*
QSPI_D0 */
+ {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /*
QSPI_D1 */
+ {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+ {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /*
QSPI_D3 */
+ {-1},
+};
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
@@ -50,6 +60,7 @@ void enable_board_pin_mux(void)
if (board_is_gpevm())
configure_module_pin_mux(gpio0_22_pin_mux);
+ configure_module_pin_mux(qspi_pin_mux);
}
void enable_i2c0_pin_mux(void)
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 4de495a..a81c586 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -79,6 +79,26 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_QSPI_SEL_GPIO 48
+#define CONFIG_SF_DEFAULT_SPEED4800
+#define CONFIG_DEFAULT_SPI_MODESPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
loadaddr=0x8020\0 \
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv2 0/5] qspi: Add AM437x support
The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. v1-v2: Remove patch 3 of previous version, as support was already added for macronix flash. Created a doc explaining the test details. This patches are developed and tested on top of the following tree: git://git.denx.de/u-boot-ti.git branch: master Sourav Poddar (5): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer doc: qspi: Add qspi test details on AM43xx arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 doc/SPI/README.ti_qspi_am43x_test| 76 ++ drivers/spi/ti_qspi.c| 33 - include/configs/am43xx_evm.h | 20 7 files changed, 142 insertions(+), 4 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_am43x_test ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv2 1/5] am43xx: add qspi support
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 97c00b4..fb654bb 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -98,6 +98,7 @@ void enable_basic_clocks(void)
cmper-emiffwclkctrl,
cmper-emifclkctrl,
cmper-otfaemifclkctrl,
+ cmper-qspiclkctrl,
0
};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 9febfa2..0736258 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -332,7 +332,9 @@ struct cm_perpll {
unsigned int mcasp1clkctrl; /* offset 0x240 */
unsigned int resv11;
unsigned int mmc2clkctrl; /* offset 0x248 */
- unsigned int resv12[5];
+ unsigned int resv12[3];
+ unsigned int qspiclkctrl; /* offset 0x258 */
+ unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
unsigned int resv13[103];
unsigned int l4lsclkstctrl; /* offset 0x400 */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index 7a7d91b..0855d16 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -29,5 +29,6 @@
#define SRAM_SCRATCH_SPACE_ADDR0x40337C00
#define AM4372_BOARD_NAME_STARTSRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE 0x4790
#endif
#endif
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv2 4/5] am43xx: add delay before xfer
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Without this patch, device does not get probed also.
Here is the log.
U-Boot#
U-Boot#
U-Boot#
U-Boot# sf probe 0
SF: Unsupported flash IDs: manuf ff, jedec , ext_jedec
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 0
While with this patch, log is
U-Boot# sf probe 0
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64
MiB, mapped at 3000
U-Boot# sf erase 0 0x8
SF: 524288 bytes @ 0x0 Erased: OK
U-Boot# mw 8100 0xdededede 0x4
U-Boot# sf write 8100 0 0x4
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 8200 0 0x4
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x8200
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
- updated commit log with error message.
- Add a FIXME comment in code,
drivers/spi/ti_qspi.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5666250..dfa5d0c 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -285,6 +285,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
qslave-cmd |= QSPI_3_PIN;
qslave-cmd |= 0xfff;
+/* FIXME: This delay is required for successfull
+ * completion of read/write/erase. Once its root
+ * caused, it will be remove from the driver.
+ */
+#ifdef CONFIG_AM43XX
+ udelay(100);
+#endif
while (words--) {
if (txp) {
debug(tx cmd %08x dc %08x data %02x\n,
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv2 5/5] doc: SPI: Add qspi test details on AM43xx
This shows the log obtained while testing qspi on AM437x board. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- doc/SPI/README.ti_qspi_am43x_test | 76 + 1 files changed, 76 insertions(+), 0 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_am43x_test diff --git a/doc/SPI/README.ti_qspi_am43x_test b/doc/SPI/README.ti_qspi_am43x_test new file mode 100644 index 000..8fbf10b --- /dev/null +++ b/doc/SPI/README.ti_qspi_am43x_test @@ -0,0 +1,76 @@ +Testing details- + + +This doc simply illustrated the testing details of qspi flash +driver with Macronix M25L51235 flash device. + +The test includes +- probing the flash device +- erasing the flash device +- Writing to flash +- Reading the contents of the flash. + +Test Log + + +Hit any key to stop autoboot: 0 +U-Boot# sf probe 0 +SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 3000 +U-Boot# sf erase 0 0x8 +SF: 524288 bytes @ 0x0 Erased: OK +U-Boot# mw 8100 0xdededede 0x4 +U-Boot# sf write 8100 0 0x4 +SF: 262144 bytes @ 0x0 Written: OK +U-Boot# sf read 8200 0 0x4 +SF: 262144 bytes @ 0x0 Read: OK +U-Boot# md 0x8200 +8200: dededede dededede dededede dededede +8210: dededede dededede dededede dededede +8220: dededede dededede dededede dededede +8230: dededede dededede dededede dededede +8240: dededede dededede dededede dededede +8250: dededede dededede dededede dededede +8260: dededede dededede dededede dededede +8270: dededede dededede dededede dededede +8280: dededede dededede dededede dededede +8290: dededede dededede dededede dededede +82a0: dededede dededede dededede dededede +82b0: dededede dededede dededede dededede +82c0: dededede dededede dededede dededede +82d0: dededede dededede dededede dededede +82e0: dededede dededede dededede dededede +82f0: dededede dededede dededede dededede +U-Boot# md 0x8201 +8201: dededede dededede dededede dededede +82010010: dededede dededede dededede dededede +82010020: dededede dededede dededede dededede +82010030: dededede dededede dededede dededede +82010040: dededede dededede dededede dededede +82010050: dededede dededede dededede dededede +82010060: dededede dededede dededede dededede +82010070: dededede dededede dededede dededede +82010080: dededede dededede dededede dededede +82010090: dededede dededede dededede dededede +820100a0: dededede dededede dededede dededede +820100b0: dededede dededede dededede dededede +820100c0: dededede dededede dededede dededede +820100d0: dededede dededede dededede dededede +820100e0: dededede dededede dededede dededede +820100f0: dededede dededede dededede dededede +U-Boot# md 0x8203 +8203: dededede dededede dededede dededede +82030010: dededede dededede dededede dededede +82030020: dededede dededede dededede dededede +82030030: dededede dededede dededede dededede +82030040: dededede dededede dededede dededede +82030050: dededede dededede dededede dededede +82030060: dededede dededede dededede dededede +82030070: dededede dededede dededede dededede +82030080: dededede dededede dededede dededede +82030090: dededede dededede dededede dededede +820300a0: dededede dededede dededede dededede +820300b0: dededede dededede dededede dededede +820300c0: dededede dededede dededede dededede +820300d0: dededede dededede dededede dededede +820300e0: dededede dededede dededede dededede +820300f0: dededede dededede dededede dededede -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv2 3/5] qspi/spi: Add AM43xx specifics changes
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/ti_qspi.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482..5666250 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -11,6 +11,8 @@
#include asm/arch/omap.h
#include malloc.h
#include spi.h
+#include asm/gpio.h
+#include asm/omap_gpio.h
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT200
@@ -39,7 +41,8 @@
#define MM_SWITCH 0x01
#define MEM_CS 0x100
#define MEM_CS_UNSELECT 0xf0ff
-#define MMAP_START_ADDR 0x5c00
+#define MMAP_START_ADDR_DRA0x5c00
+#define MMAP_START_ADDR_AM43x 0x3000
#define CORE_CTRL_IO0x4a002558
#define QSPI_CMD_READ (0x3 0)
@@ -99,7 +102,11 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave
*qslave)
struct spi_slave *slave = qslave-slave;
u32 memval = 0;
- slave-memory_map = (void *)MMAP_START_ADDR;
+#ifdef CONFIG_DRA7XX
+ slave-memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ slave-memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@@ -165,6 +172,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
{
struct ti_qspi_slave *qslave;
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, qspi_gpio);
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
if (!qslave) {
printf(SPI_error: Fail to allocate ti_qspi_slave\n);
@@ -229,7 +241,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
const uchar *txp = dout;
uchar *rxp = din;
uint status;
- int timeout, val;
+ int timeout;
+
+#ifdef CONFIG_DRA7XX
+ int val;
+#endif
debug(spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n,
slave-bus, slave-cs, bitlen, words, flags);
@@ -237,15 +253,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
/* Setup mmap flags */
if (flags SPI_XFER_MMAP) {
writel(MM_SWITCH, qslave-base-memswitch);
+#ifdef CONFIG_DRA7XX
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
} else if (flags SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, qslave-base-memswitch);
+#ifdef CONFIG_DRA7XX
val = readl(CORE_CTRL_IO);
val = MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
}
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 3/5] sf: macronix: Add support for MX66L51235F
On Thursday 19 December 2013 12:21 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com wrote:
From: Jagannadha Sutradharudu Tekijagannadha.sutradharudu-t...@xilinx.com
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/sf_probe.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 5eb8ffe..874ef8c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -68,6 +68,7 @@ static const struct spi_flash_params spi_flash_params_table[]
= {
{MX25L25635F,0xc22019, 0x0, 64 * 1024, 512,
0},
{MX25L51235F,0xc2201A, 0x0, 64 * 1024, 1024,
0},
{MX25L12855E,0xc22618, 0x0, 64 * 1024, 256,
0},
+ {MX66L51235F,0xc2201a, 0x0, 64 * 1024, 1024,
0},
What is this - this part is already available is int it?
I switched to your master branch and could not see this part added.
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
{S25FL008A, 0x010213, 0x0, 64 * 1024,16,
0},
@@ -207,6 +208,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-page_size = (ext_jedec == 0x4d00) ? 512 : 256;
flash-sector_size = params-sector_size;
flash-size = flash-sector_size * params-nr_sectors;
+ flash-memory_map = spi-memory_map;
This change is also there - please check.
Yes, this is there.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 5/5] am43xx: add delay before xfer
On Thursday 19 December 2013 12:17 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
Hi Jagan,
This patch seems to be necessary for read/write.
I tested by changing few timing variables, but it did not help.
The same driver works on J6 with a differnet flash(S25FL256S).
Is any one tested macronix flash at uboot?
Delay must be for macronix?
or common for all flashes.
For macronix.
I haven't tested macronix
drivers/spi/ti_qspi.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5666250..aa7b6ae 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -285,6 +285,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
qslave-cmd |= QSPI_3_PIN;
qslave-cmd |= 0xfff;
+#ifdef CONFIG_AM43XX
+ udelay(100);
+#endif
while (words--) {
if (txp) {
debug(tx cmd %08x dc %08x data %02x\n,
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/2] misc fix for memory mapped support, dra config
Jagan, On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote: Hi Jagan, Here are the miscellaneous fix and config update for dra7 qspi flash. Patch series adds: Add BAR config in dra7 config file. Set spi controller device control registers before doing a memory mapped read. Patches available here: git://gitorious.org/u-boot-shared/u-boot-qspi.git debug_dra_qspi Tested on dra7 evm with qspi boot. Sourav Poddar (2): config: dra7_evm: Add Bank Address Register(BAR) config driver: mtd: sf_ops: claim bus while doing memcpy drivers/mtd/spi/sf_ops.c |6 ++ include/configs/dra7xx_evm.h |1 + 2 files changed, 7 insertions(+), 0 deletions(-) Ping on this. This are miscellaneous fixes for dra7 qspi uboot. Can you pick this up ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 3/5] sf: macronix: Add support for MX66L51235F
On Thursday 19 December 2013 11:22 AM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 10:33 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 12:21 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Jagannadha Sutradharudu
Tekijagannadha.sutradharudu-t...@xilinx.com
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/sf_probe.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 5eb8ffe..874ef8c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -68,6 +68,7 @@ static const struct spi_flash_params
spi_flash_params_table[] = {
{MX25L25635F,0xc22019, 0x0, 64 * 1024, 512,
0},
{MX25L51235F,0xc2201A, 0x0, 64 * 1024, 1024,
0},
{MX25L12855E,0xc22618, 0x0, 64 * 1024, 256,
0},
+ {MX66L51235F,0xc2201a, 0x0, 64 * 1024, 1024,
0},
What is this - this part is already available is int it?
I switched to your master branch and could not see this part added.
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=commitdiff;h=28303f617a01d6663a54062852f67f8150b4c87a
Looks like its a name change, mine is MX66L..with same property
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 5/5] am43xx: add delay before xfer
On Thursday 19 December 2013 11:24 AM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 10:35 AM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:17 AM, Jagan Teki wrote: On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddarsourav.pod...@ti.com wrote: Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Signed-off-by: Sourav Poddarsourav.pod...@ti.com --- Hi Jagan, This patch seems to be necessary for read/write. I tested by changing few timing variables, but it did not help. The same driver works on J6 with a differnet flash(S25FL256S). Is any one tested macronix flash at uboot? Delay must be for macronix? or common for all flashes. For macronix. All kind of micron parts or any specific.. bcz this delay seems to be not- a reasonable. that I am not sure as I have only one macronix flash to test with I haven't tested macronix drivers/spi/ti_qspi.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5666250..aa7b6ae 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -285,6 +285,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave-cmd |= QSPI_3_PIN; qslave-cmd |= 0xfff; +#ifdef CONFIG_AM43XX + udelay(100); +#endif ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/2] misc fix for memory mapped support, dra config
On Thursday 19 December 2013 11:41 AM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 10:36 AM, Sourav Poddarsourav.pod...@ti.com wrote: Jagan, On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote: Hi Jagan, Here are the miscellaneous fix and config update for dra7 qspi flash. Patch series adds: Add BAR config in dra7 config file. Set spi controller device control registers before doing a memory mapped read. Patches available here: git://gitorious.org/u-boot-shared/u-boot-qspi.git debug_dra_qspi Tested on dra7 evm with qspi boot. Sourav Poddar (2): config: dra7_evm: Add Bank Address Register(BAR) config driver: mtd: sf_ops: claim bus while doing memcpy drivers/mtd/spi/sf_ops.c |6 ++ include/configs/dra7xx_evm.h |1 + 2 files changed, 7 insertions(+), 0 deletions(-) Ping on this. This are miscellaneous fixes for dra7 qspi uboot. Can you pick this up ? What is this series - I couldn't find it on patchwork. You sent a series with 0/5 and these two are part of that is it? This is a differnet series for dra7 soc, it has miscellaneous cleanup and fixes. The other series (0/5) is for qspi on am43x soc ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/2] misc fix for memory mapped support, dra config
On Thursday 19 December 2013 12:25 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 11:48 AM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 11:41 AM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 10:36 AM, Sourav Poddarsourav.pod...@ti.com wrote: Jagan, On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote: Hi Jagan, Here are the miscellaneous fix and config update for dra7 qspi flash. Patch series adds: Add BAR config in dra7 config file. Set spi controller device control registers before doing a memory mapped read. Patches available here: git://gitorious.org/u-boot-shared/u-boot-qspi.git debug_dra_qspi Tested on dra7 evm with qspi boot. Sourav Poddar (2): config: dra7_evm: Add Bank Address Register(BAR) config driver: mtd: sf_ops: claim bus while doing memcpy drivers/mtd/spi/sf_ops.c |6 ++ include/configs/dra7xx_evm.h |1 + 2 files changed, 7 insertions(+), 0 deletions(-) Ping on this. This are miscellaneous fixes for dra7 qspi uboot. Can you pick this up ? What is this series - I couldn't find it on patchwork. You sent a series with 0/5 and these two are part of that is it? This is a differnet series for dra7 soc, it has miscellaneous cleanup and fixes. The other series (0/5) is for qspi on am43x soc Applied to u-boot-spi/master Thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote: On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? Please send the next version patches - fix the comments as we discussed so far. I will send the next version. But, what about the delay patch, I tried other stuffs but could not see any thing that helps. So, I will send the delay patch also as of now, to make it work out of mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote: On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com wrote: On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote: On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com wrote: Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? Please send the next version patches - fix the comments as we discussed so far. I will send the next version. But, what about the delay patch, I tried other stuffs but could not see any thing that helps. So, I will send the delay patch also as of now, to make it work out of mainline. I am some how OK with that as that change is in ur driver.. Just try this change /* FIXME: comments here... */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif And also write the bug log on commit message(means with out delay) Try to ass the testing logs on doc/ - for each time you tested a new flash or new driver. Ok. I will do as you suggest above, Will add a doc/ for am43x also as it is there for dra. Thanks, Sourav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/2] misc fix for memory mapped support, dra config
Hi Jagan, On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote: Hi Jagan, Here are the miscellaneous fix and config update for dra7 qspi flash. Patch series adds: Add BAR config in dra7 config file. Set spi controller device control registers before doing a memory mapped read. Patches available here: git://gitorious.org/u-boot-shared/u-boot-qspi.git debug_dra_qspi Tested on dra7 evm with qspi boot. Can these patches be picked? Sourav Poddar (2): config: dra7_evm: Add Bank Address Register(BAR) config driver: mtd: sf_ops: claim bus while doing memcpy drivers/mtd/spi/sf_ops.c |6 ++ include/configs/dra7xx_evm.h |1 + 2 files changed, 7 insertions(+), 0 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
Hi Jagan, On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) If these patches seems fine to you, can these be picked? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 0/2] misc fix for memory mapped support, dra config
Hi Jagan, Here are the miscellaneous fix and config update for dra7 qspi flash. Patch series adds: Add BAR config in dra7 config file. Set spi controller device control registers before doing a memory mapped read. Patches available here: git://gitorious.org/u-boot-shared/u-boot-qspi.git debug_dra_qspi Tested on dra7 evm with qspi boot. Sourav Poddar (2): config: dra7_evm: Add Bank Address Register(BAR) config driver: mtd: sf_ops: claim bus while doing memcpy drivers/mtd/spi/sf_ops.c |6 ++ include/configs/dra7xx_evm.h |1 + 2 files changed, 7 insertions(+), 0 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 2/2] driver: mtd: sf_ops: claim bus while doing memcpy
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Tested-by: Yebio Mesfin ymes...@ti.com
---
drivers/mtd/spi/sf_ops.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 108665f..e316a69 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -273,9 +273,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: unable to claim SPI bus\n);
+ return ret;
+ }
spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP);
memcpy(data, flash-memory_map + offset, len);
spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+ spi_release_bus(flash-spi);
return 0;
}
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 1/2] config: dra7_evm: Add Bank Address Register(BAR) config
Add config to support bank address register. Signed-off-by: Sourav Poddar sourav.pod...@ti.com Tested-by: Yebio Mesfin ymes...@ti.com --- include/configs/dra7xx_evm.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 1600131..46cc6db 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -54,6 +54,7 @@ #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_BAR #define CONFIG_TI_SPI_MMAP #define CONFIG_SF_DEFAULT_SPEED4800 #define CONFIG_DEFAULT_SPI_MODESPI_MODE_3 -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 3/5] sf: macronix: Add support for MX66L51235F
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spi/sf_probe.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 5eb8ffe..874ef8c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -68,6 +68,7 @@ static const struct spi_flash_params spi_flash_params_table[]
= {
{MX25L25635F,0xc22019, 0x0, 64 * 1024, 512,
0},
{MX25L51235F,0xc2201A, 0x0, 64 * 1024, 1024,
0},
{MX25L12855E,0xc22618, 0x0, 64 * 1024, 256,
0},
+ {MX66L51235F,0xc2201a, 0x0, 64 * 1024, 1024,
0},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
{S25FL008A, 0x010213, 0x0, 64 * 1024,16,
0},
@@ -207,6 +208,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-page_size = (ext_jedec == 0x4d00) ? 512 : 256;
flash-sector_size = params-sector_size;
flash-size = flash-sector_size * params-nr_sectors;
+ flash-memory_map = spi-memory_map;
/* Compute erase sector and command */
if (params-flags SECT_4K) {
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 1/5] am43xx: add qspi support
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 97c00b4..fb654bb 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -98,6 +98,7 @@ void enable_basic_clocks(void)
cmper-emiffwclkctrl,
cmper-emifclkctrl,
cmper-otfaemifclkctrl,
+ cmper-qspiclkctrl,
0
};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 23af125..6537b30 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -332,7 +332,9 @@ struct cm_perpll {
unsigned int mcasp1clkctrl; /* offset 0x240 */
unsigned int resv11;
unsigned int mmc2clkctrl; /* offset 0x248 */
- unsigned int resv12[5];
+ unsigned int resv12[3];
+ unsigned int qspiclkctrl; /* offset 0x258 */
+ unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
unsigned int resv13[103];
unsigned int l4lsclkstctrl; /* offset 0x400 */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h
b/arch/arm/include/asm/arch-am33xx/omap.h
index 10f05c9..7b2f193 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -29,5 +29,6 @@
#define SRAM_SCRATCH_SPACE_ADDR0x4033C000
#define AM4372_BOARD_NAME_STARTSRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE 0x4790
#endif
#endif
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 5/5] am43xx: add delay before xfer
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Hi Jagan,
This patch seems to be necessary for read/write.
I tested by changing few timing variables, but it did not help.
The same driver works on J6 with a differnet flash(S25FL256S).
Is any one tested macronix flash at uboot?
drivers/spi/ti_qspi.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5666250..aa7b6ae 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -285,6 +285,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
qslave-cmd |= QSPI_3_PIN;
qslave-cmd |= 0xfff;
+#ifdef CONFIG_AM43XX
+ udelay(100);
+#endif
while (words--) {
if (txp) {
debug(tx cmd %08x dc %08x data %02x\n,
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 2/5] am437x_epos_evm: add SPL API, QSPI, and serial flash support
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/am43xx/mux.c| 11 +++
include/configs/am43xx_evm.h | 20
2 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 341214d..ff12981 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -35,6 +35,16 @@ static struct module_pin_mux i2c0_pin_mux[] = {
{-1},
};
+static struct module_pin_mux qspi_pin_mux[] = {
+ {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /*
QSPI_D0 */
+ {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /*
QSPI_D1 */
+ {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+ {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /*
QSPI_D3 */
+ {-1},
+};
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
@@ -44,6 +54,7 @@ void enable_board_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(qspi_pin_mux);
}
void enable_i2c0_pin_mux(void)
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 456dcaa..f28ad41 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -79,6 +79,26 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_QSPI_SEL_GPIO 48
+#define CONFIG_SF_DEFAULT_SPEED4800
+#define CONFIG_DEFAULT_SPI_MODESPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
loadaddr=0x8020\0 \
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCH 4/5] qspi/spi: Add AM43xx specifics changes
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/ti_qspi.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482..5666250 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -11,6 +11,8 @@
#include asm/arch/omap.h
#include malloc.h
#include spi.h
+#include asm/gpio.h
+#include asm/omap_gpio.h
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT200
@@ -39,7 +41,8 @@
#define MM_SWITCH 0x01
#define MEM_CS 0x100
#define MEM_CS_UNSELECT 0xf0ff
-#define MMAP_START_ADDR 0x5c00
+#define MMAP_START_ADDR_DRA0x5c00
+#define MMAP_START_ADDR_AM43x 0x3000
#define CORE_CTRL_IO0x4a002558
#define QSPI_CMD_READ (0x3 0)
@@ -99,7 +102,11 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave
*qslave)
struct spi_slave *slave = qslave-slave;
u32 memval = 0;
- slave-memory_map = (void *)MMAP_START_ADDR;
+#ifdef CONFIG_DRA7XX
+ slave-memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ slave-memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@@ -165,6 +172,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
{
struct ti_qspi_slave *qslave;
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, qspi_gpio);
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
if (!qslave) {
printf(SPI_error: Fail to allocate ti_qspi_slave\n);
@@ -229,7 +241,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
const uchar *txp = dout;
uchar *rxp = din;
uint status;
- int timeout, val;
+ int timeout;
+
+#ifdef CONFIG_DRA7XX
+ int val;
+#endif
debug(spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n,
slave-bus, slave-cs, bitlen, words, flags);
@@ -237,15 +253,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
/* Setup mmap flags */
if (flags SPI_XFER_MMAP) {
writel(MM_SWITCH, qslave-base-memswitch);
+#ifdef CONFIG_DRA7XX
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
} else if (flags SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, qslave-base-memswitch);
+#ifdef CONFIG_DRA7XX
val = readl(CORE_CTRL_IO);
val = MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
}
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCH 0/5] qspi: Add AM437x support
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote: The patch series add support for enabling qspi on AM43xx at uboot. Testing done: - Wrote a uImage to the flash, read it back and boot the kernel. Jagannadha Sutradharudu Teki (1): sf: macronix: Add support for MX25L51235F Sourav Poddar (4): am43xx: add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support qspi/spi: Add AM43xx specifics changes am43xx: add delay before xfer arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 + arch/arm/include/asm/arch-am33xx/cpu.h |4 +++- arch/arm/include/asm/arch-am33xx/omap.h |1 + board/ti/am43xx/mux.c| 11 +++ drivers/mtd/spi/sf_probe.c |2 ++ drivers/spi/ti_qspi.c| 29 ++--- include/configs/am43xx_evm.h | 20 7 files changed, 64 insertions(+), 4 deletions(-) The above series depends on this patch series: http://www.mail-archive.com/u-boot@lists.denx.de/msg125001.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: add TI QSPI driver
On Monday 07 October 2013 12:33 PM, Jagannadha Sutradharudu Teki wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
Signed-off-by: Jagannadha Sutradharudu Tekijaga...@xilinx.com
---
Changes for v6:
- Added ti related comments
- Created ti spec func for ti code
- Fixed few checkpatch.pl errors
- Rearranged the code.
v4-v5:
- use tabs wherever required.
- remove stray character in license line
- remove get_spi_bus api
- move device control stuff to spi_claim_bus
- Put prints according to the reference driver from jagan
- Move macros below header.files.
drivers/spi/Makefile | 1 +
drivers/spi/ti_qspi.c | 313 ++
2 files changed, 314 insertions(+)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..91a37aa
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,313 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+/* ti qpsi register bit masks */
+#define QSPI_TIMEOUT200
+#define QSPI_FCLK 19200
+/* clock control */
+#define QSPI_CLK_EN (1 31)
+#define QSPI_CLK_DIV_MAX0x
+/* command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n)((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL(1 16)
+#define QSPI_WR_SNGL(2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD(7 16)
+/* device control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+/* status */
+#define QSPI_WC (1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT 0xf0ff
+#define MMAP_START_ADDR 0x5c00
+#define CORE_CTRL_IO0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES (0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL (0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS (0x0 24)
+
+/* ti qspi register set */
+struct ti_qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 intr_status_raw_set;
+ u32 intr_status_enabled_clear;
+ u32 intr_enable_set;
+ u32 intr_enable_clear;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 spi_clock_cntrl;
+ u32 spi_dc;
+ u32 spi_cmd;
+ u32 spi_status;
+ u32 spi_data;
+ u32 spi_setup0;
+ u32 spi_setup1;
+ u32 spi_setup2;
+ u32 spi_setup3;
+ u32 spi_switch;
+ u32 spi_data1;
+ u32 spi_data2;
+ u32 spi_data3;
+};
+
+/* ti qspi slave */
+struct ti_qspi_slave {
+ struct spi_slave slave;
+ struct ti_qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_slave, slave);
+}
+
+#ifdef CONFIG_TI_SPI_MMAP
+static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+{
+ struct spi_slave *slave =qslave-slave;
+ u32 memval = 0;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+
[U-Boot] [UBOOT][PATCHv6 2/6] armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8..a1b249e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params
per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},/* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support.
This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. Patches are available at: git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7 Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Sourav Poddar (3): armv7: hw_data: change clock divider setting. sf: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/omap.h |3 + arch/arm/include/asm/arch-omap5/spl.h |1 + arch/arm/include/asm/omap_common.h |1 + board/ti/dra7xx/mux_data.h | 10 + doc/SPI/README.ti_qspi_dra_test| 48 + doc/SPI/README.ti_qspi_flash | 47 + drivers/mtd/spi/sf_ops.c |2 + drivers/mtd/spi/sf_probe.c |1 + drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 311 include/configs/dra7xx_evm.h | 19 ++ include/spi.h |3 + 14 files changed, 457 insertions(+), 1 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_dra_test create mode 100644 doc/SPI/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv6 4/6] spi: add TI QSPI driver
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
v5-v6:
- Added ti related comments
- Created ti spec func for ti code
- Fixed few checkpatch.pl errors
- Rearranged the code.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 311 +
2 files changed, 312 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..5a5b482
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,311 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/omap.h
+#include malloc.h
+#include spi.h
+
+/* ti qpsi register bit masks */
+#define QSPI_TIMEOUT200
+#define QSPI_FCLK 19200
+/* clock control */
+#define QSPI_CLK_EN (1 31)
+#define QSPI_CLK_DIV_MAX0x
+/* command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n)((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL(1 16)
+#define QSPI_WR_SNGL(2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD(7 16)
+/* device control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+/* status */
+#define QSPI_WC (1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT 0xf0ff
+#define MMAP_START_ADDR 0x5c00
+#define CORE_CTRL_IO0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES (0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL (0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS (0x0 24)
+
+/* ti qspi register set */
+struct ti_qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 int_stat_raw;
+ u32 int_stat_en;
+ u32 int_en_set;
+ u32 int_en_ctlr;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 clk_ctrl;
+ u32 dc;
+ u32 cmd;
+ u32 status;
+ u32 data;
+ u32 setup0;
+ u32 setup1;
+ u32 setup2;
+ u32 setup3;
+ u32 memswitch;
+ u32 data1;
+ u32 data2;
+ u32 data3;
+};
+
+/* ti qspi slave */
+struct ti_qspi_slave {
+ struct spi_slave slave;
+ struct ti_qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_slave, slave);
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+{
+ struct spi_slave *slave = qslave-slave;
+ u32 memval = 0;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+ QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS;
+
+ writel(memval, qslave-base-setup0);
+}
+
+static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ uint clk_div;
+
+ debug(ti_spi_set_speed: hz: %d, clock divider %d\n, hz, clk_div);
+
+ if (!hz
[U-Boot] [UBOOT][PATCHv6 1/6] omap5: add qspi support
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch/arm/include/asm/arch-omap5/spl.h |1 +
arch/arm/include/asm/omap_common.h |1 +
5 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index fbbc486..c00bfb8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)-cm_gmac_gmac_clkctrl,
#endif
+
+#ifdef CONFIG_TI_QSPI
+ (*prcm)-cm_l4per_qspi_clkctrl,
+#endif
0
};
@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)-cm_l4per_qspi_clkctrl, (124));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d..0b1bb46 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl= 0x4a009820,
.cm_l4per_mmcsd4_clkctrl= 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d3..414d37a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -61,6 +61,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x5000
+/* QSPI */
+#define QSPI_BASE 0x4B30
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index fe8b0c0..57f0de5 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -15,6 +15,7 @@
#define BOOT_DEVICE_MMC15
#define BOOT_DEVICE_MMC26
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 5e2f027..f865c14 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -266,6 +266,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv6 3/6] sf: Add memory mapped read support
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of memory_map flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v5-v6:
Add proper tab space
drivers/mtd/spi/sf_ops.c |2 ++
drivers/mtd/spi/sf_probe.c |1 +
include/spi.h |3 +++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..2396e22 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
return 0;
}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 1525636..6aa7086 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -203,6 +203,7 @@ struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode)
flash-page_size = (ext_jedec == 0x4d00) ? 512 : 256;
flash-sector_size = params-sector_size;
flash-size = flash-sector_size * params-nr_sectors;
+ flash-memory_map = spi-memory_map;
/* Compute erase sector and command */
if (params-flags SECT_4K) {
diff --git a/include/spi.h b/include/spi.h
index c44ebe8..c2086fc 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,6 +27,8 @@
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01/* Assert CS before transfer */
#define SPI_XFER_END 0x02/* Deassert CS after transfer */
+#define SPI_XFER_MMAP 0x08/* Memory Mapped start */
+#define SPI_XFER_MMAP_END 0x10/* Memory Mapped End */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -46,6 +48,7 @@ struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int max_write_size;
+ void *memory_map;
};
/**
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv6 6/6] README: qspi usecase and testing documentation.
Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- doc/SPI/README.ti_qspi_dra_test | 48 +++ doc/SPI/README.ti_qspi_flash| 47 ++ 2 files changed, 95 insertions(+), 0 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_dra_test create mode 100644 doc/SPI/README.ti_qspi_flash diff --git a/doc/SPI/README.ti_qspi_dra_test b/doc/SPI/README.ti_qspi_dra_test new file mode 100644 index 000..fe37857 --- /dev/null +++ b/doc/SPI/README.ti_qspi_dra_test @@ -0,0 +1,48 @@ +- + Simple steps used to test the QSPI at U-Boot +- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +-- +Boot from another medium like MMC +-- + +U-Boot# mmc dev 0 +mmc0 is current device +U-Boot# fatload mmc 0 0x8200 MLO +reading MLO +55872 bytes read in 8 ms (6.7 MiB/s) +U-Boot# fatload mmc 0 0x8300 u-boot.img +reading u-boot.img +248600 bytes read in 19 ms (12.5 MiB/s) + +-- +Commands to erase/write u-boot/mlo to flash device +-- +U-Boot# sf probe 0 +SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c00 +SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR +U-Boot# sf erase 0 0x1 +SF: 65536 bytes @ 0x0 Erased: OK +U-Boot# sf erase 0x2 0x1 +SF: 65536 bytes @ 0x2 Erased: OK +U-Boot# sf erase 0x3 0x1 +SF: 65536 bytes @ 0x3 Erased: OK +U-Boot# sf erase 0x4 0x1 +SF: 65536 bytes @ 0x4 Erased: OK +U-Boot# sf erase 0x5 0x1 +SF: 65536 bytes @ 0x5 Erased: OK +U-Boot# sf erase 0x6 0x1 +SF: 65536 bytes @ 0x6 Erased: OK +U-Boot# sf write 8200 0 0x1 +SF: 65536 bytes @ 0x0 Written: OK +U-Boot# sf write 8300 0x2 0x6 +SF: 393216 bytes @ 0x2 Written: OK + +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x2 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash new file mode 100644 index 000..1b86d01 --- /dev/null +++ b/doc/SPI/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +-- + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +--- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +--- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +--- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +-- +drivers/qspi/ti_qspi.c +- Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +--- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv6 5/6] dra7xx_evm: add SPL API, QSPI, and serial flash support
From: Matt Porter matt.por...@linaro.org
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v5-v6:
change MMAP name to amore readable name.
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 19 +++
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 0a86594..6965cc5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] =
{
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
+ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
+ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A18, (M1)}, /* QSPI1_SCLK */
+ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
+ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
+ {GPMC_CS2, (IEN | PTU | PDIS | M1)},/* QSPI1_CS0 */
+ {GPMC_CS3, (IEN | PTU | PDIS | M1)},/* QSPI1_CS1*/
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4fbe768..f9cfd18 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,23 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR2
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_SPEED4800
+#define CONFIG_DEFAULT_SPI_MODESPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+
#endif /* __CONFIG_DRA7XX_EVM_H */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 5/8] drivers: mtd: spi: Modify read/write command for sfl256s flash.
On Monday 07 October 2013 05:51 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 8:46 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Wednesday 07 August 2013 08:35 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 5:34 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 07 August 2013 05:21 PM, Jagan Teki wrote:
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing
regression
after 4k bytes, as a result doing a page by page read. Its
happening,
because
ti qpsi controller CS will get de asserted after 4096 bytes.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 32
+++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c
b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..5f8db7b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash, u32 offset,
else
read_len = remain_len;
+#ifdef CONFIG_TI_QSPI
+unsigned long page_addr, byte_addr, page_size;
+size_t chunk_len, actual;
+int ret = 0;
+
+page_size = flash-page_size;
+page_addr = offset / page_size;
+byte_addr = offset % page_size;
+
+for (actual = 0; actual read_len; actual += chunk_len)
{
+chunk_len = min(read_len - actual, page_size -
byte_addr);
+
+cmd[1] = page_addr 8;
+cmd[2] = page_addr;
+cmd[3] = byte_addr;
+
+ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+data + actual, chunk_len);
+if (ret 0) {
+debug(SF: read failed);
+break;
+}
+
+byte_addr += chunk_len;
+if (byte_addr == page_size) {
+page_addr++;
+byte_addr = 0;
+}
+}
+#else
spi_flash_addr(offset, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
@@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash,
u32 offset,
debug(SF: read failed\n);
break;
}
-
+#endif
offset += read_len;
len -= read_len;
data += read_len;
Elaborating a bit more on this,
There is a constrain on our hardware, which goes like this..
As soon as the words transfered is 4096 bytes, the CS gets deasserted
automatically.
As a result of this bottleneck, I am not able to use the current use
read
api in mtd framework.
This requires me to send the read command every time in range upto
4096
bytes only.
To overcome this, I have updated the mtd read based on TI_QSPI config
as
done above.
[Jagan]:
Do you have any suggestion of dealing this in a better way?
I don't see a way to get around this apart from updating mtd read
depending on TI_QSPI config.
Any inputs on this?
Any suggestions on the patch?
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Yes, this part is pretty much working as with other s25fl.
Can you point me the respective controller driver for this.
Thanks for the response.
This is the link to uboot patches which I submitted to uboot mailing
list.
http://patchwork.ozlabs.org/patch/260989/
http://patchwork.ozlabs.org/patch/260990/
http://patchwork.ozlabs.org/patch/260991/
http://patchwork.ozlabs.org/patch/260992/
http://patchwork.ozlabs.org/patch/260994/
http://patchwork.ozlabs.org/patch/260993/
http://patchwork.ozlabs.org/patch/260996/
http://patchwork.ozlabs.org/patch/260995/
Above are the links to uboot patches containing all def configs and uboot
ti
qspi driver.
As communicated earlier, there is a limitation in our qspi controller
driver, wherein after every
4096 bytes CS gets de asserted. So, I had to modify the above read
framework
to do a page read.
Need better way to handle this limitation, so that the above patch series
can get upstreamed.
Does linux support this ti_qspi, please point the defconfig if you have.
Patches for linux is under review and still not mainlined.
https://patchwork.kernel.org/patch/2838342/
Thanks, please give me some time I will look at these and let u know
early next week.
Thanks!!
You still see this issue.
Please ignore this mail thread. This was due to some ip limitation.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 5/8] drivers: mtd: spi: Modify read/write command for sfl256s flash.
On Monday 07 October 2013 05:59 PM, Jagan Teki wrote:
On Mon, Oct 7, 2013 at 5:58 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Monday 07 October 2013 05:51 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 8:46 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Wednesday 07 August 2013 08:35 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 5:34 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 07 August 2013 05:21 PM, Jagan Teki wrote:
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing
regression
after 4k bytes, as a result doing a page by page read. Its
happening,
because
ti qpsi controller CS will get de asserted after 4096 bytes.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 32
+++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c
b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..5f8db7b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash, u32 offset,
else
read_len = remain_len;
+#ifdef CONFIG_TI_QSPI
+unsigned long page_addr, byte_addr, page_size;
+size_t chunk_len, actual;
+int ret = 0;
+
+page_size = flash-page_size;
+page_addr = offset / page_size;
+byte_addr = offset % page_size;
+
+for (actual = 0; actual read_len; actual +=
chunk_len)
{
+chunk_len = min(read_len - actual, page_size -
byte_addr);
+
+cmd[1] = page_addr 8;
+cmd[2] = page_addr;
+cmd[3] = byte_addr;
+
+ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+data + actual, chunk_len);
+if (ret 0) {
+debug(SF: read failed);
+break;
+}
+
+byte_addr += chunk_len;
+if (byte_addr == page_size) {
+page_addr++;
+byte_addr = 0;
+}
+}
+#else
spi_flash_addr(offset, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
@@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash,
u32 offset,
debug(SF: read failed\n);
break;
}
-
+#endif
offset += read_len;
len -= read_len;
data += read_len;
Elaborating a bit more on this,
There is a constrain on our hardware, which goes like this..
As soon as the words transfered is 4096 bytes, the CS gets
deasserted
automatically.
As a result of this bottleneck, I am not able to use the current
use
read
api in mtd framework.
This requires me to send the read command every time in range upto
4096
bytes only.
To overcome this, I have updated the mtd read based on TI_QSPI
config
as
done above.
[Jagan]:
Do you have any suggestion of dealing this in a better way?
I don't see a way to get around this apart from updating mtd read
depending on TI_QSPI config.
Any inputs on this?
Any suggestions on the patch?
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Yes, this part is pretty much working as with other s25fl.
Can you point me the respective controller driver for this.
Thanks for the response.
This is the link to uboot patches which I submitted to uboot mailing
list.
http://patchwork.ozlabs.org/patch/260989/
http://patchwork.ozlabs.org/patch/260990/
http://patchwork.ozlabs.org/patch/260991/
http://patchwork.ozlabs.org/patch/260992/
http://patchwork.ozlabs.org/patch/260994/
http://patchwork.ozlabs.org/patch/260993/
http://patchwork.ozlabs.org/patch/260996/
http://patchwork.ozlabs.org/patch/260995/
Above are the links to uboot patches containing all def configs and
uboot
ti
qspi driver.
As communicated earlier, there is a limitation in our qspi controller
driver, wherein after every
4096 bytes CS gets de asserted. So, I had to modify the above read
framework
to do a page read.
Need better way to handle this limitation, so that the above patch
series
can get upstreamed.
Does linux support this ti_qspi, please point the defconfig if you
have.
Patches for linux is under review and still not mainlined.
https://patchwork.kernel.org/patch/2838342/
Thanks, please give me some time I will look at these and let u know
early next week.
Thanks!!
You still see this issue.
Please ignore this mail thread. This was due to some ip limitation.
OK.. Thread ends!
Anyways, we have move much ahead and there is already a v6 which I posted
Re: [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support.
On Monday 07 October 2013 08:01 PM, Jagan Teki wrote: On Mon, Oct 7, 2013 at 3:52 PM, Sourav Poddarsourav.pod...@ti.com wrote: This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. Patches are available at: git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7 Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Sourav Poddar (3): armv7: hw_data: change clock divider setting. sf: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/omap.h |3 + arch/arm/include/asm/arch-omap5/spl.h |1 + arch/arm/include/asm/omap_common.h |1 + board/ti/dra7xx/mux_data.h | 10 + doc/SPI/README.ti_qspi_dra_test| 48 + doc/SPI/README.ti_qspi_flash | 47 + drivers/mtd/spi/sf_ops.c |2 + drivers/mtd/spi/sf_probe.c |1 + drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 311 include/configs/dra7xx_evm.h | 19 ++ include/spi.h |3 + 14 files changed, 457 insertions(+), 1 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_dra_test create mode 100644 doc/SPI/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c Applied to u-boot-spi/master Thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Uboot][PATCH] drivers: spi: macronix: Add MX66L51235L data
On Thursday 03 October 2013 09:19 PM, Jagan Teki wrote:
Hi Sourav,
Can you test this macronix part w.r.t latest code base on
u-boot-spi.git with master-probe branch.
Please let me know about any issues/concerns.
Regarding the number of blocks, it should be 1024 only.
I will do other testing asap and let you know. This particular flash
is on another SOC so I will send that SOC specific qspi data after
testing it
with the subject patch.
On Tue, Aug 27, 2013 at 2:48 PM, Jagan Tekijagannadh.t...@gmail.com wrote:
Hi
On Tue, Aug 27, 2013 at 11:15 AM, Sourav Poddarsourav.pod...@ti.com wrote:
Add support for macronix MX66L51235L flash device.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/macronix.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c
index 70435eb..5a528c3 100644
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -61,6 +61,11 @@ static const struct macronix_spi_flash_params
macronix_spi_flash_table[] = {
.nr_blocks = 256,
.name = MX25L12855E,
},
+ {
+ .idcode = 0x201a,
+ .nr_blocks = 512,
+ .name = MX66L51235L,
+ },
};
Can you check the similar patch
http://patchwork.ozlabs.org/patch/262928/
Please confirm about nr_blocks?
Also have u tested with latest spi_flash code, since ur part is 64MB
must require a BAR to access entire memory.?
http://patchwork.ozlabs.org/patch/262929/
Let me know for any concerns.
--
Thanks,
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 3/6] driver: mtd: spi: Add memory mapped read support
On Sunday 06 October 2013 03:03 PM, Gerhard Sittig wrote:
On Fri, Oct 04, 2013 at 20:21 +0530, Sourav Poddar wrote:
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..bee4128 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
return 0;
}
Feedback has been sent before, but I'm afraid the motivation
wasn't received appropriately.
Sorry, If I missed any mails.
Shouldn't the memcpy() call be surrounded by _MAP and _MAP_END
(please note the _END in the second spi_xfer() invocation)? The
current patch doesn't close the transfer, which appears to pass
tests but isn't correct.
Yes, you are correct. Second xfer should be with a END flag.
I will add it in my next version, thanks for pointing out.
virtually yours
Gerhard Sittig
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave-cmd = 0;
+ qslave-cmd |= QSPI_WLEN(8);
+ qslave-cmd |= QSPI_EN_CS(slave-cs);
+ if (flags SPI_3WIRE)
+ qslave-cmd |= QSPI_3_PIN;
+ qslave-cmd |= 0xfff;
Functionality wise it wont effect. I am open to what you
suggest here, whether to move it or not.
Though, just one thing you should note here, is that the
above code just mask the cmd register bits. The actual
cmd register write happens inside while loop and only when
that write happens, then the cs gets activated.
So, above code does not activate the cs, it just prepare the mask
that will enable cs later.
On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized
in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went
wrong,
I
will check.
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Sunday 06 October 2013 09:00 PM, Jagan Teki wrote:
On Sun, Oct 6, 2013 at 3:44 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave-cmd = 0;
+ qslave-cmd |= QSPI_WLEN(8);
+ qslave-cmd |= QSPI_EN_CS(slave-cs);
+ if (flags SPI_3WIRE)
+ qslave-cmd |= QSPI_3_PIN;
+ qslave-cmd |= 0xfff;
Functionality wise it wont effect. I am open to what you
suggest here, whether to move it or not.
Though, just one thing you should note here, is that the
above code just mask the cmd register bits. The actual
cmd register write happens inside while loop and only when
that write happens, then the cs gets activated.
So, above code does not activate the cs, it just prepare the mask
that will enable cs later.
OK, just park this as of now try to send next level patch-set we will
discuss more.
Ok. I am working on the next version.
On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav
Poddarsourav.pod...@ti.com
wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized
in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went
wrong,
I
will check.
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/*
[U-Boot] [UBOOT][PATCHv5 1/6] omap5: add qspi support
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch/arm/include/asm/arch-omap5/spl.h |1 +
arch/arm/include/asm/omap_common.h |1 +
5 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index fbbc486..c00bfb8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)-cm_gmac_gmac_clkctrl,
#endif
+
+#ifdef CONFIG_TI_QSPI
+ (*prcm)-cm_l4per_qspi_clkctrl,
+#endif
0
};
@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)-cm_l4per_qspi_clkctrl, (124));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d..0b1bb46 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl= 0x4a009820,
.cm_l4per_mmcsd4_clkctrl= 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d3..414d37a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -61,6 +61,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x5000
+/* QSPI */
+#define QSPI_BASE 0x4B30
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index fe8b0c0..57f0de5 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -15,6 +15,7 @@
#define BOOT_DEVICE_MMC15
#define BOOT_DEVICE_MMC26
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 5e2f027..f865c14 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -266,6 +266,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv5 0/6] Add TI qspi controller with memory mapped support.
This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. Patches are available at: git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v5 Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Sourav Poddar (3): armv7: hw_data: change clock divider setting. sf: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/omap.h |3 + arch/arm/include/asm/arch-omap5/spl.h |1 + arch/arm/include/asm/omap_common.h |1 + board/ti/dra7xx/mux_data.h | 10 + doc/SPI/README.ti_qspi_dra_test| 48 + doc/SPI/README.ti_qspi_flash | 47 + drivers/mtd/spi/sf_ops.c |2 + drivers/mtd/spi/sf_probe.c |1 + drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 318 include/configs/dra7xx_evm.h | 19 ++ include/spi.h |3 + 14 files changed, 464 insertions(+), 1 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_dra_test create mode 100644 doc/SPI/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv5 3/6] sf: Add memory mapped read support
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of memory_map flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v4-v5:
- Make memory map flag more readable by using MMAP
instead of MEM_MAP
- Correct the memory mapped exit path by adding
MMAP_END
- change the commit header to use sf.
drivers/mtd/spi/sf_ops.c |2 ++
drivers/mtd/spi/sf_probe.c |1 +
include/spi.h |3 +++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..2396e22 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
return 0;
}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 1525636..6aa7086 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -203,6 +203,7 @@ struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode)
flash-page_size = (ext_jedec == 0x4d00) ? 512 : 256;
flash-sector_size = params-sector_size;
flash-size = flash-sector_size * params-nr_sectors;
+ flash-memory_map = spi-memory_map;
/* Compute erase sector and command */
if (params-flags SECT_4K) {
diff --git a/include/spi.h b/include/spi.h
index c44ebe8..f454cae 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,6 +27,8 @@
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01/* Assert CS before transfer */
#define SPI_XFER_END 0x02/* Deassert CS after transfer */
+#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
+#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -46,6 +48,7 @@ struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int max_write_size;
+ void *memory_map;
};
/**
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv5 2/6] armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8..a1b249e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params
per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},/* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv5 5/6] dra7xx_evm: add SPL API, QSPI, and serial flash support
From: Matt Porter matt.por...@linaro.org
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 19 +++
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 0a86594..6965cc5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] =
{
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
+ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
+ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A18, (M1)}, /* QSPI1_SCLK */
+ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
+ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
+ {GPMC_CS2, (IEN | PTU | PDIS | M1)},/* QSPI1_CS0 */
+ {GPMC_CS3, (IEN | PTU | PDIS | M1)},/* QSPI1_CS1*/
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4fbe768..310c7ac 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,23 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR2
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_MMAP
+#define CONFIG_SF_DEFAULT_SPEED4800
+#define CONFIG_DEFAULT_SPI_MODESPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+
#endif /* __CONFIG_DRA7XX_EVM_H */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv5 4/6] spi: add TI QSPI driver
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Added quad read support and memory mapped support).
---
v4-v5:
- use tabs wherever required.
- remove stray character in license line
- remove get_spi_bus api
- move device control stuff to spi_claim_bus
- Put prints according to the reference driver from
jagan
- Move macros below header.files.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 318 +
2 files changed, 319 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..06b20b9
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,318 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/omap.h
+#include malloc.h
+#include spi.h
+
+#define QSPI_TIMEOUT200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN (1 31)
+#define QSPI_CLK_DIV_MAX0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n)((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL(1 16)
+#define QSPI_WR_SNGL(2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD(7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC (1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT 0xf0ff
+#define MMAP_START_ADDR 0x5c00
+#define CORE_CTRL_IO0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES (0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL (0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS (0x0 24)
+
+struct qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 intr_status_raw_set;
+ u32 intr_status_enabled_clear;
+ u32 intr_enable_set;
+ u32 intr_enable_clear;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 spi_clock_cntrl;
+ u32 spi_dc;
+ u32 spi_cmd;
+ u32 spi_status;
+ u32 spi_data;
+ u32 spi_setup0;
+ u32 spi_setup1;
+ u32 spi_setup2;
+ u32 spi_setup3;
+ u32 spi_switch;
+ u32 spi_data1;
+ u32 spi_data2;
+ u32 spi_data3;
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+void spi_set_up_spi_register(struct qspi_slave *qslave)
+{
+ u32 memval = 0;
+ struct spi_slave *slave = qslave-slave;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= (QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL |
+ QSPI_CMD_WRITE
[U-Boot] [UBOOT][PATCHv5 6/6] README: qspi usecase and testing documentation.
Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- v4-v5: - Move the doc to doc/SPI - testing details formatted to actual testing logs done on the board. doc/SPI/README.ti_qspi_dra_test | 48 +++ doc/SPI/README.ti_qspi_flash| 47 ++ 2 files changed, 95 insertions(+), 0 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_dra_test create mode 100644 doc/SPI/README.ti_qspi_flash diff --git a/doc/SPI/README.ti_qspi_dra_test b/doc/SPI/README.ti_qspi_dra_test new file mode 100644 index 000..fe37857 --- /dev/null +++ b/doc/SPI/README.ti_qspi_dra_test @@ -0,0 +1,48 @@ +- + Simple steps used to test the QSPI at U-Boot +- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +-- +Boot from another medium like MMC +-- + +U-Boot# mmc dev 0 +mmc0 is current device +U-Boot# fatload mmc 0 0x8200 MLO +reading MLO +55872 bytes read in 8 ms (6.7 MiB/s) +U-Boot# fatload mmc 0 0x8300 u-boot.img +reading u-boot.img +248600 bytes read in 19 ms (12.5 MiB/s) + +-- +Commands to erase/write u-boot/mlo to flash device +-- +U-Boot# sf probe 0 +SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c00 +SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR +U-Boot# sf erase 0 0x1 +SF: 65536 bytes @ 0x0 Erased: OK +U-Boot# sf erase 0x2 0x1 +SF: 65536 bytes @ 0x2 Erased: OK +U-Boot# sf erase 0x3 0x1 +SF: 65536 bytes @ 0x3 Erased: OK +U-Boot# sf erase 0x4 0x1 +SF: 65536 bytes @ 0x4 Erased: OK +U-Boot# sf erase 0x5 0x1 +SF: 65536 bytes @ 0x5 Erased: OK +U-Boot# sf erase 0x6 0x1 +SF: 65536 bytes @ 0x6 Erased: OK +U-Boot# sf write 8200 0 0x1 +SF: 65536 bytes @ 0x0 Written: OK +U-Boot# sf write 8300 0x2 0x6 +SF: 393216 bytes @ 0x2 Written: OK + +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x2 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash new file mode 100644 index 000..1b86d01 --- /dev/null +++ b/doc/SPI/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +-- + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +--- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +--- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +--- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +-- +drivers/qspi/ti_qspi.c +- Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +--- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized in 0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went wrong, I
will check.
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS(0x0 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ return NULL;
+}
Is this function really
Re: [U-Boot] [UBOOT][PATCHv4 6/6] README: qspi usecase and testing documentation.
On Saturday 05 October 2013 01:44 AM, Jagan Teki wrote: May be your are missing my comments in previous post. - Please place these these readme files in doc/SPI/* - Please use the doc/SPI/status.txt as an example format for writing new readme files. ok. On Sat, Oct 5, 2013 at 1:15 AM, Sourav Poddarsourav.pod...@ti.com wrote: On Saturday 05 October 2013 12:08 AM, Jagan Teki wrote: Hi Sourav, Please place these these readme files in doc/SPI/* All these patches tested on top of u-boot-spi.git master-probe? Yes, this are tested on the above branch. On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com wrote: Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddarsourav.pod...@ti.com --- doc/README.ti_qspi_dra_test | 38 ++ doc/README.ti_qspi_flash| 47 +++ 2 files changed, 85 insertions(+), 0 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash diff --git a/doc/README.ti_qspi_dra_test b/doc/README.ti_qspi_dra_test new file mode 100644 index 000..c4540ea --- /dev/null +++ b/doc/README.ti_qspi_dra_test @@ -0,0 +1,38 @@ +- + Simple steps used to test the QSPI at U-Boot +- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +-- +Boot from another medium like MMC +-- + +DRA752 EVM # mmc dev 0 +DRA752 EVM # fatload mmc 0 0x8200 MLO +DRA752 EVM # fatload mmc 0 0x8300 u-boot.img + +-- +Commands to erase/write u-boot/mlo to flash device +-- + +DRA752 EVM # sf probe 0 +[should detect the S25FL256S serial flash device] + +DRA752 EVM # sf erase 0 1 +DRA752 EVM # sf erase 1 1 +DRA752 EVM # sf erase 2 1 +DRA752 EVM # sf erase 3 1 +DRA752 EVM # sf erase 4 1 +DRA752 EVM # sf erase 5 1 +DRA752 EVM # sf erase 6 1 + +DRA752 EVM # sf write 8200 0 1 +DRA752 EVM # sf write 8300 2 7 + These test procedure steps were done in real hw. Seems like written once, could be generic if you test these steps on real hw and palce the same log here... +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x2 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/README.ti_qspi_flash b/doc/README.ti_qspi_flash new file mode 100644 index 000..1b86d01 --- /dev/null +++ b/doc/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +-- + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +--- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +--- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +--- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +-- +drivers/qspi/ti_qspi.c +- Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +--- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. -- 1.7.1 Please use the doc/SPI/status.txt as an example format for writing new readme files. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 3/6] driver: mtd: spi: Add memory mapped read support
On Saturday 05 October 2013 01:36 AM, Jagan Teki wrote:
Please use the commit msg head as sf: ..
Ok.
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of memory_map flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/sf_ops.c |2 ++
drivers/mtd/spi/sf_probe.c |1 +
include/spi.h |3 +++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..bee4128 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
Is it correct, can you check it once.
where is SPI_XFER_MEM_MAP_END used?
It will be used in the driver. check 4/6 patch of this series.
Looks like you have used mem-map for only reads is it? if so where is
SPI_XFER_BEGIN is using?
Yes, only memory mapped read is supported.
Ideally, we dont need BEGIN flag for memory mapped cases. I have
explained a bit
more on your similar comment on patch 4/6.
Please use _MMAP instead of _MEM_MAP for simple naming convention.
OK.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went wrong,
I
will check.
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(131)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n28)
+#define QSPI_WLEN(n) ((n-1)19)
+#define QSPI_3_PIN (118)
+#define QSPI_RD_SNGL (116)
+#define QSPI_WR_SNGL (216)
+#define QSPI_INVAL (416)
+#define QSPI_RD_QUAD (716)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m(3 + n*8))
+#define QSPI_CKPHA(n) (1(2 + n*8))
+#define QSPI_CSPOL(n) (1(1 + n*8))
+#define QSPI_CKPOL(n) (1(n*8))
+
+/* Status */
+#define QSPI_WC(11)
+#define QSPI_BUSY (10)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x30)
+#define QSPI_CMD_READ_QUAD (0x6b0)
+#define QSPI_CMD_READ_FAST (0x0b0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x28)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x010)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x110)
+#define QSPI_SETUP0_READ_NORMAL(0x012)
+#define QSPI_SETUP0_READ_QUAD (0x312)
+#define QSPI_CMD_WRITE (0x216)
+#define QSPI_NUM_DUMMY_BITS(0x024)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave
*slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
May be not required, bcz it will come after i apply below s-o-b
---
You missed change log for all patches, i think you have summarized in
0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
+
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went
wrong,
I
will check.
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS(0x0 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline
[U-Boot] [UBOOT][PATCHv4 1/6] omap5: add qspi support
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch/arm/include/asm/arch-omap5/spl.h |1 +
arch/arm/include/asm/omap_common.h |1 +
5 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index fbbc486..c00bfb8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)-cm_gmac_gmac_clkctrl,
#endif
+
+#ifdef CONFIG_TI_QSPI
+ (*prcm)-cm_l4per_qspi_clkctrl,
+#endif
0
};
@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)-cm_l4per_qspi_clkctrl, (124));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d..0b1bb46 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl= 0x4a009820,
.cm_l4per_mmcsd4_clkctrl= 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d3..414d37a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -61,6 +61,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x5000
+/* QSPI */
+#define QSPI_BASE 0x4B30
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index fe8b0c0..57f0de5 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -15,6 +15,7 @@
#define BOOT_DEVICE_MMC15
#define BOOT_DEVICE_MMC26
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 5e2f027..f865c14 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -266,6 +266,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv4 2/6] armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8..a1b249e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params
per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},/* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv4 0/6] Add TI qspi controller with memory mapped support
This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. v3-v4: 1. Remove quad support for now 2. Rebase to master-probe barnach, where qspi framework has changed. 3. Adapt my qspi driver according to the new format suggested by Jagan.. Patches are available at: git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v4 Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Sourav Poddar (3): armv7: hw_data: change clock divider setting. driver: mtd: spi: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/omap.h |3 + arch/arm/include/asm/arch-omap5/spl.h |1 + arch/arm/include/asm/omap_common.h |1 + board/ti/dra7xx/mux_data.h | 10 + doc/README.ti_qspi_dra_test| 38 doc/README.ti_qspi_flash | 47 + drivers/mtd/spi/sf_ops.c |2 + drivers/mtd/spi/sf_probe.c |1 + drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 328 include/configs/dra7xx_evm.h | 19 ++ include/spi.h |3 + 14 files changed, 464 insertions(+), 1 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv4 6/6] README: qspi usecase and testing documentation.
Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- doc/README.ti_qspi_dra_test | 38 ++ doc/README.ti_qspi_flash| 47 +++ 2 files changed, 85 insertions(+), 0 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash diff --git a/doc/README.ti_qspi_dra_test b/doc/README.ti_qspi_dra_test new file mode 100644 index 000..c4540ea --- /dev/null +++ b/doc/README.ti_qspi_dra_test @@ -0,0 +1,38 @@ +- + Simple steps used to test the QSPI at U-Boot +- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +-- +Boot from another medium like MMC +-- + +DRA752 EVM # mmc dev 0 +DRA752 EVM # fatload mmc 0 0x8200 MLO +DRA752 EVM # fatload mmc 0 0x8300 u-boot.img + +-- +Commands to erase/write u-boot/mlo to flash device +-- + +DRA752 EVM # sf probe 0 +[should detect the S25FL256S serial flash device] + +DRA752 EVM # sf erase 0 1 +DRA752 EVM # sf erase 1 1 +DRA752 EVM # sf erase 2 1 +DRA752 EVM # sf erase 3 1 +DRA752 EVM # sf erase 4 1 +DRA752 EVM # sf erase 5 1 +DRA752 EVM # sf erase 6 1 + +DRA752 EVM # sf write 8200 0 1 +DRA752 EVM # sf write 8300 2 7 + +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x2 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/README.ti_qspi_flash b/doc/README.ti_qspi_flash new file mode 100644 index 000..1b86d01 --- /dev/null +++ b/doc/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +-- + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +--- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +--- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +--- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +-- +drivers/qspi/ti_qspi.c +- Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +--- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv4 3/6] driver: mtd: spi: Add memory mapped read support
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of memory_map flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spi/sf_ops.c |2 ++
drivers/mtd/spi/sf_probe.c |1 +
include/spi.h |3 +++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..bee4128 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
return 0;
}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 1525636..6aa7086 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -203,6 +203,7 @@ struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi, u8 *idcode)
flash-page_size = (ext_jedec == 0x4d00) ? 512 : 256;
flash-sector_size = params-sector_size;
flash-size = flash-sector_size * params-nr_sectors;
+ flash-memory_map = spi-memory_map;
/* Compute erase sector and command */
if (params-flags SECT_4K) {
diff --git a/include/spi.h b/include/spi.h
index c44ebe8..d5c4e08 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,6 +27,8 @@
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01/* Assert CS before transfer */
#define SPI_XFER_END 0x02/* Deassert CS after transfer */
+#define SPI_XFER_MEM_MAP 0x08 /* Memory Mapped start */
+#define SPI_XFER_MEM_MAP_END 0x10 /* Memory Mapped End */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -46,6 +48,7 @@ struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int max_write_size;
+ void *memory_map;
};
/**
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328 +
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ *Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/omap.h
+#include malloc.h
+#include spi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS(0x0 24)
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ return NULL;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+void spi_set_up_spi_register(struct qspi_slave *qslave)
+{
+ u32 memval = 0;
+ struct spi_slave *slave = qslave-slave;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= (QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL |
+ QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
+
+ writel(memval, qslave-base-spi_setup0);
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct qspi_slave *qslave = to_qspi_slave(slave);
+
+ uint clk_div
[U-Boot] [UBOOT][PATCHv4 5/6] dra7xx_evm: add SPL API, QSPI, and serial flash support
From: Matt Porter matt.por...@linaro.org
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 19 +++
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 0a86594..6965cc5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] =
{
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
+ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
+ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A18, (M1)}, /* QSPI1_SCLK */
+ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
+ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
+ {GPMC_CS2, (IEN | PTU | PDIS | M1)},/* QSPI1_CS0 */
+ {GPMC_CS3, (IEN | PTU | PDIS | M1)},/* QSPI1_CS1*/
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4fbe768..310c7ac 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,23 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR2
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_MMAP
+#define CONFIG_SF_DEFAULT_SPEED4800
+#define CONFIG_DEFAULT_SPI_MODESPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+
#endif /* __CONFIG_DRA7XX_EVM_H */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 6/6] README: qspi usecase and testing documentation.
On Saturday 05 October 2013 12:08 AM, Jagan Teki wrote: Hi Sourav, Please place these these readme files in doc/SPI/* All these patches tested on top of u-boot-spi.git master-probe? Yes, this are tested on the above branch. On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com wrote: Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddarsourav.pod...@ti.com --- doc/README.ti_qspi_dra_test | 38 ++ doc/README.ti_qspi_flash| 47 +++ 2 files changed, 85 insertions(+), 0 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash diff --git a/doc/README.ti_qspi_dra_test b/doc/README.ti_qspi_dra_test new file mode 100644 index 000..c4540ea --- /dev/null +++ b/doc/README.ti_qspi_dra_test @@ -0,0 +1,38 @@ +- + Simple steps used to test the QSPI at U-Boot +- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +-- +Boot from another medium like MMC +-- + +DRA752 EVM # mmc dev 0 +DRA752 EVM # fatload mmc 0 0x8200 MLO +DRA752 EVM # fatload mmc 0 0x8300 u-boot.img + +-- +Commands to erase/write u-boot/mlo to flash device +-- + +DRA752 EVM # sf probe 0 +[should detect the S25FL256S serial flash device] + +DRA752 EVM # sf erase 0 1 +DRA752 EVM # sf erase 1 1 +DRA752 EVM # sf erase 2 1 +DRA752 EVM # sf erase 3 1 +DRA752 EVM # sf erase 4 1 +DRA752 EVM # sf erase 5 1 +DRA752 EVM # sf erase 6 1 + +DRA752 EVM # sf write 8200 0 1 +DRA752 EVM # sf write 8300 2 7 + These test procedure steps were done in real hw. Seems like written once, could be generic if you test these steps on real hw and palce the same log here... +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x2 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/README.ti_qspi_flash b/doc/README.ti_qspi_flash new file mode 100644 index 000..1b86d01 --- /dev/null +++ b/doc/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +-- + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +--- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +--- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +--- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +-- +drivers/qspi/ti_qspi.c +- Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +--- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. -- 1.7.1 Please use the doc/SPI/status.txt as an example format for writing new readme files. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv4 4/6] spi: add TI QSPI driver
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddarsourav.pod...@ti.com wrote:
From: Matt Portermatt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Portermatt.por...@linaro.org
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
[Added quad read support and memory mapped support).
What is this comment, any specific?
This simply tell the portion which i did in the patch.
---
You missed change log for all patches, i think you have summarized in 0/6.
I feel it's better write it on individual patches.
Ok.
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328 +
2 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..d8a03a8
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,328 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
Got below format after apply this patch - please check
*Â SPDX-License-Identifier:Â Â Â Â Â GPL-2.0+
ahh..I copied it from a patch on some list. May be something went wrong, I
will check.
+ */
+
+#includecommon.h
+#includeasm/io.h
+#includeasm/arch/omap.h
+#includemalloc.h
+#includespi.h
+
+struct qspi_regs {
+u32 pid;
+u32 pad0[3];
+u32 sysconfig;
+u32 pad1[3];
+u32 intr_status_raw_set;
+u32 intr_status_enabled_clear;
+u32 intr_enable_set;
+u32 intr_enable_clear;
+u32 intc_eoi;
+u32 pad2[3];
+u32 spi_clock_cntrl;
+u32 spi_dc;
+u32 spi_cmd;
+u32 spi_status;
+u32 spi_data;
+u32 spi_setup0;
+u32 spi_setup1;
+u32 spi_setup2;
+u32 spi_setup3;
+u32 spi_switch;
+u32 spi_data1;
+u32 spi_data2;
+u32 spi_data3;
Please add tab space.
ok
+};
+
+struct qspi_slave {
+ struct spi_slave slave;
+ struct qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
-- TAG+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS(0x0 24)
--TAG-
TAG+ ... TAG- please move these macro definitions in below headers
Ok.
+
+static inline struct qspi_slave *to_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct qspi_slave, slave);
+}
+static inline struct qspi_regs *get_qspi_bus(int dev)
+{
+ if (!dev)
+ return (struct qspi_regs *)QSPI_BASE;
+ else
+ return NULL;
+}
Is this function really required, how many bus controller you have?
Actually one.
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
Re: [U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver
On Thursday 03 October 2013 11:19 PM, Jagan Teki wrote: Hi Sourav, Please try to code the driver as specified in below thread! http://lists.denx.de/pipermail/u-boot/2013-August/160472.html Ok. On Fri, Sep 20, 2013 at 8:21 AM, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: Hi, 2013/9/18 Sourav Poddarsourav.pod...@ti.com: From: Matt Portermatt.por...@linaro.org Adds a SPI master driver for the TI QSPI peripheral. Signed-off-by: Matt Portermatt.por...@linaro.org Signed-off-by: Sourav Poddarsourav.pod...@ti.com [Added quad read support and memory mapped support). --- drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 324 + 2 files changed, 325 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/ti_qspi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 91d24ce..e5941b0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c new file mode 100644 index 000..3e88cf4 --- /dev/null +++ b/drivers/spi/ti_qspi.c @@ -0,0 +1,324 @@ +/* + * TI QSPI driver + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ Could you change to 'SPDX-License-Identifier:GPL-2.0+', please? Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.
On Thursday 03 October 2013 11:13 PM, Jagan Teki wrote: Hi Sourav, Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch. Sorry for the delay, try to send the patches without quad related stuff. Ok. I will rebase and send only ti qspi and memory mapped part. I will prepare a thread for this quad after this release as we did lot of work last few months back. Thanks for your help.!!! Ok. On Wed, Sep 18, 2013 at 5:51 PM, Sourav Poddarsourav.pod...@ti.com wrote: This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. v2-v3: 1. run checkpatch 2. Rearrange the code logically. 3. Remove a page read hack. Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Ravikumar Kattekola (1): drivers: mtd: :spi: Add quad read support Sourav Poddar (3): armv7: hw_data: change clock divider setting. driver: mtd: spi: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/omap.h |3 + arch/arm/include/asm/arch-omap5/spl.h |1 + arch/arm/include/asm/omap_common.h |1 + board/ti/dra7xx/mux_data.h | 10 + doc/README.ti_qspi_dra_test| 38 doc/README.ti_qspi_flash | 47 + drivers/mtd/spi/spansion.c |1 + drivers/mtd/spi/spi_flash.c| 113 +++- drivers/mtd/spi/spi_flash_internal.h |2 + drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 324 include/configs/dra7xx_evm.h | 20 ++ include/spi.h |5 + 15 files changed, 575 insertions(+), 2 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT]: Mcspi/qspi conflicting configs leading to build failure.
Hi Jagan, If you see the mcspi defconfig(CONFIG_OMAP3_SPI), it is moved to common file include/configs/ti_armv7_common.h . But with this, now after adding qspi the build breaks like this.. ti_qspi.o: In function `spi_cs_is_valid': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:108: multiple definition of `spi_cs_is_valid' omap3_spi.o:/home/a0131647/clone/u-boot/drivers/spi/omap3_spi.c:415: first defined here ti_qspi.o: In function `spi_cs_activate': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:114: multiple definition of `spi_cs_activate' omap3_spi.o:/home/a0131647/clone/u-boot/drivers/spi/omap3_spi.c:419: first defined here ti_qspi.o: In function `spi_cs_deactivate': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:120: multiple definition of `spi_cs_deactivate' omap3_spi.o:/home/a0131647/clone/u-boot/drivers/spi/omap3_spi.c:423: first defined here ti_qspi.o: In function `spi_init': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:125: multiple definition of `spi_init' As of now, I am tackling this by doing a undef CONFIG_OMAP3_SPI in my configs. But, we should have a way to use both(spi/qspi) of them simultaneously ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv3 1/7] omap5: add qspi support
From: Matt Porter matt.por...@linaro.org
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch/arm/include/asm/arch-omap5/spl.h |1 +
arch/arm/include/asm/omap_common.h |1 +
5 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index fbbc486..c00bfb8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)-cm_gmac_gmac_clkctrl,
#endif
+
+#ifdef CONFIG_TI_QSPI
+ (*prcm)-cm_l4per_qspi_clkctrl,
+#endif
0
};
@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)-cm_l4per_qspi_clkctrl, (124));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)-cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d..0b1bb46 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl= 0x4a009820,
.cm_l4per_mmcsd4_clkctrl= 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d3..414d37a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -61,6 +61,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x5000
+/* QSPI */
+#define QSPI_BASE 0x4B30
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index fe8b0c0..57f0de5 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -15,6 +15,7 @@
#define BOOT_DEVICE_MMC15
#define BOOT_DEVICE_MMC26
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 5e2f027..f865c14 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -266,6 +266,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.
This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. v2-v3: 1. run checkpatch 2. Rearrange the code logically. 3. Remove a page read hack. Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Ravikumar Kattekola (1): drivers: mtd: :spi: Add quad read support Sourav Poddar (3): armv7: hw_data: change clock divider setting. driver: mtd: spi: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |1 + arch/arm/include/asm/arch-omap5/omap.h |3 + arch/arm/include/asm/arch-omap5/spl.h |1 + arch/arm/include/asm/omap_common.h |1 + board/ti/dra7xx/mux_data.h | 10 + doc/README.ti_qspi_dra_test| 38 doc/README.ti_qspi_flash | 47 + drivers/mtd/spi/spansion.c |1 + drivers/mtd/spi/spi_flash.c| 113 +++- drivers/mtd/spi/spi_flash_internal.h |2 + drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 324 include/configs/dra7xx_evm.h | 20 ++ include/spi.h |5 + 15 files changed, 575 insertions(+), 2 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv3 4/7] driver: mtd: spi: Add memory mapped read support
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of memory_map flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
SPI_XFER_MEM_MAP and SPI_XFER_MEM_MAP_END.
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spi/spansion.c |1 +
drivers/mtd/spi/spi_flash.c |4
include/spi.h |3 +++
3 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index fa7ac8c..9d801a3 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -136,6 +136,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave
*spi, u8 *idcode)
flash-page_size = 256;
flash-sector_size = 256 * params-pages_per_sector;
flash-size = flash-sector_size * params-nr_sectors;
+ flash-memory_map = spi-memory_map;
return flash;
}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 993a9d4..5ad2dc1 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -287,7 +287,9 @@ int spi_flash_cmd_read_quad(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
return 0;
}
@@ -338,7 +340,9 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
/* Handle memory-mapped SPI */
if (flash-memory_map) {
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
memcpy(data, flash-memory_map + offset, len);
+ spi_xfer(flash-spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
return 0;
}
diff --git a/include/spi.h b/include/spi.h
index 9d4b2dc..559722f 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -28,6 +28,8 @@
#define SPI_XFER_BEGIN 0x01/* Assert CS before transfer */
#define SPI_XFER_END 0x02/* Deassert CS after transfer */
#define SPI_QUAD 0x04/* Use QUAD read command */
+#define SPI_XFER_MEM_MAP 0x08 /* Memory Mapped start */
+#define SPI_XFER_MEM_MAP_END 0x10 /* Memory Mapped End */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -47,6 +49,7 @@ struct spi_slave {
unsigned intcs;
unsigned int max_write_size;
bool quad_enable;
+ void *memory_map;
};
/*---
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv3 2/7] armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8..a1b249e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params
per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},/* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver
From: Matt Porter matt.por...@linaro.org
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter matt.por...@linaro.org
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 324 +
2 files changed, 325 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 000..3e88cf4
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,324 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/omap.h
+#include malloc.h
+#include spi.h
+
+struct qspi_slave {
+ struct spi_slave slave;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave)
+
+struct qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 intr_status_raw_set;
+ u32 intr_status_enabled_clear;
+ u32 intr_enable_set;
+ u32 intr_enable_clear;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 spi_clock_cntrl;
+ u32 spi_dc;
+ u32 spi_cmd;
+ u32 spi_status;
+ u32 spi_data;
+ u32 spi_setup0;
+ u32 spi_setup1;
+ u32 spi_setup2;
+ u32 spi_setup3;
+ u32 spi_switch;
+ u32 spi_data1;
+ u32 spi_data2;
+ u32 spi_data3;
+};
+
+static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE;
+
+#define QSPI_TIMEOUT 200
+
+#define QSPI_FCLK 19200
+
+/* Clock Control */
+#define QSPI_CLK_EN(1 31)
+#define QSPI_CLK_DIV_MAX 0x
+
+/* Command */
+#define QSPI_EN_CS(n) (n 28)
+#define QSPI_WLEN(n) ((n-1) 19)
+#define QSPI_3_PIN (1 18)
+#define QSPI_RD_SNGL (1 16)
+#define QSPI_WR_SNGL (2 16)
+#define QSPI_INVAL (4 16)
+#define QSPI_RD_QUAD (7 16)
+
+/* Device Control */
+#define QSPI_DD(m, n) (m (3 + n*8))
+#define QSPI_CKPHA(n) (1 (2 + n*8))
+#define QSPI_CSPOL(n) (1 (1 + n*8))
+#define QSPI_CKPOL(n) (1 (n*8))
+
+/* Status */
+#define QSPI_WC(1 1)
+#define QSPI_BUSY (1 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT0xf0ff
+#define MMAP_START_ADDR0x5c00
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 0)
+#define QSPI_CMD_READ_QUAD (0x6b 0)
+#define QSPI_CMD_READ_FAST (0x0b 0)
+#define QSPI_SETUP0_NUM_A_BYTES(0x2 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS(0x0 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 10)
+#define QSPI_SETUP0_READ_NORMAL(0x0 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 12)
+#define QSPI_CMD_WRITE (0x2 16)
+#define QSPI_NUM_DUMMY_BITS(0x0 24)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+void spi_set_up_spi_register(struct spi_slave *slave)
+{
+ u32 memval = 0;
+
+ slave-memory_map = (void *)MMAP_START_ADDR;
+
+#ifdef CONFIG_SF_QUAD_RD
[U-Boot] [UBOOT][PATCHv3 3/7] drivers: mtd: :spi: Add quad read support
From: Ravikumar Kattekola r...@ti.com
Some flash like S25fl256s supports quad read mode also.
This patch enables the quad read support based on
CONFIG_SF_QUAD_RD config.
Enabling quad read has the following components:
1. Enable the Quad mode bit in the flash device side.
2. Add a quad read mode read api. I have created a new
api for quad mode as some flash has few more quad read
command that can be supported. As of now, I have addded only
QUAD OUTPUT READ command.
3. spi driver need to know that the read to be done is the
quad read. Communicate this to the driver through a
SPI_QUAD flag. This need to be done because quad read should
only happen when quad command is sent. For reading status register
and other configuration register normal transfers should happen.
Signed-off-by: Ravikumar Kattekola r...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 109 +-
drivers/mtd/spi/spi_flash_internal.h |2 +
include/spi.h|2 +
3 files changed, 112 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5d5055f..993a9d4 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -42,8 +42,13 @@ static int spi_flash_read_write(struct spi_slave *spi,
debug(SF: Failed to send command (%zu bytes): %d\n,
cmd_len, ret);
} else if (data_len != 0) {
+ if (spi-quad_enable)
+ flags = SPI_QUAD;
+ else
+ flags = 0;
+
ret = spi_xfer(spi, data_len * 8, data_out, data_in,
- SPI_XFER_END);
+ flags | SPI_XFER_END);
if (ret)
debug(SF: Failed to transfer %zu bytes of data: %d\n,
data_len, ret);
@@ -272,6 +277,58 @@ int spi_flash_read_common(struct spi_flash *flash, const
u8 *cmd,
return ret;
}
+int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
+ size_t len, void *data)
+{
+ struct spi_slave *spi = flash-spi;
+ u8 cmd[5], bank_sel = 0;
+ u32 remain_len, read_len;
+ int ret = -1;
+
+ /* Handle memory-mapped SPI */
+ if (flash-memory_map) {
+ memcpy(data, flash-memory_map + offset, len);
+ return 0;
+ }
+
+ spi-quad_enable = true;
+ cmd[0] = CMD_READ_ARRAY_QUAD;
+ cmd[4] = 0x00;
+
+ while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug(SF: fail to set bank%d\n, bank_sel);
+ return ret;
+ }
+#endif
+
+ remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
+ if (len remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+
+ spi_flash_addr(offset, cmd);
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+ data, read_len);
+ if (ret 0) {
+ debug(SF: read failed\n);
+ break;
+ }
+
+ offset += read_len;
+ len -= read_len;
+ data += read_len;
+ }
+
+ return ret;
+}
+
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
@@ -395,6 +452,48 @@ int spi_flash_bank_config(struct spi_flash *flash, u8
idcode0)
}
#endif
+int spi_flash_en_quad_mode(struct spi_flash *flash)
+{
+ u8 stat, con, cd;
+ u16 cr;
+ int ret;
+ cd = CMD_WRITE_STATUS;
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ goto out;
+ }
+ ret = spi_flash_cmd(flash-spi, CMD_READ_STATUS, stat, 1);
+ ret = spi_flash_cmd(flash-spi, CMD_READ_CONFIG, con, 1);
+ if (ret 0) {
+ debug(%s: SF: read CR failed\n, __func__);
+ goto out;
+ }
+ /* Byte 1 - status reg, Byte 2 - config reg */
+ cr = ((con | (0x1 1)) 8) | (stat 0);
+
+ ret = spi_flash_cmd_write(flash-spi, cd, 1, cr, 2);
+ if (ret) {
+ debug(SF: fail to write conf register\n);
+ goto out;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret 0) {
+ debug(SF: write conf register timed out\n);
+ goto out;
+ }
+
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ debug(SF: disabling write failed\n);
+ goto out
[U-Boot] [UBOOT][PATCHv3 7/7] README: qspi usecase and testing documentation.
Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- doc/README.ti_qspi_dra_test | 38 ++ doc/README.ti_qspi_flash| 47 +++ 2 files changed, 85 insertions(+), 0 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash diff --git a/doc/README.ti_qspi_dra_test b/doc/README.ti_qspi_dra_test new file mode 100644 index 000..c4540ea --- /dev/null +++ b/doc/README.ti_qspi_dra_test @@ -0,0 +1,38 @@ +- + Simple steps used to test the QSPI at U-Boot +- + +For #1, build the patched U-Boot and load MLO/u-boot.img + +-- +Boot from another medium like MMC +-- + +DRA752 EVM # mmc dev 0 +DRA752 EVM # fatload mmc 0 0x8200 MLO +DRA752 EVM # fatload mmc 0 0x8300 u-boot.img + +-- +Commands to erase/write u-boot/mlo to flash device +-- + +DRA752 EVM # sf probe 0 +[should detect the S25FL256S serial flash device] + +DRA752 EVM # sf erase 0 1 +DRA752 EVM # sf erase 1 1 +DRA752 EVM # sf erase 2 1 +DRA752 EVM # sf erase 3 1 +DRA752 EVM # sf erase 4 1 +DRA752 EVM # sf erase 5 1 +DRA752 EVM # sf erase 6 1 + +DRA752 EVM # sf write 8200 0 1 +DRA752 EVM # sf write 8300 2 7 + +For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power +on. ROM should find the GP header at offset 0 and load/execute SPL. SPL +then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to +find a U-Boot image header at offset 0x2 (set in the config file) +and proceeds to load that image using the U-Boot image payload offset/size +from the header. It will then start U-Boot. diff --git a/doc/README.ti_qspi_flash b/doc/README.ti_qspi_flash new file mode 100644 index 000..1b86d01 --- /dev/null +++ b/doc/README.ti_qspi_flash @@ -0,0 +1,47 @@ +QSPI U-boot support +-- + +Host processor is connected to serial flash device via qpsi +interface. QSPI is a kind of spi module that allows single, +dual and quad read access to external spi devices. The module +has a memory mapped interface which provide direct interface +for accessing data form external spi devices. + +The one QSPI in the device is primarily intended for fast booting +from Quad SPI flash devices. + +Usecase +--- + +MLO/u-boot.img will be flashed from SD/MMC to the flash device +using serial flash erase and write commands. Then, switch settings +will be changed to qspi boot. Then, the ROM code will read MLO +from the predefined location in the flash, where it was flashed and +execute it after storing it in SDRAM. Then, the MLO will read +u-boot.img from flash and execute it from SDRAM. + +SPI mode +--- +SPI mode uses mtd spi framework for transfer and reception of data. +Can be used in: +1. Normal mode: use single pin for transfers +2. Dual Mode: use two pins for transfers. +3. Quad mode: use four pin for transfer + +Memory mapped read mode +--- +In this, SPI controller is configured using configuration port and then +controler is switched to memory mapped port for data read. + +Driver +-- +drivers/qspi/ti_qspi.c +- Newly created file which is responsible for configuring the + qspi controller and also for providing the low level api which + is responsible for transferring the datas from host controller + to flash device and vice versa. + +Testing +--- +A seperated file named README.dra_qspi_test has been created which gives all the +details about the commands required to test qspi at u-boot level. -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
