RE: [PATCH 3/4] mtd: rawnand: brcmnand: Add BCMBCA read data bus interface
Hi Linus, > -Original Message- > From: Linus Walleij > Sent: Thursday, November 7, 2024 6:16 AM > To: david regan > Cc: u-boot ; Dario Binacchi > ; Michael Trimarchi > ; Anand Gore > ; William Zhang > ; Kursad Oney > ; Philippe Reynes > ; Florian Fainelli > ; Miquel Raynal > ; Kamal Dasu ; > David Regan ; Tom Rini ; Jiaxun > Yang > Subject: Re: [PATCH 3/4] mtd: rawnand: brcmnand: Add BCMBCA read data > bus interface > > On Wed, Nov 6, 2024 at 10:04 PM david regan > wrote: > > > The BCMBCA broadband SoC integrates the NAND controller differently than > > STB, iProc and other SoCs. It has different endianness for NAND cache > > data. > > > > Add a SoC read data bus shim for BCMBCA to meet the specific SoC need > > and performance improvement using the optimized memcpy function on > NAND > > cache memory. > > > > This is a port of the upstream Linux patch to U-Boot. > > > > https://lore.kernel.org/linux-mtd/20240223034758.13753-12- > william.zh...@broadcom.com/ > > > > Signed-off-by: david regan > > The patch looks fine, but shouldn't the existing brcmnand_read_data_bus() > in drivers/mtd/nand/raw/brcmnand/brcmnand.c also be replaced with > brcmnand_soc_data_bus_read()? > > Maybe this is a problem in the upstream kernel driver though :/ > The upstream kernel driver is correct because it uses exec_op to read the parameter page/ONFI data but exec_op is not available to the u-boot code base. So this new function brcmnand_soc_data_bus_read tries to do that in generic way to handle the endianness difference between platforms. But I agree it causes confusing to existing brcmnand_read_data_bus. We are working on a better solution and will update. > Yours, > Linus Walleij smime.p7s Description: S/MIME Cryptographic Signature
RE: [PATCH v2 7/7] mtd: rawnand: brcmnand: Add support for getting ecc setting from strap
> -Original Message-
> From: Linus Walleij
> Sent: Monday, September 16, 2024 2:59 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; David Regan
> ; Miquel Raynal
> Subject: [PATCH v2 7/7] mtd: rawnand: brcmnand: Add support for getting
> ecc setting from strap
>
> From: William Zhang
>
> Backport from the upstream Linux kernel
> commit c2cf7e25eb2a3c915a420fb8ceed8912add7f36c
> "mtd: rawnand: brcmnand: Add support for getting ecc setting from strap"
>
> Note: the upstream kernel introduces a new
> bool brcmnand_get_sector_size_1k() function because the int
> version in U-Boot has been removed in Linux. I kept the old
> int-returning version that is already in U-Boot as we depend
> on that in other code.
>
> BCMBCA broadband SoC based board design does not specify ecc setting in
> dts but rather use the SoC NAND strap info to obtain the ecc strength
> and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for
> this purpose and update driver to support this option. However these two
> options can not be used at the same time.
>
> Signed-off-by: William Zhang
> Reviewed-by: David Regan
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20240301173308.226004-1-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 70
> ++--
> 1 file changed, 66 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 071b33951648..749553c9df90 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -980,6 +980,43 @@ static void brcmnand_set_sector_size_1k(struct
> brcmnand_host *host, int val)
> nand_writereg(ctrl, acc_control_offs, tmp);
> }
>
> +static int brcmnand_get_spare_size(struct brcmnand_host *host)
> +{
> + struct brcmnand_controller *ctrl = host->ctrl;
> + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
> +
> BRCMNAND_CS_ACC_CONTROL);
> + u32 acc = nand_readreg(ctrl, acc_control_offs);
> +
> + return (acc & brcmnand_spare_area_mask(ctrl));
> +}
> +
> +static void brcmnand_get_ecc_settings(struct brcmnand_host *host,
> struct nand_chip *chip)
> +{
> + struct brcmnand_controller *ctrl = host->ctrl;
> + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
> +
> BRCMNAND_CS_ACC_CONTROL);
> + bool sector_size_1k = brcmnand_get_sector_size_1k(host);
> + int spare_area_size, ecc_level;
> + u32 acc;
> +
> + spare_area_size = brcmnand_get_spare_size(host);
> + acc = nand_readreg(ctrl, acc_control_offs);
> + ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl-
> >ecc_level_shift;
> + if (sector_size_1k)
> + chip->ecc.strength = ecc_level * 2;
> + else if (spare_area_size == 16 && ecc_level == 15)
> + chip->ecc.strength = 1; /* hamming */
> + else
> + chip->ecc.strength = ecc_level;
> +
> + if (chip->ecc.size == 0) {
> + if (sector_size_1k)
> + chip->ecc.size = 1024;
> + else
> + chip->ecc.size = 512;
> + }
> +}
> +
>
> /**
> *
> * CS_NAND_SELECT
>
> **
> */
> @@ -2323,12 +2360,33 @@ static int brcmnand_setup_dev(struct
> brcmnand_host *host)
> struct nand_memory_organization *memorg =
> nanddev_get_memorg(nanddev);
> struct brcmnand_controller *ctrl = host->ctrl;
> struct brcmnand_cfg *cfg = &host->hwcfg;
> - char msg[128];
> u32 offs, tmp, oob_sector;
> + bool use_strap = false;
> + char msg[128];
> int ret;
>
> memset(cfg, 0, sizeof(*cfg));
>
> +#ifndef __UBOOT__
> + use_strap = of_property_read_bool(nand_get_flash_node(chip),
> + "brcm,nand-ecc-use-strap"):
> +#else
> + use_strap = ofnode_read_bool(nand_get_flash_node(chip),
> + "brcm,nand-ecc-use-strap");
> +#endif /* __UBOOT__ */
> + /*
> + * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error
> out
> + * if both exist.
> + */
> + if (chip->ecc.strength && use_strap) {
> + dev_err(ctrl->dev,
>
RE: [PATCH v2 6/7] mtd: rawnand: brcmnand: Support write protection setting from dts
> -Original Message-
> From: Linus Walleij
> Sent: Monday, September 16, 2024 2:59 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; Florian Fainelli
> ; Kamal Dasu
> ; David Regan ;
> Miquel Raynal
> Subject: [PATCH v2 6/7] mtd: rawnand: brcmnand: Support write
> protection setting from dts
>
> From: William Zhang
>
> Backport of upstream Linux
> commit 8e7daa85641c9559c113f6b217bdc923397de77c
> "mtd: rawnand: brcmnand: Support write protection setting from dts"
>
> Augmented to also support the "write-protect" boolean property.
>
> The write protection feature is controlled by the module parameter wp_on
> with default set to enabled. But not all the board use this feature
> especially in BCMBCA broadband board. And module parameter is not
> sufficient as different board can have different option. Add a device
> tree property and allow this feature to be configured through the board
> dts on per board basis.
>
> Signed-off-by: William Zhang
> Reviewed-by: Florian Fainelli
> Reviewed-by: Kamal Dasu
> Reviewed-by: David Regan
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 2f786584a1ae..071b33951648 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -2844,8 +2844,17 @@ int brcmnand_probe(struct udevice *dev,
> struct brcmnand_soc *soc)
> /* Disable XOR addressing */
> brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
>
> + /* Check if the board connects the WP pin */
> +#ifndef __UBOOT__
> + if (of_property_read_bool(dn, "brcm,wp-not-connected"))
> +#else
> + if (dev_read_bool(ctrl->dev, "brcm,wp-not-connected"))
> +#endif /* __UBOOT__ */
> + wp_on = 0;
> +
> /* Read the write-protect configuration in the device tree */
> - wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
> + if (dev_read_bool(ctrl->dev, "write-protect"))
write-protect is a u32 property. Should use dev_read_u32 and check return
code to see if the property exist or not.
> + wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
>
> if (ctrl->features & BRCMNAND_HAS_WP) {
> /* Permanently disable write protection */
>
> --
> 2.46.0
Reviewed-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
RE: [PATCH v2 3/7] mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write
> -Original Message-
> From: Linus Walleij
> Sent: Monday, September 16, 2024 2:59 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; Florian Fainelli
> ; Miquel Raynal
>
> Subject: [PATCH v2 3/7] mtd: rawnand: brcmnand: Fix potential out-of-
> bounds access in oob write
>
> From: William Zhang
>
> Backport of upstream Linux
> commit 5d53244186c9ac58cb88d76a0958ca55b83a15cd
> "mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write"
>
> When the oob buffer length is not in multiple of words, the oob write
> function does out-of-bounds read on the oob source buffer at the last
> iteration. Fix that by always checking length limit on the oob buffer
> read and fill with 0xff when reaching the end of the buffer to the oob
> registers.
>
> Signed-off-by: William Zhang
> Reviewed-by: Florian Fainelli
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-5-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 18 --
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 46a4107a83a9..60d34bd21f53 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -1334,19 +1334,33 @@ static int write_oob_to_regs(struct
> brcmnand_controller *ctrl, int i,
>const u8 *oob, int sas, int sector_1k)
> {
> int tbytes = sas << sector_1k;
> - int j;
> + int j, k = 0;
> + u32 last = 0x;
> + u8 *plast = (u8 *)&last;
>
> /* Adjust OOB values for 1K sector size */
> if (sector_1k && (i & 0x01))
> tbytes = max(0, tbytes - (int)ctrl->max_oob);
> tbytes = min_t(int, tbytes, ctrl->max_oob);
>
> - for (j = 0; j < tbytes; j += 4)
> + /*
> + * tbytes may not be multiple of words. Make sure we don't read
> out of
> + * the boundary and stop at last word.
> + */
> + for (j = 0; (j + 3) < tbytes; j += 4)
> oob_reg_write(ctrl, j,
> (oob[j + 0] << 24) |
> (oob[j + 1] << 16) |
> (oob[j + 2] << 8) |
> (oob[j + 3] << 0));
> +
> + /* handle the remaing bytes */
> + while (j < tbytes)
> + plast[k++] = oob[j++];
> +
> + if (tbytes & 0x3)
> + oob_reg_write(ctrl, (tbytes & ~0x3), (__force
> u32)cpu_to_be32(last));
> +
> return tbytes;
> }
>
>
> --
> 2.46.0
Reviewed-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
RE: [PATCH v2 5/7] mtd: rawnand: brcmnand: Add read data bus interface
> -Original Message-
> From: Linus Walleij
> Sent: Monday, September 16, 2024 2:59 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij
> Subject: [PATCH v2 5/7] mtd: rawnand: brcmnand: Add read data bus
> interface
>
> This is a port of the read data bus interface from the Linux
> brcmnand driver, commit
> 546e425991205f59281e160a0d0daed47b7ca9b3
> "mtd: rawnand: brcmnand: Add BCMBCA read data bus interface"
>
> This is needed for the BCMBCA RAW NAND driver.
>
> Signed-off-by: William Zhang
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 +-
> --
> drivers/mtd/nand/raw/brcmnand/brcmnand.h | 2 ++
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 552b239b95ae..2f786584a1ae 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -769,6 +769,20 @@ static inline void brcmnand_write_fc(struct
> brcmnand_controller *ctrl,
> __raw_writel(val, ctrl->nand_fc + word * 4);
> }
>
> +static inline void brcmnand_read_data_bus(struct brcmnand_controller
> *ctrl,
> + void __iomem *flash_cache, u32
> *buffer, int fc_words)
> +{
> + struct brcmnand_soc *soc = ctrl->soc;
> + int i;
> +
> + if (soc && soc->read_data_bus) {
> + soc->read_data_bus(soc, flash_cache, buffer, fc_words);
> + } else {
> + for (i = 0; i < fc_words; i++)
> + buffer[i] = brcmnand_read_fc(ctrl, i);
> + }
> +}
> +
> static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
> {
>
> @@ -1812,7 +1826,7 @@ static int brcmnand_read_by_pio(struct
> mtd_info *mtd, struct nand_chip *chip,
> {
> struct brcmnand_host *host = nand_get_controller_data(chip);
> struct brcmnand_controller *ctrl = host->ctrl;
> - int i, j, ret = 0;
> + int i, ret = 0;
>
> brcmnand_clear_ecc_addr(ctrl);
>
> @@ -1825,8 +1839,8 @@ static int brcmnand_read_by_pio(struct
> mtd_info *mtd, struct nand_chip *chip,
> if (likely(buf)) {
> brcmnand_soc_data_bus_prepare(ctrl->soc, false);
>
> - for (j = 0; j < FC_WORDS; j++, buf++)
> - *buf = brcmnand_read_fc(ctrl, j);
> + brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf,
> FC_WORDS);
> + buf += FC_WORDS;
>
> brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
> }
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.h
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
> index 6946a62b0679..3a1d60471361 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.h
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
> @@ -11,6 +11,8 @@ struct brcmnand_soc {
> void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
> void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
>bool is_param);
> + void (*read_data_bus)(struct brcmnand_soc *soc, void __iomem
> *flash_cache,
> + u32 *buffer, int fc_words);
> void *ctrl;
> };
>
>
> --
> 2.46.0
Reviewed-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
RE: [PATCH v2 4/7] mtd: rawnand: brcmnand: Fix mtd oobsize
> -Original Message-
> From: Linus Walleij
> Sent: Monday, September 16, 2024 2:59 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; Miquel Raynal
>
> Subject: [PATCH v2 4/7] mtd: rawnand: brcmnand: Fix mtd oobsize
>
> From: William Zhang
>
> Backport from upstream Linux
> commit 60177390fa061c62d156f4a546e3efd90df3c183
> "mtd: rawnand: brcmnand: Fix mtd oobsize"
>
> brcmnand controller can only access the flash spare area up to certain
> bytes based on the ECC level. It can be less than the actual flash spare
> area size. For example, for many NAND chip supporting ECC BCH-8, it has
> 226 bytes spare area. But controller can only uses 218 bytes. So brcmand
> driver overrides the mtd oobsize with the controller's accessible spare
> area size. When the nand base driver utilizes the nand_device object, it
> resets the oobsize back to the actual flash spare aprea size from
> nand_memory_organization structure and controller may not able to
> access
> all the oob area as mtd advises.
>
> This change fixes the issue by overriding the oobsize in the
> nand_memory_organization structure to the controller's accessible spare
> area size.
>
> Fixes: a7ab085d7c16 ("mtd: rawnand: Initialize the nand_device object")
> Signed-off-by: William Zhang
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-6-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 60d34bd21f53..552b239b95ae 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -25,6 +25,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -2304,6 +2305,8 @@ static int brcmnand_setup_dev(struct
> brcmnand_host *host)
> {
> struct mtd_info *mtd = nand_to_mtd(&host->chip);
> struct nand_chip *chip = &host->chip;
> + struct nand_device *nanddev = mtd_to_nanddev(mtd);
> + struct nand_memory_organization *memorg =
> nanddev_get_memorg(nanddev);
> struct brcmnand_controller *ctrl = host->ctrl;
> struct brcmnand_cfg *cfg = &host->hwcfg;
> char msg[128];
> @@ -2331,10 +2334,11 @@ static int brcmnand_setup_dev(struct
> brcmnand_host *host)
> if (cfg->spare_area_size > ctrl->max_oob)
> cfg->spare_area_size = ctrl->max_oob;
> /*
> - * Set oobsize to be consistent with controller's spare_area_size, as
> - * the rest is inaccessible.
> + * Set mtd and memorg oobsize to be consistent with controller's
> + * spare_area_size, as the rest is inaccessible.
>*/
> mtd->oobsize = cfg->spare_area_size * (mtd->writesize >>
> FC_SHIFT);
> + memorg->oobsize = mtd->oobsize;
>
> cfg->device_size = mtd->size;
> cfg->block_size = mtd->erasesize;
>
> --
> 2.46.0
Reviewed-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
RE: [PATCH v2 1/7] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller
> -Original Message-
> From: Linus Walleij
> Sent: Monday, September 16, 2024 2:59 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; Florian Fainelli
> ; Miquel Raynal
>
> Subject: [PATCH v2 1/7] mtd: rawnand: brcmnand: Fix ECC level field
> setting for v7.2 controller
>
> From: William Zhang
>
> Backport from the Linux kernel
> commit 2ec2839a9062db8a592525a3fdabd42dcd9a3a9b
> "mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller"
>
> v7.2 controller has different ECC level field size and shift in the acc
> control register than its predecessor and successor controller. It needs
> to be set specifically.
>
> Signed-off-by: William Zhang
> Reviewed-by: Florian Fainelli
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-2-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 74
> ++--
> 1 file changed, 41 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index b1af3f717d43..700d1122639f 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -218,6 +218,7 @@ struct brcmnand_controller {
> const unsigned int *page_sizes;
> unsigned intpage_size_shift;
> unsigned intmax_oob;
> + u32 ecc_level_shift;
> u32 features;
>
> /* for low-power standby/resume only */
> @@ -544,6 +545,34 @@ enum {
> INTFC_CTLR_READY= BIT(31),
> };
>
> +/*
> **
> + * NAND ACC CONTROL bitfield
> + *
> + * Some bits have remained constant throughout hardware revision, while
> + * others have shifted around.
> +
> **
> */
> +
> +/* Constant for all versions (where supported) */
> +enum {
> + /* See BRCMNAND_HAS_CACHE_MODE */
> + ACC_CONTROL_CACHE_MODE = BIT(22),
> +
> + /* See BRCMNAND_HAS_PREFETCH */
> + ACC_CONTROL_PREFETCH= BIT(23),
> +
> + ACC_CONTROL_PAGE_HIT= BIT(24),
> + ACC_CONTROL_WR_PREEMPT = BIT(25),
> + ACC_CONTROL_PARTIAL_PAGE= BIT(26),
> + ACC_CONTROL_RD_ERASED = BIT(27),
> + ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
> + ACC_CONTROL_WR_ECC = BIT(30),
> + ACC_CONTROL_RD_ECC = BIT(31),
> +};
> +
> +#define ACC_CONTROL_ECC_SHIFT 16
> +/* Only for v7.2 */
> +#define ACC_CONTROL_ECC_EXT_SHIFT 13
> +
> static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32
> offs)
> {
> return brcmnand_readl(ctrl->nand_base + offs);
> @@ -675,6 +704,12 @@ static int brcmnand_revision_init(struct
> brcmnand_controller *ctrl)
> #endif /* __UBOOT__ */
> ctrl->features |= BRCMNAND_HAS_WP;
>
> + /* v7.2 has different ecc level shift in the acc register */
> + if (ctrl->nand_version == 0x0702)
> + ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT;
> + else
> + ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT;
> +
> return 0;
> }
>
> @@ -844,30 +879,6 @@ static inline int brcmnand_cmd_shift(struct
> brcmnand_controller *ctrl)
> return 0;
> }
>
> -
> /**
> *
> - * NAND ACC CONTROL bitfield
> - *
> - * Some bits have remained constant throughout hardware revision, while
> - * others have shifted around.
> -
> **
> */
> -
> -/* Constant for all versions (where supported) */
> -enum {
> - /* See BRCMNAND_HAS_CACHE_MODE */
> - ACC_CONTROL_CACHE_MODE = BIT(22),
> -
> - /* See BRCMNAND_HAS_PREFETCH */
> - ACC_CONTROL_PREFETCH= BIT(23),
> -
> - ACC_CONTROL_PAGE_HIT= BIT(24),
> - ACC_CONTROL_WR_PREEMPT = BIT(25),
> - ACC_CONTROL_PARTIAL_PAGE= BIT(26),
> - ACC_CONTROL_RD_ERASED
RE: [PATCH v2 2/7] mtd: rawnand: brcmnand: Fix potential false time out warning
> -Original Message- > From: Linus Walleij > Sent: Monday, September 16, 2024 2:59 AM > To: u-boot@lists.denx.de; Dario Binacchi > ; Michael Trimarchi > ; Anand Gore > ; William Zhang > ; Kursad Oney > ; Philippe Reynes > > Cc: Linus Walleij ; Florian Fainelli > ; Miquel Raynal > > Subject: [PATCH v2 2/7] mtd: rawnand: brcmnand: Fix potential false time > out warning > > From: William Zhang > > Backport from the Linux kernel: > commit 9cc0a598b944816f2968baf2631757f22721b996 > "mtd: rawnand: brcmnand: Fix potential false time out warning" > > If system is busy during the command status polling function, the driver > may not get the chance to poll the status register till the end of time > out and return the premature status. Do a final check after time out > happens to ensure reading the correct status. > > Signed-off-by: William Zhang > Reviewed-by: Florian Fainelli > Signed-off-by: Miquel Raynal > Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-3- > william.zh...@broadcom.com > Signed-off-by: Linus Walleij > --- > drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c > b/drivers/mtd/nand/raw/brcmnand/brcmnand.c > index 700d1122639f..46a4107a83a9 100644 > --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c > +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c > @@ -1011,6 +1011,14 @@ static int bcmnand_ctrl_poll_status(struct > brcmnand_controller *ctrl, > } while (get_timer(base) < limit); > #endif /* __UBOOT__ */ > > + /* > + * do a final check after time out in case the CPU was busy and the > driver > + * did not get enough time to perform the polling to avoid false > alarms > + */ > + val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); > + if ((val & mask) == expected_val) > + return 0; > + > dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", >expected_val, val & mask); > > > -- > 2.46.0 Reviewed-by: William Zhang smime.p7s Description: S/MIME Cryptographic Signature
RE: [PATCH 0/7] mtd: nand: brcmnand: Backported fixes from Linux
> -Original Message- > From: Linus Walleij > Sent: Monday, September 16, 2024 2:23 AM > To: William Zhang > Cc: u-boot@lists.denx.de; Dario Binacchi > ; Michael Trimarchi > ; Anand Gore > ; Kursad Oney > ; Philippe Reynes > ; Florian Fainelli > ; Miquel Raynal > ; Kamal Dasu ; > David Regan > Subject: Re: [PATCH 0/7] mtd: nand: brcmnand: Backported fixes from > Linux > > On Mon, Sep 16, 2024 at 6:45 AM William Zhang > wrote: > > > Yes we have it working. And your patches works too after fixing two > > Issues that I will comment on the specific patch. > > Yay! > > > You will need to > > enable the NAND related configurations and the nand dts node. > > Aha maybe I simply missed the DTS node... > > > You can use existing dts node to set the specific ecc level, oob size > > and > > ecc step size. Or use the new automatically detection from the strap > > property brcm,nand-ecc-use-strap that I upstreamed to linux. > > I was planning to used the strap, which is ... what we should have been > doing all the time. Oh well, no turning back time I guess. Maybe we > can fix a lot of DTS:es to use the strap though? > Yes we will upstream the dts including the binding document and other related patches. Your series can go in first. > > What SoC do you use? > > This is on BCM6846. > 6846 will work. Let me know if it still does not work after dts fix. > Thanks William! > Linus smime.p7s Description: S/MIME Cryptographic Signature
RE: [PATCH 7/7] mtd: rawnand: brcmnand: Add support for getting ecc setting from strap
Please also consider to update the brcmnand_get_sector_size_1k code based
on
change in the linux driver so we can keep them consistent as much as
possible.
> -Original Message-
> From: Linus Walleij
> Sent: Wednesday, September 11, 2024 12:11 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; David Regan
> ; Miquel Raynal
> Subject: [PATCH 7/7] mtd: rawnand: brcmnand: Add support for getting ecc
> setting from strap
>
> From: William Zhang
>
> Backport from the upstream Linux kernel
> commit c2cf7e25eb2a3c915a420fb8ceed8912add7f36c
> "mtd: rawnand: brcmnand: Add support for getting ecc setting from strap"
>
> Note: the upstream kernel introduces a new
> bool brcmnand_get_sector_size_1k() function because the int
> version in U-Boot has been removed in Linux. I kept the old
> int-returning version that is already in U-Boot as we depend
> on that in other code.
>
> BCMBCA broadband SoC based board design does not specify ecc setting in
> dts but rather use the SoC NAND strap info to obtain the ecc strength
> and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for
> this purpose and update driver to support this option. However these two
> options can not be used at the same time.
>
> Signed-off-by: William Zhang
> Reviewed-by: David Regan
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20240301173308.226004-1-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 70
> ++--
> 1 file changed, 66 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 55d5d27438a8..1ffd6cfff98f 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -980,6 +980,43 @@ static void brcmnand_set_sector_size_1k(struct
> brcmnand_host *host, int val)
> nand_writereg(ctrl, acc_control_offs, tmp);
> }
>
> +static int brcmnand_get_spare_size(struct brcmnand_host *host)
> +{
> + struct brcmnand_controller *ctrl = host->ctrl;
> + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
> +
> BRCMNAND_CS_ACC_CONTROL);
> + u32 acc = nand_readreg(ctrl, acc_control_offs);
> +
> + return (acc & brcmnand_spare_area_mask(ctrl));
> +}
> +
> +static void brcmnand_get_ecc_settings(struct brcmnand_host *host,
> struct nand_chip *chip)
> +{
> + struct brcmnand_controller *ctrl = host->ctrl;
> + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
> +
> BRCMNAND_CS_ACC_CONTROL);
> + bool sector_size_1k = brcmnand_get_sector_size_1k(host);
> + int spare_area_size, ecc_level;
> + u32 acc;
> +
> + spare_area_size = brcmnand_get_spare_size(host);
> + acc = nand_readreg(ctrl, acc_control_offs);
> + ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl-
> >ecc_level_shift;
> + if (sector_size_1k)
> + chip->ecc.strength = ecc_level * 2;
> + else if (spare_area_size == 16 && ecc_level == 15)
> + chip->ecc.strength = 1; /* hamming */
> + else
> + chip->ecc.strength = ecc_level;
> +
> + if (chip->ecc.size == 0) {
> + if (sector_size_1k)
> + chip->ecc.size = 1024;
> + else
> + chip->ecc.size = 512;
> + }
> +}
> +
>
> /**
> *
> * CS_NAND_SELECT
>
> **
> */
> @@ -2323,12 +2360,33 @@ static int brcmnand_setup_dev(struct
> brcmnand_host *host)
> struct nand_memory_organization *memorg =
> nanddev_get_memorg(nanddev);
> struct brcmnand_controller *ctrl = host->ctrl;
> struct brcmnand_cfg *cfg = &host->hwcfg;
> - char msg[128];
> u32 offs, tmp, oob_sector;
> + bool use_strap = false;
> + char msg[128];
> int ret;
>
> memset(cfg, 0, sizeof(*cfg));
>
> +#ifndef __UBOOT__
> + use_strap = of_property_read_bool(nand_get_flash_node(chip),
> + "brcm,nand-ecc-use-strap"):
> +#else
> + ret = ofnode_read_bool(nand_get_flash_node(chip),
> +"brcm,nand-ecc-use-strap");
> +#endif /* __UBOOT__ */
> + /*
> + * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error
> out
>
RE: [PATCH 7/7] mtd: rawnand: brcmnand: Add support for getting ecc setting from strap
> -Original Message-
> From: Linus Walleij
> Sent: Wednesday, September 11, 2024 12:11 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; David Regan
> ; Miquel Raynal
> Subject: [PATCH 7/7] mtd: rawnand: brcmnand: Add support for getting ecc
> setting from strap
>
> From: William Zhang
>
> Backport from the upstream Linux kernel
> commit c2cf7e25eb2a3c915a420fb8ceed8912add7f36c
> "mtd: rawnand: brcmnand: Add support for getting ecc setting from strap"
>
> Note: the upstream kernel introduces a new
> bool brcmnand_get_sector_size_1k() function because the int
> version in U-Boot has been removed in Linux. I kept the old
> int-returning version that is already in U-Boot as we depend
> on that in other code.
>
> BCMBCA broadband SoC based board design does not specify ecc setting in
> dts but rather use the SoC NAND strap info to obtain the ecc strength
> and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for
> this purpose and update driver to support this option. However these two
> options can not be used at the same time.
>
> Signed-off-by: William Zhang
> Reviewed-by: David Regan
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20240301173308.226004-1-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 70
> ++--
> 1 file changed, 66 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 55d5d27438a8..1ffd6cfff98f 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -980,6 +980,43 @@ static void brcmnand_set_sector_size_1k(struct
> brcmnand_host *host, int val)
> nand_writereg(ctrl, acc_control_offs, tmp);
> }
>
> +static int brcmnand_get_spare_size(struct brcmnand_host *host)
> +{
> + struct brcmnand_controller *ctrl = host->ctrl;
> + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
> +
> BRCMNAND_CS_ACC_CONTROL);
> + u32 acc = nand_readreg(ctrl, acc_control_offs);
> +
> + return (acc & brcmnand_spare_area_mask(ctrl));
> +}
> +
> +static void brcmnand_get_ecc_settings(struct brcmnand_host *host,
> struct nand_chip *chip)
> +{
> + struct brcmnand_controller *ctrl = host->ctrl;
> + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
> +
> BRCMNAND_CS_ACC_CONTROL);
> + bool sector_size_1k = brcmnand_get_sector_size_1k(host);
> + int spare_area_size, ecc_level;
> + u32 acc;
> +
> + spare_area_size = brcmnand_get_spare_size(host);
> + acc = nand_readreg(ctrl, acc_control_offs);
> + ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl-
> >ecc_level_shift;
> + if (sector_size_1k)
> + chip->ecc.strength = ecc_level * 2;
> + else if (spare_area_size == 16 && ecc_level == 15)
> + chip->ecc.strength = 1; /* hamming */
> + else
> + chip->ecc.strength = ecc_level;
> +
> + if (chip->ecc.size == 0) {
> + if (sector_size_1k)
> + chip->ecc.size = 1024;
> + else
> + chip->ecc.size = 512;
> + }
> +}
> +
>
> /**
> *
> * CS_NAND_SELECT
>
> **
> */
> @@ -2323,12 +2360,33 @@ static int brcmnand_setup_dev(struct
> brcmnand_host *host)
> struct nand_memory_organization *memorg =
> nanddev_get_memorg(nanddev);
> struct brcmnand_controller *ctrl = host->ctrl;
> struct brcmnand_cfg *cfg = &host->hwcfg;
> - char msg[128];
> u32 offs, tmp, oob_sector;
> + bool use_strap = false;
> + char msg[128];
> int ret;
>
> memset(cfg, 0, sizeof(*cfg));
>
> +#ifndef __UBOOT__
> + use_strap = of_property_read_bool(nand_get_flash_node(chip),
> + "brcm,nand-ecc-use-strap"):
> +#else
> + ret = ofnode_read_bool(nand_get_flash_node(chip),
use_strap = ofnode_read_bool(nand_get_flash_node(chip),
> +"brcm,nand-ecc-use-strap");
> +#endif /* __UBOOT__ */
> + /*
> + * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error
> out
> + * if both exist.
> + */
> + if (chip->ecc.strength && use_strap
RE: [PATCH 6/7] mtd: rawnand: brcmnand: Support write protection setting from dts
> -Original Message-
> From: Linus Walleij
> Sent: Wednesday, September 11, 2024 12:11 AM
> To: u-boot@lists.denx.de; Dario Binacchi
> ; Michael Trimarchi
> ; Anand Gore
> ; William Zhang
> ; Kursad Oney
> ; Philippe Reynes
>
> Cc: Linus Walleij ; Florian Fainelli
> ; Kamal Dasu
> ; David Regan ;
> Miquel Raynal
> Subject: [PATCH 6/7] mtd: rawnand: brcmnand: Support write protection
> setting from dts
>
> From: William Zhang
>
> Backport of upstream Linux
> commit 8e7daa85641c9559c113f6b217bdc923397de77c
> "mtd: rawnand: brcmnand: Support write protection setting from dts"
>
> The write protection feature is controlled by the module parameter wp_on
> with default set to enabled. But not all the board use this feature
> especially in BCMBCA broadband board. And module parameter is not
> sufficient as different board can have different option. Add a device
> tree property and allow this feature to be configured through the board
> dts on per board basis.
>
> Signed-off-by: William Zhang
> Reviewed-by: Florian Fainelli
> Reviewed-by: Kamal Dasu
> Reviewed-by: David Regan
> Signed-off-by: Miquel Raynal
> Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-
> william.zh...@broadcom.com
> Signed-off-by: Linus Walleij
> ---
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 2f786584a1ae..55d5d27438a8 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -2847,6 +2847,14 @@ int brcmnand_probe(struct udevice *dev,
> struct brcmnand_soc *soc)
> /* Read the write-protect configuration in the device tree */
> wp_on = dev_read_u32_default(dev, "write-protect", wp_on);
>
There is some dts file using this "write-protect" property. I believe
Phiippe
originally added but it was not upstreamed to linux. The new one in the
line
below is upstreamed and documented in brcmnand.yaml. For new dts,
we should use this new property. But we should still honor the old
flag to make sure old dtb still works instead of overriding it here.
> + /* Check if the board connects the WP pin */
> +#ifndef __UBOOT__
> + if (of_property_read_bool(dn, "brcm,wp-not-connected"))
> +#else
> + if (dev_read_bool(ctrl->dev, "brcm,wp-not-connected"))
> +#endif /* __UBOOT__ */
> + wp_on = 0;
> +
> if (ctrl->features & BRCMNAND_HAS_WP) {
> /* Permanently disable write protection */
> if (wp_on == 2)
>
> --
> 2.46.0
smime.p7s
Description: S/MIME Cryptographic Signature
RE: [PATCH 0/7] mtd: nand: brcmnand: Backported fixes from Linux
> -Original Message- > From: Linus Walleij > Sent: Thursday, September 12, 2024 1:16 AM > To: William Zhang > Cc: u-boot@lists.denx.de; Dario Binacchi > ; Michael Trimarchi > ; Anand Gore > ; Kursad Oney > ; Philippe Reynes > ; Florian Fainelli > ; Miquel Raynal > ; Kamal Dasu ; > David Regan > Subject: Re: [PATCH 0/7] mtd: nand: brcmnand: Backported fixes from > Linux > > On Thu, Sep 12, 2024 at 3:32 AM William Zhang > wrote: > > > Thanks for merging the patches to u-boot. We actually had something > > similar > > here locally but just didn't get the chance to upstream yet. > > > > We will review and compare your patches to ours and get back to you. > > Ah, excellent, I guess you guys know the stuff better than me > so I prefer if your patches are used. > > Do you even have U-Boot working on BCMBCA? I didn't get the > NAND to detect properly yet despite all the backported patches. :/ > Yes we have it working. And your patches works too after fixing two Issues that I will comment on the specific patch. You will need to enable the NAND related configurations and the nand dts node. You can use existing dts node to set the specific ecc level, oob size and ecc step size. Or use the new automatically detection from the strap property brcm,nand-ecc-use-strap that I upstreamed to linux. What SoC do you use? > Yours, > Linus Walleij smime.p7s Description: S/MIME Cryptographic Signature
RE: [PATCH 0/7] mtd: nand: brcmnand: Backported fixes from Linux
Hi Linus, Thanks for merging the patches to u-boot. We actually had something similar here locally but just didn't get the chance to upstream yet. We will review and compare your patches to ours and get back to you. Thanks, William > -Original Message- > From: Linus Walleij > Sent: Wednesday, September 11, 2024 12:11 AM > To: u-boot@lists.denx.de; Dario Binacchi > ; Michael Trimarchi > ; Anand Gore > ; William Zhang > ; Kursad Oney > ; Philippe Reynes > > Cc: Linus Walleij ; Florian Fainelli > ; Miquel Raynal > ; Kamal Dasu ; > David Regan > Subject: [PATCH 0/7] mtd: nand: brcmnand: Backported fixes from Linux > > These are a number of assorted upstream Linux fixes to the > BRCMNAND driver that I have backported in an attempt to get > BRCMBCA working with U-Boot (still not there). > > This patch set lowers the hamming distance between the Linux > and U-Boot drivers a bit as well, while we deviate quite > a bit it is still possible to bring fixes over thanks to > exercises like this. > > The set tries to prepare the ground for the BCMBCA driver > which I have a port of which is however not yet working > as it should. This is why the read data callback is included. > > These patches seem to work fine for me with my devices but > I know the maintainers have some nice test farms so try to > put these to test and see if we can merge them. I bet the > Broadcom folks has this on their TODO list anyway. > > Signed-off-by: Linus Walleij > --- > Linus Walleij (1): > mtd: rawnand: brcmnand: Add read data bus interface > > William Zhang (6): > mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 > controller > mtd: rawnand: brcmnand: Fix potential false time out warning > mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob > write > mtd: rawnand: brcmnand: Fix mtd oobsize > mtd: rawnand: brcmnand: Support write protection setting from dts > mtd: rawnand: brcmnand: Add support for getting ecc setting from > strap > > drivers/mtd/nand/raw/brcmnand/brcmnand.c | 206 > --- > drivers/mtd/nand/raw/brcmnand/brcmnand.h | 2 + > 2 files changed, 164 insertions(+), 44 deletions(-) > --- > base-commit: 5f044932413694475422d4b16607dfcf9aff8781 > change-id: 20240911-brcmnand-fixes-dabd75230a63 > > Best regards, > -- > Linus Walleij smime.p7s Description: S/MIME Cryptographic Signature
[PATCH] MAINTAINERS: update Broadcom BCMBCA maintainer
Joel is no longer with Broadcom. Remove his email from bcmbca maintainer list and replace him with myself for stack protection maintainer. Signed-off-by: William Zhang --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 921ce05755a6..7a3b4d3712c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -224,7 +224,6 @@ ARM BROADCOM BCMBCA M: Anand Gore M: William Zhang M: Kursad Oney -M: Joel Peshkin M: Philippe Reynes S: Maintained F: arch/arm/mach-bcmbca/ @@ -1568,7 +1567,7 @@ F:cmd/sqfs.c F: test/py/tests/test_fs/test_squashfs/ STACKPROTECTOR -M: Joel Peshkin +M: William Zhang S: Maintained F: common/stackprot.c F: cmd/stackprot_test.c -- 2.37.3
Re: [PATCH 65/81] spi: Remove and add needed includes
On 05/01/2024 06:31 PM, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini --- Cc: Jagan Teki Cc: Tom Rini Cc: Anand Gore Cc: William Zhang Cc: Kursad Oney Cc: Joel Peshkin Cc: Philippe Reynes Cc: Alex Nemirovsky Cc: Michal Simek Cc: Stefan Roese Cc: Neil Armstrong Cc: Gregory CLEMENT Cc: Lars Povlsen Cc: Horatiu Vultur Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Simon Glass Cc: Chin-Ting Kuo Cc: "Cédric Le Goater" Cc: Aspeed BMC SW team Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Joel Stanley Cc: Robert Marko Cc: Luka Kovacic Cc: Luka Perkov Cc: Masahisa Kojima Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Kunihiko Hayashi Cc: Dai Okamura --- drivers/spi/altera_spi.c | 1 - drivers/spi/apple_spi.c | 1 - drivers/spi/atcspi200_spi.c | 1 - drivers/spi/ath79_spi.c | 1 - drivers/spi/atmel-quadspi.c | 1 - drivers/spi/atmel_spi.c | 1 - drivers/spi/bcm63xx_hsspi.c | 1 - drivers/spi/bcm63xx_spi.c | 1 - drivers/spi/bcmbca_hsspi.c| 1 - drivers/spi/ca_sflash.c | 1 - drivers/spi/cadence_ospi_versal.c | 1 - drivers/spi/cadence_qspi.c| 1 - drivers/spi/cadence_qspi_apb.c| 1 - drivers/spi/cf_spi.c | 1 - drivers/spi/davinci_spi.c | 2 +- drivers/spi/designware_spi.c | 1 - drivers/spi/exynos_spi.c | 1 - drivers/spi/fsl_dspi.c| 1 - drivers/spi/fsl_espi.c| 2 +- drivers/spi/fsl_qspi.c| 1 - drivers/spi/ich.c | 1 - drivers/spi/iproc_qspi.c | 1 - drivers/spi/kirkwood_spi.c| 2 +- drivers/spi/meson_spifc.c | 1 - drivers/spi/microchip_coreqspi.c | 1 - drivers/spi/mpc8xx_spi.c | 1 - drivers/spi/mpc8xxx_spi.c | 1 - drivers/spi/mscc_bb_spi.c | 1 - drivers/spi/mt7621_spi.c | 1 - drivers/spi/mtk_snfi_spi.c| 1 - drivers/spi/mtk_snor.c| 1 - drivers/spi/mvebu_a3700_spi.c | 1 - drivers/spi/mxc_spi.c | 2 +- drivers/spi/mxs_spi.c | 1 - drivers/spi/npcm_pspi.c | 1 - drivers/spi/nxp_fspi.c| 1 - drivers/spi/omap3_spi.c | 2 +- drivers/spi/pic32_spi.c | 1 - drivers/spi/pl022_spi.c | 1 - drivers/spi/renesas_rpc_spi.c | 1 - drivers/spi/rk_spi.c | 1 - drivers/spi/sandbox_spi.c | 1 - drivers/spi/sh_qspi.c | 1 - drivers/spi/soft_spi.c| 1 - drivers/spi/spi-aspeed-smc.c | 1 - drivers/spi/spi-emul-uclass.c | 1 - drivers/spi/spi-mem.c | 1 - drivers/spi/spi-mxic.c| 1 - drivers/spi/spi-qup.c | 1 - drivers/spi/spi-sifive.c | 1 - drivers/spi/spi-sn-f-ospi.c | 1 - drivers/spi/spi-sunxi.c | 1 - drivers/spi/spi-synquacer.c | 1 - drivers/spi/spi-uclass.c | 1 - drivers/spi/spi.c | 1 - drivers/spi/stm32_qspi.c | 1 - drivers/spi/stm32_spi.c | 1 - drivers/spi/tegra114_spi.c| 1 - drivers/spi/tegra20_sflash.c | 1 - drivers/spi/tegra20_slink.c | 1 - drivers/spi/tegra210_qspi.c | 1 - drivers/spi/ti_qspi.c | 1 - drivers/spi/uniphier_spi.c| 1 - drivers/spi/xilinx_spi.c | 1 - drivers/spi/zynq_qspi.c | 1 - drivers/spi/zynq_spi.c| 1 - drivers/spi/zynqmp_gqspi.c| 1 - 67 files changed, 5 insertions(+), 67 deletions(-) For drivers/spi/bcm63xx_hsspi.c and drivers/spi/bcmbca_hsspi.c Reviewed-by: William Zhang smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH 43/81] mtd: Remove and add needed includes
On 05/01/2024 06:31 PM, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini --- Cc: Tom Rini Cc: Stefan Roese Cc: Dario Binacchi Cc: Michael Trimarchi Cc: Anand Gore Cc: William Zhang Cc: Kursad Oney Cc: Joel Peshkin Cc: Philippe Reynes Cc: Alex Nemirovsky Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Michal Simek Cc: Frieder Schrempf Cc: Abdellatif El Khlifi Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Jagan Teki Cc: Vignesh R Cc: Nishanth Menon Cc: Sean Anderson --- drivers/mtd/altera_qspi.c | 1 - drivers/mtd/cfi_flash.c | 3 ++- drivers/mtd/cfi_mtd.c | 1 - drivers/mtd/hbmc-am654.c| 1 - drivers/mtd/jedec_flash.c | 1 - drivers/mtd/mtd-uclass.c| 1 - drivers/mtd/mtd_uboot.c | 1 - drivers/mtd/mtdpart.c | 1 - drivers/mtd/nand/bbt.c | 1 - drivers/mtd/nand/core.c | 1 - drivers/mtd/nand/raw/am335x_spl_bch.c | 2 +- drivers/mtd/nand/raw/arasan_nfc.c | 1 - drivers/mtd/nand/raw/atmel_nand.c | 2 +- drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c | 1 - drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c| 1 - drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c| 1 - drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c | 1 - drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c| 1 - drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c| 1 - drivers/mtd/nand/raw/brcmnand/brcmnand.c| 1 - drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c | 1 - drivers/mtd/nand/raw/brcmnand/iproc_nand.c | 1 - drivers/mtd/nand/raw/cortina_nand.c | 1 - drivers/mtd/nand/raw/davinci_nand.c | 2 +- drivers/mtd/nand/raw/denali.c | 1 - drivers/mtd/nand/raw/denali_spl.c | 2 +- drivers/mtd/nand/raw/fsl_elbc_nand.c| 2 +- drivers/mtd/nand/raw/fsl_elbc_spl.c | 2 +- drivers/mtd/nand/raw/fsl_ifc_nand.c | 2 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 2 +- drivers/mtd/nand/raw/kirkwood_nand.c| 1 - drivers/mtd/nand/raw/kmeter1_nand.c | 2 +- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- drivers/mtd/nand/raw/mxc_nand.c | 2 +- drivers/mtd/nand/raw/mxc_nand_spl.c | 2 +- drivers/mtd/nand/raw/mxic_nand.c| 1 - drivers/mtd/nand/raw/mxs_nand.c | 1 - drivers/mtd/nand/raw/mxs_nand_spl.c | 1 - drivers/mtd/nand/raw/nand.c | 2 +- drivers/mtd/nand/raw/nand_base.c| 1 - drivers/mtd/nand/raw/nand_bbt.c | 1 - drivers/mtd/nand/raw/nand_bch.c | 1 - drivers/mtd/nand/raw/nand_ecc.c | 1 - drivers/mtd/nand/raw/nand_ids.c | 1 - drivers/mtd/nand/raw/nand_spl_load.c| 2 +- drivers/mtd/nand/raw/nand_spl_simple.c | 2 +- drivers/mtd/nand/raw/nand_timings.c | 1 - drivers/mtd/nand/raw/nand_util.c| 1 - drivers/mtd/nand/raw/omap_elm.c | 1 - drivers/mtd/nand/raw/omap_gpmc.c| 2 +- drivers/mtd/nand/raw/pxa3xx_nand.c | 1 - drivers/mtd/nand/raw/rockchip_nfc.c | 1 - drivers/mtd/nand/raw/stm32_fmc2_nand.c | 1 - drivers/mtd/nand/raw/sunxi_nand.c | 1 - drivers/mtd/nand/raw/sunxi_nand_spl.c | 1 - drivers/mtd/nand/raw/tegra_nand.c | 1 - drivers/mtd/nand/raw/vf610_nfc.c| 2 +- drivers/mtd/nand/raw/zynq_nand.c| 1 - drivers/mtd/nand/spi/core.c | 1 - drivers/mtd/nvmxip/nvmxip-uclass.c | 1 - drivers/mtd/nvmxip/nvmxip.c | 1 - drivers/mtd/nvmxip/nvmxip_qspi.c| 1 - drivers/mtd/onenand/onenand_base.c | 1 - drivers/mtd/onenand/onenand_bbt.c | 1 - drivers/mtd/onenand/onenand_spl.c | 3 ++- drivers/mtd/onenand/onenand_uboot.c | 2 +- drivers/mtd/onenand/samsung.c | 1 - drivers/mtd/renesas_rpc_hf.c| 1 - drivers/mtd/spi/fsl_espi_spl.c | 2 +- drivers/mtd/spi/sandbox.c | 1 - drivers/mtd/spi/sf-uclass.c | 1 - drivers/mtd/spi/sf_bootdev.c| 1 - drivers/mtd/spi/sf_dataflash.c | 1 - drivers/mtd/spi/sf_mtd.c| 1 - drivers/mtd/spi/sf_probe.c | 1 - drivers/mtd/spi/spi-nor-core.c | 1 - drivers/mtd/spi/spi-nor-ids.c
Re: [PATCH 029/149] board: broadcom: Remove and add needed includes
Hi Tom, On 04/30/2024 07:41 PM, Tom Rini wrote: Remove from this board vendor directory and when needed add missing include files directly. Signed-off-by: Tom Rini --- Cc: Anand Gore Cc: William Zhang Cc: Kursad Oney Cc: Joel Peshkin Cc: Philippe Reynes Cc: Linus Walleij Cc: Rayagonda Kokatanur Cc: Thomas Fitzsimmons --- board/broadcom/bcmbca/board.c | 1 - board/broadcom/bcmns/ns.c | 1 - board/broadcom/bcmns3/ns3.c| 2 +- board/broadcom/bcmstb/bcmstb.c | 1 - 4 files changed, 1 insertion(+), 4 deletions(-) diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c index bcecb4d78392..a6ced92565f9 100644 --- a/board/broadcom/bcmbca/board.c +++ b/board/broadcom/bcmbca/board.c @@ -3,7 +3,6 @@ * (C) Copyright 2022 Broadcom Ltd. */ -#include #include int board_init(void) diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 1249e45af036..45cc62936cec 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -4,7 +4,6 @@ * Copyright (C) 2023 Linus Walleij */ -#include #include #include #include diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 7ae6742c4be8..bb2f1e4f62ad 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -4,8 +4,8 @@ * */ -#include #include +#include #include #include #include diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index aead6f099e81..bc05aecc446d 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include For board/broadcom/bcmbca/board.c Reviewed-by: William Zhang smime.p7s Description: S/MIME Cryptographic Signature
[PATCH] spi: bcm63xx-hsspi: Fix compiler warning
When build for arm64 target, comipler reports the following warning:
drivers/spi/bcm63xx_hsspi.c: In function ‘bcm63xx_hsspi_xfer_dummy_cs’:
include/linux/kernel.h:184:17: warning: comparison of distinct pointer
types lacks a cast
184 | (void) (&_min1 == &_min2); \
| ^~
drivers/spi/bcm63xx_hsspi.c:298:22: note: in expansion of macro ‘min’
298 | size_t curr_step = min(step_size, data_bytes);
This change fix this warning by casting the data_bytes to size_t.
Fixes: 0e144ec38cbb ("spi: bcm63xx-hsspi: Add prepend mode support")
Signed-off-by: William Zhang
---
drivers/spi/bcm63xx_hsspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index a24bb430cbb4..19d9a5ae23cd 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -295,7 +295,7 @@ static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev,
unsigned int data_by
/* transfer loop */
while (data_bytes > 0) {
- size_t curr_step = min(step_size, data_bytes);
+ size_t curr_step = min(step_size, (size_t)data_bytes);
int ret;
/* copy tx data */
--
2.37.3
Re: [PATCH v3 10/10] MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers
Hi Tom, On 08/08/2023 07:02 PM, Tom Rini wrote: On Wed, Jun 07, 2023 at 04:37:10PM -0700, William Zhang wrote: Add entry for Broadcom Broadband SoC HS SPI drivers Signed-off-by: William Zhang Can you please rebase this rest of this series on top of current next and fix the compiler warnings that show up, thanks. Sorry for the delay. I noticed that patch 1 to 6 in this series are already in u-boot/next. I did see compiler warning on bcm63xx_hsspi.c when build for arm64. Should I just provide a new patch for this warning based on the current next? smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH v3 06/10] dt-bindings: spi: Add bcm63xx-hsspi controller support
Hi Jagan, On 06/11/2023 03:43 AM, Jagan Teki wrote: On Thu, Jun 8, 2023 at 5:08 AM William Zhang wrote: Bring the device tree binding document from Linux to u-boot Port from linux patches: Link: https://lore.kernel.org/r/20230207065826.285013-2-william.zh...@broadcom.com Link: https://lore.kernel.org/r/20230207065826.285013-3-william.zh...@broadcom.com Signed-off-by: William Zhang --- Reviewed-by: Jagan Teki Applied to u-boot-spi/master Thank you for accepting the patches. Do you mind to take the rest of the patches in the series as Tom was suggesting it is better to apply the whole thing and there is a dependency on patch 9 if you actually want to build with CONFIG_BCMBCA_HSSPI enabled? If not, maybe Tom can you please apply at least patch 6 to 10 of the series to the u-boot git, if there is no other concern and works for you? smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 08/10] arm64: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv8 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-5-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/bcm4908.dtsi | 17 +
arch/arm/dts/bcm4912.dtsi | 20
arch/arm/dts/bcm63146.dtsi | 19 +++
arch/arm/dts/bcm63158.dtsi | 15 ++-
arch/arm/dts/bcm6813.dtsi | 20
arch/arm/dts/bcm6856.dtsi | 23 ++-
arch/arm/dts/bcm6858.dtsi | 23 ++-
arch/arm/dts/bcm94908.dts | 4
arch/arm/dts/bcm94912.dts | 4
arch/arm/dts/bcm963146.dts | 4
arch/arm/dts/bcm963158.dts | 4
arch/arm/dts/bcm96813.dts | 4
arch/arm/dts/bcm96856.dts | 4
arch/arm/dts/bcm96858.dts | 4
14 files changed, 130 insertions(+), 35 deletions(-)
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
index 0be5cfeeffa9..fc9874623b18 100644
--- a/arch/arm/dts/bcm4908.dtsi
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -106,6 +106,12 @@
clock-frequency = <5000>;
clock-output-names = "periph";
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
bus@ff80 {
@@ -123,5 +129,16 @@
status = "disabled";
};
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4908-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi
index 3d016c2ce675..b10a0ae06187 100644
--- a/arch/arm/dts/bcm4912.dtsi
+++ b/arch/arm/dts/bcm4912.dtsi
@@ -78,6 +78,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -85,6 +86,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -116,6 +123,19 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4912-hsspi",
"brcm,bcmbca-hsspi-v1.1";
+ reg = <0x1000 0x600>, <0x2610 0x4>;
+ reg-names = "hsspi", "spim-ctrl";
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi
index 04de96bd0a03..48226cf1a7d4 100644
--- a/arch/arm/dts/bcm63146.dtsi
+++ b/arch/arm/dts/bcm63146.dtsi
@@ -59,6 +59,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -66,6 +67,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
[PATCH v3 07/10] ARM: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv7 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-4-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/bcm47622.dtsi | 18 ++
arch/arm/dts/bcm63138.dtsi | 18 ++
arch/arm/dts/bcm63148.dtsi | 18 ++
arch/arm/dts/bcm63178.dtsi | 19 +++
arch/arm/dts/bcm6756.dtsi | 19 +++
arch/arm/dts/bcm6846.dtsi | 18 ++
arch/arm/dts/bcm6855.dtsi | 27 +++
arch/arm/dts/bcm6878.dtsi | 19 +++
arch/arm/dts/bcm947622.dts | 4
arch/arm/dts/bcm963138.dts | 4
arch/arm/dts/bcm963148.dts | 4
arch/arm/dts/bcm963178.dts | 4
arch/arm/dts/bcm96756.dts | 4
arch/arm/dts/bcm96846.dts | 4
arch/arm/dts/bcm96855.dts | 4
arch/arm/dts/bcm96878.dts | 4
16 files changed, 180 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi
index c016e12b7372..86b1dff65aca 100644
--- a/arch/arm/dts/bcm47622.dtsi
+++ b/arch/arm/dts/bcm47622.dtsi
@@ -83,6 +83,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -114,6 +120,18 @@
#size-cells = <1>;
ranges = <0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm47622-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
index 42b442aec9f4..2a673c39ba68 100644
--- a/arch/arm/dts/bcm63138.dtsi
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -60,6 +60,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
/* ARM bus */
@@ -145,5 +151,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi
index df5307b6b3af..d9aed2bd7ff0 100644
--- a/arch/arm/dts/bcm63148.dtsi
+++ b/arch/arm/dts/bcm63148.dtsi
@@ -59,6 +59,12 @@
#clock-cells = <0>;
clock-frequency = <5000>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
psci {
@@ -99,5 +105,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63148-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>
[PATCH v3 09/10] broadcom: bcmbca: Enable SPI drivers by default
SPI controller is always presented in BCMBCA platform SoCs so enable the controller driver and SPI core by default. Signed-off-by: William Zhang --- Changes in v3: - Move BCMBCA_HSSPI config enabling and its dependent config from new BCMBCA driver patch to this more relevant patch - Combine multi-line condition into single line for HAVE_SPI_CS_CTRL Changes in v2: None arch/arm/Kconfig | 2 ++ arch/arm/mach-bcmbca/Kconfig | 23 +++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a64780c..c92f6c715861 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -660,6 +660,8 @@ config ARCH_BCMSTB config ARCH_BCMBCA bool "Broadcom broadband chip family" select DM + select DM_SPI + select SPI select OF_CONTROL imply CMD_DM diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 62b371612b6a..e69a71134c8a 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -11,6 +11,7 @@ config BCM47622 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM4908 bool "Support for Broadcom 4908 Family" @@ -18,6 +19,7 @@ config BCM4908 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM4912 bool "Support for Broadcom 4912 Family" @@ -25,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM63138 bool "Support for Broadcom 63138 Family" @@ -33,6 +36,7 @@ config BCM63138 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63146 bool "Support for Broadcom 63146 Family" @@ -40,6 +44,7 @@ config BCM63146 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63148 bool "Support for Broadcom 63148 Family" @@ -47,6 +52,7 @@ config BCM63148 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63158 bool "Support for Broadcom 63158 Family" @@ -54,6 +60,7 @@ config BCM63158 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63178 bool "Support for Broadcom 63178 Family" @@ -61,6 +68,7 @@ config BCM63178 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM6756 bool "Support for Broadcom 6756 Family" @@ -68,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6813 bool "Support for Broadcom 6813 Family" @@ -75,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6846 bool "Support for Broadcom 6846 Family" @@ -82,6 +92,7 @@ config BCM6846 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM6855 bool "Support for Broadcom 6855 Family" @@ -89,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI help Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. @@ -99,6 +111,7 @@ config BCM6856 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. @@ -109,6 +122,7 @@ config BCM6858 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. @@ -119,6 +133,15 @@ config BCM6878 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI + +config HAVE_SPI_CS_CTRL + bool "SoC supports SPI chip select control" + default y if BCM4912 || BCM6756 || BCM6855 || BCM6813 + default n + help + Enable this option if SoC supports SPI chip select control explicitly + through software. source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" -- 2.37.3 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 10/10] MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers
Add entry for Broadcom Broadband SoC HS SPI drivers Signed-off-by: William Zhang --- Changes in v3: None Changes in v2: - Add Álvaro Fernández Rojas as another maintainer MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 228d8af433df..0ebeaee86b33 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -824,6 +824,15 @@ F: include/bootstd.h F: net/eth_bootdevice.c F: test/boot/ +BROADCOM Broadband SoC High Speed SPI Controller DRIVER +M: William Zhang +M: Kursad Oney +M: Álvaro Fernández Rojas +S: Maintained +F: doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml +F: drivers/spi/bcm63xx_hsspi.c +F: drivers/spi/bcmbca_hsspi.c + BTRFS M: Marek Behún R: Qu Wenruo -- 2.37.3 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 05/10] spi: bcmbca-hsspi: Add driver for newer HSSPI controller
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zh...@broadcom.com Signed-off-by: William Zhang --- Changes in v3: - Move arch related Kconfig changes to SPI enabling patch Changes in v2: None drivers/spi/Kconfig| 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 + 3 files changed, 424 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core. +config BCMBCA_HSSPI + bool "BCMBCA HSSPI driver" + depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index ..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski + * Copyright (C) 2021 Broadcom Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 3000 + +/* SPI Control register */ +#define SPI_CTL_REG0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG0x010 + +#define SPI_IR_CLEAR_ALL 0xff001f1f + +/* SPI Ping-Pong Command registers */ +#define SPI_CMD_REG(0x080 + (0x40 * (HSSPI_PP)) + 0x00) +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START BIT(SPI_CMD_OP_SHIFT) +#define SPI_CMD_PFL_SHIFT 8 +#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) +#define SPI_CMD_SLAVE_SHIFT12 +#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT) + +/* SPI Ping-Pong Status registers */ +#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) +#define SPI_STAT_SRCBUSY_SHIFT 1 +#define SPI_STAT_SRCBUSY_MASK BIT(SPI_STAT_SRCBUSY_SHIFT) + +/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK BIT(SPI_PFL_CLK_RSTLOOP_SHIFT) + +/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK BIT(SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK BIT(SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK BIT(SPI_PFL_SIG_ASYNCIN_SHIFT) + +/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(
[PATCH v3 06/10] dt-bindings: spi: Add bcm63xx-hsspi controller support
Bring the device tree binding document from Linux to u-boot
Port from linux patches:
Link:
https://lore.kernel.org/r/20230207065826.285013-2-william.zh...@broadcom.com
Link:
https://lore.kernel.org/r/20230207065826.285013-3-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v3: None
Changes in v2: None
.../spi/brcm,bcm63xx-hsspi.yaml | 134 ++
1 file changed, 134 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
diff --git a/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
new file mode 100644
index ..6554978583f8
--- /dev/null
+++ b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC High Speed SPI controller
+
+maintainers:
+ - William Zhang
+ - Kursad Oney
+ - Jonas Gorski
+
+description: |
+ Broadcom Broadband SoC supports High Speed SPI master controller since the
+ early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
+ controller was carried over to recent ARM based chips, such as BCM63138,
+ BCM4908 and BCM6858. The old MIPS based chip should continue to use the
+ brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required
to
+ use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
+ defined below to match the specific chip along with ip revision info.
+
+ This rev 1.0 controller has a limitation that can not keep the chip select
line
+ active between the SPI transfers within the same SPI message. This can
+ terminate the transaction to some SPI devices prematurely. The issue can be
+ worked around by either the controller's prepend mode or using the dummy chip
+ select workaround. Driver automatically picks the suitable mode based on
+ transfer type so it is transparent to the user.
+
+ The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI
+ controller rev 1.1 that add the capability to allow the driver to control
chip
+ select explicitly. This solves the issue in the old controller.
+
+properties:
+ compatible:
+oneOf:
+ - const: brcm,bcm6328-hsspi
+ - items:
+ - enum:
+ - brcm,bcm47622-hsspi
+ - brcm,bcm4908-hsspi
+ - brcm,bcm63138-hsspi
+ - brcm,bcm63146-hsspi
+ - brcm,bcm63148-hsspi
+ - brcm,bcm63158-hsspi
+ - brcm,bcm63178-hsspi
+ - brcm,bcm6846-hsspi
+ - brcm,bcm6856-hsspi
+ - brcm,bcm6858-hsspi
+ - brcm,bcm6878-hsspi
+ - const: brcm,bcmbca-hsspi-v1.0
+ - items:
+ - enum:
+ - brcm,bcm4912-hsspi
+ - brcm,bcm6756-hsspi
+ - brcm,bcm6813-hsspi
+ - brcm,bcm6855-hsspi
+ - const: brcm,bcmbca-hsspi-v1.1
+
+ reg:
+items:
+ - description: main registers
+ - description: miscellaneous control registers
+minItems: 1
+
+ reg-names:
+items:
+ - const: hsspi
+ - const: spim-ctrl
+minItems: 1
+
+ clocks:
+items:
+ - description: SPI master reference clock
+ - description: SPI master pll clock
+
+ clock-names:
+items:
+ - const: hsspi
+ - const: pll
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - brcm,bcm6328-hsspi
+ - brcm,bcmbca-hsspi-v1.0
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+else:
+ properties:
+reg:
+ minItems: 2
+ maxItems: 2
+reg-names:
+ minItems: 2
+ maxItems: 2
+ required:
+- reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+spi@ff801000 {
+compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
+reg = <0xff801000 0x1000>,
+ <0xff802610 0x4>;
+reg-names = "hsspi", "spim-ctrl";
+interrupts = ;
+clocks = <&hsspi>, <&hsspi_pll>;
+clock-names = "hsspi", "pll";
+num-cs = <8>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
--
2.37.3
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v3 04/10] spi: bcm63xx-hsspi: Add prepend mode support
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-12-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v3: None
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 259 +---
1 file changed, 242 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 0d12c345b1dd..a24bb430cbb4 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -20,7 +20,13 @@
#define HSSPI_PP 0
-#define SPI_MAX_SYNC_CLOCK 3000
+/*
+ * The maximum frequency for SPI synchronous mode is 30MHz for some chips and
+ * 25MHz for some others. This depends on the chip layout and SPI signals
+ * distance to the pad. We use the lower of these values to cover all relevant
+ * chips.
+ */
+#define SPI_MAX_SYNC_CLOCK 2500
/* SPI Control register */
#define SPI_CTL_REG0x000
@@ -72,12 +78,16 @@
#define SPI_PFL_MODE_REG(x)(0x100 + (0x20 * (x)) + 0x08)
#define SPI_PFL_MODE_FILL_SHIFT0
#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDST_SHIFT 8
+#define SPI_PFL_MODE_MDWRST_SHIFT 12
#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
#define SPI_PFL_MODE_3WIRE_SHIFT 20
#define SPI_PFL_MODE_3WIRE_MASK(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+#define SPI_PFL_MODE_PREPCNT_SHIFT 24
+#define SPI_PFL_MODE_PREPCNT_MASK (4 << SPI_PFL_MODE_PREPCNT_SHIFT)
/* SPI Ping-Pong FIFO registers */
#define HSSPI_FIFO_SIZE0x200
@@ -96,12 +106,21 @@
#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_MAX_DATA_SIZE(HSSPI_FIFO_SIZE -
HSSPI_FIFO_OP_SIZE)
+#define HSSPI_MAX_PREPEND_SIZE 15
+
+#define HSSPI_XFER_MODE_PREPEND0
+#define HSSPI_XFER_MODE_DUMMYCS1
+
struct bcm63xx_hsspi_priv {
void __iomem *regs;
ulong clk_rate;
uint8_t num_cs;
uint8_t cs_pols;
uint speed;
+ uint xfer_mode;
+ uint32_t prepend_cnt;
+ uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE];
};
static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
@@ -143,9 +162,16 @@ static void bcm63xx_hsspi_activate_cs(struct
bcm63xx_hsspi_priv *priv,
struct dm_spi_slave_plat *plat)
{
uint32_t clr, set;
+ uint speed = priv->speed;
+
+ if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS &&
+ speed > SPI_MAX_SYNC_CLOCK) {
+ speed = SPI_MAX_SYNC_CLOCK;
+ debug("Force to dummy cs mode. Reduce the speed to %dHz\
[PATCH v3 03/10] spi: bcm63xx-hsspi: Add new compatible string support
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-6-william.zh...@broadcom.com
Signed-off-by: William Zhang
Reviewed-by: Jagan Teki
---
Changes in v3:
- Add Reviewed-by tag
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index ea34da2a3165..0d12c345b1dd 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -313,6 +313,7 @@ static const struct dm_spi_ops bcm63xx_hsspi_ops = {
static const struct udevice_id bcm63xx_hsspi_ids[] = {
{ .compatible = "brcm,bcm6328-hsspi", },
+ { .compatible = "brcm,bcmbca-hsspi-v1.0", },
{ /* sentinel */ }
};
--
2.37.3
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v3 02/10] spi: bcm63xx-hsspi: Fix multi-bit mode setting
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-11-william.zh...@broadcom.com
Signed-off-by: William Zhang
Reviewed-by: Jagan Teki
---
Changes in v3:
- Add Reviewed-by tag
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4d714adc4afd..ea34da2a3165 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -221,7 +221,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned
int bitlen,
size_t data_bytes = bitlen / 8;
size_t step_size = HSSPI_FIFO_SIZE;
uint16_t opcode = 0;
- uint32_t val;
+ uint32_t val = SPI_PFL_MODE_FILL_MASK;
const uint8_t *tx = dout;
uint8_t *rx = din;
@@ -240,14 +240,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev,
unsigned int bitlen,
step_size -= HSSPI_FIFO_OP_SIZE;
/* dual mode */
- if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
- (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
+ if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+ (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
opcode |= HSSPI_FIFO_OP_MBIT_MASK;
- /* profile mode */
- val = SPI_PFL_MODE_FILL_MASK |
- SPI_PFL_MODE_MDRDSZ_MASK |
- SPI_PFL_MODE_MDWRSZ_MASK;
+ /* profile mode */
+ if (plat->mode & SPI_RX_DUAL)
+ val |= SPI_PFL_MODE_MDRDSZ_MASK;
+ if (plat->mode & SPI_TX_DUAL)
+ val |= SPI_PFL_MODE_MDWRSZ_MASK;
+ }
+
if (plat->mode & SPI_3WIRE)
val |= SPI_PFL_MODE_3WIRE_MASK;
writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
--
2.37.3
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v3 01/10] spi: bcm63xx-hsspi: Make driver depend on BCMBCA arch
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC for common features and IP blocks. Use this config instead of each chip config as the Kconfig dependency for Broadcom HSSPI driver. Signed-off-by: William Zhang --- Changes in v3: None Changes in v2: None drivers/spi/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4f435fd26819..47a261f1e1b8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -101,9 +101,9 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158) + depends on (ARCH_BMIPS || ARCH_BCMBCA) help - Enable the BCM6328 HSSPI driver. This driver can be used to + Enable the BCM63XX HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom SPI core. -- 2.37.3 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 00/10] spi: bcm63xx-hsspi: driver and doc updates
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. Changes in v3: - Add Reviewed-by tags - Reorder the patch series for SPI changes and arch/doc changes - Move arch related Kconfig changes to SPI enabling patch - Separate the Kconfig BCM63XX_HSSPI dependency change to a dedicate patch - Combine multi-line condition into single line for config HAVE_SPI_CS_CTRL Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (10): spi: bcm63xx-hsspi: Make driver depend on BCMBCA arch spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node broadcom: bcmbca: Enable SPI drivers by default MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers MAINTAINERS | 9 + arch/arm/Kconfig | 2 + arch/arm/dts/bcm47622.dtsi| 18 + arch/arm/dts/bcm4908.dtsi | 17 + arch/arm/dts/bcm4912.dtsi | 20 + arch/arm/dts/bcm63138.dtsi| 18 + arch/arm/dts/bcm63146.dtsi| 19 + arch/arm/dts/bcm63148.dtsi| 18 + arch/arm/dts/bcm63158.dtsi| 15 +- arch/arm/dts/bcm63178.dtsi| 19 + arch/arm/dts/bcm6756.dtsi | 19 + arch/arm/dts/bcm6813.dtsi | 20 + arch/arm/dts/bcm6846.dtsi | 18 + arch/arm/dts/bcm6855.dtsi | 27 +- arch/arm/dts/bcm6856.dtsi | 23 +- arch/arm/dts/bcm6858.dtsi | 23 +- arch/arm/dts/bcm6878.dtsi | 19 + arch/arm/dts/bcm947622.dts| 4 + arch/arm/dts/bcm94908.dts | 4 + arch/arm/dts/bcm94912.dts | 4 + arch/arm/dts/bcm963138.dts| 4 + arch/arm/dts/bcm963146.dts| 4 + arch/arm/dts/bcm963148.dts| 4 + arch/arm/dts/bcm963158.dts| 4 + arch/arm/dts/bcm963178.dts| 4 + arch/arm/dts/bcm96756.dts | 4 + arch/arm/dts/bcm96813.dts | 4 + arch/arm/dts/bcm96846.dts | 4 + arch/arm/dts/bcm96855.dts | 4 + arch/arm/dts/bcm96856.dts | 4 + arch/arm/dts/bcm96858.dts | 4 + arch/arm/dts/bcm96878.dts | 4 + arch/arm/mach-bcmbca/Kconfig | 23 + .../spi/brcm,bcm63xx-hsspi.yaml | 134 ++ drivers/spi/Kconfig | 13 +- drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 277 +++- drivers/spi/bcmbca_hsspi.c| 414 ++ 38 files changed, 1157 insertions(+), 69 deletions(-) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml create mode 100644 drivers/spi/bcmbca_hsspi.c -- 2.37.3 smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates
Hi Tom, On 06/07/2023 01:05 PM, Tom Rini wrote: On Tue, Jun 06, 2023 at 01:19:47PM -0700, William Zhang wrote: Hi Jagan, On 06/02/2023 11:56 AM, William Zhang wrote: Hi Jagan, On 06/01/2023 11:01 PM, Jagan Teki wrote: On Wed, May 3, 2023 at 12:29 AM William Zhang wrote: This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting This will fix for the upcoming release. spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers Patches send the patches related to SPI as separate series. Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca. Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes There is one issue in separating the patches to SPI only changes and arch/dts changes. The new BCMBCA HSSPI driver depends on a new config HAVE_SPI_CS_CTRL that is added to arch/arm/mach-bcmbca/Kconfig in the arch change patch series. So you will get build error on generating the .config and have to pick that change to avoid that issue. Will that be okay? Frankly I'd rather the whole series just come in via Jagan's tree, or if he's uncomfortable with that, I'll take the whole series if he's fine with the SPI side. We don't need to worry about which sub-tree is used so long as maintainers are happy with the contents, in U-Boot, imho. Sounds good and thanks Tom! Let me send out the v3 of the whole series some time late today. smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates
Hi Jagan, On 06/02/2023 11:56 AM, William Zhang wrote: Hi Jagan, On 06/01/2023 11:01 PM, Jagan Teki wrote: On Wed, May 3, 2023 at 12:29 AM William Zhang wrote: This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting This will fix for the upcoming release. spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers Patches send the patches related to SPI as separate series. Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca. Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes There is one issue in separating the patches to SPI only changes and arch/dts changes. The new BCMBCA HSSPI driver depends on a new config HAVE_SPI_CS_CTRL that is added to arch/arm/mach-bcmbca/Kconfig in the arch change patch series. So you will get build error on generating the .config and have to pick that change to avoid that issue. Will that be okay? Thanks, Jagan. smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates
Hi Jagan, On 06/01/2023 11:01 PM, Jagan Teki wrote: On Wed, May 3, 2023 at 12:29 AM William Zhang wrote: This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting This will fix for the upcoming release. spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers Patches send the patches related to SPI as separate series. Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca. Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes Thanks, Jagan. smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH v2 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller
Hi Jagan, On 06/01/2023 10:54 PM, Jagan Teki wrote: On Wed, May 3, 2023 at 12:29 AM William Zhang wrote: The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zh...@broadcom.com Signed-off-by: William Zhang --- Changes in v2: None arch/arm/mach-bcmbca/Kconfig | 15 ++ Exclude this from spi driver patch. Driver has to be a separate patch. Sure drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM63138 bool "Support for Broadcom 63138 Family" @@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6813 bool "Support for Broadcom 6813 Family" @@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6846 bool "Support for Broadcom 6846 Family" @@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI help Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. @@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI +config HAVE_SPI_CS_CTRL + bool "SoC supports SPI chip select control" + default y if BCM4912 + default y if BCM6756 + default y if BCM6855 + default y if BCM6813 Use || Will update + default n + help + Enable this option if SoC supports SPI chip select control explicitly + through software. + source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core. +config BCMBCA_HSSPI + bool "BCMBCA HSSPI driver" + depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index ..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski + * Copyright (C) 2021 Broadcom Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 3000 What is this clock? spi-max-frequency ? if yes pick it from DT. Not spi-max-frequency. This is the controller internal setting that determines if controller works in sync or async mode when clock is below or above this
Re: [PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates
Hi Jagan and Tom, Any chance to get this patch series into the u-boot? I haven't heard any feedback and comments but they are largely based on patch series for linux that was accepted in kernel stable release 6.3 and verified on Broadcom reference boards. Thanks, William On 05/02/2023 11:58 AM, William Zhang wrote: This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers MAINTAINERS | 9 + arch/arm/Kconfig | 2 + arch/arm/dts/bcm47622.dtsi| 18 + arch/arm/dts/bcm4908.dtsi | 17 + arch/arm/dts/bcm4912.dtsi | 20 + arch/arm/dts/bcm63138.dtsi| 18 + arch/arm/dts/bcm63146.dtsi| 19 + arch/arm/dts/bcm63148.dtsi| 18 + arch/arm/dts/bcm63158.dtsi| 15 +- arch/arm/dts/bcm63178.dtsi| 19 + arch/arm/dts/bcm6756.dtsi | 19 + arch/arm/dts/bcm6813.dtsi | 20 + arch/arm/dts/bcm6846.dtsi | 18 + arch/arm/dts/bcm6855.dtsi | 27 +- arch/arm/dts/bcm6856.dtsi | 23 +- arch/arm/dts/bcm6858.dtsi | 23 +- arch/arm/dts/bcm6878.dtsi | 19 + arch/arm/dts/bcm947622.dts| 4 + arch/arm/dts/bcm94908.dts | 4 + arch/arm/dts/bcm94912.dts | 4 + arch/arm/dts/bcm963138.dts| 4 + arch/arm/dts/bcm963146.dts| 4 + arch/arm/dts/bcm963148.dts| 4 + arch/arm/dts/bcm963158.dts| 4 + arch/arm/dts/bcm963178.dts| 4 + arch/arm/dts/bcm96756.dts | 4 + arch/arm/dts/bcm96813.dts | 4 + arch/arm/dts/bcm96846.dts | 4 + arch/arm/dts/bcm96855.dts | 4 + arch/arm/dts/bcm96856.dts | 4 + arch/arm/dts/bcm96858.dts | 4 + arch/arm/dts/bcm96878.dts | 4 + arch/arm/mach-bcmbca/Kconfig | 26 ++ .../spi/brcm,bcm63xx-hsspi.yaml | 134 ++ drivers/spi/Kconfig | 13 +- drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 277 +++- drivers/spi/bcmbca_hsspi.c| 414 ++ 38 files changed, 1160 insertions(+), 69 deletions(-) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml create mode 100644 drivers/spi/bcmbca_hsspi.c smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers MAINTAINERS | 9 + arch/arm/Kconfig | 2 + arch/arm/dts/bcm47622.dtsi| 18 + arch/arm/dts/bcm4908.dtsi | 17 + arch/arm/dts/bcm4912.dtsi | 20 + arch/arm/dts/bcm63138.dtsi| 18 + arch/arm/dts/bcm63146.dtsi| 19 + arch/arm/dts/bcm63148.dtsi| 18 + arch/arm/dts/bcm63158.dtsi| 15 +- arch/arm/dts/bcm63178.dtsi| 19 + arch/arm/dts/bcm6756.dtsi | 19 + arch/arm/dts/bcm6813.dtsi | 20 + arch/arm/dts/bcm6846.dtsi | 18 + arch/arm/dts/bcm6855.dtsi | 27 +- arch/arm/dts/bcm6856.dtsi | 23 +- arch/arm/dts/bcm6858.dtsi | 23 +- arch/arm/dts/bcm6878.dtsi | 19 + arch/arm/dts/bcm947622.dts| 4 + arch/arm/dts/bcm94908.dts | 4 + arch/arm/dts/bcm94912.dts | 4 + arch/arm/dts/bcm963138.dts| 4 + arch/arm/dts/bcm963146.dts| 4 + arch/arm/dts/bcm963148.dts| 4 + arch/arm/dts/bcm963158.dts| 4 + arch/arm/dts/bcm963178.dts| 4 + arch/arm/dts/bcm96756.dts | 4 + arch/arm/dts/bcm96813.dts | 4 + arch/arm/dts/bcm96846.dts | 4 + arch/arm/dts/bcm96855.dts | 4 + arch/arm/dts/bcm96856.dts | 4 + arch/arm/dts/bcm96858.dts | 4 + arch/arm/dts/bcm96878.dts | 4 + arch/arm/mach-bcmbca/Kconfig | 26 ++ .../spi/brcm,bcm63xx-hsspi.yaml | 134 ++ drivers/spi/Kconfig | 13 +- drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 277 +++- drivers/spi/bcmbca_hsspi.c| 414 ++ 38 files changed, 1160 insertions(+), 69 deletions(-) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml create mode 100644 drivers/spi/bcmbca_hsspi.c -- 2.37.3
[PATCH v2 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zh...@broadcom.com Signed-off-by: William Zhang --- Changes in v2: None arch/arm/mach-bcmbca/Kconfig | 15 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM63138 bool "Support for Broadcom 63138 Family" @@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6813 bool "Support for Broadcom 6813 Family" @@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6846 bool "Support for Broadcom 6846 Family" @@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI help Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. @@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI +config HAVE_SPI_CS_CTRL + bool "SoC supports SPI chip select control" + default y if BCM4912 + default y if BCM6756 + default y if BCM6855 + default y if BCM6813 + default n + help + Enable this option if SoC supports SPI chip select control explicitly + through software. + source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core. +config BCMBCA_HSSPI + bool "BCMBCA HSSPI driver" + depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index ..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski + * Copyright (C) 2021 Broadcom Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 3000 + +/* SPI Control register */ +#define SPI_CTL_REG0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT
[PATCH v2 6/9] spi: bcm63xx-hsspi: Fix multi-bit mode setting
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-11-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 495feba02262..0d12c345b1dd 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -221,7 +221,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned
int bitlen,
size_t data_bytes = bitlen / 8;
size_t step_size = HSSPI_FIFO_SIZE;
uint16_t opcode = 0;
- uint32_t val;
+ uint32_t val = SPI_PFL_MODE_FILL_MASK;
const uint8_t *tx = dout;
uint8_t *rx = din;
@@ -240,14 +240,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev,
unsigned int bitlen,
step_size -= HSSPI_FIFO_OP_SIZE;
/* dual mode */
- if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
- (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
+ if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+ (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
opcode |= HSSPI_FIFO_OP_MBIT_MASK;
- /* profile mode */
- val = SPI_PFL_MODE_FILL_MASK |
- SPI_PFL_MODE_MDRDSZ_MASK |
- SPI_PFL_MODE_MDWRSZ_MASK;
+ /* profile mode */
+ if (plat->mode & SPI_RX_DUAL)
+ val |= SPI_PFL_MODE_MDRDSZ_MASK;
+ if (plat->mode & SPI_TX_DUAL)
+ val |= SPI_PFL_MODE_MDWRSZ_MASK;
+ }
+
if (plat->mode & SPI_3WIRE)
val |= SPI_PFL_MODE_3WIRE_MASK;
writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
--
2.37.3
[PATCH v2 7/9] spi: bcm63xx-hsspi: Add prepend mode support
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-12-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 259 +---
1 file changed, 242 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 0d12c345b1dd..a24bb430cbb4 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -20,7 +20,13 @@
#define HSSPI_PP 0
-#define SPI_MAX_SYNC_CLOCK 3000
+/*
+ * The maximum frequency for SPI synchronous mode is 30MHz for some chips and
+ * 25MHz for some others. This depends on the chip layout and SPI signals
+ * distance to the pad. We use the lower of these values to cover all relevant
+ * chips.
+ */
+#define SPI_MAX_SYNC_CLOCK 2500
/* SPI Control register */
#define SPI_CTL_REG0x000
@@ -72,12 +78,16 @@
#define SPI_PFL_MODE_REG(x)(0x100 + (0x20 * (x)) + 0x08)
#define SPI_PFL_MODE_FILL_SHIFT0
#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDST_SHIFT 8
+#define SPI_PFL_MODE_MDWRST_SHIFT 12
#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
#define SPI_PFL_MODE_3WIRE_SHIFT 20
#define SPI_PFL_MODE_3WIRE_MASK(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+#define SPI_PFL_MODE_PREPCNT_SHIFT 24
+#define SPI_PFL_MODE_PREPCNT_MASK (4 << SPI_PFL_MODE_PREPCNT_SHIFT)
/* SPI Ping-Pong FIFO registers */
#define HSSPI_FIFO_SIZE0x200
@@ -96,12 +106,21 @@
#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_MAX_DATA_SIZE(HSSPI_FIFO_SIZE -
HSSPI_FIFO_OP_SIZE)
+#define HSSPI_MAX_PREPEND_SIZE 15
+
+#define HSSPI_XFER_MODE_PREPEND0
+#define HSSPI_XFER_MODE_DUMMYCS1
+
struct bcm63xx_hsspi_priv {
void __iomem *regs;
ulong clk_rate;
uint8_t num_cs;
uint8_t cs_pols;
uint speed;
+ uint xfer_mode;
+ uint32_t prepend_cnt;
+ uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE];
};
static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
@@ -143,9 +162,16 @@ static void bcm63xx_hsspi_activate_cs(struct
bcm63xx_hsspi_priv *priv,
struct dm_spi_slave_plat *plat)
{
uint32_t clr, set;
+ uint speed = priv->speed;
+
+ if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS &&
+ speed > SPI_MAX_SYNC_CLOCK) {
+ speed = SPI_MAX_SYNC_CLOCK;
+ debug("Force to dummy cs mode. Reduce the speed to %dHz\n",
speed);
+ }
[PATCH v2 9/9] MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers
Add entry for Broadcom Broadband SoC HS SPI drivers Signed-off-by: William Zhang --- Changes in v2: - Add Álvaro Fernández Rojas as another maintainer MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4c17c6cb9f1e..a1d490e66ed4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -823,6 +823,15 @@ F: include/bootstd.h F: net/eth_bootdevice.c F: test/boot/ +BROADCOM Broadband SoC High Speed SPI Controller DRIVER +M: William Zhang +M: Kursad Oney +M: Álvaro Fernández Rojas +S: Maintained +F: doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml +F: drivers/spi/bcm63xx_hsspi.c +F: drivers/spi/bcmbca_hsspi.c + BTRFS M: Marek Behún R: Qu Wenruo -- 2.37.3
[PATCH v2 5/9] spi: bcm63xx-hsspi: Add new compatible string support
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-6-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4d714adc4afd..495feba02262 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -310,6 +310,7 @@ static const struct dm_spi_ops bcm63xx_hsspi_ops = {
static const struct udevice_id bcm63xx_hsspi_ids[] = {
{ .compatible = "brcm,bcm6328-hsspi", },
+ { .compatible = "brcm,bcmbca-hsspi-v1.0", },
{ /* sentinel */ }
};
--
2.37.3
[PATCH v2 4/9] spi: bcm63xx-hsspi: Enable SPI drivers by default
SPI controller is always presented in BCMBCA platform SoCs so enable the controller driver and SPI core by default. Signed-off-by: William Zhang --- Changes in v2: None arch/arm/Kconfig | 2 ++ arch/arm/mach-bcmbca/Kconfig | 11 +++ drivers/spi/Kconfig | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0118e225419..4aa91282f649 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -650,6 +650,8 @@ config ARCH_BCMSTB config ARCH_BCMBCA bool "Broadcom broadband chip family" select DM + select DM_SPI + select SPI select OF_CONTROL imply CMD_DM diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 62b371612b6a..6441ed5929d2 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -11,6 +11,7 @@ config BCM47622 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM4908 bool "Support for Broadcom 4908 Family" @@ -18,6 +19,7 @@ config BCM4908 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM4912 bool "Support for Broadcom 4912 Family" @@ -33,6 +35,7 @@ config BCM63138 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63146 bool "Support for Broadcom 63146 Family" @@ -40,6 +43,7 @@ config BCM63146 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63148 bool "Support for Broadcom 63148 Family" @@ -47,6 +51,7 @@ config BCM63148 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63158 bool "Support for Broadcom 63158 Family" @@ -54,6 +59,7 @@ config BCM63158 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63178 bool "Support for Broadcom 63178 Family" @@ -61,6 +67,7 @@ config BCM63178 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM6756 bool "Support for Broadcom 6756 Family" @@ -82,6 +89,7 @@ config BCM6846 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM6855 bool "Support for Broadcom 6855 Family" @@ -99,6 +107,7 @@ config BCM6856 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. @@ -109,6 +118,7 @@ config BCM6858 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. @@ -119,6 +129,7 @@ config BCM6878 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4f435fd26819..47a261f1e1b8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -101,9 +101,9 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158) + depends on (ARCH_BMIPS || ARCH_BCMBCA) help - Enable the BCM6328 HSSPI driver. This driver can be used to + Enable the BCM63XX HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom SPI core. -- 2.37.3
[PATCH v2 1/9] dt-bindings: spi: Add bcm63xx-hsspi controller support
Bring the device tree binding document from Linux to u-boot
Port from linux patches:
Link:
https://lore.kernel.org/r/20230207065826.285013-2-william.zh...@broadcom.com
Link:
https://lore.kernel.org/r/20230207065826.285013-3-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
.../spi/brcm,bcm63xx-hsspi.yaml | 134 ++
1 file changed, 134 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
diff --git a/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
new file mode 100644
index ..6554978583f8
--- /dev/null
+++ b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC High Speed SPI controller
+
+maintainers:
+ - William Zhang
+ - Kursad Oney
+ - Jonas Gorski
+
+description: |
+ Broadcom Broadband SoC supports High Speed SPI master controller since the
+ early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
+ controller was carried over to recent ARM based chips, such as BCM63138,
+ BCM4908 and BCM6858. The old MIPS based chip should continue to use the
+ brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required
to
+ use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
+ defined below to match the specific chip along with ip revision info.
+
+ This rev 1.0 controller has a limitation that can not keep the chip select
line
+ active between the SPI transfers within the same SPI message. This can
+ terminate the transaction to some SPI devices prematurely. The issue can be
+ worked around by either the controller's prepend mode or using the dummy chip
+ select workaround. Driver automatically picks the suitable mode based on
+ transfer type so it is transparent to the user.
+
+ The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI
+ controller rev 1.1 that add the capability to allow the driver to control
chip
+ select explicitly. This solves the issue in the old controller.
+
+properties:
+ compatible:
+oneOf:
+ - const: brcm,bcm6328-hsspi
+ - items:
+ - enum:
+ - brcm,bcm47622-hsspi
+ - brcm,bcm4908-hsspi
+ - brcm,bcm63138-hsspi
+ - brcm,bcm63146-hsspi
+ - brcm,bcm63148-hsspi
+ - brcm,bcm63158-hsspi
+ - brcm,bcm63178-hsspi
+ - brcm,bcm6846-hsspi
+ - brcm,bcm6856-hsspi
+ - brcm,bcm6858-hsspi
+ - brcm,bcm6878-hsspi
+ - const: brcm,bcmbca-hsspi-v1.0
+ - items:
+ - enum:
+ - brcm,bcm4912-hsspi
+ - brcm,bcm6756-hsspi
+ - brcm,bcm6813-hsspi
+ - brcm,bcm6855-hsspi
+ - const: brcm,bcmbca-hsspi-v1.1
+
+ reg:
+items:
+ - description: main registers
+ - description: miscellaneous control registers
+minItems: 1
+
+ reg-names:
+items:
+ - const: hsspi
+ - const: spim-ctrl
+minItems: 1
+
+ clocks:
+items:
+ - description: SPI master reference clock
+ - description: SPI master pll clock
+
+ clock-names:
+items:
+ - const: hsspi
+ - const: pll
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - brcm,bcm6328-hsspi
+ - brcm,bcmbca-hsspi-v1.0
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+else:
+ properties:
+reg:
+ minItems: 2
+ maxItems: 2
+reg-names:
+ minItems: 2
+ maxItems: 2
+ required:
+- reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+spi@ff801000 {
+compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
+reg = <0xff801000 0x1000>,
+ <0xff802610 0x4>;
+reg-names = "hsspi", "spim-ctrl";
+interrupts = ;
+clocks = <&hsspi>, <&hsspi_pll>;
+clock-names = "hsspi", "pll";
+num-cs = <8>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
--
2.37.3
[PATCH v2 3/9] arm64: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv8 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-5-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
arch/arm/dts/bcm4908.dtsi | 17 +
arch/arm/dts/bcm4912.dtsi | 20
arch/arm/dts/bcm63146.dtsi | 19 +++
arch/arm/dts/bcm63158.dtsi | 15 ++-
arch/arm/dts/bcm6813.dtsi | 20
arch/arm/dts/bcm6856.dtsi | 23 ++-
arch/arm/dts/bcm6858.dtsi | 23 ++-
arch/arm/dts/bcm94908.dts | 4
arch/arm/dts/bcm94912.dts | 4
arch/arm/dts/bcm963146.dts | 4
arch/arm/dts/bcm963158.dts | 4
arch/arm/dts/bcm96813.dts | 4
arch/arm/dts/bcm96856.dts | 4
arch/arm/dts/bcm96858.dts | 4
14 files changed, 130 insertions(+), 35 deletions(-)
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
index 0be5cfeeffa9..fc9874623b18 100644
--- a/arch/arm/dts/bcm4908.dtsi
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -106,6 +106,12 @@
clock-frequency = <5000>;
clock-output-names = "periph";
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
bus@ff80 {
@@ -123,5 +129,16 @@
status = "disabled";
};
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4908-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi
index 3d016c2ce675..b10a0ae06187 100644
--- a/arch/arm/dts/bcm4912.dtsi
+++ b/arch/arm/dts/bcm4912.dtsi
@@ -78,6 +78,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -85,6 +86,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -116,6 +123,19 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4912-hsspi",
"brcm,bcmbca-hsspi-v1.1";
+ reg = <0x1000 0x600>, <0x2610 0x4>;
+ reg-names = "hsspi", "spim-ctrl";
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi
index 04de96bd0a03..48226cf1a7d4 100644
--- a/arch/arm/dts/bcm63146.dtsi
+++ b/arch/arm/dts/bcm63146.dtsi
@@ -59,6 +59,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -66,6 +67,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
[PATCH v2 2/9] ARM: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv7 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-4-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
arch/arm/dts/bcm47622.dtsi | 18 ++
arch/arm/dts/bcm63138.dtsi | 18 ++
arch/arm/dts/bcm63148.dtsi | 18 ++
arch/arm/dts/bcm63178.dtsi | 19 +++
arch/arm/dts/bcm6756.dtsi | 19 +++
arch/arm/dts/bcm6846.dtsi | 18 ++
arch/arm/dts/bcm6855.dtsi | 27 +++
arch/arm/dts/bcm6878.dtsi | 19 +++
arch/arm/dts/bcm947622.dts | 4
arch/arm/dts/bcm963138.dts | 4
arch/arm/dts/bcm963148.dts | 4
arch/arm/dts/bcm963178.dts | 4
arch/arm/dts/bcm96756.dts | 4
arch/arm/dts/bcm96846.dts | 4
arch/arm/dts/bcm96855.dts | 4
arch/arm/dts/bcm96878.dts | 4
16 files changed, 180 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi
index c016e12b7372..86b1dff65aca 100644
--- a/arch/arm/dts/bcm47622.dtsi
+++ b/arch/arm/dts/bcm47622.dtsi
@@ -83,6 +83,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -114,6 +120,18 @@
#size-cells = <1>;
ranges = <0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm47622-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
index 42b442aec9f4..2a673c39ba68 100644
--- a/arch/arm/dts/bcm63138.dtsi
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -60,6 +60,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
/* ARM bus */
@@ -145,5 +151,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi
index df5307b6b3af..d9aed2bd7ff0 100644
--- a/arch/arm/dts/bcm63148.dtsi
+++ b/arch/arm/dts/bcm63148.dtsi
@@ -59,6 +59,12 @@
#clock-cells = <0>;
clock-frequency = <5000>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
psci {
@@ -99,5 +105,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63148-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock
[PATCH 0/9] spi: bcm63xx-hsspi: driver and doc updates
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers MAINTAINERS | 8 + arch/arm/Kconfig | 2 + arch/arm/dts/bcm47622.dtsi| 18 + arch/arm/dts/bcm4908.dtsi | 17 + arch/arm/dts/bcm4912.dtsi | 20 + arch/arm/dts/bcm63138.dtsi| 18 + arch/arm/dts/bcm63146.dtsi| 19 + arch/arm/dts/bcm63148.dtsi| 18 + arch/arm/dts/bcm63158.dtsi| 15 +- arch/arm/dts/bcm63178.dtsi| 19 + arch/arm/dts/bcm6756.dtsi | 19 + arch/arm/dts/bcm6813.dtsi | 20 + arch/arm/dts/bcm6846.dtsi | 18 + arch/arm/dts/bcm6855.dtsi | 27 +- arch/arm/dts/bcm6856.dtsi | 23 +- arch/arm/dts/bcm6858.dtsi | 23 +- arch/arm/dts/bcm6878.dtsi | 19 + arch/arm/dts/bcm947622.dts| 4 + arch/arm/dts/bcm94908.dts | 4 + arch/arm/dts/bcm94912.dts | 4 + arch/arm/dts/bcm963138.dts| 4 + arch/arm/dts/bcm963146.dts| 4 + arch/arm/dts/bcm963148.dts| 4 + arch/arm/dts/bcm963158.dts| 4 + arch/arm/dts/bcm963178.dts| 4 + arch/arm/dts/bcm96756.dts | 4 + arch/arm/dts/bcm96813.dts | 4 + arch/arm/dts/bcm96846.dts | 4 + arch/arm/dts/bcm96855.dts | 4 + arch/arm/dts/bcm96856.dts | 4 + arch/arm/dts/bcm96858.dts | 4 + arch/arm/dts/bcm96878.dts | 4 + arch/arm/mach-bcmbca/Kconfig | 26 ++ .../spi/brcm,bcm63xx-hsspi.yaml | 134 ++ drivers/spi/Kconfig | 13 +- drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 277 +++- drivers/spi/bcmbca_hsspi.c| 414 ++ 38 files changed, 1159 insertions(+), 69 deletions(-) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml create mode 100644 drivers/spi/bcmbca_hsspi.c -- 2.37.3
[PATCH 6/9] spi: bcm63xx-hsspi: Fix multi-bit mode setting
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-11-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
drivers/spi/bcm63xx_hsspi.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 495feba02262..0d12c345b1dd 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -221,7 +221,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned
int bitlen,
size_t data_bytes = bitlen / 8;
size_t step_size = HSSPI_FIFO_SIZE;
uint16_t opcode = 0;
- uint32_t val;
+ uint32_t val = SPI_PFL_MODE_FILL_MASK;
const uint8_t *tx = dout;
uint8_t *rx = din;
@@ -240,14 +240,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev,
unsigned int bitlen,
step_size -= HSSPI_FIFO_OP_SIZE;
/* dual mode */
- if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
- (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
+ if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+ (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
opcode |= HSSPI_FIFO_OP_MBIT_MASK;
- /* profile mode */
- val = SPI_PFL_MODE_FILL_MASK |
- SPI_PFL_MODE_MDRDSZ_MASK |
- SPI_PFL_MODE_MDWRSZ_MASK;
+ /* profile mode */
+ if (plat->mode & SPI_RX_DUAL)
+ val |= SPI_PFL_MODE_MDRDSZ_MASK;
+ if (plat->mode & SPI_TX_DUAL)
+ val |= SPI_PFL_MODE_MDWRSZ_MASK;
+ }
+
if (plat->mode & SPI_3WIRE)
val |= SPI_PFL_MODE_3WIRE_MASK;
writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
--
2.37.3
[PATCH 2/9] ARM: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv7 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-4-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
arch/arm/dts/bcm47622.dtsi | 18 ++
arch/arm/dts/bcm63138.dtsi | 18 ++
arch/arm/dts/bcm63148.dtsi | 18 ++
arch/arm/dts/bcm63178.dtsi | 19 +++
arch/arm/dts/bcm6756.dtsi | 19 +++
arch/arm/dts/bcm6846.dtsi | 18 ++
arch/arm/dts/bcm6855.dtsi | 27 +++
arch/arm/dts/bcm6878.dtsi | 19 +++
arch/arm/dts/bcm947622.dts | 4
arch/arm/dts/bcm963138.dts | 4
arch/arm/dts/bcm963148.dts | 4
arch/arm/dts/bcm963178.dts | 4
arch/arm/dts/bcm96756.dts | 4
arch/arm/dts/bcm96846.dts | 4
arch/arm/dts/bcm96855.dts | 4
arch/arm/dts/bcm96878.dts | 4
16 files changed, 180 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi
index c016e12b7372..86b1dff65aca 100644
--- a/arch/arm/dts/bcm47622.dtsi
+++ b/arch/arm/dts/bcm47622.dtsi
@@ -83,6 +83,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -114,6 +120,18 @@
#size-cells = <1>;
ranges = <0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm47622-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
index 42b442aec9f4..2a673c39ba68 100644
--- a/arch/arm/dts/bcm63138.dtsi
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -60,6 +60,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
/* ARM bus */
@@ -145,5 +151,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi
index df5307b6b3af..d9aed2bd7ff0 100644
--- a/arch/arm/dts/bcm63148.dtsi
+++ b/arch/arm/dts/bcm63148.dtsi
@@ -59,6 +59,12 @@
#clock-cells = <0>;
clock-frequency = <5000>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
psci {
@@ -99,5 +105,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63148-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi&qu
[PATCH 9/9] MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers
Add entry for Broadcom Broadband SoC HS SPI drivers Signed-off-by: William Zhang --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4c17c6cb9f1e..cfec29ee5c07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -823,6 +823,14 @@ F: include/bootstd.h F: net/eth_bootdevice.c F: test/boot/ +BROADCOM Broadband SoC High Speed SPI Controller DRIVER +M: William Zhang +M: Kursad Oney +S: Maintained +F: doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml +F: drivers/spi/bcm63xx_hsspi.c +F: drivers/spi/bcmbca_hsspi.c + BTRFS M: Marek Behún R: Qu Wenruo -- 2.37.3
[PATCH 3/9] arm64: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv8 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-5-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
arch/arm/dts/bcm4908.dtsi | 17 +
arch/arm/dts/bcm4912.dtsi | 20
arch/arm/dts/bcm63146.dtsi | 19 +++
arch/arm/dts/bcm63158.dtsi | 15 ++-
arch/arm/dts/bcm6813.dtsi | 20
arch/arm/dts/bcm6856.dtsi | 23 ++-
arch/arm/dts/bcm6858.dtsi | 23 ++-
arch/arm/dts/bcm94908.dts | 4
arch/arm/dts/bcm94912.dts | 4
arch/arm/dts/bcm963146.dts | 4
arch/arm/dts/bcm963158.dts | 4
arch/arm/dts/bcm96813.dts | 4
arch/arm/dts/bcm96856.dts | 4
arch/arm/dts/bcm96858.dts | 4
14 files changed, 130 insertions(+), 35 deletions(-)
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
index 0be5cfeeffa9..fc9874623b18 100644
--- a/arch/arm/dts/bcm4908.dtsi
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -106,6 +106,12 @@
clock-frequency = <5000>;
clock-output-names = "periph";
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
bus@ff80 {
@@ -123,5 +129,16 @@
status = "disabled";
};
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4908-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi
index 3d016c2ce675..b10a0ae06187 100644
--- a/arch/arm/dts/bcm4912.dtsi
+++ b/arch/arm/dts/bcm4912.dtsi
@@ -78,6 +78,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -85,6 +86,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -116,6 +123,19 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4912-hsspi",
"brcm,bcmbca-hsspi-v1.1";
+ reg = <0x1000 0x600>, <0x2610 0x4>;
+ reg-names = "hsspi", "spim-ctrl";
+ interrupts = ;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi
index 04de96bd0a03..48226cf1a7d4 100644
--- a/arch/arm/dts/bcm63146.dtsi
+++ b/arch/arm/dts/bcm63146.dtsi
@@ -59,6 +59,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -66,6 +67,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -98,6 +105,18 @@
#siz
[PATCH 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zh...@broadcom.com Signed-off-by: William Zhang --- arch/arm/mach-bcmbca/Kconfig | 15 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM63138 bool "Support for Broadcom 63138 Family" @@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6813 bool "Support for Broadcom 6813 Family" @@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6846 bool "Support for Broadcom 6846 Family" @@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI help Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. @@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI +config HAVE_SPI_CS_CTRL + bool "SoC supports SPI chip select control" + default y if BCM4912 + default y if BCM6756 + default y if BCM6855 + default y if BCM6813 + default n + help + Enable this option if SoC supports SPI chip select control explicitly + through software. + source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core. +config BCMBCA_HSSPI + bool "BCMBCA HSSPI driver" + depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index ..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski + * Copyright (C) 2021 Broadcom Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 3000 + +/* SPI Control register */ +#define SPI_CTL_REG0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG0x008 +#defi
[PATCH 7/9] spi: bcm63xx-hsspi: Add prepend mode support
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-12-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
drivers/spi/bcm63xx_hsspi.c | 259 +---
1 file changed, 242 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 0d12c345b1dd..a24bb430cbb4 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -20,7 +20,13 @@
#define HSSPI_PP 0
-#define SPI_MAX_SYNC_CLOCK 3000
+/*
+ * The maximum frequency for SPI synchronous mode is 30MHz for some chips and
+ * 25MHz for some others. This depends on the chip layout and SPI signals
+ * distance to the pad. We use the lower of these values to cover all relevant
+ * chips.
+ */
+#define SPI_MAX_SYNC_CLOCK 2500
/* SPI Control register */
#define SPI_CTL_REG0x000
@@ -72,12 +78,16 @@
#define SPI_PFL_MODE_REG(x)(0x100 + (0x20 * (x)) + 0x08)
#define SPI_PFL_MODE_FILL_SHIFT0
#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDST_SHIFT 8
+#define SPI_PFL_MODE_MDWRST_SHIFT 12
#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
#define SPI_PFL_MODE_3WIRE_SHIFT 20
#define SPI_PFL_MODE_3WIRE_MASK(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+#define SPI_PFL_MODE_PREPCNT_SHIFT 24
+#define SPI_PFL_MODE_PREPCNT_MASK (4 << SPI_PFL_MODE_PREPCNT_SHIFT)
/* SPI Ping-Pong FIFO registers */
#define HSSPI_FIFO_SIZE0x200
@@ -96,12 +106,21 @@
#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_MAX_DATA_SIZE(HSSPI_FIFO_SIZE -
HSSPI_FIFO_OP_SIZE)
+#define HSSPI_MAX_PREPEND_SIZE 15
+
+#define HSSPI_XFER_MODE_PREPEND0
+#define HSSPI_XFER_MODE_DUMMYCS1
+
struct bcm63xx_hsspi_priv {
void __iomem *regs;
ulong clk_rate;
uint8_t num_cs;
uint8_t cs_pols;
uint speed;
+ uint xfer_mode;
+ uint32_t prepend_cnt;
+ uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE];
};
static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
@@ -143,9 +162,16 @@ static void bcm63xx_hsspi_activate_cs(struct
bcm63xx_hsspi_priv *priv,
struct dm_spi_slave_plat *plat)
{
uint32_t clr, set;
+ uint speed = priv->speed;
+
+ if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS &&
+ speed > SPI_MAX_SYNC_CLOCK) {
+ speed = SPI_MAX_SYNC_CLOCK;
+ debug("Force to dummy cs mode. Reduce the speed to %dHz\n",
speed);
+ }
/* pr
[PATCH 5/9] spi: bcm63xx-hsspi: Add new compatible string support
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-6-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
drivers/spi/bcm63xx_hsspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4d714adc4afd..495feba02262 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -310,6 +310,7 @@ static const struct dm_spi_ops bcm63xx_hsspi_ops = {
static const struct udevice_id bcm63xx_hsspi_ids[] = {
{ .compatible = "brcm,bcm6328-hsspi", },
+ { .compatible = "brcm,bcmbca-hsspi-v1.0", },
{ /* sentinel */ }
};
--
2.37.3
[PATCH 4/9] spi: bcm63xx-hsspi: Enable SPI drivers by default
SPI controller is always presented in BCMBCA platform SoCs so enable the controller driver and SPI core by default. Signed-off-by: William Zhang --- arch/arm/Kconfig | 2 ++ arch/arm/mach-bcmbca/Kconfig | 11 +++ drivers/spi/Kconfig | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0118e225419..4aa91282f649 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -650,6 +650,8 @@ config ARCH_BCMSTB config ARCH_BCMBCA bool "Broadcom broadband chip family" select DM + select DM_SPI + select SPI select OF_CONTROL imply CMD_DM diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 62b371612b6a..6441ed5929d2 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -11,6 +11,7 @@ config BCM47622 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM4908 bool "Support for Broadcom 4908 Family" @@ -18,6 +19,7 @@ config BCM4908 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM4912 bool "Support for Broadcom 4912 Family" @@ -33,6 +35,7 @@ config BCM63138 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63146 bool "Support for Broadcom 63146 Family" @@ -40,6 +43,7 @@ config BCM63146 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63148 bool "Support for Broadcom 63148 Family" @@ -47,6 +51,7 @@ config BCM63148 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63158 bool "Support for Broadcom 63158 Family" @@ -54,6 +59,7 @@ config BCM63158 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63178 bool "Support for Broadcom 63178 Family" @@ -61,6 +67,7 @@ config BCM63178 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM6756 bool "Support for Broadcom 6756 Family" @@ -82,6 +89,7 @@ config BCM6846 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM6855 bool "Support for Broadcom 6855 Family" @@ -99,6 +107,7 @@ config BCM6856 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. @@ -109,6 +118,7 @@ config BCM6858 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. @@ -119,6 +129,7 @@ config BCM6878 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4f435fd26819..47a261f1e1b8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -101,9 +101,9 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158) + depends on (ARCH_BMIPS || ARCH_BCMBCA) help - Enable the BCM6328 HSSPI driver. This driver can be used to + Enable the BCM63XX HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom SPI core. -- 2.37.3
[PATCH 1/9] dt-bindings: spi: Add bcm63xx-hsspi controller support
Bring the device tree binding document from Linux to u-boot
Port from linux patches:
Link:
https://lore.kernel.org/r/20230207065826.285013-2-william.zh...@broadcom.com
Link:
https://lore.kernel.org/r/20230207065826.285013-3-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
.../spi/brcm,bcm63xx-hsspi.yaml | 134 ++
1 file changed, 134 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
diff --git a/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
new file mode 100644
index ..6554978583f8
--- /dev/null
+++ b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC High Speed SPI controller
+
+maintainers:
+ - William Zhang
+ - Kursad Oney
+ - Jonas Gorski
+
+description: |
+ Broadcom Broadband SoC supports High Speed SPI master controller since the
+ early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
+ controller was carried over to recent ARM based chips, such as BCM63138,
+ BCM4908 and BCM6858. The old MIPS based chip should continue to use the
+ brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required
to
+ use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
+ defined below to match the specific chip along with ip revision info.
+
+ This rev 1.0 controller has a limitation that can not keep the chip select
line
+ active between the SPI transfers within the same SPI message. This can
+ terminate the transaction to some SPI devices prematurely. The issue can be
+ worked around by either the controller's prepend mode or using the dummy chip
+ select workaround. Driver automatically picks the suitable mode based on
+ transfer type so it is transparent to the user.
+
+ The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI
+ controller rev 1.1 that add the capability to allow the driver to control
chip
+ select explicitly. This solves the issue in the old controller.
+
+properties:
+ compatible:
+oneOf:
+ - const: brcm,bcm6328-hsspi
+ - items:
+ - enum:
+ - brcm,bcm47622-hsspi
+ - brcm,bcm4908-hsspi
+ - brcm,bcm63138-hsspi
+ - brcm,bcm63146-hsspi
+ - brcm,bcm63148-hsspi
+ - brcm,bcm63158-hsspi
+ - brcm,bcm63178-hsspi
+ - brcm,bcm6846-hsspi
+ - brcm,bcm6856-hsspi
+ - brcm,bcm6858-hsspi
+ - brcm,bcm6878-hsspi
+ - const: brcm,bcmbca-hsspi-v1.0
+ - items:
+ - enum:
+ - brcm,bcm4912-hsspi
+ - brcm,bcm6756-hsspi
+ - brcm,bcm6813-hsspi
+ - brcm,bcm6855-hsspi
+ - const: brcm,bcmbca-hsspi-v1.1
+
+ reg:
+items:
+ - description: main registers
+ - description: miscellaneous control registers
+minItems: 1
+
+ reg-names:
+items:
+ - const: hsspi
+ - const: spim-ctrl
+minItems: 1
+
+ clocks:
+items:
+ - description: SPI master reference clock
+ - description: SPI master pll clock
+
+ clock-names:
+items:
+ - const: hsspi
+ - const: pll
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - brcm,bcm6328-hsspi
+ - brcm,bcmbca-hsspi-v1.0
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+else:
+ properties:
+reg:
+ minItems: 2
+ maxItems: 2
+reg-names:
+ minItems: 2
+ maxItems: 2
+ required:
+- reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+spi@ff801000 {
+compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
+reg = <0xff801000 0x1000>,
+ <0xff802610 0x4>;
+reg-names = "hsspi", "spim-ctrl";
+interrupts = ;
+clocks = <&hsspi>, <&hsspi_pll>;
+clock-names = "hsspi", "pll";
+num-cs = <8>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
--
2.37.3
Re: [PATCH v2] nand: brcmnand: add iproc support
;
+ struct brcmnand_soc *soc;
+ struct resource res;
+ int ret;
+
+ soc = &priv->soc;
+
+ ret = dev_read_resource_byname(pdev, "iproc-idm", &res);
+ if (ret)
+ return ret;
+
+ priv->idm_base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(priv->idm_base))
+ return PTR_ERR(priv->idm_base);
+
+ ret = dev_read_resource_byname(pdev, "iproc-ext", &res);
+ if (ret)
+ return ret;
+
+ priv->ext_base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(priv->ext_base))
+ return PTR_ERR(priv->ext_base);
+
+ soc->ctlrdy_ack = iproc_nand_intc_ack;
+ soc->ctlrdy_set_enabled = iproc_nand_intc_set;
+ soc->prepare_data_bus = iproc_nand_apb_access;
+
+ return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id iproc_nand_dt_ids[] = {
+ {
+ .compatible = "brcm,nand-iproc",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(iproc_nand) = {
+ .name = "iproc-nand",
+ .id = UCLASS_MTD,
+ .of_match = iproc_nand_dt_ids,
+ .probe = iproc_nand_probe,
+ .priv_auto = sizeof(struct iproc_nand_soc),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(iproc_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2] mtd: rawnand: nand_base: Handle algorithm selection
On 03/08/2023 01:28 PM, Linus Walleij wrote:
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Drop pointless check for ecc_algo >= 0, it is always
>= 0.
---
drivers/mtd/nand/raw/nand_base.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 9eba360d55f3..c173fd09237a 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode
node)
{
int ret, ecc_mode = -1, ecc_strength, ecc_step;
+ int ecc_algo = NAND_ECC_UNKNOWN;
const char *str;
ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
@@ -4512,10 +4513,13 @@ static int nand_dt_init(struct mtd_info *mtd, struct
nand_chip *chip, ofnode nod
ecc_mode = NAND_ECC_SOFT_BCH;
}
- if (ecc_mode == NAND_ECC_SOFT) {
- str = ofnode_read_string(node, "nand-ecc-algo");
- if (str && !strcmp(str, "bch"))
+ str = ofnode_read_string(node, "nand-ecc-algo");
+ if (str && !strcmp(str, "bch")) {
+ ecc_algo = NAND_ECC_BCH;
+ if (ecc_mode == NAND_ECC_SOFT)
ecc_mode = NAND_ECC_SOFT_BCH;
+ } else if (!strcmp(str, "hamming")) {
+ ecc_algo = NAND_ECC_HAMMING;
}
ecc_strength = ofnode_read_s32_default(node,
@@ -4529,6 +4533,8 @@ static int nand_dt_init(struct mtd_info *mtd, struct
nand_chip *chip, ofnode nod
return -EINVAL;
}
+ chip->ecc.algo = ecc_algo;
+
if (ecc_mode >= 0)
chip->ecc.mode = ecc_mode;
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 00/10] Backport BRCMNAND changes from Linux
Hi Linus. On 02/11/2023 07:28 AM, Linus Walleij wrote: Hunting down a bug on my system I took to back-porting all reasonable changes from the Linux brcmnand driver that were not yet in the U-Boot derivative. I noticed that a simple diff -ur between brcmnand.c between the file in Linux and U-Boot was possible to see what differs. Combining this with some git log --oneline manual comparison, fuzzing and manual intervention I backported a set of relevant patches from Linux that compiles and WorksForMe(TM). The diff between Linux and U-Boot is much smaller after this, the main missing part are subsystem cosmetics changes and the EDU DMA mode support. This was as much as I could bite off in one go. All patches countersigned-off and marked as [backported]. ChangeLog v1->v2: - Drop the patch to use the new OOB data layout helpers "mtd: nand: brcm: switch to mtd_ooblayout_ops" - Drop all patches depending on the previous patch, in total 4 patches. Claire Lin (1): mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips Kamal Dasu (3): mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: nand: brcmnand: Add support for flash-dma v0 Álvaro Fernández Rojas (6): mtd: rawnand: brcmnand: correctly verify erased pages mtd: rawnand: brcmnand: rename v4 registers mtd: rawnand: brcmnand: fix CS0 layout mtd: rawnand: brcmnand: rename page sizes mtd: rawnand: brcmnand: support v2.1-v2.2 controllers mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECC drivers/mtd/nand/raw/brcmnand/brcmnand.c | 353 +-- 1 file changed, 268 insertions(+), 85 deletions(-) Sorry for the delay. Finally I got some time to try your patches on a BCM63158 based board with NAND controller 7.1. It works fine. smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH v2 10/10] mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECC
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Álvaro Fernández Rojas
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall
always be done without ECC enabled.
This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2
clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed
from ff ff ff to 00 00 00, reporting incorrect ECC errors.
Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND
controller")
Signed-off-by: Álvaro Fernández Rojas
Acked-by: Brian Norris
Signed-off-by: Miquel Raynal
Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index b2ebcaf7a5bf..efbf9a3120a4 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -2515,6 +2515,12 @@ static int brcmnand_init_cs(struct brcmnand_host *host,
ofnode dn)
ret = nand_register(0, mtd);
#endif /* __UBOOT__ */
+ /* If OOB is written with ECC enabled it will cause ECC errors */
+ if (is_hamming_ecc(host->ctrl, &host->hwcfg)) {
+ chip->ecc.write_oob = brcmnand_write_oob_raw;
+ chip->ecc.read_oob = brcmnand_read_oob_raw;
+ }
+
return ret;
}
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 09/10] mtd: rawnand: brcmnand: support v2.1-v2.2 controllers
0202)
+ ctrl->page_sizes = page_sizes_v2_2;
+ else
+ ctrl->page_sizes = page_sizes_v2_1;
+
+ if (ctrl->nand_version >= 0x0202)
+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
+ else
+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
+
if (ctrl->nand_version >= 0x0600)
ctrl->block_sizes = block_sizes_v6;
- else
+ else if (ctrl->nand_version >= 0x0400)
ctrl->block_sizes = block_sizes_v4;
+ else if (ctrl->nand_version >= 0x0202)
+ ctrl->block_sizes = block_sizes_v2_2;
+ else
+ ctrl->block_sizes = block_sizes_v2_1;
if (ctrl->nand_version < 0x0400) {
- ctrl->max_page_size = 4096;
+ if (ctrl->nand_version < 0x0202)
+ ctrl->max_page_size = 2048;
+ else
+ ctrl->max_page_size = 4096;
ctrl->max_block_size = 512 * 1024;
}
}
@@ -756,6 +814,9 @@ static void brcmnand_wr_corr_thresh(struct brcmnand_host
*host, u8 val)
enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
int cs = host->cs;
+ if (!ctrl->reg_offsets[reg])
+ return;
+
if (ctrl->nand_version == 0x0702)
bits = 7;
else if (ctrl->nand_version >= 0x0600)
@@ -814,8 +875,10 @@ static inline u32 brcmnand_spare_area_mask(struct
brcmnand_controller *ctrl)
return GENMASK(7, 0);
else if (ctrl->nand_version >= 0x0600)
return GENMASK(6, 0);
- else
+ else if (ctrl->nand_version >= 0x0303)
return GENMASK(5, 0);
+ else
+ return GENMASK(4, 0);
}
#define NAND_ACC_CONTROL_ECC_SHIFT 16
@@ -2149,7 +2212,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *host,
(!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
(device_size << CFG_DEVICE_SIZE_SHIFT);
if (cfg_offs == cfg_ext_offs) {
- tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
+ tmp |= (page_size << ctrl->page_size_shift) |
(block_size << CFG_BLK_SIZE_SHIFT);
nand_writereg(ctrl, cfg_offs, tmp);
} else {
@@ -2161,9 +2224,11 @@ static int brcmnand_set_cfg(struct brcmnand_host *host,
tmp = nand_readreg(ctrl, acc_control_offs);
tmp &= ~brcmnand_ecc_level_mask(ctrl);
- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
tmp &= ~brcmnand_spare_area_mask(ctrl);
- tmp |= cfg->spare_area_size;
+ if (ctrl->nand_version >= 0x0302) {
+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
+ tmp |= cfg->spare_area_size;
+ }
nand_writereg(ctrl, acc_control_offs, tmp);
brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
@@ -2543,6 +2608,8 @@ const struct dev_pm_ops brcmnand_pm_ops = {
EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
static const struct of_device_id brcmnand_of_match[] = {
+ { .compatible = "brcm,brcmnand-v2.1" },
+ { .compatible = "brcm,brcmnand-v2.2" },
{ .compatible = "brcm,brcmnand-v4.0" },
{ .compatible = "brcm,brcmnand-v5.0" },
{ .compatible = "brcm,brcmnand-v6.0" },
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 08/10] mtd: rawnand: brcmnand: rename page sizes
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Álvaro Fernández Rojas
Current pages sizes apply to controllers after v3.4
Signed-off-by: Álvaro Fernández Rojas
Acked-by: Florian Fainelli
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 1ea9091e6497..10a2e2c0f599 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -526,7 +526,7 @@ static int brcmnand_revision_init(struct
brcmnand_controller *ctrl)
{
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512,
1024, 2048, 0 };
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256,
1024, 2048, 0 };
- static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
+ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192,
0 };
ctrl->nand_version = nand_readreg(ctrl, 0) & 0x;
@@ -573,7 +573,7 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
ctrl->max_page_size = 16 * 1024;
ctrl->max_block_size = 2 * 1024 * 1024;
} else {
- ctrl->page_sizes = page_sizes;
+ ctrl->page_sizes = page_sizes_v3_4;
if (ctrl->nand_version >= 0x0600)
ctrl->block_sizes = block_sizes_v6;
else
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 07/10] mtd: rawnand: brcmnand: fix CS0 layout
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Álvaro Fernández Rojas
Only v3.3-v5.0 have a different CS0 layout.
Controllers before v3.3 use the same layout for every CS.
Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND
controller")
Signed-off-by: Álvaro Fernández Rojas
Acked-by: Florian Fainelli
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index ee7c3a21602e..1ea9091e6497 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -561,8 +561,9 @@ static int brcmnand_revision_init(struct
brcmnand_controller *ctrl)
} else {
ctrl->cs_offsets = brcmnand_cs_offsets;
- /* v5.0 and earlier has a different CS0 offset layout */
- if (ctrl->nand_version <= 0x0500)
+ /* v3.3-5.0 have a different CS0 offset layout */
+ if (ctrl->nand_version >= 0x0303 &&
+ ctrl->nand_version <= 0x0500)
ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
}
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 06/10] mtd: rawnand: brcmnand: rename v4 registers
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Álvaro Fernández Rojas
These registers are also used on v3.3.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Miquel Raynal
Acked-by: Florian Fainelli
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 5d3fb460d89a..ee7c3a21602e 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -293,8 +293,8 @@ enum brcmnand_reg {
BRCMNAND_FC_BASE,
};
-/* BRCMNAND v4.0 */
-static const u16 brcmnand_regs_v40[] = {
+/* BRCMNAND v3.3-v4.0 */
+static const u16 brcmnand_regs_v33[] = {
[BRCMNAND_CMD_START]= 0x04,
[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
[BRCMNAND_CMD_ADDRESS] = 0x0c,
@@ -546,8 +546,8 @@ static int brcmnand_revision_init(struct
brcmnand_controller *ctrl)
ctrl->reg_offsets = brcmnand_regs_v60;
else if (ctrl->nand_version >= 0x0500)
ctrl->reg_offsets = brcmnand_regs_v50;
- else if (ctrl->nand_version >= 0x0400)
- ctrl->reg_offsets = brcmnand_regs_v40;
+ else if (ctrl->nand_version >= 0x0303)
+ ctrl->reg_offsets = brcmnand_regs_v33;
/* Chip-select stride */
if (ctrl->nand_version >= 0x0701)
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 05/10] mtd: rawnand: brcmnand: correctly verify erased pages
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Álvaro Fernández Rojas
The current code checks that the whole OOB area is erased.
This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will
fail due to the usable OOB bytes not being 0xff.
Correct this by only checking that data and ECC bytes aren't 0xff.
Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Álvaro Fernández Rojas
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200512082451.771212-1-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index a934373a2992..5d3fb460d89a 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -1777,11 +1777,12 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd,
struct nand_chip *chip,
static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
struct nand_chip *chip, void *buf, u64 addr)
{
- int i, sas;
- void *oob = chip->oob_poi;
+ struct mtd_oob_region ecc;
+ int i;
int bitflips = 0;
int page = addr >> chip->page_shift;
int ret;
+ void *ecc_bytes;
void *ecc_chunk;
if (!buf) {
@@ -1794,18 +1795,20 @@ static int brcmstb_nand_verify_erased_page(struct
mtd_info *mtd,
chip->pagebuf = -1;
}
- sas = mtd->oobsize / chip->ecc.steps;
-
/* read without ecc for verification */
ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
if (ret)
return ret;
- for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
+ for (i = 0; i < chip->ecc.steps; i++) {
ecc_chunk = buf + chip->ecc.size * i;
- ret = nand_check_erased_ecc_chunk(ecc_chunk,
- chip->ecc.size,
- oob, sas, NULL, 0,
+
+ mtd_ooblayout_ecc(mtd, i, &ecc);
+ ecc_bytes = chip->oob_poi + ecc.offset;
+
+ ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
+ ecc_bytes, ecc.length,
+ NULL, 0,
chip->ecc.strength);
if (ret < 0)
return ret;
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 04/10] mtd: nand: brcmnand: Add support for flash-dma v0
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Kamal Dasu
This change adds support for flash dma v0.0.
Signed-off-by: Kamal Dasu
Signed-off-by: Miquel Raynal
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 0402cb06a74b..a934373a2992 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -120,6 +120,18 @@ enum flash_dma_reg {
};
#ifndef __UBOOT__
+/* flash_dma registers v0*/
+static const u16 flash_dma_regs_v0[] = {
+ [FLASH_DMA_REVISION]= 0x00,
+ [FLASH_DMA_FIRST_DESC] = 0x04,
+ [FLASH_DMA_CTRL]= 0x08,
+ [FLASH_DMA_MODE]= 0x0c,
+ [FLASH_DMA_STATUS] = 0x10,
+ [FLASH_DMA_INTERRUPT_DESC] = 0x14,
+ [FLASH_DMA_ERROR_STATUS]= 0x18,
+ [FLASH_DMA_CURRENT_DESC]= 0x1c,
+};
+
/* flash_dma registers v1*/
static const u16 flash_dma_regs_v1[] = {
[FLASH_DMA_REVISION]= 0x00,
@@ -614,6 +626,8 @@ static void brcmnand_flash_dma_revision_init(struct
brcmnand_controller *ctrl)
/* flash_dma register offsets */
if (ctrl->nand_version >= 0x0703)
ctrl->flash_dma_offsets = flash_dma_regs_v4;
+ else if (ctrl->nand_version == 0x0602)
+ ctrl->flash_dma_offsets = flash_dma_regs_v0;
else
ctrl->flash_dma_offsets = flash_dma_regs_v1;
}
@@ -1645,8 +1659,11 @@ static void brcmnand_dma_run(struct brcmnand_host *host,
dma_addr_t desc)
flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
- flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
- (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
+ if (ctrl->nand_version > 0x0602) {
+ flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,
+upper_32_bits(desc));
+ (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
+ }
/* Start FLASH_DMA engine */
ctrl->dma_pending = true;
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 03/10] mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips
On 02/11/2023 07:29 AM, Linus Walleij wrote:
From: Claire Lin
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation
while correcting erased page bitflips is wrong, fix it.
Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Claire Lin
Reviewed-by: Ray Jui
Signed-off-by: Kamal Dasu
Signed-off-by: Miquel Raynal
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 170aece0aa79..0402cb06a74b 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -1765,6 +1765,7 @@ static int brcmstb_nand_verify_erased_page(struct
mtd_info *mtd,
int bitflips = 0;
int page = addr >> chip->page_shift;
int ret;
+ void *ecc_chunk;
if (!buf) {
#ifndef __UBOOT__
@@ -1784,7 +1785,9 @@ static int brcmstb_nand_verify_erased_page(struct
mtd_info *mtd,
return ret;
for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
- ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
+ ecc_chunk = buf + chip->ecc.size * i;
+ ret = nand_check_erased_ecc_chunk(ecc_chunk,
+ chip->ecc.size,
oob, sas, NULL, 0,
chip->ecc.strength);
if (ret < 0)
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 02/10] mtd: rawnand: brcmnand: Add support for v7.3 controller
reg reg)
{
@@ -675,7 +741,7 @@ static void brcmnand_wr_corr_thresh(struct brcmnand_host
*host, u8 val)
enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
int cs = host->cs;
- if (ctrl->nand_version >= 0x0702)
+ if (ctrl->nand_version == 0x0702)
bits = 7;
else if (ctrl->nand_version >= 0x0600)
bits = 6;
@@ -729,7 +795,7 @@ enum {
static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
{
- if (ctrl->nand_version >= 0x0702)
+ if (ctrl->nand_version == 0x0702)
return GENMASK(7, 0);
else if (ctrl->nand_version >= 0x0600)
return GENMASK(6, 0);
@@ -877,20 +943,6 @@ static inline void brcmnand_set_wp(struct
brcmnand_controller *ctrl, bool en)
* Flash DMA
***/
-enum flash_dma_reg {
- FLASH_DMA_REVISION = 0x00,
- FLASH_DMA_FIRST_DESC= 0x04,
- FLASH_DMA_FIRST_DESC_EXT= 0x08,
- FLASH_DMA_CTRL = 0x0c,
- FLASH_DMA_MODE = 0x10,
- FLASH_DMA_STATUS= 0x14,
- FLASH_DMA_INTERRUPT_DESC= 0x18,
- FLASH_DMA_INTERRUPT_DESC_EXT= 0x1c,
- FLASH_DMA_ERROR_STATUS = 0x20,
- FLASH_DMA_CURRENT_DESC = 0x24,
- FLASH_DMA_CURRENT_DESC_EXT = 0x28,
-};
-
static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
{
return ctrl->flash_dma_base;
@@ -906,14 +958,19 @@ static inline bool flash_dma_buf_ok(const void *buf)
#endif /* __UBOOT__ */
}
-static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
- u32 val)
+static inline void flash_dma_writel(struct brcmnand_controller *ctrl,
+ enum flash_dma_reg dma_reg, u32 val)
{
+ u16 offs = ctrl->flash_dma_offsets[dma_reg];
+
brcmnand_writel(val, ctrl->flash_dma_base + offs);
}
-static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
+static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl,
+ enum flash_dma_reg dma_reg)
{
+ u16 offs = ctrl->flash_dma_offsets[dma_reg];
+
return brcmnand_readl(ctrl->flash_dma_base + offs);
}
@@ -2470,6 +2527,7 @@ static const struct of_device_id brcmnand_of_match[] = {
{ .compatible = "brcm,brcmnand-v7.0" },
{ .compatible = "brcm,brcmnand-v7.1" },
{ .compatible = "brcm,brcmnand-v7.2" },
+ { .compatible = "brcm,brcmnand-v7.3" },
{},
};
MODULE_DEVICE_TABLE(of, brcmnand_of_match);
@@ -2600,7 +2658,11 @@ int brcmnand_probe(struct udevice *dev, struct
brcmnand_soc *soc)
goto err;
}
- flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
+ /* initialize the dma version */
+ brcmnand_flash_dma_revision_init(ctrl);
+
+ /* linked-list and stop on error */
+ flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK);
flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
/* Allocate descriptor(s) */
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH v2 01/10] mtd: rawnand: brcmnand: Refactored code to introduce helper functions
GE_READ */
brcmnand_send_cmd(host, CMD_PAGE_READ);
brcmnand_waitfunc(mtd, chip);
@@ -1633,21 +1669,15 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd,
struct nand_chip *chip,
host->hwcfg.sector_size_1k);
if (ret != -EBADMSG) {
- *err_addr = brcmnand_read_reg(ctrl,
- BRCMNAND_UNCORR_ADDR) |
- ((u64)(brcmnand_read_reg(ctrl,
- BRCMNAND_UNCORR_EXT_ADDR)
- & 0x) << 32);
+ *err_addr = brcmnand_get_uncorrecc_addr(ctrl);
+
if (*err_addr)
ret = -EBADMSG;
}
if (!ret) {
- *err_addr = brcmnand_read_reg(ctrl,
- BRCMNAND_CORR_ADDR) |
- ((u64)(brcmnand_read_reg(ctrl,
- BRCMNAND_CORR_EXT_ADDR)
- & 0x) << 32);
+ *err_addr = brcmnand_get_correcc_addr(ctrl);
+
if (*err_addr)
ret = -EUCLEAN;
}
@@ -1721,7 +1751,7 @@ static int brcmnand_read(struct mtd_info *mtd, struct
nand_chip *chip,
dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
try_dmaread:
- brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
+ brcmnand_clear_ecc_addr(ctrl);
#ifndef __UBOOT__
if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
@@ -1875,15 +1905,9 @@ static int brcmnand_write(struct mtd_info *mtd, struct
nand_chip *chip,
}
#endif /* __UBOOT__ */
- brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
- (host->cs << 16) | ((addr >> 32) & 0x));
- (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
-
for (i = 0; i < trans; i++, addr += FC_BYTES) {
/* full address MUST be set before populating FC */
- brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
- lower_32_bits(addr));
- (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+ brcmnand_set_cmd_addr(mtd, addr);
if (buf) {
brcmnand_soc_data_bus_prepare(ctrl->soc, false);
Acked-by: William Zhang
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH 01/14] mtd: nand: brcm: switch to mtd_ooblayout_ops
Hi Linus and Michael, On 02/03/2023 03:10 AM, Linus Walleij wrote: On Fri, Feb 3, 2023 at 9:48 AM Michael Nazzareno Trimarchi wrote: On Thu, Jan 26, 2023 at 6:39 PM William Zhang wrote: On 01/26/2023 12:43 AM, Linus Walleij wrote: On Thu, Jan 26, 2023 at 2:02 AM William Zhang wrote: Can you add your review-by? I think maybe I need to rebase the series and take out all the changes that does not relate to patch 1 that changes the way we handle the OOB layout so William can test the result? Yeah I think that is a good idea and I can add my review-by and test-by tag if everything is good. Yours, Linus Walleij smime.p7s Description: S/MIME Cryptographic Signature
Re: [PATCH] mtd: rawnand: nand_base: Handle algorithm selection
Hi Linus and Rafał,
On 01/26/2023 12:59 AM, Linus Walleij wrote:
Hi William,
so this is the patch that actually solved my bug in the end :)
On Thu, Jan 26, 2023 at 2:14 AM William Zhang
wrote:
On 01/21/2023 03:43 PM, Linus Walleij wrote:
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
For 1 bit HW ECC, the BRCMNAND driver only uses HAMMING ECC. The
brcmnand_setup_dev function should take care of it with just these two
properties in the device tress without any code changes:
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
unless these D-Link device has always been using software BCH-1 and
wants to continue to use software BCH-1.
BTW, I didn't see this change from master branch of linux nand base
driver. The "nand-ecc-algo" is only used by the ecc engine code(ecc.c)
but this code is not in the u-boot obviously. Were you porting this from
a different version of linux nand driver?
Rafał has provided the answer already: the D-Link DIR-885L and DIR-890L
did choose to use BCH-1 ECC. The brcmnand controller does support it
in hardware too, if configured correctly.
The way the device tree properties work is that:
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
will indeed result in 1-bit Hamming just like you say while:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
will explicitly hammer it down to BCH-1. Currently the D-Link devices
are the two only devices I know that does this in the entire world, but
one of them happens to be on my desktop and I think Rafal has the
other one so we need this.
It does not use software ECC, this is just a (maybe non-standard)
way of using the hw ECC in the brcmnand controller.
In brcmnand.c we reach this:
if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
if (chip->ecc.strength == 1 && chip->ecc.size == 512)
/* Default to Hamming for 1-bit ECC, if unspecified */
chip->ecc.algo = NAND_ECC_HAMMING;
else
/* Otherwise, BCH */
chip->ecc.algo = NAND_ECC_BCH;
}
if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
chip->ecc.size != 512)) {
dev_err(ctrl->dev, "invalid Hamming params: %d bits
per %d bytes\n",
chip->ecc.strength, chip->ecc.size);
return -EINVAL;
}
Since we now have ecc.algo == NAND_ECC_BCH none of these branches
will be taken and we will not default to hamming.
Next:
switch (chip->ecc.size) {
case 512:
if (chip->ecc.algo == NAND_ECC_HAMMING)
cfg->ecc_level = 15;
else
cfg->ecc_level = chip->ecc.strength;
cfg->sector_size_1k = 0;
break;
Here cfg->ecc_level will be set to 1 since algo is NAND_ECC_BCH.
And this is what these D-Link devices are using.
I understand that from a Broadcom perspective this may look like
a bit of abusive and unintended way of using the hardware, but
D-Link use it and have burnt this specific usecase into the ROM of
a few million routers so...
Yours,
Linus Walleij
Okay this makes sense now. Thanks for the back porting!
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH 01/14] mtd: nand: brcm: switch to mtd_ooblayout_ops
On 01/26/2023 12:43 AM, Linus Walleij wrote:
On Thu, Jan 26, 2023 at 2:02 AM William Zhang
wrote:
Unfortunately the u-boot nand base code still uses nand_ecclayout
structure because it was based on old kernel nand driver. Your change
cause bugcheck in the nand_scan_tail at line 4978 when mtd->oobsize is
not one of the default size (i.e. some large nand with BCH-8 ecc
requirement and has 224 bytes oobsize per 4K page) because ecc->layout
is never set. Also certainly any data built based on nand_cclayout like
mtd->oobavail will not be correct.
I actually converted back to nand_ecclayout structure from mtd_ooblayout
with this fix to solve the above issues.
Fixes: e365de90517b ("drivers: nand: brcmnand: fix nand_chip ecc layout
structure")
Argh yeah I see. Let's hold this series off then.
It was worth a try!
I can see your point to get the latest from the brcmnand linux kernel
driver but this requires updating the u-boot nand base driver to use
mtd_ooblayout as well and all others nand controller drivers too. I am
not sure if this is something you want to tackle right now.
No I can't do that I do not have a big enough experience with NAND
flash and no testbed for it either.
As far as I can see, all other oob/ecc layout setting patches you back
ported in this series are not in the original brcmstb_choose_ecc_layout
code you replaced. So I am not worried about that we must switch to
mtd_ooblayout_ops at this point. If indeed there is bug in
brcmstb_choose_ecc_layout, we can port and convert the fix to
nand_ecclayout structure from kernel code.
OK no they seemed to be mostly improvements of the algorithm so we
can certainly live without.
Was the bug you were hunting down in the code related to this patch?
Actually not, I think, it's one of the other patches I sent, the one enabling
BCH-1 by reading the proper ECC properties from the device tree.
That made it finally work.
>
The iproc NAND driver I sent should also work pretty much as-is, nothing
depends on these backports.
Yes the patches that are not relate to the ooblayout should still be
good to have.
Yours,
Linus Walleij
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH] mtd: rawnand: nand_base: Handle algorithm selection
Hi Linus,
On 01/21/2023 03:43 PM, Linus Walleij wrote:
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
For 1 bit HW ECC, the BRCMNAND driver only uses HAMMING ECC. The
brcmnand_setup_dev function should take care of it with just these two
properties in the device tress without any code changes:
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
unless these D-Link device has always been using software BCH-1 and
wants to continue to use software BCH-1.
BTW, I didn't see this change from master branch of linux nand base
driver. The "nand-ecc-algo" is only used by the ecc engine code(ecc.c)
but this code is not in the u-boot obviously. Were you porting this from
a different version of linux nand driver?
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/nand_base.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 9eba360d55f3..872b58ec5f23 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode
node)
{
int ret, ecc_mode = -1, ecc_strength, ecc_step;
+ int ecc_algo = NAND_ECC_UNKNOWN;
const char *str;
ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
@@ -4512,10 +4513,13 @@ static int nand_dt_init(struct mtd_info *mtd, struct
nand_chip *chip, ofnode nod
ecc_mode = NAND_ECC_SOFT_BCH;
}
- if (ecc_mode == NAND_ECC_SOFT) {
- str = ofnode_read_string(node, "nand-ecc-algo");
- if (str && !strcmp(str, "bch"))
+ str = ofnode_read_string(node, "nand-ecc-algo");
+ if (str && !strcmp(str, "bch")) {
+ ecc_algo = NAND_ECC_BCH;
+ if (ecc_mode == NAND_ECC_SOFT)
ecc_mode = NAND_ECC_SOFT_BCH;
+ } else if (!strcmp(str, "hamming")) {
+ ecc_algo = NAND_ECC_HAMMING;
}
ecc_strength = ofnode_read_s32_default(node,
@@ -4529,6 +4533,9 @@ static int nand_dt_init(struct mtd_info *mtd, struct
nand_chip *chip, ofnode nod
return -EINVAL;
}
+ if (ecc_algo >= 0)
+ chip->ecc.algo = ecc_algo;
+
if (ecc_mode >= 0)
chip->ecc.mode = ecc_mode;
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [PATCH 01/14] mtd: nand: brcm: switch to mtd_ooblayout_ops
Hi Linus,
Unfortunately the u-boot nand base code still uses nand_ecclayout
structure because it was based on old kernel nand driver. Your change
cause bugcheck in the nand_scan_tail at line 4978 when mtd->oobsize is
not one of the default size (i.e. some large nand with BCH-8 ecc
requirement and has 224 bytes oobsize per 4K page) because ecc->layout
is never set. Also certainly any data built based on nand_cclayout like
mtd->oobavail will not be correct.
I actually converted back to nand_ecclayout structure from mtd_ooblayout
with this fix to solve the above issues.
Fixes: e365de90517b ("drivers: nand: brcmnand: fix nand_chip ecc layout
structure")
I can see your point to get the latest from the brcmnand linux kernel
driver but this requires updating the u-boot nand base driver to use
mtd_ooblayout as well and all others nand controller drivers too. I am
not sure if this is something you want to tackle right now.
As far as I can see, all other oob/ecc layout setting patches you back
ported in this series are not in the original brcmstb_choose_ecc_layout
code you replaced. So I am not worried about that we must switch to
mtd_ooblayout_ops at this point. If indeed there is bug in
brcmstb_choose_ecc_layout, we can port and convert the fix to
nand_ecclayout structure from kernel code.
Was the bug you were hunting down in the code related to this patch?
Thanks,
William
On 01/15/2023 11:52 AM, Linus Walleij wrote:
From: Boris Brezillon
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 260 ++-
1 file changed, 156 insertions(+), 104 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 74c9348f7fc4..8ea33e861354 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -894,131 +894,183 @@ static inline bool is_hamming_ecc(struct
brcmnand_controller *ctrl,
}
/*
- * Returns a nand_ecclayout strucutre for the given layout/configuration.
- * Returns NULL on failure.
+ * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
+ * the layout/configuration.
+ * Returns -ERRCODE on failure.
*/
-static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
-struct brcmnand_host *host)
+static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct brcmnand_host *host = nand_get_controller_data(chip);
struct brcmnand_cfg *cfg = &host->hwcfg;
- int i, j;
- struct nand_ecclayout *layout;
- int req;
- int sectors;
- int sas;
- int idx1, idx2;
-#ifndef __UBOOT__
- layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
-#else
- layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL);
-#endif
- if (!layout)
- return NULL;
-
- sectors = cfg->page_size / (512 << cfg->sector_size_1k);
- sas = cfg->spare_area_size << cfg->sector_size_1k;
-
- /* Hamming */
- if (is_hamming_ecc(host->ctrl, cfg)) {
- for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
- /* First sector of each page may have BBI */
- if (i == 0) {
- layout->oobfree[idx2].offset = i * sas + 1;
- /* Small-page NAND use byte 6 for BBI */
- if (cfg->page_size == 512)
- layout->oobfree[idx2].offset--;
- layout->oobfree[idx2].length = 5;
- } else {
- layout->oobfree[idx2].offset = i * sas;
- layout->oobfree[idx2].length = 6;
- }
- idx2++;
- layout->eccpos[idx1++] = i * sas + 6;
- layout->eccpos[idx1++] = i * sas + 7;
- layout->eccpos[idx1++] = i * sas + 8;
- layout->oobfree[idx2].offset = i * sas + 9;
- layout->oobfree[idx2].length = 7;
- idx2++;
- /* Leave zero-terminated entry for OOBFREE */
- if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
- idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
- break;
- }
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+ int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
- return layout;
- }
+ if (section >= s
Re: [PATCH 00/14] Backport BRCMNAND changes from Linux
Hi Linus, I will try to review and test your patches late this week or early next week. I don't have those old chips (v2.1, v2.2, v4) but will test on some of recent Broadcom broadband(BCMBCA) SoCs with v7.0 and 7.1 controller. Thanks, William On 01/16/2023 11:11 AM, Michael Nazzareno Trimarchi wrote: Hi On Sun, Jan 15, 2023 at 8:53 PM Linus Walleij wrote: Hunting down a bug on my system I took to back-porting all reasonable changes from the Linux brcmnand driver that were not yet in the U-Boot derivative. I noticed that a simple diff -ur between brcmnand.c between the file in Linux and U-Boot was possible to see what differs. Combining this with some git log --oneline manual comparison, fuzzing and manual intervention I backported a set of relevant patches from Linux that compiles and WorksForMe(TM). The diff between Linux and U-Boot is much smaller after this, the main missing part are subsystem cosmetics changes and the EDU DMA mode support. This was as much as I could bite off in one go. All patches countersigned-off and marked as [backported]. Thank you for your time It's nice if someone else tests this I think. I don't have any board to test those changes Boris Brezillon (1): mtd: nand: brcm: switch to mtd_ooblayout_ops Claire Lin (1): mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips Kamal Dasu (4): mtd: rawnand: brcmnand: Fix BCH ECC layout for large page NAND parts mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: nand: brcmnand: Add support for flash-dma v0 Álvaro Fernández Rojas (8): mtd: rawnand: brcmnand: fix hamming oob layout mtd: rawnand: brcmnand: improve hamming oob layout mtd: rawnand: brcmnand: correctly verify erased pages mtd: rawnand: brcmnand: rename v4 registers mtd: rawnand: brcmnand: fix CS0 layout mtd: rawnand: brcmnand: rename page sizes mtd: rawnand: brcmnand: support v2.1-v2.2 controllers mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECC drivers/mtd/nand/raw/brcmnand/brcmnand.c | 615 --- 1 file changed, 425 insertions(+), 190 deletions(-) Plan to review this week and run ci-pipeline to include in nand-next MIchael -- 2.39.0 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH] dm: tpl: Add fdt address translation support in TPL
This is needed in the platforms that use "ranges" node property for address translation in their dts for TPL. Signed-off-by: William Zhang --- drivers/core/Kconfig | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index c9bf5de4332b..041d6c502690 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -350,6 +350,20 @@ config SPL_OF_TRANSLATE used for the address translation. This function is faster and smaller in size than fdt_translate_address(). +config TPL_OF_TRANSLATE + bool "Translate addresses using fdt_translate_address in TPL" + depends on TPL_DM && TPL_OF_CONTROL + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address() + config VPL_OF_TRANSLATE bool "Translate addresses using fdt_translate_address in SPL" depends on SPL_DM && VPL_OF_CONTROL -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v2 2/2] timer: bcmbca: use arm global timer for bcm63138 SoC
As STI timer is renamed to ARM A9 global timer, change BCM63138 to use the new global timer config symbol name. This patch applies on top of the my previous patch [1]. [1]: https://lists.denx.de/pipermail/u-boot/2022-August/491060.html Signed-off-by: William Zhang --- Changes in v2: - Fix typo in the subject line and patch link in the commit message arch/arm/mach-bcmbca/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 27b243cbc3d8..62b371612b6a 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -29,7 +29,7 @@ config BCM4912 config BCM63138 bool "Support for Broadcom 63138 Family" select TIMER - select STI_TIMER + select ARM_GLOBAL_TIMER select CPU_V7A select DM_SERIAL select BCM6345_SERIAL -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v2 1/2] timer: sti: convert sti-timer to arm a9 global timer
STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.
Signed-off-by: William Zhang
---
(no changes since v1)
MAINTAINERS | 2 +-
drivers/timer/Kconfig | 8 +++--
drivers/timer/Makefile| 2 +-
.../timer/{sti-timer.c => arm_global_timer.c} | 30 ++-
4 files changed, 23 insertions(+), 19 deletions(-)
rename drivers/timer/{sti-timer.c => arm_global_timer.c} (66%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1103bb068154..f7d77bb8cfa9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -503,7 +503,7 @@ F: drivers/mmc/sti_sdhci.c
F: drivers/reset/sti-reset.c
F: drivers/serial/serial_sti_asc.c
F: drivers/sysreset/sysreset_sti.c
-F: drivers/timer/sti-timer.c
+F: drivers/timer/arm_global_timer.c
F: drivers/usb/host/dwc3-sti-glue.c
F: include/dwc3-sti-glue.h
F: include/dt-bindings/clock/stih407-clks.h
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 20b5af7e260f..3e1d70fbb930 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -215,12 +215,14 @@ config SANDBOX_TIMER
Select this to enable an emulated timer for sandbox. It gets
time from host os.
-config STI_TIMER
- bool "STi timer support"
+config ARM_GLOBAL_TIMER
+ bool "ARM Cortex A9 global timer support"
depends on TIMER
+ depends on ARM
default y if ARCH_STI
help
- Select this to enable a timer for STi devices.
+ Select this to enable global timer found on ARM Cortex A9
+ based devices.
config STM32_TIMER
bool "STM32 timer support"
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index d9822a537009..d23569365408 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
-obj-$(CONFIG_STI_TIMER)+= sti-timer.o
+obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/sti-timer.c b/drivers/timer/arm_global_timer.c
similarity index 66%
rename from drivers/timer/sti-timer.c
rename to drivers/timer/arm_global_timer.c
index 87444a0650f6..065f10bb742b 100644
--- a/drivers/timer/sti-timer.c
+++ b/drivers/timer/arm_global_timer.c
@@ -2,6 +2,8 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, for
STMicroelectronics.
+ *
+ * ARM Cortext A9 global timer driver
*/
#include
@@ -13,13 +15,13 @@
#include
#include
-struct sti_timer_priv {
+struct arm_global_timer_priv {
struct globaltimer *global_timer;
};
-static u64 sti_timer_get_count(struct udevice *dev)
+static u64 arm_global_timer_get_count(struct udevice *dev)
{
- struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct arm_global_timer_priv *priv = dev_get_priv(dev);
struct globaltimer *global_timer = priv->global_timer;
u32 low, high;
u64 timer;
@@ -37,10 +39,10 @@ static u64 sti_timer_get_count(struct udevice *dev)
return (u64)((timer << 32) | low);
}
-static int sti_timer_probe(struct udevice *dev)
+static int arm_global_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct arm_global_timer_priv *priv = dev_get_priv(dev);
struct clk clk;
int err;
ulong ret;
@@ -66,20 +68,20 @@ static int sti_timer_probe(struct udevice *dev)
return 0;
}
-static const struct timer_ops sti_timer_ops = {
- .get_count = sti_timer_get_count,
+static const struct timer_ops arm_global_timer_ops = {
+ .get_count = arm_global_timer_get_count,
};
-static const struct udevice_id sti_timer_ids[] = {
+static const struct udevice_id arm_global_timer_ids[] = {
{ .compatible = "arm,cortex-a9-global-timer" },
{}
};
-U_BOOT_DRIVER(sti_timer) = {
- .name = "sti_timer",
+U_BOOT_DRIVER(arm_global_timer) = {
+ .name = "arm_global_timer",
.id = UCLASS_TIMER,
- .of_match = sti_timer_ids,
- .priv_auto = sizeof(struct sti_timer_priv),
- .probe = sti_timer_probe,
- .ops = &sti_timer_ops,
+ .of_match = arm_global_timer_ids,
+ .priv_auto = sizeof(struct arm_global_timer_priv),
+ .probe = arm_global_timer_probe,
+ .ops = &arm_global_timer_ops,
};
--
2.37.1
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH 2/2] timer: bcmbca: use arm global timer for bcm63138 SoS
As STI timer is renamed to ARM A9 global timer, change BCM63138 to use the new global timer config symbol name. This patch applies on top of the my previous patch [1]. [1]: https://lists.denx.de/pipermail/u-boot/2022-August//491060.html Signed-off-by: William Zhang --- arch/arm/mach-bcmbca/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 27b243cbc3d8..62b371612b6a 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -29,7 +29,7 @@ config BCM4912 config BCM63138 bool "Support for Broadcom 63138 Family" select TIMER - select STI_TIMER + select ARM_GLOBAL_TIMER select CPU_V7A select DM_SERIAL select BCM6345_SERIAL -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH 1/2] timer: sti: convert sti-timer to arm a9 global timer
STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.
Signed-off-by: William Zhang
---
MAINTAINERS | 2 +-
drivers/timer/Kconfig | 8 +++--
drivers/timer/Makefile| 2 +-
.../timer/{sti-timer.c => arm_global_timer.c} | 30 ++-
4 files changed, 23 insertions(+), 19 deletions(-)
rename drivers/timer/{sti-timer.c => arm_global_timer.c} (66%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1103bb068154..f7d77bb8cfa9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -503,7 +503,7 @@ F: drivers/mmc/sti_sdhci.c
F: drivers/reset/sti-reset.c
F: drivers/serial/serial_sti_asc.c
F: drivers/sysreset/sysreset_sti.c
-F: drivers/timer/sti-timer.c
+F: drivers/timer/arm_global_timer.c
F: drivers/usb/host/dwc3-sti-glue.c
F: include/dwc3-sti-glue.h
F: include/dt-bindings/clock/stih407-clks.h
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 20b5af7e260f..3e1d70fbb930 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -215,12 +215,14 @@ config SANDBOX_TIMER
Select this to enable an emulated timer for sandbox. It gets
time from host os.
-config STI_TIMER
- bool "STi timer support"
+config ARM_GLOBAL_TIMER
+ bool "ARM Cortex A9 global timer support"
depends on TIMER
+ depends on ARM
default y if ARCH_STI
help
- Select this to enable a timer for STi devices.
+ Select this to enable global timer found on ARM Cortex A9
+ based devices.
config STM32_TIMER
bool "STM32 timer support"
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index d9822a537009..d23569365408 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
-obj-$(CONFIG_STI_TIMER)+= sti-timer.o
+obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/sti-timer.c b/drivers/timer/arm_global_timer.c
similarity index 66%
rename from drivers/timer/sti-timer.c
rename to drivers/timer/arm_global_timer.c
index 87444a0650f6..065f10bb742b 100644
--- a/drivers/timer/sti-timer.c
+++ b/drivers/timer/arm_global_timer.c
@@ -2,6 +2,8 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, for
STMicroelectronics.
+ *
+ * ARM Cortext A9 global timer driver
*/
#include
@@ -13,13 +15,13 @@
#include
#include
-struct sti_timer_priv {
+struct arm_global_timer_priv {
struct globaltimer *global_timer;
};
-static u64 sti_timer_get_count(struct udevice *dev)
+static u64 arm_global_timer_get_count(struct udevice *dev)
{
- struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct arm_global_timer_priv *priv = dev_get_priv(dev);
struct globaltimer *global_timer = priv->global_timer;
u32 low, high;
u64 timer;
@@ -37,10 +39,10 @@ static u64 sti_timer_get_count(struct udevice *dev)
return (u64)((timer << 32) | low);
}
-static int sti_timer_probe(struct udevice *dev)
+static int arm_global_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct arm_global_timer_priv *priv = dev_get_priv(dev);
struct clk clk;
int err;
ulong ret;
@@ -66,20 +68,20 @@ static int sti_timer_probe(struct udevice *dev)
return 0;
}
-static const struct timer_ops sti_timer_ops = {
- .get_count = sti_timer_get_count,
+static const struct timer_ops arm_global_timer_ops = {
+ .get_count = arm_global_timer_get_count,
};
-static const struct udevice_id sti_timer_ids[] = {
+static const struct udevice_id arm_global_timer_ids[] = {
{ .compatible = "arm,cortex-a9-global-timer" },
{}
};
-U_BOOT_DRIVER(sti_timer) = {
- .name = "sti_timer",
+U_BOOT_DRIVER(arm_global_timer) = {
+ .name = "arm_global_timer",
.id = UCLASS_TIMER,
- .of_match = sti_timer_ids,
- .priv_auto = sizeof(struct sti_timer_priv),
- .probe = sti_timer_probe,
- .ops = &sti_timer_ops,
+ .of_match = arm_global_timer_ids,
+ .priv_auto = sizeof(struct arm_global_timer_priv),
+ .probe = arm_global_timer_probe,
+ .ops = &arm_global_timer_ops,
};
--
2.37.1
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v2 3/3] arm: bcmbca: replace ARCH_BCM6753 symbols in Kconfig with BCM6855
As CONFIG_ARCH_BCM6753 is replaced with CONFIG_BCM6855, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang --- Changes in v2: - Update subject line to be more clear for patch 3 drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 929f3fb9eacb..d8020de969ef 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -111,7 +111,7 @@ config BCM2835_GPIO config BCM6345_GPIO bool "BCM6345 GPIO driver" depends on DM_GPIO && (ARCH_BMIPS || BCM6856 || \ - BCM6858 || BCM63158 || ARCH_BCM6753) + BCM6858 || BCM63158 || BCM6855) help This driver supports the GPIO banks on BCM6345 SoCs. diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 98f015a07f97..996b757e6d00 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -30,7 +30,7 @@ config LED_BCM6358 config LED_BCM6753 bool "LED Support for BCM6753" - depends on LED && ARCH_BCM6753 + depends on LED && BCM6855 help This option enables support for LEDs connected to the BCM6753 HW has blinking and fading capabilities and up to 32 LEDs can be controlled. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index f8445e09633c..d6e3eeb3c093 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -97,7 +97,7 @@ config NAND_BRCMNAND_6368 config NAND_BRCMNAND_6753 bool "Support Broadcom NAND controller on bcm6753" - depends on NAND_BRCMNAND && ARCH_BCM6753 + depends on NAND_BRCMNAND && BCM6855 help Enable support for broadcom nand driver on bcm6753. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 84a4034fe87c..65f2d0821c60 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -129,7 +129,7 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ - BCM6858 || BCM63158 || ARCH_BCM6753) + BCM6858 || BCM63158 || BCM6855) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v2 2/3] arm: bcmbca: remove bcm6753 support under CONFIG_ARCH_BCM6753
BCM6753 is essentially same as the main chip BCM6855 but with different
SKU number. Now that BCM6855 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM6855, remove the original ARCH_BCM6753 support and migrate its
configuration and dts settings. This includes:
- Remove the bcm96753ref board folder. It is replaced by the
generic bcmbca board folder.
- Merge the 6753.dtsi setting to the new 6855.dtsi file. Update
96753ref board dts with the new compatible string.
- Delete broadcom_bcm96763ref.h and merge its setting to the new
bcm96855.h file.
- Delete bcm96753ref_ram_defconfig and use a basic config version of
bcm96855_defconfig
Signed-off-by: William Zhang
---
(no changes since v1)
arch/arm/Kconfig | 8 -
arch/arm/dts/Makefile| 6 +-
arch/arm/dts/bcm6753.dtsi| 208 ---
arch/arm/dts/bcm6855.dtsi| 137 +++
arch/arm/dts/bcm96753ref.dts | 6 +-
board/broadcom/bcm96753ref/Kconfig | 16 --
board/broadcom/bcm96753ref/MAINTAINERS | 6 -
board/broadcom/bcm96753ref/Makefile | 3 -
board/broadcom/bcm96753ref/bcm96753ref.c | 40 -
configs/bcm96753ref_ram_defconfig| 87 --
include/configs/bcm96855.h | 4 +
include/configs/broadcom_bcm96753ref.h | 32
12 files changed, 146 insertions(+), 407 deletions(-)
delete mode 100644 arch/arm/dts/bcm6753.dtsi
delete mode 100644 board/broadcom/bcm96753ref/Kconfig
delete mode 100644 board/broadcom/bcm96753ref/MAINTAINERS
delete mode 100644 board/broadcom/bcm96753ref/Makefile
delete mode 100644 board/broadcom/bcm96753ref/bcm96753ref.c
delete mode 100644 configs/bcm96753ref_ram_defconfig
delete mode 100644 include/configs/broadcom_bcm96753ref.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 063616ff8d0b..c1f195e9d106 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -665,13 +665,6 @@ config ARCH_BCM283X
imply CMD_DM
imply FAT_WRITE
-config ARCH_BCM6753
- bool "Broadcom BCM6753 family"
- select CPU_V7A
- select DM
- select OF_CONTROL
- imply CMD_DM
-
config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
select CPU_V7A
@@ -2267,7 +2260,6 @@ source "board/Marvell/octeontx2/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
-source "board/broadcom/bcm96753ref/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5fd38cc63b63..8fba735cc8ab 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1147,9 +1147,6 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-4-b.dtb
-dtb-$(CONFIG_ARCH_BCM6753) += \
- bcm96753ref.dtb
-
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
@@ -1177,7 +1174,8 @@ dtb-$(CONFIG_BCM6813) += \
dtb-$(CONFIG_BCM6846) += \
bcm96846.dtb
dtb-$(CONFIG_BCM6855) += \
- bcm96855.dtb
+ bcm96855.dtb \
+ bcm96753ref.dtb
dtb-$(CONFIG_BCM6856) += \
bcm96856.dtb \
bcm968360bg.dtb
diff --git a/arch/arm/dts/bcm6753.dtsi b/arch/arm/dts/bcm6753.dtsi
deleted file mode 100644
index e88ab095c290..
--- a/arch/arm/dts/bcm6753.dtsi
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 Philippe Reynes
- */
-
-#include "skeleton.dtsi"
-
-/ {
- compatible = "brcm,bcm6753";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- u-boot,dm-pre-reloc;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0x2>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- l2: l2-cache0 {
- co
[PATCH v2 1/3] arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCA
BCM6855 is a Broadcom ARM A7 based PON Gateway SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family. Like other
broadband SoC, this patch adds it under CONFIG_BCM6855 chip config and
CONFIG_ARCH_BCMBCA platform config.
This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and ARM PL101 uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from linux.
The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.
Signed-off-by: William Zhang
---
Changes in v2:
- Add help in BCM6855 Kconfig option to include the list of the
supported chips.
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/bcm6855.dtsi | 120 ++
arch/arm/dts/bcm96855.dts | 30 +++
arch/arm/mach-bcmbca/Kconfig | 11 +++
arch/arm/mach-bcmbca/Makefile | 1 +
arch/arm/mach-bcmbca/bcm6855/Kconfig | 17
arch/arm/mach-bcmbca/bcm6855/Makefile | 5 ++
board/broadcom/bcmbca/Kconfig | 7 ++
configs/bcm96855_defconfig| 23 +
include/configs/bcm96855.h| 11 +++
11 files changed, 228 insertions(+)
create mode 100644 arch/arm/dts/bcm6855.dtsi
create mode 100644 arch/arm/dts/bcm96855.dts
create mode 100644 arch/arm/mach-bcmbca/bcm6855/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm6855/Makefile
create mode 100644 configs/bcm96855_defconfig
create mode 100644 include/configs/bcm96855.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 819fa5b87824..371e84de1bc1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -230,6 +230,7 @@ N: bcm[9]?63178
N: bcm[9]?6756
N: bcm[9]?6813
N: bcm[9]?6846
+N: bcm[9]?6855
N: bcm[9]?6856
N: bcm[9]?6858
N: bcm[9]?6878
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 07e6130042f5..5fd38cc63b63 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1176,6 +1176,8 @@ dtb-$(CONFIG_BCM6813) += \
bcm96813.dtb
dtb-$(CONFIG_BCM6846) += \
bcm96846.dtb
+dtb-$(CONFIG_BCM6855) += \
+ bcm96855.dtb
dtb-$(CONFIG_BCM6856) += \
bcm96856.dtb \
bcm968360bg.dtb
diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi
new file mode 100644
index ..620f51aee1a2
--- /dev/null
+++ b/arch/arm/dts/bcm6855.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "brcm,bcm6855", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = ,
+ ,
+ ;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>
[PATCH v2 0/3] arm: bcmbca: move bcm6753 support under CONFIG_ARCH_BCMBCA
Sorry for another version of patch series with some minor updates. Please see the change log and specific patch for details. BCM6753 is essentially same as the main chip BCM6855 with different SKU number. It is part of the Broadcom BCA (Broadband Carrier Access origin) chipset family. BCM6753 was originally added by Philippe before Broadcom started to upstream the support for BCMBCA SoCs. The ARM based broadband SoC family is now supported under the unified ARCH_BCMBCA config. This patch series migrate the BCM6753 support under the config of ARCH_BCMBCA and BCM6855. This patch series need to apply on top of my previous patch series [1]. This concludes the addition of BCA SoC support to u-boot at least for now. [1]: https://lists.denx.de/pipermail/u-boot/2022-August/492474.html Changes in v2: - Add help in BCM6855 Kconfig option to include the list of the supported chips. - Update subject line to be more clear for patch 3 William Zhang (3): arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCA arm: bcmbca: remove bcm6753 support under CONFIG_ARCH_BCM6753 arm: bcmbca: replace ARCH_BCM6753 symbols in Kconfig with BCM6855 MAINTAINERS | 1 + arch/arm/Kconfig | 8 - arch/arm/dts/Makefile| 6 +- arch/arm/dts/bcm6753.dtsi| 208 -- arch/arm/dts/bcm6855.dtsi| 257 +++ arch/arm/dts/bcm96753ref.dts | 6 +- arch/arm/dts/bcm96855.dts| 30 +++ arch/arm/mach-bcmbca/Kconfig | 11 + arch/arm/mach-bcmbca/Makefile| 1 + arch/arm/mach-bcmbca/bcm6855/Kconfig | 17 ++ arch/arm/mach-bcmbca/bcm6855/Makefile| 5 + board/broadcom/bcm96753ref/Kconfig | 16 -- board/broadcom/bcm96753ref/MAINTAINERS | 6 - board/broadcom/bcm96753ref/Makefile | 3 - board/broadcom/bcm96753ref/bcm96753ref.c | 40 board/broadcom/bcmbca/Kconfig| 7 + configs/bcm96753ref_ram_defconfig| 87 configs/bcm96855_defconfig | 23 ++ drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- include/configs/bcm96855.h | 15 ++ include/configs/broadcom_bcm96753ref.h | 32 --- 24 files changed, 377 insertions(+), 410 deletions(-) delete mode 100644 arch/arm/dts/bcm6753.dtsi create mode 100644 arch/arm/dts/bcm6855.dtsi create mode 100644 arch/arm/dts/bcm96855.dts create mode 100644 arch/arm/mach-bcmbca/bcm6855/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm6855/Makefile delete mode 100644 board/broadcom/bcm96753ref/Kconfig delete mode 100644 board/broadcom/bcm96753ref/MAINTAINERS delete mode 100644 board/broadcom/bcm96753ref/Makefile delete mode 100644 board/broadcom/bcm96753ref/bcm96753ref.c delete mode 100644 configs/bcm96753ref_ram_defconfig create mode 100644 configs/bcm96855_defconfig create mode 100644 include/configs/bcm96855.h delete mode 100644 include/configs/broadcom_bcm96753ref.h -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v2 3/3] arm: bcmbca: replace ARCH_BCM6858 symbols in Kconfig with BCM6858
As CONFIG_ARCH_BCM6858 is replaced with CONFIG_BCM6858, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang --- Changes in v2: -Update subject line to be more clear for patch 3 drivers/gpio/Kconfig | 3 +-- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/spi/Kconfig | 3 +-- drivers/watchdog/Kconfig | 3 +-- 5 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 9e00b48234ab..929f3fb9eacb 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -111,8 +111,7 @@ config BCM2835_GPIO config BCM6345_GPIO bool "BCM6345 GPIO driver" depends on DM_GPIO && (ARCH_BMIPS || BCM6856 || \ - ARCH_BCM6858 || BCM63158 || \ - ARCH_BCM6753) + BCM6858 || BCM63158 || ARCH_BCM6753) help This driver supports the GPIO banks on BCM6345 SoCs. diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index bd8f23fd9631..98f015a07f97 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -37,7 +37,7 @@ config LED_BCM6753 config LED_BCM6858 bool "LED Support for BCM6858" - depends on LED && (BCM6856 || ARCH_BCM6858 || BCM63158) + depends on LED && (BCM6856 || BCM6858 || BCM63158) help This option enables support for LEDs connected to the BCM6858 HW has blinking capabilities and up to 32 LEDs can be controlled. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5d006ca1ea07..f8445e09633c 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -115,7 +115,7 @@ config NAND_BRCMNAND_6838 config NAND_BRCMNAND_6858 bool "Support Broadcom NAND controller on bcm6858" - depends on NAND_BRCMNAND && ARCH_BCM6858 + depends on NAND_BRCMNAND && BCM6858 help Enable support for broadcom nand driver on bcm6858. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 978e5c86a420..e815a715f9b2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -91,8 +91,7 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || BCM6856 || \ - ARCH_BCM6858 || BCM63158) + depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158) help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6d559515b78b..84a4034fe87c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -129,8 +129,7 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ - ARCH_BCM6858 || BCM63158 || \ - ARCH_BCM6753) + BCM6858 || BCM63158 || ARCH_BCM6753) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v2 2/3] arm: bcmbca: remove bcm6858 support under CONFIG_ARCH_BCM6858
Now that BCM6858 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM6858, remove the original ARCH_BCM6858 support and migrate its
configuration and dts settings. This includes:
- Remove the bcm968580xref board folder. It is replaced by the generic
bcmbca board folder.
- Update bcm968580xref board dts with the new compatible string.
- Delete broadcom_bcm968580xref.h and merge its setting to the new
bcm96858.h file.
- Remove bcm968580xref_ram_defconfig as a basic config version of
bcm96858_defconfig is now added.
Signed-off-by: William Zhang
---
(no changes since v1)
arch/arm/Kconfig | 7 ---
arch/arm/dts/Makefile| 6 +-
arch/arm/dts/bcm968580xref.dts | 4 +-
board/broadcom/bcm968580xref/Kconfig | 17 --
board/broadcom/bcm968580xref/MAINTAINERS | 6 --
board/broadcom/bcm968580xref/Makefile| 3 -
board/broadcom/bcm968580xref/bcm968580xref.c | 62 ---
configs/bcm968580xref_ram_defconfig | 64
include/configs/bcm96858.h | 4 ++
include/configs/broadcom_bcm968580xref.h | 32 --
10 files changed, 8 insertions(+), 197 deletions(-)
delete mode 100644 board/broadcom/bcm968580xref/Kconfig
delete mode 100644 board/broadcom/bcm968580xref/MAINTAINERS
delete mode 100644 board/broadcom/bcm968580xref/Makefile
delete mode 100644 board/broadcom/bcm968580xref/bcm968580xref.c
delete mode 100644 configs/bcm968580xref_ram_defconfig
delete mode 100644 include/configs/broadcom_bcm968580xref.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f124ab0ce85..063616ff8d0b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -672,12 +672,6 @@ config ARCH_BCM6753
select OF_CONTROL
imply CMD_DM
-config ARCH_BCM6858
- bool "Broadcom BCM6858 family"
- select DM
- select OF_CONTROL
- imply CMD_DM
-
config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
select CPU_V7A
@@ -2274,7 +2268,6 @@ source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
source "board/broadcom/bcm96753ref/Kconfig"
-source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ee3475b97a40..07e6130042f5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1150,9 +1150,6 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
dtb-$(CONFIG_ARCH_BCM6753) += \
bcm96753ref.dtb
-dtb-$(CONFIG_ARCH_BCM6858) += \
- bcm968580xref.dtb
-
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
@@ -1183,7 +1180,8 @@ dtb-$(CONFIG_BCM6856) += \
bcm96856.dtb \
bcm968360bg.dtb
dtb-$(CONFIG_BCM6858) += \
- bcm96858.dtb
+ bcm96858.dtb \
+ bcm968580xref.dtb
dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
index a034e38318bd..6d787bd011b8 100644
--- a/arch/arm/dts/bcm968580xref.dts
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -8,8 +8,8 @@
#include "bcm6858.dtsi"
/ {
- model = "Broadcom bcm68580xref";
- compatible = "broadcom,bcm68580xref", "brcm,bcm6858";
+ model = "Broadcom BCM968580xref Reference Board";
+ compatible = "brcm,bcm968580xref", "brcm,bcm6858", "brcm,bcmbca";
aliases {
serial0 = &uart0;
diff --git a/board/broadcom/bcm968580xref/Kconfig
b/board/broadcom/bcm968580xref/Kconfig
deleted file mode 100644
index b5730367a2d2..
--- a/board/broadcom/bcm968580xref/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if ARCH_BCM6858
-
-config SYS_VENDOR
- default "broadcom"
-
-config SYS_BOARD
- default "bcm968580xref"
-
-config SYS_CONFIG_NAME
- default "broadcom_bcm968580xref"
-
-endif
-
-config TARGET_BCM968580XREF
- bool "Support Broadcom bcm968580xref"
- depends on ARCH_BCM6858
- select ARM64
diff --git a/board/broadcom/bcm968580xref/MAINTAINERS
b/board/broadcom/bcm968580xref/MAINTAINERS
deleted file mode 100644
index 5ee0c4dd4e42..
--- a/board/broadcom/bcm968580xref/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCM968580XREF BOARD
-M: Philippe Reynes
-S: Maintained
-F: board/broadcom/bcm968580xref/
-F: include/configs/broadcom_bcm968580xref.h
-F: configs/bcm968580xref_ram_defconfig
diff --git a/board/broadcom/bcm968580xref/Makefile
b/board/broadcom/bcm968580xref/Makefile
deleted file mode 100644
index 5cd393b19629..
--- a/board/broadcom/bcm968580xref/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-Lic
[PATCH v2 1/3] arm: bcmbca: add bcm6858 SoC support under CONFIG_ARCH_BCMBCA
BCM6858 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family. Like other broadband
SoC, this patch adds it under CONFIG_BCM6858 chip config and
CONFIG_ARCH_BCMBCA platform config.
This initial support includes a bare-bone implementation and the
original dts is updated with the one from linux next git repository.
The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.
Signed-off-by: William Zhang
---
Changes in v2:
-Add help in BCM6858 Kconfig option to include the list of the supported
chips.
MAINTAINERS | 1 +
arch/arm/dts/Makefile| 2 +
arch/arm/dts/bcm6858.dtsi| 197 ++-
arch/arm/dts/bcm96858.dts| 30
arch/arm/mach-bcmbca/Kconfig | 11 ++
arch/arm/mach-bcmbca/Makefile| 1 +
arch/arm/mach-bcmbca/bcm6858/Kconfig | 17 ++
arch/arm/mach-bcmbca/bcm6858/Makefile| 5 +
arch/arm/mach-bcmbca/bcm6858/mmu_table.c | 32
board/broadcom/bcmbca/Kconfig| 7 +
configs/bcm96858_defconfig | 23 +++
include/configs/bcm96858.h | 11 ++
12 files changed, 258 insertions(+), 79 deletions(-)
create mode 100644 arch/arm/dts/bcm96858.dts
create mode 100644 arch/arm/mach-bcmbca/bcm6858/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm6858/Makefile
create mode 100644 arch/arm/mach-bcmbca/bcm6858/mmu_table.c
create mode 100644 configs/bcm96858_defconfig
create mode 100644 include/configs/bcm96858.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1f50dad583ce..819fa5b87824 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -231,6 +231,7 @@ N: bcm[9]?6756
N: bcm[9]?6813
N: bcm[9]?6846
N: bcm[9]?6856
+N: bcm[9]?6858
N: bcm[9]?6878
ARM BROADCOM BCMSTB
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0ea9fa6029d..ee3475b97a40 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1182,6 +1182,8 @@ dtb-$(CONFIG_BCM6846) += \
dtb-$(CONFIG_BCM6856) += \
bcm96856.dtb \
bcm968360bg.dtb
+dtb-$(CONFIG_BCM6858) += \
+ bcm96858.dtb
dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 02225621710b..19c4dd6fa7e4 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -1,122 +1,161 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes
+ * Copyright 2022 Broadcom Ltd.
*/
-#include "skeleton64.dtsi"
+#include
+#include
/ {
- compatible = "brcm,bcm6858";
+ compatible = "brcm,bcm6858", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- spi0 = &hsspi;
- };
+ interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_2: cpu@2 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_3: cpu@3 {
+
[PATCH v2 0/3] arm: bcmbca: move bcm6858 support under CONFIG_ARCH_BCMBCA
Sorry for another version of patch series with some minor updates. Please see the change log and specific patch for details. BCM6858 is part of the Broadcom BCA (Broadband Carrier Access origin) chipset family. BCM6858 was originally added by Philippe before Broadcom started to upstream the support for BCMBCA SoCs. The ARM based Broadband SoC family is now supported under the unified ARCH_BCMBCA config. This patch series migrate the BCM6858 support under the config of ARCH_BCMBCA and BCM6858. This patch series need to apply on top of my previous patch series [1]. [1]: https://lists.denx.de/pipermail/u-boot/2022-August/492470.html Changes in v2: -Add help in BCM6858 Kconfig option to include the list of the supported chips. -Update subject line to be more clear for patch 3 William Zhang (3): arm: bcmbca: add bcm6858 SoC support under CONFIG_ARCH_BCMBCA arm: bcmbca: remove bcm6858 support under CONFIG_ARCH_BCM6858 arm: bcmbca: replace ARCH_BCM6858 symbols in Kconfig with BCM6858 MAINTAINERS | 1 + arch/arm/Kconfig | 7 - arch/arm/dts/Makefile| 6 +- arch/arm/dts/bcm6858.dtsi| 197 +++ arch/arm/dts/bcm96858.dts| 30 +++ arch/arm/dts/bcm968580xref.dts | 4 +- arch/arm/mach-bcmbca/Kconfig | 11 ++ arch/arm/mach-bcmbca/Makefile| 1 + arch/arm/mach-bcmbca/bcm6858/Kconfig | 17 ++ arch/arm/mach-bcmbca/bcm6858/Makefile| 5 + arch/arm/mach-bcmbca/bcm6858/mmu_table.c | 32 +++ board/broadcom/bcm968580xref/Kconfig | 17 -- board/broadcom/bcm968580xref/MAINTAINERS | 6 - board/broadcom/bcm968580xref/Makefile| 3 - board/broadcom/bcm968580xref/bcm968580xref.c | 62 -- board/broadcom/bcmbca/Kconfig| 7 + configs/bcm968580xref_ram_defconfig | 64 -- configs/bcm96858_defconfig | 23 +++ drivers/gpio/Kconfig | 3 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/spi/Kconfig | 3 +- drivers/watchdog/Kconfig | 3 +- include/configs/bcm96858.h | 15 ++ include/configs/broadcom_bcm968580xref.h | 32 --- 25 files changed, 270 insertions(+), 283 deletions(-) create mode 100644 arch/arm/dts/bcm96858.dts create mode 100644 arch/arm/mach-bcmbca/bcm6858/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm6858/Makefile create mode 100644 arch/arm/mach-bcmbca/bcm6858/mmu_table.c delete mode 100644 board/broadcom/bcm968580xref/Kconfig delete mode 100644 board/broadcom/bcm968580xref/MAINTAINERS delete mode 100644 board/broadcom/bcm968580xref/Makefile delete mode 100644 board/broadcom/bcm968580xref/bcm968580xref.c delete mode 100644 configs/bcm968580xref_ram_defconfig create mode 100644 configs/bcm96858_defconfig create mode 100644 include/configs/bcm96858.h delete mode 100644 include/configs/broadcom_bcm968580xref.h -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v4 3/3] arm: bcmbca: replace ARCH_BCM68360 symbols in Kconfig with BCM6856
As CONFIG_ARCH_BCM68360 is replaced with CONFIG_BCM6856, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang --- Changes in v4: -Update subject line to be more clear for patch 3 drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 83f4f5089992..9e00b48234ab 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -110,7 +110,7 @@ config BCM2835_GPIO config BCM6345_GPIO bool "BCM6345 GPIO driver" - depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ + depends on DM_GPIO && (ARCH_BMIPS || BCM6856 || \ ARCH_BCM6858 || BCM63158 || \ ARCH_BCM6753) help diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index d777414dda8d..bd8f23fd9631 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -37,7 +37,7 @@ config LED_BCM6753 config LED_BCM6858 bool "LED Support for BCM6858" - depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || BCM63158) + depends on LED && (BCM6856 || ARCH_BCM6858 || BCM63158) help This option enables support for LEDs connected to the BCM6858 HW has blinking capabilities and up to 32 LEDs can be controlled. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 24c27b6ecf7f..5d006ca1ea07 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -103,7 +103,7 @@ config NAND_BRCMNAND_6753 config NAND_BRCMNAND_68360 bool "Support Broadcom NAND controller on bcm68360" - depends on NAND_BRCMNAND && ARCH_BCM68360 + depends on NAND_BRCMNAND && BCM6856 help Enable support for broadcom nand driver on bcm68360. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0a666eee80e7..978e5c86a420 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -91,7 +91,7 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || ARCH_BCM68360 || \ + depends on (ARCH_BMIPS || BCM6856 || \ ARCH_BCM6858 || BCM63158) help Enable the BCM6328 HSSPI driver. This driver can be used to diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index ff4d1ee530d2..6d559515b78b 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -128,7 +128,7 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" - depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \ + depends on WDT && (ARCH_BMIPS || BCM6856 || \ ARCH_BCM6858 || BCM63158 || \ ARCH_BCM6753) help -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v4 2/3] arm: bcmbca: remove bcm68360 support under CONFIG_ARCH_BCM68360
BCM68360 is a variant within the BCM6856 chip family. Now that BCM6856
is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM6856, remove the
original ARCH_BCM68360 support and migrate its configuration and dts
settings. This includes:
- Remove the bcm968360bg board folder. It is replaced by the generic
bcmbca board folder.
- Merge the 68360.dtsi setting to the new 6856.dtsi file. Update board
dts with the new compatible string.
- Merge broadcom_bcm968360bg.h setting to the new bcm96856.h file.
- Remove bcm968360bg_ram_defconfig as a basic config version of
bcm96856_defconfig is now added.
Signed-off-by: William Zhang
---
(no changes since v3)
Changes in v3:
- Remove bcm968360bg_ram_defconfig per discussion with Philippe as a
basic config version of bcm96856_defconfig is now added.
- Update commit message
Changes in v2:
- Bring Philippe Reynes copyright tag from 68360 dts to 6856 dts
arch/arm/Kconfig | 7 -
arch/arm/dts/Makefile| 6 +-
arch/arm/dts/bcm68360.dtsi | 217 ---
arch/arm/dts/bcm6856.dtsi| 150
arch/arm/dts/bcm968360bg.dts | 6 +-
board/broadcom/bcm968360bg/Kconfig | 17 --
board/broadcom/bcm968360bg/MAINTAINERS | 6 -
board/broadcom/bcm968360bg/Makefile | 3 -
board/broadcom/bcm968360bg/bcm968360bg.c | 62 ---
configs/bcm968360bg_ram_defconfig| 63 ---
include/configs/bcm96856.h | 4 +
include/configs/broadcom_bcm968360bg.h | 32
12 files changed, 159 insertions(+), 414 deletions(-)
delete mode 100644 arch/arm/dts/bcm68360.dtsi
delete mode 100644 board/broadcom/bcm968360bg/Kconfig
delete mode 100644 board/broadcom/bcm968360bg/MAINTAINERS
delete mode 100644 board/broadcom/bcm968360bg/Makefile
delete mode 100644 board/broadcom/bcm968360bg/bcm968360bg.c
delete mode 100644 configs/bcm968360bg_ram_defconfig
delete mode 100644 include/configs/broadcom_bcm968360bg.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da4defa08466..3f124ab0ce85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -672,12 +672,6 @@ config ARCH_BCM6753
select OF_CONTROL
imply CMD_DM
-config ARCH_BCM68360
- bool "Broadcom BCM68360 family"
- select DM
- select OF_CONTROL
- imply CMD_DM
-
config ARCH_BCM6858
bool "Broadcom BCM6858 family"
select DM
@@ -2280,7 +2274,6 @@ source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
source "board/broadcom/bcm96753ref/Kconfig"
-source "board/broadcom/bcm968360bg/Kconfig"
source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a32bdf8c9f17..a0ea9fa6029d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1147,9 +1147,6 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-4-b.dtb
-dtb-$(CONFIG_ARCH_BCM68360) += \
- bcm968360bg.dtb
-
dtb-$(CONFIG_ARCH_BCM6753) += \
bcm96753ref.dtb
@@ -1183,7 +1180,8 @@ dtb-$(CONFIG_BCM6813) += \
dtb-$(CONFIG_BCM6846) += \
bcm96846.dtb
dtb-$(CONFIG_BCM6856) += \
- bcm96856.dtb
+ bcm96856.dtb \
+ bcm968360bg.dtb
dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
diff --git a/arch/arm/dts/bcm68360.dtsi b/arch/arm/dts/bcm68360.dtsi
deleted file mode 100644
index 7bbe207794eb..
--- a/arch/arm/dts/bcm68360.dtsi
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Philippe Reynes
- */
-
-#include "skeleton64.dtsi"
-
-/ {
- compatible = "brcm,bcm68360";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- spi0 = &hsspi;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
- u-boot,dm-pre-reloc;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- reg = <0x0 0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- reg = <0x0 0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
-
[PATCH v4 1/3] arm: bcmbca: add bcm6856 SoC support under CONFIG_ARCH_BCMBCA
BCM6856 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family. Like other Broadband
SoC, this patch adds it under CONFIG_BCM6856 chip config and
CONFIG_ARCH_BCMBCA platform config.
This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and Broadcom uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from
linux.
The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.
Signed-off-by: William Zhang
---
Changes in v4:
-Add help in BCM6856 Kconfig option to include the list of the supported
chips.
MAINTAINERS | 1 +
arch/arm/dts/Makefile| 2 +
arch/arm/dts/bcm6856.dtsi| 103 +++
arch/arm/dts/bcm96856.dts| 30 +++
arch/arm/mach-bcmbca/Kconfig | 11 +++
arch/arm/mach-bcmbca/Makefile| 1 +
arch/arm/mach-bcmbca/bcm6856/Kconfig | 17
arch/arm/mach-bcmbca/bcm6856/Makefile| 5 ++
arch/arm/mach-bcmbca/bcm6856/mmu_table.c | 32 +++
board/broadcom/bcmbca/Kconfig| 7 ++
configs/bcm96856_defconfig | 23 +
include/configs/bcm96856.h | 11 +++
12 files changed, 243 insertions(+)
create mode 100644 arch/arm/dts/bcm6856.dtsi
create mode 100644 arch/arm/dts/bcm96856.dts
create mode 100644 arch/arm/mach-bcmbca/bcm6856/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm6856/Makefile
create mode 100644 arch/arm/mach-bcmbca/bcm6856/mmu_table.c
create mode 100644 configs/bcm96856_defconfig
create mode 100644 include/configs/bcm96856.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d0a5b2352cc8..1f50dad583ce 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -230,6 +230,7 @@ N: bcm[9]?63178
N: bcm[9]?6756
N: bcm[9]?6813
N: bcm[9]?6846
+N: bcm[9]?6856
N: bcm[9]?6878
ARM BROADCOM BCMSTB
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c55bc3569662..a32bdf8c9f17 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1182,6 +1182,8 @@ dtb-$(CONFIG_BCM6813) += \
bcm96813.dtb
dtb-$(CONFIG_BCM6846) += \
bcm96846.dtb
+dtb-$(CONFIG_BCM6856) += \
+ bcm96856.dtb
dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi
new file mode 100644
index ..0bce6497219f
--- /dev/null
+++ b/arch/arm/dts/bcm6856.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "brcm,bcm6856", "brcm,bcmbca";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+ ;
+ interrupt-affinity = <&B53_0>, <&B53_1>;
+ };
+
+ clocks: clocks {
+ periph_clk:periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@8100 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x8100 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400
[PATCH v4 0/3] arm: bcmbca: move bcm68360 support under CONFIG_ARCH_BCMBCA
Sorry for another version of patch series with some minor updates. Please see the change log and specific patch for details. BCM68360 is a variant for the main PON chip BCM6856 which is part of the Broadcom BCA (Broadband Carrier Access origin) chipset family. BCM68360 was originally added by Philippe before Broadcom started to upstream the support for BCMBCA SoCs. The ARM based Broadband SoC family is now supported under the unified ARCH_BCMBCA config. This patch series migrate the BCM68360 support under the config of ARCH_BCMBCA and BCM6856. This patch series need to apply on top of my previous patch series [1]. [1]: https://lists.denx.de/pipermail/u-boot/2022-August/492464.html Changes in v4: -Add help in BCM6856 Kconfig option to include the list of the supported chips. -Update subject line to be more clear for patch 3 Changes in v3: - Remove bcm968360bg_ram_defconfig per discussion with Philippe as a basic config version of bcm96856_defconfig is now added. - Update commit message Changes in v2: - Bring Philippe Reynes copyright tag from 68360 dts to 6856 dts William Zhang (3): arm: bcmbca: add bcm6856 SoC support under CONFIG_ARCH_BCMBCA arm: bcmbca: remove bcm68360 support under CONFIG_ARCH_BCM68360 arm: bcmbca: replace ARCH_BCM68360 symbols in Kconfig with BCM6856 MAINTAINERS | 1 + arch/arm/Kconfig | 7 - arch/arm/dts/Makefile| 6 +- arch/arm/dts/bcm68360.dtsi | 217 --- arch/arm/dts/bcm6856.dtsi| 253 +++ arch/arm/dts/bcm968360bg.dts | 6 +- arch/arm/dts/bcm96856.dts| 30 +++ arch/arm/mach-bcmbca/Kconfig | 11 + arch/arm/mach-bcmbca/Makefile| 1 + arch/arm/mach-bcmbca/bcm6856/Kconfig | 17 ++ arch/arm/mach-bcmbca/bcm6856/Makefile| 5 + arch/arm/mach-bcmbca/bcm6856/mmu_table.c | 32 +++ board/broadcom/bcm968360bg/Kconfig | 17 -- board/broadcom/bcm968360bg/MAINTAINERS | 6 - board/broadcom/bcm968360bg/Makefile | 3 - board/broadcom/bcm968360bg/bcm968360bg.c | 62 -- board/broadcom/bcmbca/Kconfig| 7 + configs/bcm968360bg_ram_defconfig| 63 -- configs/bcm96856_defconfig | 23 +++ drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- include/configs/bcm96856.h | 15 ++ include/configs/broadcom_bcm968360bg.h | 32 --- 26 files changed, 406 insertions(+), 418 deletions(-) delete mode 100644 arch/arm/dts/bcm68360.dtsi create mode 100644 arch/arm/dts/bcm6856.dtsi create mode 100644 arch/arm/dts/bcm96856.dts create mode 100644 arch/arm/mach-bcmbca/bcm6856/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm6856/Makefile create mode 100644 arch/arm/mach-bcmbca/bcm6856/mmu_table.c delete mode 100644 board/broadcom/bcm968360bg/Kconfig delete mode 100644 board/broadcom/bcm968360bg/MAINTAINERS delete mode 100644 board/broadcom/bcm968360bg/Makefile delete mode 100644 board/broadcom/bcm968360bg/bcm968360bg.c delete mode 100644 configs/bcm968360bg_ram_defconfig create mode 100644 configs/bcm96856_defconfig create mode 100644 include/configs/bcm96856.h delete mode 100644 include/configs/broadcom_bcm968360bg.h -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 5/5] arm: bcmbca: make reset_cpu function weak
BCM63158 carries the CONFIG_SYSRESET from the original configuration. It
provide reset_cpu function already so need to define weak version of the
dummy reset_cpu for other BCMBCA SoCs to avoid linking error.
Signed-off-by: William Zhang
---
Changes in v3:
-Fix reset_cpu function prototype.
board/broadcom/bcmbca/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c
index 4aa1d659d5c7..bcecb4d78392 100644
--- a/board/broadcom/bcmbca/board.c
+++ b/board/broadcom/bcmbca/board.c
@@ -30,6 +30,6 @@ int print_cpuinfo(void)
return 0;
}
-void reset_cpu(ulong addr)
+__weak void reset_cpu(void)
{
}
--
2.37.1
smime.p7s
Description: S/MIME Cryptographic Signature
[PATCH v3 4/5] MAINTAINERS: Add BCM63158 maintainer to BCMBCA entry
Since ARCH_BCM63158 SoC support is merged into ARCH_BCMBCA, add BCM63158 maintainer Philippe to bcmbca maintainer list. Signed-off-by: William Zhang --- (no changes since v1) MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b219d62f6bf..d0a5b2352cc8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -213,6 +213,7 @@ M: Anand Gore M: William Zhang M: Kursad Oney M: Joel Peshkin +M: Philippe Reynes S: Maintained F: arch/arm/mach-bcmbca/ F: board/broadcom/bcmbca/ -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 3/5] arm: bcmbca: replace ARCH_BCM63158 symbols in Kconfig with BCM63158
As CONFIG_ARCH_BCM63158 is replaced with CONFIG_BCM63158, update the Kconfig to use the new config symbol. Signed-off-by: William Zhang --- Changes in v3: -Update subject line to be more clear drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index aaa152fae73b..83f4f5089992 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -111,7 +111,7 @@ config BCM2835_GPIO config BCM6345_GPIO bool "BCM6345 GPIO driver" depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \ - ARCH_BCM6858 || ARCH_BCM63158 || \ + ARCH_BCM6858 || BCM63158 || \ ARCH_BCM6753) help This driver supports the GPIO banks on BCM6345 SoCs. diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index ccdd7d7395c8..d777414dda8d 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -37,7 +37,7 @@ config LED_BCM6753 config LED_BCM6858 bool "LED Support for BCM6858" - depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || ARCH_BCM63158) + depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || BCM63158) help This option enables support for LEDs connected to the BCM6858 HW has blinking capabilities and up to 32 LEDs can be controlled. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde25..24c27b6ecf7f 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -121,7 +121,7 @@ config NAND_BRCMNAND_6858 config NAND_BRCMNAND_63158 bool "Support Broadcom NAND controller on bcm63158" - depends on NAND_BRCMNAND && ARCH_BCM63158 + depends on NAND_BRCMNAND && BCM63158 help Enable support for broadcom nand driver on bcm63158. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 75b794548b22..0a666eee80e7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -92,7 +92,7 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" depends on (ARCH_BMIPS || ARCH_BCM68360 || \ - ARCH_BCM6858 || ARCH_BCM63158) + ARCH_BCM6858 || BCM63158) help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 50e6a1efba51..ff4d1ee530d2 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -129,7 +129,7 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \ - ARCH_BCM6858 || ARCH_BCM63158 || \ + ARCH_BCM6858 || BCM63158 || \ ARCH_BCM6753) help Select this to enable watchdog timer for BCM6345 SoCs. -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH v3 2/5] arm: bcmbca: remove bcm63158 support under CONFIG_ARCH_BCM63158
Now that BCM63158 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM63158, remove the original ARCH_BCM63158 support and migrate
configuration settings.
Signed-off-by: William Zhang
---
(no changes since v2)
Changes in v2:
- Remove bcm963158_ram_defconfig per discussion with Philippe as a
basic config version of bcm963158_defconfig is now added.
arch/arm/Kconfig | 8 +---
arch/arm/dts/Makefile| 3 --
board/broadcom/bcm963158/Kconfig | 17 ---
board/broadcom/bcm963158/MAINTAINERS | 6 ---
board/broadcom/bcm963158/Makefile| 3 --
board/broadcom/bcm963158/bcm963158.c | 62 -
configs/bcm963158_ram_defconfig | 67
include/configs/bcm963158.h | 4 ++
include/configs/broadcom_bcm963158.h | 32 -
9 files changed, 5 insertions(+), 197 deletions(-)
delete mode 100644 board/broadcom/bcm963158/Kconfig
delete mode 100644 board/broadcom/bcm963158/MAINTAINERS
delete mode 100644 board/broadcom/bcm963158/Makefile
delete mode 100644 board/broadcom/bcm963158/bcm963158.c
delete mode 100644 configs/bcm963158_ram_defconfig
delete mode 100644 include/configs/broadcom_bcm963158.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d4903a2eb5b..da4defa08466 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -665,12 +665,6 @@ config ARCH_BCM283X
imply CMD_DM
imply FAT_WRITE
-config ARCH_BCM63158
- bool "Broadcom BCM63158 family"
- select DM
- select OF_CONTROL
- imply CMD_DM
-
config ARCH_BCM6753
bool "Broadcom BCM6753 family"
select CPU_V7A
@@ -706,6 +700,7 @@ config ARCH_BCMBCA
bool "Broadcom broadband chip family"
select DM
select OF_CONTROL
+ imply CMD_DM
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
@@ -2284,7 +2279,6 @@ source "board/Marvell/octeontx2/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
-source "board/broadcom/bcm963158/Kconfig"
source "board/broadcom/bcm96753ref/Kconfig"
source "board/broadcom/bcm968360bg/Kconfig"
source "board/broadcom/bcm968580xref/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a7fc3d7d7021..c55bc3569662 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1147,9 +1147,6 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-4-b.dtb
-dtb-$(CONFIG_ARCH_BCM63158) += \
- bcm963158.dtb
-
dtb-$(CONFIG_ARCH_BCM68360) += \
bcm968360bg.dtb
diff --git a/board/broadcom/bcm963158/Kconfig b/board/broadcom/bcm963158/Kconfig
deleted file mode 100644
index 08a8bc1c14d3..
--- a/board/broadcom/bcm963158/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if TARGET_BCM963158
-
-config SYS_VENDOR
- default "broadcom"
-
-config SYS_BOARD
- default "bcm963158"
-
-config SYS_CONFIG_NAME
- default "broadcom_bcm963158"
-
-endif
-
-config TARGET_BCM963158
- bool "Support Broadcom bcm963158"
- depends on ARCH_BCM63158
- select ARM64
diff --git a/board/broadcom/bcm963158/MAINTAINERS
b/board/broadcom/bcm963158/MAINTAINERS
deleted file mode 100644
index d28d971f9d36..
--- a/board/broadcom/bcm963158/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BROADCOM BCM963158
-M: Philippe Reynes
-S: Maintained
-F: board/broadcom/bcm963158/
-F: include/configs/broadcom_bcm963158.h
-F: configs/bcm963158_ram_defconfig
diff --git a/board/broadcom/bcm963158/Makefile
b/board/broadcom/bcm963158/Makefile
deleted file mode 100644
index 0a902c9cf618..
--- a/board/broadcom/bcm963158/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += bcm963158.o
diff --git a/board/broadcom/bcm963158/bcm963158.c
b/board/broadcom/bcm963158/bcm963158.c
deleted file mode 100644
index 9feaee3c0fc4..
--- a/board/broadcom/bcm963158/bcm963158.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Philippe Reynes
- */
-
-#include
-#include
-#include
-#include
-
-#ifdef CONFIG_ARM64
-#include
-
-static struct mm_region broadcom_bcm963158_mem_map[] = {
- {
- /* RAM */
- .virt = 0xUL,
- .phys = 0xUL,
- .size = 8UL * SZ_1G,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-PTE_BLOCK_INNER_SHARE
- }, {
- /* SoC */
- .virt = 0x8000UL,
- .phys = 0x8000UL,
- .size = 0xff8000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-PTE_BLOCK_NON_SHARE |
-
[PATCH v3 1/5] arm: bcmbca: add bcm63158 SoC support under CONFIG_ARCH_BCMBCA
BCM63158 is a Broadcom B53 based DSL Gateway SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family. Like other
Broadband SoC, this patch adds it under CONFIG_BCM63158 chip
config and CONFIG_ARCH_BCMBCA platform config.
This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and ARM PL011 uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from
linux.
The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there to the console.
Signed-off-by: William Zhang
---
(no changes since v2)
Changes in v2:
- Remove extra nodes from bcm963158.dts and keep it as a generic minimun
board support dts following other BCA chip convention.
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/bcm63158.dtsi| 207 +-
arch/arm/dts/bcm963158.dts| 121 +
arch/arm/mach-bcmbca/Kconfig | 8 +
arch/arm/mach-bcmbca/Makefile | 1 +
arch/arm/mach-bcmbca/bcm63158/Kconfig | 17 ++
arch/arm/mach-bcmbca/bcm63158/Makefile| 5 +
arch/arm/mach-bcmbca/bcm63158/mmu_table.c | 32
board/broadcom/bcmbca/Kconfig | 7 +
configs/bcm963158_defconfig | 23 +++
include/configs/bcm963158.h | 11 ++
12 files changed, 239 insertions(+), 196 deletions(-)
create mode 100644 arch/arm/mach-bcmbca/bcm63158/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm63158/Makefile
create mode 100644 arch/arm/mach-bcmbca/bcm63158/mmu_table.c
create mode 100644 configs/bcm963158_defconfig
create mode 100644 include/configs/bcm963158.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3f250942ced1..5b219d62f6bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -224,6 +224,7 @@ N: bcm[9]?4912
N: bcm[9]?63138
N: bcm[9]?63146
N: bcm[9]?63148
+N: bcm[9]?63158
N: bcm[9]?63178
N: bcm[9]?6756
N: bcm[9]?6813
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9a6582d9c1c8..a7fc3d7d7021 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1175,6 +1175,8 @@ dtb-$(CONFIG_BCM63146) += \
bcm963146.dtb
dtb-$(CONFIG_BCM63148) += \
bcm963148.dtb
+dtb-$(CONFIG_BCM63158) += \
+ bcm963158.dtb
dtb-$(CONFIG_BCM63178) += \
bcm963178.dtb
dtb-$(CONFIG_BCM6756) += \
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 7dd285843849..8b179ba0fca8 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -1,122 +1,167 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes
+ * Copyright 2022 Broadcom Ltd.
*/
-#include "skeleton64.dtsi"
+#include
+#include
/ {
- compatible = "brcm,bcm63158";
+ compatible = "brcm,bcm63158", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- spi0 = &hsspi;
- };
+ interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_2: cpu@2 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
[PATCH v3 0/5] arm: bcmbca: move bcm63158 support under CONFIG_ARCH_BCMBCA
Sorry for another version of patch series with some minor updates. Please see the change log and specific patch for details. BCM63158 is one of the Broadcom Broadband origin DSL Gateway router SoC. It was originally added by Philippe before Broadcom started to upstream the support for broadband SoCs. The ARM based Broadcom Broadband SoC family is now supported under the same ARCH_BCMBCA config. This patch series migrate the BCM63158 support to ARCH_BCMBCA. This patch series need to apply on top of my previous patch series [1]. [1]: https://lists.denx.de/pipermail/u-boot/2022-August/491061.html Changes in v3: -Update subject line to be more clear for patch 3 -Fix reset_cpu function prototype. Changes in v2: - Remove extra nodes from bcm963158.dts and keep it as a generic minimun board support dts following other BCA chip convention. - Remove bcm963158_ram_defconfig per discussion with Philippe as a basic config version of bcm963158_defconfig is now added. William Zhang (5): arm: bcmbca: add bcm63158 SoC support under CONFIG_ARCH_BCMBCA arm: bcmbca: remove bcm63158 support under CONFIG_ARCH_BCM63158 arm: bcmbca: replace ARCH_BCM63158 symbols in Kconfig with BCM63158 MAINTAINERS: Add BCM63158 maintainer to BCMBCA entry arm: bcmbca: make reset_cpu function weak MAINTAINERS | 2 + arch/arm/Kconfig | 8 +- arch/arm/dts/Makefile | 5 +- arch/arm/dts/bcm63158.dtsi| 207 +- arch/arm/dts/bcm963158.dts| 121 + arch/arm/mach-bcmbca/Kconfig | 8 + arch/arm/mach-bcmbca/Makefile | 1 + arch/arm/mach-bcmbca/bcm63158/Kconfig | 17 ++ arch/arm/mach-bcmbca/bcm63158/Makefile| 5 + arch/arm/mach-bcmbca/bcm63158/mmu_table.c | 32 board/broadcom/bcm963158/Kconfig | 17 -- board/broadcom/bcm963158/MAINTAINERS | 6 - board/broadcom/bcm963158/Makefile | 3 - board/broadcom/bcm963158/bcm963158.c | 62 --- board/broadcom/bcmbca/Kconfig | 7 + board/broadcom/bcmbca/board.c | 2 +- configs/bcm963158_defconfig | 23 +++ configs/bcm963158_ram_defconfig | 67 --- drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- include/configs/bcm963158.h | 15 ++ include/configs/broadcom_bcm963158.h | 32 25 files changed, 251 insertions(+), 399 deletions(-) create mode 100644 arch/arm/mach-bcmbca/bcm63158/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm63158/Makefile create mode 100644 arch/arm/mach-bcmbca/bcm63158/mmu_table.c delete mode 100644 board/broadcom/bcm963158/Kconfig delete mode 100644 board/broadcom/bcm963158/MAINTAINERS delete mode 100644 board/broadcom/bcm963158/Makefile delete mode 100644 board/broadcom/bcm963158/bcm963158.c create mode 100644 configs/bcm963158_defconfig delete mode 100644 configs/bcm963158_ram_defconfig create mode 100644 include/configs/bcm963158.h delete mode 100644 include/configs/broadcom_bcm963158.h -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
[PATCH 3/3] arm: bcmbca: make bcm6753 driver depending on CONFIG_BCM6855
As CONFIG_ARCH_BCM6753 is replaced with CONFIG_BCM6855, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang --- drivers/gpio/Kconfig | 2 +- drivers/led/Kconfig | 2 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 929f3fb9eacb..d8020de969ef 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -111,7 +111,7 @@ config BCM2835_GPIO config BCM6345_GPIO bool "BCM6345 GPIO driver" depends on DM_GPIO && (ARCH_BMIPS || BCM6856 || \ - BCM6858 || BCM63158 || ARCH_BCM6753) + BCM6858 || BCM63158 || BCM6855) help This driver supports the GPIO banks on BCM6345 SoCs. diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 98f015a07f97..996b757e6d00 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -30,7 +30,7 @@ config LED_BCM6358 config LED_BCM6753 bool "LED Support for BCM6753" - depends on LED && ARCH_BCM6753 + depends on LED && BCM6855 help This option enables support for LEDs connected to the BCM6753 HW has blinking and fading capabilities and up to 32 LEDs can be controlled. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index f8445e09633c..d6e3eeb3c093 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -97,7 +97,7 @@ config NAND_BRCMNAND_6368 config NAND_BRCMNAND_6753 bool "Support Broadcom NAND controller on bcm6753" - depends on NAND_BRCMNAND && ARCH_BCM6753 + depends on NAND_BRCMNAND && BCM6855 help Enable support for broadcom nand driver on bcm6753. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 84a4034fe87c..65f2d0821c60 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -129,7 +129,7 @@ config WDT_AT91 config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ - BCM6858 || BCM63158 || ARCH_BCM6753) + BCM6858 || BCM63158 || BCM6855) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. -- 2.37.1 smime.p7s Description: S/MIME Cryptographic Signature
