Re: [USRP-users] RFNoC Block with two inputs and one output.
Hi Mark, Are you getting a specific error message in GRC? You'll need to post more details for someone to help you. Jonathon On Wed, Dec 13, 2017 at 4:46 AM, Mark Luscombe via USRP-users wrote: > Hi all, > > My next question ;-) > > I want to create a RFNoC Block with two SC16 inputs and one SC16 output. > There doesn’t seem to be an existing Block that does this, so I tried to > copy the RFNoC AddSub Block that has two in and two out, and leave one > output open and adjust the XML to indicate this. I’ve tried many times but > cannot achieve a setup that GRC is happy with. > > Has anybody else got a two in and one out RFNoC Block to work in GRC, and if > so could you share the XML’s with me? > > Thanks, Mark. > > P.S. As a temporary measure i replicate the single output to achieve a two > in and two out RFNoC Block that GRC is happy with. > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi Tien, Run 'make xsim' in the same directory as the testbench. Jonathon On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < usrp-users@lists.ettus.com> wrote: Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simulate the built-in RFNoC block? I see the simulate file (for example noc_block_fft_tb.sv) but not sure how to run it.. Thank you very much for the help. Best, Tien On Mon, Jan 22, 2018 at 10:55 AM, EJ Kreinar wrote: > Hi Tien, > > If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can > follow the example provided in the Makefile for the noc_block_fft_tb: > https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/n > oc_block_fft_tb/Makefile > > Note the three steps: > 1. set LIB_IP_DIR > 2. Include the Makefile.inc associated with the Xilinx IP > 3. Append generated IP to the DESIGN_SRCS > > If the Xilinx IP you want to use is contained in an OOT repo, then you > would want to follow the Makefile.inc process of including the OOT repo: > https://github.com/ejk43/rfnoc-ootexample > > The "noc_block_complextomagphase_tb" example shows an example of how to > include and simulate Xilinx IP inside an OOT repo: > https://github.com/ejk43/rfnoc-ootexample/blob/master/ > rfnoc/testbenches/noc_block_complextomagphase_tb/Makefile > > For another example, this repo with a polyphase channelizer also shows how > to include and simulate Xilinx IP in an OOT repo: https://github.com/e33b1 > 711/rfnoc-ppchan > > Hope this helps, > EJ > > On Fri, Jan 19, 2018 at 10:28 PM, Dang tien Vo-Huu via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi all, >> I have this error when trying to simulate a custom RFNoC block in an OOT >> module: >> >> $ make noc_block_hbFilter_tb >> . >> . >> Starting static elaboration >> ERROR: [VRFC 10-2063] Module not found while processing >> module instance [/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] >> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design >> unit(s) in library work failed. >> INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/r >> fnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_ >> tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' >> ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check >> the Tcl console output or '/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xs >> im_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more >> information. >> . >> . >> >> I can build an FPGA image with the custom RFNoC block following the >> instruction here: http://www.synchronouslabs.com/blog/creating-a-custom- >> rfnoc-block-with-using-xillinx-ip >> but I haven't found a way to simulate this block. >> Is there any way to run the simulation in this situation? Otherwise it >> would be difficult to debug if anything goes wrong.. >> >> Thanks in advance. >> >> Best, >> Tien >> >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] RFNoC: Synthesizing a block containing modules from uhd-fpga
Hi Adam, Can you post your testbench makefile? Jonathon On Jan 10, 2018 5:07 PM, "Adam Parower via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hello everyone, > > > I am trying to create a custom RFNoC block that is similar to the built-in > DUC block. As such, it depends on the cordic_timed, axi_rate_change, and > duc modules defined in uhd-fpga/usrp3/lib/rfnoc. When I attempt to run the > testbench for my block, Vivado fails in synthesis. While Vivado is able to > find cordic_timed.v, axi_rate_change.v, and duc.v, it is unable to find > the submodules that these modules depend on (e.g. axi_rate_change requires > setting_reg, axi_fifo_flop2, and axi_drop_partial_packet). What can I do to > get Vivado to find these dependencies and synthesize my block? > > > Thank you in advance for your assistance. > > > Adam Parower > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Installing Python Modules into E310
Is there a specific method/process to install external modules into the E310? For example, "python bit-array". We would need this module installed to run a .grc file using GNUradio directly on the E310. I have tired installing bitarray directly onto the radio using 'python setup.py install' but wasn't successful. Any help would be appreciated. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images
Tarik, please remember to keep responses on the mailing list, lest they get lost. Yeah, just add fpga=/path/to/image.lvbitx to your device args. -- M On 01/29/2018 09:56 PM, Tarik Kazaz wrote: > Hello Martin, > > Could you provide me more detailed instruction, how to disable PCIe to reload > image. > > I think instead of .bit, I should flash it with .lvbit if I want to use USRP > over PCIe with RFNoC? Or I am wrong. > > Kind Regards, > > Tarik > > -Original Message- > From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf Of > Martin Braun via USRP-users > Sent: maandag 29 januari 2018 20:46 > To: usrp-users@lists.ettus.com > Subject: Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote: >> Hello everyone, >> >> >> >> I am just starting to use RFNoC and I am a bit confused with hardware >> compatibility for RFNoC development. >> >> In order to describe my setup I will list items below: >> >> >> >> 1. I have NI USRP RIO (equivalent of X310 with integrated GPS >> module) >> >> 2. I am connecting it with PC over PCIe interface >> >> >> >> I tried to flash USRP with RFNoC *usrp_x310_fpga_RFNOC_XG.bit* image. >> However, after I power cycle USRP >> >> and execute *uhd_usrp_probe* seems that fpga is again flashed with NI >> USRP as it contains *only DDCs, DMA and Radio* >> >> *RFNoC blocks*. >> >> >> >> In general I am confused what is a right RFNoC image for setup >> consisting of USRP connected with PC over PCIe interface. >> >> Should I *use XG RFNoC FPGA images*? Are RFNoC images compatible with >> PCIe interface? > > Yeah, but PCIe does reload images on every run. If you specify > fpga=/path/to/rfnoc_image.bit, it'll pick that. > > > -- M > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] X310 - Vivado mig segfaults
I did some more searching and I found this github issue with a workaround: https://github.com/EttusResearch/uhd/issues/103 (begin quote): I hit the same ddr3_32bit build error on Windows: [IP_Flow 19-3475] Tcl error in ::ipgui_ddr3_32bit::updateAllModelParams procedure for IP 'ddr3_32bit'. Loading device for application Rf_Device from file '7k410t.nph' in environment C:/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: floating-point exception Workaround I found is the following: $ cd build-ip/xc7k410tffg900-2/ddr3_32bit/ $ rm mig_a.prj $ cp mig_xc7k410tffg900-2.prj mig_a.prj It looks like tcl does not like mig_a.prj being a link on Windows. (end quote) The build seems to successfully get past the mig however it fails on the "pga" block (much later in the build process): synth_ip: Time (s): cpu = 00:47:50 ; elapsed = 00:55:13 . Memory (MB): peak = 1815.309 ; gain = 1479.445 BUILDER: Adding file from Block Design list: C: pga pga-maintusrp3op ERROR: [Vivado 12-172] File or Directory 'pga' does not exist INFO: [Common 17-206] Exiting Vivado at Mon Jan 29 15:12:30 2018... make[1]: *** [Makefile.x300.inc:111: bin] Error 1 make[1]: Leaving directory '/cygdrive/c/fpga/fpga-maint/usrp3/top/x300' make: *** [Makefile:61: X310_HG] Error 2 I will switch over to the master branch if you think my time will be more productive there? I saw that you are working toward a new release very soon. On Mon, Jan 29, 2018 at 2:52 PM, Martin Braun via USRP-users < usrp-users@lists.ettus.com> wrote: > On 01/26/2018 03:49 PM, Martin K via USRP-users wrote: > > I have Cygwin64 setup in Windows 10 > > Vivado 15.4.2 installed and licensed. > > > > [...] > > Some web searching shows that other people have had trouble with the mig > > failing - on both Windows and Linux, but obviously it works for you > > guys. I appreciate any advice. > > We've had issues like this (not sure if exactly this issue), and > recently saw them again when we updated Vivado (I think). Maybe this is > a Cygwin issue, but maybe not. Which branch are you running? If it's > master, can you update to the latest and try 2017.4? > > -- M > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Martin K. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] X310 - Vivado mig segfaults
On 01/26/2018 03:49 PM, Martin K via USRP-users wrote: > I have Cygwin64 setup in Windows 10 > Vivado 15.4.2 installed and licensed. > > [...] > Some web searching shows that other people have had trouble with the mig > failing - on both Windows and Linux, but obviously it works for you > guys. I appreciate any advice. We've had issues like this (not sure if exactly this issue), and recently saw them again when we updated Vivado (I think). Maybe this is a Cygwin issue, but maybe not. Which branch are you running? If it's master, can you update to the latest and try 2017.4? -- M ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images
On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote: > Hello everyone, > > > > I am just starting to use RFNoC and I am a bit confused with hardware > compatibility for RFNoC development. > > In order to describe my setup I will list items below: > > > > 1. I have NI USRP RIO (equivalent of X310 with integrated GPS module) > > 2. I am connecting it with PC over PCIe interface > > > > I tried to flash USRP with RFNoC *usrp_x310_fpga_RFNOC_XG.bit* image. > However, after I power cycle USRP > > and execute *uhd_usrp_probe* seems that fpga is again flashed with NI > USRP as it contains *only DDCs, DMA and Radio* > > *RFNoC blocks*. > > > > In general I am confused what is a right RFNoC image for setup > consisting of USRP connected with PC over PCIe interface. > > Should I *use XG RFNoC FPGA images*? Are RFNoC images compatible with > PCIe interface? Yeah, but PCIe does reload images on every run. If you specify fpga=/path/to/rfnoc_image.bit, it'll pick that. -- M ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] NI USRP / PCIe interface and RFNoC FPGA images
Hello everyone, I am just starting to use RFNoC and I am a bit confused with hardware compatibility for RFNoC development. In order to describe my setup I will list items below: 1. I have NI USRP RIO (equivalent of X310 with integrated GPS module) 2. I am connecting it with PC over PCIe interface I tried to flash USRP with RFNoC usrp_x310_fpga_RFNOC_XG.bit image. However, after I power cycle USRP and execute uhd_usrp_probe seems that fpga is again flashed with NI USRP as it contains only DDCs, DMA and Radio RFNoC blocks. In general I am confused what is a right RFNoC image for setup consisting of USRP connected with PC over PCIe interface. Should I use XG RFNoC FPGA images? Are RFNoC images compatible with PCIe interface? Kind Regards, Tarik ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] X310 - Vivado mig segfaults
I have Cygwin64 setup in Windows 10 Vivado 15.4.2 installed and licensed. source setupenv.sh --vivado-path=/cygdrive/c/Xilinx/Vivado/ Setting up a 64-bit FPGA build environment for the USRP-X3x0... - Vivado: Found (/cygdrive/c/Xilinx/Vivado//2015.4/bin) - Vivado HLS: Found (/cygdrive/c/Xilinx/Vivado_HLS/2015.4/bin) Environment successfully initialized. $ make X310_HA [cut out a lot of successful operations] BUILDER: Refreshing IP INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'ddr3_32bit'... Loading device for application Rf_Device from file '7k410t.nph' in environment C:/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: floating-point exception CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/xit/instantiation_template.xit': Loading device for application Rf_Device from file '7k410t.nph' in environment C:/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: floating-point exception ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s). ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'ddr3_32bit'. Failed to generate 'Verilog Instantiation Template' outputs: ERROR: [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'ddr3_32bit'. Failed to generate 'Verilog Instantiation Template' outputs: INFO: [Common 17-206] Exiting Vivado at Fri Jan 26 14:44:19 2018... It also failed with the X310_HG target. I don't suspect it would work for any targets. Some web searching shows that other people have had trouble with the mig failing - on both Windows and Linux, but obviously it works for you guys. I appreciate any advice. Thanks! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
