Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Felix, thanks for the catch. That looks like a problem I may have
introduced by accident a few months ago. This PR should fix it, hopefully:
https://github.com/EttusResearch/fpga/pull/47/files
Note I expect this would get merged into master and potentially not
backported to whatever version of uhd-fpga you're using, so I'd recommend
keeping what you have locally if it works for you :D
EJ
On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi EJ,
>
> thank you for your answer! To make my error more traceable, I created a
> new OOT Module and added the default gain block from rfnoc getting
> started.
>
> I also took your advice and looked at the uhd_image_builder.py script. I
> noticed very strange behaviour, because my print statements suggested,
> that the script did not include my makefile.srcs because it first edited
> the path
>
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
>
> As you can see two rfnoc's here hence it did not find the makefile.src in
> /fpga-src. The changes (marked with fgr) in the create_oot_include
> here seem to resolve the issue, hopefully helpful for other people too and
> maybe even a major bug?:
>
> def create_oot_include(device, include_dirs):
> """
> Create the include file for OOT RFNoC sources
> """
> oot_dir_list = []
> target_dir = device_dict(device.lower())
> dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
> target_dir, 'Makefile.OOT.inc')
> incfile = open(dest_srcs_file, 'w')
> incfile.write(OOT_SRCS_FILE_HDR)
> if include_dirs is not None:
> for dirs in include_dirs:
> currpath = os.path.abspath(str(dirs))
> if os.path.isdir(currpath) & (os.path.basename(currpath) ==
> "rfnoc"):
> # Case 1: Pointed directly to rfnoc directory
> oot_path = currpath
> elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
> # Case 2: Pointed to top level rfnoc module directory
> oot_path = os.path.join(currpath, 'rfnoc')
> elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
> # Case 3: Pointed to a random directory with a Makefile.inc
> oot_path = currpath
> else:
> print('No RFNoC module found at ' +
> os.path.abspath(currpath))
> continue
> if oot_path not in oot_dir_list:
> oot_dir_list.append(oot_path)
> named_path = os.path.join('$(BASE_DIR)',
> get_relative_path(get_basedir(), oot_path))
> incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
> if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> #elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs')): # Original
> elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs')): # Anders fgr
> # Legacy: Check for fpga-src/Makefile.srcs
> # Read, then append to file
> # curr_srcs = open(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs'), 'r').read() # Original
> curr_srcs = open(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs'), 'r').read() # Anders fgr
> # curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
> Original
> curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
> print('Searching for Makefile.srcs: ' + curr_srcs) #fgr
> incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
> else:
> print('No valid makefile found at ' +
> os.path.abspath(currpath))
> continue
>
> However 30 minutes later in the build I got the next errror and again have
> no idea what to do. My command was:
>
> ./uhd_image_builder.py gain ddc fft -I
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
> --fill-with-fifos
>
> Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
>
>
> Erros are:
>
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
> has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
> bus_clk_gen/inst/clkout4_buf/O.
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
> radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
> multiple drivers:
>
> ce_reset_sync/reset_double_syn
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hi Brian, thank you for the answer, with your help I was able to successfully build an Image! One last question: Do I need to worry about all those critical warnings that popped up during the build? Seems like a lot to me. Example: CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more evaluation cores that will cease to function after a certain period of time. This design should NOT be used in production systems. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_dq.idelaye2 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. CRITICAL
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi EJ,
>
> thank you for your answer! To make my error more traceable, I created a
> new OOT Module and added the default gain block from rfnoc getting
> started.
>
> I also took your advice and looked at the uhd_image_builder.py script. I
> noticed very strange behaviour, because my print statements suggested,
> that the script did not include my makefile.srcs because it first edited
> the path
>
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
>
> As you can see two rfnoc's here hence it did not find the makefile.src in
> /fpga-src. The changes (marked with fgr) in the create_oot_include
> here seem to resolve the issue, hopefully helpful for other people too and
> maybe even a major bug?:
>
> def create_oot_include(device, include_dirs):
> """
> Create the include file for OOT RFNoC sources
> """
> oot_dir_list = []
> target_dir = device_dict(device.lower())
> dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
> target_dir, 'Makefile.OOT.inc')
> incfile = open(dest_srcs_file, 'w')
> incfile.write(OOT_SRCS_FILE_HDR)
> if include_dirs is not None:
> for dirs in include_dirs:
> currpath = os.path.abspath(str(dirs))
> if os.path.isdir(currpath) & (os.path.basename(currpath) ==
> "rfnoc"):
> # Case 1: Pointed directly to rfnoc directory
> oot_path = currpath
> elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
> # Case 2: Pointed to top level rfnoc module directory
> oot_path = os.path.join(currpath, 'rfnoc')
> elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
> # Case 3: Pointed to a random directory with a Makefile.inc
> oot_path = currpath
> else:
> print('No RFNoC module found at ' +
> os.path.abspath(currpath))
> continue
> if oot_path not in oot_dir_list:
> oot_dir_list.append(oot_path)
> named_path = os.path.join('$(BASE_DIR)',
> get_relative_path(get_basedir(), oot_path))
> incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
> if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'Makefile.inc')):
> # Check for Makefile.inc
> incfile.write(OOT_INC_TMPL)
> #elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs')): # Original
> elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs')): # Anders fgr
> # Legacy: Check for fpga-src/Makefile.srcs
> # Read, then append to file
> # curr_srcs = open(os.path.join(oot_path, 'rfnoc',
> 'fpga-src', 'Makefile.srcs'), 'r').read() # Original
> curr_srcs = open(os.path.join(oot_path, 'fpga-src',
> 'Makefile.srcs'), 'r').read() # Anders fgr
> # curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
> Original
> curr_srcs = curr_srcs.replace('SOURCES_PATH',
> os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
> print('Searching for Makefile.srcs: ' + curr_srcs) #fgr
> incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
> else:
> print('No valid makefile found at ' +
> os.path.abspath(currpath))
> continue
>
> However 30 minutes later in the build I got the next errror and again have
> no idea what to do. My command was:
>
> ./uhd_image_builder.py gain ddc fft -I
> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
> --fill-with-fifos
>
> Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
>
>
> Erros are:
>
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
> has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
> bus_clk_gen/inst/clkout4_buf/O.
> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
> radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
> multiple drivers:
>
> ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
> and
>
> radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
> ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
> ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
> [00:24:46] Current task: DRC +++ Current Phase: Starting
> [00:24:46] Current task: DRC +++ Curren
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hi EJ,
thank you for your answer! To make my error more traceable, I created a
new OOT Module and added the default gain block from rfnoc getting
started.
I also took your advice and looked at the uhd_image_builder.py script. I
noticed very strange behaviour, because my print statements suggested,
that the script did not include my makefile.srcs because it first edited
the path
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
As you can see two rfnoc's here hence it did not find the makefile.src in
/fpga-src. The changes (marked with fgr) in the create_oot_include
here seem to resolve the issue, hopefully helpful for other people too and
maybe even a major bug?:
def create_oot_include(device, include_dirs):
"""
Create the include file for OOT RFNoC sources
"""
oot_dir_list = []
target_dir = device_dict(device.lower())
dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
target_dir, 'Makefile.OOT.inc')
incfile = open(dest_srcs_file, 'w')
incfile.write(OOT_SRCS_FILE_HDR)
if include_dirs is not None:
for dirs in include_dirs:
currpath = os.path.abspath(str(dirs))
if os.path.isdir(currpath) & (os.path.basename(currpath) ==
"rfnoc"):
# Case 1: Pointed directly to rfnoc directory
oot_path = currpath
elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
# Case 2: Pointed to top level rfnoc module directory
oot_path = os.path.join(currpath, 'rfnoc')
elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
# Case 3: Pointed to a random directory with a Makefile.inc
oot_path = currpath
else:
print('No RFNoC module found at ' +
os.path.abspath(currpath))
continue
if oot_path not in oot_dir_list:
oot_dir_list.append(oot_path)
named_path = os.path.join('$(BASE_DIR)',
get_relative_path(get_basedir(), oot_path))
incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
# Check for Makefile.inc
incfile.write(OOT_INC_TMPL)
elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
'Makefile.inc')):
# Check for Makefile.inc
incfile.write(OOT_INC_TMPL)
#elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
'fpga-src', 'Makefile.srcs')): # Original
elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
'Makefile.srcs')): # Anders fgr
# Legacy: Check for fpga-src/Makefile.srcs
# Read, then append to file
# curr_srcs = open(os.path.join(oot_path, 'rfnoc',
'fpga-src', 'Makefile.srcs'), 'r').read() # Original
curr_srcs = open(os.path.join(oot_path, 'fpga-src',
'Makefile.srcs'), 'r').read() # Anders fgr
# curr_srcs = curr_srcs.replace('SOURCES_PATH',
os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
Original
curr_srcs = curr_srcs.replace('SOURCES_PATH',
os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
print('Searching for Makefile.srcs: ' + curr_srcs) #fgr
incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
else:
print('No valid makefile found at ' +
os.path.abspath(currpath))
continue
However 30 minutes later in the build I got the next errror and again have
no idea what to do. My command was:
./uhd_image_builder.py gain ddc fft -I
/home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
--fill-with-fifos
Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
Erros are:
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
bus_clk_gen/inst/clkout4_buf/O.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
multiple drivers:
ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
and
radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
[00:24:46] Current task: DRC +++ Current Phase: Starting
[00:24:46] Current task: DRC +++ Current Phase: Finished
[00:24:46] Process terminated. Status: Failure
Warnings: 1304
Critical Warnings: 40
Errors: 4
Makefile.x300.inc:106: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Verzeichnis /home
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hi Felix, It's tough to debug your specific issues without seeing the whole OOT repo structure, including makefiles, etc. However I regularly use rfnoc with OOT folders successfully and have an example here you might be able to refer to for some hints: github.com/ejk43/rfnoc-ootexample I might suggest trying to check that out and see if you can build with one of those blocks first, then modify for your purposes? Also, one other thing to mention is you might have some luck debugging the uhd_image_builder.py to see where it's going wrong in your case (it's just a python file so it's pretty easy to add debug markers or print statements if you want)... EJ On Sat, Jan 4, 2020, 5:10 AM Felix Greiwe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello again, > > has no one an idea? I have still not managed to get it working.. > I would take any advice! > > Best regards, > > Felix > > > > Hello together, > > > > recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install > > of Kubuntu 18.04 LTS. I followed the instructions from > > https://kb.ettus.com/Getting_Started_with_RFNoC_Development > > and used the Pybombs install. > > > > (I ran into a lot of problems there and had to install a lot of stuff > > manually because most of the commands were not working properly. Maybe > the > > Pybombs Tutorial Section needs an update?) > > > > Finally I managed to install it successfully and the command > > uhd_config_version -- info prints: UHD 3.15.0.0-124-geb448043 > > (I also installed Vivado 2018.3 and added the License which seems to > > work.) > > > > After the install I wanted to validate it by creating an OOT Module and > > OOT Block named noc_block_checkdevprocess.v. I did not edit the Verilog > > Code because I only wanted to know if I was able to build an Image > > properly. > > (I ran the default Testbench too, which worked without errors.) > > > > The command to build my image is: > > > > ./uhd_image_builder.py checkdevprocess digital_gain -t X310_RFNOC_HG -d > > X310 -I /home/lskt/rfnoc-blocks_lskt/rfnoc > > > > with "rfnoc-blocks_lskt" beeing my OOT Module and "checkdevprocess" > beeing > > my custom block. > > (I also tried the paths home/lskt/rfnoc-blocks_lskt/rfnoc/; > > home/lskt/rfnoc-blocks_lskt/; home/lskt/rfnoc-blocks_lskt/rfnoc/fpga-src > ) > > > > Every single time I get the same error message: > > ERROR: [Synth 8-439] module 'noc_block_checkdevprocess' not found > > > [/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] > > > > and I don't know why. > > > > I also tried the the uhd_image_builder_gui.py which did not even pop up > > until I uncommented the Line at row 149. I can see my OOT Block here > after > > adding the Module in the gui, but it prints the same error message as the > > non-gui version. > > > > If you need further information to help please ask. > > > > Any help is appreciated. > > > > Felix > > > > > > > > > > > > ___ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hello again, has no one an idea? I have still not managed to get it working.. I would take any advice! Best regards, Felix > Hello together, > > recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install > of Kubuntu 18.04 LTS. I followed the instructions from > https://kb.ettus.com/Getting_Started_with_RFNoC_Development > and used the Pybombs install. > > (I ran into a lot of problems there and had to install a lot of stuff > manually because most of the commands were not working properly. Maybe the > Pybombs Tutorial Section needs an update?) > > Finally I managed to install it successfully and the command > uhd_config_version -- info prints: UHD 3.15.0.0-124-geb448043 > (I also installed Vivado 2018.3 and added the License which seems to > work.) > > After the install I wanted to validate it by creating an OOT Module and > OOT Block named noc_block_checkdevprocess.v. I did not edit the Verilog > Code because I only wanted to know if I was able to build an Image > properly. > (I ran the default Testbench too, which worked without errors.) > > The command to build my image is: > > ./uhd_image_builder.py checkdevprocess digital_gain -t X310_RFNOC_HG -d > X310 -I /home/lskt/rfnoc-blocks_lskt/rfnoc > > with "rfnoc-blocks_lskt" beeing my OOT Module and "checkdevprocess" beeing > my custom block. > (I also tried the paths home/lskt/rfnoc-blocks_lskt/rfnoc/; > home/lskt/rfnoc-blocks_lskt/; home/lskt/rfnoc-blocks_lskt/rfnoc/fpga-src ) > > Every single time I get the same error message: > ERROR: [Synth 8-439] module 'noc_block_checkdevprocess' not found > [/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] > > and I don't know why. > > I also tried the the uhd_image_builder_gui.py which did not even pop up > until I uncommented the Line at row 149. I can see my OOT Block here after > adding the Module in the gui, but it prints the same error message as the > non-gui version. > > If you need further information to help please ask. > > Any help is appreciated. > > Felix > > > > > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found
Hello together, recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install of Kubuntu 18.04 LTS. I followed the instructions from https://kb.ettus.com/Getting_Started_with_RFNoC_Development and used the Pybombs install. (I ran into a lot of problems there and had to install a lot of stuff manually because most of the commands were not working properly. Maybe the Pybombs Tutorial Section needs an update?) Finally I managed to install it successfully and the command uhd_config_version -- info prints: UHD 3.15.0.0-124-geb448043 (I also installed Vivado 2018.3 and added the License which seems to work.) After the install I wanted to validate it by creating an OOT Module and OOT Block named noc_block_checkdevprocess.v. I did not edit the Verilog Code because I only wanted to know if I was able to build an Image properly. (I ran the default Testbench too, which worked without errors.) The command to build my image is: ./uhd_image_builder.py checkdevprocess digital_gain -t X310_RFNOC_HG -d X310 -I /home/lskt/rfnoc-blocks_lskt/rfnoc with "rfnoc-blocks_lskt" beeing my OOT Module and "checkdevprocess" beeing my custom block. (I also tried the paths home/lskt/rfnoc-blocks_lskt/rfnoc/; home/lskt/rfnoc-blocks_lskt/; home/lskt/rfnoc-blocks_lskt/rfnoc/fpga-src ) Every single time I get the same error message: ERROR: [Synth 8-439] module 'noc_block_checkdevprocess' not found [/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22] and I don't know why. I also tried the the uhd_image_builder_gui.py which did not even pop up until I uncommented the Line at row 149. I can see my OOT Block here after adding the Module in the gui, but it prints the same error message as the non-gui version. If you need further information to help please ask. Any help is appreciated. Felix ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
