[PATCH] RISC-V: Expand subreg move via slide if necessary [PR116086].

Hi, when the source mode is potentially larger than one vector (e.g. an LMUL2 mode for VLEN=128) we don't know which vector the subreg actually refers to. For zvl128b and LMUL=2 the subreg in (subreg:V2DI (reg:V4DI)) could actually be the a full (high) vector register of a two-register group (at

[gcc r15-2337] RISC-V: Work around bare apostrophe in error string.

https://gcc.gnu.org/g:3f2bf415b447a0f6bc424c688b06e1f5946688a0 commit r15-2337-g3f2bf415b447a0f6bc424c688b06e1f5946688a0 Author: Robin Dapp Date: Fri Jul 26 12:58:38 2024 +0200 RISC-V: Work around bare apostrophe in error string. An unquoted apostrophe slipped through when

[PATCH] RISC-V: Work around bare apostrophe in error string.

Hi, an unquoted apostrophe slipped through when testing the recent V/M extension patch. This, again, re-words the message to "Currently the 'V' implementation requires the 'M' extension". Going to commit as obvious after testing. Regards Robin gcc/ChangeLog: * config/riscv/riscv.cc

[PATCH] fold: Allow SSA names in inverse_conditions_p and fold VCOND_MASK.

Hi, In preparation for the maskload else operand I split off this patch. The patch looks through SSA names for the conditions passed to inverse_conditions_p which helps match.pd recognize more redundant vec_cond expressions. It also adds VCOND_MASK to the respective iterators in match.pd. Is

[gcc r15-2301] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:e589ffb6d78881572ddea21df0d9b6c2641d574d commit r15-2301-ge589ffb6d78881572ddea21df0d9b6c2641d574d Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we

[gcc r15-2300] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

https://gcc.gnu.org/g:4cbbce045681c234387d8d56376ea179dc869229 commit r15-2300-g4cbbce045681c234387d8d56376ea179dc869229 Author: Juzhe-Zhong Date: Thu Feb 1 23:45:50 2024 +0800 RISC-V: Allow LICM hoist POLY_INT configuration code sequence Realize in recent benchmark evaluation

Re: [PATCH v2] RISC-V: Error early with V and no M extension.

> That phrasing makes sense to me. It's consistent with the -mbig-endian > sorry message: > > https://godbolt.org/z/oWMeorEeM I seem to remember that explicitly mentioning GCC in an error message like that was discouraged but I might be confusing things. So probably "GCC's current 'V'

Re: [PATCH v2] RISC-V: Error early with V and no M extension.

> It's really GCC's implementation of the V extension that requires M, not > the actul ISA V extension. So I think the wording could be a little > confusing for users here, but no big deal either way on my end so > > Reviewed-by: Palmer Dabbelt Hmm, fair. How about just "the 'V'

[PATCH v2] RISC-V: Error early with V and no M extension.

Hi, now with proper diff... For calculating the value of a poly_int at runtime we use a multiplication instruction that requires the M extension. Instead of just asserting and ICEing this patch emits an early error at option-parsing time. We have several tests that use only "i" (without "m")

Re: [PATCH] RISC-V: Error early with V and no M extension. [PR116036]

> diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc > index 826d552a6fd..eb6c033535c 100644 > --- a/gcc/internal-fn.cc > +++ b/gcc/internal-fn.cc > @@ -5049,7 +5049,8 @@ internal_len_load_store_bias (internal_fn ifn, > machine_mode mode) > } > > /* Return true if the given ELS_VALUE is

[PATCH] RISC-V: Error early with V and no M extension. [PR116036]

Hi, for calculating the value of a poly_int at runtime we use a multiplication instruction that requires the M extension. Instead of just asserting and ICEing this patch emits an early error at option-parsing time. We have several tests that use only "i" (without "m") and I adjusted all of them

Re: [PATCH v3 2/2] Prevent divide-by-zero

> Thanks for the explanation! I have a few clarification questions about this. > If I understand correctly, B would represent the number of elements the > vector can have (for 128b vector operating on 32b elements, B == 4, but if > operating on 64b elements B == 2); however, I'm not too sure what

Re: [PATCH v3] RISC-V: Implement the .SAT_TRUNC for scalar

LGTM. -- Regards Robin

Re: [PATCH v2] RISC-V: More support of vx and vf for autovec comparison

> I have a test. > The backend can't see -0.0 and It becomes 0.0 when translate to gimple. I don't think it should except when specifying -ffast-math or similar. But we don't have a shortcut to load a negative zero, just the positive one. -- Regards Robin

Re: [PATCH v2] RISC-V: More support of vx and vf for autovec comparison

> -(match_operand:V_VLSF 3 "register_operand")]))] > +(match_operand:V_VLSF 3 "nonmemory_operand")]))] Even though the integer compares have nonmemory operand here their respective insn patterns don't (but constrain properly). I guess what's happening with register operand and a

Re: [PATCH] RISC-V: More support of vx and vf for autovec comparison

Hi Demin, > + void add_integer_operand (rtx x) > + { > +create_integer_operand (_ops[m_opno++], INTVAL (x)); > +gcc_assert (m_opno <= MAX_OPERANDS); > + } Can that be folded into add_input_operand somehow? >void add_input_operand (rtx x, machine_mode mode) >{ >

Re: [RFC] tree-if-conv: Handle nonzero masked elements [PR115336].

> Yeah, I think so. I guess for RVV there's a choice between: > > (1) making the insn predicate accept all else values and making > the insn emit an explicit blend between the loaded result > and the else value > > (2) making the insn predicate only accept “undefined” (SCRATCH in >

Re: [RFC] tree-if-conv: Handle nonzero masked elements [PR115336].

> To me this looks like mis-applying of match.pd:6083? > > Applying pattern match.pd:6083, gimple-match-1.cc:45749 > gimple_simplified to iftmp.0_62 = iftmp.0_61 | _219; > new phi replacement stmt > iftmp.0_62 = iftmp.0_61 | _219; > > so originally it wasn't > > iftmp.0_61 = .MASK_LOAD (_260,

Re: [RFC] tree-if-conv: Handle nonzero masked elements [PR115336].

> FTR, my concern & suggestion was: > > I suppose the difficulty is that we might make: > > MASK_LOAD (mask, ptr, some-arbitrary-else-value) > > seem as cheap as: > > MASK_LOAD (mask, ptr, { 0, 0,. ... 0}) > > which definitely isn't the case for SVE (and I'm guessing also >

[gcc r15-1861] RISC-V: Use tu policy for first-element vec_set [PR115725].

https://gcc.gnu.org/g:acc3b703c05debc6276451f9daae5d0ffc797eac commit r15-1861-gacc3b703c05debc6276451f9daae5d0ffc797eac Author: Robin Dapp Date: Mon Jul 1 13:37:17 2024 +0200 RISC-V: Use tu policy for first-element vec_set [PR115725]. This patch changes the tail policy

[RFC] tree-if-conv: Handle nonzero masked elements [PR115336].

Hi, in PR115336 we have the following vect_patt_391 = .MASK_LEN_GATHER_LOAD (_470, vect__59, 1, { 0, ... }, { 0, ... }, _482, 0); vect_iftmp.44 = vect_patt_391 | { 1, ... }; .MASK_LEN_STORE (vectp_f.45, 8B, { -1, ... }, _482, 0, vect_iftmp.44); which assumes that a maskload sets the

[PATCH] RISC-V: Use tu policy for first-element vec_set [PR115725].

Hi, this patch changes the tail policy for vmv.s.x from ta to tu. By default the bug does not show up with qemu because qemu's current vmv.s.x implementation always uses the tail-undisturbed policy. With a local qemu version that overwrites the tail with ones when the tail-agnostic policy is

Re: [PATCH v2] RISC-V: Remove float vector eqne pattern

OK. Thanks for adding the test. Regards Robin

Re: [PATCH V2 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn

OK. Regards Robin

Re: [PATCH V2 1/2] RISC-V: Fix vwsll combine on rv32 targets

> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md > index 6a2eabbd854..29916adb62b 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -1517,8 +1517,7 @@ (define_insn_and_split "*vwsll_zext1_scalar_" >"&& 1" >

Re: [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets

> I did a test run without the subreg condition and it also appears to > work when running on rv32gcv and rv64gcv newlib. Would it be better > to remove the subreg? Yep, if it works, i.e. all tests still pass then let's get rid of it. Regards Robin

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

> Hmm, ok. The bit that confused me most was: > > if (last_needs_comparison != -1) > { > end_sequence (); > start_sequence (); > ... > } > > which implied that the second attempt was made conditionally. > It seems like it's always used and is an inherent part of the

Re: [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets

Hi Edwin, this is OK but did you check if we can get rid of the subreg condition now that we have gen_lowpart? Regards Robin

Re: [PATCH 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn

:00:00 2001 From: Robin Dapp Date: Fri, 31 May 2024 14:51:17 +0200 Subject: [PATCH] RISC-V: Use descriptive errors instead of asserts. In emit_insn we forestall possible ICEs in maybe_legitimize_operand by asserting. This patch replaces the assertions by more descriptive internal errors.

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

> I was looking at the code in more detail and just wanted to check. > We have: > > int last_needs_comparison = -1; > > bool ok = noce_convert_multiple_sets_1 > (if_info, _no_cmov, _src, , , > _insns, _needs_comparison); > if (!ok) > return false; > > /* If there are

[gcc r15-1187] vect: Merge loop mask and cond_op mask in fold-left reduction [PR115382].

https://gcc.gnu.org/g:2b438a0d2aa80f051a09b245a58f643540d4004b commit r15-1187-g2b438a0d2aa80f051a09b245a58f643540d4004b Author: Robin Dapp Date: Fri Jun 7 14:36:41 2024 +0200 vect: Merge loop mask and cond_op mask in fold-left reduction [PR115382]. Currently we discard the cond

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

The attached v3 tracks the use of cond_earliest as you suggested and adds its cost in default_noce_conversion_profitable_p. Bootstrapped and regtested on x86 and p10, aarch64 still running. Regtested on riscv64. Regards Robin Before noce_find_if_block processes a block it sets up an if_info

Re: [PATCH v1] RISC-V: Implement .SAT_SUB for unsigned vector int

Thanks, the patch is OK then. Regards Robin

Re: [PATCH v1] RISC-V: Implement .SAT_SUB for unsigned vector int

Hi Pan, in general LGTM. Would you mind adding the coremark-pro testcase which should be working now, and, was the original reason for doing this? I believe the following should do: extern int wsize; typedef unsigned short Posf; #define NIL 0 void foo (Posf *p) { register unsigned n, m;

[PATCH v2] vect: Merge loop mask and cond_op mask in fold-left, reduction [PR115382].

> Actually, as Richard mentioned in the PR, it would probably be better > to use prepare_vec_mask instead. It should work in this context too > and would avoid redundant double masking. Attached is v2 that uses prepare_vec_mask. Regtested on riscv64 and armv8.8-a+sve via qemu. Bootstrap and

Re: [PATCH] vect: Merge loop mask and cond_op mask in fold-left, reduction.

Just realized I missed the PR115382 tag in the patch... Regards Robin

[PATCH] internal-fn: Force to reg if operand doesn't match.

Hi, despite looking good on cfarm185 and Linaro's pre-commit CI gcc-15-638-g7ca35f2e430 now appears to have caused several regressions on arm-eabi cortex-m55 as found by Linaro's CI: https://linaro.atlassian.net/browse/GNU-1252 I'm assuming this target is not tested as regularly and thus the

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0? > > target = (a == b) ? x : y > target = (a != b) ? y : x > > Are equivalent, even for IEEE IIRC. Yes, that should be fine. My concern was not that we do a canonicalization but that we might not do it for some of the

[PATCH] vect: Merge loop mask and cond_op mask in fold-left, reduction.

Hi, currently we discard the cond-op mask when the loop is fully masked which causes wrong code in gcc.dg/vect/vect-cond-reduc-in-order-2-signed-zero.c when compiled with -O3 -march=cascadelake --param vect-partial-vector-usage=2. This patch ANDs both masks instead. Bootstrapped and regtested

Re: [PATCH v3] RISC-V: Implement .SAT_SUB for unsigned scalar int

LGTM. Let's keep in mind that min/max will save us two insns(?) and a conditional move would save us one. Regards Robin

Re: [PATCH v2] RISC-V: Implement .SAT_SUB for unsigned scalar int

>> When you say other variants are still to be implemented >> does that also include variants for zbb with min/max >> or zicond? > > No, I mean some other forms like branch need the improvement from the > middle end(aka widen_mul). Ah, I see, thanks. Those can save one instruction and we want

Re: [PATCH v2] RISC-V: Implement .SAT_SUB for unsigned scalar int

Hi Pan, > + /* Step-2: lt = x < y */ > + riscv_emit_binary (LTU, pmode_lt, pmode_x, pmode_y); > + > + /* Step-3: lt = -lt */ > + riscv_emit_unary (NEG, pmode_lt, pmode_lt); > + > + /* Step-4: lt = ~lt */ > + riscv_emit_unary (NOT, pmode_lt, pmode_lt); Can we replace step 3 and 4 with

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

> Is there any way we can avoid using pattern_cost here? Using it means > that we can make use of targetm.insn_cost for the jump but circumvent > it for the condition, giving a bit of a mixed metric. > > (I realise there are existing calls to pattern_cost in ifcvt.cc, > but if possible I think

[gcc r15-1061] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:037fc4d1012dc9d533862ef7e2c946249877dd71 commit r15-1061-g037fc4d1012dc9d533862ef7e2c946249877dd71 Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding

[PATCH] RISC-V: Regenerate opt urls.

Hi, I wasn't aware that I needed to regenerate the opt urls when adding an option. For this patch I did it now. I suppose this doesn't require an extra OK but I'm going to wait some minutes before applying still. Regards Robin gcc/ChangeLog: * config/riscv/riscv.opt.urls:

[gcc r15-1043] check_GNU_style: Use raw strings.

https://gcc.gnu.org/g:03e1a7270314800eb33632f778401570e65345bd commit r15-1043-g03e1a7270314800eb33632f778401570e65345bd Author: Robin Dapp Date: Mon May 13 22:05:57 2024 +0200 check_GNU_style: Use raw strings. This silences some warnings when using check_GNU_style

[gcc r15-1042] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:68b0742a49de7122d5023f0bf46460ff2fb3e3dd commit r15-1042-g68b0742a49de7122d5023f0bf46460ff2fb3e3dd Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces

[gcc r15-957] RISC-V: Remove dead perm series code and document.

https://gcc.gnu.org/g:30cfdd6ff56972d9d1b9dbdd43a8333c85618775 commit r15-957-g30cfdd6ff56972d9d1b9dbdd43a8333c85618775 Author: Robin Dapp Date: Fri May 17 12:48:52 2024 +0200 RISC-V: Remove dead perm series code and document. With the introduction of shuffle_series_patterns

[gcc r15-956] RISC-V: Add vector popcount, clz, ctz.

https://gcc.gnu.org/g:6fa4b0135439d64c0ea1816594d7dc830e836376 commit r15-956-g6fa4b0135439d64c0ea1816594d7dc830e836376 Author: Robin Dapp Date: Wed May 15 17:41:07 2024 +0200 RISC-V: Add vector popcount, clz, ctz. This patch adds the zvbb vcpop, vclz and vctz to the autovec

[gcc r15-955] RISC-V: Add vandn combine helper.

https://gcc.gnu.org/g:f48448276f29a3823827292c72b7fc8e9cd39e1e commit r15-955-gf48448276f29a3823827292c72b7fc8e9cd39e1e Author: Robin Dapp Date: Wed May 15 15:01:35 2024 +0200 RISC-V: Add vandn combine helper. This patch adds a combine pattern for vandn as well as tests

[gcc r15-954] RISC-V: Use widening shift for scatter/gather if applicable.

https://gcc.gnu.org/g:309ee005aa871286c8daccbce7586f82be347440 commit r15-954-g309ee005aa871286c8daccbce7586f82be347440 Author: Robin Dapp Date: Fri May 10 13:37:03 2024 +0200 RISC-V: Use widening shift for scatter/gather if applicable. With the zvbb extension we can emit

[gcc r15-953] RISC-V: Add vwsll combine helpers.

https://gcc.gnu.org/g:af4bf422a699de0e7af5a26e02997d313e7301a6 commit r15-953-gaf4bf422a699de0e7af5a26e02997d313e7301a6 Author: Robin Dapp Date: Mon May 13 22:09:35 2024 +0200 RISC-V: Add vwsll combine helpers. This patch enables the usage of vwsll in autovec context by adding

[gcc r15-952] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

https://gcc.gnu.org/g:9781885a624f3e29634d95c14cd10940cefb1a5a commit r15-952-g9781885a624f3e29634d95c14cd10940cefb1a5a Author: Robin Dapp Date: Thu May 16 12:43:43 2024 +0200 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. vwadd.wx and vwsub.wx have the same problem

[gcc r15-951] RISC-V: Do not allow v0 as dest when merging [PR115068].

https://gcc.gnu.org/g:a2fd0812a54cf51520f15e900df4cfb5874b75ed commit r15-951-ga2fd0812a54cf51520f15e900df4cfb5874b75ed Author: Robin Dapp Date: Mon May 13 13:49:57 2024 +0200 RISC-V: Do not allow v0 as dest when merging [PR115068]. This patch splits the vfw...wf pattern so we do

[PATCH] check_GNU_style: Use raw strings.

Hi, this silences some warnings when using check_GNU_style. I didn't expect this to have any bootstrap or regtest impact but I still ran it on x86 - no change. Regards Robin contrib/ChangeLog: * check_GNU_style_lib.py: Use raw strings for regexps. --- contrib/check_GNU_style_lib.py

[PATCH] RISC-V: Add min/max patterns for ifcvt.

Hi, ifcvt likes to emit (set (if_then_else) (ge (reg 1) (reg2)) (reg 1) (reg 2)) which can be recognized as min/max patterns in the backend. This patch adds such patterns and the respective iterators as well as a test. This depends on the generic ifcvt change. Regtested on

[PATCH] ifcvt: Clarify if_info.original_cost.

Hi, before noce_find_if_block processes a block it sets up an if_info structure that holds the original costs. At that point the costs of the then/else blocks have not been added so we only care about the "if" cost. The code originally used BRANCH_COST for that but was then changed to

Re: [PATCH 1/2] RISC-V: add option -m(no-)autovec-segment

On 5/28/24 23:55, Patrick O'Neill wrote: > From: Greg McGary > > Add option -m(no-)autovec-segment to enable/disable autovectorizer > from emitting vector segment load/store instructions. This is useful for > performance experiments. I think the question was raised before but does a vector tune

[PATCH v4] RISC-V: Introduce -mvector-strict-align.

Hi, this patch disables movmisalign by default and introduces the -mno-vector-strict-align option to override it and re-enable movmisalign. For now, generic-ooo is the only uarch that supports misaligned vector access. The patch also adds a check_effective_target_riscv_v_misalign_ok to the

Re: [PATCH v3] RISC-V: Introduce -mvector-strict-align.

>> + /* By default, when -mno-vector-strict-align is not specified, do not >> allow >> + unaligned vector memory accesses except if -mtune's setting explicitly >> + allows it. */ >> + riscv_vector_unaligned_access_p = rvv_vector_strict_align == 0 || > > opts->x_rvv_vector_strict_align

[PATCH v3] RISC-V: Introduce -mvector-strict-align.

Attached is v3 with the discussed changes. It now has -mscalar-strict-align which is an alias to -mstrict-align as well as -mvector-strict-align. Testsuite shows no new regressions on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/riscv-opts.h

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

> * -mstrict-align: Both scalar and vector misaligned accesses are > unsupported (-mrvv-allow-misalign doesn't matter). I'm not sure if > there's hardware there, but given we have systems that don't support > scalar misaligned accesses it seems reasonable to assume they'll also > not support

[PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

> We should have something in doc/invoke too, this one is going to be > tricky for users. We'll also have to define how this interacts with > the existing -mstrict-align. Addressed the rest in the attached v2 which also fixes tests. I'm really not sure about -mstrict-align. I would have hoped

[PATCH] RISC-V: Introduce -mrvv-allow-misalign.

Hi, this patch changes the default from always enabling movmisalign to disabling it. It adds an option to override the default and adds generic-ooo to the uarchs that support misaligned vector access. It also adds a check_effective_target_riscv_v_misalign_ok to the testsuite which enables or

Re: [PATCH] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

The patch is OK from the riscv side. generic-ooo includes fast unaligned access. Regards Robin

[gcc r15-639] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:e0b9c8ad7098fb08a25a61fe17d4274dd73e5145 commit r15-639-ge0b9c8ad7098fb08a25a61fe17d4274dd73e5145 Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores

[gcc r15-638] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:7ca35f2e430081d6ec91e910002f92d9713350fa commit r15-638-g7ca35f2e430081d6ec91e910002f92d9713350fa Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch

Re: [PATCH v6] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

Hi Pan, all in all LGTM. Just insignificant nits. > +void > +expand_vec_usadd (rtx op_0, rtx op_1, rtx op_2, machine_mode vec_mode) > +{ > + emit_vec_saddu (op_0, op_1, op_2, BINARY_OP, vec_mode); > +} > + Do we really need this function? Or do you want it to be a dispatcher for later? If

[PATCH] RISC-V: Remove dead perm series code and document.

Hi, with the introduction of shuffle_series_patterns the explicit handler code for a perm series is dead. This patch removes it and also adds a function-level comment to shuffle_series_patterns. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/riscv-v.cc

[PATCH] RISC-V: Add vector popcount, clz, ctz.

Hi, this patch adds the zvbb vcpop, vclz and vctz to the autovec machinery as well as tests for them. It also changes several non-VLS iterators to V_VLS iterators for consistency. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (ctz2): New

[PATCH] RISC-V: Add vandn combine helper.

Hi, this patch adds a combine pattern for vandn as well as tests for it. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/autovec-opt.md (*vandn_): New pattern. * config/riscv/vector.md: Add vandn to mode_idx. gcc/testsuite/ChangeLog: *

[PATCH] RISC-V: Use widening shift for scatter/gather if applicable.

Hi, with the zvbb extension we can emit a widening shift for scatter/gather index preparation in case we need to multiply by 2 and zero extend. The patch also adds vwsll to the mode_idx attribute and removes the mode from shift-count operand of the insn pattern. Regtested on rv64gcv_zvfh_zvbb.

[PATCH] RISC-V: Add vwsll combine helpers.

Hi, this patch enables the usage of vwsll in autovec context by adding the necessary combine patterns and tests. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/autovec-opt.md (*vwsll_zext1_): New pattern. (*vwsll_zext2_): Ditto.

[PATCH] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

Hi, vwadd.wx and vwsub.wx have the same problem vfwadd.wf had. This patch splits the insn pattern in the same way vfwadd.wf was split. It also adds two patterns to recognize extended scalars. In practice those do not provide a lot of improvement over what we already have but in some instances

Re: [PATCH] internal-fn: Do not force vcond operand to reg.

> OK if that pre-commit CI works out. The CI didn't pick it up, guess it needs to be a bit more explicit. In the meanwhile, however, I managed to catch a short window with > 10G free on gcc185 => Bootstrap and regtest successful on aarch64. Going to push the patch later today. Regards Robin

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

> Can eqne pattern removal patches be committed firstly? Please first make sure you test with corner cases, NaNs in particular. I'm pretty sure we don't have any test cases for those. Regards Robin

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

Hi Demin, are you still going to continue with this? Regards Robin

Re: [PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068].

> I saw vwadd/vwsub.wx have same issue. Could you change them and add test too ? Yes, will do. At first I didn't manage to reproduce it because we seem to be lacking a combine-opt pattern for it. I'm going to post it separately. Regards Robin

Re: [PATCH v1 2/3] RISC-V: Implement vectorizable early exit with vcond_mask_len

Hi Pan, thanks for working on this. In general the patch looks reasonable to me but I'd rather have some more comments about the high-level idea. E.g. cbranch is implemented like aarch64 by xor'ing the bitmasks and comparing the result against zero (so we branch based on mask equality). > +;;

[PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068].

Hi, this patch splits the vfw...wf pattern so we do not emit e.g. vfwadd.wf v0,v8,fa5,v0.t anymore. Regtested on rv64gcv_zvfh. Regards Robin gcc/ChangeLog: PR target/115068 * config/riscv/vector.md: Split vfw.wf pattern. gcc/testsuite/ChangeLog: *

Re: [PATCH v1 3/3] RISC-V: Enable vectorizable early exit test

Hi Pan, > > @@ -4114,6 +4115,7 @@ proc check_effective_target_vect_early_break_hw { } { > || [check_effective_target_arm_v8_neon_hw] > || [check_sse4_hw_available] > || [istarget amdgcn-*-*] > + || [check_effective_target_riscv_v] > }}] > } I believe this should be

Re: [PATCH] internal-fn: Do not force vcond operand to reg.

> What happens if we simply remove all of the force_reg here? On x86 I bootstrapped and tested the attached without fallout (gcc188, so it's no avx512-native machine and therefore limited coverage). riscv regtest is unchanged. For aarch64 I would to rely on the pre-commit CI to pick it up (does

Re: [PATCH] internal-fn: Do not force vcond operand to reg.

> How does this make a difference in the end? I'd expect say forwprop to > fix things? In general we try to only add the masking "boilerplate" of our instructions at split time so fwprop, combine et al. can do their work uninhibited of it (and we don't need numerous (if_then_else ...

[PATCH] internal-fn: Do not force vcond operand to reg.

Hi, this only forces the first comparison operator into a register if it is not already suitable. Bootstrap and regtest is running on x86 and aarch64, successful on p10. Regtested on riscv. gcc/ChangeLog: PR middle-end/113474 * internal-fn.cc (expand_vec_cond_mask_optab_fn):

[PATCH] RISC-V: Add testcase for PR114749.

Hi, this adds a test case for PR114749. Going to commit as obvious unless somebody complains. Regards Robin gcc/testsuite/ChangeLog: PR tree-optimization/114749 * gcc.target/riscv/rvv/autovec/pr114749.c: New test. --- .../gcc.target/riscv/rvv/autovec/pr114749.c | 15

Re: State of risc-v port in the current merge, revert, rinse-repeat commotion

Thanks Vineet! > The dynamic icounts looks sane (vs. Apr 10 snapshot) except for a > regression in x264 which is likely independent of the chaos going on. > > Apr 10 | Apr 23  | >   109f1b28fc94  |  6f0a646dd2fc   | > +-+ > 276,584,692,883

Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for vwcvt"

> (define_insn "@pred_vwsll_scalar" > - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, > vd, vr, vd, vr, vd, vr, ?, ?") > + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr") Just noticed, not a problem of the revert but wasn't that wrong before without the

Re: [PATCH] RISC-V: Add xfail test case for wv insn highest overlap

LGTM. Regards Robin

Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and xfail tests

Hi Pan, > The RVV register overlap requires both the dest, and src operands. > Thus the rigister filter in constraint cannot cover the fully sematics > of the vector register overlap. I'm not sure I'm following. Did we miss something that should have been covered? Like only an overlap on the

[gcc r14-9972] RISC-V: Add VLS to mask vec_extract [PR114668].

https://gcc.gnu.org/g:02cc8f3e68f9af96d484d9946ceaa9e3eed38151 commit r14-9972-g02cc8f3e68f9af96d484d9946ceaa9e3eed38151 Author: Robin Dapp Date: Mon Apr 15 12:44:56 2024 +0200 RISC-V: Add VLS to mask vec_extract [PR114668]. This adds the missing VLS modes to the mask extract

[PATCH] RISC-V: Add VLS to mask vec_extract [PR114668].

Hi, this adds the missing VLS modes to the mask extract expanders. I found a dump scan difficult to create reliably so I just kept the PR's run test case. Regtested on rv64gcv. Regards Robin gcc/ChangeLog: PR target/114668 * config/riscv/autovec.md: Add VLS.

Re: [PATCH] RISC-V: Add initial cost handling for segment loads/stores.

> So where do we stand with this? Juzhe asked it to be rebased, but I > don't see a rebased version in my inbox and I don't see anything that > looks like this on the trunk. I missed this one and figured as we're pretty late in the cycle it can wait until GCC 15. Therefore let's call it

Re: [PATCH v2] RISC-V: Introduce option -mrvv-max-lmul for RVV autovec

LGTM as well. Regards Robin

Re: [PATCH] RISC-V: Introduce option -mrvv-autovec-max-lmul for RVV autovec

Should it really be called autovec-max-lmul? We also use TARGET_MAX_LMUL for builtins etc. Or are we just following LLVM's naming here? Isn't -mrvv-max-lmul sufficient? > PR target/112648 This PR is not really resolved or affected by the

[gcc r14-9366] vect: Do not peel epilogue for partial vectors.

https://gcc.gnu.org/g:226043a4d8fb23c7fe7bf16e485b3cfaa094db21 commit r14-9366-g226043a4d8fb23c7fe7bf16e485b3cfaa094db21 Author: Robin Dapp Date: Wed Mar 6 16:54:35 2024 +0100 vect: Do not peel epilogue for partial vectors. r14-7036-gcbf569486b2dec added an epilogue vectorization

Re: [PATCH] vect: Do not peel epilogue for partial vectors [PR114196].

Attached v2 combines the checks. Bootstrapped and regtested on x86 an power10, aarch64 still running. Regtested on riscv64. Regards Robin Subject: [PATCH v2] vect: Do not peel epilogue for partial vectors. r14-7036-gcbf569486b2dec added an epilogue vectorization guard for early break but

Re: [PATCH] vect: Do not peel epilogue for partial vectors [PR114196].

> r14-7036-gcbf569486b2dec added an epilogue vectorization guard for early > break but PR114196 shows that we also run into the problem without early > break. Therefore remove early break from the conditions. Forgot: Bootstrapped and regtested on x86, aarch64 and power10. Regtested on riscv64.

[PATCH] vect: Do not peel epilogue for partial vectors [PR114196].

Hi, r14-7036-gcbf569486b2dec added an epilogue vectorization guard for early break but PR114196 shows that we also run into the problem without early break. Therefore remove early break from the conditions. gcc/ChangeLog: PR middle-end/114196 * tree-vect-loop-manip.cc

[gcc r14-9345] RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].

https://gcc.gnu.org/g:59554a50be8ebbd52e8a6348a92110af182e1874 commit r14-9345-g59554a50be8ebbd52e8a6348a92110af182e1874 Author: Robin Dapp Date: Wed Mar 6 12:15:40 2024 +0100 RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200]. Three-operand instructions

[gcc r14-9344] RISC-V: Adjust vec unit-stride load/store costs.

https://gcc.gnu.org/g:9ae83078fe45d093bbaa02b8348f2407fe0c62d6 commit r14-9344-g9ae83078fe45d093bbaa02b8348f2407fe0c62d6 Author: Robin Dapp Date: Mon Jan 15 17:34:58 2024 +0100 RISC-V: Adjust vec unit-stride load/store costs. Scalar loads provide offset addressing while unit

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