Thanks Alex.
Hi Matthew,
Any comments?
Thanks,
Arun.
On 7/9/2024 1:42 AM, Alex Deucher wrote:
On Thu, Jul 4, 2024 at 4:40 AM Arunpravin Paneer Selvam
wrote:
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in sit
--
发件人：Felix Kuehling
发送时间：2024年7月10日(星期三) 01:07
收件人：周春明(日月) ; Tvrtko Ursulin ;
dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org ; Dave Airlie
; Daniel Vetter ; criu
抄 送："Errabolu, Ramesh" ; "Christian König"
主 题：
From: Jiadong Zhu
The job's embedded fence is dma_fence which shall not be conversed
to amdgpu_fence. The start timestamp shall be saved on job for
hw_fence.
v2: optimize get_fence_start_time.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 31 --
On 2024-07-08 17:41, David Belanger wrote:
> Always use MTYPE_UC if UNCACHED flag is specified.
>
> This makes kernarg region uncached and it restores
> usermode cache disable debug flag functionality.
>
> Do not set MTYPE_UC for COHERENT flag, on GFX12 coherence is handled by
> shader code.
>
On 2024-07-09 5:30, 周春明(日月) wrote:
>
>
>
>
>
>
> --
> 发件人：Felix Kuehling
> 发送时间：2024年7月9日(星期二) 06:40
> 收件人：周春明(日月) ; Tvrtko Ursulin
> ; dri-de...@lists.freedesktop.org
> ; amd-gfx@lists.freedesktop.org
> ; Dave Airlie ; Da
From: Li Ma
[ Upstream commit c223376b3019a00a0241faea0bc8c966738d1cc5 ]
[Why]
SMU firmware has not supported MALL PG.
[How]
Disable MALL PG and make it always on until SMU firmware is ready.
Signed-off-by: Li Ma
Reviewed-by: Tim Huang
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Sig
On 7/9/24 3:10 AM, Ma Ke wrote:
To avoid reports of NULL_RETURN warning, we should add
otg_master NULL check.
Cc: sta...@vger.kernel.org
Fixes: c51d87202d1f ("drm/amd/display: do not attempt ODM power optimization if
minimal transition doesn't exist")
Signed-off-by: Ma Ke
---
Changes in v2:
-
On 7/9/24 6:41 AM, Linux regression tracking (Thorsten Leemhuis) wrote:
On 30.06.24 01:18, Mikhail Gavrilov wrote:
On Sat, Jun 29, 2024 at 9:46 PM Rodrigo Siqueira Jordao
wrote:
I'm trying to reproduce this issue, but until now, I've been unable to
reproduce it. I tried some different scen
On 6/29/24 5:18 PM, Mikhail Gavrilov wrote:
On Sat, Jun 29, 2024 at 9:46 PM Rodrigo Siqueira Jordao
wrote:
Hi Mikhail,
I'm trying to reproduce this issue, but until now, I've been unable to
reproduce it. I tried some different scenarios with the following
components:
1. Displays: I tried w
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks Alex
-Original Message-
From: Alex Deucher
Sent: Tuesday, July 9, 2024 7:27 PM
To: Khatri, Sunil
Cc: Deucher, Alexander ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v1 3/3] drm/amdgpu: select com
On 7/9/24 06:09, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
enable PSR more quickly for displays that support it.
Signed-o
Makes sense, although the pattern elsewhere is to just start at 1 for
mec. Not sure if it's worth the effort to fix all of those cases up
too.
Series is:
Acked-by: Alex Deucher
On Tue, Jul 9, 2024 at 2:07 AM Sunil Khatri wrote:
>
> GFX ME right now is one but this could change in
> future SOC's
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: amd-gfx On Behalf Of Lazar, Lijo
Sent: Tuesday, July 9, 2024 3:03 PM
To: Slivka, Danijel ; amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Feng, Kenneth
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
> On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
> > Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
> > enable PSR more quickly for displays that support it.
> >
> > Signed-off-by: Hamza Mahfooz
>
On 7/8/2024 7:01 PM, Danijel Slivka wrote:
> Why:
> If the reg mmMP1_SMN_C2PMSG_90 is being written to during amdgpu driver
> load or driver unload, subsequent amdgpu driver load will fail at
> smu_hw_init. The default of mmMP1_SMN_C2PMSG_90 register at a clean
> environment is 0x1 and if value
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx On Behalf Of Danijel
Slivka
Sent: Monday, July 8, 2024 9:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Slivka, Danijel
Subject: [PATCH v2] drm/amd/pm: Ignore initial valu
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
> Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
> enable PSR more quickly for displays that support it.
>
> Signed-off-by: Hamza Mahfooz
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++-
On Mon, Jul 08, 2024 at 04:29:06PM -0400, Hamza Mahfooz wrote:
> We would like to be able to adjust the vblank off delay dynamically for
> a given CRTC. Since, it will allow drivers to apply static screen
> optimizations more quickly and consequently allow users to benefit more
> so from the power
--
发件人：Felix Kuehling
发送时间：2024年7月9日(星期二) 06:40
收件人：周春明(日月) ; Tvrtko Ursulin ;
dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org ; Dave Airlie
; Daniel Vetter ; criu
抄 送："Errabolu, Ramesh" ; "Christian König"
主 题：R
Am 08.07.24 um 21:04 schrieb Alex Deucher:
Use the dev_info/err variants so we get per device logging
in multi-GPU cases.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 21 +++--
1 file changed, 11 insertions(+), 10
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, July 9, 2024 13:17
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Thadvai, Satya ; Chang,
HaiJun ; Shi,
Hi Felix,
Thank you for your email. It has been received and a member of the team will
be in contact as soon as possible. We are usually able to respond to queries
within 1-2 working days.
(If not already given, please let us know your full name, order number, and
purchase date to aid us in
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: amd-gfx On Behalf Of
> jiadong@amd.com
> Sent: Tuesday, July 9, 2024 2:56 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Jiadong
> Subject: [PATCH] drm/amdgpu: set start timestamp of fence in the
23 matches
Mail list logo
