Re: [ARTIQ] DSP gateware

​Thank you for the detailed study Robert. ​ > This setup can -- for example -- generate a two-tone signal at 162 MHz > and 238 MHz by setting f0=157 MHz, f1=5 MHz, f2=81 MHz. The attached > plot has the data and the spectrum from a bit-accurate simulation of > the full FPGA gateware. Units are

Re: [ARTIQ] DSP gateware

Hi Dave, On Mon, Aug 1, 2016 at 5:15 PM, Leibrandt, David R. (Fed) wrote: > 1. I assume this logic would be followed by some sort of digital filter to > remove the unwanted Nyquist images. Have you thought about how good of > suppression you might be able to achieve,

Re: [ARTIQ] DSP gateware

On Mon, Aug 1, 2016 at 3:59 PM, Jonathan Mizrahi wrote: > I have one question, just out of curiosity: What is the motivation of > linking two "buddy" channels in the way you described, with the b and c > flags to turn these on and off? What application uses this feature? A pair

Re: [ARTIQ] DSP gateware

Hi Robert, This is a nice writeup. A couple questions for now: 1. I assume this logic would be followed by some sort of digital filter to remove the unwanted Nyquist images. Have you thought about how good of suppression you might be able to achieve, and at what FPGA resource and phase

Re: [ARTIQ] DSP gateware

Hello, to fuel the discussion and planning of the smart arbitrary waveform generator requirements for the different applications, I did another extended design study for the proposed ARTIQ/Sayma DSP gateware and signal flow, looking at actual signal quality, resource usage and possible

Re: [ARTIQ] DSP gateware

On Fri, Apr 1, 2016 at 1:09 AM, Slichter, Daniel H. (Fed) wrote: >> And a 16 ns pulse would be just about 20 samples. Why would you want to >> describe that using ~4 spline knots each being maybe 16 times 16 bits in >> data. >> If you need the full bandwidth, the idea

Re: [ARTIQ] DSP gateware

> to allow for FPGA selection and to rush the funding I have done a design > study and implemented a basic DSP output channel for the ARTIQ DSP > hardware. A 1.25 GS/s, 16 bit, "smart" channel pair would do > > o0 = u0 + i0 * a0 * cos(f0 * t + p0) + q1 * a1 * sin(f1 * t + p1) > o1 = u1 + q0 * a0

Re: [ARTIQ] DSP gateware

Yes, but for such speed you don't need to match better than several mm. Greg On 31 March 2016 at 13:51, Robert Jördens wrote: > On Thu, Mar 31, 2016 at 8:51 AM, Florent Kermarrec > wrote: > > When choosing between Artix7 or Kintex7 you also have to

Re: [ARTIQ] DSP gateware

Hello, When choosing between Artix7 or Kintex7 you also have to consider that Artix7 only have HR IOs which mean they don't have ODELAYE2 primitives and we are currently using them in the actual DDR PHY for leveling. Also when choosing XC7A200T you will stuck to this FPGA on your board because