Re: [casper] NIC tuning and IRQ binding : Regarding

> I think modern Linux network drivers use a "polling" approach rather than > an interrupt driven approach, so I've found IRQ affinity to be less > important than it used to be. This can be observed as relatively low > interrupt counts in /proc/interrupts. The main things that I've found > benefi

Re: [casper] packet capture

Use a NIC that can do dpdk: http://dpdk.org/doc/nics then look on the web for dpdk packet capture utils. David On 30 June 2016 at 10:30, Andrew Siemion wrote: > Hi Louis, > > We found this paper quite useful: > > http://www.ieee-hpec.org/2014/CD/index_htm_files/FinalPapers/95.pdf > > Cheers, >

Re: [casper] Roach2 QDR

A small chip-in - QDR doesn't work below 120 MHz: http://www.cypress.com/?id=4&rID=31542 Regards On 10 March 2015 at 22:17, Matt Strader wrote: > Hi Jack, > > Thanks for your reply. I think I understand better what's going on. I was > thinking in terms of 64-bit words that get written or read

Re: [casper] Roach2 i2c read/write failures

This problem is likely the FTDI not being configured to tristate the IIC pins on reset, hence they are likely driven. This may be weakly enough that IIC open drain might work, or possibly some are configured to tristate and other aren't, or the config is random - just a thought.

Re: [casper] Fault LED

Hi all - all these sensors can have their fault outputs masked in software; either using linux drivers or in uboot. The faults also go away when you read the sensor values (if I remember correctly); uboot has a sensor command which should do this. Either have a look at the uboot code or lmsensors f

Re: [casper] Bidirectional IO?

Hi All. The solution here is a new type of gpio pcore which has three gateway ports: gpio_o, gpio_i and gpio_oe. Currently there are two gpio pcores; one for in and one for out. David

Re: [casper] Shared BRAM yellow block

Hi Glen. We've also been experimenting with adding TIG (timing ignore) statements to > the timing constraint file so that things like shared registers are not > constrained to meet timing, since it shouldn't make much difference. This > is not yet commonly done though. > > I would be very nervous

Re: [casper] ROACH 2 GPIO

Hi Nimish. > Is there any documentation for ROACH 2 specific GPIO interface? If not, can > someone throw light on how to configure the GPIO yellow block for ROACH 2. I guess there is no documentation on R2 interfaces at the moment. Something equivalent to: https://casper.berkeley.edu/wiki/ROACH_F

Re: [casper] UDP problem

Hi Rick > I have a design which uses the TenGbE core (version 1) and sends out 8kB > packets. It works fine and we achieve 6Gb/s throughput which is > plenty. Recently i made a change to send a short packet with some timer > data following all of the big packets. This short packet contains just

Re: [casper] Roach I Board Power Requirements

Hi Joseph. I guess I could comment on the power management side. > *  Since we have two Roach Boards in close proximity, could we power them > both from one larger ATX supply? I think it is possible to gang two roaches on one supply. Just remember whatever scenario you choose, the roach will exp

Re: [casper] Roach IIc

Hi Patrick. > The team at the Green Bank NRAO has opted to use IIc on the ROACH board > (ROACH1 for the short term, but ROACH2 in the future).  Does anyone have > experience with IIc on ROACH, primarily from the software side? First up; are you using IIC driven from the PPC or the FPGA? If you p

Re: [casper] Roach clocking question

Hi Rick > the FPGA.  I gather that the software registers are resynch'ed to the fabric > clock; is there a way to defeat this resynching, or some other option for > switching clocks?  It'd be trivial in Verilog, but I don't see how to do it > in Simulink. As you said, all the Simulink signals are

Re: [casper] I2C and SPI on roach {I,II}

> What voltage levels are on the IIC bus on R and R2? They are both 3v3. > Thanks, David. My pleasure.

Re: [casper] I2C and SPI on roach {I,II}

Hi John. > We have a need for an I2C *or* an SPI port on ROACH 1 and 2. There are > actual headers on R1 that say "SPI" and "IIC". Are these attached to the > PPC? Is there any driver support for them? These do attach to the PowerPC. There are two separate ports on R1, labelled IIC and SPI. Th

Re: [casper] Accessing SMA clock inputs and DCM?

Hi Suraj/Jon. > 0) Sacrifice a goat to the EDK gods so that they will allow you to complete > in a reasonable amount of time. > > Hah. To get EDK to work you may need to go bigger. Perhaps a few cattle or a first-born. hehe. It's not that bad, just copy the way another block does it. Monkey see

Re: [casper] ROACH clocks and chassis setup

Hi Matt. > What is the CHS_LED1 signal ? > This is the red LED below the green/power LED on the front of > the iStar 1.3U chassis. > In the recent past we've started to see a couple of systems > where this LED turns on for some reason. > > The schematics show it connects to the D1 pin of the Actel

Re: [casper] mmcboot with updated kernel

page. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] Low level design on a Roach board

Hi Aziz. > Now I just need to find how to program the FPGA. One option to create a BOF > file using mkbof, I tried that but I got an error. I think its because I do > not have a valid core_info.tab file. I just used the one from ROACH_BASE. This is how you make a bof file: (From xps_library/gen_x

Re: [casper] Low level design on a Roach board

Hi Aziz. > I want to use a Roach board (one with virtex5 FPGA) to test some VHDL > designs and I’m not using Simulink, matlab, XPS . To do so I need to know You could start with this project: https://casper.berkeley.edu/svn/trunk/roach/gw/roach_bsp/ It is a verilog project we use to test the RO

[casper] Updated linux kernel for ROACH

also updated the latest version wiki page: https://casper.berkeley.edu/wiki/Latest_version Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] Sample design for ROACH DRAM and CPU

ibility with the others DIMMs. They seem to add an extra column address bits, which would lead to dead spots if the memory on the supported DIMMs. Hopefully this clears things up a bit and I haven't been talking rubbish! Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-

Re: [casper] Roach questions

ous FIFO with the associated clock on the input and the application clock on the output. Regards, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] casper.berkeley.edu hacked

txn': Permission denied Also mantis appears to be broken. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] PlanAhead and broken borph executables

Hey Billy. > By "broken", i mean: i can program the fpga, but all the registers read > out zero; if i write a register, it continues to read back zero. I would just check that you aren't running into the "read-back all zero's" issue. Refer to this email: http://www.mail-archive.com/casper@lists.

Re: [casper] Possible 10gbe bug

Hi Jon. > This is a known problem and I don't believe anybody's working on a fix. There > is a slight complication in that the core uses multiple clock domains so > there is potential for race conditions during reset at clock boundaries if > this is not handled properl

Re: [casper] Roach CPLD Revision

time and stored in the design. This is an artifact created when source other than the CPLD stuff changes in the repository. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] Roach 1: QDR to reference designator mapping

Hey Henry. I'm sending this from my phone, so apologies for the brevity. I suspect the test bitstream is old. I don't have the version numbers at hand now. I'll mail tomorrow. The NEC and ISSI qdrs exposed a bug in the controller that caused cal to fail. The dll reset was screwy. This was fixed ju

Re: [casper] 10 gbe mysteriously disabled?

Hi Jon. I would check the 10Ge link status register. It sits at an offset of 0x24 in the 10Ge register. It should be equal to 0x7e or 0x7c. If it equals one of these values the controller and link are working fine. Has this same bitstream worked on the same board before? I have on rare occasions

[casper] ROACH-2 prototypes working well

appen at the regular ROACH telecon time. I'll post these details a little later. Kind regards, David -- David George Karoo Array Telescope Tel: +27 11 442-2434

Re: [casper] U-boot, DTT: 1 FAILED INIT

Hi Luis. This looks distinctly as if a AD7414-1 has been populated instead of the AD7414-0. I see you have a device that has i2c address 0x4D which is what would happen if the -0 and -1 were swapped. You can query the device manually by running the following from uboot: i2c md 4d 0 1 What you sho

Re: [casper] tut2 10gbe not configuring

Hi Andrew. *sigh* > > > > It creates a tap interface, which is of dubious value. (Does anyone > know which packets received on 10gbe are passed along to the tap > interface? It better not be a lot of them, because there's no way > that the PPC could keep up at full speed.) > The 10Ge control

Re: [casper] katADC, ISE/SysGen10.1 compatible?

Hey Jason (and CASPER) > FWIW, it looks like ROACH2 will start using 12.x tools so it might be a good > idea not to fall too far behind the development versions. ROACH-2 will start out using the 11 toolflow. A whole lot of work is required to get things moved over to the 12 and 13 tools. We will

Re: [casper] katADC, ISE/SysGen10.1 compatible?

Hi Luis. > I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo, > using FIFO Generator v4.3 and selecting the options according to the original > XCO files. As you have worked out, the FIFO netlists were generated using ISE 11 tools, making them incompatible with 10.1. Re

[casper] ROACH 2 Wiki page updated

Hi All. I have updated some of the info on the ROACH 2 wiki page: http://casper.berkeley.edu/wiki/ROACH2 More importantly I have added some pics too. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] Roach QSH-DP connector pin number and roach ucf pinout name

d. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

[casper] ROACH 2: it exists

have also uploaded a video of the board in action for your enjoyment. You can view the video directly here: http://casper.berkeley.edu/wiki/images/d/d1/Roach2_knight_rider.mpg Expect more updates on the casper lists and the wiki soon. All the best, David -- David George Karoo Array Telescope Tel:

Re: [casper] RMSPEC Project

Hi Andrea. Glad you got it working. > I think there are still something to manage because the output plot seems > to be just a part of 1 Million Channels and I got many 'udp > over/underflow' warning messages but for today I'm very happy. If you are running linux it help to increase the size of

Re: [casper] RMSPEC Project

le with the dram, tie all the inputs to 0's and enable the cpu interface. You should then be able to access the memory from the dram_memory register. Hopefully we can help you sort out this problem. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] RMSPEC Project

d the time to put polish on the design, but I would be happy to help you bring it back to life. Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] ROACH qdr latency question

if rd_en is high > at cycle 0, the data is available at cycle 10). That doc was written a while ago and has slipped out of sync with the current state of the code. The latency is 10. Regards, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] PAR could not meet all timing constraints.

e toolflow (or I suppose a missing feature) as this could very comfortably be done automatically. I'll file a bug report on this and it will probably be fixed soon. Hopefully I'm correct in understanding the problem and have helped ease your mind about it too. Cheers, David George

Re: [casper] OPB address overlap on ROACH

mit is imposed so you dont overlap the qdr (which sits at 0x200) Hopefully this solution works and doesn't affect your sensibilities;) Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

[casper] ppc440epx debugging breakthrough

t hunt me down... Cheers, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] How to disable the 'bee_xps' timing check?

wont cover here. Once you have identified the problem block you need to adjusting the latency for the primitives that are causing the timing problem. Good luck. Kind regards, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

Re: [casper] ROACH bootstrap configuration info (fix for read back all '0's)

ome time. (when I can get git to work) Kind regards, David -- David George Karoo Array Telescope Tel: +27 11 442-2434 Email: david.geo...@ska.ac.za

[casper] Sporadic ROACH Power-up issue

the pulse width and makes the part behave as it should. You can test whether this is indeed the issue affecting your ROACH by pushing the chassis reset button. If the behaviour returns to normal, then you should change the cap. Regards, David -- David George Karoo Array Telescope Tel: +27 21 531

Re: [casper] .bof generation problems

e thing I've noticed is that sometines mkbof creates a >>> file that >>> is executable and sometimes it doesn't and I have to manually set >>> it as >>> executable.  Is this a sign that maybe it's quitting early? >> >> I don't know, but I agree that it sounds fishy. >> >> Dave > > -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

Re: [casper] ROACH bootstrap configuration info

erspace, rather than parsing the kernel logs. I would think sysfs entries would be ideal, but this would require real work. Cheers, David -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

Re: [casper] ROACH bootstrap configuration info

http://casper.berkeley.edu/mantis/view.php?id=3 It is a pretty serious problem and I'll try to find time in the next few weeks to zap it. The FPGA should be able to handle the 83 MHz bus. The real headache is that it did at some point. Cheers, David -- David George Karoo Array Telescope Tel: +27 21 531-

Re: [casper] GPU Spectrometer

r could have been replaced just a DRAM vector accumulator. Also lots of slices could be freed up by using DSPs. The other bonus is you would clock your FPGA 50 Mhz slower. I think you could comfortably do dual-pol with 2 ROACHs. Cheers, David -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

Re: [casper] ROACH File I/O Bottleneck

Hi All. Just a few comments on bus performance. The processor bus is 16 bits at 66 MHz (or 83), so the theoretical maximum is 133 MB/s. There are 3 cycles bus overhead per transaction (for registering etc in FPGA) and an extra two or so for for accessing the register/bram. So that is roughly a bu

Re: [casper] Optimized software registers

hanks, > Henry > > > On 4/19/2010 8:26 AM, David George wrote: > >> Hi Aaron. >> >>Nice work! Are there any tantalizing details you might be able to >>pass along as to what changes made the difference? I always like the >>lessons-learned section

Re: [casper] Optimized software registers

its). I'm not sure that these features were ever used and are definitely not required for BORPH. I think that the registers are now as simple as they could be. Cheers, David > > On Mon, Apr 19, 2010 at 7:34 AM, David George > wrote: > > Greetings All. > > I

[casper] Optimized software registers

to 25 slices (2.9x less). This should help out with utilization if you use a lot of software registers (eg the packetized correlator). These changes apply from svn revision 2945. Cheers, David -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

Re: [casper] IOB conflict between ADCs and GPIO banks

out mixed voltage levels on a single bank. This is now fixed in SVN. Cheers, David -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

[casper] Roach II schematics

Hi all. To those who may be interested, you can grab a prelim version of the schematics here: http://casper.berkeley.edu/svn/roach2/elec/roach2/schematic/roach2_0_0.pdf -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

[casper] roach II design review docs

h2/doc/blockdiagram/roach2_block_diagram0.4.pdf ROACH II Design Review presentation: http://casper.berkeley.edu/svn/roach2/doc/review/ROACH%20II%20Review.pdf Cheers, David -- David George Karoo Array Telescope Tel: +27 21 531-7282 Email: david.geo...@ska.ac.za

Re: [casper] filesystem update

al console. warning: `ntpd' uses 32-bit capabilities (legacy support in use) and then the boot process freezes. I've repartitioned and rebuilt the filesystem as ext3 and then simply copied (cp -rp) over the files as i've done on other working usb sticks. Any suggestions? Tha

Re: [casper] interrupt the booting process

edure. > Or is there any way I can clear the uboot environment without > booting into the uboot. > > -- > Zhiwei Liu > > > > > > -- > Zhiwei Liu -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

Re: [casper] Reference to non-existent field 'clock_loc'

'ngc_config',ngc_config); xlsetparam(xsg_blk, 'synthesis_language', 'VHDL'); Fixes the problem for me but causes the Xilinx block to take a quite a bit longer to update. I would be interested if this solves it for anyone else. Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

[casper] MSSGE 11.3 weirdness: Undefined variable "com" or class

Hi All. It appears that if sysgen crashes enough it seems to unload itself for some reason. If you see this error: ??? Undefined variable "com" or class "com.xilinx.sysgen.XFixJavaLoader.setClassLoader" Try running xlAddSysgen(getenv('XILINX_DSP')) Cheers,

Re: [casper] Xilinx MAXDELAY constraint compiler bug

ld both work. But they don't. For some reason, as you have experienced, some net get the constraint and some get 0ns. I'm almost 100% that this is a xilinx bug. Hopefully this helps. Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-

Re: [casper] I2C driver

rface, designed to handle high latency (tcpborphserver). There is some documentation at: http://casper.berkeley.edu/svn/trunk/mlib_devel_10_1/xps_lib/pcores/kat_iic_controller_v1_00_a/doc/ Currently it is in no way integrated into the toolflow. Cheers, David -- David George Digital Design Eng

Re: [casper] ROACH clocks and chassis setup

connector in the corner. You just need to follow the silkscreen labels. The only gotcha is that you need to connect the power switch to CHS_SW not PWR. Hopefully this stuff will be documented properly. Some day. Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27

Re: [casper] The Roach GPIO error in casper library

ol the direction buses of the GPIO using the gpioa_oe_n and gpiob_oe_n output enables signals. So setting gpioa_oe_n to '0' (active low) will set the whole gpioa bus to outputs and '1' to inputs. Regards, David -- David George Digital Design Engineer Karoo Array Telescope Tel:

Re: [casper] Slow HD write speed

system isn't mounted 'sync'. Regards, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

[casper] A revision control library block for your application model file

tortoiseSVN to your path in your startup batch (.bat) file. I adding this to mine: set RCS_BIN="C:\Program Files\TortoiseSVN\bin" set PATH=%RCS_BIN%;%PATH% I will try to add something equivalent for the mlib libraries. Hopefully this will help people keep track of their versions.

[casper] Using mlib_devel_10_1 with Matlab 2008b & ISE 11.3 on 64-bit Linux

far) is the new draconian licensing for both Matlab 2008b and ISE 11.3. I have started a wiki page which contains information on installing and running system generator on Linux: http://casper.berkeley.edu/wiki/Linux_xps Cheers, David -- David George Digital Design Engineer Karoo Array

Re: [casper] Using "ten_GbE_v2" above 120MHz...

ee slots in the TX FIFO (I think it is actually more, but rather be safe). This means you have some time to back-off your tx state machine and don't need to cause undue timing hazards. Rate matching is sometimes the easiest, but won't get you maximum performance. Cheers, David George --

Re: [casper] More Versatile 10Ge Block(s)?

conceivable to change the user bit width to any multiple or factor of 64 and use multiplexors internally to make the 64 bit for the 10ge interface. However, this function can be more easily and flexibly done in the application interface using the the application 'data valid' signal. Regards

Re: [casper] PowerPC U-Boot Configuration

right. Cheers, David > Dear David > > You are right. > I change another DDRII ram, it works!!! > Before this ROACH was broken, this DDRII is OK... > After all, thanks for your help very much. > > Regards A-Hsin > > - Original Message - From: "David George"

Re: [casper] 10 GbE Xilinx core

ilinx licensed cores? And if so, which one? Thanks, Laura -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

Re: [casper] PowerPC U-Boot Configuration

Hello again... > I try the mac file > http://casper.berkeley.edu/svn/trunk/roach/production/test_software/roach_testing/macraigor_macros/loadram_rinit_auto.mac > > it works. > But the ROACH can't complete the whole uboot process. > The screen only shows the message as follows: > ---

Re: [casper] PowerPC U-Boot Configuration

ind the latest file in: http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/uboot/ You should have uboot running after the xmodem transfer completes. Cheers. -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

Re: [casper] ROACH file copy failure

XPS_ROACH_base\implementation folder. Any ideas? Laura -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

Re: [casper] Booting problem

http://casper.berkeley.edu/wiki/Roach_getting_started Cheers. -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

[casper] Roach MMC/SD support

ate) which will try to boot linux off an attached mmc/sd card. Just remember to install the latest kernel in uboot and install your etch filesystem on an ext2 formatted partition mmc/sd card. (note: you must use the first primary partition). Cheers. -- David George Digital Design Engineer Ka

[casper] Updated Linux Kernel

to work you will need to reprogram your CPLD with the latest binary using a Xilinx programmer. The latest binary sits at: casper_svn: roach/gw/binaries/roach_cpld/roach_cpld_8_0_1588.jed I hope this solves your problem. The MMC documentation is a tad thin. (Read non-existant:p) Cheers. -- Da

Re: [casper] ADC initiate software

Hi Homin. I have read the VHDL code as you specified in last email. But i still can't find there is parallel to 3-wire serial mechanism in that file. That's because it is sneakily written in verilog; There are two parts to the opb_adc_controller. The first is the OPB interface, which has al

Re: [casper] Virtex 5 Power Consumption Measurements

d in the overall power measurement. I think all those with Roach interests would be interested in your results, so best of luck! Regards, David George

Re: [casper] ADC initiate software

Hi Homin. The ROACH iADC is 'automatically' set up in gateware, have a look at the casper svn at: mlib_devel_10_1/xps_lib/XPS_ROACH_base/pcores/opb_adccontroller_v1_00_a At the time this was done BORPH wasn't quite ready and a software-free configuration mechanism was required. Currently the

Re: [casper] Virtex 5 Power Consumption Measurements

ou program the FPGA, which is what we did here. Hope this helps. Regards -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

Re: [casper] SPI driver

e_v1_01_a/ With this you can configure your adc via borph, or uboot (using the mw and md commands), when your FPGA is programmed. Regards, David George -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo.

Re: [casper] How to read and write ADC register

t the yellow block guide: http://casper.berkeley.edu/wiki/How_to_make_a_%22yellow%22_block Regards, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

[casper] A useful tool for making timing

Hi All. This might help 10.1 users with timing problems who are trying to tweak map and par settings. I've recently come across a tool which will run your fpga implementation several times with different map and par settings. You can run several builds simultaneously, useful if you have a mu

Re: [casper] The max frequency of DD2 DRAM of ROACH

3 MHz. Only these options are valid, other values will default to 266 MHz. 266 MHz is a safe options that seems to compile happily, I have run into timing problems with 300 MHz before and 333 MHz is ambitious to say the least. Cheers -- David George Digital Design Engineer Karoo Array Telescop

Re: [casper] maximum 10 GbE packet size

A note to all those who are interested in or are using the 10Ge V2 core, it now supports frame sizes of 8704 bytes, and will resolve the issues discussed earlier in this thread. These changes apply from CASPER SVN revision 2019. Cheers, David

Re: [casper] maximum 10 GbE packet size

with packet sizes up to 1100x64b. But this was a long time ago. So this might work for you, but YMMV. The old core can do 16k (less a few) packets, hence the high bram utilization. Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 2

Re: [casper] problem of ADC 1.1 card with Roach

y problem? I think, basically, the problem is the ADC chip > is not configured correctly. I agree. As before I suggest you rebuild your design with an up-to-date svn. I will build a basic adc design to test the toolflow and see if I have these problems. (I'm off sick so it won't be to

Re: [casper] problem of ADC 1.1 card with Roach

e ADC card with Roach? I been using the iADCs with ROACHs for about 7 months. Good luck. Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

[casper] A new 10Ge Controller (ten_Gbe_v2)

at http://casper.berkeley.edu/wiki/Ten_GbE_v2 The software interface remains the same. The core is still very green and equires a bit more testing. It would be great if some CASPER folk with ROACHs would get their hands dirty. Cheers, David -- David George Digital Design Engineer Karoo Array Teles

Re: [casper] Keeping DRAM from showing up in BORPH

interfaces to do so take up a fair amount of resources. Is there any (not too painful) way to remove those interfaces to free up the resources? Thanks, Glenn -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.

[casper] KAT XAUI

(other than the fact it may be a tad green). Please feel free to test it! Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

[casper] DRAM on ROACH

Hi Wan. We use the Xilinx Memory Interface Generator (MIG) 2.3 through COREGEN to generate our controller. The generated code is in the CASPER svn at: mlib_devel_10_1/xps_lib/XPS_ROACH_base/pcores/dram_controller_v1_00_a/hdl/verilog Regards, -- David George Digital Design Engineer Karoo

[casper] ROACH BORPH/MSSGE toolflow update

ifo_out1 sh_reg_outsys_monitor sys_scratchpad r...@roach:/proc/22/hw/ioreg# echo "1234" >> sh_reg_in r...@roach:/proc/22/hw/ioreg# cat sh_reg_out 04D2 r...@roach:/proc/22/hw/ioreg# Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel:

[casper] 10.1 dev: ROACH ADC and 10GE Auto-configuration

allow the possibility of zero-config designs. Regards, David George (note: the 10ge pre-configuration is also implemented on iBOB) -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za

Re: [casper] the recapture bits are lost in ADC interface

work without support software to configure the ADC (currently there is no simple way of configuring the ADCs) Regards, David George -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.

[casper] Resolved: bug report -- opb_adccontroller_v1_00_a -- user_logic.vhd

to ensure minimum skew attribute iob of adc1_ddrb_reg : signal is "true"; ------- -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.