Hi Jonathan and all:
Thanks of inform me the bug that is the exact fault caused the malfunction.
We just had a good luck while running Rev 1, turned out we didn't pay
attention to it.
So, please check the R104 and R105 if you are using the 5G adc.
cheers
homin
On Fri, Apr 19, 2013 at 11:02 AM
Hi Homin,
One other thing to check is the resistor locations R104 and R105.
-->R104 should be unpopulated.
-->R105 should be populated with 0 ohm.
When checking this note that the silkscreen markings are quite ambiguous. So
identify R104 explicitly by noting that one side of it goes to pin 7
We are just using the adc5g yellow block from ska-sa/mlib_devel, which i
think is the same as that in the sma-wideband/mlib_devel
Glenn
On Apr 18, 2013 10:27 PM, "Homin Jiang" wrote:
> Dear Rurik:
>
> I downloaded the library from github/ska-sa at Jan 21,2013.
> Could you specify where is the flo
Dear Rurik:
I downloaded the library from github/ska-sa at Jan 21,2013.
Could you specify where is the floating reset line ? that might give me
some hints.
Dear Mark and Glenn:
Could you share me what you have done ? That might save me couple of days.
cheers
homin
On Thu, Apr 18, 2013 at 11:
Hi Homin,
What version of the yellow block are you using?
We had an issue with the clock not coming through due to a floating
reset line that was not being driven. This was fixed a while ago on
sma-wideband/mlib_devel and I believe has also been merged into the main
casper-astro repository.
> Hi
>
> Thanks of prompt response
> I have compared the schematics of both versions . The clock pins are kept
> the same.
> I compiled the bof files using the rev 2 ucf file.
Hi Homin.
We are successfully using the ASIAA 5 GS/s ADC and Rev 2 roach together
using the ADC clock input. Maybe Glenn
Hi
Thanks of prompt response
I have compared the schematics of both versions . The clock pins are kept
the same.
I compiled the bof files using the rev 2 ucf file.
Homin
Henno Kriel 於 2013年4月18日星期四寫道:
> Hi Homin
>
> There was a change to the routing from the ZDOK pins to the FPGA from rev1
> t
Hi Homin
There was a change to the routing from the ZDOK pins to the FPGA from rev1
to rev2.
Are you still running a design that was compiled for rev1?
Regards
Henno
On Thu, Apr 18, 2013 at 2:22 PM, Homin Jiang wrote:
> Hello:
>
> After couple of tests, we found that the ADC clock signal is no
Hello:
After couple of tests, we found that the ADC clock signal is not able enter
to the ROACH2 Rev 2. We physically measure the clock pin on ZDOK (F19,F20)
of one 5G adc board which was plugged into Rev 1 and then Rev 2. In the Rev
1, there is clock signal, but no signal in the Rev 2.
4 of ROAC
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