Hi Paul,
I believe the placement cost table is the parameter you want to
change (See http://www.xilinx.com/support/answers/35534.html).
You should be able to change this and other compile parameters in
xps_base/XPS_ROACH[2]_base/etc/fast_runtime.opt
You might find that you get on better changing
On 01/30/2014 07:33 AM, Jack Hickish wrote:
Hi Paul,
I believe the placement cost table is the parameter you want to
change (See http://www.xilinx.com/support/answers/35534.html).
You should be able to change this and other compile parameters in
xps_base/XPS_ROACH[2]_base/etc/fast_runtime.opt
I've toyed with Planahead a bit, and quickly found I was in way over my
head. Could you recommend a good starting point for learning this tool?
I'm sure you've found the planahead user guide, which is a bit of a
documentation behemoth, but useful if you have a vague idea of what
setting you're
wow. Thanks a lot Jack!
Paul
On 01/30/2014 10:15 AM, Jack Hickish wrote:
I've toyed with Planahead a bit, and quickly found I was in way over my
head. Could you recommend a good starting point for learning this tool?
I'm sure you've found the planahead user guide, which is a bit of a
Hi all,
Should such software (simulink) features as subsystems and and gotos
have any affect on the final circuit created when I build my bof file?
I am compiling models on Roach I that use almost all of the available
Logic Slices (~97%). That the subsequent build should contain timing
On 01/29/2014 01:03 PM, Paul Marganian wrote:
Hi all,
Should such software (simulink) features as subsystems and and gotos
have any affect on the final circuit created when I build my bof file?
I am compiling models on Roach I that use almost all of the available
Logic Slices (~97%). That
On 01/29/2014 01:03 PM, Paul Marganian wrote:
Hi all,
Should such software (simulink) features as subsystems and and gotos
have any affect on the final circuit created when I build my bof file?
I am compiling models on Roach I that use almost all of the available
Logic Slices (~97%). That
I'm not sure what, if any, difference a subsystem will make to the
mapped design (I thought none), but I believe it's the case that
changing module names etc. can affect the place and route algorithm's
start seed. I seem to remember seeing this mentioned in a Xilinx doc
under the heading I've
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