e I/O capacity of a single
> Roach2 board – just trying to figure out how many I may need?
>
> Thank you,
>
> Neil
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* 18 December 2015 15:08
> *To:* James Smith; Neil Salmon
>
>
> *Cc:* cas
7;m not entirely sure
what's available in the board design realm.
Jack
> Many thanks,
>
> Neil
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* 18 December 2015 17:26
> *To:* Neil Salmon; James Smith
>
>
> *Cc:* casper@lists.berkeley
Hi Homin,
What total size of FFT are you trying to do? How does the FFT fail?
Cheers,
Jack
On Mon, 11 Jan 2016 at 00:35 Homin Jiang wrote:
> Hello:
>
> Does anyone have the experience of the 32 simultaneous inputs to the
> fft_wideband_real ? I have tried that for couple of days without any l
Hi Michael,
I just cloned https://github.com/casper-astro/tutorials_devel.git and
compiled tut3_noquant_r111 against mlib_devel
b6e70b660910482b1f1028d32d29284468e38cda using Xilinx 14.7 and MATLAB 2012b
(I ran update_casper_blocks(bdroot) on the model, and changed the target
for roach2 before com
rds
> homin
>
> On Tue, Jan 12, 2016 at 12:38 AM, Jack Hickish
> wrote:
>
>> Hi Homin,
>>
>> What total size of FFT are you trying to do? How does the FFT fail?
>>
>> Cheers,
>> Jack
>>
>> On Mon, 11 Jan 2016 at 00:35 Homin Ji
Hi Matt,
You can resynthesize the "main" simulink netlist, but off the top of my
head I don't know the exact way to go about this. I think you can dig out
the netlist from the sysgen build directory and use the resynth script on
that. Perhaps Dave MacMahon (who I believe wrote that script) could c
Ha, I just read my email in the thread you linked. I guess turning off
behavioural hdl isn't (ever? always?) the solution.
On Mon, 25 Jan 2016 5:14 pm Jack Hickish wrote:
> Hi Matt,
>
> You can resynthesize the "main" simulink netlist, but off the top of my
> head I
r port, and also on a ROACH1.
>
>
>
> https://dl.dropboxusercontent.com/u/38103354/r2_spectra.zip
>
>
>
> BW
> Michael
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
>
> *Sent:* 12 January 2016 21:28
>
> *To:* Michael D'Cruze
&g
Hi all,
In case you are interested, please see http://www.jobs.cam.ac.uk/job/9372/
for details of a Research Associate position currently being adversed at
the University of Cambridge. Informal enquiries should be directed to Dr
Nima Razavi-Ghods -- n...@mrao.cam.ac.uk.
Thanks (and apologies to t
Hi Vishwa,
Is the syntax definitely -demux=1 andnot either --demux=1 or -d 1 ?
Jack
On Wed, 3 Feb 2016, 12:39 a.m. Vishwa Seneviratne
wrote:
> Hi,
>
> I am working on how to work with different operating of the 'ADC16x250-8
> coax rev 2' for a very simple design to test how the ADC works. The
Hi Johnathon,
What incantation are you using with mkbof? I believe what you want is:
mkbof_64 -o output.bof -s core_info.tab -t 3 top.bin
Note you want a .bin rather than a .bit file -- I believe this is an option
in bitgen (maybe it automatically happens in planahead).
Jack
On Wed, 3 Feb 201
There's also a UCF yellow block that lets you add ucf files to your design
(much like the PCORE yellow block). I think there's also a method to inject
ucf constraints via an environment variable (I think you could find this in
the git log somewhere).
Cheers,
Jack
On Wed, 3 Feb 2016 at 10:31 David
Hi Rolando,
This is wrong -- the User IP clock source should be adc0_clk, at 24 MHz.
If you see a design with an ADC, but the clock source is set to to sys_clk,
this is *almost always* a mistake.
Jack
On Sat, 20 Feb 2016 at 19:04 Rolando Paz wrote:
> Hi
>
> I have a question about the "User IP
gt;>> parameter?
>>>
>>> Thank you
>>>
>>>
>>> Sincerely,
>>>
>>>
>>> *Vishwa Seneviratne*
>>>
>>> *Graduate Student*
>>>
>>> *Dept. of Electrical and Computer Engineering*
>>> *University of
ce, ADCs need to be clocked at 480 MHz for the demux=2 mode, how does
> the FPGA clock at 240 MHz? does it use a clock divider internally?
>
> Is there any maximum operating frequency for the FPGA, when we use the
> adc16 block?
>
> Regards,
> Nilan Udayanga.
>
> On Wed, Mar
ked at 480 MHz for the demux=2 mode, how does
>> the FPGA clock at 240 MHz? does it use a clock divider internally?
>>
>> Is there any maximum operating frequency for the FPGA, when we use the
>> adc16 block?
>>
>> Regards,
>> Nilan Udayanga.
>>
>&g
n removed during optimization...
Jack
On Fri, 11 Mar 2016 at 00:18 Jack Hickish wrote:
> Hi Nilan,
>
> It looks like there's a block called (something like) ppcm12/block_t_z2
> with a huge logic delay -- from line 135 of the failing twr file --
>
> Data Path Delay:
egards,
> Nilan Udayanga.
>
> On Thu, Mar 10, 2016 at 7:18 PM, Jack Hickish
> wrote:
>
>> Hi Nilan,
>>
>> It looks like there's a block called (something like) ppcm12/block_t_z2
>> with a huge logic delay -- from line 135 of the failing twr file --
ow whether it may change the
> critical path delay.
>
> Regards,
> Nilan Udayanga.
>
> On Thu, Mar 10, 2016 at 8:02 PM, Jack Hickish
> wrote:
>
>> I think if you can add latency in those multipliers / adders you'll
>> probably find your problem will go away
;
> On Thu, Mar 10, 2016 at 8:38 PM, Jack Hickish
> wrote:
>
>> Hi Nilan,
>>
>> Yeah, I figured that would be a problem... :)
>> Does something like this (which i confess I haven't read, but Fig 14
>> looks potentially relevent) help? --
>> http://w
Hi Rolando, CASPER,
The ROACH should still be supported by all the CASPER tutorials which are
on the wiki -- https://casper.berkeley.edu/wiki/Tutorials
Cheers,
Jack
On Wed, 6 Apr 2016 at 16:48 Rolando Paz wrote:
> Hi Jack
>
> The next Friday I will travel to Mexico to pick up one ROACH1!
> I w
Hi Rolando,
That guide should still be up to date and working.
Jack
On Wed, 6 Apr 2016 at 22:35 Rolando Paz wrote:
> Thanks Jack.
>
> So, Can I follow this guide?
>
> https://casper.berkeley.edu/wiki/ROACH_NFS_guide
>
> Regards
>
> Rolando
>
>
> 201
>
> Regards
>
> Rolando
>
> 2016-04-06 23:37 GMT-06:00 Jack Hickish :
>
>> Hi Rolando,
>>
>> That guide should still be up to date and working.
>>
>> Jack
>>
>> On Wed, 6 Apr 2016 at 22:35 Rolando Paz wrote:
>>
>>
>
> b) The third roach has password, and could not find it is. How we can
> change the user and password?
>
>
The most straightforward way is probably to just copy the SD card image
from one of your working ROACH boards, or from the svn links you found.
> Best Regards
&
Howdy all,
I'm trying to program a Valon 5008 synth with the ValonSynth nrao python
API -- https://github.com/nrao/ValonSynth (master branch) -- running on a
raspberry pi 3.
Does anyone know if this code actually works with a 5008 -- it's advertised
for a 5007 and I get some fun results when I at
Thanks for the various replies people sent. I think this can be filed under
User Incompetence -- I believe I may have set the reference frequency to
10.0, when it should have been specified (unlike most of the other freqs)
in Hz.
Cheers,
Jack
On Tue, 26 Apr 2016 at 20:14 Jack Hickish wrote
Hi Matt,
The usual way to deal with this is IODELAY blocks as you suggest. The adc5g
core has an example of the correct instantiation of the IODELAY primitive
and some controller code to talk to them. IIRC, the delay goes straight
after the input buffer, prior to the SERDES (or presumably immediat
100100010 00001000
> 26 : 10110001 0010 101100100010 110110001000
> 27 : 1011 101100100010 110110001000
> 28 : 0011 101110100010 110110001000
> 29 : 00110100 101110100010 110110001000
> 30 : 00010100
Howdy,
If you go to the opb_opb_lite pcore directory you'll find a file
data/opb_opb_lite_something.mpd. This should have a line indicating
supported platforms - add VIRTEX6 and you should be good to go. You might
have to do this for some of the other deprecated pcores too.
The currently linked pc
eers,
Jack
-- Forwarded message -
From: Rolando Paz
Date: Tue, 24 May 2016 at 11:48
Subject: rpoco8-beamformer
To: Jack Hickish
Hi Jack
Can you help me understand how I can recompile the rpoco8_testbench_v11.mdl
model?
https://github.com/zakiali/pocket_corr
I do not understand
Hi Amit,
That's correct, assuming you are operating the adc in single input mode. It
also has a dual-input mode, where the first 8 outputs are one input, and
the second 8 are the other.
Don't forget that the input clock in single input (aka interleaved) mode
should be half the total sample rate. E
Hi Kaushal, cc. CASPER,
All good here (Berkeley), thanks. Hope you are well too.
It's been a long time since I've used that ADC, but from what I remember...
- Yes, you need to appropriately drive the ADC's reset through the jumper.
If things aren't working and you're debugging with a probe, note
Hi Christopher,
Which scope outputs are you not able to reproduce from the wiki? What
outputs did you see?
Cheers
Jack
On Tue, 14 Jun 2016 at 10:21 Christopher Barnes wrote:
> Hello,
>
> My name is Christopher Barnes, and I'm a graduate student at the
> University of Michigan. I'm working thr
er output and then just an empty
> set of axes for the adder output.
>
> On Tue, Jun 14, 2016 at 1:56 PM, Jack Hickish
> wrote:
>
>> Hi Christopher,
>>
>> Which scope outputs are you not able to reproduce from the wiki? What
>> outputs did you see?
>&
; For the counter, the settings are correct; I just checked them again. Do
> you have any more ideas on this?
>
> On Tue, Jun 14, 2016 at 2:04 PM, Jack Hickish
> wrote:
>
>> For the adder, have you clicked the icon at the top marked with a pair of
>> binoculars to auto-scale
Hi all,
SNAP revision 2 is (finally) about to finish being tested. Various folk
expressed interest in purchasing them once they were verified.
Could those who are still interested please reply to me off-list with
- the approximate number of boards they want
- the FPGA model they need*
- any
Hi Amit,
For what it's worth, you can always just run the ADC faster, but only use a
subset of the yellow block outputs. Eg., clock the ADC at 1280MHz, and use
every 8th yellow block output. This can be handy because
1. You get to avoid whatever edge cases exist which cause various blocks to
break
(at $280), not
including enclosure or 12v power supply.
Cheers
Jack
On Sat, 18 Jun 2016, 15:15 Jack Hickish, wrote:
> Hi all,
>
> SNAP revision 2 is (finally) about to finish being tested. Various folk
> expressed interest in purchasing them once they were verified.
>
> Could t
Hi Andrea, cc-ing maillist, since I don't think you're the only one to do
(or want to do) this,
What you are suggesting is absolutely technically possible, though (as much
as I dislike simulink), I'd think really hard before going through with it.
Note also, if you don't use the toolflow, you beco
urself.
>
> Good luck!
>
>
> Kind Regards,
>
> Adam
>
> On Tue, Jun 21, 2016 at 11:47 PM, Jack Hickish
> wrote:
>
>> Hi Andrea, cc-ing maillist, since I don't think you're the only one to do
>> (or want to do) this,
>>
>> What yo
Is that 85% including both 18kb and 36kb brams? Could you post your map
report?
On Mon, 27 Jun 2016 3:17 pm Michael D'Cruze, <
michael.dcr...@postgrad.manchester.ac.uk> wrote:
> Dear all,
>
>
>
> I’m trying to compile a relatively simple 64k-channel spectrometer. I’m
> getting an error which indi
, <
michael.dcr...@postgrad.manchester.ac.uk> wrote:
> Hi Jack,
>
>
>
> Ahh, that explains it. The sum exceeds 100%. I’ll adjust the design….
>
>
>
> Thanks
>
> Michael
>
>
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* 27 June 2016 16:48
WOL packets indicate power-down mode of ADC, so is there a way to
> check the digitized output at the ZDOK connector?
>
There's no way to check, unless you mess with the interface verilog. All
-1's signify a reset problem though, so I would expect that is genuinely
what's com
Hi CASPERites,
The JAI is having a special issue for radio astronomy DSP, and I think it
would be really great if there was a paper submitted representing the
current state of CASPER hardware/software/toolflow efforts.
One awesome thing to have in such a paper would be a comprehensive table of
in
left out (and, sorry!) -- but please *do* let me know!
Thanks,
Jack
On Tue, 12 Jul 2016 at 17:10 Jack Hickish wrote:
> Hi CASPERites,
>
> The JAI is having a special issue for radio astronomy DSP, and I think it
> would be really great if there was a paper submitted representing the
&
Hi Heystek,
>From a clean install, you shouldn't really have this many problems, and I
suspect all your chmod/chown-ing to/from root is just making everything
worse.You certainly don't need to run startsg as root (and you shouldn't,
who knows what code CASPER collaborators have hidden in there!) a
to warm up seems to get rid
> of most of them (though not all). Note: if you do choose to do a second
> MMCM cal. do not issue a sync to the ZDOK 0 ADC as this will disturb your
> FPGA clock.
>
> As you rightly point out it would be better to adjust delay lines per data
> bit. In
Hi Homin,
JASPER works for SNAP (https://casper.berkeley.edu/wiki/SNAP_Bringup --
there are instructions to find the repo there, too) -- i.e., you can go
from simulink to boffiles. Toolflow support includes all the SNAP-relevant
yellow blocks -- tge, software registers, bram, gpio, on-board ADC. S
Hi Kaustubh,
What version of the mlib_devel libraries are you using?
Cheers,
Jack
On Mon, 5 Sep 2016 at 08:11 Kaustubh Rajwade wrote:
> Hi Casperites,
>
> I have a simple ROACH 1 design streaming packets via two 10GbE ports
> (clock:160 MHz). When I compile the design using old libraries (XSG
ing:
>
> Old library: commit a88c343 (16 Nov 2010)
>
> New library: commit ecab6f (2 Jan 2015)
>
> Cheers,
> Kaustubh
>
> On Mon, Sep 5, 2016 at 6:07 PM, Jack Hickish
> wrote:
>
>> Hi Kaustubh,
>>
>> What version of the mlib_devel libraries are you
No probs!
On Mon, 5 Sep 2016 at 11:27 Kaustubh Rajwade wrote:
> Hi Jack,
>
> Thanks for pointing me in the right direction!
>
> Cheers,
> Kaustubh
>
> On Mon, Sep 5, 2016 at 8:14 PM, Jack Hickish
> wrote:
>
>> Hi Kaustubh,
>>
>> I think you miss
Hi Ho-Cheung,
I think in theory simulink does support multiple clock domains (though
maybe not truly asynchronous ones?), but I expect in any event it would
break the toolflow somewhere if you tried to design such a system only
using the simulink designer. This has come up periodically on the mail
Hi Michael,
Is this actually the optimisation parameter of the xilinx bram block, or an
optimisation of a casper block which completely changes some underlying
circuit (eg by doing a bunch of fanout control and instantiating multiple
small brams instead of one big one)?
If the latter, are you sure
lay_bram init
> script. Line 84 which configures the Xilinx ram block, I changed the
> parameter ‘optimize’ from ‘Area’ to ‘Speed’. No other changes were made,
> so, I think this is the former case?
>
> BW
> Michael
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.c
Hi Heystek,
You can also just delete the simulation blocks inside the ADC for the time
being. You don't need them to compile the design, only to be able to
simulate the ADC analog inputs properly.
Cheers
Jack
On Tue, 20 Sep 2016 at 13:32 Heystek Grobler
wrote:
> Hi Michael
>
> Thanks for your
gt; Heystek
>
>
>
>
> On Tue, Sep 20, 2016 at 10:40 PM, Jack Hickish
> wrote:
>
>> Hi Heystek,
>>
>> You can also just delete the simulation blocks inside the ADC for the
>> time being. You don't need them to compile the design, only to be able to
&
On Wed, 21 Sep 2016 at 04:47 Guenter Knittel
wrote:
> Hi all,
>
>
>
> I’m still busy trying to speed-optimize our DSP pipeline, and it’s amazing
>
> how sophisticated the tools are in picking ever new signals to let them
> miss timing.
>
> But a few of them occur frequently, often inside fft_wide
p.
>
> >> You could always add your own constraint file using the "UCF" block.
>
> I have to admit, I’m not aware of a UCF block. Is that a Simulink block?
> We are
>
> using Simulink R2013a, I couldn’t find it in the browser.
>
>
>
> Thanks, cheers
>
Hi Guenter,
Your mileage may vary, and I don't know what the specs of your system are,
but if it were me I'd start by drawing loose pblock constraints for the DSP
and ram in each stage in the fft. I would suggest not going overboard with
pipelining, which in my experience can frequently make thing
Hi All,
I'm trying to update the wiki, and our records at UCB which we use to sell
CASPER to funding bodies (is it a coincidence that this email is going out
a couple of weeks before the NSF ATI deadline? Probably not).
If you are a CASPER user, or CASPER technologies feature significantly in
you
Hi Claudio, cc. maillist
Have you modified the tut3 software or firmware? You seem to have a problem
reading the "even" bram. Does this exist in your model? Are you reading the
correct number of bytes from it -- the error message suggests you tried to
read 4096 bytes -- is this right?
Can you tal
Hi Alec,
What version of the casper libraries are you using?
The top of the tutorials page on the wiki states:
"""
These tutorials were constructed using Xilinx System Generator 14.7 and
MATLAB 2012b. Other mutually compatible versions of Xilinx and MATLAB tools
may work correctly, but have not
Hi Sravan,
Hard to say without you model, but are all the binary points in your model
and interpretations of binary outputs in your python correct?
Regarding the issue of not reading the right number of values -- it looks
like you're reading from a normal bram (rather than a snapshot block), so I
Hi Alec,
That's a fun one. Is this the vanilla tut4 design after running
update_casper_blocks? I can try and recreate the problem here
Cheers
Jack
On Mon, 14 Nov 2016 at 16:35 Alec Josaitis wrote:
Dear Dave and Glenn,
You were both correct, my MLIB_DEVEL_PATH returned any empty string; th
ba5efb4
> <https://github.com/casper-astro/mlib_devel/commit/4c7ba5efb421fda1cec0640cf0e3b830a9987640>
> .
>
>
> Best,
> Alec
>
> On Mon, Nov 14, 2016 at 7:52 PM, Jack Hickish
> wrote:
>
> Hi Alec,
>
> That's a fun one. Is this the vanilla tut4 design after running
>
Hi Pamela,
Welcome to the casper maillist! -- to submit questions, the address you
want is casper@lists.berkeley.edu .
>From the directory containing the python script, can you run the script
with the command:
python ./tut3_noquant_r111.py -b
Maybe I'm way off base, but this is potentially re
ecause of a disconnection between munge_in and convert_din1.
> Should those blocks really be disconnected? Do you know why they came
> disconnected in model?
>
> Best,
> Alec
>
> On Mon, Nov 14, 2016 at 10:29 PM, Jack Hickish
> wrote:
>
> Hi Alec,
>
>
> So I
Hi Rolando,
If I had to guess, I'd say there is a problem with the version of the
python katcp/corr libraries you're using, and the version of tcpborphserver
running on your ROACH. Do you know the versions of these bits of code that
you're using?
Cheers
Jack
On Thu, 1 Dec 2016 at 16:52 Rolando P
Hi Eric,
If no-one knows the answer to this I'd suggest pinging Techne Instruments,
who should have the answer. There's a link to the board schematics at
http://techneinstruments.com/Boards_for_Roach which probably could also
have answered your question but it seems to be dead :(
Cheers
Jack
p, the previous broken links of the model
> become connected.
>
> Unfortunately, even after performing this drag-and-delete operation by
> hand for every shared bram block in either dir_x, I receive the same "||
> and && operator" error described above.
>
> Any n
cp-0.3.4.
>
> What are the correct versions of corr and katcp for my ROACH? Or, should
> I use casperfpga?
>
> Best Regard
>
> Rolando
>
> 2016-12-04 15:30 GMT-06:00 Jack Hickish :
>
> Hi Rolando,
>
> If I had to guess, I'd say there is a problem with the
elp watchdog pings\_the\_system\_(?watchdog)
> #help log-level
> sets\_the\_minimum\_reported\_log\_priority\_(?log-level\_[priority])
> #help help displays\_this\_help\_(?help\_[command])
> #help restart restarts\_the\_system\_(?restart)
> #help halt shuts\_the\_system\_down\_(?halt
so I had to install
> katcp-0.3.4. so, I am thinking update my filesystem version, because can be
> outdated?
>
> Regards
>
> Rolando
>
>
>
>
>
>
> 2016-12-05 14:04 GMT-06:00 Jack Hickish :
>
> Hi Rolando,
>
> Nice work!
>
> My advice - i
Hi Michael, cc. List,
Do you see glitches if you leave the adc in test ramp mode and grab lots of
samples? If not, the problem isn't related to IO calibration.
I might be misinterpreting your email, but just to be clear, you must
recalibrate the MMCMs (or iodelays, or both) every time you program
es the mmcm and the ogp stuff in one hit?
Cheers
Jack
Thanks
>
> Michael
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* 08 December 2016 23:26
> *To:* Michael D'Cruze; Primiani, Rurik; casper@lists.berkeley.edu
>
>
> *Subject:* Re: [caspe
Hi Roberto,
The input to the mkbof program needs to be a .bin (not .bit) file. I
believe there's a "generate binary" option you can specify in the planahead
options for bitgen.
Hope that helps,
Jack
On Wed, 14 Dec 2016 5:30 pm Roberto F., wrote:
> Hello everyone,
>
> I want to generate a boff
More broadly speaking, has anyone ever used the DDR powerPC interface on
ROACH2? Is it actually know to work with code as-provided in the mlib_devel
/ katcp repos?
Franco -- perhaps this project --
https://github.com/argonnexraydetector/RoachFirmPy -- which I found linked
on the DDR page of the CAS
Wesley New for vetting/committing to their repo but I
> guess he hasn't done it yet. I can send the info to those interested.
> Regards, mm.
>
> From: casper-boun...@lists.berkeley.edu [casper-boun...@lists.berkeley.edu]
> on behalf of Jack Hic
Hi Kaushal,
On Mon, 2 Jan 2017 10:16 am Kaushal Buch, wrote:
> Dear all,
>
> We have interfaced 64-channel ADC with ROACH-1 board and it is working
> as expected using on-board clock (50MHz). There is provision to
> provide an external clock to this board to operate ADC to get a
> maximum data r
Hi Luca,
Did you get anywhere with this - it seems like you're missing some of the
adc_mkid_4x_interface code. Which version of mlib_devel are you using?
Cheers
Jack
On Thu, 15 Dec 2016 3:40 pm , wrote:
> Dear all,
>
>
>
> I’m working on a project with ROACH2 and ADC/DAC MKID boards. I can use
32 Kaushal Buch wrote:
> Hi Jack,
>
> Thanks for the reply.
>
> The design compiled for 260 MHz (adc0_clk) with yellow block set to 65 MHz.
>
> However, I am not yet clear about the external clock input requirements.
>
>
>
> Regards,
>
> Kaushal
>
> On
there is a good way to rescue missing emails,
other than just sending them again. Feel free to do so if you thing the
information in the mail should be archived.
Cheers
Jack
On Fri, 3 Feb 2017 at 11:32 Jack Hickish wrote:
> Hi all,
>
> A few people contacted me in the last 48 hours to say
Hi Oliver,
Have you tried increasing the MATLAB Java heap size, as per
https://www.mail-archive.com/casper@lists.berkeley.edu/msg04642.html ?
Cheers
Jack
On Sun, 26 Mar 2017 at 22:32 Wang Jinqing wrote:
> Hi ,
>
> I am developing a project. It seems good when do the simulation. But When
> I
Hi Claudio,
This is a classic problem -- the library version you are using is not
compatible with the version the tutorials were designed in. The particular
error you have can be solved by deleting the XSG yellow block and pulling a
new one from the library (I believe it is now called XSG_core_con
Further, is the board clocking OK? -- I believe the initialization script
should give feedback on whether of not the FPGA's PLL has successfully
locked to the ADC clock, and what the current measured board clock is.
Cheers
Jack
On Wed, 29 Mar 2017 at 14:28 Matt Dexter wrote:
> Is the design and
d for ADC A.
> ERROR: SERDES calibration failed for ADC B.
> ERROR: SERDES calibration failed for ADC C.
> ERROR: SERDES calibration failed for ADC D.
> Selecting analog inputs...
> Using default digital gain of 1...
> Done!
>
>
> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hi
nd I am not sure how to
> check the adc repo and mlib_devel repo versions ? Could you please help me
> in that ?
> Thank you.
>
> On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish
> wrote:
>
> I like the triumphant "done!" at the end :)
>
> Next questions --
> Wha
configure the brams ?
>
> On Thu, Mar 30, 2017 at 4:36 PM, vijay kumar > wrote:
>
> The following is output I get when i type the 'git rev-parse HEAD':
>
> a949c9d5c1761078b4c884699ff52c1497a17ff6
>
> On Thu, Mar 30, 2017 at 2:32 PM, Mark Wagner wrote:
>
Hi Franco,
I don't know the low frequency limit, but for what it's worth, you could
always run the adc at 320 MHz and just use 1 of the 8 outputs, which also
has the benefit of avoiding and inter-core mismatch issues, since you'd
effectively only be using 1 core. Or run faster and only use every N
I'm sure I remember merging Tim's code in the past. I've just got off a
flight and am a bit dazed and confused right now, but I'll check what's in
the main casper-astro repository tomorrow and update the r2 core if needed.
Cheers
Jack
On Thu, 6 Apr 2017, 15:48 Madden, Timothy J., wrote:
> Olive
Hi Franco,
Looking at the schematics, the over-range pins are routed to the ZDOK, so
it should be possible to add these signals to the yellow block if you
really want them. As things stand at the moment, I don't know how you'd
check for an over-range condition other than just monitoring the ADC ou
This is now in the main casper-astro repo (
github.com/casper-astro/mlib_devel) .
Thanks Tim!
Jack
On Thu, 6 Apr 2017 at 16:52 Jack Hickish wrote:
> I'm sure I remember merging Tim's code in the past. I've just got off a
> flight and am a bit dazed and confused righ
Hi Luca,
Maybe this response is too delayed to be useful, but using the main
casper-astro repository (https://github.com/casper-astro/mlib_devel),
the xps_adc_mkid_4x
should now work with both roach1 and roach2.
I'm not sure what repository you are using which contained the
xps_adc_mkid_4x_r2
bloc
ps://github.com/ska-sa/mlib_devel)
>
>
>
> 3. Xilink 14.7
>
>
>
> thanks,
>
> Chunsik
>
>
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* Thursday, April 20, 2017 11:16 AM
> *To:* Chae, Chun Sik (382G) ;
>
7 Apr 2017, 01:05 Chae, Chun Sik (382G), <
chun.sik.c...@jpl.nasa.gov> wrote:
> Hi jack,
>
>
>
> I am tyring this. It seems to me that the ‘startsg’ needs ‘startsg.local’.
> Am I correct?
>
> If so, where can I find ‘startsg.local’?
>
>
>
> thanks,
>
>
Hi Franco,
Some guesses below
On Thu, 27 Apr 2017 at 15:22 Franco wrote:
> Dear Casper Community,
>
>
> I was playing with the sync_gen block, and I have some question
> regarding its parameters. I read the syn_gen memo
> (https://casper.berkeley.edu/memos/sync_memo_v1.pdf) but it didn't he
Hi Franco,
I've had this error before. To be honest, since ISE compiled my design fine
and I could see no issues in hardware when comparing digital noise sent
through multiple FFT channels, I just ignored the problem. That is, I used
planahead to generate constraints/pblocks, but compiled these wi
Hi Franco,
1) Yes, this is an optimization the tools have performed. If you dig into
the Xilinx manuals you can probably find some options / UCF entries to turn
off this type of optimization, or at least make it less aggressive. I don't
use these enough to know exactly which ones you want, but I'd
Hi Xavier,
Assuming you're only going to use the katcp stuff in Corr to talk to your
boards, you don't really need corr_functions at all.
In fact you can edit the __init__.py file in Corr/ to remove a lot of the
superfluous imports if they are causing you trouble.
The real solution is that everyo
Hi Xavier,
The ROACH2 (unlike the ROACH1) has a dedicated 1GbE connection straight to
the FPGA fabric -- it's the "other" RJ45 connector in addition to the one
you're using to talk katcp. You can access it using the one_gbe yellow
block -- I think this is probably the way to go.
Cheers
Jack
On M
101 - 200 of 607 matches
Mail list logo
