[PATCH] D125728: [WebAssembly] Update supported features in -mcpu=generic

asb added a comment. Oh, and per recent updates to the LLVM Developer policy I think it would be worth updating the Clang ReleaseNotes.rst to mention this change. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION http

[PATCH] D125728: [WebAssembly] Update supported features in -mcpu=generic

asb added a comment. Based on the discussion we had, I think this makes sense. It's a bit repetitive, but could you please add a test to clang/test/Driver that checks the list of enabled features for generic (and for completeness, probably bleeding-edge as well). Thanks. Repository: rG LLVM

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

asb added a comment. Thanks for the patch - can you add test coverage for this please? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125765/new/ https://reviews.llvm.org/D125765 ___ cfe-commits mailing l

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

asb added a comment. @maskray: Are you happy all your comments are addressed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120639/new/ https://reviews.llvm.org/D120639 ___ cfe-commits mailing list cfe-c

[PATCH] D122215: [WebAssembly] Initial support for reference types in clang

asb added inline comments. Comment at: clang/test/CodeGen/WebAssembly/wasm-externref.c:1 +// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +reference-types -o - -emit-llvm %s | FileCheck %s + It might be worth using update_cc_test_checks.py for

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. It would be good to have someone else who's reviewed earlier versions of this patch to confirm, but this LGTM. Thanks. If you were editing it anyway, you could change "has passed" to "is passed" (t

[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added subscribers: s, arichardson. Thanks, this looks good to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121578/new/ https://reviews.llv

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In D118333#3329422 , @asb wrote: > Thanks, I've put this on the agenda for the RISC-V LLVM sync call today. I > think this is more attractive than the previ

[PATCH] D120297: [Driver][RISCV] Add missing rv64 test case

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120297/new/ https://reviews.llvm.org/D120297

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

asb added a comment. Thanks, I've put this on the agenda for the RISC-V LLVM sync call today. I think this is more attractive than the previous proposal due to unifying logic between llc and Clang. I could see a counter-argument about llc being a low-level tool that should be controlled very ex

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In that case, LGTM (needs a rebase though). Thanks for your patience on this @achieveartificialintelligence. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 _

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks Kito. This LGTM, but I'd appreciate someone else reviewing and approving as well. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119837/new/ ht

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. Not an issue for this MC-layer patch, but I've created https://github.com/riscv/riscv-zfinx/issues/14 to point out what seems to be an incorrect statement about the status quo on the ABI for 32-bit floating point types on RV64 in the Zfinx spec. Repository: rG LLVM Gith

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. Herald added a subscriber: pcwang-thead. Thanks for your work on this. The way you've managed to use multiclasses to handle this with the 'ExtInfo' definitions takes a bit of unpicking to follow, but it does a really good job of keeping the instruction definitions largely u

[PATCH] D118015: [RISCV][NFC] Rename RequiredExtensions to RequiredFeatures.

asb added a comment. Makes sense to me, but I'll defer to someone else working more actively with this part of the codebase for a final LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118015/new/ https://reviews.llvm.org/D118015 _

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

asb added a comment. In D112987#3257899 , @frasercrmck wrote: > If we're bumping it to 1.0, does that mean it's no longer "experimental"? Whether RVV is non-experimental or not is the big open question for 14.0. I've put it on the agenda for today's sy

[PATCH] D117131: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG33d008b169f3: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be… (authored by asb). Repository: rG LLVM Github Monorepo CHA

[PATCH] D117130: [RISCV] Move Zba/Zbb/Zbc/Zbs out of experimental since they have been ratified.

asb added a comment. Doh - looks like we had the same idea at the same time :) D117131 . I've not done a full diff, but one thing I spotted was that the RISCVInstrInfoZb.td header needs updating. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D117131: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental

asb created this revision. asb added reviewers: craig.topper, luismarques. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, StephenFan, vkmr, frasercrmck, jdoerfert, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Marti

[PATCH] D113237: [RISCV] Support I extension version 2.1

asb added a comment. @kito-cheng In D113237#3183969 , @kito-cheng wrote: > Here is a long discussion[1] at 2019, at that moment I think we all agree > -misa-spec is a good solution, > > However it's kind of awkward for this scheme is ISA spec changing

[PATCH] D113237: [RISCV] Support I extension version 2.1

asb added a comment. In D113237#3172492 , @achieveartificialintelligence wrote: > In D113237#3124232 , @luismarques > wrote: > >> In D113237#3124188 , @luismarques >> w

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

asb added a comment. OK, that reasoning makes sense. I think my only outstanding request would be to ensure there's some test coverage for the case of .attribute arch with an experimental extension without version info. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. This seems to match the emerging consensus in the various RISC-V GitHub issue threads and as you point out, is needed to support extensions in the 1.0 V spec. Looks good to me - thanks! =

[PATCH] D111866: [RISCV] Support Zfhmin extension

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, modulo one tiny nit on a comment. Thanks! Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:253 def PseudoFSH : PseudoStore<"fsh", FPR16>; } // Predicates = [HasStdEx

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

asb added a comment. In D112359#3098960 , @eopXD wrote: > > Add version numbers for test case in `attribute-arch.s` Thanks for updating the patch. Why change this test case? I thought those lines were verifying that .attribute arch without a version

[PATCH] D111866: [RISCV] Support Zfhmin extension

asb added inline comments. Herald added a subscriber: luke957. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1153 bool ForCodeSize) const { - if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) + if (VT == MVT::f16 && !Subtarget.ha

[PATCH] D111866: [RISCV] Support Zfhmin extension

asb added a comment. Herald added a reviewer: luke957. From an initial look, I think this is almost ready to land - thank you. One suggestion would be to review the various `Subtarget.hasStdExtZfhmin() || Subtarget.hasStdExtZfh()`. I'd first thought adding a new helper to RISCVSubtarget to be c

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

asb added a comment. Herald added a reviewer: luke957. This doesn't apply cleanly to current HEAD, could you please rebase? I think the second part of this that you list, where the ISA extension version becomes optional is undesirable. We made the explicit choice of requiring the version string

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

asb added a comment. Is this blocked on anything or is it good to land? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111062/new/ https://reviews.llvm.org/D111062 ___ cfe-commits mailing list cfe-commits

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Looks good to me - I'm surprised only Arm, AArch64, and X86 implement this! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108624/new/ https://reviews.

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

asb added a comment. I'm getting a build error (building with clang 12.0.1): FAILED: lib/Support/CMakeFiles/LLVMSupport.dir/RISCVISAInfo.cpp.o /usr/bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/asb/llvm-p

[PATCH] D106888: [RISC-V] Implement jump tables for CFI-icall

asb added a comment. Is it possible to write a test case for this? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106888/new/ https://reviews.llvm.org/D106888 ___ cfe-commits mailing list cfe-commits@list

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

asb added inline comments. Comment at: llvm/test/CodeGen/RISCV/loop-alignment.ll:3-4 +; RUN: llc < %s -mtriple=riscv64 | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16 +; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileC

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. This looks good to me, and as Jessica says this patch improves robustness and correctness so it would be great to land it for 13.x. @jrtc27 - I think @khchen has reflected all of your comments, but

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

asb added a comment. This looks like a good improvement to me - anything that still makes it a "[PoC]" proof of concept? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 __

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

asb added a comment. In D102839#2784585 , @kito-cheng wrote: > Personally I prefer to deprecate `-mno-div` soon, but based on the rule for > RISC-V GNU toolchain, it need to wait `Zmmul` extension frozen. > My plan is deprecate the `-mno-div` and emit w

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

asb added a comment. In D70401#2733003 , @khchen wrote: > Hi, I would like to add ilp32e ABI support in llvm > Is there anyone working on this? > It seem the one thing missed is ilp32e ABI should disallow D ISA extension. > Is there anything else? Nobody

[PATCH] D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99108/new/ https://reviews.llvm.org/D99108 ___ cfe-co

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

asb added a comment. Can I just check the reasoning on the naming? I see that the bitmanip 0.93 spec proposes _{rv,rv32,rv64}_{opname} intrinsics. Does the __builtin__{riscv,riscv32,riscv64}_opname format match what GCC are doing / planning to do here? Precedent for RVV, for other archs, or som

[PATCH] D97896: [Clang][RISCV][RFC] Add byval parameter attribute?

asb added a comment. I think I may have had the impression from some previous discussions that byval may have limited positive impact, and that letting Clang add the copies to the IR might in some cases help optimisations (that may not be written to reason about byval). You've got a good exampl

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. In D93298#2544459 , @StephenFan wrote: > According to @jrtc27 's review that is > "As for Zfinx itself, well, the idea is fine, but I really detest the way > it's being done as an extension to F/D/Zfh. Running F code on an FZfh core

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. I started reviewing this alongside the specification in https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem to be used in this patch. I think intent is that rv32ifd_zfinx

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

asb accepted this revision. asb added a comment. LGTM modulo one additional request: please update the comment at the top of RISCVInstrInfoV.td to say "0.10" rather than "0.9". Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95680/new/ https://revie

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

asb accepted this revision. asb added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:61 isExperimentalExtension(StringRef Ext) { - if (Ext == "b" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" || + if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

asb added a comment. I don't think any of the other patches in the stack update the comment at the top of RISCVInstrInfoB.td to say "version 0.92" rather than "version 0.93", and this is probably a reasonable patch to do it in. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D94403: [RISCV] Implement new architecture extension macros

asb added a comment. @kito-cheng could you please confirm that this patch handles sub-extensions in the same way GCC does. i.e. -march=rv32izbb0p92 defines `__riscv_zbb` but NOT `__riscv_b`? That seems logical to me, as otherwise it would be cumbersome to check if the whole extension is support

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

asb added a comment. In D92715#2443376 , @craig.topper wrote: > Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng > @khchen @liaolucy I've added it to the agenda CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new

[PATCH] D84414: [RISCV] Support Shadow Call Stack

asb accepted this revision. asb added a comment. I think once @jrtc27 confirms all her issues are addressed this is good to land. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84414/new/ https://reviews.llvm.org/D84414

[PATCH] D71124: [RISCV] support clang driver to select cpu

asb accepted this revision. asb added a comment. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71124/new/ https://reviews.llvm.org/D71124 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D83819: [RISCV] Add error checking for extensions missing separating underscores

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83819/new/ https://reviews.llvm.org/D83819

[PATCH] D71124: [RISCV] support clang driver to select cpu

asb added a comment. I've added some suggestions to clarify the code comments. I think before landing it would be good to address the crash Sam pointed out for an invalid -march, but otherwise I think this looks good to me (at least, it seems worth landing this and if further issues crop up we

[PATCH] D81583: Update SystemZ ABI to handle C++20 [[no_unique_address]] attribute

asb added a comment. This LGTM from a RISC-V perspective. I'll likely follow up with a RISC-V test case similar to the SystemZ one post-commit, but given this is really fixing a cross-platform ABI issue this seems non-urgent. Thanks for spotting and addressing this issue. CHANGES SINCE LAST A

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

asb added a comment. I've gone through and can't see any obvious issues. I defer to one of the RISC-V Vector extension usual suspects for giving a LGTM on the detail of the altered instructions etc. Once we have that, this looks good to land IMHO. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D71124: [RISCV] support clang driver to select cpu

asb added a comment. This has been hanging around for a while, but I think we'd basically agreed this is the right logic. The comments have ended up referring to flags that don't exist on Clang making it a little hard to follow, and I've added a request to slightly expand testing. If you make t

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

asb added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:9 +/// +/// This file describes the RISC-V instructions from the standard 'V', +/// Vector instruction set extension. Please add similar language as in RISCVInstrInfoB.td to indicate

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In D69987#2079524 , @rogfer01 wrote: > The patch as it stands now LGTM and I think it can be committed. Is there any > objection remaining? > > Any further c

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was automatically updated to reflect the committed changes. Closed by commit rG3dcfd482cb17: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets… (authored by asb). Changed

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb added a comment. In D79155#2088191 , @efriedma wrote: > Please add a comment explaining what OffsetInRecord means; then LGTM. Thanks. It's not easy to follow, but having stepped through it I agree with yu that it is the size in bits of the current r

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb added a comment. Ping on this. The patch still applies cleanly against current HEAD. @efriedma: was your comment an LGTM? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79155/new/ https://reviews.llvm.org/D79155 ___ cfe-commits mailing

[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Good catch, thanks for the fix! The logic was incorrectly written assuming `isFloatingType` would return false for complex values which is of course incorrect. Comment at: clang/

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb updated this revision to Diff 261138. asb added a comment. Updated patch to include full context. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79155/new/ https://reviews.llvm.org/D79155 Files: clang/lib/CodeGen/CGRecordLayoutBuilder.cpp clang/test/CodeGenCXX/finegrain-bitfield

[PATCH] D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

asb created this revision. asb added reviewers: wmi, hfinkel, efriedma. Herald added subscribers: cfe-commits, luismarques, sameer.abuasal, s.egerton, lenary, PkmX, simoncook. Herald added a project: clang. asb added a subscriber: apazos. As pointed out in PR45708

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

asb added a comment. I've approved D65649 now, so I think this one can land as soon as that one does. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 ___

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

asb accepted this revision. asb added a comment. LGTM, thanks Simon! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luismarques. This looks good to me, thanks James. I had a closer step through of the logic here to convince myself. Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

asb accepted this revision. asb added a comment. Please update the commit message to clarify the cases where we do deviate from the GCC defaults, but this looks good to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69383/new/ https://reviews.l

[PATCH] D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types

asb added a comment. Thanks James - won't this still leave problems for structs that need flattening? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69590/new/ https://reviews.llvm.org/D69590 ___ cfe-co

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

asb added a comment. In D67185#1707849 , @lenary wrote: > Note, D68862 is in-progress at the moment, > which is related to this patch. Indeed - Simon, could you please go through that patch and ensure that the implemen

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb added a comment. This LGTM, but given how much discussion there has been about MaxPromoteWidth it would be great to get some test coverage for it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450

[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

asb added a comment. In D65634#1618443 , @rogfer01 wrote: > Thanks @asb @lenary for the review! > > I understand that, after this change, we will also want to make > `-march=rv{32,64}gc` the default in Linux as well. Otherwise there will be an > ABI mism

[PATCH] D65693: [driver][riscv] Support riscv64-linux-gnu multiarch paths

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Many thanks for the patch. Could you please add some tests for this behaviour? I imagine you'll want to add a new directory in test/Driver/Inputs with a Debian tree skeleton. See D63497

[PATCH] D65634: [RISCV] Default to lp64d in 64-bit RISC-V Linux

asb added a comment. Thank Roger. While we're doing this, I think it would make sense to default to ilp32d on 32-bit Linux? I know the glibc support etc is less mature than for RV64, but it seems the sensible thing to do. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https

[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65500/new/ https://reviews.llvm.org/D65500

[PATCH] D60456: [RISCV] Hard float ABI support

This revision was automatically updated to reflect the committed changes. Closed by commit rL366450: [RISCV] Hard float ABI support (authored by asb, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D60456?v

[PATCH] D60456: [RISCV] Hard float ABI support

asb added a comment. Thanks for the careful review John, I really appreciate it! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60456/new/ https://reviews.llvm.org/D60456 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[PATCH] D60456: [RISCV] Hard float ABI support

asb added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9236 +if (IsInt && Field1Ty && Field1Ty->isIntegerTy()) + return false; +if (!Field1Ty) { rjmccall wrote: > asb wrote: > > rjmccall wrote: > > > The comment here is wrong because

[PATCH] D60456: [RISCV] Hard float ABI support

asb updated this revision to Diff 208477. asb marked 4 inline comments as done. asb added a comment. Tweaked a code comment. Just to confirm, @rjmccall are you happy for me to commit this? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60456/new/ https://reviews.llvm.org/D60456 Files:

[PATCH] D60456: [RISCV] Hard float ABI support

asb updated this revision to Diff 208392. asb marked an inline comment as done. asb added a comment. Updated to address comment typo picked up by @rogfer01 (thanks!). As noted in another comment, it's not entirely clear what zero-width bitfield behaviour to match (see here

[PATCH] D60456: [RISCV] Hard float ABI support

asb marked an inline comment as done. asb added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9352 +return false; + // As a quirk of the ABI, zero-width bitfields aren't ignored for fp+fp + // or int+fp structs, but are ignored for a struct with

[PATCH] D60456: [RISCV] Hard float ABI support

asb updated this revision to Diff 208308. asb marked 7 inline comments as done. asb retitled this revision from "[RISCV][WIP/RFC] Hard float ABI support" to "[RISCV] Hard float ABI support". asb edited the summary of this revision. asb added a comment. Herald added subscribers: lenary, Jim, MaskRa

[PATCH] D60456: [RISCV] Hard float ABI support

asb added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:9232 +if (IsFloat && Size > FLen) + return false; +// Can't be eligible if an integer type was already found (only fp+int or rjmccall wrote: > Is this the only consideration for

[PATCH] D63417: [RISCV] Specify registers used for exception handling

This revision was automatically updated to reflect the committed changes. Closed by commit rL365305: [RISCV] Specify registers used for exception handling (authored by asb, committed by ). Herald added subscribers: llvm-commits, lenary, MaskRay. Herald added a project: LLVM. Changed prior to comm

[PATCH] D63497: Add support for openSUSE RISC-V triple

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added a subscriber: lenary. LGTM, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63497/new/ https://reviews.llvm.org/D63497

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb added a comment. Ed, if you haven't already could you request commit access so you can commit these approved patches yourself? See https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access for details. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://revie

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb added inline comments. Comment at: test/CodeGen/builtins-riscv.c:4 + +void test_eh_return_data_regno() +{ Nit: having `{` on this line would be more consistent with usual LLVM style CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://r

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks, looks good to me! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63417/new/ https://reviews.llvm.org/D63417 ___ cfe-commits mailing lis

[PATCH] D63417: [RISCV] Specify registers used for exception handling

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Could you please add a riscv64 RUN line too, for completeness? Other archs seem to call the equivalent test file `builtins-archname.c` rather than `builtin-archname.c`, so I'd adjust the n

[PATCH] D64008: [RISCV] Avoid save-restore target feature warning

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64008/new/ https://reviews.llvm.org/D64008

[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! There was some discussion about the potential stdout+stderr merging issues http://lists.llvm.org/pipermail/llvm-dev/2017-February/110469.html but I don't think it resulted in any new

[PATCH] D57055: [RISCV] Mark TLS as supported

asb accepted this revision. asb added a comment. Herald added subscribers: Jim, benna, psnobl. LGTM, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57055/new/ https://reviews.llvm.org/D57055 ___ cfe-commits ma

[PATCH] D63497: Add support for openSUSE RISC-V triple

asb added a comment. Thanks for the contribution! I'd recommend adding a skeleton toolchain dir structure to clang/test/Driver/Inputs and adding a test to clang/test/Driver/riscv64-toolchain.c. You should be able to see examples in test/Driver/Inputs. Repository: rC Clang CHANGES SINCE LAS

[PATCH] D63498: [RISC-V] Add -msave-restore and -mno-save-restore to clang driver

asb added a comment. Can you add a CHECK line that shows the expected warning is emitted? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63498/new/ https://reviews.llvm.org/D63498 ___ cfe-commits mailin

[PATCH] D54295: [RISCV] Add inline asm constraint A for RISC-V

asb accepted this revision. asb added a comment. LGTM, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54295/new/ https://reviews.llvm.org/D54295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://

[PATCH] D60974: Clang IFSO driver action.

asb added inline comments. Comment at: cfe/trunk/lib/Frontend/CMakeLists.txt:58 clangDriver + clangIndex clangEdit plotfi wrote: > MaskRay wrote: > > This is a layering issue. clangIndex depends on clangFrontend so > > clangFrontend should not depend on c

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added a subscriber: Jim. This looks good to me, but is blocked on the dependent patch being updated. I added a minor comment on riscv-inline-asm.c Comment at: test/CodeGen/

[PATCH] D57795: [RISCV] Add FreeBSD targets

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. This looks good to me, thanks! Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57795/new/ https://reviews.llvm.org/D57795 __

[PATCH] D60456: [RISCV][WIP/RFC] Hard float ABI support

asb added inline comments. Comment at: lib/CodeGen/TargetInfo.cpp:9223 + + bool IsInt = Ty->isIntegralOrEnumerationType(); + bool IsFloat = Ty->isRealFloatingType(); rjmccall wrote: > Should this include pointers? Pointers are often interchangeably with > int

[PATCH] D60456: [RISCV][WIP/RFC] Hard float ABI support

asb updated this revision to Diff 198797. asb marked 3 inline comments as done. asb added a comment. Update: - Expanded and improved tests - Set ABI defines - Remove errant TODO - Use alignTo Still to do: - Review and test bitfield handling (which is likely incomplete) CHANGES SINCE LAST ACTI

<    1   2   3   4   >