Product info page:
http://h10025.www1.hp.com/ewfrf/wc/document?cc=us&lc=en&docname=c01486798&product=3752693
lspci -tvnn:
$ lspci -tvnn
-[:00]-+-00.0 nVidia Corporation MCP78S [GeForce 8200] Memory
Controller [10de:0754]
+-01.0 nVidia Corporation Device [10de:075e]
Monte Cabet wrote:
> -[:00]-+-00.0 nVidia Corporation MCP78S [GeForce 8200] Memory Controller
> [10de:0754]
..
> The question is if I can flash my BIOS and replace it with
> coreboot? Or is coreboot not mature enough to handle laptops and
> my mileage may vary?
coreboot currently supports a
Author: uwe
Date: Wed Nov 3 14:19:50 2010
New Revision: 6014
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6014
Log:
Clean up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs
Acked-by: Uwe Hermann
On Tue, Nov 02, 2010 at 10:32:39PM +0100, Nils wrote:
> This patch cleans up some comments and white space in gx2/northbridgeinit.c
> and gx2/raminit.c.
>
> Signed-off-by: Nils Jacobs
Thanks, r6014 with some further cosmetic fixes I noticed.
Uwe.
--
http://hermann-uwe.de | http://sigrok.
Author: uwe
Date: Wed Nov 3 14:21:41 2010
New Revision: 6015
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6015
Log:
Clean up some more comments and white space in model_gx2/cpureginit.c.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs
Acked-by: Uwe Hermann
Modified:
On Tue, Nov 02, 2010 at 10:32:59PM +0100, Nils wrote:
> This patch cleans up some more comments and white space in
> model_gx2/cpureginit.c .
>
> Signed-off-by: Nils Jacobs
Thanks, r6015. Minor request, please drop the "This patch ..." from the
patch descriptions, just say directly what it doe
Author: uwe
Date: Wed Nov 3 14:24:29 2010
New Revision: 6016
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6016
Log:
Remove some unused code from gx2/raminit.c.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs
Acked-by: Uwe Hermann
Modified:
trunk/src/northbridge/amd
On Tue, Nov 02, 2010 at 10:33:53PM +0100, Nils wrote:
> This patch removes some unused code from gx2/raminit.c .
>
> Signed-off-by: Nils Jacobs
Thanks, r6016.
Uwe.
--
http://hermann-uwe.de | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
--
coreboot
Rudolf Marek wrote:
> On 29.10.2010 13:59, Tobias Diedrich wrote:
>> Instead of duplicating the pci_locate_device calls multiple times,
>> add a get_vt8237_lpc() function.
>
> Yeah nice idea! Can I get separate patch for that? In the meanwhile do we
> need to call the enablefidvid for "A" ? I thin
On Tue, Nov 02, 2010 at 11:20:43PM +0100, Uwe Hermann wrote:
> I don't object to the patch, and we should probably fix this in all
> other southbridges, I think the same problem applies there.
>
> But: the die() call itself also does a printk(), so that'll still hang
> if the error path is chosen
Rudolf Marek wrote:
> On 29.10.2010 14:14, Tobias Diedrich wrote:
>> This adds the m2v directory to src/mainboards/asus and adjusts the Kconfig.
>> Note:
>>
>> I added pci irq routing setup based on pirq tables:
>> pci_fixup_irqs() in irq_tables.c
>>
>> I didn't see any existing functionality that
Hello, I looked over the F71889 Fintek datasheet, and its very similar to the
F71863FG I noticed. I used sed to replace some of the names around and such. I
haven't tested it, nor will I, since I have little to no experience with
flashing devices, and have no back-up (can't recover) and I do hav
Hi Scott,
I am not totally convinced that all changes are a net win.
On 03.11.2010 05:29, Scott Duplichan wrote:
> (Re-submitting with correction to GFX debug bar setup procedure needed
> for use with AMD family 0Fh processor).
>
> This patch solves crashes and BSODs that occur when booting Win7
Rudolf Marek wrote:
> Hi,
>
> I think following is not true. The VT8237A has something else at 0x50, so
> vt8237_sb_enable_fid_vid should not be neccessary to call. Do you call it
> or not? If not then we either need to fix it for the "old" location 0x11
> iirc or not to put there any test for A
Rudolf Marek wrote:
>> +if (!devfun7)
>> +return;
>> +
>> +/*
>> + * This init code is valid only for the VT8237A! For different
>> + * sounthbridges (e.g. VT8237S, VT8237R (without plus R)
>
> typo :) maybe was just copied? Did you get the values from orig bios? Or
> j
Rudolf Marek wrote:
>> -/* ROM memory cycles go to LPC. */
>> +/* Only ROM memory cycles go to LPC. */
>
> I think it should be,
>
> > + /* Only memory ROM cycles go to LPC. */
>
> Because this bit is telling if all memory cycles should go to LPC or just
> those from ROM range. Please t
Tobias Diedrich wrote:
> >> + /*
> >> + * Northbridge pcie bridge 3.3 is not connected to anything, hide it.
> >> + */
> >> + tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
> >> + tmp&= ~0x10; /* hide pcie bridge 0:3.3 */
> >> + tmp&= ~0x40; /* hide scratch register function 0
Signed-off-by: Alec Ari
--- On Wed, 11/3/10, Neo The User wrote:
> From: Neo The User
> Subject: F71889 Super I/O patch
> To: coreboot@coreboot.org
> Date: Wednesday, November 3, 2010, 5:55 PM
> Hello, I looked over the F71889
> Fintek datasheet, and its very similar to the F71863FG I
> notic
Peter Stuge wrote:
> Tobias Diedrich wrote:
> > >> +/*
> > >> + * Northbridge pcie bridge 3.3 is not connected to anything,
> > >> hide it.
> > >> + */
> > >> +tmp = pci_cf8_conf1.read8(NULL, 0, PCI_DEVFN(0x0, 5), 0xf0);
> > >> +tmp&= ~0x10; /* hide pcie bri
Op woensdag 3 november 2010 14:20:31 schreef u:
> Thanks, r6014 with some further cosmetic fixes I noticed.
>
>
> Uwe.
Thanks for the fast review and commit.
Nils.
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Hello,
please advise on EPIA 800 board hanging after northbridge initialisation. I
checked against chipset datasheet and working AWARD dump - the northbridge
SDRAM configuration registers are correctly set. There are no errors in
memory test, I can induce errors in memory test for example with wr
Hi Uwe,
Op woensdag 3 november 2010 14:23:36 schreef u:
>Thanks, r6015
Thanks for the fast review and commit.
> "Clean up stuff" looks better than "This patch cleans up stuff" in svn
> logs.
OK will do better next time.
Thanks, Nils.
--
coreboot mailing list: coreboot@coreboot.org
http://www.co
> Is this rom structure reasonable (missing fallback/romstage?):
It's fine. The romstage (boot block) isn't part of CBFS.
> Loading stage image.
> Check CBFS header at
Normally a hang here means that the whole ROM isn't mapped, so trying
to read from the top of the ROM hangs, even though the bo
Uwe wrote,
Op woensdag 3 november 2010 14:24:47 schreef u:
> Thanks, r6016.
Thanks for the fast review and commit.
Nils.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Ranges unavailable for PCI BARs should be marked as reserved in the E820
memory map, in case the OS wants to change the BARs.
This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm no
-Original Message-
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2...@gmx.net]
Sent: Wednesday, November 03, 2010 01:14 PM
To: Scott Duplichan
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
(revised)
]Hi Scott,
]
]I am
Hi Scott,
I tried to boot with that on famF CPU and it went well.
ruiktest:~#
ruiktest:~# lspci -vvv -s 01:05.0
01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200]
(prog-if 00 [VGA controller])
Subsystem: ATI Technologies Inc Device
Control: I/O+ Mem+ B
Author: uwe
Date: Wed Nov 3 22:46:41 2010
New Revision: 6017
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6017
Log:
Add Fintek F71889 Super I/O support.
Untested, but should work mostly (even though some TODOs remain).
Signed-off-by: Alec Ari
Acked-by: Uwe Hermann
Added:
trun
On Wed, Nov 03, 2010 at 12:18:56PM -0700, Neo The User wrote:
> Signed-off-by: Alec Ari
Thanks, committed in r6017 with a few changes:
- Changed unsigned int etc. to u8/u16 etc. everywhere.
- Add the missing LDNs as per datasheet to f71889.h and added superio.c
code to handle the devices (
Since XP only implements parts of ACPI 2.0, it chokes on the TOM2 qword in the
SSDT, which is present if a board uses k8acpi_write_vars.
With the acpigen_write_name_qword("TOM2"... in place I get a
Stop A5 (0x11, 0x8, , )
bluescreen on boot.
This patch replaces the qword with a dword, which conta
Hi,
I just want to tell "me too", so question is we go to direction of claiming less
ram_resource as intel do or others.
Is the AMD uma limited to < 4GB?
Thanks,
Rudolf
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Remove banner wrapper function and unify print(k).
Signed-off-by: Nils Jacobs
The banner part was requested by Uwe.
This is Abuild and boot tested.
Thanks, Nils.
Index: src/northbridge/amd/gx2/raminit.c
===
--- src/northbridge/amd
On Wed, Nov 3, 2010 at 3:34 PM, Rudolf Marek wrote:
> Hi Scott,
>
> I tried to boot with that on famF CPU and it went well.
> ruiktest:~#
> ruiktest:~# lspci -vvv -s 01:05.0
>
> 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD
> 4200] (prog-if 00 [VGA controller])
>
2010/11/4 Nils
> Remove banner wrapper function and unify print(k).
>
Index: src/northbridge/amd/gx2/raminit.c
> ===
> --- src/northbridge/amd/gx2/raminit.c(revision 6017)
> +++ src/northbridge/amd/gx2/raminit.c(working copy
On Wed, Nov 03, 2010 at 03:00:54PM -0600, Myles Watson wrote:
> > Is this rom structure reasonable (missing fallback/romstage?):
> It's fine. The romstage (boot block) isn't part of CBFS.
>
>
> > Loading stage image.
> > Check CBFS header at
> Normally a hang here means that the whole ROM isn't
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Marc Jones
Sent: Wednesday, November 03, 2010 06:53 PM
To: Rudolf Marek
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
(revise
Sent from my mobile phone
On 03.11.2010, at 09:56, Ward Vandewege wrote:
> On Tue, Nov 02, 2010 at 11:20:43PM +0100, Uwe Hermann wrote:
>> I don't object to the patch, and we should probably fix this in all
>> other southbridges, I think the same problem applies there.
>>
>> But: the die() ca
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