Marc Jones wrote:
]Hi Scott,
]
]I'm acking and committing all except the LTO patch, which should wait
]for the crossgcc changes for gcc4.6. i only made a minor tweak to the
]AHCI patch to add a #define for the PCI DID.
Thanks Marc. I noticed the PCI ID also, how embarrassing! I will test
everythi
]Peter Stuge wrote:
]
]Reading this I think that there should be a Kconfig option to choose
]if the chipset should be set up as SATA IDE or AHCI.
]
]Talking to a lot of visitors at LinuxTag it is absolutely clear that
]this is an example of what should actually be an NVRAM option.
]
]Do we have som
Stefan Reinauer wrote:
]>> + // all cores: allow caching of flash chip code and data
]>> + // (there are no cache-as-ram reliability concerns with family 14h)
]>> + __writemsr (0x20c, (0x01ull - CONFIG_ROM_SIZE) | 5);
]>> + __writemsr (0x20d, (0x10ull - CONFIG_ROM_SIZE) | 0x800
Peter Stuge wrote:
]> +__outdword (0xcf8, 0x8000a3b8);
]> +__outdword (0xcfc, __indword (0xcfc) | 0 << 24);
]> +}
]
]PCI function? And maybe this, as well as the 33MHz setup, is good to
]have in the chipset code, as opposed to duplicated per mainboard?
Hello Peter,
I will try improve
Cristi Magherusan wrote:
> Signed-off-by: Cristian Magherusan-Stanciu
Skip the distclean target for now since it's not being called anyway,
and since the unpacked tarballs should also be cleaned up somehow.
(How?)
Acked-by: Peter Stuge
r6598
--
coreboot mailing list: coreboot@coreboot.org
ht
Author: stuge
Date: Mon May 16 03:35:03 2011
New Revision: 6598
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6598
Log:
Add crossgcc target to automatically build reference toolchain
This means that a simple:
$ make crossgcc
creates the reference toolchain in the correct directory.
Please see the patch below.
Signed-off-by: Cristian Magherusan-Stanciu
diff --git a/Makefile b/Makefile
index ac7115d..69e32a4 100644
--- a/Makefile
+++ b/Makefile
@@ -242,6 +242,12 @@ $(shell mkdir -p $(obj) $(objutil)/kconfig/lxdialog
$(additional-dirs) $(alldirs
cscope:
cscope -bR
+
On 5/15/11 3:57 PM, Peter Stuge wrote:
repository service wrote:
+++ trunk/src/mainboard/amd/persimmon/romstage.cSun May 15 23:54:04
2011(r6584)
..
+ // early enable of PrefetchEnSPIFromHost
+ if (boot_cpu())
+{
+__outdword (0xcf8, 0x8000a3b8);
+__outdword (0xcfc
repository service wrote:
> Log:
> Enable SPI cacheline prefetch early to reduce boot time.
This is the same commit message as the previous commit, r6584.
..
> +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:56:03
> 2011(r6585)
> @@ -50,6 +50,21 @@
>// all cores:
On 5/15/11 4:52 PM, Peter Stuge wrote:
repository service wrote:
Log:
Enable rom cache early to reduce boot time.
+++ trunk/src/mainboard/amd/persimmon/romstage.cMon May 16 00:06:09
2011(r6591)
@@ -47,6 +47,11 @@
u32 val;
u8 reg8;
+ // all cores: allow caching of flash
Author: stuge
Date: Mon May 16 02:05:50 2011
New Revision: 6597
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6597
Log:
cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
Signed-off-by: Peter Stuge
Acked-by: Peter Stuge
Modified:
trunk/src/southbridge/amd/cimx_wrapper/sb800
repository service wrote:
> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Mon May 16
> 00:07:56 2011(r6592)
..
> @@ -414,15 +413,16 @@
> break;
>
> case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
> + sb_config->PORTCONFIG[0].PortCfg.PortPresent = d
repository service wrote:
> Log:
> Enable rom cache early to reduce boot time.
> +++ trunk/src/mainboard/amd/persimmon/romstage.c Mon May 16 00:06:09
> 2011(r6591)
> @@ -47,6 +47,11 @@
>u32 val;
>u8 reg8;
>
> + // all cores: allow caching of flash chip code and data
> + /
Hi,
repository service wrote:
> Enable AHCI mode and hide IDE controller
..
> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.cSun May 15
> 23:38:08 2011(r6579)
> @@ -83,7 +83,7 @@
> sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
> sb_config->SATA
On Sun, May 15, 2011 at 4:51 PM, Peter Stuge wrote:
> repository service wrote:
>> Move mmconf base from e000 to f800
> ..
>> +++ trunk/src/mainboard/amd/persimmon/dsdt.asl Sun May 15 23:26:04
>> 2011 (r6578)
>> @@ -36,7 +36,7 @@
>> Name(PBAD, 0x0) /* Address of BIOS a
Author: mjones
Date: Mon May 16 01:13:54 2011
New Revision: 6596
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6596
Log:
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Marc Jones
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/dsdt.
Good example of whitespace changes making it a bit difficult to see
the actual change. :\
repository service wrote:
> +++ trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:05:00
> 2011(r6590)
//Peter
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org
repository service wrote:
> Log:
> .. agesa options
> +++ trunk/src/mainboard/amd/persimmon/buildOpts.c Mon May 16 00:03:45
> 2011(r6589)
> @@ -80,16 +80,16 @@
> #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
>
> #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
> -//#define
repository service wrote:
> +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:54:04
> 2011(r6584)
..
> + // early enable of PrefetchEnSPIFromHost
> + if (boot_cpu())
> +{
> +__outdword (0xcf8, 0x8000a3b8);
> +__outdword (0xcfc, __indword (0xcfc) | 0 << 24);
repository service wrote:
> +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:48:22
> 2011(r6582)
..
> +volatile u32 *spiBase = (void *) 0xa000;
> +u32 save;
> +__outdword (0xcf8, 0x8000a3a0);
> +save = __indword (0xcfc);
> +__outdword (0xcfc, (u32
repository service wrote:
> Move mmconf base from e000 to f800
..
> +++ trunk/src/mainboard/amd/persimmon/dsdt.aslSun May 15 23:26:04
> 2011(r6578)
> @@ -36,7 +36,7 @@
> Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
> Name(PBLN, 0x0) /* L
Author: stuge
Date: Mon May 16 00:40:40 2011
New Revision: 6595
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6595
Log:
agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge
Acked-by: Peter Stuge
Modified:
trunk/src/northbridge/amd/agesa_wrapper/fam
On Sat, Apr 30, 2011 at 3:10 AM, Scott Duplichan wrote:
> The attached changes for the AMD Persimmon board improve OS support and
> reduce boot time.
> DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can
> install from
> DVD and boot from hard disk.
>
> Signed-off-by: Scott D
Author: mjones
Date: Mon May 16 00:10:15 2011
New Revision: 6594
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6594
Log:
Cosmetic cleanup.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
trunk/src/include/
Author: mjones
Date: Mon May 16 00:09:09 2011
New Revision: 6593
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6593
Log:
1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd
Author: mjones
Date: Mon May 16 00:07:56 2011
New Revision: 6592
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6592
Log:
Update gpp port configuration.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/devicetree.cb
trunk/src/sout
Author: mjones
Date: Mon May 16 00:06:09 2011
New Revision: 6591
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6591
Log:
Enable rom cache early to reduce boot time.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/agesawrapper.c
Author: mjones
Date: Mon May 16 00:05:00 2011
New Revision: 6590
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6590
Log:
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/
Author: mjones
Date: Mon May 16 00:03:45 2011
New Revision: 6589
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6589
Log:
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/b
Author: mjones
Date: Mon May 16 00:02:27 2011
New Revision: 6588
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6588
Log:
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainbo
Author: mjones
Date: Mon May 16 00:00:23 2011
New Revision: 6587
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6587
Log:
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/dsd
Author: mjones
Date: Sun May 15 23:59:19 2011
New Revision: 6586
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6586
Log:
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/
Author: mjones
Date: Sun May 15 23:56:03 2011
New Revision: 6585
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6585
Log:
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/romst
Author: mjones
Date: Sun May 15 23:54:04 2011
New Revision: 6584
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6584
Log:
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/romst
Author: mjones
Date: Sun May 15 23:51:31 2011
New Revision: 6583
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6583
Log:
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/
Author: mjones
Date: Sun May 15 23:48:22 2011
New Revision: 6582
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6582
Log:
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/ro
Author: mjones
Date: Sun May 15 23:45:46 2011
New Revision: 6581
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6581
Log:
Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/northbrid
Author: mjones
Date: Sun May 15 23:41:00 2011
New Revision: 6580
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6580
Log:
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
Modified: trunk/sr
Author: mjones
Date: Sun May 15 23:38:08 2011
New Revision: 6579
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6579
Log:
Enable AHCI mode and hide IDE controller to reduce boot time.
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/m
Author: mjones
Date: Sun May 15 23:26:04 2011
New Revision: 6578
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6578
Log:
Move mmconf base from e000 to f800 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/a
Author: mjones
Date: Sun May 15 23:19:54 2011
New Revision: 6577
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6577
Log:
Fix ACPI shutdown function by removing reliance on SMI.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/vendorcode/amd/cimx/sb800/OEM.
Author: mjones
Date: Sun May 15 23:18:59 2011
New Revision: 6576
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6576
Log:
Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/southbridge/amd/cimx_wrapper/sb80
Author: mjones
Date: Sun May 15 23:13:00 2011
New Revision: 6575
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6575
Log:
Match DIMM SPD addressing to implemented slots.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/dimmSpd.c
Mod
Author: mjones
Date: Sun May 15 23:11:41 2011
New Revision: 6574
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6574
Log:
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/mainboard/amd/persimmon/agesawrappe
Author: mjones
Date: Sun May 15 23:10:20 2011
New Revision: 6573
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6573
Log:
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfff to fecf.
3) Add AMD recommended non-posted mapping for SB
Author: mjones
Date: Sun May 15 23:07:43 2011
New Revision: 6572
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6572
Log:
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
t
Author: mjones
Date: Sun May 15 23:06:30 2011
New Revision: 6571
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6571
Log:
Correct the number of MCA error reporting banks cleared.
Signed-off-by: Scott Duplichan
Acked-by: Marc Jones
Modified:
trunk/src/cpu/amd/agesa_wrapper/family1
Author: mjones
Date: Sun May 15 23:01:42 2011
New Revision: 6570
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6570
Log:
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code
handles it.
Signed-
Hi all,
Sorry for the delay. I'm adding some of mine ideas for the discussion. What I
like on u-boot is interactive command line ;) this is why I started to tickle this.
The coreboot + u-boot is a win for u-boot because it can run on then on any
coreboot supported board (including QEMU).
Fr
Hello everybody,
I'm a newbe in this question. And english is not my native language. So,
sorry for stupid and smooth questions..
I have a motherboard (epox 9NPA3I / 9NPA3J / 9NPAJ-3 / 9NPA3 Ultra Series)
which is not supported 4GB memory.. at least in 4x1GB variant.
I thinked may be it is softw
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