The output of uname on my MacOS.
# uname -a
Darwin Baos-Mac-Pro.local 13.0.0 Darwin Kernel Version 13.0.0: суббота, 9
ноября 2013 г. 02:42:04 (MSK);
root:xnu-2422.1.72_by_bronya_sinetek_anv_rc7/BUILD/obj/RELEASE_X86_64 x86_64
Gcc version:
# gcc --version
Configured with: --prefix=/Library/Deve
You can remove the -Werror
In util/cbfstool/Makefile.inc
Try again.
Zheng.
> -Original Message-
> From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Kurt Qiao
> Sent: Wednesday, September 09, 2015 5:43 PM
> To: coreboot@coreboot.org
> Subject: [coreboot] [help]build cbfsto
I am porting the coreboot to a platform with a new AMD APU, which is close to
Kabini and Mullins.
Now the board can boot Ubuntu and Windows 7. But it failed to boot Windows 8.
It crashes at a very early stage, which seems to be Windows bootloader. The
debug message of SeaBIOS is attached.
The in
I am porting the coreboot to a platform with a new AMD APU, which is close to
Kabini and Mullins.
Now the board can boot Ubuntu and Windows 7. But it failed to boot Windows 8.
It crashes at a very early stage, which seems to be Windows bootloader. The
debug message of SeaBIOS
is attached.
The in
I am porting the coreboot to a platform with a new AMD APU, which is close to
Kabini and Mullins.
Now the board can boot Ubuntu and Windows 7. But it failed to boot Windows 8.
It crashes at a very early stage, which seems to be Windows bootloader. The
debug message of SeaBIOS is attached.
The in
be Fm2,
Fp2, or Fs1.
Zheng
> -Original Message-
> From: Rudolf Marek [mailto:r.ma...@assembler.cz]
> Sent: Thursday, November 07, 2013 7:58 PM
> To: Bao, Zheng; 'Coreboot'
> Subject: Re: [coreboot] AMD Richland support?
>
> Hi Zheng,
>
> >Richl
Richland has its own AGESA package. It is not ported yet.
I assume the current fam15tn code doesn't support Richland.
Zheng
> -Original Message-
> From: coreboot-bounces+zheng.bao=amd@coreboot.org [mailto:coreboot-
> bounces+zheng.bao=amd@coreboot.org] On Behalf Of Rudolf Marek
>
.@se-eng.com; Martin Roth; Bao,
> Zheng
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] AGESA: RunLateApTaskOnAllAPs(..) function and
> ProbeFilter
>
> On Thu, Mar 7, 2013 at 9:53 AM, §Ў§Э§С§Х§н§к§Ц§У §¬§а§Я§г§д§С§Я§д§Ъ§Я
> wrote:
> >
> > AGESA code have two m
, 2012 12:19 PM
To: Bao, Zheng
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] git push by http failed.
what's your git config ?
Best wishes
QingPei Wang
Phone: 86+018930528086
On Tue, Aug 21, 2012 at 10:54 AM, Bao, Zheng wrote:
RPC failed; result=22, HTTP code = 500
--
coreboot mailing
Hi, All,
If I run git push, it says,
$ git push
Counting objects: 9, done.
Delta compression using up to 4 threads.
Compressing objects: 100% (5/5), done.
Writing objects: 100% (5/5), 499 bytes, done.
Total 5 (delta 4), reused 0 (delta 0)
error: RPC failed; result=22, HTTP code = 500
fatal: The re
Hi, Stefan & folks,
Is it just me or do you guys have the same problem when clone the code via http?
#git clone http://[:@]review.coreboot.org/p/coreboot.git
Initialized empty Git repository in /home/baozheng/LinuxBIOS/temp/coreboot/.git/
error: The requested URL returned error: 503 while accessing
Hi, Andy,
The persimmon board I have got doesn't have any PCIe slot or onboard PCIe
device attached to SB800. And I am wondering if you actually use a inagua
board, which has the same APU & SB with persimmon and 2 minipcie slots other
than that.
Let us assume you are testing on Inagua.
Here is
Hi, Martin,
Are you test on persimmon or other board which is quite close it?
I guess, just guess, have you checked the input clkin in F81865? It has two
options, 48MHz or 24MHz.
You should set in superio register based on the actual input clock freq.
Zheng (Joe)
> -Original Message-
I tried. It behaves as bad as wbinvd does.
Joe
> -Original Message-
> From: Andrew Goodbody [mailto:ajg4tadp...@gmail.com]
> Sent: Tuesday, April 10, 2012 7:04 PM
> To: Bao, Zheng
> Cc: 'Marc Jones'; Marc Jones; 'coreboot@coreboot.org'
> Subject: Re:
Hi,
It is unstable. In most cases, it hangs at this wbinvd. Once it pass that
instruction, it will hang at when AP cores are launched.
Joe
> -Original Message-
> From: Marc Jones [mailto:marcj...@gmail.com]
> Sent: Friday, April 06, 2012 11:27 PM
> To: Bao, Zheng
&g
Actually, it hurts my board.
AMD trinity fam15 + Hudson.
Zheng
> -Original Message-
> From: coreboot-boun...@coreboot.org [mailto:coreboot-
> boun...@coreboot.org] On Behalf Of ger...@coreboot.org
> Sent: Friday, April 06, 2012 5:03 AM
> To: coreboot@coreboot.org
> Subject: [coreboot] Pa
PM
> To: Bao, Zheng
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] Can we push using http user/password
> authentication
>
> On Fri, Mar 23, 2012 at 07:33, Bao, Zheng wrote:
> > Hi,
> > These commits are uploaded at my home by ssh:29418. In our lab, it is
&
pk
> Sent: Friday, March 23, 2012 2:11 PM
> To: coreboot@coreboot.org
> Subject: Re: [coreboot] Can we push using http user/password
> authentication
>
> On 2012-03-23 04:31, Bao, Zheng wrote:
> > Hi,
> > In our lab, we need to get access the repository
> >by http b
Hi,
In our lab, we need to get access the repository by http because of the
firewall. I tried to push my commit through http. It didn't say anything wrong.
But I cannot see my change on gerrit. I am wondering if http really works. Does
it?
Zheng
--
coreboot mailing list: coreboot@coreboot.or
Hi,
I tried to change my username for accessing the repository. In
http://review.coreboot.org/#settings
the username, which is bound to my OpenID and was accidentally set as a
silly name, is unchangeable.
Any chance that I can change it?
Zheng
--
coreboot mailing list: coreboot@coreboot.org
ht
Hi, All,
We are building a build machine, which is connect the AMD network with a
firewall. We need to provide the IP address and port(29418) of
coreboot.org to access the git server. It doesn't work yet.
I am wondering if the OpenID needs extra website address and port to
check the authorization.
>
> On 4/21/11 12:53 AM, Bao, Zheng wrote:
> > Hi, All,
> > Since we can only access the code tree via a firewall, I need to
give
> > the IP address I need to access to the administrator. But the
> seabios
> > git server just seems to have changed, hasn't it?
Hi, All,
Since we can only access the code tree via a firewall, I need to give
the IP address I need to access to the administrator. But the seabios
git server just seems to have changed, hasn't it? Actually I am pretty
sure it has and I can resolve the IP address. What I am wondering is
whether i
The "temp" will be used later. So it has to be calculated correctly.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdht/h3ncmn.c
===
--- src/northbridge/amd/amdht/h3ncmn.c (revision 6512)
+++ src/northbridge/amd/amdht/h3nc
Sorry. I missed some files to diff. Resent it.
Zheng
> -Original Message-
> From: Marc Jones [mailto:marcj...@gmail.com]
> Sent: Friday, March 25, 2011 9:18 AM
> To: Bao, Zheng
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] [PATCH 5/7] SuperMicro H8SCM support
Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
Signed-off-by: Zheng Bao
sb700_to_sb7xx_51xx.patch
Description: sb700_to_sb7xx_51xx.patch
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Add AMD C32 support.
It is based on other existing Fam10 code.
Signed-off-by: Zheng Bao
amd_c32.patch
Description: amd_c32.patch
--
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amd_sr5650_sp5100_add_entries.patch
Description: amd_sr5650_sp5100_add_entries.patch
--
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http://www.coreboot.org/mailman/listinfo/coreboot
This is for board Supermicro H8scm. The code was done by existing chips
and
superiotool.
WPCM450 is more like an EC. SuperIO is just a part of multi-features.
Signed-off-by: Zheng Bao
superio_nuvoton_wpcm450.patch
Description: superio_nuvoton_wpcm450.patch
--
coreboot mailing list: coreboot
SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.
Signed-off-by: Zheng Bao
amd_southbridge_sp5100.patch
Description: amd_southbridge_sp5100.patch
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I have \_S4 in my dsdt.asl. But the dmesg only reports:
ACPI: (supports S0 S1 S2 S3 S5)
And cat /sys/power/state only says:
Standby mem
So what else is needed?
Thanks.
Zheng
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In src/arch/x86/Makefile.bootblock.inc:
###
75 # Build the romstage
76 $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs)
$(obj)/romstage/ldscript.ld
77 @printf "LINK $(subst $(obj)/,,$(@))\n"
78
to .rom.text. But I don't think it is worth to do such a
complicated job.
Zheng
-Original Message-
From: Marc Jones [mailto:marcj...@gmail.com]
Sent: Wednesday, February 23, 2011 5:25 AM
To: Bao, Zheng
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Add .text into romstage s
The text sections in *.romstage.o are called .text instead of .rom.text.
The .text can be built in, but the _erom cannot be calculated correctly
without this patch. Nobody uses _erom currently, so nobody seems cares
it.
Signed-off-by: Zheng Bao
Index: src/arch/x86/init/ldscript_fallback
[coreboot] what if some mainboard use that function,
others
> dont
>
> Bao, Zheng wrote:
> > I need to add some functions in early_setup.c of southbridge, sb700,
for
> > example. But some other mainboards don't use those functions. Given
the
> > Werror in Makefile, I can
.
Zheng
> -Original Message-
> From: Stefan Reinauer [mailto:stefan.reina...@coreboot.org]
> Sent: Thursday, January 20, 2011 2:36 AM
> To: Bao, Zheng
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] [patch] AMDMCT DDR3 fix Dual rank + high mem
> frequency.
>
>
I need to add some functions in early_setup.c of southbridge, sb700, for
example. But some other mainboards don't use those functions. Given the
Werror in Makefile, I can't make these 2 cases pass the compiling both.
What is the resolution? Do I have to add a configuration in mainboard
Kconfig for
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
pDCTstat->PresetmaxFreq = 800;
}
> -Original Message-
> From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
> On Behalf Of Scott Duplichan
> Sent: Tuesday, January 11, 2011 11:03 AM
> To: Bao, Zheng; coreboot@coreboot.org
> Subject: Re: [coreboot] sb800 code derived from sb
I boot my board (Fam10/RS780/SB700) with coreboot. Sometimes it hangs at
a place where it seems to a multi-core initialization. Before I debug
this, could anyone give me a hint?
Dmesg is below.
Zheng
coreboot-4.0-r964:968M Mon Jan 10 17:17:17 CST 2011 starting...
BSP Family_Model: 00100f81
*s
The code is tested on my board with register DIMMs. More tests need to
be
done. Please send the testing report.
Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.
Signed-off-by: Zheng Bao
Index: src/northbridg
You can run superiotool to find out the logical device number (LDN) of
each device. That is the way if we don't have the datasheet.
Zheng
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of ali hagigat
> Sent: Wednesday, January
Add detection of Nuvoton WPCM450.
Signed-off-by: Zheng Bao
Index: util/superiotool/nuvoton.c
===
--- util/superiotool/nuvoton.c (revision 6221)
+++ util/superiotool/nuvoton.c (working copy)
@@ -64,6 +64,8 @@
Add RS785(RS880) support. Just few pci_ids.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/rs780/gfx.c
===
--- src/southbridge/amd/rs780/gfx.c (revision 6204)
+++ src/southbridge/amd/rs780/gfx.c (working copy)
@@ -26,6
datasheet when
they conflict.
Zheng
> -Original Message-
> From: Uwe Hermann [mailto:u...@hermann-uwe.de]
> Sent: Tuesday, December 14, 2010 10:05 AM
> To: Bao, Zheng
> Cc: Stefan Reinauer; Scott Duplichan; Peter Stuge;
coreboot@coreboot.org
> Subject: Re: [coreboo
The datasheet is available on nuvoton's website.
http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=cf
73485c-9e0a-4218-9bee-89dfe9a7bb87
Signed-off-by: Zheng Bao
Index: util/superiotool/winbond.c
===
--- util/s
Set the ROMSIZE as 4MB.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/sb600/Kconfig
===
--- src/southbridge/amd/sb600/Kconfig (revision 6169)
+++ src/southbridge/amd/sb600/Kconfig (working copy)
@@ -23,6 +23,11 @@
Running result.
superiotool r6131
Found Winbond W83527HG (id=0xb0, rev=0x73) at 0x2e
The documentation is not available yet.
Signed-off-by: Zheng Bao
Index: util/superiotool/winbond.c
===
--- util/superiotool/winbond.c (revision
ck Georgi
> Sent: Friday, December 10, 2010 8:58 PM
> To: coreboot@coreboot.org
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
>
> Am 10.12.2010 13:29, schrieb Bao, Zheng:
> >> How about
> >> pci_write_config16(dev, 0x6c,
> >&
Sent: Friday, December 10, 2010 8:10 PM
> To: coreboot@coreboot.org
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
>
> Am 10.12.2010 13:02, schrieb Bao, Zheng:
> > Set the register based on the ROMSIZE.
>
> > @@ -57,8 +57,18 @@
> > * Ena
Set the register based on the ROMSIZE.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/sb600/Kconfig
===
--- src/southbridge/amd/sb600/Kconfig (revision 6159)
+++ src/southbridge/amd/sb600/Kconfig (working copy)
@@ -23,6 +23
Before lane reversal,
De-asserts STRAP_BIF_all_valid for PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for PCIE-GFX core.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/rs780/rs780_gfx.c
===
--- src/southbridg
More explicite and straight way to set seed.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdmct/mct/mctsrc.c
===
--- src/northbridge/amd/amdmct/mct/mctsrc.c (revision 6135)
+++ src/northbridge/amd/amdmct/mct/mctsrc.c
But there would be nothing on the screen if no payload is attached. That
would be confusing when the board is still in debug stage.
Zheng
From: coreboot-bounces+zheng.bao=amd@coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Be
According to the description in datasheet of f71889,
"To enable configuration, the entry key 0x87 must be written to
the index port"
"
-o 4e 87
-o 4e 87 (enable configuration)
-o 4e aa (disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
superiotool_fintek_f81865_id.patch
Description: superiotool_fintek_f81865_id.patch
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现在急需300元的体育用品发票，可在超市，屈臣式等手写发票的地方开，如果你没有办法解决，
可在舞美买个暖风机。
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I checked the code and found a stupid bug.
I wonder if it can fix your problem.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/rs780/rs780_cmn.c
===
--- src/southbridge/amd/rs780/rs780_cmn.c (revision 5926)
+++ src/southbrid
essage-
> From: coreboot-bounces+zheng.bao=amd@coreboot.org
[mailto:coreboot-
> bounces+zheng.bao=amd@coreboot.org] On Behalf Of Bao, Zheng
> Sent: Saturday, October 09, 2010 10:37 AM
> To: Coreboot
> Subject: [coreboot] [patch]: Remove
src/northbridge/amd/amdmct/mct/
Remove src/northbridge/amd/amdmct/mct/mct.h, which is not used any more.
No attached patches to reduce confusing.
Signed-off-by: Zheng Bao
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The following words are got from SB700 rpr. It seems that the phy
settings have something to do with the eSATA.
SATA_PCI_config
0x01B48017
SATA_PCI_config
0x01B48019
SATA_PCI_config
0x01B48016
SATA_PCI_config
0x01B48016
SATA_PCI_config
0x01B48016
SATA_PCI_config
0x01B48016
SATA GENI PHY ports set
Complete the code which was missing.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdmct/mct/mct_d.c
===
--- src/northbridge/amd/amdmct/mct/mct_d.c (revision 5818)
+++ src/northbridge/amd/amdmct/mct/mct_d.c (workin
Fix the typo. Field DisAutoRefresh is in DramTimngHi.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
===
--- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c (revision 5818)
+++ src/northbridge/amd/amdmct/mct
Please see the log when the mahogany_fam10 was created. That is r5221.
That is the problem located in folder amdht, which is about HT
initialization of Family 10.
Zheng
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of Warren
Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
===
--- src/northbridge/amd/amdmct/mct_ddr3/mct
Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
===
--- src/northbridge/amd/amdmct/mct_ddr3/mct_
Acked-by: Zheng Bao
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Qing Pei Wang
Sent: Wednesday, August 18, 2010 9:29 AM
To: Coreboot
Subject: [coreboot] [PATCH]pa78vm5 dev3
hi all
the attach file add pa78
It should be Signed-off-by: Kerry She
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of repository service
> Sent: Tuesday, August 17, 2010 10:15 AM
> To: coreboot@coreboot.org
> Subject: [coreboot] [commit] r5703 - trunk/src
The tilapia can configured as dual slot or single slot. It depends on
whether one device is behind the gfx slot 2(dev 3). And tilapia provides
a easy way to detect this, instead of the whole training process. In
this case, we define the gfx_dual_slot as 2, which means it should be
detected.
Zheng
Acked-by: Zheng Bao
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Qing Pei Wang
Sent: Monday, August 16, 2010 3:18 PM
To: Coreboot
Subject: [coreboot] RS780 dev3 detection
hi all,
tilapila support both dual sl
Acked-by: Zheng Bao zheng@amd.com
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Qing Pei Wang
Sent: Monday, August 16, 2010 3:18 PM
To: Coreboot
Subject: [coreboot] RS780 dev3 detection
hi all,
tilapila
Please add Signed-off-by line in the mail text instead of the
attachment.
feature Lane reversal is tested.
Signed-off-by: Kerry She
Index: src/southbridge/amd/rs780/rs780_gfx.c
===
--- src/southbridge/amd/rs780/rs780_
When the trailing spaces are highlighted, it is easy for us to delete it
and don't create new trailing spaces.
Zheng
Vim:
Add following lines in the .vimrc
"The highlight way can be in your own way.
Highlight ExtraWhitespace ctermfg=DarkGray ctermbg=yellow
"Show trailing whitespace
match ExtraWh
When the trailing spaces are highlighted, it is easy for us to delete it
and don't create new trailing spaces.
Zheng
Vim:
Add following lines in the .vimrc
"
Highlight ExtraWhitespace ctermfg=DarkGray ctermbg=yellow
" Show trailing whitespace:
:match ExtraWhitespace /\s\+$/
Emacs:
Add t
The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8].
The bit 15 seems to be a new feature when CPU started to have more that
4
cores.
Signed-off-by: Zheng Bao
Index: src/northbridge/amd/amdht/h3ncmn.c
===
--- src/
I noticed that ite871x has watchdog. You can try to kill the watchdog
like the
what it8712 does.
Zheng
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Qing Pei Wang
Sent: Tuesday, July 27, 2010 4:20 PM
To: Coreboot;
I am porting coreboot to a new board. The processor is family 10 C32. The
chipset is close to rs780. It seems to be quite close to ok. But the linux
reports "No irq handler for vector (irq -1)".
I am wondering whether IOAPIC or LAPIC will cause that problem. Or any other
suggestion?
Zheng
--
Check the devicetree.cb. set the correct configuration of
gppsb_configuration and gpp_configuration.
Set the needed port as
device pci x.0 on end # x
and
Please uncomment the PciePowerOffGppPorts() in rs780_pcie.c to see what
we can see.
I assume the PCIE GPP you mentioned is GPPSB,
The releasing of 5650 is in the progress. It is about 1 month to go. If
you can not wait, please contact AMD to get the code.
Zheng
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of bari
> Sent: Thursday, July 22, 2010 5:16 AM
Some of the VGA modules have almost same function and vgabios. The only
difference is the Device ID. I am wondering, if I got a Vgabios for
graphics card A, can I just change the device ID in the binary file to
fit the graphics B? Is there any checksum in the vgabios.bin? Is there a
tool to handle
Yes, it works. I will have to figure how _CRS fails.
Thanks.
> -Original Message-
> From: yhlu [mailto:yingha...@gmail.com]
> Sent: Thursday, June 24, 2010 12:04 PM
> To: Bao, Zheng
> Cc: coreboot@coreboot.org
> Subject: Re: [coreboot] Why my kernel 2.6.34 failed?
&
The code was ported. Now it is what it should be.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/rs780/rs780_gfx.c
===
--- src/southbridge/amd/rs780/rs780_gfx.c (revision 5605)
+++ src/southbridge/amd/rs780/rs780_gfx.c
Attached is my output of a new board. The chipset are quite close. Just
for reference.
For the problem of early stage, I met that before. I don't know why, but
we can change pci_located_device to PCI_DEV(b, d, f) in
sb700_early_setup.
The DIMM you are using is ECC capable. The code is there but I
For the mainboard with AMD Family 10, if we make clean and make again,
it will fail. why?
After make clean, .c files created by iasl are still left in the build
folder, it will match the rule of
$(obj)/%.o: $(obj)/%.c $(obj)/config.h
@printf "CC $(subst $(obj)/,
ogany(_fam10)
>
> Am 25.03.2010 08:37, schrieb Bao, Zheng:
> > 1. Remove warnings and multiple blank lines.
> > 2. Mahogany uses GPIO9 to detect 80-pin IDE cable.
> >
> > Signed-off-by: Zheng Bao
>
&
1. Remove warnings and multiple blank lines.
2. Mahogany uses GPIO9 to detect 80-pin IDE cable.
Signed-off-by: Zheng Bao
Throw my last patch away.
Index: src/mainboard/amd/mahogany_fam10/Kconfig
===
--- src/mainboard/amd/mahogany_
-Original Message-
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Bao, Zheng
Sent: Thursday, March 25, 2010 3:20 PM
To: coreboot@coreboot.org
Subject: [coreboot] (no subject)
1. Remove warnings and multiple blank lines.
2. Mahogany uses GPIO9 to
1. Remove warnings and multiple blank lines.
2. Mahogany uses GPIO9 to detect 80-pin IDE cable.
Signed-off-by: Zheng Bao
Index: src/mainboard/amd/mahogany/devicetree.cb
===
--- src/mainboard/amd/mahogany/devicetree.cb(revision
I made it.
Bash# sed -i 's/printk_\([a-z]*\)(/printk(BIOS_\U\1\E, /g' *.c
Zheng
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of Bao, Zheng
> Sent: Wednesday, March 24, 2010 11:27 AM
> To: c
Hi, Stefan,
Do you have a script to do that? If the script was recorded in the log,
that would be the best.
Zheng
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of repository service
> Sent: Monday, March 22, 2010 7:43 PM
> To
remove building warnings of mahogany(_fam10).
About get_ide_dma66(), the SATA has port 5,6 as PATA emulation
since SB700. I havent tried the IDE yet. It will be tested later.
So we leave this function for furture.
Signed-off-by: Zheng Bao
Index: src/mainboard/amd/mahogany/mptable.c
===
Remove the building warnings.
Signed-off-by: Zheng Bao
Index: src/mainboard/amd/mahogany/mptable.c
===
--- src/mainboard/amd/mahogany/mptable.c(revision 5265)
+++ src/mainboard/amd/mahogany/mptable.c(working copy)
@@
Remove the building warnings.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/sb700/sb700_sata.c
===
--- src/southbridge/amd/sb700/sb700_sata.c (revision 5265)
+++ src/southbridge/amd/sb700/sb700_sata.c (working copy)
Remove the building warnings.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/rs780/rs780_cmn.c
===
--- src/southbridge/amd/rs780/rs780_cmn.c (revision 5265)
+++ src/southbridge/amd/rs780/rs780_cmn.c (working copy)
The parameters of memset() should be
memset(addr, value, size), right?
It is an obvious bug created at r5201. I am wondering
why it doesnt trouble you. I took a quike look at other
files and didnt find other calling error.
Signed-off-by: Zheng Bao
Index: src/cpu/amd/model_fxx/model_fxx_init.c
==
The SB600 also has the BootFailTimer. We should disable it,
otherwise it will keeps reboot. The comment was also added in
detail to make less confusing when we debug SB600/SB700.
Signed-off-by: Zheng Bao
Index: src/southbridge/amd/sb600/sb600_early_setup.c
==
This patch configures the toppology of rs780 graphics. The new
gfx_dual_slot option 2 is for the board which can configure the
double/single mode. In that case, we need to know whether a device
is plugged behind DEV 3. So the is_dev3_present() is needed.
This doesn't help mahogany much. You will ne
Thanks. Commited.
r5218.
r5219.
r5220.
r5221.
r5222.
r5223.
> -Original Message-
> From: Marc Jones [mailto:marcj...@gmail.com]
> Sent: Tuesday, March 16, 2010 7:51 AM
> To: Bao, Zheng
> Cc: coreboot@coreboot.org; Ni, John; Tanguay, Kevin; Xie, Michael
> Subject: Re:
This is for the mahogany_fam10 I just sent. It is not a signed-off-by
patch. We need to work it out about this problem.
Index: src/northbridge/amd/amdht/h3finit.c
===
--- src/northbridge/amd/amdht/h3finit.c (revision 4521)
+++ src/no
Add an AM2R2 entry in to the src/arch/i386/Makefile.inc.
The board seems to be working even without this patch.
Signed-off-by: Zheng Bao
Index: src/arch/i386/Makefile.inc
===
--- src/arch/i386/Makefile.inc (revision 5210)
+++ src
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