On Wed, Sep 3, 2008 at 5:23 PM, Ed Swierk <[EMAIL PROTECTED]> wrote:
> Thanks for the feedback. I have addressed most of your comments;
> please see the attached patch.
>
> I will address your comment about the duplicate struct dimm_size
> declaration separately. Would it make
On Tue, Sep 23, 2008 at 5:09 PM, Joseph Smith <[EMAIL PROTECTED]> wrote:
> Wait, making a common file for this?
>
> struct dimm_size {
>unsigned long side1;
>unsigned long side2;
> };
>
> Four four lines of code that seems a little silly to me?
This was in response to Uwe's suggest
On Tue, Sep 23, 2008 at 6:38 PM, Joseph Smith <[EMAIL PROTECTED]> wrote:
> Looks good if you have tested it on real hardware:
>
> Acked-by: Joseph Smith <[EMAIL PROTECTED]>
Yup, I've tested it on the Tolapai development board.
Committed in r3600.
--Ed
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your comments from the first version; see
inline for exceptions.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
On Mon, Aug 25, 2008 at 1:49 PM, Uwe Hermann <[EMAIL PROTECTED]> wrote:
> Comments below, but this should be the last commit anyway (after all the
> NB/SB code is comm
On Mon, Oct 13, 2008 at 4:01 PM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> With the romcc changes as indicated above and outlined below, this is
> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Thanks, r3656.
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On Mon, Aug 11, 2008 at 8:20 AM, Ed Swierk <[EMAIL PROTECTED]> wrote:
> Here's my wish list for a new version of the dongle (some of which
> overlap previous responses). I'd like to be able to:
>
> 1. Reset the dongle by issuing a command from the host, instead of
>
2008/10/27 Stephan GUILLOUX <[EMAIL PROTECTED]>:
> We have a mother board, based on EP80579. On board, there is a flash from
> SPANSION S25FL016A.
> Both are indicated as supported by flashrom (from coreboot v2-3695).
>
> When I start flashrom on my machine, only the EP80579 is seen.
> For the flas
On Tue, Nov 4, 2008 at 1:37 PM, Shadravan Fontanov
<[EMAIL PROTECTED]> wrote:
> citation from datasheet of ICH5/ICH5R chipset
> (http://download.intel.com/design/chipsets/datashts/25251601.pdf),
> page 385:
> "These registers are enabled in the PCI Device 31: Function 0 space
> (PM_IO_EN), and can
On Fri, Nov 7, 2008 at 7:23 AM, Peter Stuge <[EMAIL PROTECTED]> wrote:
> Jordan Crouse wrote:
>> My main concern is that if seabios becomes a defacto mandatory
>
> I will protest very loudly against mandatory. It must be an option.
+1
Modularity is one of the key technical advantages of coreboot.
On Fri, Nov 7, 2008 at 7:38 AM, Jordan Crouse <[EMAIL PROTECTED]> wrote:
> Its getting harder and harder to make it an option. We are going to have to
> deal with optionROMs - regardless what any of us think about legacy software
> callbacks, we are not going to get very far unless we can handle l
On Dec 27, 2007 4:25 PM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> I'm currently reviewing the rest of the patch. Looks nice so far.
There's no urgency, but I'm wondering if there's anything I can do to help.
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Uwe,
Thanks for the detailed review. I am working on a new set of patches.
Most of the southbridge code was derived the esb6300 code, and the
northbridge code is derived from the e7525 code. For the files you
marked "missing license header," does that mean I need to track down
every contributor t
On Fri, Aug 8, 2008 at 4:15 AM, Martin-Éric Racine
<[EMAIL PROTECTED]> wrote:
> In conjunction with item #2 above, we are hereby giving the Coreboot
> community an opportunity to influence the design of this new product.
> While we cannot guarantee that every idea submitted will be used, we
> will
The following set of patches implement support for the Intel EP80579
Integrated Processor (codename "Tolapai"). This is a fairly powerful
system-on-a-chip (SoC), integrating a CPU, northbridge, southbridge,
SuperIO and (optionally) various security and signal processing
accelerators in a single pac
This patch implements support for the CPU core of the Intel EP80579
Integrated Processor.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ep80579-cpu.patch
Description: Binary data
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This patch adds PCI device IDs for the Intel EP80579 Integrated Processor.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ep80579-pci_ids.patch
Description: Binary data
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mileage will definitely vary with other
DIMMs.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ep80579-northbridge.patch
Description: Binary data
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This patch modifies the Intel 3100 southbridge code to recognize the
integrated LPC, SMBus, USB and SATA devices of the Intel EP80579
Integrated Processor.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ep80579-southbridge.patch
Description: Binary data
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This patch modifies flashrom to recognize the Intel EP80579 LPC flash interface.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ep80579-flashrom.patch
Description: Binary data
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This patch implements support for the Intel EP80579 Development Board.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ep80579-truxton-mainboard.patch
Description: Binary data
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On Thu, Aug 21, 2008 at 4:10 PM, Uwe Hermann <[EMAIL PROTECTED]> wrote:
> Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Thanks, r3534.
> but see minor comments below...
>> +static struct cpu_device_id cpu_table[] = {
>> + { X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */
>> + { 0, 0 },
>> +};
>
>
On Thu, Aug 21, 2008 at 4:10 PM, Uwe Hermann <[EMAIL PROTECTED]> wrote:
> Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Thanks, r3535.
> Looks good, committable if build-tested (IMO). But please double-check
> that all init code for i3100 and EP80579 are the same (same register
> offsets, same regist
On Wed, Aug 20, 2008 at 1:41 PM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> A few comments about this one:
>
>> Index: coreboot-v2-3363/src/include/device/pci_ids.h
>> ===
>> --- coreboot-v2-3363.orig/src/include/device/pci_id
On Mon, Aug 25, 2008 at 3:48 PM, ron minnich <[EMAIL PROTECTED]> wrote:
> now let's get some boards with this part on them :-)
Here are a few recently-announced boards, and, umm, a spaceship:
http://www.adiengineering.com/php-bin/ecomm4/products.php?category_id=25&product_id=90&PHPSESSID=20d479f1
Eric Biederman believes that he and Tom Zimmerman of the defunct
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100
raminit code.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
intel-northbridge-copyright.patch
Description: Binary data
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This patch adds definitions for DDR2 SPD registers.
Signed-off-by: Ed Swierk <[EMAIL PROTECTED]>
ddr2-spd-registers.patch
Description: Binary data
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On Thu, Aug 28, 2008 at 11:21 AM, Stefan Reinauer <[EMAIL PROTECTED]> wrote:
> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Thanks, r3546.
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On Thu, Aug 28, 2008 at 11:21 AM, Stefan Reinauer <[EMAIL PROTECTED]> wrote:
> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Thanks, r3547.
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Apparently I'm not the only one who forgets which way the outb and outl
arguments go.
Signed-off-by: Ed Swierk
---
Index: coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
===
--- coreboot-v2/src/southb
On Fri, Jul 10, 2009 at 6:17 AM, Peter Stuge wrote:
> Acked-by: Peter Stuge
Thanks, committed in r4422.
--Ed
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On Sat, Jul 11, 2009 at 2:12 PM, Uwe Hermann wrote:
> Nice, thanks! Have you looked around in those files whether there are
> other occurences of this? We should get rid of all of them in the whole
> v2 code base ASAP before we forget about the issue ;)
I did a quick glance over a global grep for
On Wed, Jul 29, 2009 at 1:45 PM, Kevin O'Connor wrote:
> Okay, that is different - it leads me to believe that coreboot isn't
> turning on your ps2 port.
The mtarvon mainboard config in coreboot only sets up the SuperIO-like
device embedded in the CPU for the internal UARTs; it does not set up
an
On Wed, Jul 29, 2009 at 4:48 PM, Ed Swierk wrote:
> The mtarvon mainboard config in coreboot only sets up the SuperIO-like
> device embedded in the CPU for the internal UARTs; it does not set up
> an external SuperIO at all.
s/mtarvon/truxton/
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On Thu, Jul 30, 2009 at 3:04 PM, Arnaud Maye wrote:
> The last remaining items would be the VGA output. Do you see any problems in
> your port that
> would prevent to use an external GFX card? I've been able to use the DMA
> engine part of our
> PMC cards so I believe the PCIe itself is trained cor
On Thu, Sep 10, 2009 at 5:13 PM, ron minnich wrote:
> I'm looking but don't see info yet on a USB debug port in ICH5, anyone know?
>
> The issue is that the Dell Server 1850 node I'm trying to get working
> doesn't give direct COM1 access to the P4; it goes through a (ack!
> Ptui!) baseboard maint
Also see the ICH5 EHCI programming manual:
http://www.intel.com/Assets/PDF/manual/298656.pdf
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On Wed, Sep 30, 2009 at 5:02 PM, wrote:
> + /* using SerialICE, we've seen this basic reset sequence on the dell.
> + * we don't understand it as it uses undocumented registers, but
> + * we're going to clone it.
> + */
> + /* enable a hidden device. */
> +
On Wed, Sep 30, 2009 at 5:44 PM, ron minnich wrote:
> On Wed, Sep 30, 2009 at 5:11 PM, Stefan Reinauer
> wrote:
>>> + /* operate on undocumented device */
>>>
>> Can you dump the pci config space or read the pci id of that device?
>
> no, because the Dell BIOS turns it completely off.
It sh
On Thu, Apr 16, 2009 at 2:40 AM, Arnaud Maye wrote:
> We are designing a mainboard powered by an EP80579 and I came across
> coreboot.
>
> I've seen corebot v2 supports the Truxton EP80579 Development kit. However I
> cannot get any
> relevant information about Truxton.
>
> Is this the "official"
On Tue, Jun 16, 2009 at 7:24 AM, Arnaud Maye wrote:
> I've just received my UART dongle and I could see that indeed something has
> been sent over UART.
>
> The first error seen was about the fact only ECC DIMMs are allowed, in the
> devkit they provide
> non-ecc memory. Is it normal coreboot only
On Mon, Jun 22, 2009 at 5:06 AM, Arnaud Maye wrote:
> I've narrowed down the problem to the mtrr.c file in src/cpu/x86/mtrr/ in
> the function set_fixed_mtrrs().
>
> The first time disable_cache() is called, the CPU gets "lost". It either
> hang or jump back to some code
> to hang a bit after.
>
>
On Wed, Jun 24, 2009 at 6:36 AM, Arnaud Maye wrote:
> I've tried a reverse engineer approach. Plug a DIMM into the system and
> launch Linux with the
> legacy BIOS. lspci -xxx then shows me the IMCH BAR and implicitly the
> settings doctored by the
> legacy BIOS. The first try I've done was to try
On Sat, Mar 6, 2010 at 8:13 AM, Carl-Daniel Hailfinger
wrote:
> 2. Tiny flashrom stub for remote flashing over serial/network/whatever
> (~10 kB uncompressed and 3 kB lzma compressed, maybe even smaller).
> 3. Load flashrom from an external medium (serial/USB/floppy/whatever) to
> RAM and execute
On Fri, Mar 5, 2010 at 8:58 AM, ron minnich wrote:
> Just got a new nehalem box in for test yesterday. Experiences so far:
>
> 1. POST from power-on takes 45 seconds. *45 SECONDS*. Now, I had it
> said to me at SCALE7x last year from someone from Intel that all new
> BIOSes on Intel chips are real
On Sun, Mar 14, 2010 at 10:30 PM, Bao, Zheng wrote:
> Please see the comment and Signed-off-by line in each patch file.
Thank you, AMD!
Getting code like this through all the technical, legal and business
hurdles and out the door requires herculean effort. Here's hoping it
helps AMD sell lots an
I ran into a couple of errors while building a mahogany_fam10 target;
CONFIG_CAR_FAM10 was renamed some time ago to
CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as
l3_cache().
Signed-off-by: Ed Swierk
---
Index: src/southbridge/amd/rs780/rs780_early_setup.c
On Fri, Mar 19, 2010 at 2:07 PM, Marc Jones wrote:
> Acked-by: Marc Jones
Thanks, r5262.
--Ed
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On Mon, Apr 12, 2010 at 3:28 AM, Arne Georg Gleditsch
wrote:
> My only remaining real issue is that parts of the nvidia mcp55 init code
> will not run properly using mmconf. The offending line is
>
> RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FF, 0x1900,
>
> which causes the operations
>
>
On Tue, Apr 13, 2010 at 12:35 AM, Arne Georg Gleditsch
wrote:
> I'd like to push this mmconf patch upstream in some shape or form, so if
> anyone would like to chime in how to approach this I'd be glad. I could
> just wrap the offending line with "#if !CONFIG_MMCONF_SUPPORT_DEFAULT"
> or somethin
On Tue, Apr 13, 2010 at 12:35 AM, Arne Georg Gleditsch
wrote:
> That's a valuable data point. I'm also running with it disabled, no
> apparent problems here either.
>
> I'd like to push this mmconf patch upstream in some shape or form, so if
> anyone would like to chime in how to approach this I'
On Thu, Apr 15, 2010 at 9:53 AM, Dustin Harrison
wrote:
> I've tried my BIOS build on Truxton to no avail. I get stuck at the same
> spot.
>
> Does someone have a reference to an archive of a working Truxton build
> directory? At least I can start to compare differences in the
> assembly/.config
I'm attempting to port Coreboot to an Asus M4A78XTD board, which has
an RS780/SB700 chipset with a socket AM3 (Fam10h+DDR3) CPU.
Starting with the tilapia_10h mainboard code, the first problem I'm
hitting occurs very early on: any attempt to call pci_locate_device(),
for example in sb700_lpc_init(
On Wed, Apr 28, 2010 at 6:26 AM, Myles Watson wrote:
> Have you tried changing it to pci_locate_device_on_bus()? That will
> constrain the search to a single bus.
That doesn't help; config space accesses to the PCIe bridge devices
themselves are hanging.
I worked around the problem by replacing
On Sun, May 2, 2010 at 3:45 PM, Rudolf Marek wrote:
> I re-checked and it was OK, we do have an early function with same name which
> takes bytes parameters (mtrr-early.c). So this is not the case. I investigated
> MTRRs bit more.
I noticed that too. Perhaps we should rename the early version to
r than mapping it from the
full ROM image.
Both of these changes are the result of random hacking rather than any
real understanding of the issues involved. I'd appreciate any better
ideas.
Signed-off-by: Ed Swierk
---
hw/pc.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff
Hi folks,
I'm using Coreboot to implement an old-school Linux-as-bootloader for
a prototype board, which has an 8-MByte SPI flash attached to an AMD
SB800 southbridge. I'd like to take advantage of that nice roomy
flash, as well as the normal/fallback capabilities of Coreboot and the
layout and pa
On Tue, Mar 3, 2015 at 5:54 AM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2...@gmx.net> wrote:
> This is one of the reasons the lightning bolt of the old official logo
> looks the way it does.
> The following features had been chosen to avoid any unfortunate visual
> associations:
> - close in
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