[coreboot] Re: Error 404 , can't open change 38107 on Gerrit

I think Mike means changesets that are not abandoned but trashed, like https://review.coreboot.org/c/coreboot/+/37815 Op wo 8 jan. 2020 om 19:53 schreef : > > See > https://review.coreboot.org/q/owner:ehaouas%2540noos.fr+Switch+away+from+ROMCC_BOOTBLOCK+status:abandoned > ‌ > De : "Carl-Daniel

Re: [coreboot] freebsd

2017-12-03 12:35 GMT+01:00 ingegneriafore...@alice.it : > Hello guys, > > I apologize with you for the strange question. > > Can you tell me if some of you uses coreboot with the Freebsd Operating > system on its machine ? Yes, I'm running -CURRENT on an ASUS F2A85-M

Re: [coreboot] Unable to include iPXE in coreboot

It's installed through the liblzma-dev package: https://packages.debian.org/stretch/amd64/liblzma-dev/filelist 2017-06-26 15:13 GMT+02:00 Dhanasekar Jaganathan : > Hi All, > > I am trying to enable ethernet in coreboot + GRUB2. So I have enabled > following option in

Re: [coreboot] Warm reset support in Coreboot

Do you have access to, or read, the relevant datasheet(s)? http://www.intel.com/Assets/PDF/datasheet/322896.pdf for example appiies to NM10 and describes the bits involved on section 13.7.5 (RST_CNT). 2017-04-28 12:46 GMT+02:00 : > Hi, > > > > Is there a way to do

Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard

2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry : > Hi, > > I am trying to bring up the AMD G series Olive hill plus mainboard with > coreboot. > > These are the options i have enabled in make menuconfig but I am not able > to see anything on the screen when i power on the

Re: [coreboot] server board support - Supermicro H8DGi-F ?

2017-04-23 19:55 GMT+02:00 Michael L. Wilson <michael.l.wil...@utu.fi>: > Hello Idwer Vollering, > > I came across an old mailing list item concerning the H8SGL Opteron > motherboards. > > https://mail.coreboot.org/pipermail/coreboot/2013-April/075629.html > > Is it

Re: [coreboot] iPXE as payload?

2017-03-19 1:24 GMT+01:00 Gert Menke : > Hi Martin, > > thanks for your reply. > > On 2017-03-19 00:59, Martin Roth wrote: >> >> This will build iPXE option rom into the coreboot.rom file. > > > Which is exactly what I do not want. > It consumes a few seconds on every boot, which is

Re: [coreboot] post_code to text file

cbmem, in util/cbmem/, should be what you are looking for. 2016-12-15 2:35 GMT+01:00 Haleigh Novak : > Hello All, > > I was wondering if it would be possible to add a few lines in the post_code > method so it also writes all the codes to a text file and then keep that > text file

Re: [coreboot] radare

2016-11-08 19:32 GMT+01:00 Zoran Stojsavljevic : > Hello to all radare2 experienced people, > > From my VM Fedora 25 x86_64 on the top of VMWorkstation 12.5.1, on WIN10 64 > Pro! > > Here is my take on radare2... And I am not getting through. Transcript > follows: >

Re: [coreboot] radare

First you'll need to clone radare2 from git. Then apply the patch from https://github.com/radare/radare2/pull/6125 and build and install radare. After opening the binary, enter 'Vp' then follow the [1] shortcut on the far right. 's f000:0' will seek to the start of the bootblock. 2016-11-02 6:59

Re: [coreboot] PCIEXBAR 946 and 945

2016-11-01 4:21 GMT+01:00 Riko Ho : > Good day everyone, > > I got info from Kmalkki, that I need to adapt PCIEXBAR value for 946 from > 945 > I saw in bootblock.c for 945, it's 0x48... > > What value is it for i946 ? inteltool can show these registers. Presuming you

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-31 0:18 GMT+01:00 Riko Ho : > Hi Idwer, > 80 81 82 83 84 > 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 0x84 starts here: ^^ > > isn't it : > > pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00073401); > ? The byte ordering has to do with endianness,

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-30 1:18 GMT+02:00 Idwer Vollering <vid...@gmail.com>: > 2016-10-30 1:04 GMT+02:00 Riko Ho <antonius.r...@gmail.com>: >> >> Everyone, >> >> How can I use the result from >> >> sudo lspci -xxx -s 0:1F.0 >> >>

Re: [coreboot] lspci -xxx -s 0:1F.0 ?

2016-10-30 1:04 GMT+02:00 Riko Ho : > > Everyone, > > How can I use the result from > > sudo lspci -xxx -s 0:1F.0 > > inside this function ? > > static void ich7_enable_lpc(void) > { > // Enable Serial IRQ > pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); This

Re: [coreboot] setting up a bug tracker

2015-11-03 19:17 GMT+01:00 Patrick Georgi : > Hey coreboot folks, > > people were nagging me to set up a bug tracker for the project. > > Last time we dicussed that, we mostly quibbled over the UI and data > model (whether the tracker should feature free form vs. structured >

Re: [coreboot] build coreboot off-line

2015-08-24 17:43 GMT+02:00 nanc...@infomed.sld.cu: HI. I want build coreboot off-line. Can I make that __ Yes, that's possible. First you have to get a copy of the codebase, which is described here: http://www.coreboot.org/Download_coreboot Then you'll prepare the compiler and its

Re: [coreboot] mute button on X200

2015-08-22 11:04 GMT+02:00 Francis Rowe i...@gluglug.org.uk: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Any ideas? Boot into vendor BIOS/EFI thing, install and start acpi_listen, then press the mute button. http://linux.die.net/man/8/acpi_listen Regards, Francis Rowe. -BEGIN PGP

[coreboot] Hudson-D4 (A88X): IRQ routing of XHCI seems incomplete?

Board: asus/f2a85-m In AMD Bolton FCH Register Reference Guide (51192), page 2-154, this register Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch] is 0x12/0x11 while having booted the vendor binary and 0xff/0xff when having booted coreboot. Could the erratic value cause SeaBIOS boot issues? See

Re: [coreboot] Hudson-D4 (A88X): IRQ routing of XHCI seems incomplete?

Subject should read Re: Hudson-D4 (A85X): IRQ routing of XHCI seems incomplete? 2015-07-08 15:59 GMT+02:00 Idwer Vollering vid...@gmail.com: Board: asus/f2a85-m In AMD Bolton FCH Register Reference Guide (51192), page 2-154, this register Interrupt Line – RW – 32 bits - [PCI_Reg:3Ch] is 0x12

Re: [coreboot] Automated test system: Nominations wanted

2015-02-19 0:14 GMT+01:00 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net: Hi, I am currently planning to set up a test system with 5 (later up to 10) machines boot testing each new coreboot commit. This test system will be serviced (i.e. recovery from bricking) Mo-Fr during CET/CEST

Re: [coreboot] updating coreboot SeaBIOS on an Acer C720

? 2015-02-08 21:55 GMT+01:00 Matthias Apitz g...@unixarea.de: El día Sunday, February 08, 2015 a las 02:40:45PM -0600, Alex G. escribió: Suspect number one is the device overheating. The shutdown is triggered by the EC. I don't know how you can enable ACPI debug output on BSD though. On

Re: [coreboot] cbfstool build issue in gcc 4.6.3

2014-11-21 6:03 GMT+01:00 The Gluglug i...@gluglug.org.uk: One possible solution is to simply upgrade GCC, which I will, but I would also like to get cbfstool to build again for this version of GCC. The patch in the gerrit link works, but is not accepted for upstream. Does anyone know a

Re: [coreboot] Coreboot and HP Pavilion 6746C-L?

2014-11-07 15:21 GMT+01:00 theodore.preunin...@lycos.com: #1 Ok, so let me get this straight It is possible, but it requires opening up the case to getting to the hardware - while the computer is on? It is possible to swap flash chips while your computer is running, yes. The term is

Re: [coreboot] Coreboot and HP Pavilion 6746C-L?

2014-11-04 4:38 GMT+01:00 theodore.preunin...@lycos.com: Step 1 (or equal to step 1) and step 5 From http://h10025.www1.hp.com/ewfrf/wc/document?docname=bph05159tmp_task=prodinfoCategorycc=usdlc=enlc=enproduct=57589 Intel Socket 370 Pentium III Celeron i810 i810 might still work.

Re: [coreboot] MinnowMax: Tentative patch for S3 suspend/resume support

2014-09-11 9:34 GMT+02:00 Mohan mo...@ndr.co.jp: Hi, This is a tentative patch for S3 suspend/resume support in MinnowMax Board. (..) Comments, suggestion, corrections are welcome. I would like to get it added it, can anyone help me ? Certainly. Have you read this subpage,

Re: [coreboot] nvidia/tegra build tool

2014-08-14 23:25 GMT+02:00 Isaac isaac.christen...@se-eng.com: The new nvidia/tegra124 support requires a build tool from NVIDIA called cbootimage (https://github.com/NVIDIA/cbootimage). I'm not sure of the best way to add support into coreboot so I'd like to get some feedback. Would it make

Re: [coreboot] F2A85-M: Chassis Fan Not Working

2014-06-28 17:59 GMT+02:00 HacKurx hack...@gmail.com: Hi, I just update coreboot on my motherboard and after reboot of my computer the chassis fan stopped working. I did not have this problem with the version of coreboot from 1 March 2014: http://review.coreboot.org/#/c/5226/ Have you an

Re: [coreboot] compiling on FreeBSD

2014-06-28 17:29 GMT+02:00 Beeblebrox zap...@berentweb.com: On FreeBSD platform, $ make menuconfig bombs pretty hard. Part of the problem seems like bash vs sh, but I doubt if that's the whole of it. Is FreeBSD within consideration of working build platforms? I had no problems compiling on

Re: [coreboot] EHCI debug port finder

2008-09-09 15:21 GMT+02:00 Carl-Daniel Hailfinger Updated version attached. This one works with slightly older lspci versions as well and fixes one bug with multiple cards. Updated version attached. This one works around grep behaviour. finddebugport.sh Description: Bourne shell script --

[coreboot] Fwd: [flashrom] A couple of bugs..

-- Forwarded message -- From: Mike Hibbett mhibb...@ircona.com Date: 2014-05-20 14:06 GMT+02:00 Subject: [flashrom] A couple of bugs.. To: flash...@flashrom.org flash...@flashrom.org I spotted these two in yesterday’s code base. I’m not likely to commit code anytime soon so I

Re: [coreboot] AMD doesn't get it either in some ways

2014-04-05 15:48 GMT+02:00 Luc Verhaegen l...@skynet.be: On Sat, Apr 05, 2014 at 03:20:08PM +0200, Rudolf Marek wrote: Hi all, I think there is OpenRadeonBios. The problem is that thhe AtomBIOS bytecode is vendor specific blob, which cannot be in principle released by AMD because it is

Re: [coreboot] P965/ICH8 support revisited

2014-04-05 1:24 GMT+02:00 Yuval Adam yuv@gmail.com: The P965/ICH8 combo is suspiciously lacking from the coreboot supported chipsets. Who knows how similar i945 is to i965 ;) I have a motherboard that might be fit for development on these chipsets (Gigabyte GA-965P-DS3) and I'm curious

Re: [coreboot] F2A85-M LE

2014-04-03 17:07 GMT+02:00 Dominic Walden domi...@dwalden.co.uk: Hi all, I understand the f2a85-m is working with coreboot. Does anyone know if the Limited Edition version will also work, or whether it will require some work? See these posts:

Re: [coreboot] [Coreboot] About (re)flash BIOS utility

2014-03-12 11:23 GMT+01:00 yu chyuan fu fuh0...@gmail.com: Hi All I am a novice with coreboot. I successfully build coreboot.rom follow www.coreboot.org. Now i want to burn it to flash chips. I tried using the vendors provide flash utility write to flash chips, it's can write success. The

Re: [coreboot] Acer C710-2856 coreboot+seabios blue screen?

2014-02-20 9:38 GMT+01:00 Justin Roylance justin.royla...@gmail.com: the flashrom utility in Kubuntu says no chipset found and no EEPROM/flash device found. The version that Kubuntu ships could very well be outdated. (dist-)upgrade your installation and/or see

Re: [coreboot] Help using IRC

2014-02-17 6:56 GMT+01:00 Anthony Ross anthonyross...@gmail.com: Hello Folks Well Im a bit confused on how to use the IRC provided for the list members. It seems just silent for hours, no responses at all. Could someone provide help? Quiet? Are you sure you joined the right channel :) ?

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

Thank you for this information. Please indicate the compatible processor on the motherboard page. See this list: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29 I'll add it to the board's wiki page. -- coreboot

Re: [coreboot] Unable to start correctly coreboot on Asus f2a85-m REV 1.02

2014-02-04 22:36 GMT+01:00 Rudolf Marek r.ma...@assembler.cz: Perfect thank you for this whole procedure. This is what I obtain: My rom (with my vga bios): coreboot-4.0-5394-gba6b07e Thu Jan 30 19:48:58 CET 2014 starting... BSP Family_Model: 00610f31 cpu_init_detectedx =

Re: [coreboot] Setting up build environment

2014-02-09 20:05 GMT+01:00 Andy Pont andy.p...@sdcsystems.com: Hello Idwer, 8 I have noticed that whenever I call make it gives a warning about not having a compiler for aarch64-elf and also complains about not having an IASL compiler and suggesting that I install the one that comes with

Re: [coreboot] Setting up build environment

Adding seabios at seabios dot org to the recipients. 2014-02-10 0:47 GMT+01:00 Andy Pont andy.p...@sdcsystems.com: Hello! Apparently CentOS installs, or will install, a really old version of iasl; here you'll see that they (still) use iasl-20090123-3.1.el6.x86_64:

Re: [coreboot] Setting up build environment

2014-02-07 Andy Pont andy.p...@sdcsystems.com: Hello! Hello! I am trying to setup a build environment on 64bit CentOS 6.5 platform to be able to build coreboot. I have cloned the coreboot sources from git and have run the following commands: make crossgcc -- to build the cross

[coreboot] Can't build ASUS F2A85-M for a 4 megabyte flash chip

Compiling for 8MB however works just fine. Error output: Created CBFS image (capacity = 4193256 bytes) E: Could not add [build/coreboot_hudson_romsig.bin, 16 bytes (0 KB)@0xffc2]; too big? E: Failed to add 'build/coreboot_hudson_romsig.bin' into ROM image. make: *** [build/coreboot.pre1]

Re: [coreboot] AMD Geode LX800 - CS5536 with Coreboot v3?

2014-01-30 Darmawan Salihun darmawan.sali...@gmail.com: Is this where to clone it from: http://review.coreboot.org/coreboot.git You can find cloning instructions, and how to contribute/push changes, on this wiki page: http://www.coreboot.org/Git HTH, Idwer -- coreboot mailing list:

[coreboot] Fwd: coreboot on amd A85 can't work

Forwarding the reply where 陈军根 c...@bolod.net informed me of his findings, see below. -- Forwarded message -- From: 陈军根 c...@bolod.net Date: 2013/12/17 Subject: Re: [coreboot] coreboot on amd A85 can't work To: Idwer Vollering vid...@gmail.com Idwer: the vendor(ASUS) EFI

Re: [coreboot] coreboot on amd A85 can't work

2013/12/13 陈军根 c...@bolod.net: Dear all: I run coreboot in ASUS F2A85-MLE CPU is A10-5800k, kingston ddr3 1600(kvr1600d3n9/4g),coreboot halt at assertion Failed:file 'src/vendorcode/amd/agesa/f15tn/proc/mem/main/mmexcludedimm.c',line 236. I don't know how to do, can anyone help me?

Re: [coreboot] looking for a good, small, low power, portable board

Oops, let's send it to the list as well. 2013/11/25 ron minnich rminn...@gmail.com: Folks, I'm looking for a very small board with the following: - x86_64, preferably with virtualization capability - 4-8 G or so of memory - intel e1000 or rtl8139 gige - coreboot not required, but strongly

Re: [coreboot] Issues getting ASUS F2A85-M to boot

2013/10/29 Haywood-Evans Matthew mahev...@qinetiq.com: Hi, I am presently looking at trying to get Coreboot up and running on an ASUS F2A85-M system. I am however running into some issues. Using a bus pirate and flashrom I first backed up the original bios, then erased the chip and restored

Re: [coreboot] need to build coreboot on via epia-m w gcc 4.5.1 - impossible, eh ?

2013/8/27 matti christensen mat...@iki.fi /mc matti christensen ---keep-IT-simple--- No one can, or will, help you when you don't include any information at all. Which linux distribution are you using? Did you run 'make crossgcc' ? coreboot supports three [1] epia-m boards, which one do you

Re: [coreboot] T60 issues

2013/6/25 Gerd Hoffmann kra...@redhat.com: Hi, Two little issues with T60: First, the keyboard doesn't work on cold boots. http://www.coreboot.org/SeaBIOS#Other_Configuration_items You have to create the file etc/ps2-keyboard-spinup: $ ./encodeint.py ps2-keyboard-spinup 2000 $ hexdump

Re: [coreboot] [flashrom] About flashing mx25l4005 on Itona TC2331

2013/5/14 Bin X z2...@outlook.com: I apologize if it does not make sense at all since this is my first attempt to flash a bios with unmatched bios ID. I was trying to flash bios on a Itona TC2331 to get rid of the limitation they put on of any IDE HDD and USB HDD can’t be larger than 64mb.

Re: [coreboot] coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.

2013/4/11 Pradish M P, ERS, HCLTech pradis...@hcl.com: Dear coreboot folks i downloaded the latest source code form coreboot.org , when i tried to build the cross compiler using the command make crossgcc it gives the following error root@test-VirtualBox:~/coreboot# make crossgcc

Re: [coreboot] server board support - Supermicro H8DGi-F ?

2013/4/6 Marc Jones marcj...@gmail.com: Hi Ward, I think that the H8QGI has fairly good support (the one SMP late init bug noted). I didn't look at the details, but similar boards should be a easy port. The supermicro boards will often have the pads for the debug header for when the going

Re: [coreboot] [flashrom] flashrom first use....

2013/2/26 Francisco Otero Martínez de Al girot...@yahoo.es: I didn't flash nothing yet. Please advise me if it is safe to load coreboot on this motherboard. Quoting the logfile: Found chipset NVIDIA MCP61 MCP61 is not in this list: http://www.coreboot.org/Supported_Chipsets_and_Devices so the

Re: [coreboot] Asus F2A85-M progress

2012/12/18 David Hubbard david.c.hubbard+coreb...@gmail.com: Hi all, On Mon, Dec 17, 2012 at 6:40 AM, Bernhard Urban lew...@gmail.com wrote: On Mon, Dec 17, 2012 at 2:33 PM, darkdefe...@gmail.com wrote: Rudolf Marek writes: Maybe it is slowly time to prepare a patch, I think I will need

Re: [coreboot] ROM option compile problem

2012/11/1 jeroenkrabben...@fastmail.fm: Thank you for this tip. I followed the instructions (make crossgcc), but got stuck while building gcc on a 'bus error' of genautomata. Details (total of 3): 1. Output of make crossgcc: Indus ~ # cd /usr/src/coreboot/ Indus coreboot # make

Re: [coreboot] ROM option compile problem

2012/11/1 jeroenkrabben...@fastmail.fm: Thx for replying. I switch to this email address, trying not to pollute the mailing list. Please keep coreboot@ in the To: or CC field, others can't help you when you don't use reply-to-all. I think is not a hardware problem, as the error occurs on

Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways

2012/10/15 Hristo Venev mustrum...@gmail.com: Is it a gcc bug or is it a coreboot bug? Actually it is a binutils 'bug'. You should run 'make crossgcc' (and remove .xcompile) in the top directory, where you run 'make menuconfig'. -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways

2012/10/15 Hristo Venev mustrum...@gmail.com: Binutils bug or feature? Rather a distribution feature. http://www.coreboot.org/Development_Guidelines#Required_Toolchain -- Linux distributions usually modify their compilers in ways incompatible with coreboot. If in doubt, use our toolchain. --

Re: [coreboot] #188: gcc-4.7 miscompiles coreboot on -Os, -O1, -O2, -O3 in 3 different ways

Please reply with reply to all, thanks. 2012/10/15 Hristo Venev mustrum...@gmail.com: Fixed it by using my linux distribution's toolchain but specifying -march=i686 Probable reason: some instructions enabled by default by gcc but not enabled at early stages of booting. Hm, I suppose that

Re: [coreboot] New laptop: Lenovo ThinkPad X230 tablet, with dumps to go with it

CC: flash...@flashrom.org 2012/9/15 Keith Hui buu...@gmail.com: Hi all, I'm back. With a new laptop. I'm now rocking a Lenovo x230 tablet, dual-booting Windows 7 and Fuduntu, both 64-bit. Knowing the last time I contributed to coreboot it was the good old 440BX when life was much simpler,

Re: [coreboot] How can get 3rd party bins like mrc.bin for SandyBridge/Ivybridge

2012/7/26 wx fred...@hotmail.com: How can get 3rd party bins like mrc.bin for SandyBridge/Ivybridge ? Besides having the possibility to extract mrc.bin with cbfstool, you can 'download' at least one mrc.bin from the blobs repository: git clone http://review.coreboot.org/p/blobs.git Folder

Re: [coreboot] Porting to Thinkpad T42

2012/7/15 David Griffith d...@661.org: Would it be worthwhile, at least as an learning experience, to port Coreboot to the Thinkpad T42? My advice is to make i855 work on a desktop machine first. lspci of a thinkpad t42: http://www.linuxquestions.org/hcl/showproduct.php/product/3047/cat/all

Re: [coreboot] flashrom patches for X60s

2012/7/14 Motiejus Jakštys desired@gmail.com: On Fri, Jul 13, 2012 at 10:43 AM, Motiejus Jakštys desired@gmail.com wrote: On Thu, Jul 12, 2012 at 1:26 PM, Tomasz Ostaszewski ostaszewski.tom...@gmail.com wrote: Hi Peter, Motiejus, Tried to ask on the flashrom mailing list but to

Re: [coreboot] [ltp] Re: [Thinkpad] Free T60

2012/7/9 ron minnich rminn...@gmail.com: On Sat, Jul 7, 2012 at 6:24 PM, Idwer Vollering vid...@gmail.com wrote: netconsole won't - afaik - work because IP (UDP) isn't functional/loaded at the time of the crash.. hi, did not check this, but you did not used to need IP or any kind up

Re: [coreboot] [ltp] Re: [Thinkpad] Free T60

2012/7/2 Sven Schnelle sv...@stackframe.org: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net writes: [adding coreboot mailing list to CC] Am 29.06.2012 16:49 schrieb Stefan Monnier: You do know that all Thinkpad T60/X60 can replace the BIOS with coreboot? No, I didn't, that would

Re: [coreboot] [ltp] Re: [Thinkpad] Free T60

2012/7/8 Peter Stuge pe...@stuge.se: Idwer Vollering wrote: I have a X60 (1707-CTO / 1707YAU) that won't boot Linux (it segfaults while booting either a 32- or 64-bit kernel/distribution) at all, with ACPI enabled. What does the failed boot look like? Maybe you could try netconsole

Re: [coreboot] SIGILL on an ASUS A8V-E Deluxe

2012/7/6 Michael Büchler mbuechle...@gmail.com: On Fri, 2012-07-06 at 13:10 +0200, Michael Büchler wrote: I'm trying to run coreboot on an ASUS A8V-E Deluxe. It stops with a SIGILL after saying the following (tail of the log I got over serial): I was able to get around this by using gcc-4.4.6

Re: [coreboot] GA-6BXE doesn't boot with Intel PRO/1000 GT

2012/6/25 Tomi Leppänen tomppel...@gmail.com: Hi, I have a Gigabyte GA-6BXE (Rev 2.1) motherboard with coreboot (built last week, I think). My processor is Intel Pentium III 550 and I have 786 MiB of RAM (actually 1 GiB but the motherboard can't see a part of it). It works just fine when I

Re: [coreboot] Support for HP Compaq NC6320

2012/6/6 Ross McDonald ross0mcdon...@gmail.com: Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq NC6320. The board vendor is HP. It is a HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M southbridge and i945 northbridge). The CPU is an Intel Core 2 Duo T5600. It has a

Re: [coreboot] [AMD] Persimmon

2012/5/23 martin.m...@mic.com.tw: Hello all, I check out coreboot and build and run persimmon project via menuconfig, Are you using a payload? If so, which one are you using? Mainborad: AMD Mainboard Model: Persimon FlashSize: 4MB But it always show 0x00 on my PCI debug card.

Re: [coreboot] Asus M2N68-LA HP Narra 2

Op 30 maart 2012 18:59 heeft Marc Dunivan mduni...@hawk.iit.edu het volgende geschreven: I have and old HP Pavillion with an Asus M2N68-LA Narra 2 mother board.     Coreboot hasn't been ported to it.  Not asking for it either.  I just want to know the northbridge and southbridge it has.

Re: [coreboot] Fwd: porting Coreboot to a new motherboard....

Op 28 maart 2012 14:52 heeft ali hagigat hagigat...@gmail.com het volgende geschreven: - Forwarded message -- From: ali hagigat hagigat...@gmail.com Date: Wed, Mar 28, 2012 at 4:58 PM Subject: Re: [coreboot] porting Coreboot to a new motherboard To: Kyösti Mälkki

Re: [coreboot] [SerialICE] [ANNOUNCE] libhwremote 0.1

patch is totally untested, but I expect it to work. A big THANK YOU goes to Idwer Vollering who tested a dozen iterations of this code until I had figured out the very surprising and unique properties of the SerialICE protocol. Another big THANK YOU goes to Ron Minnich who sent a mail titled

[coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)?

Or: how to start a multicore (hyperthreading) processor as if it were a singlecore (non-hyperthreading) processor. Would it be necessary to configure APIC/IPI in serialice' mainboard specific code? See these message [1] [2] [3]. This is the output from two processors with hyperthreading disabled

Re: [coreboot] Trouble building coreboot/SeaBios

2011/12/30 Prakash Punnoor prak...@punnoor.de: Hi, I am trying to build coreboot with SeaBios (for a new mainboard I am trying to port). Initially the build system complained about a broken LD, so I built make crossgcc -j1 (iasl compile fails in parallel mode, btw) Oh? Wasn't that fixed..

Re: [coreboot] Getting serial output from w83627hf?

2011/10/18 Alp Eren Köse alperenk...@buyutech.com.tr Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f val ff 52 41 ff fe c0 00 00 00 00 fe c0 ff 00 ff def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 CR24

Re: [coreboot] Getting serial output from w83627hf?

Comments inline: 2011/10/17 Idwer Vollering vid...@gmail.com 2011/10/17 Alp Eren Köse alperenk...@buyutech.com.tr Hi all, I can't get serial output from the board I am trying to put coreboot on, so I am not able to go any further to see whats going on.. The board has a Winbond

Re: [coreboot] Getting serial output from w83627hf?

2011/10/17 Alp Eren Köse alperenk...@buyutech.com.tr Hi all, I can't get serial output from the board I am trying to put coreboot on, so I am not able to go any further to see whats going on.. The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. It is likely that you need

Re: [coreboot] make crossgcc fails with 'Building IASL 20110623 ... failed'

2011/10/10 Alp Eren Köse alperenk...@buyutech.com.tr: As written on the subject 'make crossgcc' fails as following: Skipping GDB as requested by command line Building IASL 20110623 ... failed make[1]: *** [build-without-gdb] Error 1 make: *** [crossgcc] Error 2 Anyone knows why? and the

Re: [coreboot] Coreboot on Axiomtek PICO821

2011/10/5 Alp Eren Köse alperenk...@buyutech.com.tr: Anyone has an idea? Another question is I can't find my mainboard vendor Axiomtek in Mainboard Vendor selection list in menuconfig as expectedly, but all the chips and chipset of it seem to be supported as I see them in coreboot website. Is

Re: [coreboot] Video card bios project

2011/8/15 dove - railing doverail...@gmail.com: Please tell if you interested in doing this project, leaving aside the money issues. Please use reply to all, thanks in advance. Idwer Regards Meeku On Sun, Aug 14, 2011 at 6:49 PM, Idwer Vollering vid...@gmail.com wrote: 2011/8/2 dove

Re: [coreboot] Video card bios project

2011/8/2 dove - railing doverail...@gmail.com: If I said I am prepared to pay for it, what are you going to charge for doing this project? Sorry, I have no idea what (amount of money) to charge, nor how much work it will be. Others can most likely provide a better/more satisfying answer. Idwer

Re: [coreboot] Video card bios project

2011/6/19 dove - railing doverail...@gmail.com: I have phoned Australia and spoke to an expert in Procon.com.au about 2 times and corresponded via email.  Procon.com.au are wanting several hundred dollars whether it's  my font or theirs.  This is not affordable.  I don't know why vga bios is

Re: [coreboot] haveing troubling building core boot!

2011/5/27 Cui Lei neverforget_2...@163.com: I had the same error, just install the lastest binutils, try again. Quote: If you have compiler or binutils trouble, REPRODUCE WITH coreboot/util/crossgcc and then send a log to the mailing list i try to do a build Of core boot and I get this after

Re: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?

2011/5/16 Scott Duplichan sc...@notabs.org: If you happen to want to test windows xp setup using a standard setup CD, windows will not find the drives because it has no AHCI support. The standard solution is the F6 floppy method of adding an AHCI driver, but lack of floppy support on new

Re: [coreboot] [flashrom] Failed Flash Dead Board

2011/4/22 Schenk, John josch...@uncc.edu: Could anyone help in identifying the Phoenix BIOS Chip on the motherboard? It looks like the chip is just below the lower right corner of the cardbus frame: http://www.techex.biz/ebaybiz/pics/Motherboards/MBD-00544_02.jpg The objective is to replace

Re: [coreboot] [flashrom] Need assistance for using non-coreboot bios image

2011/4/20 David Bein d.b...@f5.com: Hello Idwer, Hello David,  Thank you very much for the assistance. I assume that something like: nvramtool -c 0 will force the newly booted bios to re-compute the checksum on the cmos? I assume you want to save the current contents with nvramtool -b

Re: [coreboot] Gigabyte GA AMD E350N USB3 Board

2011/4/18 Peter Stuge pe...@stuge.se: Marek wrote: What about the DB_PORT programming header? http://hardforum.com/showthread.php?t=1598236 Maybe! Can you trace the connections from the port to the flash chips? Is the dual BIOS stored on the MX25L1606EM2I-12G chip? GIGABYTE boards that

Re: [coreboot] [PATCH] 440BX registered SDRAM support

2011/4/1 Keith Hui buu...@gmail.com: ping? Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD;

Re: [coreboot] I865 memory controller status

2011/4/5 James Wall scouter...@gmail.com: Hello all, What is the status of the i865 memory controller? That chipset as a whole is (currently) unsupported, however plans to support it are there. RAM init is work in progress, another developer and I have a total of three i865 boards. Since RAM

Re: [coreboot] I865 memory controller status

2011/4/6 James Wall scouter...@gmail.com: I will look at the source code then for more ideas and to help understand the code then. thanks for the information. If you want to help porting, can you produce a serialice log (and send it to Josephd and me, offlist) ? See the website,

[coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated

/deskpro_en_sff_p600 emulation/qemu-x86 gigabyte/ga-6bxc gigabyte/ga-6bxe msi/ms6119 msi/ms6147 msi/ms6156 nokia/ip530 soyo/sy-6ba-plus-iii tyan/s1846 Signed-off-by: Idwer Vollering vid...@gmail.com --- Index: src/southbridge/intel/i82371eb/Makefile.inc

Re: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated

2011/4/1 Stefan Reinauer stefan.reina...@coreboot.org: * Idwer Vollering vid...@gmail.com [110401 20:29]: Signed-off-by: Idwer Vollering vid...@gmail.com --- Index: src/southbridge/intel/i82371eb/Makefile.inc === --- src

Re: [coreboot] [patch] fix compilation of all i82371eb boards when ACPI tables aren't generated

V2. Signed-off-by: Idwer Vollering vid...@gmail.com --- Index: src/southbridge/intel/i82371eb/Makefile.inc === --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) +++ src/southbridge/intel/i82371eb/Makefile.inc (working

Re: [coreboot] make Error while building Seabios as payload

2011/3/29 Georgi, Patrick patrick.geo...@secunet.com: Am Dienstag, den 29.03.2011, 16:22 +0530 schrieb sharib khan: sharib/coreboot]$ make menuconfig Makefile, line 23: Missing dependency operator Makefile, line 25: Need an operator Error expanding embedded variable. Could anyone tell what

Re: [coreboot] Intel 855GM status?

2011/3/10 Peter James messageforpe...@gmail.com Just wondering if any further progress has been made to the intel 82855 chipset which as far as I can tell is in a WIP status. Has anyone been able to get this working successfully? Apparently not/not really. What board images have you tried

Re: [coreboot] ACPI breakage/questions and ramstage code question

2011/3/2 Keith Hui buu...@gmail.com --- First, Mysterious breakage on experimental i82371eb ACPI stuff Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B series of boards: I'm seeing mysterious compiler breakge after updating my local copy to r6424. I copied that from P2B to

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

2011/1/8 Roger rogerx@gmail.com On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote: Hi Parts of original patch are already in coreboot. This version made cache work in my board now. It might need work so it doesn't break others. Here is part of serial capture.

Re: [coreboot] [PATCH] Add easy SeaBIOS as payload option

2010/12/26 Stefan Reinauer stefan.reina...@coresystems.de See patch Nice. Can you extend it so the serial port number, #define DEBUG_PORT PORT_SERIAL1, in $seabios_dir/src/output.c is shared with CONFIG_CONSOLE_SERIAL_COM1 in coreboot's .config, and so on for COM2..4 ? Dito for #define

Re: [coreboot] [PATCH] CONFIG_DEBUG_RAM_SETUP breaks build on i82810, i440bx and maybe more

2010/12/21 Keith Hui buu...@gmail.com: As promised. Attached is my fix: Copy/paste: Index: src/northbridge/intel/i440bx/raminit.c === --- src/northbridge/intel/i440bx/raminit.c (revision 6205) +++

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