On Wed, 2008-02-20 at 23:21 +0100, Ronald Hoogenboom wrote:
On Tue, 2008-02-19 at 23:34 -0500, Ward Vandewege wrote:
...
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1458
+default
Hi Ward,
Thanks for reviewing my patch. I'm glad to hear that it got you a
booting mainboard too.
Most of the seemingly unrelated changes are a result of my quest to get
my nvidia VGA to work. Also I'm quite new submitting patches and I'm not
yet very familiar with what stuff is allowed to be in
Hi Ronald,
On Mon, Feb 18, 2008 at 10:45:23PM +0100, Ronald Hoogenboom wrote:
Finally, now I know it's working (at least the part that I'm patching
here...), here is the patch that uses PIO mode read from SPI rom with
lzma decompression.
This patch allows direct out-of-SPI-flash boot of a
Finally, now I know it's working (at least the part that I'm patching
here...), here is the patch that uses PIO mode read from SPI rom with
lzma decompression.
This patch allows direct out-of-SPI-flash boot of a Linux kernel. It
circumvents the 512KB limitation in the IT8716f superio of memory
Am Dienstag, 22. Januar 2008 01:09:09 schrieben Sie:
Harald: This patch should fix your problems writing to the chip. Use
either patch -l or remove the // before
//while (generic_spi_read_status_register() JEDEC_RDSR_BIT_WIP)
I've updated my flashrom tree to revision 3068 and commented that
On 22.01.2008 12:08, Harald Gutmann wrote:
Am Dienstag, 22. Januar 2008 01:09:09 schrieben Sie:
Harald: This patch should fix your problems writing to the chip. Use
either patch -l or remove the // before
//while (generic_spi_read_status_register() JEDEC_RDSR_BIT_WIP)
I've updated
Carl-Daniel Hailfinger wrote:
Harald: This patch should fix your problems writing to the chip. Use
either patch -l or remove the // before
//while (generic_spi_read_status_register() JEDEC_RDSR_BIT_WIP)
Ronald: I need an ack to commit this.
On 20.01.2008 11:59, Ronald Hoogenboom wrote:
Carl-Daniel Hailfinger wrote:
Did you have time to test with the while
(generic_spi_read_status_register() .._WIP) enabled? It would be more
correct to have it enabled.
I had that in initially (that's why it was there, but commented out) but
all it got me was slower programming times and
On 20.01.2008 12:48, Ronald Hoogenboom wrote:
On Sun, 2008-01-20 at 11:59 +0100, Ronald Hoogenboom wrote:
The read status register will take at least:
16*(2/33) us = about 1 us (excluding the LPC latency, which is?), so
assuming that the first read status will show busy and the second
On Mon, 2008-01-21 at 00:24 +0100, Ronald Hoogenboom wrote:
(LPC is the only datapath to the SB and CPU, so it has to!). We could
optimize by omitting the wait for SPI ready when there is no data to be
read, eg. readcnt==0. I'll have a look at what can be gained by that.
Omitting it saves 10
On Sun, 2008-01-20 at 22:28 +0100, Carl-Daniel Hailfinger wrote:
I think we can shorten the delay in the loop to about 5 us. However,
even with 10 us delay we still can't explain the time needed to program
the chip.
In the case without status reading, we have exactly 5 bytes on the SPI
bus
Carl-Daniel Hailfinger wrote:
*/
- //while (generic_spi_read_status_register()
JEDEC_RDSR_BIT_WIP)
+ while (generic_spi_read_status_register() JEDEC_RDSR_BIT_WIP)
myusec_delay(10);
- //if (i%1024==0) fputc('b',stderr);
+ if (i
On 19.01.2008 19:34, Ronald Hoogenboom wrote:
Carl-Daniel Hailfinger wrote:
*/
-//while (generic_spi_read_status_register()
JEDEC_RDSR_BIT_WIP)
+while (generic_spi_read_status_register() JEDEC_RDSR_BIT_WIP)
myusec_delay(10);
-//if (i%1024==0)
On 18.01.2008 23:10, Ward Vandewege wrote:
On Wed, Jan 16, 2008 at 10:34:29PM -0500, Ward Vandewege wrote:
Winbond W25X16VSSI
Winbond W25X32VSSI
Problem with Winbond is they really only want to sell large
quantities. I haven't even gotten a quote and delivery time
back from my sales rep
On 19.01.2008 01:08, Carl-Daniel Hailfinger wrote:
On 19.01.2008 00:17, Ronald Hoogenboom wrote:
On Fri, 2008-01-18 at 23:31 +0100, Carl-Daniel Hailfinger wrote:
Thanks for reworking the code! I have factored out some common status
registers to duplicate less code and hope the
On Fri, 2008-01-18 at 23:31 +0100, Carl-Daniel Hailfinger wrote:
Thanks for reworking the code! I have factored out some common status
registers to duplicate less code and hope the code still works. Could
you please review it and tell me what you think?
Fine by me, works like a charm, the way
On Wed, Jan 16, 2008 at 10:34:29PM -0500, Ward Vandewege wrote:
Winbond W25X16VSSI
Winbond W25X32VSSI
Problem with Winbond is they really only want to sell large
quantities. I haven't even gotten a quote and delivery time
back from my sales rep on a request I made in November.
What
On Fri, 2008-01-18 at 09:39 -0800, ron minnich wrote:
On Jan 18, 2008 6:49 AM, Carl-Daniel Hailfinger
should work as well and fit a little better into flashrom structure.
The top 512 flash fine, the lower 1.5M did not flash, but did erase,
maybe. hard to say if
readback worked.
That is
On Fri, 2008-01-18 at 03:00 +0100, Carl-Daniel Hailfinger wrote:
On 17.01.2008 22:25, Ronald Hoogenboom wrote:
...
the limited io transfer length options of the IT8716). It might be more
appropriate to have an 'over512k_page_write' for more speed with chips
that do support that. Also the
On 19.01.2008 00:17, Ronald Hoogenboom wrote:
On Fri, 2008-01-18 at 23:31 +0100, Carl-Daniel Hailfinger wrote:
Thanks for reworking the code! I have factored out some common status
registers to duplicate less code and hope the code still works. Could
you please review it and tell me what
On 18.01.2008 21:09, Ronald Hoogenboom wrote:
OK, I've checked it again and fixed a few things, see the read function
and the erase also has the block protect disable, and it works again.
Thanks! It seems I was half asleep while coding the if (size 512k) part.
It takes just under a
On 18.01.2008 21:48, Ronald Hoogenboom wrote:
I think this is a matter of taste... But if the style is like this, I
will comply. So I changed my patch again to do exactly the same, but
with a few JEDEC_... defines.
Signed-off-by: Ronald Hoogenboom [EMAIL PROTECTED]
Thanks for
Do you think it would be possible to add write support for the MX25L8005 and
the MX25L3205D to flashrom based on this patch?
I'd be really glad to see write support for those chips.
regards,
Harald
--
coreboot mailing list
coreboot@coreboot.org
On Jan 17, 2008 2:32 PM, Ronald Hoogenboom [EMAIL PROTECTED] wrote:
Now I'm looking at how to make the rom_stream read the flash chip like
in the over512k_read_chip.
But I'm a bit stuck on the overal mechanics of the initialization
process and how to get hold of the assigned io port for the
On Thu, Jan 17, 2008 at 01:24:38AM +0100, Carl-Daniel Hailfinger wrote:
Please be aware that the M57SLI may read the reset vector and other
really early stuff at 33 MHz, thereby causing read errors
(sometimes single bit shifts) which are really hard to find.
English translation:
SST25VF016B
On Thu, Jan 17, 2008 at 03:03:48AM +0100, Peter Stuge wrote:
On Wed, Jan 16, 2008 at 08:57:52PM -0500, Ward Vandewege wrote:
English translation:
SST25VF016B is not really compatible with the IT8716F superio.
All right. So how about the Atmel AT45DB321D-SU
Unfortunately it has a
On 17.01.2008 02:48, Ward Vandewege wrote:
Hi Ronald,
On Thu, Jan 17, 2008 at 12:13:48AM +0100, Ronald Hoogenboom wrote:
Problem1 (for reading) is solved by NOT using the mmap method for
reading the flash contents, but using outb() for sending the flash read
commands (using a specific
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