I don’t think a warning message around EFI_MEMORY_UC is useful… it’s typical to
request such a mapping for device MMIO (e.g. PciHostBridgeDxe,
NonDiscoverablePciDeviceDxe, etc). On a system without PBMT yeah the M mode
firmware will have to enforce the correct type, but that’s been true until
Reviewed-by: Michael D Kinney
> -Original Message-
> From: mikub...@linux.microsoft.com
> Sent: Friday, March 1, 2024 3:33 PM
> To: devel@edk2.groups.io
> Cc: Sean Brogan ; Joey Vagedes
> ; Kinney, Michael D
>
> Subject: [PATCH v2 1/1] .github/workflows/codeql.yml: Update actions
>
From: Michael Kubacki
Currently CodeQL runs have the following warnings:
Node.js 16 actions are deprecated. Please update the following
actions to use Node.js 20: actions/setup-python@v4,
actions/upload-artifact@v3, actions/cache@v3. For more information
see:
Thanks for the detailed review. Please see my comments below.
On Fri, Mar 1, 2024 at 4:14 AM Laszlo Ersek wrote:
> On 3/1/24 02:29, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> > supported when Svpbmt extension available.
> >
> > Cc: Gerd Hoffmann
>
On 3/1/24 08:43, Gerd Hoffmann wrote:
> So I ran with the suggestion by Laszlo to move the page table setup into
> macros and untangle the non-CoCo / TDX / SEV code paths. The first five
> patches of the series are doing that (without functional changes).
>
> Support for 5-level paging is added
On 2/22/24 03:39, Zhou Jianfeng wrote:
> Some IN OUT parameters in CpuPageTableMap.c were mistakenly marked as IN.
> "IN" replaced with "IN OUT" in the following interfaces:
>
> PageTableLibSetPte4K(): Pte4K
> PageTableLibSetPleB(): PleB
> PageTableLibSetPle(): Ple
> PageTableLibSetPnle():
On 3/1/24 08:11, Li, Zhihao wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4697
>
> EvacuateTempRam function will copy the temporary memory context to the rebased
> pages and the raw pages. Migrations of rebased PEIMs is from cache to memory,
> while raw PEIMs is from memory to
On 3/1/24 04:01, Zhiguang Liu wrote:
> This patch set is to support to unregister SMI handler inside SMI handler,
> also add check to not allow unregister SMI handler in other SMI handler.
> This patch set also have the same logic in StandaloneMmPkg.
> Because no change on the first patch, I kept
On 3/1/24 03:54, Zhou Jianfeng wrote:
> Add volatile qualifier to page table related variable to prevent
> compiler from optimizing away the variables which may lead to
> unexpected result.
>
> Signed-off-by: Zhou Jianfeng
> Cc: Ray Ni
> Cc: Laszlo Ersek
> Cc: Rahul Kumar
> Cc: Gerd Hoffmann
On 3/1/24 08:43, Gerd Hoffmann wrote:
> [...]
For future patch submissions: please include the Cc: tags in the commit
message bodies; PatchCheck.py (also part of CI) enforces that now.
Thanks
Laszlo
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
On 3/1/24 15:52, Gerd Hoffmann wrote:
> Hi,
>
>>> OneTimeCall CheckSevFeatures
>>> +cmp byte[WORK_AREA_GUEST_TYPE], 1
>>> +jnz NoSevIa32
>>> +OneTimeCall SevClearVcHandlerAndStack
>>>
>>> +NoSevIa32:
>>> ;
>>> ; Restore initial EAX value into the EAX
This looks fine.
Reviewed-by: Michael Kubacki
On 3/1/2024 7:58 AM, gaoliming wrote:
I agree this change. It should have no negative impact. Reviewed-by: Liming
Gao
Michael:
Have you any comments for this change?
Thanks
Liming
-邮件原件-
发件人: Zhihao Li
发送时间: 2024年3月1日 15:12
收件人:
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set
the desired performance.
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA
---
From: Shriram K
RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA
---
The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file
Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.
Signed-off-by: Prabin CA
---
In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.
From: Vivek Gautam
On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.
Signed-off-by: Prabin CA
---
Changes since V3:
- Rebase on top of latest upstream branch.
Changes since V2:
- Removed author's signed-off on the patches, which is owned by another author.
Changes since V1:
- Corrected memory map in the DSDT file.
This patch series introduce support for RD-Fremont reference design
platform.
The Neoverse RD-N2-Cfg3 platform is a variant of RD-N2 platform with a
different mesh size and GIC ITS count. As part of the initial platform
support, add the corresponding platform and flash description files.
Use PcdPlatformVariant for the RD-N2-Cfg3 platform to specify the
platform variant.
From: Pranav Madhu
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
From: Pranav Madhu
Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++-
A new PCD named PcdPlatformVariant is introduced to specify the variant
number of a platform. This PCD can be used to select platform variant
specific configurations. The default value of this PCD is 0 which
selects the base variant.
Signed-off-by: Prabin CA
---
From: Vijayenthiran Subramaniam
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3479
A recent change in MdeModulePkg [1] introduced VariableFlashInfoLib as a
dependency to support dynamic variable flash information. Add an
instance for the library class VariableFlashInfoLib in
From: Omkar Anand Kulkarni
The software executing at a higher privileged level on the reference
design platforms have been updated to allow software executing at EL1
and EL0 to access the Advanced SIMD and floating-point registers (FPEN
field of CPACR_EL1 system register is programmed to allow
Changes since V4:
- Rebase on top of latest upstream branch.
Changes since V3:
- Removed author's signed-off on the patches, which is owned by another author.
Changes since V2:
- Removed the patch which introduce fno-stack-protector in the build flag.
Changes since V1:
- Addressed comments from
Right, if it is only required by ARM, then it should under ARM section.
Thank you
Yao, Jiewen
> -Original Message-
> From: Leif Lindholm
> Sent: Friday, March 1, 2024 7:45 PM
> To: Yao, Jiewen ; Pierre Gondois
> ; devel@edk2.groups.io
> Cc: Ard Biesheuvel ; Liming Gao
> ; Kinney,
Hi,
> > OneTimeCall CheckSevFeatures
> > +cmp byte[WORK_AREA_GUEST_TYPE], 1
> > +jnz NoSevIa32
> > +OneTimeCall SevClearVcHandlerAndStack
> >
> > +NoSevIa32:
> > ;
> > ; Restore initial EAX value into the EAX register
> > ;
>
> Did you miss
On Wed, 28 Feb 2024 at 17:59, Sami Mujawar wrote:
>
> +Resending with email address for maintainers.
>
>
>
> Hi Ard, Leif,
>
> This patch adds macros that can be used to validate that the SPI ranges are
> valid.
> These have been define here so that we do not duplicate it at multiple places.
>
>
Hi,
> Did you place the "CheckForSev:" label intentionally outside of the %if
> scope? If it was intentional, then I'm OK with it.
>
> If it was unintended / an oversight, then next question: do you want me
> to move the label into the %if's scope for you, upon merge? Or do you
> like it
Hi Sahil,
There are multiple items that need fixing in this patch. Also, the changes in
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec from Patch 3/4 must be part of this
patch.
To save my time from reviewing the whole thing again, I am going to fix that
before merging.
However, do find my
Hi Sahil,
Thank you for this patch.
This patch can clearly be split into 2, one for the
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/* changes and
the other for the Silicon/ARM/NeoverseN1Soc/* changes.
I am going to do that before merging.
With that,
Reviewed-by: Sami
Hi Sahil,
Thank you for this patch.
On Thu, Jan 4, 2024 at 05:16 AM, sahil wrote:
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> b/Silicon/ARM/Neov=
> erseN1Soc/NeoverseN1Soc.dec
> index c04162e7e7cd..cca5bf45db67 100644
> --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +++
Hi Sahil,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#116254): https://edk2.groups.io/g/devel/message/116254
Mute This
On 3/1/24 13:52, gaoliming via groups.io wrote:
> Looks good. Reviewed-by: Liming Gao
Thank you, merged as commit range a31e3c842bee..1ea6546578fe.
Laszlo
>
>> -邮件原件-
>> 发件人: devel@edk2.groups.io 代表 Laszlo Ersek
>> 发送时间: 2024年2月25日 5:29
>> 收件人: edk2-devel-groups-io
>> 抄送: Bob Feng ;
On 3/1/24 13:53, gaoliming via groups.io wrote:
> Looks good. Reviewed-by: Liming Gao
Thank you, merged as commit range db69f5661cae..7a7165a7d199.
Laszlo
>
>> -邮件原件-
>> 发件人: devel@edk2.groups.io 代表 Laszlo Ersek
>> 发送时间: 2024年2月25日 5:24
>> 收件人: edk2-devel-groups-io
>> 抄送: Bob Feng ;
On 3/1/24 08:44, Gerd Hoffmann wrote:
> Turn the GetSevCBitMaskAbove31 OneTimeCall into a macro because we
> need that twice (for 4-level and 5-level paging). Change include
> order to allow AmdSev.asm macros being used in PageTables64.asm.
I *think* the include order change will not only make
On 3/1/24 08:44, Gerd Hoffmann wrote:
> When running in SEV mode keep the VC handler installed.
> Add a function to uninstall it later.
>
> This allows using the cpuid instruction in SetCr3ForPageTables64,
> which is needed to check for la57 & 1G page support.
>
> Signed-off-by: Gerd Hoffmann
>
I agree this change. It should have no negative impact. Reviewed-by: Liming
Gao
Michael:
Have you any comments for this change?
Thanks
Liming
> -邮件原件-
> 发件人: Zhihao Li
> 发送时间: 2024年3月1日 15:12
> 收件人: devel@edk2.groups.io
> 抄送: Liming Gao
> 主题: [PATCH v1] MdeModulePkg/Core/Pei:
On 3/1/24 08:44, Gerd Hoffmann wrote:
> BSP workflow is quite simliar to the non-coco case.
>
> TDX_WORK_AREA_PGTBL_READY is used to record the paging mode:
> 1 == 4-level paging
> 2 == 5-level paging
>
> APs will look at TDX_WORK_AREA_PGTBL_READY to figure whenever
> they should enable
Looks good. Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Laszlo Ersek
> 发送时间: 2024年2月25日 5:24
> 收件人: edk2-devel-groups-io
> 抄送: Bob Feng ; Liming Gao
> ; Michael D Kinney
> ; Rebecca Cran ; Yuwei
> Chen
> 主题: [edk2-devel] [edk2-BuildSpecification PATCH 0/3]
Looks good. Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Laszlo Ersek
> 发送时间: 2024年2月25日 5:29
> 收件人: edk2-devel-groups-io
> 抄送: Bob Feng ; Liming Gao
> ; Michael D Kinney
> ; Rebecca Cran ; Yuwei
> Chen
> 主题: [edk2-devel] [edk2-InfSpecification PATCH 0/2] README:
>
On 3/1/24 08:43, Gerd Hoffmann wrote:
> Add macros to check for 5-level paging and gigabyte page support.
> Enable 5-level paging for the non-confidential-computing case.
>
> Signed-off-by: Gerd Hoffmann
> ---
> OvmfPkg/ResetVector/ResetVector.inf | 1 +
>
Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: Gerd Hoffmann
> 发送时间: 2024年2月22日 18:54
> 收件人: devel@edk2.groups.io
> 抄送: Michael Roth ; Jiewen Yao
> ; Liming Gao ; Laszlo
> Ersek ; Tom Lendacky ;
> Paolo Bonzini ; Ard Biesheuvel
> ; Gerd Hoffmann ; Min Xu
> ; Erdem Aktas ; Oliver
> Steffen ;
Reviewed-by: Liming Gao
> -邮件原件-
> 发件人: Gerd Hoffmann
> 发送时间: 2024年2月22日 18:54
> 收件人: devel@edk2.groups.io
> 抄送: Michael Roth ; Jiewen Yao
> ; Liming Gao ; Laszlo
> Ersek ; Tom Lendacky ;
> Paolo Bonzini ; Ard Biesheuvel
> ; Gerd Hoffmann ; Min Xu
> ; Erdem Aktas ; Oliver
> Steffen ;
On 3/1/24 03:54, Zhou Jianfeng wrote:
> Add volatile qualifier to page table related variable to prevent
> compiler from optimizing away the variables which may lead to
> unexpected result.
>
> Signed-off-by: Zhou Jianfeng
> Cc: Ray Ni
> Cc: Laszlo Ersek
> Cc: Rahul Kumar
> Cc: Gerd Hoffmann
On 3/1/24 04:01, Zhiguang Liu wrote:
> In last patch, we add code support to unregister MMI handler inside
> itself. However, the code doesn't support unregister MMI handler
> insider other MMI handler. While this is not a must-have usage.
> So add check to disallow unregister MMI handler in other
On 3/1/24 04:01, Zhiguang Liu wrote:
> In last patch, we add code support to unregister SMI handler inside
> itself. However, the code doesn't support unregister SMI handler
> insider other SMI handler. While this is not a must-have usage.
> So add check to disallow unregister SMI handler in other
On 3/1/24 02:29, Tuan Phan wrote:
> The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> supported when Svpbmt extension available.
>
> Cc: Gerd Hoffmann
> Cc: Laszlo Ersek
> Cc: Rahul Kumar
> Cc: Ray Ni
> Signed-off-by: Tuan Phan
> ---
>
Il ven 1 mar 2024, 12:10 Michael Brown ha scritto:
> It feels as though this should be able to be cleanly modelled with a
> single global state array
>
>BOOLEAN mSavedInterruptState[TPL_HIGH_LEVEL]
>
Pretty much, yes. But you only have to write it when the interrupts are
already disabled,
Hi Oliver,
On Tue, 27 Feb 2024 at 21:27, Oliver Smith-Denny
wrote:
>
> When an ImageRecord is stored by ImagePropertiesRecordLib, it reports the
> CodeSegmentSize as the SizeOfRawData from the image. However, the image
> as loaded into memory is aligned to the SectionAlignment, so
>
Reviewed-by: Michael Brown
Thanks,
Michael
On 01/03/2024 02:54, Zhou Jianfeng wrote:
Add volatile qualifier to page table related variable to prevent
compiler from optimizing away the variables which may lead to
unexpected result.
Signed-off-by: Zhou Jianfeng
Cc: Ray Ni
Cc: Laszlo Ersek
Thank you.
OK, that's logically consistent.
So we'd need an ArmLibNull in MdePkg until ArmLib itself migrates there
(ideally subsumed into BaseLib).
But the dependency in .inf should still be able to be declared under
[LibraryClasses.AArch64, LibraryClasses.ARM]?
Regards,
Leif
On
Hi Mike,
can you please comment on the Build and Inf spec changes proposed in
this thread?
Thanks,
Laszlo
On 2/24/24 21:59, Laszlo Ersek wrote:
> v1 posting:
>
> https://edk2.groups.io/g/devel/message/115193
> msgid <36593e23-d3e8-b71a-808d-ef94260b5...@redhat.com>
>
> Bugzilla:
>
>
On 3/1/24 02:26, Chao Li wrote:
> Hi Ray, Lazslo,
>
> This library is almost complete to refactored, it refer to ARM and
> RISC-V version, the API include set/get memory region attribute.
>
> I have one last question, in ARM and RISC-V version, even LoongArch old
> and current version, they all
On 01/03/2024 09:33, Paolo Bonzini wrote:
On Fri, Mar 1, 2024 at 10:27 AM Michael Brown wrote:
It's possible that it doesn't matter. The new logic will effectively
mean that RestoreTPL() will restore not only the TPL but also the
interrupts-enabled state to whatever existed at the time of the
On 3/1/24 03:10, Yuting Yang wrote:
> Enhance PcdValueInit for storage saving
>
> Cc: Rebecca Cran rebe...@bsdio.com
> Cc: Liming Gao gaolim...@byosoft.com.cn
> Cc: Bob Feng bob.c.f...@intel.com
> Signed-off-by: Yuting Yang
> ---
> .../Source/Python/Workspace/DscBuildData.py | 43
Add volatile qualifier to page table related variable to prevent
compiler from optimizing away the variables which may lead to
unexpected result.
Signed-off-by: Zhou Jianfeng
Cc: Ray Ni
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Pedro Falcato
Cc: Zhang Di
Cc: Tan Dun
Cc:
On Wed, Feb 28, 2024 at 09:51:41AM -0600, Tom Lendacky wrote:
> On 2/28/24 02:40, Gerd Hoffmann wrote:
> > > +/**
> > > + Perform a native PVALIDATE operation for the page ranges specified.
> > > +
> > > + Validate or rescind the validation of the specified pages.
> > > +
> > > + @param[in]
On Fri, Mar 1, 2024 at 10:27 AM Michael Brown wrote:
> > My version is attached, feel free to reuse it (either entirely or
> > partially) for a hypothetical v2. Apologies to you and Mike K for the
> > confusion!
>
> I much prefer this version of the patch, because the explanations are
> easier to
On 01/03/2024 08:37, Paolo Bonzini wrote:
So I am starting to see more and more similarities between the two
approaches. I went a step further with fresh mind, removing the while
loop... and basically reinvented your and Michael's patch. :) The only
difference in the logic is a slightly
Paolo,
Happy weekends!
Thanks! I will read it on my next Monday.
Thanks,
Ray
> -Original Message-
> From: Paolo Bonzini
> Sent: Friday, March 1, 2024 4:44 PM
> To: Ni, Ray
> Cc: devel@edk2.groups.io; Kinney, Michael D ;
> Liming Gao ; Laszlo Ersek ;
> Michael Brown
> Subject: Re:
One fix is needed in the code.
On Thu, Feb 29, 2024 at 2:04 PM Ray Ni wrote:
> + //
> + // Save the "Interrupted TPL" (TPL that was interrupted).
> + //
> + mInterruptedTplMask |= (UINTN)(1 << gEfiCurrentTpl);
> +}
>}
> + //
> + // Clear interrupted TPL
On Fri, Mar 1, 2024 at 4:08 AM Ni, Ray wrote:
> @@ -161,5 +191,46 @@ CoreRestoreTpl (
>IN EFI_TPL NewTpl
>)
> {
> + BOOLEAN InInterruptHandler = FALSE;
> +
> + //
> + // Unwind the nested interrupt handlers up to the required
> + // TPL, paying attention not to overflow the stack.
66 matches
Mail list logo
