Hi all,
I hope you and your family are having good holidays.
I just added support for having multiple files on EDA Playground. This will
make it easier to have larger Migen examples/prototypes, since each part of
design/testbench can be in its own file. This also allows having generic
input.txt f
OK. Sounds like I don't need to update Migen right away. In the future, let
me know when you'd like me to update Migen on EDA Playground.
I will add the Migen Divisor to examples tomorrow.
-Victor
On Mon, Dec 2, 2013 at 12:44 PM, Sébastien Bourdeauducq <
sebastien.bourdeaud...@lekernel.net> wro
On 12/02/2013 07:34 PM, Victor Lyuboslavsky wrote:
> Regarding upgrading Migen, it looks like the way to launch the
> simulation changed. Does it mean that code on EDA Playground is not
> compatible with the latest Migen changes (from the last couple of days)?
Compatibility is retained, but using
The Divider testbench works: http://www.edaplayground.com/s/4/485
Sebastien,
Regarding upgrading Migen, it looks like the way to launch the simulation
changed. Does it mean that code on EDA Playground is not compatible with
the latest Migen changes (from the last couple of days)?
Ideally, I woul
The whole thing is also quite ugly. I guess the divider should use DF
(and be moved to actorlib in Migen) so that the testbench can use the
Token transaction objects instead of this little mess :)
Sebastien
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On 12/02/2013 05:59 PM, Sébastien Bourdeauducq wrote:
> elif self.state == "WAIT0":
> self.state = "WAIT"
> elif self.state == "WAIT":
> s.wr(self.divider.start_i, 0) <= this should be moved up 2 lines
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Hi,
Good news :)
On 12/02/2013 04:14 PM, Victor Lyuboslavsky wrote:
> (http://www.edaplayground.com/s/example/453). It would be good to have a
> Migen example on EDA Playground that is both synthesizable and has a
> simple testbench
I have written a quick testbench code for the divider, it's bel
I have Migen synthesis working on EDA Playground. Example:
http://www.edaplayground.com/s/4/484
- Migen synthesis only works with Yosys flow, since VTR flow does not
support the newer Verilog port declaration syntax that Migen creates
- the Wishbone example can't be converted to Verilog (
http://w
On 11/30/2013 03:36 PM, Victor Lyuboslavsky wrote:
> Sebastien,
> Can you add a link to Migen documentation? Something like: EDA
> Playground -- run Migen simulations online
Sure:
http://milkymist.org/3/migen.html
https://twitter.com/Milkymist_Labs/status/406825848226848769
By the way I found htt
It runs server side.
On Saturday, November 30, 2013, Yann Sionneau wrote:
> Victor,
>
> It looks really great :)
> Really cool web based tool!
>
> Did you compile iverilog to javascript and run it locally on the user's
> browser?
> Or does it run server-side?
>
>
>
> 2013/11/30 Victor Lyuboslavsk
Victor,
It looks really great :)
Really cool web based tool!
Did you compile iverilog to javascript and run it locally on the user's
browser?
Or does it run server-side?
2013/11/30 Victor Lyuboslavsky
> Migen is now available on EDA Playground for simulations. Example:
> http://www.edaplaygr
Migen is now available on EDA Playground for simulations. Example:
http://www.edaplayground.com/s/example/453
Please try it out. It works with the waveform viewer.
It would be good to have a couple more Migen examples, like a memory
example (all the other methodologies have a RAM example). If you
Hi,
On 11/29/2013 10:32 PM, Victor Lyuboslavsky wrote:
> That seems to be working. Signals seem to be getting mapped to input
> ports. What about output ports -- does the convert method automatically
> figure out what is input and output?
Yes, if you assign to IO signals via comb/sync statements
+dev list
That seems to be working. Signals seem to be getting mapped to input ports.
What about output ports -- does the convert method automatically figure out
what is input and output? And Sink/Source variables -- are they not
synthesizable?
What are a couple good example designs that I can tr
Hi,
On 11/29/2013 09:19 PM, Victor Lyuboslavsky wrote:
> Thank you for the response. I plan to make Migen available for
> simulation on EDA Playground (using Icarus Verilog) on Sunday or Monday.
Great! :)
> print(verilog.convert(top, ios={name for name in dir(top) if name[0] !=
> "_" and
> isins
Sebastien,
Thank you for the response. I plan to make Migen available for simulation
on EDA Playground (using Icarus Verilog) on Sunday or Monday.
Regarding synthesis,
I won't be able to pre-fill the list of modules using Python since I only
have Javascript available for the front end.
For pre-f
On 11/27/2013 11:52 PM, Victor Lyuboslavsky wrote:
> 2. Ask the user to enter the top level Module class and the list of
> ports. And then I simply run print(verilog.convert(UserModule(),
> ios{ports})) on the server.
I would be in favor of that. You can pre-fill the list of modules by
analyzing t
Regarding the "streamlined synthesis flow", my primary motivation is figure
out how to add easy-to-use Migen synthesis to EDA Playground.
1. having a script that converts design.py -> design.v would be ideal, but
it doesn't exist
2. Ask the user to enter the top level Module class and the list of
On 11/27/2013 05:49 PM, Victor Lyuboslavsky wrote:
> This would help with having a more streamlined synthesis flow.
Have you tried the Migen tutorial with Mibuild?
http://milkymist.org/3/migen-tutorial.pdf
Do you see improvements for it?
Sebastien
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Hi,
can we take this discussion to the developer mailing list? You may need
to subscribe at http://lists.milkymist.org so your messages do not go
into the moderation queue and you'll get the possible answers from other
people.
On 11/27/2013 05:49 PM, Victor Lyuboslavsky wrote:
> I tried migen, an
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