On 03/20/2012 01:55 AM, Werner Almesberger wrote:
- the DRAM data sheet [1] says the -5B version (which is what we
have) needs Vdd = VddQ = 2.6 ± 0.1 V for DDR400 operation. If
operating at a lower speed, it is content with 2.5 ± 0.2 V.
Do we plan to operate the DRAM in M1r4 at DDR400
S?bastien Bourdeauducq wrote:
No. But the -5B part is needed because it supports CAS latency 3 in
DDR366, which makes it easier to align the data than CAS latency
2.5. Also, it generally has better timing.
Okay. But at least some of the better timings may only apply to
2.6 V. In the data
New week, new review: the memories. Let's begin with the DRAM:
- nitpicking: the official names of pins 20 and 47 of U14/U15 are
LDM/UDM, not LDQM/UDQM
- the DRAM data sheet [1] says the -5B version (which is what we
have) needs Vdd = VddQ = 2.6 +/- 0.1 V for DDR400 operation. If
operating
On Tue, Mar 20, 2012 at 8:55 AM, Werner Almesberger
wer...@almesberger.netwrote:
- nitpicking: the official names of pins 20 and 47 of U14/U15 are
LDM/UDM, not LDQM/UDQM
Nice catch :-) applied temporarily to:
http://downloads.qi-hardware.com/people/adam/m1/tmp/m1r4/SDRAM_20120320.pdf
-
