Thanks a lot.
I found the problem. I should have used 'int16' instead of 'int' nor
'float'.
I think I have better spectrum shape for 20Mhz signal using UHD compared to
gnuradio
usrp2_rx_cfile.py.
But I found high frequency portion is somewhat suppressed than the original
samples transmitted.
One
- Original Message -
From: Jeff Brower
Date: Wednesday, January 12, 2011 9:43 pm
Subject: Re: [Discuss-gnuradio] re: Low cost hardware option
To: Jamie Morken
Cc: discuss-gnuradio@gnu.org
> Jamie-
>
> > Hi Brian,
> >
> > That sounds like a pretty good system. I should say right
> > o
On 13.01.2011 02:36, Jamie Morken wrote:
> I am interested in helping out with making some new gnuradio hardware that is
> compatible with the USRP daughterboards. I worked with Matt doing CAD
> on the original gnuradio project hardware and have since then made lots more
> boards including a cyc
On Jan 12, 2011, at 9:17 PM, Jamie Morken wrote:
> That sounds like a pretty good system. I should say right off the bat that
> if I am involved to make this I would want to add a clause in the open source
> hardware license to not allow the hardware to be used for military
> applications. I
On 13.01.2011 01:49, Tom Rondeau wrote:
> >From my experiments, I don't thinks its a A _and_ B situation. I think
> if you have either A) a large amount of data _OR_ B) have to pound on
> it furiously, you get a win. Most filters needed for normal comms is
> not enough data or computation, but doin
Hi
I am not that coded up on UHD, but I would think that they have the same
type of file writing system as is used in the GNU Radio code. In the GNU
Radio code they use a binary file writing system. I have attached a matlab M
file that reads these types of files, the file can be found in GNU Radio
Jamie-
> Hi Brian,
>
> That sounds like a pretty good system. I should say right
> off the bat that if I am involved to make this I would want
> to add a clause in the open source hardware license to not
> allow the hardware to be used for military applications. I
> think it is important to stat
> I am trying to use "rx_samples_to_file.cpp" in UHD to save samples received.
> UHD seems save samples in complex integer format in c++.
yes, COMPLEX_INT16
> However, it is not possible to read that format from Matlab.
I'm not a huge matlab fan, but I am sure that it can read integers from
a f
> On Wed, Jan 12, 2011 at 8:36 PM, Jamie Morken
> wrote:
> >
> > Hi,
> >
> > I am interested in helping out with making some new gnuradio
> hardware that is compatible with the USRP daughterboards. I
> worked with Matt doing CAD on the original gnuradio project
> hardware and have since then
Hello,
I am trying to use "rx_samples_to_file.cpp" in UHD to save samples received.
UHD seems save samples in complex integer format in c++.
However, it is not possible to read that format from Matlab.
I have checked the Matlab utilities in Gnuradio, but they were not useful.
Is that any simpler wa
On 01/12/2011 10:46 PM, Brian Padalino wrote:
>
> Agreed on PCIe, though I think less platforms have USB3.
>
Almost certainly the case right now.
> When speaking of noise at baseband (2V driving 50Ohms), assuming you
> have a little can over the analog bits, is the noise that high?
>
>
>
Not
On Wed, Jan 12, 2011 at 10:26 PM, Marcus D. Leech wrote:
> On 01/12/2011 10:01 PM, Brian Padalino wrote:
>>
>> Altera Cyclone IV EP4CGX15 FPGA, Analog Devices AD9861 MxFE, USB2
>> microcontroller (for reprogramming the FPGA) in an ExpressCard/34
>> format. The FPGA has a hard PCIe 1.1 x1 lane wit
On 01/12/2011 10:01 PM, Brian Padalino wrote:
>
> Altera Cyclone IV EP4CGX15 FPGA, Analog Devices AD9861 MxFE, USB2
> microcontroller (for reprogramming the FPGA) in an ExpressCard/34
> format. The FPGA has a hard PCIe 1.1 x1 lane with a hard IP core for
> PCIe connectivity. The PCIe interface ha
On Wed, Jan 12, 2011 at 8:36 PM, Jamie Morken wrote:
>
> Hi,
>
> I am interested in helping out with making some new gnuradio hardware that is
> compatible with the USRP daughterboards. I worked with Matt doing CAD on the
> original gnuradio project hardware and have since then made lots more b
Hi,
I am interested in helping out with making some new gnuradio hardware that is
compatible with the USRP daughterboards. I worked with Matt doing CAD on the
original gnuradio project hardware and have since then made lots more boards
including a cyclone 3 board.
Here is a possible hardware
On Wed, Jan 12, 2011 at 3:39 PM, Marcus D. Leech wrote:
>> On Jan 12, 2011, at 2:56 PM, Moeller wrote:
>> The "very large FIR filters" was a thought, as an example of an operation
>> that might benefit from a GPU at least when using OpenCL (or CUDA). I
>> haven't done testing yet to know if a GPU
Hi, Tom
I am not quite understand the ofdm_sync_xx.cc in python/gnuradio/blks2impl/.
What is the difference between frequency synchronization and carrier
frequency offset.
Why we have to do the timing and frequency synchronization before it?
Also,
Thanks,
Guanbo
Tom Rondeau wrote:
>
> On
Hi, Tom
I am not quite understand the ofdm_sync_xx.cc in python/gnuradio/blks2impl/.
What is the difference between frequency synchronization and carrier
frequency offset.
Why we have to do the timing and frequency synchronization before it?
Thanks,
Guanbo
Tom Rondeau wrote:
>
> On Tue, Feb
Has anyone done this? Looking to see what configurations ppl have tried.
Im using the 1800 dboard.
Thanks,
Isaac
___
Discuss-gnuradio mailing list
Discuss-gnuradio@gnu.org
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Has anyone done this? Looking to see what configurations ppl have
tried. Im using the 1800 dboard.
Thanks,
Isaac
It should run fine on a 6 to 7.5V battery. It draws a couple of amps
with a transceiver daughtercard in place.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astron
By the way, USB3 is now hitting the mainstream, with PCI boards,
motherboards, disk drives and USB sticks from all the major vendors.
It provides a significant bandwidth boost over USB2 (it's designed for
3Gbits/sec, both ways simultaneously). This would be very useful to
any newly designed USR
> If one desired USB instead, then a simple [Cypress] EZ-FX2 USB-2.0
> card with an FMC connector on it, and whatever logic was necessary
> to grab samples from the ADC could be designed and built.
By the way, USB3 is now hitting the mainstream, with PCI boards,
motherboards, disk drives and USB s
>
>> If you don't trust me, try it. Use Xilinx on Windows, create a project
>> and put in all file of all different makefile in the repo for USRP2 with
>> u2_rev3.v in top. Implement top module and create the bin file. After,
>> give me some news plz. It's not loosing time, nobody had answer to m
Just to place some previous experience I have, if you have diferent
configuration parameters, the hardware, possibly, will not work!!! Same code
without change nothing, and will not work. This is not a USRP issue, FPGA
projects can go wrong with diferent parameters for synthesis.
2011/1/12 Matt Et
On 01/12/2011 12:31 PM, Gabriel Morel wrote:
Ok, I will compile the raw ethernet project for the USRP2 to be sure
that I can modify it and use the modified version to my master. I was
try to compile the project fpga.git under ISE10.1 and under ISE12.1. The
two method compile well, give two differ
2011/1/12 Marcus D. Leech
> Hi, i'm watching all discussion about poor students and the evil Mr Ettus
>> who don't play like Santa Claus and whant to make some profit :). I'm also
>> watching all topics and discussion regarding a low cost solution for use
>> with GNURADIO. I guess we can have a c
On 12.01.2011 20:22, Marcus D. Leech wrote:
If connected to a Xilinx board, FIR and decimation could still be done in the
FPGA.
Agreed.
There's a cheap one here, with USB2 and Spartan3, only 70€ (<$100)
http://www.ztex.de/usb-fpga-1/usb-fpga-1.2.d.html
Or this one for 145€?
http://www.cesys.co
Hi, i'm watching all discussion about poor students and the evil Mr
Ettus who don't play like Santa Claus and whant to make some profit
:). I'm also watching all topics and discussion regarding a low cost
solution for use with GNURADIO. I guess we can have a cheap option to
us and I'm
I don't
On Wed, Jan 12, 2011 at 3:31 PM, Gabriel Morel
wrote:
> If you don't trust me, try it. Use Xilinx on Windows, create a project and
> put in all file of all different makefile in the repo for USRP2 with
> u2_rev3.v in top. Implement top module and create the bin file. After,
> give me some news
On 12.01.2011 20:22, Marcus D. Leech wrote:
> http://www.sbrac.org/files/digital_receiver2.pdf
>
The RF range is interesting, from 70 MHz to 2.2 GHz.
For USRP you would need 2 different boards to cover that range,
or invest much more money into the WBX transceiver.
> This has a "reasonable" RF Rx
Hi, i'm watching all discussion about poor students and the evil Mr Ettus
who don't play like Santa Claus and whant to make some profit :). I'm also
watching all topics and discussion regarding a low cost solution for use
with GNURADIO. I guess we can have a cheap option to us and I'm very
interest
Matt,
Ok, I will compile the raw ethernet project for the USRP2 to be sure
that I can modify it and use the modified version to my master. I was
try to compile the project fpga.git under ISE10.1 and under ISE12.1.
The two method compile well, give two different size of binary file,
but bo
On Jan 12, 2011, at 2:56 PM, Moeller wrote:
The "very large FIR filters" was a thought, as an example of an operation that
might benefit from a GPU at least when using OpenCL (or CUDA). I haven't done testing yet to
know if a GPU can do better than a CPU using vector instructions ... but I'm ge
On Wed, Jan 12, 2011 at 3:22 PM, Michael Dickens wrote:
> On Jan 12, 2011, at 2:56 PM, Moeller wrote:
> > On 12.01.2011 14:25, Michael Dickens wrote:
> >> the CPU). I think that if a GPU can be used, it will be most effective
> in things like filterbanks, or when searching for packets (via their
- Original Message -
From: "Matt Ettus"
To: "Gabriel Morel"
Cc:
Sent: Wednesday, January 12, 2011 2:43 PM
Subject: Re: [Discuss-gnuradio] Finally compiled USRP2 code works fine with
UDPimage ...but not with compiled Raw Ethernet Image
Matt: If the raw ethernet version can onl
On Jan 12, 2011, at 2:56 PM, Moeller wrote:
> On 12.01.2011 14:25, Michael Dickens wrote:
>> the CPU). I think that if a GPU can be used, it will be most effective in
>> things like filterbanks, or when searching for packets (via their unique
>> sync sequence, so matched filtering), or very larg
>From the product brochure:
"The entire USRP design is open source, including schematics,
firmware, drivers, and even the FPGA and daughterboard designs.
When combined with the open source GNU Radio software, you
get a completely open software radio system enabling host-based
signal processing on
A little something to help along the newcomers like me :-)
In Fedora 14, I installed all packages except fftw using the package
manager. I had to install fftw from source because gnuradio requires a
custom-built single precision floating point version of fftw
I haven't had to install FFTW f
On Wed, 2011-01-12 at 13:43 -0600, John Andrews wrote:
> Hi,
> Suppose I have two gnuradio blocks called gr_ACQUISITION and
> gr_TRACKING where, gr_TRACKING is dependent upon some result derived
> from gr_ACQ block. Is it possible to pass certain messages to gr_TRACK
> in order to change its state
A little something to help along the newcomers like me :-)
Unoffical installation guide for gnuradio on Fedora 14, January 2011 (Note
the gnuradio installation procedure may change and hence render this guide
unusable)
===
On 12.01.2011 14:25, Michael Dickens wrote:
> the CPU). I think that if a GPU can be used, it will be most effective in
> things like filterbanks, or when searching for packets (via their unique sync
> sequence, so matched filtering), or very large FIR filters -- places where a
> LOT of computa
Hi,
Suppose I have two gnuradio blocks called gr_ACQUISITION and gr_TRACKING
where, gr_TRACKING is dependent upon some result derived from gr_ACQ block.
Is it possible to pass certain messages to gr_TRACK in order to change its
state while the flowgraph is running? One way to do is to have an outpu
Matt: If the raw ethernet version can only be compile with ISE 10.1, why
the bin file on the net is 842.4KB. When I compile the project on
ISE10.1, the bin file is 837KB
Gabriel,
I can't follow what you are doing here. Do you want the raw ethernet
version or the udp version? Which versio
schrieb Marcus D. Leech am 2011-01-12 02:40:
There is a lot of people outside the Linux world, especially in the
non-academic hobbyist corner. These people seem to me to try to work
with least possible changes, that is install no new OS, install no
additional tricky exotic drivers, and at most plu
- Original Message -
From: "Matt Ettus"
To: "anirudh2059."
Cc:
Sent: Wednesday, January 12, 2011 2:10 PM
Subject: Re: [Discuss-gnuradio] Finally compiled USRP2 code works fine with
UDPimage ...but not with compiled Raw Ethernet Image
On 01/12/2011 05:13 AM, anirudh2059. wrote:
H
On 01/12/2011 05:13 AM, anirudh2059. wrote:
Hi all,
I have successfully generated a usrp2 FPGA image in ISE 12.3 (ubuntu 10.10
32 bit version). When I burn my FPGA image with the UDP image (obtained from
the repository) and I port it everything works fine.
:-D
But when I use the FPGA image
Hi everyone,
I recently compiled and installed gnuradio.
I then tried to find the usrp2:
#find_usrps
00:50:c2:85::3b:5c hw_rev = 0x0400
Next I tried to plot an FFT of the GPS L1 signal (note that my
daughterboard is a dbsrx2)
#usrp2_fft.py -f 1.57542G
usrp2: channel 0 not receiving
usrp2::r
Hi everyone,
I recently compiled and installed gnuradio.
I then tried to find the usrp2:
#find_usrps
00:50:c2:85::3b:5c hw_rev = 0x0400
Next I tried to plot an FFT of the GPS L1 signal (note that my daughterboard
is a dbsrx2)
#usrp2_fft.py -f 1.57542G
usrp2: channel 0 not receiving
usrp2::rx_s
On Wed, Jan 12, 2011 at 11:03 AM, Tom Rondeau wrote:
>
> I wanted to throw out another idea that no one seems to be bringing
> up, and this relates to a comment back about how CUDA is limited
> because of the bus transfers. That's not CUDA that is doing that but
> the architecture of the machine a
I suggest you to first look into the USRP documentation available on
gnuradio website. In it you will learn how a USRP upcoverts and downconverts
a signal. In gnuradio we always deal with baseband signals i.e. the signal
reaching your computer from the usrp or the signal entering the usrp from
the
Have it a ise10 branch like it have a ise12 branch? Because the main repo
in fpga.git don't compile. It have any difference between compilation on
windows or on linux, some engineer of the ETS confirm that. Can anybody try
to compile the main project of fpga.git and try it with a USRP2? For
On 01/12/2011 08:17 AM, Patrick Strasser wrote:
>
> Now that is not exactly the cheap one, but with its 150MSPS it would be
> quite a frequency range with low additional effort.
>
> What would be the goal for such a device? Which bandwidth are of
> interest, which dynamic ranges? Which frequency ra
On Wed, Jan 12, 2011 at 9:56 AM, Steven Clark wrote:
> On Wed, Jan 12, 2011 at 2:44 AM, Moeller wrote:
>>
>> On 11.01.2011 23:13, Andrew Hofmaier wrote:
>> > I've begun to look into accelerating GNURadio applications with Nvidia
>> > CUDA GPU's
>> > and have scanned through the archives of the di
On 01/12/2011 03:20 AM, Moeller wrote:
> I have no experience with such FPGA evaluation kits.
> Is there an easy way to attach a RF daughter board and ADC/DAC?
> What bus would be suitable, Rocket-IO or some parallel digital ports?
> I didn't find analog ports on the board.
>
>
The standard for
Hi All,
I have USRP1(4.5 Version) purchased from Matt Ettus around 2 years back.
Am interested to sell them at half price. I have two mother boards with four
daughter boards. I had purchased it for experimenting MIMO based designs.
Since am not at all using them, now am planning to sell them. Boa
On Wed, Jan 12, 2011 at 2:44 AM, Moeller wrote:
> On 11.01.2011 23:13, Andrew Hofmaier wrote:
> > I've begun to look into accelerating GNURadio applications with Nvidia
> CUDA GPU's
> > and have scanned through the archives of the discussion list. I had two
> > questions on the topic:
> >
> > 1.
Has anyone thought about something like Apple's Core Image for signal
processing? Core Image lets you express image filters in a C-like filter
language (a subset of GLSL). You chain a set of filters together to achieve the
desired effect and then at runtime Core Image uses an LLVM complier to ge
I have a feeling -- from working with OpenCL for a while now (but, not in GNU
Radio yet), watching profiling timing information (how long it takes to move
data around, how long kernels take to get queued and executed) -- that what
folks here have written seems mostly true: there is -significant-
schrieb Marcus D. Leech am 2011-01-12 02:40:
> Well, I *personally* don't care very much about random-disk-noise, errr,
> I mean Windows,
> but I'm sure others do :-)
There is a lot of people outside the Linux world, especially in the
non-academic hobbyist corner. These people seem to me to try
Hi all,
I have successfully generated a usrp2 FPGA image in ISE 12.3 (ubuntu 10.10
32 bit version). When I burn my FPGA image with the UDP image (obtained from
the repository) and I port it everything works fine.
:-D
But when I use the FPGA image with the raw ethernet image there is a
problem
On Wed, Jan 12, 2011 at 7:17 AM, Moeller wrote:
> You need a critical mass of developers to start a GNU-like open hardware.
> Anybody interested?
> It's a lot of work for a single person, but not so much in a shared effort.
I absolutely agree. Production costs may be high for an individual
tryi
On 01/12/2011 08:44 AM, Moeller wrote:
> On 11.01.2011 23:13, Andrew Hofmaier wrote:
>> I've begun to look into accelerating GNURadio applications with Nvidia CUDA
>> GPU's
>> and have scanned through the archives of the discussion list. I had two
>> questions on the topic:
>>
>> 1. Is the CUDA-
On 12.01.2011 09:11, Marcus D. Leech wrote:
>
>> http://www.eetimes.com/electronics-products/fpga-pld-products/4103784/-395-Virtex-5-FXT-FPGA-evaluation-kit
>>
> There's also the Xilinx SP601, which has roughly half the number of
> logic blocks as the board you
> mentioned above, but is also o
On 01/12/2011 02:32 AM, Moeller wrote:
> Maybe an FPGA Experimentation kit could be extended with an RF/Sampling part:
>
> $400 price class, includes PowerPC, 64 DSP slices,
> Gigabit Ethernet, 64 MB RAM, just RF part and A/D converters are missing:
> http://www.eetimes.com/electronics-products/fpg
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