[8100296b] system_call_fastpath+0x16/0x1b
Luca
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-dev_private at that point is NULL and is initialied only a few lines
later.
Signed-off-by: Luca Tettamanti kronos...@gmail.com
---
I'm beginnig to dive into DRMKMS, that assignment really confused me :P
drivers/gpu/drm/i915/i915_dma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion
the
KMS feature: drm_core_check_feature(dev, DRIVER_MODESET).
I'm note sure how to check that a device is graphic card though :|
Luca
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It seems to me that Linus' technical argument is indeed being mostly ignored.
While breaking the ABI is unfortunate, the real problem that Linus
complained about is that you can't install several userspace versions
side-by-side.
This means that if you install your new kernel and userspace,
I think you need to be clearer about that. Your distribution packaging
may not support that out of the box. There are a variety of ways to do
almsot all of this including having entire parallel X installs for
development work.
Sure, but each user must manually find out how to setup that, and
So overall, I'd say that we spent about a month of developer time
at least between jbarnes, ickle, and myself, on extending the execbuf
interface to add a flag saying dear kernel, please don't do this bit of
work on this buffer, because I don't need it and it makes things slow.
Perhaps then,
While this is almost surely a good idea, note that userspace caching
and suballocation substantially improves Mesa performance even on PCIe
systems.
This is mostly due to the unavoidable overhead of kernel calls and
pagetable modifications, as well as the avoidable linear search the
kernel
^^^ Luca, I've never seen this show up high on a profile (yet). Do you see
that with Nouveau? I used to have an rb-tree implementation of drm_mm_xxx
lying around, but I didn't use it because I didn't have a case where it
showed up?
Yes, before I did userspace allocation, in doom3 profiles
]0 engine/memory: 22/30
[ 156.578942] [drm]1 engine/memory: 22/30
[ 156.578981] [drm]2 engine/memory: 22/30
radeon_pick_power_state with a mobility chip only uses battery and
powersave states.
Luca
Alex,
AMD GPU clock tool also reports an Internal TSS, do you have clue on this one?
Luca
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With the exception of adding a new unused API in the form of
gem_free_object_unlocked driver hook, I like this.
Nouveau and Radeon should be able to use it (by setting it to the same
function used for gem_free_object) with little or no modification
(they rely on TTM locking).
I didn't do it
struct_mutex and just calls -gem_free_object
Signed-off-by: Luca Barbieri l...@luca-barbieri.com
---
drivers/gpu/drm/drm_gem.c | 49
include/drm/drmP.h| 28 +++--
2 files changed, 69 insertions(+), 8 deletions(-)
diff --git
Mostly obvious simplifications.
The i915 pread/pwrite ioctls, intel_overlay_put_image and
nouveau_gem_new were incorrectly using the locked versions
without locking: this is also fixed in this patch.
Signed-off-by: Luca Barbieri l...@luca-barbieri.com
---
drivers/gpu/drm/drm_gem.c
If you set to uncached | cached, VRAM-SYSTEM will still be broken
because it will choose uncached.
Assuming VRAM is uncached and not WC of course.
The reasoning still holds if you replace all instances of uncached with WC.
I see a problem with this.
If you have uncached TT (e.g. AGP) you want to get uncached for
TT-SYSTEM, but you want cached for VRAM-SYSTEM.
If you set SYSTEM to uncached, then VRAM-SYSTEM will broken, and if
you set SYSTEM to cached, TT-SYSTEM will be broken.
If you set to uncached | cached,
Idea is to mask all move which involve TT (AGP) with the agp_caching_mask,
it's easy to do in radeon ttm layer code and i believe it's easy to do
in nouveau
too. On non AGP you set agp_caching_mask to UC|WC|CACHED.
Sure, but isn't that uglier and much more ad-hoc that the patch I proposed?
Your patch remove the consistency of caching attribute and make move btw
non fixed area different than others move, while driver can already achieve
so.
It is already different, because TTM does it by changing the page
attributes, as opposed to copying data.
Thus, it is useful to preserve the
context but I still see corruption (I'm using a M76).
Luca
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/TT.
In theory, we should also do that if moving between two device memory
spaces that are backend by the same physical memory area.
However, I'm not sure how to do that in the current TTM framework and
I suspect no card/driver uses memory spaces in that way.
Signed-off-by: Luca Barbieri l...@luca
Nvidia cards have a synchronization primitive that could be used to
synchronize several FIFOs in hardware (AKA semaphores, see [1] for an
example).
Does this operate wholly on the GPU on all nVidia cards?
It seems that at least on some GPUs this will trigger software
methods that are
At a first glance:
1) We probably *will* need a delayed destroyed workqueue to avoid wasting
memory that otherwise should be freed to the system. At the very least, the
delayed delete process should optionally be run by a system shrinker.
You are right. For VRAM we don't care since we are the
I'm not sure I understand your proposal correctly.
It seems your proposoal is similar to mine, replacing the term fence
nodes with ttm transactions, but I'm not sure if I understand it
correctly
Here is some pseudocode for a improved, simplified version of my proposal.
It is modified so that
If not, it could possibly be hacked around by reading from a DMA
object at the address of the fence sequence number and then resizing
the DMA object so that addresses from a certain point on would trigger
a protection fault interrupt.
I don't think you can safely modify a DMA object without
Doing it without software methods means you need to have a semaphore
that exists in the cpu domain and therefore cannot be used again
until the cpu is sure it's done. So that will probably require a
rotating queue of several semaphores and a fallback to cpu waiting.
Why would it need a
The card also keeps some internal FIFO caches, so it seems to me that
getting that safe of races and efficient at the same time could be a bit
non-trivial.
Are they flushable?
It seems this *might* do the job:
if (!pfifo-cache_flush(dev))
return;
pfifo-reassign(dev, false);
We had to do a similar thing in the
Poulsbo driver and it turned out that we could save a significant amount of
CPU by using a delayed workqueue, collecting objects and destroying them
periodically.
Yes, indeed, we don't really care about a fence expiring unless we
want to use that buffer or
Also note that the delayed delete list is not in fence order but in
deletion-time order, which perhaps gives room for more optimizations.
You are right.
I think then that ttm_bo_delayed_delete may still need to be changed,
because it stops when ttm_bo_cleanup_refs returns -EBUSY, which
happens
When designing this, we should also keep in mind that some drivers
(e.g. nouveau) have multiple FIFO channels, and thus we would like a
buffer to be referenced for reading by multiple channels at once (and
be destroyed only when all fences are expired, obviously).
Also, hardware may support on-GPU
already got a reference to nentry-next.
v2 updated by me according to Thomas Hellstrom's feedback.
v3 proposed by Thomas Hellstrom. Commit comment updated by me.
Both updates fixed minor efficiency/style issues only and all three versions
should be correct.
Signed-off-by: Luca Barbieri l...@luca
and may not be possible.
From 68972c220abe3ce19eb046d72fa218646168adc7 Mon Sep 17 00:00:00 2001
From: Luca Barbieri l...@luca-barbieri.com
Date: Mon, 18 Jan 2010 19:34:53 +0100
Subject: [PATCH] drm/ttm: Fix race condition in ttm_bo_delayed_delete (v2)
ttm_bo_delayed_delete has a race condition
+ before trying to
write 0x%08X\n, reg);
Cosmetic issue: a space is missing between supplied and before.
Luca
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and free of races, but please double check this.
Signed-off-by: Luca Barbieri l...@luca-barbieri.com
---
drivers/gpu/drm/ttm/ttm_bo.c | 58 +
1 files changed, 24 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm
On Wed, Dec 30, 2009 at 08:03:53AM +0100, Michel Dänzer wrote:
On Tue, 2009-12-29 at 19:35 +0100, Luca Tettamanti wrote:
Il Mon, Dec 28, 2009 at 05:27:13PM -0500, Alex Deucher ha scritto:
2009/12/28 Luca Tettamanti kronos...@gmail.com:
On Mon, Dec 28, 2009 at 01:32:24PM -0500, Alex
On Wed, Dec 30, 2009 at 10:56 AM, Luca Tettamanti kronos...@gmail.com wrote:
On Wed, Dec 30, 2009 at 08:03:53AM +0100, Michel Dänzer wrote:
On Tue, 2009-12-29 at 19:35 +0100, Luca Tettamanti wrote:
Il Mon, Dec 28, 2009 at 05:27:13PM -0500, Alex Deucher ha scritto:
2009/12/28 Luca Tettamanti
Il Mon, Dec 28, 2009 at 05:27:13PM -0500, Alex Deucher ha scritto:
2009/12/28 Luca Tettamanti kronos...@gmail.com:
On Mon, Dec 28, 2009 at 01:32:24PM -0500, Alex Deucher wrote:
2009/12/28 Luca Tettamanti kronos...@gmail.com:
2009/12/28 Alex Deucher alexdeuc...@gmail.com:
On Mon, Dec 28
On Sun, Dec 27, 2009 at 1:55 AM, Rafał Miłecki zaj...@gmail.com wrote:
W dniu 26 grudnia 2009 20:08 użytkownik Alex Deucher
alexdeuc...@gmail.com napisał:
It may be that the engine doesn't like to be reclocked while it's
running. Perhaps we should use the GUI idle interrupt rather than
2009/12/28 Alex Deucher alexdeuc...@gmail.com:
On Mon, Dec 28, 2009 at 5:53 AM, Luca Tettamanti kronos...@gmail.com wrote:
On Sun, Dec 27, 2009 at 1:55 AM, Rafał Miłecki zaj...@gmail.com wrote:
W dniu 26 grudnia 2009 20:08 użytkownik Alex Deucher
alexdeuc...@gmail.com napisał:
It may
The mask happens to be the same, but the IH is reading the status, not the
not the control register.
Signed-off-by: Luca Tettamanti kronos...@gmail.com
---
drivers/gpu/drm/radeon/rs600.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux-2.6.git/drivers/gpu/drm/radeon/rs600.c
On Mon, Dec 28, 2009 at 01:32:24PM -0500, Alex Deucher wrote:
2009/12/28 Luca Tettamanti kronos...@gmail.com:
2009/12/28 Alex Deucher alexdeuc...@gmail.com:
On Mon, Dec 28, 2009 at 5:53 AM, Luca Tettamanti kronos...@gmail.com
wrote:
On Sun, Dec 27, 2009 at 1:55 AM, Rafał Miłecki zaj
2009/12/25 Rafał Miłecki zaj...@gmail.com:
W dniu 24 grudnia 2009 23:19 użytkownik Luca Tettamanti
kronos...@gmail.com napisał:
2009/12/24 Rafał Miłecki zaj...@gmail.com:
W dniu 24 grudnia 2009 17:32 użytkownik Luca Tettamanti
kronos...@gmail.com napisał:
I think it would be safer to execute
; the rest of the ops seem safe.
What do you think?
Luca
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2009/12/24 Rafał Miłecki zaj...@gmail.com:
W dniu 24 grudnia 2009 17:32 użytkownik Luca Tettamanti
kronos...@gmail.com napisał:
I think it would be safer to execute that code in the IH (or in a tasklet,
which is guaranteed to run after the handler); the only problem I see
A drm_handle_t can be safely converted to a pointer and back even on a
64bit platform (where the size is not the same).
Signed-off-by: Luca Tettamanti kronos...@gmail.com
---
I looked at the kernel part of the ioctl and it seems that the handle is
always a 32bit quantity, but please double check
On Wed, Dec 23, 2009 at 10:05 PM, Robert Noland rnol...@2hip.net wrote:
On Wed, 2009-12-23 at 21:36 +0100, Luca Tettamanti wrote:
A drm_handle_t can be safely converted to a pointer and back even on a
64bit platform (where the size is not the same).
Signed-off-by: Luca Tettamanti kronos
2009/12/19 Christian König deathsim...@vodafone.de:
Hi,
Am Samstag, den 19.12.2009, 15:37 +0100 schrieb Luca Tettamanti:
- first of all, I have a M56 (RV630) which lacks the PCI audio
function, I guess in this case the audio shouldn't be enabled at all
That's definitely a bug, AFAIK
2009/12/20 Christian König deathsim...@vodafone.de:
Am Sonntag, den 20.12.2009, 19:10 +0100 schrieb Luca Tettamanti:
Typo, sorry: it's a M76 (the core is a RV630).
Interesting, I always thought that every R6xx based chipset has an audio
codec. Could you make sure that there is no audio codec
) interacts (can someone point me to the relevant docs?).
Maybe a tighter integration between them is needed?
thanks,
Luca
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Luca
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Il Thu, May 17, 2007 at 06:04:54PM -0700, Jesse Barnes ha scritto:
On Thursday, May 17, 2007, Luca Tettamanti wrote:
Il Thu, May 17, 2007 at 03:37:45PM -0700, Jesse Barnes ha scritto:
This patch adds the core of the new DRM based modesetting system.
A couple of comments on drm_fb since
.
+
+ printk(KERN_INFO fb%d: %s frame buffer device\n, info-node,
+info-fix.id);
+ return 0;
+}
+EXPORT_SYMBOL(drmfb_probe);
Luca
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-prefetchable) [size=4K]
[virtual] Expansion ROM at 2800 [disabled] [size=128K]
Capabilities: [50] AGP version 1.0
Capabilities: [5c] Power Management version 1
Tell me, if you need some information.
What i try to do? help me.
thank you.
bye.
Luca
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On 5/11/06, Matthias Hopf [EMAIL PROTECTED] wrote:
On May 03, 06 14:35:45 +0200, Luca Dionisi wrote:
On 3/28/06, Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
It will, just no yet. It's beeing developped on intel chipsets at the
moment and will probably be ported over at one point. I can't
precisely.
As far as you know, does the ATI binary driver have FBO support?
I didn't try it, yet, but should I try, may I expect better performance?
TIA
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Get
What does it mean? That is, is the driver _never_ going to have that
support?
It will, just no yet. It's beeing developped on intel chipsets at the
moment and will probably be ported over at one point. I can't tell more
precisely.
Thanks Ben, have a nice work.
--Luca
On 3/25/06, Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
On Sat, 2006-03-25 at 02:26 +0100, Luca Dionisi wrote:
I'm having problems with Xorg built from cvs sources very recently.
I've also built from cvs sources libdrm and the latest kernel (2.6.16)
with the drm enabled for my card
I'm having problems with Xorg built from cvs sources very recently.
I've also built from cvs sources libdrm and the latest kernel (2.6.16)
with the drm enabled for my card (radeon)
I don't know for sure, but I think my problem is with the
video driver (the ati open source driver)
The syptom is
it seems a different problem.
Luca
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Can you post a brief summary?
Luca
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Luca
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Il Fri, Nov 11, 2005 at 12:40:10PM -0500, Felix Kühling ha scritto:
Am Freitag, den 11.11.2005, 16:26 +0100 schrieb Luca:
Hi,
I installed the latest X.Org server from Debian (6.8.99.901.dfsg.1-2)
and decided to try DRI (I have a Radeon 9500 Pro).
When X.Org starts with AGPFastWrite
2.3.2
Dynamic linker (ldd) 2.3.2
Procps 3.2.1
Net-tools 1.60
Kbd[opzione...]
Console-tools 0.2.3
Sh-utils 5.2.1
udev 042
Regards,
Luca
-BEGIN PGP SIGNATURE
As suggested I tried to connect a vga cable, and seem to work even in dvi mode.
Thanks for the info!
regards,
Luca
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I tried to use proprietary ati driver to see if they have the same problem and
everythink worked well even without the vga cable connected.
This seems to exclude a hardware problem.
regards
Luca
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I tried to use proprietary ati driver to see if they have the same problem and
everythink worked well even without the vga cable connected.
This seems to exclude a hardware problem.
regards
Luca
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/Building but the problem is not resolved.
I attached the output of glxinfo and xorg.conf
I don't know what log can be useful for understand the problem, so I attend your
requests ;)
regards,
Luca
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