Could you update the function comments of InitDmar() and
SiliconInitializedPpiNotifyCallback()?
There are two lines of " DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar)) " in
InitDmar(), are they added on purpose?
Thanks,
Star
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@l
The patch shouldn't impact functionality.
Original code records the ImageHandle of Option ROM by creating a
new entry. It's not necessary.
The patch updates the ImageHandle in the old entry.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni
Cc: Star Zeng
---
MdeMo
The patch doesn't impact real functionality.
It only renames EFI_PCI_ROM_IMAGE_MAPPING to PCI_ROM_IMAGE,
and changes prototype of PciRomAddImageMapping so that
no explicit type cast is needed when calling this function.
It also removes unused field RomBase from PCI_IO_DEVICE structure.
Contribute
It's a regression of below commit:
SHA-1: 8be37a5cee700777ca8e8e8a34cc2225b21931a7
* MdeModulePkg/SecurityStubDxe: Defer 3rd party image before EndOfDxe
When PciBus driver fails to load the Option ROM, it doesn't produce
BusOverride protocol. It was a correct behavior before the above
commit. But
It's a regression of below commit:
SHA-1: 8be37a5cee700777ca8e8e8a34cc2225b21931a7
* MdeModulePkg/SecurityStubDxe: Defer 3rd party image before EndOfDxe
When PciBus driver fails to load the Option ROM, it doesn't produce
BusOverride protocol. It was a correct behavior before the above
commit. But
Reviewed-by: Star Zeng
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jiewen
Yao
Sent: Friday, October 27, 2017 1:40 PM
To: edk2-devel@lists.01.org
Cc: Zeng, Star
Subject: [edk2] [PATCH V2 1/2] IntelSiliconPkg/VtdPmrPei: Add premem support.
Re
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Guo Mang
---
Platform/BroxtonPlatformPkg/BiosId.env | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/BroxtonPlatformPkg/BiosId.env
b/Platform/BroxtonPlatformPkg/BiosId.env
index 9456cb8..d32d1d0 1
>v4:
> No content change but move this patch to be the first one
Cc: Star Zeng
Cc: Eric Dong
Cc: Jiewen Yao
Suggested-by: Ayellet Wolman
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang
---
MdeModulePkg/MdeModulePkg.dec | 60 +
> v4
> Coding style cleanup
> v3
> Fix build error with GCC toolchain
> v2
> According to Eric's feedback:
> a. Remove local variable initializer with memory copy from globals
> b. Add comment for the use of mOnGuarding
> c. Change map table dump code to use DEBUG_PAGE|DEBUG_POOL level
>messa
Heap guard feature will frequently update page attributes. The debug message
in CpuDxe driver will slow down the boot performance noticeably. Changing the
debug level to DEBUG_POOL and DEBUG_PAGE to reduce the message output for
normal debug configuration.
Cc: Eric Dong
Cc: Jiewen Yao
Suggested-
> v4
> a. According to Ray's feedback, change the name of new protocol definitions
from EFI_ to EDKII_.
> b. Coding style cleanup
> v3
> According to Jiewen's feedback, use new added protocol
> gEdkiiSmmMemoryAttributeProtocolGuid
> to update memory attribute.
>
> v2
> According to Eric'
The new protocol gEdkiiSmmMemoryAttributeProtocolGuid is intended for
PiSmmCore to be able to change memory page attributes for the sake of
heap guard feature.
This protocol provides three interfaces to get/set/clear page attribute.
struct _EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL {
EDKII_SMM_GET_ME
> v4
> a. According to Ray's feedback, change the definition name prefix from EFI_
>to EDKII_
> b. Coding style cleanup
> c. Add more comments for the use of PcdHeapGuardPropertyMask
> v3
> According to Jiewen's feedback, implement new protocol
> gEdkiiSmmMemoryAttributeProtocolGuid
> to c
> Path V4 changes:
> a. Change names of gEdkiiSmmMemoryAttributeProtocolGuid related
>definitions from EFI_ to EDKII_
> b. Coding style cleanup
> c. Split patches in a more reasonable order and groups
> Patch V3 changes:
> a. Add new protocol gEdkiiSmmMemoryAttributeProtocolGuid to do
>mem
Heap guard feature needs paging to work properly. 64-bit BIOS uses
PcdDxeIplBuildPageTables to control the page table setup. 32-bit BIOS
has to check heap guard feature to decide enabling paging or not.
Cc: Star Zeng
Cc: Eric Dong
Cc: Jiewen Yao
Suggested-by: Ayellet Wolman
Contributed-under:
Hi Ard,
Thanks for you comments. Please see my comments below.
On 10/10/2017 03:59 AM, Ard Biesheuvel wrote:
On 10 October 2017 at 04:41, Daniil Egranov wrote:
Hi Ard, Ray,
Thanks for your comments.
On 10/09/2017 07:23 AM, Ard Biesheuvel wrote:
On 9 October 2017 at 11:40, Ard Biesheuvel
Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.
This update is to demonstrate how to support pre-mem VTd usage.
Cc: Star Zeng
Contributed-under: Ti
V2 =
Minor enhancement:
Replace IsDmaProtectionEnabled() by GetDmaProtectionEnabledEngineMask(),
for better code management.
V1 =
This series patch adds Pre-Memory DMA protection in PEI.
The purpose is to make sure when the system memory is initial
Remove memory discovered dependency to support both premem
VTD_INFO_PPI and postmem VTD_INFO_PPI.
If VTD_INFO_PPI is installed before memory is ready, this
driver protects all memory region.
If VTD_INFO_PPI is installed or reinstalled after memory
is ready, this driver allocates DMA buffer and pro
Set a PCI IO attribute allowing 64-bit DMA transfer.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Daniil Egranov
---
EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/S
Corrected memory allocation during startup.
Added driver stop procedure and exit boot event handler.
Added driver memory and protocols cleanup procedures.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Daniil Egranov
---
EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c |
This set of patches fixes an issue with 64-bit DMA and implements
the missing exit boot event and driver stop functionality including
memory/protocols cleanup procedure.
Daniil Egranov (4):
Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations
Drivers/SataSiI3132Dxe: Allow 64-bit DMA
Saved controller specific data into the driver's information structure.
Removed global variable indicating the driver's status and added
check for the driver's status based on the available protocol.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Daniil Egranov
---
Embedd
The ATA pass through read should use PCI IO bus master write operation
and ATA pass through write should use PCI IO bus master read operation
as the read and write operations executed from the bus master's point
of view.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Daniil
I think it does exist.
If I use IOMMU to prevent all DMA transaction, I have seen XHCI driver and AHCI
driver reporting error.
Thank you
Yao Jiewen
> -Original Message-
> From: Ni, Ruiyu
> Sent: Friday, October 27, 2017 10:38 AM
> To: Yao, Jiewen ; Laszlo Ersek ;
> Zeng, Star ; edk2-deve
Reviewed-by: Hao Wu
Best Regards,
Hao Wu
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jiaxin
> Wu
> Sent: Friday, October 27, 2017 10:24 AM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A; Ye, Ting; Fu, Siyuan; Wu, Jiaxin
> Subject: [edk2]
Reviewed-by: Star Zeng after the minor typo " isse " is
fixed to " issue ".
Thanks,
Star
-Original Message-
From: Laszlo Ersek [mailto:ler...@redhat.com]
Sent: Thursday, October 26, 2017 11:48 PM
To: edk2-devel-01
Cc: Aleksei Kovura ; Ard Biesheuvel
; Dann Frazier ; Dong, Eric
; Zeng
Hi,
The TimeOut handling in SerialRead() in SerialDxe(MdeModulepkg),
IsaSerialRead() in IsaSerialDxe(IntelFrameworkModulePkg) and SerialRead() in
PciSioSerialDxe(MdeModulePkg) are consistent, and we did not see this kind of
"slow down" before.
After some investigation, I found it is related t
I also doubt such device driver exists.
Thanks/Ray
> -Original Message-
> From: Yao, Jiewen
> Sent: Friday, October 27, 2017 9:47 AM
> To: Ni, Ruiyu ; Laszlo Ersek ; Zeng,
> Star ; edk2-devel@lists.01.org
> Cc: Ard Biesheuvel ; Kinney, Michael D
>
> Subject: RE: [edk2] [PATCH] IntelSilic
Cc: Wu Hao A
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
---
NetworkPkg/IScsiDxe/IScsiConfig.c | 4
1 file changed, 4 insertions(+)
diff --git a/NetworkPkg/IScsiDxe/IScsiConfig.c
b/NetworkPkg/IScsiDxe/IScsiConfig.c
index 338
Cc: Wu Hao A
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
---
NetworkPkg/HttpBootDxe/HttpBootDxe.c | 50 +++-
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/NetworkPkg/HttpBootDxe/Htt
Cc: Wu Hao A
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
Jiaxin Wu (2):
NetworkPkg/HttpBootDxe: Add check to avoid use NULL pointer
NetworkPkg/IScsiDxe: Add check to avoid use NULL pointer
NetworkPkg/HttpBootDxe/HttpBootDxe.c
Chris:
Ni, Ruiyu has sent this patch yesterday.
>-Original Message-
>From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>Chris Ruffin
>Sent: Friday, October 27, 2017 9:04 AM
>To: edk2-devel@lists.01.org
>Subject: [edk2] [PATCH] MdePkg/Include: fix incorrect structure
I think the error might be PCI device specific.
BTW: We already have bugzillar on that
https://bugzilla.tianocore.org/show_bug.cgi?id=739
It has been validated by Microsoft. We can validate more device cards to see if
there is any issue.
Thank you
Yao Jiewen
> -Original Message-
> Fro
Hi Laszlo,
> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Thursday, October 26, 2017 9:27 PM
> To: Wang, Jian J
> Cc: Yao, Jiewen ; edk2-devel@lists.01.org; Kinney,
> Michael D ; Wolman, Ayellet
> ; Dong, Eric ; Zeng, Star
>
> Subject: Re: [edk2] [PATCH v3 0
Laszlo,
Update both and pushed the change at 86121874.
Thanks,
Eric
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Laszlo Ersek
> Sent: Thursday, October 26, 2017 4:26 PM
> To: Dong, Eric ; edk2-devel@lists.01.org
> Cc: Ni, Ruiyu
> Subjec
Brian,
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Brian J. Johnson
> Sent: Friday, October 27, 2017 4:48 AM
> To: Dong, Eric ; Laszlo Ersek ;
> edk2-devel@lists.01.org
> Cc: Ni, Ruiyu ; Paolo Bonzini
> Subject: Re: [edk2] [Patch 2/2] Ue
Hi Karunakar,
I guess you configure the VLAN on the NIC that PXE boot option selected. If so,
that's the expect behavior since the VLAN callback function will destroy the
previous NIC info including the MNP service data, then PXE driver binding
stop/start will be called again to update the devi
Hi Laszlo,
> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Thursday, October 26, 2017 6:08 PM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Yao, Jiewen ; Dong, Eric
> Subject: Re: [edk2] [PATCH] UefiCpuPkg/CpuDxe: Fix multiple entries of
> RT_CODE in memo
Changing controller's FIFO default values is not necessary and
possibly can cause instabilities, when using some devices.
Disable the modification and rely on initial settings.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas
Reviewed-by: Leif Lindholm
---
Pl
Hi,
I present you a second version of the patchset with post review
fixes and improvements. 9/10 patch was completely changed -
the diff is bigger, but such generic clock handling gives some chances
to benefit if we want to merge Xenon support with original EDK2
SdMmc driver in future. More detail
From: David Greeson
During each transaction start, clearing the I2C_CONTROL_FLAG
was surrounded by 3 uncoditional stalls. This was not necessary,
so replace them with one busy-wait loop, whose polling
count could be also safely reduced.
Above improvements result in faster transfer initialization
From: Ard Biesheuvel
MppLib may be used very early (in SEC), at which point stack protection
measures are more likely to cause harm than help, given that not even
the UART has been configured to the point where we can complain usefully.
So just disable it.
Contributed-under: TianoCore Contributi
Currently initial forcing link status happened for all ports, not only
marked as 'always-up'. Although this didn't actually matter for the MAC
settings, because MAC is automatically updated with PHY HW polling
feature of the controller, perform mv_gop110_fl_cfg only when
the appropriate flag is tru
In MvI2cStartRequest the status was assigned to the variable
without dereferencing a pointer. Fix it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas
---
Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
This patch fixes incorrect settings for UHS mode in
SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which
the latter was missing. This field should be set to:
0x4 for DDR52
0x2 for SDR50
0x1 for SDR25
0x0 for others.
This way EmmcSwitchToHighSpeed function is on par with Linux
set_uhs_signa
From: David Greeson
Although the I2C transaction routines were prepared to
return their status, they were never used. This could
cause bus lock-up e.g. in case of failing to send a
slave address, the data transfer was attempted to be
continued anyway.
This patch fixes faulty behavior by checking
Some SdMmc host controllers are run by clocks with different
frequency than it is reflected in Capabilities Register 1.
Because the bitfield is only 8 bits wide, a maximum value
that could be obtained from hardware is 255(MHz).
In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq
mem
From: Ard Biesheuvel
The MppSel definition PCDs contain 0xFF placeholders for values that
should be left untouched. MppLib needs to be taught how to take those
into account.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Signed-off-by: Marcin Wojtas
---
From: Joe Zhou
After enabling dynamic PCDs, it is possible to reconfigure
MPP during platform initialization. It occurred that due to
a faulty way of passing temporary values, information obtained
from PCDs was overwritten. This patch fixes the issue, which
on the occasion simplifies PcdToMppRegs
Fix incorrect structure definitions for PCI_REG_PCIE_SLOT_CONTROL in
PciExpress21.h.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Ruffin
---
MdePkg/Include/IndustryStandard/PciExpress21.h | 24
1 file changed, 12 insertions(+), 12 deletion
Reviewed-by: Fu Siyuan
> -Original Message-
> From: Wu, Jiaxin
> Sent: Thursday, October 26, 2017 4:27 PM
> To: edk2-devel@lists.01.org
> Cc: Karunakar P ; Ye, Ting ;
> Fu, Siyuan ; Wu, Jiaxin
> Subject: [Patch] NetworkPkg/IScsiDxe: Clear the old IFR TargetIp to avoid
> sharing it with o
Jiewen,
If the BME bit is cleared in Command register, but a device driver
uses DMA to transfer data, what kind of error will be seen by SW?
-Original Message-
From: Yao, Jiewen
Sent: Friday, October 27, 2017 8:34 AM
To: Laszlo Ersek ; Zeng, Star ;
edk2-devel@lists.01.org
Cc: Ni, Ruiyu ;
Good Info. I think a correct implementation should not use busy wait.
It should add error handling to check if there is hardware error during that.
> - busy wait (poll) unil the transfer is complete,
The process of busy wait should be something like below:
while(TRUE) {
if (error) {
On Thu, Oct 26, 2017 at 04:41:07PM +0100, Ard Biesheuvel wrote:
> > - Is there a good reason for leaving out Uhci/Ehci?
>
> No not really, other than the fact that nobody is every likely to use
> it (although I suppose you could put a UHCI PCI card into a PCIe to
> PCI bridge)
Well, more likely a
On Wed, Oct 25, 2017 at 06:59:46PM +0100, Ard Biesheuvel wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
> ---
> Platform/Socionext/DeveloperBox/DeveloperBox.dsc
>| 624
> Platfo
On Wed, Oct 25, 2017 at 06:59:47PM +0100, Ard Biesheuvel wrote:
> In order to improve the 'out of the box' experience when booting
> this system with a monitor and keyboard attached, include the serial
> console preference driver that prevents the installer GUI to only
> appear on the serial port i
On Wed, Oct 25, 2017 at 06:59:45PM +0100, Ard Biesheuvel wrote:
> Implement workaround suggested by Socionext to get legacy endpoints with
> 32-bit BARs working.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
This was the modification that made the De
On Wed, Oct 25, 2017 at 06:59:44PM +0100, Ard Biesheuvel wrote:
> The ACPI hack to support the broken Synopsys IP only works for endpoints,
> not for non-trivial topologies involving switches. Given that the Linaro
> developer board has a switch soldered on, there is really no way to do
> anything
On Wed, Oct 25, 2017 at 06:59:43PM +0100, Ard Biesheuvel wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
> ---
> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
>| 20 +
> Platform/Socionext/Syn
On Wed, Oct 25, 2017 at 06:59:42PM +0100, Ard Biesheuvel wrote:
> Now that we switched to PrePeiCore, we can execute the firmware image
> in place, using a stack and temporary heap in non-secure SRAM. This
> allows us to query the secure firmware for the size and placement of
> DRAM, and also allow
On Wed, Oct 25, 2017 at 06:59:41PM +0100, Ard Biesheuvel wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
> ---
> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++-
> Platform/Socionext/SynQuacerE
On Wed, Oct 25, 2017 at 06:59:40PM +0100, Ard Biesheuvel wrote:
> Add support for dealing with capsules left in memory by the OS before
> reboot. This needs to be done early, before the memory is reused, which
> is why the initial handling must reside here.
>
> Contributed-under: TianoCore Contrib
On Wed, Oct 25, 2017 at 06:59:39PM +0100, Ard Biesheuvel wrote:
> In order to support capsule update, implement PlatformFlashAccessLib that
> exposes write access to the UEFI NOR partition.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
> ---
>
> Sil
On Wed, Oct 25, 2017 at 06:59:37PM +0100, Ard Biesheuvel wrote:
> From: Pipat Methavanitpong
>
> This imports the driver sources provided by Socionext for the FIP006
> SPI NOR flash device found on SynQuacer SoCs. It has been slightly
> tweaked to bring it up to date with the changes made on the
On 10/25/2017 08:13 PM, Dong, Eric wrote:
Laszlo,
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
Laszlo Ersek
Sent: Wednesday, October 25, 2017 11:08 PM
To: Dong, Eric ; edk2-devel@lists.01.org
Cc: Ni, Ruiyu ; Paolo Bonzini
Subject: Re: [edk2
On Thu, Oct 26, 2017 at 9:48 AM, Laszlo Ersek wrote:
> Clearing I/O port decoding in the PCI command register at
> ExitBootServices() breaks IDE boot in Windows, on QEMU's "pc" (i440fx)
> machine type. (AHCI boot on "q35" is unaffected.) Windows seems repeatedly
> stuck, apparently waiting for a t
Hi Laszlo,
Thank you for your help.
On 26/10/17 16:20, Laszlo Ersek wrote:
On 10/26/17 17:13, Laszlo Ersek wrote:
Hello Julien,
On 10/26/17 13:05, Julien Grall wrote:
Hi all,
I was doing more testing of UEFI in Xen guests and noticed some slow
down when using the shell. The characters are o
On Wed, Oct 25, 2017 at 06:59:35PM +0100, Ard Biesheuvel wrote:
> Add a device tree description of the SynQuacer SoC, and expose it for
> the SynQuacerEvalBoard platforms. This includes the menu option in the
> UEFI boot menu to switch between ACPI and DT.
>
> Contributed-under: TianoCore Contribu
On Wed, Oct 25, 2017 at 06:59:34PM +0100, Ard Biesheuvel wrote:
> Enable ACPI support for the SynQuacerEvalBoard platform: add descriptions
> of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
> including the MSI routing via the GICv3 ITS.
>
> Note that PCIe support is limited to
On Thu, 2017-10-26 at 11:13 +0100, Achin Gupta wrote:
> Hi Supreeth,
>
> some CIL,
>
> On Wed, Oct 25, 2017 at 05:32:57PM +0100, Supreeth Venkatesh wrote:
> >
> > PI v1.5 Specification Volume 4 defines Management Mode Core
> > Interface
> > and defines EFI_MM_COMMUNICATION_PROTOCOL. This protoco
Clearing I/O port decoding in the PCI command register at
ExitBootServices() breaks IDE boot in Windows, on QEMU's "pc" (i440fx)
machine type. (AHCI boot on "q35" is unaffected.) Windows seems repeatedly
stuck, apparently waiting for a timeout of sorts.
This is arguably a Windows bug; a native OS
On 26 October 2017 at 16:38, Leif Lindholm wrote:
> On Wed, Oct 25, 2017 at 06:59:32PM +0100, Ard Biesheuvel wrote:
>> Wire up the various drivers and libraries for the SynQuacerEvalBoard
>> platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
>> and the various bus, partition and fi
On Wed, Oct 25, 2017 at 06:59:33PM +0100, Ard Biesheuvel wrote:
> Add the NETSEC driver to the SynQuacerEvalBoard platform.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
> ---
> Platform/Socionext/SynQuacerEvalBoard/SynQ
On Wed, Oct 25, 2017 at 06:59:32PM +0100, Ard Biesheuvel wrote:
> Wire up the various drivers and libraries for the SynQuacerEvalBoard
> platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
> and the various bus, partition and file system drivers that we need
> to make use of PCIe dev
On 10/26/17 17:13, Laszlo Ersek wrote:
> Hello Julien,
>
> On 10/26/17 13:05, Julien Grall wrote:
>> Hi all,
>>
>> I was doing more testing of UEFI in Xen guests and noticed some slow
>> down when using the shell. The characters are only echoed after a second
>> or two that is a bit annoying.
>>
>
On Thu, 2017-10-26 at 05:05 +, Udit Kumar wrote:
> Hi
>
> >
> > + Status = gBS->AllocatePages (AllocateAddress,
> > + EfiRuntimeServicesData,
> > + EFI_SIZE_TO_PAGES
> > (mNsCommBuffMemRegion.Length),
> > +
On 26 October 2017 at 16:02, Leif Lindholm wrote:
> On Wed, Oct 25, 2017 at 06:59:28PM +0100, Ard Biesheuvel wrote:
>> This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
>> code provided by Socionext. It can boot into the UiApp menu screen
>> or the UEFI Shell, but lacks support fo
On Wed, Oct 25, 2017 at 06:59:31PM +0100, Ard Biesheuvel wrote:
> The SynQuacer SOC has two separate PCIe RCs, which means there is
> no single value for the translation offset between I/O port accesses
> and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
> that takes the tw
Hello Julien,
On 10/26/17 13:05, Julien Grall wrote:
> Hi all,
>
> I was doing more testing of UEFI in Xen guests and noticed some slow
> down when using the shell. The characters are only echoed after a second
> or two that is a bit annoying.
>
> The change that introduced this issue is 4cf3f37
On 26 October 2017 at 16:10, Leif Lindholm wrote:
> On Wed, Oct 25, 2017 at 06:59:30PM +0100, Ard Biesheuvel wrote:
>> Implement the glue library that exposes the PCIe root complexes to
>> the generic PCI host bridge driver. Since that driver is the first
>> one to access the PCI config space, put
On Wed, Oct 25, 2017 at 06:59:30PM +0100, Ard Biesheuvel wrote:
> Implement the glue library that exposes the PCIe root complexes to
> the generic PCI host bridge driver. Since that driver is the first
> one to access the PCI config space, put the low level init code for
> the RCs into this library
On 10/26/17 13:34, Ard Biesheuvel wrote:
> On 26 October 2017 at 12:33, Leif Lindholm wrote:
>> On Thu, Oct 26, 2017 at 12:11:16PM +0100, Ard Biesheuvel wrote:
>>> On 26 October 2017 at 12:09, Laszlo Ersek wrote:
On 10/26/17 12:12, Ard Biesheuvel wrote:
> The standard GCC preprocessor we
2017-10-26 16:52 GMT+02:00 Leif Lindholm :
> On Thu, Oct 26, 2017 at 04:29:39PM +0200, Marcin Wojtas wrote:
>> 2017-10-26 16:02 GMT+02:00 Leif Lindholm :
>> >> > Why is Capability.BaseClkFreq the wrong frequency to use?
>> >>
>> >> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255M
On 10/26/17 15:36, Yao, Jiewen wrote:
> Hi Laszlo
> I have discussed this with Mike Kinney offline and some Microsoft engineers.
>
> We believe the impact of BME disable is different with the impact of SEV.
>
> For SEV, if a DMA buffer is in transition when SEV bit change, the DMA will
> still b
On Wed, Oct 25, 2017 at 06:59:29PM +0100, Ard Biesheuvel wrote:
> Having two distinct root complexes is not supported by the standard
> set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
> of the latter specifically for this platform (and forget about the
> others).
>
> This also
On Thu, Oct 26, 2017 at 03:57:38PM +0100, Ard Biesheuvel wrote:
> On 26 October 2017 at 15:56, Leif Lindholm wrote:
> > On Wed, Oct 25, 2017 at 06:59:27PM +0100, Ard Biesheuvel wrote:
> >> Replace the common MemoryInitPeiLib implementation with one that does
> >> not remove the primary FV from the
On Wed, Oct 25, 2017 at 06:59:28PM +0100, Ard Biesheuvel wrote:
> This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
> code provided by Socionext. It can boot into the UiApp menu screen
> or the UEFI Shell, but lacks support for any peripherals.
>
> Contributed-under: TianoCore Con
On 26 October 2017 at 15:56, Leif Lindholm wrote:
> On Wed, Oct 25, 2017 at 06:59:27PM +0100, Ard Biesheuvel wrote:
>> Replace the common MemoryInitPeiLib implementation with one that does
>> not remove the primary FV from the memory map. This is a waste of
>> memory and TLB entries, given that th
On Wed, Oct 25, 2017 at 06:59:27PM +0100, Ard Biesheuvel wrote:
> Replace the common MemoryInitPeiLib implementation with one that does
> not remove the primary FV from the memory map. This is a waste of
> memory and TLB entries, given that the OS can no longer use a 1 GB
> block mapping to map thi
Could you please provide your comments.
Thank You,
Karunakar
From: Karunakar P
Sent: Monday, October 23, 2017 8:38 PM
To: 'edk2-devel@lists.01.org'
Cc: Wu, Jiaxin; 'Fu, Siyuan'; Ye, Ting
Subject: RE: Adding VLAN changing Boot order to default
Hello All,
Boot order is changing to default if we a
On Thu, Oct 26, 2017 at 04:29:39PM +0200, Marcin Wojtas wrote:
> 2017-10-26 16:02 GMT+02:00 Leif Lindholm :
> >> > Why is Capability.BaseClkFreq the wrong frequency to use?
> >>
> >> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz.
> >> An alternative would be change this gene
Hi Jiaxin,
It can resolve the issue.
Thanks,
Karunakar
-Original Message-
From: Jiaxin Wu [mailto:jiaxin...@intel.com]
Sent: Thursday, October 26, 2017 1:57 PM
To: edk2-devel@lists.01.org
Cc: Karunakar P; Ye Ting; Fu Siyuan; Wu Jiaxin
Subject: [Patch] NetworkPkg/IScsiDxe: Clear the old
On Wed, Oct 25, 2017 at 06:59:26PM +0100, Ard Biesheuvel wrote:
> This adds the NetSecDxe driver provided by Socionext, but reworked
> extensively to improve compliance with the SimpleNetworkProtocol API,
> and to avoid uncached allocations for streaming DMA.
So, I see all of my important style co
On Wed, Oct 25, 2017 at 06:59:25PM +0100, Ard Biesheuvel wrote:
> Add a package .DEC description for SynQuacer with an [Includes]
> section, and add header files containing descriptions of the
> platform's memory map and PCIe configuration. No code yet.
>
> Contributed-under: TianoCore Contributio
2017-10-26 16:02 GMT+02:00 Leif Lindholm :
> On Thu, Oct 26, 2017 at 03:54:41PM +0200, Marcin Wojtas wrote:
>> 2017-10-26 15:46 GMT+02:00 Leif Lindholm :
>> > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote:
>> >> Incorrectly the clock divisor was calculated relatively
>> >> to 255MHz
On 26 October 2017 at 15:09, Laszlo Ersek wrote:
> Ard, Star,
>
> (CC Igor)
>
> On 10/26/17 07:08, Zeng, Star wrote:
>> Good point.
>>
>> Could we find out what change causes the performance regression? Bus Master
>> disable / Memory Space disable / IO Space disable?
>> How about to only disable
Ard, Star,
(CC Igor)
On 10/26/17 07:08, Zeng, Star wrote:
> Good point.
>
> Could we find out what change causes the performance regression? Bus Master
> disable / Memory Space disable / IO Space disable?
> How about to only disable Bus Master in the exit boot service event
> notification? It
On Thu, Oct 26, 2017 at 03:54:41PM +0200, Marcin Wojtas wrote:
> 2017-10-26 15:46 GMT+02:00 Leif Lindholm :
> > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote:
> >> Incorrectly the clock divisor was calculated relatively
> >> to 255MHz instead of actual 400MHz.
> >
> > This describes
2017-10-26 15:55 GMT+02:00 Ard Biesheuvel :
> On 26 October 2017 at 14:54, Marcin Wojtas wrote:
>> 2017-10-26 15:46 GMT+02:00 Leif Lindholm :
>>> On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote:
Incorrectly the clock divisor was calculated relatively
to 255MHz instead of ac
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