[edk2] [PATCH V2 2/2] IntelSiliconPkg/VtdPeiSample: Add premem support.

Before memory is ready, this sample produces one VTd engine. After memory and silicon is initialized, this sample produces both IGD VTd engine and all-rest VTd engine by reinstall the FV_INFO_PPI. This update is to demonstrate how to support pre-mem VTd usage. Cc: Star Zeng

[edk2] [PATCH V2 0/2] IntelSiliconPkg: Add Pre-Memory DMA protection in PEI

V2 = Minor enhancement: Replace IsDmaProtectionEnabled() by GetDmaProtectionEnabledEngineMask(), for better code management. V1 = This series patch adds Pre-Memory DMA protection in PEI. The purpose is to make sure when the system memory is

[edk2] [PATCH V2 1/2] IntelSiliconPkg/VtdPmrPei: Add premem support.

Remove memory discovered dependency to support both premem VTD_INFO_PPI and postmem VTD_INFO_PPI. If VTD_INFO_PPI is installed before memory is ready, this driver protects all memory region. If VTD_INFO_PPI is installed or reinstalled after memory is ready, this driver allocates DMA buffer and

[edk2] [PATCH 2/4] Drivers/SataSiI3132Dxe: Allow 64-bit DMA transfer

Set a PCI IO attribute allowing 64-bit DMA transfer. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov --- EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[edk2] [PATCH 4/4] Drivers/SataSiI3132Dxe: Fixed startup and shutdown procedures

Corrected memory allocation during startup. Added driver stop procedure and exit boot event handler. Added driver memory and protocols cleanup procedures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov ---

[edk2] [PATCH 0/4] SataSiI3132Dxe fixes

This set of patches fixes an issue with 64-bit DMA and implements the missing exit boot event and driver stop functionality including memory/protocols cleanup procedure. Daniil Egranov (4): Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations Drivers/SataSiI3132Dxe: Allow 64-bit DMA

[edk2] [PATCH 3/4] Drivers/SataSiI3132Dxe: Enable multi-controller support

Saved controller specific data into the driver's information structure. Removed global variable indicating the driver's status and added check for the driver's status based on the available protocol. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov

[edk2] [PATCH 1/4] Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations

The ATA pass through read should use PCI IO bus master write operation and ATA pass through write should use PCI IO bus master read operation as the read and write operations executed from the bus master's point of view. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by:

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

I think it does exist. If I use IOMMU to prevent all DMA transaction, I have seen XHCI driver and AHCI driver reporting error. Thank you Yao Jiewen > -Original Message- > From: Ni, Ruiyu > Sent: Friday, October 27, 2017 10:38 AM > To: Yao, Jiewen ; Laszlo Ersek

Re: [edk2] [Patch 0/2] Add check to avoid use NULL pointer

Reviewed-by: Hao Wu Best Regards, Hao Wu > -Original Message- > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jiaxin > Wu > Sent: Friday, October 27, 2017 10:24 AM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A; Ye, Ting; Fu, Siyuan; Wu,

Re: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: disable only BM-DMA at ExitBootServices()

Reviewed-by: Star Zeng after the minor typo " isse " is fixed to " issue ". Thanks, Star -Original Message- From: Laszlo Ersek [mailto:ler...@redhat.com] Sent: Thursday, October 26, 2017 11:48 PM To: edk2-devel-01 Cc: Aleksei Kovura

Re: [edk2] Xen Console input very slow in recent UEFI

Hi, The TimeOut handling in SerialRead() in SerialDxe(MdeModulepkg), IsaSerialRead() in IsaSerialDxe(IntelFrameworkModulePkg) and SerialRead() in PciSioSerialDxe(MdeModulePkg) are consistent, and we did not see this kind of "slow down" before. After some investigation, I found it is related

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

I also doubt such device driver exists. Thanks/Ray > -Original Message- > From: Yao, Jiewen > Sent: Friday, October 27, 2017 9:47 AM > To: Ni, Ruiyu ; Laszlo Ersek ; Zeng, > Star ; edk2-devel@lists.01.org > Cc: Ard Biesheuvel

[edk2] [Patch 2/2] NetworkPkg/IScsiDxe: Add check to avoid use NULL pointer

Cc: Wu Hao A Cc: Ye Ting Cc: Fu Siyuan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Wu Jiaxin --- NetworkPkg/IScsiDxe/IScsiConfig.c | 4 1 file changed, 4 insertions(+) diff --git

[edk2] [Patch 1/2] NetworkPkg/HttpBootDxe: Add check to avoid use NULL pointer

Cc: Wu Hao A Cc: Ye Ting Cc: Fu Siyuan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Wu Jiaxin --- NetworkPkg/HttpBootDxe/HttpBootDxe.c | 50 +++- 1 file

[edk2] [Patch 0/2] Add check to avoid use NULL pointer

Cc: Wu Hao A Cc: Ye Ting Cc: Fu Siyuan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Wu Jiaxin Jiaxin Wu (2): NetworkPkg/HttpBootDxe: Add check to avoid use NULL pointer

Re: [edk2] [PATCH] MdePkg/Include: fix incorrect structure definition

Chris: Ni, Ruiyu has sent this patch yesterday. >-Original Message- >From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of >Chris Ruffin >Sent: Friday, October 27, 2017 9:04 AM >To: edk2-devel@lists.01.org >Subject: [edk2] [PATCH] MdePkg/Include: fix incorrect

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

I think the error might be PCI device specific. BTW: We already have bugzillar on that https://bugzilla.tianocore.org/show_bug.cgi?id=739 It has been validated by Microsoft. We can validate more device cards to see if there is any issue. Thank you Yao Jiewen > -Original Message- >

Re: [edk2] [PATCH v3 0/6] Implement heap guard feature

Hi Laszlo, > -Original Message- > From: Laszlo Ersek [mailto:ler...@redhat.com] > Sent: Thursday, October 26, 2017 9:27 PM > To: Wang, Jian J > Cc: Yao, Jiewen ; edk2-devel@lists.01.org; Kinney, > Michael D ;

Re: [edk2] [Patch] UefiCpuPkg/MpInitLib: Keep compatible with former solution.

Laszlo, Update both and pushed the change at 86121874. Thanks, Eric > -Original Message- > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of > Laszlo Ersek > Sent: Thursday, October 26, 2017 4:26 PM > To: Dong, Eric ; edk2-devel@lists.01.org >

Re: [edk2] [Patch 2/2] UefiCpuPkg/MpInitLib: Enhance waiting for AP initialization logic.

Brian, > -Original Message- > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of > Brian J. Johnson > Sent: Friday, October 27, 2017 4:48 AM > To: Dong, Eric ; Laszlo Ersek ; > edk2-devel@lists.01.org > Cc: Ni, Ruiyu

Re: [edk2] Adding VLAN changing Boot order to default

Hi Karunakar, I guess you configure the VLAN on the NIC that PXE boot option selected. If so, that's the expect behavior since the VLAN callback function will destroy the previous NIC info including the MNP service data, then PXE driver binding stop/start will be called again to update the

Re: [edk2] [PATCH] UefiCpuPkg/CpuDxe: Fix multiple entries of RT_CODE in memory map

Hi Laszlo, > -Original Message- > From: Laszlo Ersek [mailto:ler...@redhat.com] > Sent: Thursday, October 26, 2017 6:08 PM > To: Wang, Jian J ; edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Dong, Eric > Subject: Re: [edk2]

[edk2] [platforms: PATCH v2 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values

Changing controller's FIFO default values is not necessary and possibly can cause instabilities, when using some devices. Disable the modification and rely on initial settings. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by:

[edk2] [platforms: PATCH v2 03/10] Marvell/Drivers: MvI2cDxe: Reduce bus occupation time

From: David Greeson During each transaction start, clearing the I2C_CONTROL_FLAG was surrounded by 3 uncoditional stalls. This was not necessary, so replace them with one busy-wait loop, whose polling count could be also safely reduced. Above improvements result in faster

[edk2] [platforms: PATCH v2 00/10] Armada 7k/8k - misc improvements pt.2

Hi, I present you a second version of the patchset with post review fixes and improvements. 9/10 patch was completely changed - the diff is bigger, but such generic clock handling gives some chances to benefit if we want to merge Xenon support with original EDK2 SdMmc driver in future. More

[edk2] [platforms: PATCH v2 05/10] Marvell/Library: MppLib: Disable the stack protector

From: Ard Biesheuvel MppLib may be used very early (in SEC), at which point stack protection measures are more likely to cause harm than help, given that not even the UART has been configured to the point where we can complain usefully. So just disable it.

[edk2] [platforms: PATCH v2 07/10] Marvell/Drivers: Pp2Dxe: Change settings for the always-up link

Currently initial forcing link status happened for all ports, not only marked as 'always-up'. Although this didn't actually matter for the MAC settings, because MAC is automatically updated with PHY HW polling feature of the controller, perform mv_gop110_fl_cfg only when the appropriate flag is

[edk2] [platforms: PATCH v2 02/10] Marvell/Drivers: MvI2cDxe: Fix returning status in MvI2cStartRequest

In MvI2cStartRequest the status was assigned to the variable without dereferencing a pointer. Fix it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 2 +- 1 file changed, 1

[edk2] [platforms: PATCH v2 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting

This patch fixes incorrect settings for UHS mode in SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which the latter was missing. This field should be set to: 0x4 for DDR52 0x2 for SDR50 0x1 for SDR25 0x0 for others. This way EmmcSwitchToHighSpeed function is on par with Linux

[edk2] [platforms: PATCH v2 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail

From: David Greeson Although the I2C transaction routines were prepared to return their status, they were never used. This could cause bus lock-up e.g. in case of failing to send a slave address, the data transfer was attempted to be continued anyway. This patch fixes faulty

[edk2] [platforms: PATCH v2 09/10] Marvell/Drivers: XenonDxe: Allow overriding base clock frequency

Some SdMmc host controllers are run by clocks with different frequency than it is reflected in Capabilities Register 1. Because the bitfield is only 8 bits wide, a maximum value that could be obtained from hardware is 255(MHz). In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq

[edk2] [platforms: PATCH v2 06/10] Marvell/Library: MppLib: Take 0xFF placeholders into account

From: Ard Biesheuvel The MppSel definition PCDs contain 0xFF placeholders for values that should be left untouched. MppLib needs to be taught how to take those into account. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel

[edk2] [platforms: PATCH v2 04/10] Marvell/Library: MppLib: Prevent overwriting PCD values

From: Joe Zhou After enabling dynamic PCDs, it is possible to reconfigure MPP during platform initialization. It occurred that due to a faulty way of passing temporary values, information obtained from PCDs was overwritten. This patch fixes the issue, which on the occasion

[edk2] [PATCH] MdePkg/Include: fix incorrect structure definition

Fix incorrect structure definitions for PCI_REG_PCIE_SLOT_CONTROL in PciExpress21.h. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin --- MdePkg/Include/IndustryStandard/PciExpress21.h | 24 1 file changed, 12

Re: [edk2] [Patch] NetworkPkg/IScsiDxe: Clear the old IFR TargetIp to avoid sharing it with other attempts.

Reviewed-by: Fu Siyuan > -Original Message- > From: Wu, Jiaxin > Sent: Thursday, October 26, 2017 4:27 PM > To: edk2-devel@lists.01.org > Cc: Karunakar P ; Ye, Ting ; > Fu, Siyuan ; Wu, Jiaxin

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

Jiewen, If the BME bit is cleared in Command register, but a device driver uses DMA to transfer data, what kind of error will be seen by SW? -Original Message- From: Yao, Jiewen Sent: Friday, October 27, 2017 8:34 AM To: Laszlo Ersek ; Zeng, Star ;

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

Good Info. I think a correct implementation should not use busy wait. It should add error handling to check if there is hardware error during that. > - busy wait (poll) unil the transfer is complete, The process of busy wait should be something like below: while(TRUE) { if (error) {

Re: [edk2] [PATCH edk2-platforms v2 08/23] Platform/SynQuacerEvalBoard: add PCI support

On Thu, Oct 26, 2017 at 04:41:07PM +0100, Ard Biesheuvel wrote: > > - Is there a good reason for leaving out Uhci/Ehci? > > No not really, other than the fact that nobody is every likely to use > it (although I suppose you could put a UHCI PCI card into a PCIe to > PCI bridge) Well, more likely

Re: [edk2] [PATCH edk2-platforms v2 22/23] Platform/Socionext: add support for Socionext Developer Box rev 0.1

On Wed, Oct 25, 2017 at 06:59:46PM +0100, Ard Biesheuvel wrote: > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Platform/Socionext/DeveloperBox/DeveloperBox.dsc >| 624

Re: [edk2] [PATCH edk2-platforms v2 23/23] Platform/DeveloperBox: add ConsolePrefDxe driver

On Wed, Oct 25, 2017 at 06:59:47PM +0100, Ard Biesheuvel wrote: > In order to improve the 'out of the box' experience when booting > this system with a monitor and keyboard attached, include the serial > console preference driver that prevents the installer GUI to only > appear on the serial port

Re: [edk2] [PATCH edk2-platforms v2 21/23] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards

On Wed, Oct 25, 2017 at 06:59:45PM +0100, Ard Biesheuvel wrote: > Implement workaround suggested by Socionext to get legacy endpoints with > 32-bit BARs working. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel This was the

Re: [edk2] [PATCH edk2-platforms v2 20/23] Silicon/SynQuacer/AcpiTables: hide PCI domain #0

On Wed, Oct 25, 2017 at 06:59:44PM +0100, Ard Biesheuvel wrote: > The ACPI hack to support the broken Synopsys IP only works for endpoints, > not for non-trivial topologies involving switches. Given that the Linaro > developer board has a switch soldered on, there is really no way to do > anything

Re: [edk2] [PATCH edk2-platforms v2 19/23] Platform/SynQuacerEvalBoard: add signed capsule update support

On Wed, Oct 25, 2017 at 06:59:43PM +0100, Ard Biesheuvel wrote: > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >| 20

Re: [edk2] [PATCH edk2-platforms v2 18/23] Socionext/SynQuacerEvalBoard: switch to execute in place

On Wed, Oct 25, 2017 at 06:59:42PM +0100, Ard Biesheuvel wrote: > Now that we switched to PrePeiCore, we can execute the firmware image > in place, using a stack and temporary heap in non-secure SRAM. This > allows us to query the secure firmware for the size and placement of > DRAM, and also

Re: [edk2] [PATCH edk2-platforms v2 17/23] Socionext/SynQuacerEvalBoard: wire up basic capsule support

On Wed, Oct 25, 2017 at 06:59:41PM +0100, Ard Biesheuvel wrote: > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- >

Re: [edk2] [PATCH edk2-platforms v2 16/23] SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support

On Wed, Oct 25, 2017 at 06:59:40PM +0100, Ard Biesheuvel wrote: > Add support for dealing with capsules left in memory by the OS before > reboot. This needs to be done early, before the memory is reused, which > is why the initial handling must reside here. > > Contributed-under: TianoCore

Re: [edk2] [PATCH edk2-platforms v2 15/23] Silicon/SynQuacer: implement PlatformFlashAccessLib

On Wed, Oct 25, 2017 at 06:59:39PM +0100, Ard Biesheuvel wrote: > In order to support capsule update, implement PlatformFlashAccessLib that > exposes write access to the UEFI NOR partition. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel

Re: [edk2] [PATCH edk2-platforms v2 13/23] Silicon/Socionext: add driver for SPI NOR flash

On Wed, Oct 25, 2017 at 06:59:37PM +0100, Ard Biesheuvel wrote: > From: Pipat Methavanitpong > > This imports the driver sources provided by Socionext for the FIP006 > SPI NOR flash device found on SynQuacer SoCs. It has been slightly > tweaked to bring it up

Re: [edk2] [Patch 2/2] UefiCpuPkg/MpInitLib: Enhance waiting for AP initialization logic.

On 10/25/2017 08:13 PM, Dong, Eric wrote: Laszlo, -Original Message- From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Laszlo Ersek Sent: Wednesday, October 25, 2017 11:08 PM To: Dong, Eric ; edk2-devel@lists.01.org Cc: Ni, Ruiyu

Re: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: disable only BM-DMA at ExitBootServices()

On Thu, Oct 26, 2017 at 9:48 AM, Laszlo Ersek wrote: > Clearing I/O port decoding in the PCI command register at > ExitBootServices() breaks IDE boot in Windows, on QEMU's "pc" (i440fx) > machine type. (AHCI boot on "q35" is unaffected.) Windows seems repeatedly > stuck,

Re: [edk2] Xen Console input very slow in recent UEFI

Hi Laszlo, Thank you for your help. On 26/10/17 16:20, Laszlo Ersek wrote: On 10/26/17 17:13, Laszlo Ersek wrote: Hello Julien, On 10/26/17 13:05, Julien Grall wrote: Hi all, I was doing more testing of UEFI in Xen guests and noticed some slow down when using the shell. The characters are

Re: [edk2] [PATCH edk2-platforms v2 11/23] Silicon/SynQuacer: add device tree support for eval board

On Wed, Oct 25, 2017 at 06:59:35PM +0100, Ard Biesheuvel wrote: > Add a device tree description of the SynQuacer SoC, and expose it for > the SynQuacerEvalBoard platforms. This includes the menu option in the > UEFI boot menu to switch between ACPI and DT. > > Contributed-under: TianoCore

Re: [edk2] [PATCH edk2-platforms v2 10/23] Silicon/SynQuacer: add ACPI support

On Wed, Oct 25, 2017 at 06:59:34PM +0100, Ard Biesheuvel wrote: > Enable ACPI support for the SynQuacerEvalBoard platform: add descriptions > of the CPUs, the GIC, the serial port, the timers and the PCIe RCs, > including the MSI routing via the GICv3 ITS. > > Note that PCIe support is limited to

Re: [edk2] [PATCH v2 2/3] ArmPkg/Drivers: Add EFI_MM_COMMUNICATION_PROTOCOL DXE driver.

On Thu, 2017-10-26 at 11:13 +0100, Achin Gupta wrote: > Hi Supreeth, > > some CIL, > > On Wed, Oct 25, 2017 at 05:32:57PM +0100, Supreeth Venkatesh wrote: > > > > PI v1.5 Specification Volume 4 defines Management Mode Core > > Interface > > and defines EFI_MM_COMMUNICATION_PROTOCOL. This

[edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: disable only BM-DMA at ExitBootServices()

Clearing I/O port decoding in the PCI command register at ExitBootServices() breaks IDE boot in Windows, on QEMU's "pc" (i440fx) machine type. (AHCI boot on "q35" is unaffected.) Windows seems repeatedly stuck, apparently waiting for a timeout of sorts. This is arguably a Windows bug; a native OS

Re: [edk2] [PATCH edk2-platforms v2 08/23] Platform/SynQuacerEvalBoard: add PCI support

On 26 October 2017 at 16:38, Leif Lindholm wrote: > On Wed, Oct 25, 2017 at 06:59:32PM +0100, Ard Biesheuvel wrote: >> Wire up the various drivers and libraries for the SynQuacerEvalBoard >> platform. Also enable the usual PCI suspects: XHCI, SATA and NVME, >> and the

Re: [edk2] [PATCH edk2-platforms v2 09/23] Platform/SynQuacerEvalBoard: add NETSEC driver

On Wed, Oct 25, 2017 at 06:59:33PM +0100, Ard Biesheuvel wrote: > Add the NETSEC driver to the SynQuacerEvalBoard platform. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm

Re: [edk2] [PATCH edk2-platforms v2 08/23] Platform/SynQuacerEvalBoard: add PCI support

On Wed, Oct 25, 2017 at 06:59:32PM +0100, Ard Biesheuvel wrote: > Wire up the various drivers and libraries for the SynQuacerEvalBoard > platform. Also enable the usual PCI suspects: XHCI, SATA and NVME, > and the various bus, partition and file system drivers that we need > to make use of PCIe

Re: [edk2] Xen Console input very slow in recent UEFI

On 10/26/17 17:13, Laszlo Ersek wrote: > Hello Julien, > > On 10/26/17 13:05, Julien Grall wrote: >> Hi all, >> >> I was doing more testing of UEFI in Xen guests and noticed some slow >> down when using the shell. The characters are only echoed after a second >> or two that is a bit annoying. >>

Re: [edk2] [PATCH v2 2/3] ArmPkg/Drivers: Add EFI_MM_COMMUNICATION_PROTOCOL DXE driver.

On Thu, 2017-10-26 at 05:05 +, Udit Kumar wrote: > Hi  > > > > > +  Status = gBS->AllocatePages (AllocateAddress, > > +   EfiRuntimeServicesData, > > +   EFI_SIZE_TO_PAGES > > (mNsCommBuffMemRegion.Length), > > + 

Re: [edk2] [PATCH edk2-platforms v2 04/23] Platform: add support for Socionext SynQuacer eval board

On 26 October 2017 at 16:02, Leif Lindholm wrote: > On Wed, Oct 25, 2017 at 06:59:28PM +0100, Ard Biesheuvel wrote: >> This is a barebones port based on the .DSC/.FDF and ArmPlatformLib >> code provided by Socionext. It can boot into the UiApp menu screen >> or the UEFI

Re: [edk2] [PATCH edk2-platforms v2 07/23] Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL

On Wed, Oct 25, 2017 at 06:59:31PM +0100, Ard Biesheuvel wrote: > The SynQuacer SOC has two separate PCIe RCs, which means there is > no single value for the translation offset between I/O port accesses > and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL > that takes the

Re: [edk2] Xen Console input very slow in recent UEFI

Hello Julien, On 10/26/17 13:05, Julien Grall wrote: > Hi all, > > I was doing more testing of UEFI in Xen guests and noticed some slow > down when using the shell. The characters are only echoed after a second > or two that is a bit annoying. > > The change that introduced this issue is

Re: [edk2] [PATCH edk2-platforms v2 06/23] Silicon/SynQuacer: implement PciHostBridgeLib support

On 26 October 2017 at 16:10, Leif Lindholm wrote: > On Wed, Oct 25, 2017 at 06:59:30PM +0100, Ard Biesheuvel wrote: >> Implement the glue library that exposes the PCIe root complexes to >> the generic PCI host bridge driver. Since that driver is the first >> one to

Re: [edk2] [PATCH edk2-platforms v2 06/23] Silicon/SynQuacer: implement PciHostBridgeLib support

On Wed, Oct 25, 2017 at 06:59:30PM +0100, Ard Biesheuvel wrote: > Implement the glue library that exposes the PCIe root complexes to > the generic PCI host bridge driver. Since that driver is the first > one to access the PCI config space, put the low level init code for > the RCs into this

Re: [edk2] [PATCH] BaseTools/tools_def: suppress GCC predefined macros in DTB compilation

On 10/26/17 13:34, Ard Biesheuvel wrote: > On 26 October 2017 at 12:33, Leif Lindholm wrote: >> On Thu, Oct 26, 2017 at 12:11:16PM +0100, Ard Biesheuvel wrote: >>> On 26 October 2017 at 12:09, Laszlo Ersek wrote: On 10/26/17 12:12, Ard Biesheuvel

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

2017-10-26 16:52 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 04:29:39PM +0200, Marcin Wojtas wrote: >> 2017-10-26 16:02 GMT+02:00 Leif Lindholm : >> >> > Why is Capability.BaseClkFreq the wrong frequency to use? >> >> >> >> The

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

On 10/26/17 15:36, Yao, Jiewen wrote: > Hi Laszlo > I have discussed this with Mike Kinney offline and some Microsoft engineers. > > We believe the impact of BME disable is different with the impact of SEV. > > For SEV, if a DMA buffer is in transition when SEV bit change, the DMA will > still

Re: [edk2] [PATCH edk2-platforms v2 05/23] Silicon/SynQuacer: implement PciSegmentLib to support dual RCs

On Wed, Oct 25, 2017 at 06:59:29PM +0100, Ard Biesheuvel wrote: > Having two distinct root complexes is not supported by the standard > set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one > of the latter specifically for this platform (and forget about the > others). > > This also

Re: [edk2] [PATCH edk2-platforms v2 03/23] Silicon/SynQuacer: add MemoryInitPeiLib implementation

On Thu, Oct 26, 2017 at 03:57:38PM +0100, Ard Biesheuvel wrote: > On 26 October 2017 at 15:56, Leif Lindholm wrote: > > On Wed, Oct 25, 2017 at 06:59:27PM +0100, Ard Biesheuvel wrote: > >> Replace the common MemoryInitPeiLib implementation with one that does > >> not

Re: [edk2] [PATCH edk2-platforms v2 04/23] Platform: add support for Socionext SynQuacer eval board

On Wed, Oct 25, 2017 at 06:59:28PM +0100, Ard Biesheuvel wrote: > This is a barebones port based on the .DSC/.FDF and ArmPlatformLib > code provided by Socionext. It can boot into the UiApp menu screen > or the UEFI Shell, but lacks support for any peripherals. > > Contributed-under: TianoCore

Re: [edk2] [PATCH edk2-platforms v2 03/23] Silicon/SynQuacer: add MemoryInitPeiLib implementation

On 26 October 2017 at 15:56, Leif Lindholm wrote: > On Wed, Oct 25, 2017 at 06:59:27PM +0100, Ard Biesheuvel wrote: >> Replace the common MemoryInitPeiLib implementation with one that does >> not remove the primary FV from the memory map. This is a waste of >> memory and

Re: [edk2] [PATCH edk2-platforms v2 03/23] Silicon/SynQuacer: add MemoryInitPeiLib implementation

On Wed, Oct 25, 2017 at 06:59:27PM +0100, Ard Biesheuvel wrote: > Replace the common MemoryInitPeiLib implementation with one that does > not remove the primary FV from the memory map. This is a waste of > memory and TLB entries, given that the OS can no longer use a 1 GB > block mapping to map

Re: [edk2] Adding VLAN changing Boot order to default

Could you please provide your comments. Thank You, Karunakar From: Karunakar P Sent: Monday, October 23, 2017 8:38 PM To: 'edk2-devel@lists.01.org' Cc: Wu, Jiaxin; 'Fu, Siyuan'; Ye, Ting Subject: RE: Adding VLAN changing Boot order to default Hello All, Boot order is changing to default if we

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

On Thu, Oct 26, 2017 at 04:29:39PM +0200, Marcin Wojtas wrote: > 2017-10-26 16:02 GMT+02:00 Leif Lindholm : > >> > Why is Capability.BaseClkFreq the wrong frequency to use? > >> > >> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz. > >> An

Re: [edk2] [Patch] NetworkPkg/IScsiDxe: Clear the old IFR TargetIp to avoid sharing it with other attempts.

Hi Jiaxin, It can resolve the issue. Thanks, Karunakar -Original Message- From: Jiaxin Wu [mailto:jiaxin...@intel.com] Sent: Thursday, October 26, 2017 1:57 PM To: edk2-devel@lists.01.org Cc: Karunakar P; Ye Ting; Fu Siyuan; Wu Jiaxin Subject: [Patch] NetworkPkg/IScsiDxe: Clear the old

Re: [edk2] [PATCH edk2-platforms v2 02/23] Silicon/Socionext: add driver for NETSEC network controller

On Wed, Oct 25, 2017 at 06:59:26PM +0100, Ard Biesheuvel wrote: > This adds the NetSecDxe driver provided by Socionext, but reworked > extensively to improve compliance with the SimpleNetworkProtocol API, > and to avoid uncached allocations for streaming DMA. So, I see all of my important style

Re: [edk2] [PATCH edk2-platforms v2 01/23] Silicon/SynQuacer: add package with platform headers

On Wed, Oct 25, 2017 at 06:59:25PM +0100, Ard Biesheuvel wrote: > Add a package .DEC description for SynQuacer with an [Includes] > section, and add header files containing descriptions of the > platform's memory map and PCIe configuration. No code yet. > > Contributed-under: TianoCore

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

2017-10-26 16:02 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:54:41PM +0200, Marcin Wojtas wrote: >> 2017-10-26 15:46 GMT+02:00 Leif Lindholm : >> > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: >> >> Incorrectly the

Re: [edk2] [PATCH 03/10] MdeModulePkg/AtaAtapiPassThru: disable the device at ExitBootServices()

On 26 October 2017 at 15:09, Laszlo Ersek wrote: > Ard, Star, > > (CC Igor) > > On 10/26/17 07:08, Zeng, Star wrote: >> Good point. >> >> Could we find out what change causes the performance regression? Bus Master >> disable / Memory Space disable / IO Space disable? >> How

Re: [edk2] [PATCH 03/10] MdeModulePkg/AtaAtapiPassThru: disable the device at ExitBootServices()

Ard, Star, (CC Igor) On 10/26/17 07:08, Zeng, Star wrote: > Good point. > > Could we find out what change causes the performance regression? Bus Master > disable / Memory Space disable / IO Space disable? > How about to only disable Bus Master in the exit boot service event > notification? It

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

On Thu, Oct 26, 2017 at 03:54:41PM +0200, Marcin Wojtas wrote: > 2017-10-26 15:46 GMT+02:00 Leif Lindholm : > > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: > >> Incorrectly the clock divisor was calculated relatively > >> to 255MHz instead of actual

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

2017-10-26 15:55 GMT+02:00 Ard Biesheuvel : > On 26 October 2017 at 14:54, Marcin Wojtas wrote: >> 2017-10-26 15:46 GMT+02:00 Leif Lindholm : >>> On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: Incorrectly

Re: [edk2] [platforms: PATCH 05/10] Marvell/Library: MppLib: Disable the stack protector

On Thu, Oct 26, 2017 at 02:29:02PM +0100, Ard Biesheuvel wrote: > On 26 October 2017 at 14:26, Leif Lindholm wrote: > > On Thu, Oct 26, 2017 at 03:19:32AM +0200, Marcin Wojtas wrote: > >> From: Ard Biesheuvel > >> > >> MppLib may be used very

Re: [edk2] [platforms: PATCH 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail

2017-10-26 15:54 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:19:36PM +0200, Marcin Wojtas wrote: >> Hi Leif, >> >> 2017-10-26 14:51 GMT+02:00 Leif Lindholm : >> > On Thu, Oct 26, 2017 at 03:19:28AM +0200, Marcin Wojtas wrote: >> >>

Re: [edk2] [platforms: PATCH 02/10] Marvell/Drivers: MvI2cDxe: Fix returning status in MvI2cStartRequest

On Thu, Oct 26, 2017 at 03:22:32PM +0200, Marcin Wojtas wrote: > 2017-10-26 15:11 GMT+02:00 Leif Lindholm : > > On Thu, Oct 26, 2017 at 03:19:29AM +0200, Marcin Wojtas wrote: > >> In MvI2cStartRequest the status was assigned to the variable > >> without dereferencing a

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

2017-10-26 15:46 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: >> Incorrectly the clock divisor was calculated relatively >> to 255MHz instead of actual 400MHz. > > This describes the specific symptom, not the problem with the

Re: [edk2] [platforms: PATCH 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail

On Thu, Oct 26, 2017 at 03:19:36PM +0200, Marcin Wojtas wrote: > Hi Leif, > > 2017-10-26 14:51 GMT+02:00 Leif Lindholm : > > On Thu, Oct 26, 2017 at 03:19:28AM +0200, Marcin Wojtas wrote: > >> From: David Greeson > >> > >> Although the I2C

Re: [edk2] [platforms: PATCH 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values

On Thu, Oct 26, 2017 at 03:19:37AM +0200, Marcin Wojtas wrote: > Changing controller's FIFO default values is not necessary and > possibly can cause instabilities, when using some devices. > Disable the modification and rely on initial settings. > > Contributed-under: TianoCore Contribution

Re: [edk2] [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency

On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: > Incorrectly the clock divisor was calculated relatively > to 255MHz instead of actual 400MHz. This describes the specific symptom, not the problem with the existing code. > Fix this. > > Contributed-under: TianoCore Contribution

Re: [edk2] [platforms: PATCH 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting

On Thu, Oct 26, 2017 at 03:19:35AM +0200, Marcin Wojtas wrote: > This patch fixes incorrect settings for UHS mode in > SD_MMC_HC_HOST_CTRL2 register. This field should be set to > > 0x4 for DDR52 > 0x2 for SDR50 > 0x1 for SDR25 > 0x0 for others. > > This way EmmcSwitchToHighSpeed function is on

Re: [edk2] [platforms: PATCH 07/10] Marvell/Drivers: Pp2Dxe: Change settings for the always-up link

On Thu, Oct 26, 2017 at 03:19:34AM +0200, Marcin Wojtas wrote: > Currently initial forcing link status happened for all ports, not only > marked as 'always-up'. Although this didn't actually matter for the MAC > settings, because MAC is automatically updated with PHY HW polling > feature of the

Re: [edk2] [PATCH] IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.

Hi Laszlo I have discussed this with Mike Kinney offline and some Microsoft engineers. We believe the impact of BME disable is different with the impact of SEV. For SEV, if a DMA buffer is in transition when SEV bit change, the DMA will still be active, but the content is different. It will

Re: [edk2] [platforms: PATCH 06/10] Marvell/Library: MppLib: Take 0xFF placeholders into account

On Thu, Oct 26, 2017 at 03:19:33AM +0200, Marcin Wojtas wrote: > From: Ard Biesheuvel > > The MppSel definition PCDs contain 0xFF placeholders for values that > should be left untouched. MppLib needs to be taught how to take those > into account. > >

Re: [edk2] [platforms: PATCH 05/10] Marvell/Library: MppLib: Disable the stack protector

On 26 October 2017 at 14:26, Leif Lindholm wrote: > On Thu, Oct 26, 2017 at 03:19:32AM +0200, Marcin Wojtas wrote: >> From: Ard Biesheuvel >> >> MppLib may be used very early (in SEC), at which point stack protection >> measures are more

Re: [edk2] [platforms: PATCH 05/10] Marvell/Library: MppLib: Disable the stack protector

On Thu, Oct 26, 2017 at 03:19:32AM +0200, Marcin Wojtas wrote: > From: Ard Biesheuvel > > MppLib may be used very early (in SEC), at which point stack protection > measures are more likely to cause harm than help, given that not even > the UART has been configured to

Re: [edk2] [PATCH v3 0/6] Implement heap guard feature

Hi Jian, On 10/26/17 09:38, Wang, Jian J wrote: > Thanks for the feedback. > >> -Original Message- >> From: Yao, Jiewen >> Sent: Thursday, October 26, 2017 2:49 PM >> To: Wang, Jian J ; edk2-devel@lists.01.org >> Cc: Kinney, Michael D ;

Re: [edk2] [platforms: PATCH 02/10] Marvell/Drivers: MvI2cDxe: Fix returning status in MvI2cStartRequest

2017-10-26 15:11 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:19:29AM +0200, Marcin Wojtas wrote: >> In MvI2cStartRequest the status was assigned to the variable >> without dereferencing a pointer. Fix it. >> >> Contributed-under: TianoCore Contribution

Re: [edk2] [platforms: PATCH 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail

Hi Leif, 2017-10-26 14:51 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:19:28AM +0200, Marcin Wojtas wrote: >> From: David Greeson >> >> Although the I2C transaction routines were prepared to >> return their status, they were never used.

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