hello:
I am a PhD student working on optimal instruction scheduling problems. I want
to
integrate my scheduler into the GCC. Can you tell me where to start? and
important links which can be helpful for the integration work?
Thanks
Abid Malik
This mail
Hi :
I am getting the following compilation error:
/tmp/ccIUvX3i.o(.gnu.linkonce.d._ZTV4ListIiE+0x8): undefined reference to
`List::Find(int const&)'
the declaration is:
virtual int Find (const Etype &X);
and the definition is:
template
int
List::Find (const Etype &X){
Node
hi, i am a beginner in this tech world. i want to learn 1/how to do programming
in c in unix or linux. i don't know anything about linux. where to start.
Never miss a thing. Make Yahoo your home page.
h
hi, i am a beginner in this tech world. i want to learn how to do programming
in c in unix or linux. i don't know anything about linux. where to start.
Looking for last minute shopping deals?
Find them
Dear all!
It posible to receive function with type defined logicaly as '...false, true, true,
""' in 'attribute_spec', to
a TARGET_EXPAND_BUILTIN or TARGET_RESOLVE_OVERLOADED_BUILTIN hooks?
Criteria function return type and arguments count/type must be ignored for
filtering.
--
Regards
Iva
On Jun 28, 2006, at 1:59 PM, [EMAIL PROTECTED] wrote:
I am a PhD student working on optimal instruction scheduling
problems. I want to
integrate my scheduler into the GCC. Can you tell me where to
start? and
important links which can be helpful for the integration work?
I'd start by downlo
[EMAIL PROTECTED] writes:
> I am getting the following compilation error:
>
> /tmp/ccIUvX3i.o(.gnu.linkonce.d._ZTV4ListIiE+0x8): undefined reference to
> `List::Find(int const&)'
Wrong mailing list. This sort of question should go to
[EMAIL PROTECTED] Thanks.
I don't know the answer to your q
On Mon, Feb 25, 2008 at 3:23 PM, Mag cool <[EMAIL PROTECTED]> wrote:
> hi, i am a beginner in this tech world. i want to learn 1/how to do
> programming in c in unix or linux. i don't know anything about linux. where
> to start.
>
Try this book: http://www.advancedlinuxprogramming.com/
>
>
>
i am try to star hit my password and just don't letme beginig and tele smoking
about certifiques and signaturas than i never see befor
On 12/04/09 10:00, jose manuel Herrera Magana wrote:
i am try to star hit my password and just don't letme beginig and tele smoking
about certifiques and signaturas than i never see befor
well first things first is gcc has nothing
todo with your password settings.
maybe resetting your accoun
I am trying to improve code generation for coremark to match a recent
improvement that was made in LLVM.
I added the following transformation to match.pd which attempts to
replace a branch with straight line code:
/* (cond (and (x , 0x1) == 0), y, (z ^ y) ) -> (-(and (x , 0x1)) & z ) ^
y */
Hi,
I have some question on gcc driver.
Whenever we invoke gcc, it'll pass some default options to the
compiler, assembler linker etc. But if i dont want to pass all these
default options but only some of them, what should i do?
For eg: gcc will pass the following option to cc1
/usr/libexec/gcc
On Thu, Oct 6, 2022 at 4:00 PM Michael Collison wrote:
>
> I am trying to improve code generation for coremark to match a recent
> improvement that was made in LLVM.
>
> I added the following transformation to match.pd which attempts to
> replace a branch with straight line code:
>
> /* (cond (and
On Thu, Oct 06, 2022 at 06:57:40PM -0400, Michael Collison wrote:
> I am trying to improve code generation for coremark to match a recent
> improvement that was made in LLVM.
>
> I added the following transformation to match.pd which attempts to replace a
> branch with straight line code:
>
> /*
Hello GCC team,
Greetings...
I am new user of Linux. I have RHEL 6.0 installed and want to run C++
on my system but I do not know how.
Please help me or let me know where to contact.
--
Thanks & Regards,
Kumar Aditya
+919015142426
Hello,
I'm looking for advice on how to debug and fix PR50906:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50906
The basic summary is that GCC is generating bad unwinder information or
is incorrectly saving registers onto the stack on PowerPC e500v2. Any
ordinary function call+return works fin
Vikram KS wrote:
Hi,
I have some question on gcc driver.
You really should give more context. Are you doing cross-compilation?
Are you patching the GCC sources? Why do you want to generate a *.sl
file? What are your host & target systems?
Whenever we invoke gcc, it'll pass some default opt
On Thu, Jul 30, 2009 at 8:14 PM, Basile STARYNKEVITCH
wrote:
>
> Vikram KS wrote:
>>
>> Hi,
>>
>> I have some question on gcc driver.
>
> You really should give more context. Are you doing cross-compilation? Are you
> patching the GCC sources? Why do you want to generate a *.sl file? What are
>
Vikram KS wrote:
So in the back-end there are driver options that will help me to
invoke the existing tool-chain through GCC driver. But the assembler
takes only .sl extensions. I tried to replace the .s extension with
.sl extension. But by default the cc1 will have some options passed
from the
Could someone provide a hint for me? I'm trying to put in "real"
prototypes for a builtin function where the arguments don't follow the
default promotion rules. Specifically, one of the arguments is a
reference type (like C++'s "int&"). However, I'm bumping into two
problems:
1. The compiler e
Hello
For my diploma thesis I have to implement a new back-end for GCC.
The microcontroller is based on an FPGA and was developed one year ago.
Only an Assembler is available and now my university lecturer wants an C
compiler too. I decided to use GCC in version 4.2.1 as basis for the new
comp
Hi,
I appreciate if someone can help me with my linking error:
In my "c++" options , i already have ' -L/usr/local/lib -lgnet-2.0'.
I get a number of '7: undefined reference to `gnet_conn_readline'' errors.
Can you please tell me why the linking fails? I have the 'gnet.h'
include in my .cpp an
The section "Pointer Bounds Checker builtins" in extend.texi is on my
list for being in need of copy-editing, but reading through the existing
text, I am quite confused. In several places it refers to turning the
Pointer Bounds Checker off, but how do you do that? I don't see any
documented c
Hey Kumar.
Just use your package manager.
in terminal:
yum search gcc-c++
Determine which version are available.
Then run:
yum install gcc-c++
You will need root access for the install step.
If you want another version RPM’s can be found here:
http://www.rpmfind.net/linux/rpm2h
On 11/04/15 04:08, Kumar Aditya wrote:
> I am new user of Linux. I have RHEL 6.0 installed and want to run C++
> on my system but I do not know how.
yum install gcc-c++.
Andrew.
On Mon, Oct 31, 2011 at 10:58:03AM -0500, Moffett, Kyle D wrote:
> I have not yet been able to figure out if it's a libgcc issue or an
> actual compiler issue.
It is a gcc bug. I've added a comment to the PR.
--
Alan Modra
Australia Development Lab, IBM
I need advise before I submit pathc to fix the test
gcc-torture/execute/vla-dealloc-1.c (attached below)
The test appears to be unsafe. The original fault was failure to
deallocate VLA on the jump - thus with the fault present the test would
appear to perform 1 million new allocation - and fa
I'm hoping I can get it to do what I want, if only I can get the MI to
treat the function definition given to it by the target as the one
true definition, and not just some advisory one.
DJ Delorie <[EMAIL PROTECTED]> writes:
> Is there a trick to this? I need this type of functionality because
> some builtins modify multiple values, so a simple return value is
> insufficient, plus this worked with older versions of gcc so our users
> are used to it syntax-wise.
I've never found
On Thu, 9 Aug 2007, DJ Delorie wrote:
> Could someone provide a hint for me? I'm trying to put in "real"
> prototypes for a builtin function where the arguments don't follow the
> default promotion rules. Specifically, one of the arguments is a
> reference type (like C++'s "int&"). However, I'm
> I don't know about using reference types, but there are several math
> builtins that "return" multiple values, the extra ones via pointer
> arguments. E.g. see frexp, lgamma_r, modf, remquo and/or sincos.
Like I said, I'm kinda locked into the syntax. People have been using
these builtins for
Michael_fogel writes:
> Hello
>
> For my diploma thesis I have to implement a new back-end for GCC.
> The microcontroller is based on an FPGA and was developed one year ago.
> Only an Assembler is available and now my university lecturer wants an C
> compiler too. I decided to use GCC in v
This list is for discussing GCC development, not deal with usage
problems. Please try asking [EMAIL PROTECTED]
Thanks,
Ben
Hi Team,
We are using GCC 4.8.3 for one of our legacy applications i.e: Automatch. after
database upgrade from 11/2 to 19.0.0, while recompiling one of our proc program
we are getting below error. Could you please help us to resolve below issue.
Please find full error trace in above attachment.
2015-02-20 3:48 GMT+03:00 Sandra Loosemore :
> The section "Pointer Bounds Checker builtins" in extend.texi is on my list
> for being in need of copy-editing, but reading through the existing text, I
> am quite confused. In several places it refers to turning the Pointer
> Bounds Checker off, but
On 02/20/2015 01:12 AM, Ilya Enkovich wrote:
2015-02-20 3:48 GMT+03:00 Sandra Loosemore :
The section "Pointer Bounds Checker builtins" in extend.texi is on my list
for being in need of copy-editing, but reading through the existing text, I
am quite confused. In several places it refers to turn
2015-02-20 19:39 GMT+03:00 Sandra Loosemore :
> On 02/20/2015 01:12 AM, Ilya Enkovich wrote:
>>
>> 2015-02-20 3:48 GMT+03:00 Sandra Loosemore :
>>>
>>> The section "Pointer Bounds Checker builtins" in extend.texi is on my
>>> list
>>> for being in need of copy-editing, but reading through the exist
On 02/24/2015 01:14 AM, Ilya Enkovich wrote:
2015-02-20 19:39 GMT+03:00 Sandra Loosemore :
On 02/20/2015 01:12 AM, Ilya Enkovich wrote:
2015-02-20 3:48 GMT+03:00 Sandra Loosemore :
The section "Pointer Bounds Checker builtins" in extend.texi is on my
list
for being in need of copy-editing, b
2015-02-24 19:47 GMT+03:00 Sandra Loosemore :
> On 02/24/2015 01:14 AM, Ilya Enkovich wrote:
>>
>> 2015-02-20 19:39 GMT+03:00 Sandra Loosemore :
>>>
>>> On 02/20/2015 01:12 AM, Ilya Enkovich wrote:
2015-02-20 3:48 GMT+03:00 Sandra Loosemore :
>
>
> The section "Pointer Bo
On 02/25/2015 12:56 AM, Ilya Enkovich wrote:
2015-02-24 19:47 GMT+03:00 Sandra Loosemore :
Poking around, I see that the -fcheck-pointer-bounds and various -fchkp-*
options are listed in c-family/c.opt, but they are not listed in the GCC
manual. The section on intrinsics is not enough, by itse
2015-02-25 19:16 GMT+03:00 Sandra Loosemore :
> On 02/25/2015 12:56 AM, Ilya Enkovich wrote:
>>
>> 2015-02-24 19:47 GMT+03:00 Sandra Loosemore :
>>>
>>>
>>> Poking around, I see that the -fcheck-pointer-bounds and various -fchkp-*
>>> options are listed in c-family/c.opt, but they are not listed in
On 02/25/2015 09:47 AM, Ilya Enkovich wrote:
2015-02-25 19:16 GMT+03:00 Sandra Loosemore :
On 02/25/2015 12:56 AM, Ilya Enkovich wrote:
2015-02-24 19:47 GMT+03:00 Sandra Loosemore :
Poking around, I see that the -fcheck-pointer-bounds and various -fchkp-*
options are listed in c-family/c.op
On Wed, 25 Feb 2015, Sandra Loosemore wrote:
>> Patch is a part of a series which is waiting for additional steering
>> committee approval due to copyright and a license.
> I don't imagine the documentation for *features already committed*
> needs to wait for steering committee approval; per the G
On Sun, 6 Dec 2009, Andrew Hutchinson wrote:
> The test appears to be unsafe. The original fault was failure to deallocate
> VLA on the jump - thus with the fault present the test would appear to perform
> 1 million new allocation - and fail presumably due to either execution time or
> run time er
Thanks
I am submitting patch to drop count to 10,000 for 16 bit int target.
Using 32 bit counter of 1 million takes a minute or so on simulator -
which is high.
The lower count is quick and only requires a (16bit) stack limit to be
lower than 10MB - which is pretty safe.
Andy
Joseph S. My
Please don't cross-post to several mailing lists, this belongs on the
gcc-help mailing list only.
On Wed, 1 Mar 2023, 06:33 Kondreddy, Vinay Kumar, <
vinaykumar.kondre...@staples.com> wrote:
> Hi Team,
>
>
>
> We are using GCC 4.8.3 for one of our legacy applications i.e: Automatch.
> after dat
Given a specific VAR_DECL tree node, I need to find out whether
its type is built in or not. Up to now I have
tree tn = TYPE_NAME (TREE_TYPE (var_decl));
if (tn != NULL_TREE && TREE_CODE (tn) == TYPE_DECL && DECL_NAME (tn))
{
...
}
This if-condition is true for both,
int x;
On Fri, Feb 14, 2014 at 9:59 AM, Dominik Vogt wrote:
> Given a specific VAR_DECL tree node, I need to find out whether
> its type is built in or not. Up to now I have
>
> tree tn = TYPE_NAME (TREE_TYPE (var_decl));
> if (tn != NULL_TREE && TREE_CODE (tn) == TYPE_DECL && DECL_NAME (tn))
>
On Fri, Feb 14, 2014 at 02:40:44PM +0100, Richard Biener wrote:
> On Fri, Feb 14, 2014 at 9:59 AM, Dominik Vogt wrote:
> > Given a specific VAR_DECL tree node, I need to find out whether
> > its type is built in or not. Up to now I have
> >
> > tree tn = TYPE_NAME (TREE_TYPE (var_decl));
> >
On Mon, Feb 17, 2014 at 1:15 PM, Dominik Vogt wrote:
> On Fri, Feb 14, 2014 at 02:40:44PM +0100, Richard Biener wrote:
>> On Fri, Feb 14, 2014 at 9:59 AM, Dominik Vogt
>> wrote:
>> > Given a specific VAR_DECL tree node, I need to find out whether
>> > its type is built in or not. Up to now I ha
On Mon, Feb 17, 2014 at 5:28 AM, Richard Biener
wrote:
> On Mon, Feb 17, 2014 at 1:15 PM, Dominik Vogt wrote:
>> On Fri, Feb 14, 2014 at 02:40:44PM +0100, Richard Biener wrote:
>>> On Fri, Feb 14, 2014 at 9:59 AM, Dominik Vogt
>>> wrote:
>>> > Given a specific VAR_DECL tree node, I need to find
Tracking this wrong-code bug, I ended up in combine.c::get_last_value() which
returns a wrong result. gcc generates wrong code at least with: 4.9 head, 5.2,
6.1 and trunk from today.
Before combine we have:
(insn 43 31 44 2 (set (reg:QI 18 r18)
(const_int 0 [0])) bug-combin.c:29 56 {m
Hello!
Execuse me but I have something bothering me.
I inserted a method into rest_of_compilation() (before calling
rest_of_handle_life()) to insert some new insn before insn were
translated to asm. But after my modification, when processing some
insn moving one pseudo reg to another ps
Hi,
I have compiled and generated a C++ shared library with the "-fPIC" option.
But this shared library requires text relocation during runtime and is not
usable on seLinux which disables writeable text segments. The text relocation
is due to use of exceptions inside the shared library. There
Hello,
I have currently a reproducable seg fault from an exe produced by gcc
4.0.1 (*). It does not appear using gcc 2.95, 3.2, 3.3, 3.4.
If I run it throught gdb I get:
0x402814b1 in __gnu_cxx::__pool::_M_reclaim_block () from
/usr/lib/libstdc++.so.6
(gdb) bt
#0 0x402814b1 in __gnu_cxx::_
On Mon, Jul 25, 2016 at 02:28:28PM +0200, Georg-Johann Lay wrote:
> (insn 43 31 44 2 (set (reg:QI 18 r18)
> (const_int 0 [0])) bug-combin.c:29 56 {movqi_insn}
> (nil))
> (insn 51 50 52 2 (set (reg:QI 16 r16)
> (const_int 40 [0x28])) bug-combin.c:29 56 {movqi_insn}
> (nil)
On 25.07.2016 23:05, Segher Boessenkool wrote:
On Mon, Jul 25, 2016 at 02:28:28PM +0200, Georg-Johann Lay wrote:
(insn 43 31 44 2 (set (reg:QI 18 r18)
(const_int 0 [0])) bug-combin.c:29 56 {movqi_insn}
(nil))
(insn 51 50 52 2 (set (reg:QI 16 r16)
(const_int 40 [0x28])) bu
On Tue, Jul 26, 2016 at 02:14:49PM +0200, Georg-Johann Lay wrote:
> >>which returns const0_rtx because reg 18 is set in insn 43 to const0_rtx.
> >>Total outcome is that the right shift of reg:DI 18 is transformed to a
> >>no-op move and cancelled out in the remainder.
> >
> >Why does num_sign_bit_c
On 26.07.2016 14:51, Segher Boessenkool wrote:
On Tue, Jul 26, 2016 at 02:14:49PM +0200, Georg-Johann Lay wrote:
which returns const0_rtx because reg 18 is set in insn 43 to const0_rtx.
Total outcome is that the right shift of reg:DI 18 is transformed to a
no-op move and cancelled out in the rem
On Tue, Jul 26, 2016 at 03:38:18PM +0200, Georg-Johann Lay wrote:
> >>@@ -13206,6 +13206,13 @@ get_last_value (const_rtx x)
> >> && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
> >> return 0;
> >>
> >>+ /* If the lookup is for a hard register make sure that value contains
> >>at
> >>
Segher Boessenkool schrieb:
On Tue, Jul 26, 2016 at 03:38:18PM +0200, Georg-Johann Lay wrote:
@@ -13206,6 +13206,13 @@ get_last_value (const_rtx x)
&& DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
return 0;
+ /* If the lookup is for a hard register make sure that value contains
at
On Wed, Jul 27, 2016 at 09:14:27PM +0200, Georg-Johann Lay wrote:
> >diff --git a/gcc/combine.c b/gcc/combine.c
> >index 77e0d2b..dec6226 100644
> >--- a/gcc/combine.c
> >+++ b/gcc/combine.c
> >@@ -9977,6 +9977,9 @@ reg_num_sign_bit_copies_for_combine (const_rtx x,
> >machine_mode mode,
> >
Hi Johann,
I tested a variant of your patch, building Linux for 32 different
(sub-)architectures; surprisingly (to me) there are no regressions
at all.
Do you want to send it to gcc-patches?
Segher
diff --git a/gcc/combine.c b/gcc/combine.c
index 77e0d2b..750bf83 100644
--- a/gcc/combine.c
++
On 29.07.2016 09:47, Segher Boessenkool wrote:
Hi Johann,
I tested a variant of your patch, building Linux for 32 different
(sub-)architectures; surprisingly (to me) there are no regressions
at all.
I am not so surprised because most backends don't make such an intense use of
hard-regs like t
On Fri, Jul 29, 2016 at 11:05:13AM +0200, Georg-Johann Lay wrote:
> There might still problems linger around if hard-regs are used:
>
> Suppose we set the reg in DImode and then get_last_value is called for the
> same reg in SImode. Using the DI value might be wrong, e.g. if it is used
> to com
Hello,
I am trying to port big C/C++ programs (see www.dslinux.org) to the
nintendo DS console.
The console has 4 Mbytes internal memory, and 32 MBytes external
memory which is *not* 8bit writable (only 16 and 32 bits). CPU is an ARM
946. Using the external memory for ROM(XIP) and the internal
Hi all,
I originally posted these messages to gcc-help, but had no reply, so I am
re-posting links to them here.
I think I have found a bug in g++ 4.0.0, but need help in reporting it.
Maintainers like their bug reports to include short test cases, but I don't
know how to generate a
Shankar Iyer writes:
> I have compiled and generated a C++ shared library with the "-fPIC" option.
> But this shared library requires text relocation during runtime and is not
> usable on seLinux which disables writeable text segments. The text relocation
> is due to use of exceptions inside
Hello all,
I am trying to do a port on GCC 4.5. The target has a memory
resolution of 32bits i.e. char is 32bits in the target (addr 0 selects
1st 32bit and addr 1 selects 2nd 32bit). It has only word (32bit)
access.
In terms of address resolution this target is similar to c4x which
became obsole
Dear gcc and/or apple OS X 7.9 users:
Union-Souths-Computer:~/gcc-5250 UnionSouth$ cat config.log
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
configure:595: checking host system type
configure:616: checking target s
good question, actually I did not know where is the error too.
to solve by easy, can you just email me a cc binary of (MAC OS X 7.9,
apple G5)yours by email?
> I found arm.md and the moveqi insns, but because of the different
> addressing modes of strb and swpb, its not easy to make the change.
> And there must be a compiler option for this, too.
>
> Could somebody please tell me how to implement this change?
Short answer is probably not.
There are a
On Tue, May 30, 2006 at 09:03:54PM +0100, Paul Brook wrote:
> > I found arm.md and the moveqi insns, but because of the different
> > addressing modes of strb and swpb, its not easy to make the change.
> > And there must be a compiler option for this, too.
> >
> > Could somebody please tell me how
> > There are a couple of complications that spring to mind. The different
> > addressing modes and the fact that swp clobbers a register are the most
> > immediate ones.
> >
> > You'll need to modify at least the movqi insn patterns, memory
> > constraints and the legitimate address stuff. I'm not
On Tuesday 30 May 2006 23:47, Daniel Jacobowitz wrote:
> On Tue, May 30, 2006 at 09:03:54PM +0100, Paul Brook wrote:
> > > I found arm.md and the moveqi insns, but because of the different
> > > addressing modes of strb and swpb, its not easy to make the
> > > change. And there must be a compiler o
Paul,
thank you for commenting...
On Tuesday 30 May 2006 22:03, Paul Brook wrote:
> > I found arm.md and the moveqi insns, but because of the different
> > addressing modes of strb and swpb, its not easy to make the change.
> > And there must be a compiler option for this, too.
> >
> > Could some
> > (define_insn "*arm_movqi_insn"
> > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q")
> > (match_operand:QI 1 "general_operand" "rI,K,m,+r"))]
> Changing "m" to "Q", narrowing the address modes
> Changing "r" to "+r", (register is globbered)
This is wrong. the "+" applies to th
On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote:
> > (define_insn "*arm_movqi_insn"
> > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q")
> > (match_operand:QI 1 "general_operand" "rI,K,m,+r"))]
> > "TARGET_ARM
> >&& ( register_operand (operands[0], QImode)
>
Rask,
On Thursday 01 June 2006 16:13, Rask Ingemann Lambertsen wrote:
> I think you will need to remove the '+' as already suggested and add
> (clobber (match_scratch:QI "=X,X,X,1")) to tell GCC that the register
> allocated to operand 1 is clobbered by the instruction for this
> particular altern
On Fri, Jun 02, 2006 at 08:23:49AM +0200, Wolfgang Mües wrote:
> Rask,
>
> (_only_ adding the clobber statement),
> I get
> >0/newlib/li bc/argz/argz_create_sep.c:60: error: unrecognizable insn:
> (insn 192 21 24 0 (set (reg:QI 1 r1) (reg:QI 4 r4)) -1
> (nil) (nil))
>
> What do you mean wit
Hello Rask,
On Friday 02 June 2006 09:24, Rask Ingemann Lambertsen wrote:
> There may be a faster way of seeing if the modification is going to
> work for the DS at all. I noticed from the output template
> "swp%?b\\t%1, %1, [%M0]" that "swp" takes three operands. I don't
> know ARM assembler, but
On Sunday 04 June 2006 11:31, Wolfgang Mües wrote:
> Hello Rask,
>
> On Friday 02 June 2006 09:24, Rask Ingemann Lambertsen wrote:
> > There may be a faster way of seeing if the modification is going to
> > work for the DS at all. I noticed from the output template
> > "swp%?b\\t%1, %1, [%M0]" that
Paul,
On Sunday 04 June 2006 13:24, Paul Brook wrote:
> On Sunday 04 June 2006 11:31, Wolfgang Mües wrote:
> > Splitting the insn
> >
> > (define_insn "*arm_movqi_insn"
> > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
> > (match_operand:QI 1 "general_operand" "rI,K,m,r"))]
>
On Sunday 04 June 2006 16:26, Wolfgang Mües wrote:
> Paul,
>
> On Sunday 04 June 2006 13:24, Paul Brook wrote:
> > On Sunday 04 June 2006 11:31, Wolfgang Mües wrote:
> > > Splitting the insn
> > >
> > > (define_insn "*arm_movqi_insn"
> > > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,
On Sun, Jun 04, 2006 at 12:31:08PM +0200, Wolfgang Mües wrote:
> Hello Rask,
>
> On Friday 02 June 2006 09:24, Rask Ingemann Lambertsen wrote:
> > There may be a faster way of seeing if the modification is going to
> > work for the DS at all. I noticed from the output template
> > "swp%?b\\t%1, %1
On Sun, Jun 04, 2006 at 12:24:53PM +0100, Paul Brook wrote:
> For the record these hacks are unlikely to ever be acceptable in mainline
> gcc.
> They're relatively invasive changes who's only purpose is to support
> fundamentally broken hardware.
We don't yet know if they'll be invasive. There
On Sun, Jun 04, 2006 at 05:26:42PM +0200, Wolfgang Mües wrote:
> Paul,
>
> On Sunday 04 June 2006 13:24, Paul Brook wrote:
>
> > You should just change the valid QImode memory addresses, adding a new
> > constraint if neccessary.
>
> H... I have tried this. I have changed the operand const
On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote:
> > (define_insn "*arm_movqi_insn"
> > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
> > (match_operand:QI 1 "general_operand" "rI,K,m,r"))]
> > "TARGET_ARM
> >&& ( register_operand (operands[0], QImode)
>
Rask Ingemann Lambertsen wrote:
There are other targets with targets specific options to work around this or
that bug, quirk, defect or errata. In this case, why would two options
-mno-byte-writes and -mbyte-writes, with the latter being the default, be
unlikely to be acceptable? In particular, t
Paul,
On Sunday 04 June 2006 17:57, Paul Brook wrote:
> Because then you have several different patterns for the same
> operation. The different variants of movsi should be part of the same
> pattern so that the compiler can change its mind which variant it
> wants to use.
Together with the comme
On Sun, 2006-06-04 at 22:01, Rask Ingemann Lambertsen wrote:
> On Sun, Jun 04, 2006 at 12:24:53PM +0100, Paul Brook wrote:
>
> > For the record these hacks are unlikely to ever be acceptable in mainline
> > gcc.
> > They're relatively invasive changes who's only purpose is to support
> > fundam
Hello Dave ;-)
On Monday 05 June 2006 02:12, Dave Murphy wrote:
> I was just about to ask about this very thing since I'm quite sure
> that there would be interest in adding this to devkitARM.
You are following the process in dslinux, don't you?
In fact, devkitARM is my current build environment
Richard,
On Monday 05 June 2006 12:06, Richard Earnshaw wrote:
> I'm confident right now that these will be too invasive to include in
> mainline.
As said before, this is OK for me.
> The changes that tend to get incorporated into the compiler are to
> work around bugs in the CPU, not bugs in s
Hello,
my first little success...
in arm.h, I have changed
> /* Output the address of an operand. */
> #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
> { \
> int is_minus = GET_CODE (X) == MINUS;
On Mon, 2006-06-05 at 12:47, Wolfgang Mües wrote:
> > /* Output the address of an operand. */
> > #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X)\
> > { \
> > int is_minus = GET_CODE (X) == MINUS;
> > Tightening the predicates isn't sufficient (and may not even be
> > neccessary). You need to set the constraints so that the compiler
> > knows *how* to fix invalid instructions.
>
> And if I have 4 different constraints in a single insn, and only one of
> them is needing a temporary register,
On Mon, Jun 05, 2006 at 01:47:10PM +0200, Wolfgang Mües wrote:
> I don't know why the form "[%r, #0]" was coded before, because the
> assembler understands "[%r]" very well for all instructions. The form
> "[%r]" has a wider usage because it covers swp too.
Does GCC happen to accept "[%r, #0]"
Rask,
On Monday 05 June 2006 16:16, Rask Ingemann Lambertsen wrote:
> On Mon, Jun 05, 2006 at 01:47:10PM +0200, Wolfgang Mües wrote:
> Does GCC happen to accept "[%r, #0]" for swp?
No. But no problem here to change that.
> I think the comment in arm.h is wrong. The manual seems to agree with
> t
Wolfgang Mües <[EMAIL PROTECTED]> writes:
> On Sunday 04 June 2006 23:36, Rask Ingemann Lambertsen wrote:
>> On Wed, May 31, 2006 at 10:49:35PM +0200, Wolfgang Mües wrote:
>> > > (define_insn "*arm_movqi_insn"
>> > > [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
>> > > (match_oper
On Tue, Jun 06, 2006 at 10:39:46AM +0100, Richard Sandiford wrote:
> Wolfgang Mües <[EMAIL PROTECTED]> writes:
> >> ../../../gcc-4.0.2/gcc/unwind-dw2-fde.c: In function
> >> __register_frame_info_table_bases':
> >> ../../../gcc-4.0.2/gcc/unwind-dw2-fde.c:146: error: insn does not
> >> satisfy its
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