On Thu, Aug 31, 2023 at 7:25 PM Andrew Pinski via Gcc-patches
wrote:
>
> This patch adds the following match patterns to optimize these:
> /* (a != b) ? (a - b) : 0 -> (a - b) */
> /* (a != b) ? (a ^ b) : 0 -> (a ^ b) */
> /* (a != b) ? (a & b) : a -> (a & b) */
> /* (a != b) ? (a | b) : a ->
On Thu, 31 Aug 2023, Andrew Pinski wrote:
> On Thu, Aug 31, 2023 at 5:15?AM Richard Biener via Gcc-patches
> wrote:
> >
> > On Thu, 31 Aug 2023, Filip Kastl wrote:
> >
> > > > The most obvious places would be right after SSA construction and
> > > > before RTL expansion.
> > > > Can you provide
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_):
New combine pattern.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_2): Ditto.
* config/riscv/autovec.md (2): Adjust.
(2): Adjust.
(2):
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_extend):
New combine pattern.
(*cond_trunc): Ditto.
* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-v.cc (needs_fp_rounding): Add FP extend.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_):
New combine pattern.
(*cond_): Ditto.
(*cond_): Ditto.
(*cond_trunc): Ditto.
* config/riscv/autovec.md (2): Adjust.
(2): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/a
Hi,
these patchs support combining convert_op + vcond_mask to convert_op with mask
operand. The method is to keep the vector convert pattern simple (by changing
define_expand to define_insn_and_split) until the combine pass and introduce
the corresponding pattern to match the pattern after the com
This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code`
to `unsigned icode` and use the icode directly to determine whether the
rounding_mode operand is required.
gcc/ChangeLog:
* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-protos.h (expand_cond_len_un
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation ADD/SUB/MUL/DIV.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] + in2[i];
}
Before this patch:
test:
csrr a4,vle
Brief version history of patch set:
v1 -> v2:
According to the GNU code specification, adjust the format of the
function implementation with "q" as the suffix function.
v2 - >v3:
1.On the LoongArch architecture, refer to the functionality of 64-bit
functions and modify the underlying imple
(Looks like this was committed as r14-3580-g597b9ec69bca8a)
> Cc: g...@gcc.gnu.org, gcc-patches@gcc.gnu.org, Eric Feng
> From: Eric Feng via Gcc
> gcc/testsuite/ChangeLog:
> PR analyzer/107646
> * gcc.dg/plugin/analyzer_cpython_plugin.c: Implements reference count
> * checking for PyO
This pushes the conversion further down the chain which allows to optimize away
more
conversions in many cases.
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR tree-optimization/107765
PR tree-optimization/107137
gcc/ChangeLog:
* match.pd (`(nop_
On Thu, Aug 31, 2023 at 03:09:52PM +0200, Marc Poulhiès wrote:
>
> Yang Yujie writes:
>
> Hello Yujie,
>
> > gcc/ChangeLog:
> >
> > * ada/Makefile.rtl: Add LoongArch support.
> > * ada/libgnarl/s-linux__loongarch.ads: New.
> > * ada/libgnat/system-linux-loongarch.ads: New.
> > *
On 2023-08-29 09:46 Jeff Law wrote:
>
>
>
>On 8/28/23 19:28, Fei Gao wrote:
>> On 2023-08-29 06:54 Jeff Law wrote:
>>>
>>>
>>>
>>> On 8/28/23 01:47, Fei Gao wrote:
no functional changes but allow targets to check shrink-wrap-separate
enabled or not.
gcc/ChangeLog:
>>
On Thu, Aug 31, 2023 at 05:56:26PM +, Joseph Myers wrote:
> On Thu, 31 Aug 2023, Yujie Yang wrote:
>
> > -If none of such suffix is present, the configured value of
> > -@option{--with-multilib-default} can be used as a common default suffix
> > -for all library ABI variants. Otherwise, the d
On Fri, 2023-09-01 at 00:04 +0200, priour...@gmail.com wrote:
> Hi,
>
> Succesfully regstrapped off trunk 7f2ed06ddc825e8a4e0edfd1d66b5156e6dc1d34
> on x86_64-linux-gnu.
>
> Is it OK for trunk ?
Hi Benjamin.
Thanks for the patch. It's OK as-is, but it doesn't cover every
case...
[...snip..
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the pic instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib with newlib/linux.
gcc/Changelog:
We are going to support dynamic LMUL support.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Add dynamic
enum.
* config/riscv/riscv.opt: Add dynamic compile option.
---
gcc/config/riscv/riscv-opts.h | 4 +++-
gcc/config/riscv/riscv.opt| 3 +++
2
since we have added COST framework, we by default enable VECT_COMPARE_COSTS.
Also, add 16/32/64 to provide more choices for COST comparison.
This patch doesn't change any behavior from the current testsuite since we are
using
default COST model.
gcc/ChangeLog:
* config/riscv/riscv-v.cc
From: benjamin priour
Hi,
Succesfully regstrapped off trunk 7f2ed06ddc825e8a4e0edfd1d66b5156e6dc1d34
on x86_64-linux-gnu.
Is it OK for trunk ?
Thanks,
Benjamin.
Patch below.
---
Fixed spurious possibly-NULL warning always tagging along throwing
operator new despite it never returning NULL.
On 8/31/23 04:08, Jakub Jelinek wrote:
Hi!
C++17 had in [basic.block.scope]/2
"A parameter name shall not be redeclared in the outermost block of the function
definition nor in the outermost block of any handler associated with a
function-try-block."
and in [basic.block.scope]/4 similar rule for
On Thu, Aug 31, 2023 at 5:15 AM Richard Biener via Gcc-patches
wrote:
>
> On Thu, 31 Aug 2023, Filip Kastl wrote:
>
> > > The most obvious places would be right after SSA construction and before
> > > RTL expansion.
> > > Can you provide measurements for those positions?
> >
> > The algorithm sho
Dear all,
gfortran's array bounds-checking code does a mostly reasonable
job for array sections in expressions and assignments, but
forgot the case that (rank-1) expressions can involve array
constructors, which have a shape ;-)
The attached patch walks over the loops generated by the
scalarizer,
On 8/31/23 03:20, Jakub Jelinek wrote:
Hi!
As the following testcase shows, while check_local_shadow diagnoses most of
the [basic.scope.block]/2 violations, it doesn't diagnose when parameter's
name is redeclared inside of the compound-stmt of a function-try-block.
There is in that case an extr
On Thu, 31 Aug 2023 at 18:42, Jonathan Wakely wrote:
>
> On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
> wrote:
> >
> > As discussed in PR104167 (comments #8 and below), and PR111238, using
> > -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> > (cross-toolchain) avoids link failures for
On 8/31/23 15:14, Jakub Jelinek wrote:
On Thu, Aug 31, 2023 at 01:11:57PM -0400, Jason Merrill wrote:
2023-08-28 Jakub Jelinek
PR c++/111069
gcc/
* common.opt (fabi-version=): Document version 19.
* doc/invoke.texi (-fabi-version=): Likewise.
gcc/c-family/
* c
> From: Hans-Peter Nilsson
> Date: Thu, 31 Aug 2023 19:05:19 +0200
> > Date: Thu, 31 Aug 2023 17:25:45 +0200
> > From: Christophe Lyon via Gcc-patches
> > However, this would hide the fact that libstdc++ somehow forces the
> > user to use -Wl,-gc-sections to avoid undefined references to chdir,
On Thu, Aug 31, 2023 at 01:11:57PM -0400, Jason Merrill wrote:
> > 2023-08-28 Jakub Jelinek
> >
> > PR c++/111069
> > gcc/
> > * common.opt (fabi-version=): Document version 19.
> > * doc/invoke.texi (-fabi-version=): Likewise.
> > gcc/c-family/
> > * c-opts.cc (c_common_post_op
On 8/31/23 06:51, Jeff Law wrote:
On 8/30/23 15:57, Vineet Gupta wrote:
This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the
pattern semantics can't be expressed by zicond instructions.
This involves test code snippet:
if (a == 0)
return 0;
else
retu
On Thu, 31 Aug 2023, Yujie Yang wrote:
> -If none of such suffix is present, the configured value of
> -@option{--with-multilib-default} can be used as a common default suffix
> -for all library ABI variants. Otherwise, the default build option
> -@code{-march=abi-default} is applied when buildin
On Thu, 31 Aug 2023, 18:43 Jonathan Wakely via Libstdc++, <
libstd...@gcc.gnu.org> wrote:
> On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
> wrote:
> >
> > As discussed in PR104167 (comments #8 and below), and PR111238, using
> > -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> > (cross-
On Thu, 31 Aug 2023 at 16:26, Christophe Lyon
wrote:
>
> As discussed in PR104167 (comments #8 and below), and PR111238, using
> -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> (cross-toolchain) avoids link failures for a few tests:
>
> 27_io/filesystem/path/108636.cc
I think this one
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib for linux/newlib.
gcc/Changelog:
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the riscv instructions to ensure that no insn is left
without a type attribute. Added new types: "trap" (self explanatory) and "cbo"
(for cache related instructions)
Te
This patch adds the following match patterns to optimize these:
/* (a != b) ? (a - b) : 0 -> (a - b) */
/* (a != b) ? (a ^ b) : 0 -> (a ^ b) */
/* (a != b) ? (a & b) : a -> (a & b) */
/* (a != b) ? (a | b) : a -> (a | b) */
/* (a != b) ? min(a,b) : a -> min(a,b) */
/* (a != b) ? max(a,b) : a
On 8/28/23 09:58, Jakub Jelinek wrote:
Hi!
On Thu, Aug 24, 2023 at 06:39:10PM +0200, Jakub Jelinek via Gcc-patches wrote:
Maybe do this in mangle_decomp, based on the actual mangling in process
instead of this pseudo-mangling?
Not sure that is possible, for 2 reasons:
1) determine_local_discr
> Date: Thu, 31 Aug 2023 17:25:45 +0200
> From: Christophe Lyon via Gcc-patches
> As discussed in PR104167 (comments #8 and below), and PR111238, using
> -Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
> (cross-toolchain) avoids link failures for a few tests:
>
> 27_io/filesystem/path/1
On Wed, 2023-08-30 at 18:15 -0400, Eric Feng wrote:
> On Tue, Aug 29, 2023 at 5:14 PM David Malcolm
> wrote:
> >
> > On Tue, 2023-08-29 at 13:28 -0400, Eric Feng wrote:
> > > Additionally, by using the old model and the pointer per your
> > > suggestion,
> > > we are able to find the representati
Hi,
Thanks Sandra and Iain.
Patch pushed.
FX
On 8/31/23 05:27, Iain Sandoe wrote:
Hi FX,
+Sandra
On 31 Aug 2023, at 12:13, FX Coudert wrote:
This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It is
not a global replacement though, and
As discussed in PR104167 (comments #8 and below), and PR111238, using
-Wl,-gc-sections in the libstdc++ testsuite for arm-eabi
(cross-toolchain) avoids link failures for a few tests:
27_io/filesystem/path/108636.cc
std/time/clock/gps/1.cc
std/time/clock/gps/io.cc
std/time/clock/tai/1.cc
std/time/c
While backporting another patch to an earlier release, I hit a
situation in which lra_eliminate_regs_1 would eliminate an address to:
(plus (reg:P R) (const_int 0))
This address compared not-equal to plain:
(reg:P R)
which caused an ICE in a later peephole2. (The ICE showed up in
gfort
While working on another patch, I hit a problem with the aarch64
expansion of untyped_call. The expander emits the usual:
(set (mem ...) (reg resN))
instructions to store the result registers to memory, but it didn't
say in RTL where those resN results came from. This eventually led
to a fail
On Thu, Aug 31, 2023 at 6:57 AM Ken Matsui wrote:
>
> On Tue, Aug 8, 2023 at 1:19 PM Jonathan Wakely wrote:
> >
> >
> >
> > On Tue, 18 Jul 2023 at 07:25, Ken Matsui via Libstdc++
> > wrote:
> >>
> >> Hi,
> >>
> >> I took a benchmark for this.
> >>
> >> https://github.com/ken-matsui/gcc-benches/
On Wed, 30 Aug 2023 at 19:20, David Malcolm wrote:
>
> On Wed, 2023-08-30 at 11:52 +0530, Prathamesh Kulkarni wrote:
> > On Wed, 30 Aug 2023 at 04:21, David Malcolm
> > wrote:
> > >
> > > On Tue, 2023-08-29 at 11:01 +0530, Prathamesh Kulkarni wrote:
> > > > On Fri, 25 Aug 2023 at 18:15, David Mal
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, August 31, 2023 9:09 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
LGTM
On Thu, Aug 24
On Tue, Aug 8, 2023 at 1:19 PM Jonathan Wakely wrote:
>
>
>
> On Tue, 18 Jul 2023 at 07:25, Ken Matsui via Libstdc++
> wrote:
>>
>> Hi,
>>
>> I took a benchmark for this.
>>
>> https://github.com/ken-matsui/gcc-benches/blob/main/is_fundamental-disjunction.md#mon-jul-17-105937-pm-pdt-2023
>>
>> t
On 8/30/23 15:57, Vineet Gupta wrote:
This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the
pattern semantics can't be expressed by zicond instructions.
This involves test code snippet:
if (a == 0)
return 0;
else
return x;
}
which is equiva
On Tue, Aug 8, 2023 at 1:14 PM Jonathan Wakely wrote:
>
>
>
> On Tue, 18 Jul 2023 at 07:28, Ken Matsui via Libstdc++
> wrote:
>>
>> I will eventually work on disjunction to somehow optimize, but in the
>> meantime, this might be a better implementation. Of course, my
>> benchmark could be wrong.
Yang Yujie writes:
Hello Yujie,
> gcc/ChangeLog:
>
> * ada/Makefile.rtl: Add LoongArch support.
> * ada/libgnarl/s-linux__loongarch.ads: New.
> * ada/libgnat/system-linux-loongarch.ads: New.
> * config/loongarch/loongarch.h: mark normalized options
> passed from d
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, August 31, 2023 9:10 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec
LGTM
On Thu, Aug 24
LGTM
On Thu, Aug 24, 2023 at 12:49 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination
>
> vfadd RTZ <- intrinisc static rounding
> vfmadd <- autovec/autovec-opt
>
> The autovec generated vfmadd should take DYN mode,
LGTM
On Thu, Aug 24, 2023 at 3:13 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfmsub <- autovec/autovec-opt
>
> The autovec generated vfmsub should take DYN mode,
These are exported according to the LoongArch Toolchain Conventions[1]
as a replacement of the obsolete "_LOONGARCH_{ARCH,TUNE}" macros,
which are expanded to strings representing the actual architecture
and microarchitecture of the target.
[1] currently relased at https://github.com/loongson/Loon
This is an update of
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628772.html
Changes since the last patchset:
1. Fix texinfo format of the install.texi document.
2. Add documentation for --with-strict-align-lib.
v1 -> v2:
1. Add new configure option --with-strict-align-lib to control
The configure script and the GCC driver are updated so that
it is easier to customize and control GCC builds for targeting
different LoongArch implementations.
* Make --with-abi obsolete, since it might cause different default ABI
under the same target triplet, which is undesirable. The default
gcc/ChangeLog:
* config.gcc: add loongarch*-elf target.
* config/loongarch/elf.h: New file.
Link against newlib by default.
libgcc/ChangeLog:
* config.host: add loongarch*-elf target.
---
gcc/config.gcc | 15 ++-
gcc/config/loongarch/elf.h | 5
LoongArch processors may not support memory accesses without natural
alignments. Building libraries with -mstrict-align may help with
toolchain binary compatiblity and performance on these implementations
(e.g. Loongson 2K1000LA).
No significant performance degredation is observed on current main
On Thu, Aug 31, 2023 at 12:37:59PM +, Richard Biener via Gcc-patches wrote:
> The following keeps dumping SSA def stmt RHS during diagnostic
> reporting only for gimple_assign_single_p defs which means
> memory loads. This avoids diagnostics containing PHI nodes
> like
>
> warning: 'realloc
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Thursday, August 31, 2023 8:39 PM
To: Robin Dapp
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; Juzhe-Zhong
Subject: Re: [PATCH] RISC-V: Add Vector cost model framework
LGTM, Awesome!! It seems a sign of the next big move for RISC-V vectorization!
On Thu, Aug 31, 2023 at 8:36 PM Robin Dapp wrote:
>
> OK. As it doesn't do anything and we'll be needing it anyway no harm
> in adding it.
>
> Regards
> Robin
The following keeps dumping SSA def stmt RHS during diagnostic
reporting only for gimple_assign_single_p defs which means
memory loads. This avoids diagnostics containing PHI nodes
like
warning: 'realloc' called on pointer '*_42 = PHI .t_mem_caches' with nonzero offset 40
instead getting back
OK. As it doesn't do anything and we'll be needing it anyway no harm
in adding it.
Regards
Robin
On Tue, Aug 8, 2023 at 1:23 PM Jonathan Wakely wrote:
>
>
>
> On Wed, 19 Jul 2023 at 20:33, Ken Matsui via Libstdc++
> wrote:
>>
>> This patch defines _GLIBCXX_HAS_BUILTIN_TRAIT macro, which will be used
>> as a flag to toggle the use of built-in traits in the type_traits header
>> through _GLIB
Sorry for that, rebased and send V4 patch, thanks.
On 2023/8/31 17:50, Kito Cheng via Gcc-patches wrote:
Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...
On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding wrote:
Because functions which fol
Functions which follow vector calling convention variant need be annotated by
.variant_cc directive according the RISC-V Assembly Programmer's Manual[1] and
RISC-V ELF Specification[2].
[1]
https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
[2]
https://github.c
Because functions which follow vector calling convention variant has
callee-saved vector reigsters but functions which follow standard calling
convention don't have. We need to distinguish which function callee is so that
we can tell GCC exactly which vector registers callee will clobber. So I enco
I post the vector register calling convention rules from in the proposal[1]
directly here:
v0 is used to pass the first vector mask argument to a function, and to return
vector mask result from a function. v8-v23 are used to pass vector data
arguments, vector tuple arguments and the rest vector ma
V4 change: Rebasing.
Hi RISC-V folks,
This patch implement the proposal of RISC-V vector calling convention[1] and
this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
all vector type arguments and return values are pass by reference. With this
patch, these arguments and r
On Wed, Aug 30, 2023 at 11:33 AM Di Zhao OS
wrote:
>
> Hello Richard,
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Tuesday, August 29, 2023 7:11 PM
> > To: Di Zhao OS
> > Cc: Jeff Law ; Martin Jambor ; gcc-
> > patc...@gcc.gnu.org
> > Subject: Re: [PATCH] [tree-optimizatio
Hi, currently RVV vectorization only support picking LMUL according to
compile option --param=riscv-autovec-lmul= which is no ideal.
Compiler should be able to pick optimal LMUL/vectorization factor to
vectorize the loop according to the loop_vec_info and SSA-based register
pressure analysis.
Now
On Thu, Aug 31, 2023 at 12:27 AM Andrew Pinski via Gcc-patches
wrote:
>
> This simple patch extends the min_value/max_value match to vector integer
> types.
> Using uniform_integer_cst_p makes this easy.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
>
> The testcases pr
On Thu, 31 Aug 2023, Filip Kastl wrote:
> > The most obvious places would be right after SSA construction and before
> > RTL expansion.
> > Can you provide measurements for those positions?
>
> The algorithm should only remove PHIs that break SSA form minimality. Since
> GCC's SSA construction a
On Thu, Aug 31, 2023 at 01:26:37PM +0200, Filip Kastl wrote:
> Regarding debug info coverage: I didn't notice any additional guality
> testcases
> failing after I applied the patch. *Is there any other way how I should check
> debug info coverage?*
I'm usually using https://github.com/pmachata/dw
This patch removes zero extension from vctzlsbb as it already zero extends.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
alre
This patch removes zero extension from vctzlsbb as it already zero extends.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index
For rs6000 target we dont need zero_extend after vctzlsbb as vctzlsbb
al
Hi FX,
+Sandra
> On 31 Aug 2023, at 12:13, FX Coudert wrote:
>
> This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
> OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It
> is not a global replacement though, and each use was audited.
>
> -
> The most obvious places would be right after SSA construction and before RTL
> expansion.
> Can you provide measurements for those positions?
The algorithm should only remove PHIs that break SSA form minimality. Since
GCC's SSA construction already produces minimal SSA form, the algorithm isn't
On Thu, 31 Aug 2023, Robin Dapp wrote:
> Hi,
>
> on some targets we fail to vectorize with the first type the vectorizer
> tries but succeed with the second. This patch changes several regex
> patterns to reflect that behavior.
>
> Before we would look for a single occurrence of e.g.
> "vect_re
Before optimization, the operation of taking fixed-point numbers from memory
and then forcing type conversion needs to be loaded into fixed-point registers
before conversion. After the optimization is completed, the fixed-point value
is directly transferred to the floating-point register for type c
This patch homogenizes to some extent the use of “Mac OS X” or “OS X” or “Mac
OS” in the gcc/ folder to “macOS”, which is the modern way of writing it. It is
not a global replacement though, and each use was audited.
- When referring to specific versions that used the “OS X” or “Mac OS” as their
Committed, thanks Kito.
On 2023/8/31 17:13, Kito Cheng via Gcc-patches wrote:
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
This patch change the vsetvl policy to default policy
(returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
fixed policy. Any policy is now r
The testcase requires hardware support for V2DImode vectors because
otherwise we do not rewrite inserts via BIT_FIELD_REF to
BIT_INSERT_EXPR. There's no effective target for this so the
following makes the testcase x86 specific, requiring and enabling SSE2.
Pushed.
* gcc.dg/tree-ssa/forw
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> Current reload infrastructure does not support selective base_reg_class
> for backend insn. Add insn argument to base_reg_class for
> lra/reload usage.
I don't think this is the correct approach. Ideally, a memory
co
Thanks for the testing work! I will continue to try to find and resolve
some subtle issues too (Such as use compiler to compile some large
project). I'm also curious about the partly saved register problem and
will take some learning and investigation in the future.
On Thu, 2023-08-31 at 17:41 +08
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
>
> From: Kong Lingling
>
> These legacy insn in opcode map0/1 only support GPR16,
> and do not have vex/evex counterpart, directly adjust constraints and
> add gpr32 attr to patterns.
>
> insn list:
> 1. xsave/xsave64, xrstor/xrstor64
> 2. xsav
Hi,
on some targets we fail to vectorize with the first type the vectorizer
tries but succeed with the second. This patch changes several regex
patterns to reflect that behavior.
Before we would look for a single occurrence of e.g.
"vect_recog_dot_prod_pattern" but would possible find two (one f
On Thu, Aug 31, 2023 at 11:18 AM Jakub Jelinek via Gcc-patches
wrote:
>
> On Thu, Aug 31, 2023 at 04:20:17PM +0800, Hongyu Wang via Gcc-patches wrote:
> > From: Kong Lingling
> >
> > In inline asm, we do not know if the insn can use EGPR, so disable EGPR
> > usage by default from mapping the comm
Hi Robin,
Thanks for these comments.
On 2023/8/31 17:16, Robin Dapp wrote:
Hi Lehua,
thanks, this definitely goes into the direction of what I had in mind and
simplifies a lot of the reduntant emit_... so it's good to have it.
I was too slow for a detailed response :) So just some high-level
Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...
On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding wrote:
>
> Because functions which follow vector calling convention variant has
> callee-saved vector reigsters but functions which follow stand
On Thu, Aug 31, 2023 at 04:20:19PM +0800, Hongyu Wang via Gcc-patches wrote:
> For vector move insns like vmovdqa/vmovdqu, their evex counterparts
> requrire explicit suffix 64/32/16/8. The usage of these instruction
> are prohibited under AVX10_1 or AVX512F, so for AVX2+APX_F we select
> vmovaps/v
On Thu, 2023-08-31 at 17:08 +0800, Chenghui Pan wrote:
> This is an update of:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628303.html
>
> Changes since last version of patch set:
> - "dg-skip-if"-related Changes of the g++.dg/torture/vshuf* testcases are
> reverted.
> (Replaced by
On Thu, Aug 31, 2023 at 11:26:26AM +0200, Richard Biener wrote:
> On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
> wrote:
> >
> > From: Kong Lingling
> >
> > Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> > but no evex counterpart.
> >
> > insn list:
> >
On Thu, Aug 31, 2023 at 11:26 AM Richard Biener
wrote:
>
> On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
> wrote:
> >
> > From: Kong Lingling
> >
> > Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> > but no evex counterpart.
> >
> > insn list:
> > 1. phm
On Thu, Aug 31, 2023 at 10:25 AM Hongyu Wang via Gcc-patches
wrote:
>
> From: Kong Lingling
>
> Disable EGPR usage for below legacy insns in opcode map2/3 that have vex
> but no evex counterpart.
>
> insn list:
> 1. phminposuw/vphminposuw
> 2. ptest/vptest
> 3. roundps/vroundps, roundpd/vroundpd,
On Thu, Aug 31, 2023 at 10:22 AM Hongyu Wang via Gcc-patches
wrote:
>
> Intel Advanced performance extension (APX) has been released in [1].
> It contains several extensions such as extended 16 general purpose registers
> (EGPRs), push2/pop2, new data destination (NDD), conditional compare
> (CCMP
On Thu, Aug 31, 2023 at 04:20:17PM +0800, Hongyu Wang via Gcc-patches wrote:
> From: Kong Lingling
>
> In inline asm, we do not know if the insn can use EGPR, so disable EGPR
> usage by default from mapping the common reg/mem constraint to non-EGPR
> constraints. Use a flag mapx-inline-asm-use-gp
Ok, I just went through the patchlist and found this patch seems
not committed yet, anyway I will mark this as commit now :)
On Thu, Aug 31, 2023 at 5:14 PM Tsukasa OI via Gcc-patches
wrote:
>
> On 2023/08/31 18:10, Kito Cheng wrote:
> > Hi Tsukasa:
> >
> > I guess you might did something wrong
Hi Lehua,
thanks, this definitely goes into the direction of what I had in mind and
simplifies a lot of the reduntant emit_... so it's good to have it.
I was too slow for a detailed response :) So just some high-level comments.
One thing I noticed is the overloading of "MASK_OP", we use it as
LGTM
On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding wrote:
>
> This patch change the vsetvl policy to default policy
> (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
> fixed policy. Any policy is now returned, allowing change to agnostic
> or undisturbed. In the future, users
On 2023/08/31 18:10, Kito Cheng wrote:
> Hi Tsukasa:
>
> I guess you might did something wrong during commit this patch and
> "RISC-V: Add stub support for existing extensions"
>
> https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
>
It's fine. That patch was a p
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