On Tue, 29 Jul 2025, Jakub Jelinek wrote:
> On Tue, Jul 29, 2025 at 11:20:25AM -0500, Robert Dubner wrote:
> > I removed the pick of 0eac9cfe, and I removed the pick of ed8761241ac529,
> > which had already been done by Thomas.
> >
> > I just applied the other 45 relevant commits, and pushed tha
On Tue, 29 Jul 2025, 14:34 Björn Schäpers, wrote:
> From: Björn Schäpers
>
> I want assertions to be enabled, while compiling for bare metal and I
> don't have any printf variants at my hand (nor want I).
>
Then don't you want to use --disable-libstdcxx-verbose ?
> -- >8 --
> Mark it as weak
OK
(The zoned_time feature does work for this build config, and the error
should be present, but the { target cxx11_abi } selector doesn't consider
the "no dual ABI" case so the error doesn't match the dg-error. The
simplest fix is this patch.)
On Tue, 29 Jul 2025, 18:50 François Dumont, wrote
On Wed, Jul 30, 2025 at 11:45 AM H.J. Lu wrote:
>
> commit 4c80062d7b8c272e2e193b8074a8440dbb4fe588
> Author: H.J. Lu
> Date: Sun May 25 07:40:29 2025 +0800
>
> x86: Enable *mov_(and|or) only for -Oz
>
> disabled transformation from "movq $-1,reg" to "pushq $-1; popq reg" for
> -Oz. But fo
Hi Harald,
>From a very quick perusal of the F2018 standard, I have come to the
tentative conclusion that:
(i) 'real module function realg (arg1, arg2)' is almost certainly a
correct requirement, although both flang-new and gfortran compile happily
without the module attribute; and
(ii) As far as
Hi Kito,
Kito Cheng 於 2025年7月30日 週三 上午9:01寫道：
>
> > +(define_insn "@nds_vfwcvt_bf16"
> > + [(set (match_operand:NDS_VWEXTBF 0 "register_operand"
> > "=&vr")
> > + (unspec_volatile:NDS_VWEXTBF
> > + [(float_extend:NDS_VWEXTBF
> > +(match_operand: 1 "reg
> -Original Message-
> From: Richard Biener
> Sent: Monday, July 28, 2025 2:28 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Tamar Christina
>
> Subject: [PATCH] Record get_load_store_info results from analysis
>
> The following is a prototype-quality patch to make us record
From: Pan Li
The unsigned avg ceil share the vaaddx.vx for the vx combine,
so add the test case to make sure it works well as expected.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/v
I checked, and GCC 14 (and others) uses https; not sure how http snuck
in here for the GCC 15 web pages?
Pushed.
Gerald
---
htdocs/gcc-15/index.html | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/htdocs/gcc-15/index.html b/htdocs/gcc-15/index.html
index d68da280..5670dd
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 1:43 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra
> Subject: [PATCH] aarch64: Improve
> On 29 Jul 2025, at 18:41, Richard Sandiford wrote:
>
> This patch continues the work of making ACLE intrinsics use VNx16BI
> for svbool_t results. It deals with the floating-point forms of svcmp*.
>
> gcc/
> * config/aarch64/aarch64-sve.md (@aarch64_pred_fcm_acle)
> (*aarch64_pred_fcm_acle,
On Tue, Jul 29, 2025 at 10:29:37PM +0200, Harald Anlauf wrote:
>
> - I am a little confused about the handling of the access specification.
> After the first "public :: g", NAG complains about the
>
> generic, public :: g ...
>
> and only allows
>
> generic :: g ...
>
> Then duplicate pub
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 5:20 PM
> To: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra ; gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PAT
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 5:20 PM
> To: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra ; gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, July 29, 2025 4:33 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Alex Coplan ; Alice Carlotti
> ;
> pins...@gmail.com; ktkac...@nvidia.com; Richard Earnshaw
> ; Tamar Christina ;
> Wilco Dijkstra
> Subject: [PATCH] aarch64: Use VNx
commit 4c80062d7b8c272e2e193b8074a8440dbb4fe588
Author: H.J. Lu
Date: Sun May 25 07:40:29 2025 +0800
x86: Enable *mov_(and|or) only for -Oz
disabled transformation from "movq $-1,reg" to "pushq $-1; popq reg" for
-Oz. But for legacy integer registers, the former is 4 bytes and the
latter
The patch is trying to unroll the vectorized loop when there're
FMA/DOT_PRDO_EXPR reductions, it will break cross-iteration dependence
and enable more parallelism(since vectorize will also enable partial
sum).
When there's gather/scatter or scalarization in the loop, don't do the
unroll since the
On Tue, Jul 29, 2025 at 11:13 AM Yeoul Na wrote:
>
>
> On Jul 28, 2025, at 5:54 PM, Bill Wendling wrote:
>
> On Mon, Jul 28, 2025 at 4:52 PM Yeoul Na wrote:
>
>
> Could someone working on Linux answer my earlier question? Working on a
> compromise solution is one thing, but I’m trying to unders
Hi Jeff & Kito,
Thanks for all your review.
We'll Fixed these in next patch version.
Kito Cheng 於 2025年7月30日 週三 上午9:48寫道：
>
> On Tue, Jul 22, 2025 at 6:40 AM Jeff Law wrote:
> >
> >
> >
> > On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > > This extension defines instructions to perform scalar floa
On Mon, Jul 28, 2025 at 11:36 PM Martin Uecker wrote:
>
> Am Montag, dem 28.07.2025 um 17:45 -0700 schrieb Bill Wendling:
> > On Mon, Jul 28, 2025 at 4:29 PM Martin Uecker wrote:
> > > Am Montag, dem 28.07.2025 um 16:01 -0700 schrieb Bill Wendling:
> > > > On Mon, Jul 28, 2025 at 2:39 PM Martin U
It's needed by avx5124vnniw/avx5124fmaps which have been removed by
r15-656-ge1a7e2c54d52d0.
Ready push to trunk after passing regression test.
gcc/ChangeLog:
* config/i386/i386-modes.def: Remove VECTOR_MODES(FLOAT, 256)
and VECTOR_MODE (INT, SI, 64).
* config/i386/i386.c
On Tue, Jul 22, 2025 at 6:40 AM Jeff Law wrote:
>
>
>
> On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > This extension defines instructions to perform scalar floating-point
> > conversion between the BFLOAT16 floating-point data and the IEEE-754
> > 32-bit single-precision floating-point (SP) data in
No worries, thanks!
在 2025/7/29 23:02, Kito Cheng 写道:
I thought I already merged that until today's RISC-V patchwork
meeting, committed to trunk :P
Jeff Law 於 2025年7月22日 週二 上午6:34寫道：
Hi Jeff,
Thanks your review.
> > +
> > +(define_insn "*nds_branch_imms7"
> > + [(set (pc)
> > + (if_then_else
> > + (match_operator 1 "equality_operator"
> > + [(match_operand:X 2 "register_operand" "r")
> > + (match_operand:X 3 "ad
r14-1902-g96c3539f2a3813 split TImode move with 2 DImode move, it's
supposed to optimize TImode in parameter/return since accoring to
psABI it's stored into 2 general registers.
But when TImode is not in parameter/return, it could create redundancy
in the PR.
The patch add a splitter to handle th
The failure of CI is unrelated, will commit it soon.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, July 29, 2025 11:23 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; Liu, Hongtao
; Li, Pan2
This one is LGTM :)
On Tue, Jul 22, 2025 at 6:04 AM Jeff Law wrote:
>
>
>
> On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
> > This patch add basic support for the following XAndes ISA extensions:
> >
> > XANDESPERF
> > XANDESBFHCVT
> > XANDESVBFHCVT
> > XANDESVSINTLOAD
> > XANDESVPACKFPH
> > XANDESVDO
> +(define_insn "@nds_vfwcvt_bf16"
> + [(set (match_operand:NDS_VWEXTBF 0 "register_operand"
> "=&vr")
> + (unspec_volatile:NDS_VWEXTBF
> + [(float_extend:NDS_VWEXTBF
> +(match_operand: 1 "register_operand" "
> vr"))]
> + UNSPEC_NDS_VFWCVTBF16
On 7/27/2025 8:51 PM, Mikael Morin wrote:
Le 27/07/2025 à 13:46, Yuao Ma a écrit :
On 7/27/2025 7:14 PM, Mikael Morin wrote:
Le 27/07/2025 à 11:37, Yuao Ma a écrit :
On 7/27/2025 5:19 PM, Mikael Morin wrote:
+gfc_charlen_type
+string_split (gfc_charlen_type stringlen, const CHARTYPE *str
r16-2590-ga51bf9e10182cf was not the correct fix for this in the end.
Instead a much simplier and localized fix is needed, just change the phi
that is being worked on with the new result and arguments that is from the
factored out operator.
This solves the issue of not having result in the IR and c
r16-2614-g965564eafb721f had a typo where it would assume byte==0
rather than use the byte (offset) that was passed.
This fixes that typo and also fixes the comment since it is not just
about lowerpart subregs but all non-paradoxical subregs.
Pushed as obvious after bootstrap/test on x86_64-linux
Changes in v7:
* Clean up comments, inactive cases in tests.
* Restore symmetry of tests for bind_back and bind_front
* Add another test for type qualifier propagation, per review
* Add test verifying arguments are properly moved into the capture
object.
Changes in v6:
* Remove deletion of
On 7/29/25 3:20 AM, Jakub Jelinek wrote:
Hi!
The PR13358 r0-92909 change changed the diagnostics on long long
in C++ (either with -std=c++98 or -Wlong-long), but unlike the
C FE we unfortunately warn even in the
__extension__ long long a;
etc. cases. The C FE in that case in
disable_extension_d
On 7/29/25 3:45 AM, Jakub Jelinek wrote:
Hi!
The P2843R3 Preprocessing is never undefined paper contains comments
that various compilers handle comma operators in preprocessor expressions
incorrectly and I think they are right.
In both C and C++ the grammar uses constant-expression non-terminal
On Tue, Jul 22, 2025 at 11:13 PM Gerald Pfeifer wrote:
>
> On Tue, 15 Jul 2025, H.J. Lu wrote:
> >> This feels a bit complex to parse. How about something like
> >>
> >> + The new --enable-x86-64-mfentry configure option
> >> + makes -mfentry use __fentry__ instead
> >> + of mcount for
On Tue, Jul 29, 2025 at 7:40 AM Alfie Richards wrote:
>
> Hi All,
>
> Quick fixup for the gating (s/&&/|/) for an error I made.
>
> Only needed for trunk as the intrinsics were only added recently.
>
> Bootstrapped and reg tested on Aatch64.
Ok. Though this seems obvious since AARCH64_FL_SME2 and
On Sun, 13 Jul 2025, Jonathan Wakely wrote:
> This is an anachronism: ChangeLog entries should never be part of the
> patch, because nobody should be editing them locally and including them
> in a commit. Whether you can self-approve or not isn't relevant.
Nice. In general we should be looking at
An update on this version:
1. Sam reported two hangs when he tested the v7 with glibc and tinc.
I have fixed this issue in my local area.
2. David provided the patch for his latest change r16-2520-g6d9152659f4f6a
I have included into my latest version.
The v8 is under testing, will
On Tue, Jul 29, 2025 at 6:58 AM Stefan Schulze Frielinghaus
wrote:
>
> From: Stefan Schulze Frielinghaus
>
> Targets hppa, m68k, pdp11, rx, sh, vax do not default to LRA. Since old
> reload pass is still used, add option -mlra for those targets.
>
> For hppa, register 0 cannot be used as a gener
> On Jul 28, 2025, at 12:48, Jakub Jelinek wrote:
>
> On Wed, Jul 23, 2025 at 05:59:22PM +, Qing Zhao wrote:
>> struct S {
>> int n;
>> int *p __attribute__((counted_by(n)));
>> } *f;
>> Int *g;
>> void setup (int **ptr, int count)
>> {
>> *ptr = __builtin_malloc (sizeof (int) * count);
>
Am 29.07.25 um 15:56 schrieb Stefan Schulze Frielinghaus:
From: Stefan Schulze Frielinghaus
Targets hppa, m68k, pdp11, rx, sh, vax do not default to LRA. Since old
reload pass is still used, add option -mlra for those targets.
For hppa, register 0 cannot be used as a general register. Theref
On Tue, Jul 29, 2025 at 6:31 AM Richard Sandiford
wrote:
>
> gcc.target/aarch64/saturating_arithmetic_{1,2}.c expect w0 and w1 to
> be duplicated into vectors. The tests expected the duplication of w1
> to happen first, but the other order would be fine too. A later
> simplify-rtx.cc patch happe
Hi Paul!
Am 24.07.25 um 08:07 schrieb Paul Richard Thomas:
I forgot to include subroutine tests. Please find attached the patch with
updated testcases.
Paul
On Wed, 23 Jul 2025 at 17:53, Paul Richard Thomas <
paul.richard.tho...@gmail.com> wrote:
Hi All,
The attached implements the F2018 ge
On Wed, 23 Jul 2025, 1nfocalypse wrote:
> Implements Philox Engine (P2075R6) and associated tests.
>
> Implements additional feedback from v4 from Patrick Palka.
>
> While fixing the carry bit propagation, I noted an issue for the
> limb carry reset as well, which has been fixed, plus I snagged
On Tue, 29 Jul 2025, Nathaniel Shead wrote:
> Tested on x86_64-pc-linux-gnu, OK for trunk if full bootstrap+regtest
> passes?
>
> -- >8 --
>
> For the sake of determining if there are other errors in user code to
> report early, many trait functions don't return error_mark_node if not
> called i
> Am 29.07.2025 um 16:54 schrieb Pengfei Li :
>
> Hi,
>
> I have adjusted the test case as you suggested.
>
> Ok for trunk?
Ok
Thanks,
Richard
> Thanks,
> Pengfei
>
> -- >8 --
> This fixes a miscompilation issue introduced by the enablement of
> combined loop peeling and versioning. A t
> Am 29.07.2025 um 20:37 schrieb Pengfei Li :
>
> Hi,
>
> The comment in v2 is addressed. Tested again on both trunk and gcc-15.
>
> Ok for trunk and gcc-15?
>
Ok
Richard
> Changes in v3:
> - Extract the constant VF check out.
>
> Changes in v2:
> - Remove the condition of dr_safe_spe
Hi,
Just following up on this patch.
Would appreciate any feedback or suggestions on the implementation approach.
Thanks again!
Best,
Piyush
On 17/07/25 17:43, Piyush Raj wrote:
Hi,
This patch is an attempt to integrate the bpf-vmtest-tool with DejaGnu.
Instead of modifying gcc-dg specific p
Hi,
The comment in v2 is addressed. Tested again on both trunk and gcc-15.
Ok for trunk and gcc-15?
Changes in v3:
- Extract the constant VF check out.
Changes in v2:
- Remove the condition of dr_safe_speculative_read_required.
- Add a constant VF check.
Thanks,
Pengfei
-- >8 --
This patch
> On Jul 28, 2025, at 5:54 PM, Bill Wendling wrote:
>
> On Mon, Jul 28, 2025 at 4:52 PM Yeoul Na wrote:
>>
>> Could someone working on Linux answer my earlier question? Working on a
>> compromise solution is one thing, but I’m trying to understand the situation
>> better.
>>
>>> Out of curi
The problem here is that in tree-prof.exp does not cleanup if requiring
auto-profile
but it is not supported and the testcase uses dg-additional-sources. Currently
additional_sources
is not reset to "" and then another testcase comes along and thinks that is the
additional source
to be added.
C
On Tue, Jul 29, 2025 at 1:44 AM Tamar Christina wrote:
>
> Hi Yury,
>
> > -Original Message-
> > From: Yury Khrustalev
> > Sent: Wednesday, July 23, 2025 9:45 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Andrew Pinski ; Richard Sandiford
> > ; Tamar Christina ;
> > Alfie Richards ; Alice Ca
Fixes an ICE on invalid code (15/16 regression).
Bootstrapped and regression tested on x86_64.
c: Fix ICE on invalid code involving bit fields [PR121217]
Under some error condition we can end up with NULL_TREEs for
the type of bitfields, which can cause an ICE when testing for
Hello.
> > OK.
>
> BTW: How do you plan to go forward with these patches?
>
> If you don't have compyright assignment then we need your
> Signed-off-by: on the patches, please read "Legal Prerequisites" of
> https://gcc.gnu.org/contribute.html . Also,
Like myself, Artemiy is covered by company-
On Tue, Jul 29, 2025 at 6:58 PM Uros Bizjak wrote:
>
> On Tue, Jul 29, 2025 at 5:04 PM wrote:
> >
> > On 2025-07-25 11:18, Uros Bizjak wrote:
> > > On Thu, Jul 24, 2025 at 5:35 PM Artemiy Granat
> > > wrote:
> > >>
> > >> gcc/testsuite/ChangeLog:
> > >>
> > >> * g++.dg/abi/regparm1.C: Us
On Tue, Jul 29, 2025 at 5:04 PM wrote:
>
> On 2025-07-25 11:18, Uros Bizjak wrote:
> > On Thu, Jul 24, 2025 at 5:35 PM Artemiy Granat
> > wrote:
> >>
> >> gcc/testsuite/ChangeLog:
> >>
> >> * g++.dg/abi/regparm1.C: Use regparm attribute only if not in
> >> 64-bit mode.
> >>
I ran testsuite with --enable-symvers=gnu-versioned-namespace config and
1 test is failing because there is no dual abi in this mode and it
defaults to COW string implementation.
libstdc++: Fix test when dual abi disabled
When !_GLIBCXX_USE_DUAL_ABI the old COW std::string implementati
After previous patches, we should always get a VNx16BI result
for ACLE intrinsics that return svbool_t. This patch adds
an assert that checks a more general condition than that.
gcc/
* config/aarch64/aarch64-sve-builtins.cc
(function_expander::expand): Assert that the return value
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svpnext* intrinsics.
gcc/
* config/aarch64/iterators.md (PNEXT_ONLY): New int iterator.
* config/aarch64/aarch64-sve.md
(@aarch64_sve_): Restrict SVE_PITER pattern
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svmatch* and svnmatch*
intrinsics.
gcc/
* config/aarch64/aarch64-sve2.md (@aarch64_pred_):
Split SVE2_MATCH pattern into a VNx16QI_ONLY define_ins and a
VNx8HI_ONLY
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the predicate forms of svdupq.
The general predicate expansion builds an equivalent integer vector
and then compares it with zero. This patch therefore relies on
the earlier patches to the com
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svac* intrinsics (floating-
point compare absolute).
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_pred_fac):
Replace with...
(@aarch64_pred_fac_acle): ...this new
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the floating-point forms of svcmp*.
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_pred_fcm_acle)
(*aarch64_pred_fcm_acle, @aarch64_pred_fcmuo_acle)
(*aarch64_pred_fcmuo
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the predicate forms of svdup.
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_emit_sve_pred_vec_duplicate): Declare.
* config/aarch64/aarch64.cc
(aarch64_emit_sv
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svcmp*_wide intrinsics.
Since the only uses of these patterns are for ACLE intrinsics,
there didn't seem much point adding an "_acle" suffix.
gcc/
* config/aarch64/aarch64.cc (@aar
Patterns that fuse a predicate operation P with a PTEST use
aarch64_sve_same_pred_for_ptest_p to test whether the governing
predicates of P and the PTEST are compatible. Most patterns were also
written as define_insn_and_rewrites, with the rewrite replacing P's
original governing predicate with PT
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the non-widening integer forms
of svcmp*. The handling of the PTEST patterns is similar to that
for the earlier svwhile* patch.
Unfortunately, on its own, this triggers a failure in the
pred_c
The patterns for the svcmp_wide intrinsics used a VNx16BI
input predicate for all modes, instead of the usual .
That unnecessarily made some input bits significant, but more
importantly, it triggered an ICE in aarch64_sve_same_pred_for_ptest_p
when testing whether a comparison pattern could be fuse
This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svunpk* intrinsics.
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_sve_punpk_acle)
(*aarch64_sve_punpk_acle): New patterns.
* config/aarch64/aarch64-sve-builtins-bas
There have been at least two distinct problems with using VNx8BI,
VNx4BI, and VNx2BI for predicates in which every bit is significant,
and which should therefore be represented as VNx16BI instead:
* PR121118: https://gcc.gnu.org/pipermail/gcc-patches/2025-July/691024.html
* PR121294: https://gcc.g
The previous patch for PR121294 handled svtrn1/2, svuzp1/2, and svzip1/2.
This one extends it to handle svrev intrinsics, where the same kind of
wrong code can be generated.
gcc/
PR target/121294
* config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec.
* config/aarch64/aa
The patterns for the predicate forms of svtrn1/2, svuzp1/2,
and svzip1/2 are shared with aarch64_vectorize_vec_perm_const.
The .H, .S, and .D forms operate on VNx8BI, VNx4BI, and VNx2BI
respectively. Thus, for all four element widths, there is one
significant bit per element, for both the inputs a
On Tue, Jul 29, 2025 at 11:20:25AM -0500, Robert Dubner wrote:
> I removed the pick of 0eac9cfe, and I removed the pick of ed8761241ac529,
> which had already been done by Thomas.
>
> I just applied the other 45 relevant commits, and pushed that.
Great, thanks.
git diff
r15-10108-g50c91681558e4
One long-standing problem with the implementation of the SVE ACLE
is that .H, .S, and .D predicate operations tend to have VNx8BI,
VNx4BI, and VNx2BI results. As with the fix for PR121118, this
representation is usually incorrect, since every bit of an svbool_t
result is significant:
https://
> -Original Message-
> From: Thomas Schwinge
> Sent: Tuesday, July 29, 2025 03:46
> To: Robert Dubner
> Cc: Jakub Jelinek ; Richard Biener
> ; Richard Biener ;
> jklow...@cobolworx.com; gcc-patches@gcc.gnu.org
> Subject: Re: cobol: [PATCH] Bring the COBOL front end in releases/gcc-15
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, July 29, 2025 02:55
> To: Robert Dubner
> Cc: Jakub Jelinek ; Richard Biener ;
> jklow...@cobolworx.com; Thomas Schwinge ; gcc-
> patc...@gcc.gnu.org
> Subject: Re: cobol: [PATCH] Bring the COBOL front end in releases/gcc-15
>
On Mon, Jul 28, 2025 at 11:40 PM Jakub Jelinek wrote:
>
> On Sat, Jul 26, 2025 at 10:37:35AM -0700, H.J. Lu wrote:
> > __tls_get_addr doesn't preserve vector registers. When a function
> > with no_caller_saved_registers attribute calls __tls_get_addr, YMM
> > and ZMM registers will be clobbered.
On Tue, 29 Jul 2025, Jakub Jelinek wrote:
> On Tue, Jul 29, 2025 at 11:02:08AM -0400, Hans-Peter Nilsson wrote:
> > > If you have a target with bogus MAX_FIXED_MODE_SIZE definition, you should
> > > just fix that.
> >
> > That macro should be avoided, for one because it's misleading
> > and ends
> Am 29.07.2025 um 16:58 schrieb Pengfei Li :
>
> Hi,
>
> I have updated the fix and the test case as you suggested.
>
> Patch is re-tested on trunk and gcc-15. Ok for both trunk and gcc-15?
Ok, but can you put the VF check somewhere more global? It seems we never want
to do alignment ver
Hi Hans.
Thank you for the heads up.
I think it is ok to use the new default in BPF. It is extremely
unlikely it will ever impact existing current BPF programs, and when/if
it comes to that, it will help to use the best default so we can at that
point formalize the ABI.
> From: Hans-Peter Nil
> On Jul 29, 2025, at 11:52, Martin Uecker wrote:
>
> Am Dienstag, dem 29.07.2025 um 13:49 + schrieb Qing Zhao:
>>
>>> On Jul 28, 2025, at 17:39, Martin Uecker wrote:
>>>
>>> Am Montag, dem 28.07.2025 um 20:48 + schrieb Qing Zhao:
> On Jul 28, 2025, at 16:09, Martin Uecker
Am Dienstag, dem 29.07.2025 um 13:49 + schrieb Qing Zhao:
>
> > On Jul 28, 2025, at 17:39, Martin Uecker wrote:
> >
> > Am Montag, dem 28.07.2025 um 20:48 + schrieb Qing Zhao:
> > >
> > > > On Jul 28, 2025, at 16:09, Martin Uecker wrote:
> > > >
> > > > >
...
> > > > > Ex 6)
> > >
GCC doesn't support SME without SVE2, so the -march=armv8-a+ argument to
check_no_compiler_messages causes aarch64_asm__ok to return zero for SME
and any that implies it. This patch changes the baseline architecure to
armv9-a for these extensions.
The tests for ACLE SME2 intrinsics that require
On 7/29/25 4:34 PM, Juergen Christ wrote:
Loop peeling and minimal loop vectorization threshold prevented loop
vectorization in these examples. Adjust parameters in the test to
make the test pass.
Tested on s390x. Okay for main and gcc15?
Signed-off-by: Juergen Christ
PR testsuite/1
PR121118 is about a case where we try to construct a predicate
constant using a permutation of a PFALSE and a WHILELO. The WHILELO
is a .H operation and its result has mode VNx8BI. However, the
permute instruction expects both inputs to be VNx16BI, leading to
an unrecognisable insn ICE.
VNx8BI i
Spencer Abson writes:
> This patch extends the expander for conditional smax, smin, add, sub, mul,
> min, max, and div to support partial SVE FP modes.
>
> If exceptions from undefined vector elements must be suppressed, this
> expansion converts the container-level predicate to an element-level o
On 29/07/2025 11:39, Richard Biener wrote:
On Tue, 29 Jul 2025, Alfie Richards wrote:
On 29/07/2025 10:13, Richard Biener wrote:
On Tue, 29 Jul 2025, Alfie Richards wrote:
(Whoops, s/WIP/RFC)
Hi All,
This patch adds support for capping VF at runtime for VLA loops with a
data dependency.
On
This patch adds dispatch constraints for Neoverse V2 and illustrates the steps
necessary to enable dispatch scheduling for an AArch64 core.
The dispatch constraints are based on section 4.1 of the Neoverse V2 SWOG.
Please note that the values used here deviate slightly from the current SWOG
versio
On Tue, Jul 29, 2025 at 11:02:08AM -0400, Hans-Peter Nilsson wrote:
> > If you have a target with bogus MAX_FIXED_MODE_SIZE definition, you should
> > just fix that.
>
> That macro should be avoided, for one because it's misleading
> and ends up being used for other than target tweaking (QED).
N
This patch adds dispatch scheduling for AArch64 by implementing the two target
hooks TARGET_SCHED_DISPATCH and TARGET_SCHED_DISPATCH_DO.
The motivation for this is that cores with out-of-order processing do
most of the reordering to avoid pipeline hazards on the hardware side
using large reorder b
On 2025-07-25 11:18, Uros Bizjak wrote:
On Thu, Jul 24, 2025 at 5:35 PM Artemiy Granat
wrote:
gcc/testsuite/ChangeLog:
* g++.dg/abi/regparm1.C: Use regparm attribute only if not in
64-bit mode.
* gcc.target/i386/20020224-1.c: Likewise.
* gcc.target/i386/pr10378
On Mon, 28 Jul 2025, Jakub Jelinek wrote:
> On Sun, Jul 27, 2025 at 09:27:30PM -0400, Pietro Monteiro wrote:
> > On Mon, Jul 14, 2025, at 10:43 PM, Hans-Peter Nilsson wrote:
> > > Tested to fix build for MMIX (and to fix a few type-generic-builtin
> > > test-cases; c-c++-common/pr111309-1.c, gcc.d
I thought I already merged that until today's RISC-V patchwork
meeting, committed to trunk :P
On Wed, Jun 25, 2025 at 9:21 PM Dongyan Chen
wrote:
>
> Automatically generate -mcpu and -mtune options in invoke.texi from
> the unified riscv-cores.def metadata, ensuring documentation stays in sync
>
Hi,
I have updated the fix and the test case as you suggested.
Patch is re-tested on trunk and gcc-15. Ok for both trunk and gcc-15?
Thanks,
Pengfei
-- >8 --
This patch fixes a segmentation fault issue that can occur in vectorized
loops with an early break. When GCC vectorizes such loops, it ma
This patch removes unused local variables from three procedures.
gcc/m2/ChangeLog:
* gm2-compiler/M2GenGCC.mod (FoldBecomes): Remove all
local variables.
(CodeIndrX): Remove length.
Remove newstr.
* gm2-compiler/M2Range.mod (FoldTypeIndrX): Remove desType.
Hi,
I have adjusted the test case as you suggested.
Ok for trunk?
Thanks,
Pengfei
-- >8 --
This fixes a miscompilation issue introduced by the enablement of
combined loop peeling and versioning. A test case that reproduces the
issue is included in the patch.
When performing loop peeling, GCC u
Hi Gerald,
Gerald Pfeifer wrote:
+ OpenACC 3.4: In Fortran, named constants (PARAMETER) used as
+ var in clauses are now accepted (and ignored as not being
+ required). The support for named constants has been added to the
+ specification and GCC for better compatibility with exi
From: Hans-Peter Nilsson
The change of default value for MAX_FIXED_MODE_SIZE was
approved contingent on not changing it for BPF, since it
could not be trivially ruled out to change the ABI for a
target. See thread at
"https://gcc.gnu.org/pipermail/gcc-patches/2025-July/690288.html";.
Since this
Hi All,
Quick fixup for the gating (s/&&/|/) for an error I made.
Only needed for trunk as the intrinsics were only added recently.
Bootstrapped and reg tested on Aatch64.
Thanks,
Alfie
-- >8 --
Fixes the feature gating for the SME2+FAMINMAX intrinsics.
PR target/121300
gcc/ChangeLo
Loop peeling and minimal loop vectorization threshold prevented loop
vectorization in these examples. Adjust parameters in the test to
make the test pass.
Tested on s390x. Okay for main and gcc15?
Signed-off-by: Juergen Christ
PR testsuite/121286
PR testsuite/121288
gcc/tests
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